Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T539 /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1080611124 Jul 15 05:52:37 PM PDT 24 Jul 15 05:52:39 PM PDT 24 131231071 ps
T540 /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2835889966 Jul 15 05:51:29 PM PDT 24 Jul 15 05:51:31 PM PDT 24 131398876 ps
T541 /workspace/coverage/default/41.rstmgr_reset.1676672861 Jul 15 05:52:51 PM PDT 24 Jul 15 05:52:59 PM PDT 24 1643215665 ps
T542 /workspace/coverage/default/26.rstmgr_sw_rst.3976816440 Jul 15 05:52:30 PM PDT 24 Jul 15 05:52:33 PM PDT 24 136776952 ps
T543 /workspace/coverage/default/20.rstmgr_por_stretcher.66010642 Jul 15 05:52:10 PM PDT 24 Jul 15 05:52:11 PM PDT 24 135235171 ps
T60 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3431632448 Jul 15 05:51:11 PM PDT 24 Jul 15 05:51:14 PM PDT 24 124911945 ps
T56 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.754661307 Jul 15 05:50:58 PM PDT 24 Jul 15 05:51:00 PM PDT 24 130775093 ps
T57 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3023009277 Jul 15 05:50:50 PM PDT 24 Jul 15 05:50:51 PM PDT 24 86791288 ps
T58 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2259572526 Jul 15 05:51:03 PM PDT 24 Jul 15 05:51:05 PM PDT 24 94540285 ps
T59 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2671103246 Jul 15 05:51:00 PM PDT 24 Jul 15 05:51:03 PM PDT 24 162158647 ps
T61 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3527931910 Jul 15 05:50:48 PM PDT 24 Jul 15 05:50:52 PM PDT 24 288372742 ps
T62 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.136238700 Jul 15 05:51:10 PM PDT 24 Jul 15 05:51:12 PM PDT 24 118989531 ps
T63 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.816832408 Jul 15 05:51:04 PM PDT 24 Jul 15 05:51:08 PM PDT 24 824821932 ps
T101 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3407879168 Jul 15 05:51:26 PM PDT 24 Jul 15 05:51:28 PM PDT 24 65979888 ps
T68 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3918802552 Jul 15 05:51:11 PM PDT 24 Jul 15 05:51:13 PM PDT 24 112322642 ps
T102 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.932712059 Jul 15 05:51:11 PM PDT 24 Jul 15 05:51:14 PM PDT 24 222279178 ps
T103 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1105150329 Jul 15 05:50:58 PM PDT 24 Jul 15 05:51:00 PM PDT 24 144950665 ps
T139 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1044583220 Jul 15 05:50:56 PM PDT 24 Jul 15 05:50:59 PM PDT 24 147022777 ps
T64 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.123425555 Jul 15 05:51:21 PM PDT 24 Jul 15 05:51:25 PM PDT 24 407206026 ps
T71 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1346994444 Jul 15 05:50:58 PM PDT 24 Jul 15 05:51:01 PM PDT 24 414580936 ps
T73 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2933852776 Jul 15 05:50:48 PM PDT 24 Jul 15 05:50:52 PM PDT 24 342583187 ps
T72 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1225951887 Jul 15 05:50:56 PM PDT 24 Jul 15 05:50:58 PM PDT 24 420960321 ps
T104 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.427433264 Jul 15 05:51:01 PM PDT 24 Jul 15 05:51:03 PM PDT 24 141739839 ps
T87 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.799464504 Jul 15 05:51:03 PM PDT 24 Jul 15 05:51:05 PM PDT 24 183987583 ps
T105 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.104633673 Jul 15 05:51:12 PM PDT 24 Jul 15 05:51:15 PM PDT 24 201073960 ps
T544 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1616884491 Jul 15 05:51:21 PM PDT 24 Jul 15 05:51:24 PM PDT 24 66317248 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.92397632 Jul 15 05:50:59 PM PDT 24 Jul 15 05:51:04 PM PDT 24 790863338 ps
T106 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2236984852 Jul 15 05:50:58 PM PDT 24 Jul 15 05:50:59 PM PDT 24 76818651 ps
T88 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.418300905 Jul 15 05:51:00 PM PDT 24 Jul 15 05:51:03 PM PDT 24 179363641 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2064791179 Jul 15 05:50:59 PM PDT 24 Jul 15 05:51:01 PM PDT 24 145118828 ps
T107 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2379565059 Jul 15 05:51:04 PM PDT 24 Jul 15 05:51:06 PM PDT 24 67027167 ps
T75 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1696061260 Jul 15 05:51:12 PM PDT 24 Jul 15 05:51:16 PM PDT 24 183414588 ps
T74 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.365905527 Jul 15 05:50:56 PM PDT 24 Jul 15 05:51:01 PM PDT 24 483608553 ps
T108 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3314736394 Jul 15 05:51:20 PM PDT 24 Jul 15 05:51:22 PM PDT 24 228495718 ps
T80 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4198905925 Jul 15 05:51:20 PM PDT 24 Jul 15 05:51:23 PM PDT 24 207533465 ps
T109 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1464092919 Jul 15 05:50:56 PM PDT 24 Jul 15 05:50:58 PM PDT 24 115666078 ps
T134 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.64655793 Jul 15 05:51:22 PM PDT 24 Jul 15 05:51:25 PM PDT 24 422793125 ps
T136 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.354556639 Jul 15 05:51:11 PM PDT 24 Jul 15 05:51:14 PM PDT 24 481441867 ps
T547 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2571480144 Jul 15 05:51:21 PM PDT 24 Jul 15 05:51:23 PM PDT 24 165232971 ps
T548 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3162700568 Jul 15 05:51:20 PM PDT 24 Jul 15 05:51:21 PM PDT 24 61741809 ps
T549 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.245791994 Jul 15 05:51:01 PM PDT 24 Jul 15 05:51:05 PM PDT 24 583660254 ps
T137 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.564374638 Jul 15 05:51:24 PM PDT 24 Jul 15 05:51:27 PM PDT 24 410789756 ps
T550 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.874552827 Jul 15 05:51:13 PM PDT 24 Jul 15 05:51:15 PM PDT 24 77991066 ps
T78 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.410927031 Jul 15 05:51:12 PM PDT 24 Jul 15 05:51:17 PM PDT 24 1527830231 ps
T551 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1434390959 Jul 15 05:51:03 PM PDT 24 Jul 15 05:51:06 PM PDT 24 122816004 ps
T552 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1923203475 Jul 15 05:51:03 PM PDT 24 Jul 15 05:51:06 PM PDT 24 161483519 ps
T553 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3154714577 Jul 15 05:51:22 PM PDT 24 Jul 15 05:51:25 PM PDT 24 257315254 ps
T554 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3571817317 Jul 15 05:50:57 PM PDT 24 Jul 15 05:51:01 PM PDT 24 382666911 ps
T555 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.948471381 Jul 15 05:51:21 PM PDT 24 Jul 15 05:51:24 PM PDT 24 473942585 ps
T556 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1670728883 Jul 15 05:51:03 PM PDT 24 Jul 15 05:51:05 PM PDT 24 78402821 ps
T557 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2932380014 Jul 15 05:50:56 PM PDT 24 Jul 15 05:51:02 PM PDT 24 477985528 ps
T558 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3215111013 Jul 15 05:50:51 PM PDT 24 Jul 15 05:50:57 PM PDT 24 1023407828 ps
T559 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3204783357 Jul 15 05:51:11 PM PDT 24 Jul 15 05:51:13 PM PDT 24 110863226 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3630271635 Jul 15 05:50:55 PM PDT 24 Jul 15 05:50:57 PM PDT 24 92790877 ps
T561 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3448730754 Jul 15 05:51:13 PM PDT 24 Jul 15 05:51:17 PM PDT 24 883320880 ps
T562 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2962435998 Jul 15 05:51:21 PM PDT 24 Jul 15 05:51:24 PM PDT 24 123161890 ps
T563 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.925803973 Jul 15 05:51:06 PM PDT 24 Jul 15 05:51:10 PM PDT 24 806570064 ps
T564 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3735304302 Jul 15 05:50:51 PM PDT 24 Jul 15 05:50:53 PM PDT 24 184324003 ps
T565 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2077939694 Jul 15 05:51:05 PM PDT 24 Jul 15 05:51:07 PM PDT 24 115658747 ps
T79 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.54900994 Jul 15 05:51:20 PM PDT 24 Jul 15 05:51:24 PM PDT 24 927120201 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2439972847 Jul 15 05:50:56 PM PDT 24 Jul 15 05:50:59 PM PDT 24 179484992 ps
T567 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3411672045 Jul 15 05:51:05 PM PDT 24 Jul 15 05:51:08 PM PDT 24 202656658 ps
T568 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1393945634 Jul 15 05:51:00 PM PDT 24 Jul 15 05:51:01 PM PDT 24 64658926 ps
T569 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3076557393 Jul 15 05:51:10 PM PDT 24 Jul 15 05:51:11 PM PDT 24 80449041 ps
T570 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2753357964 Jul 15 05:51:04 PM PDT 24 Jul 15 05:51:07 PM PDT 24 156197801 ps
T94 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2149189891 Jul 15 05:51:13 PM PDT 24 Jul 15 05:51:15 PM PDT 24 91233381 ps
T571 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1217494564 Jul 15 05:51:12 PM PDT 24 Jul 15 05:51:14 PM PDT 24 130902360 ps
T572 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4222563867 Jul 15 05:51:06 PM PDT 24 Jul 15 05:51:08 PM PDT 24 138648176 ps
T135 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3423933939 Jul 15 05:50:56 PM PDT 24 Jul 15 05:51:00 PM PDT 24 778032020 ps
T573 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3646091479 Jul 15 05:51:21 PM PDT 24 Jul 15 05:51:24 PM PDT 24 185455107 ps
T574 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3520735137 Jul 15 05:51:09 PM PDT 24 Jul 15 05:51:11 PM PDT 24 90775185 ps
T138 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3787654169 Jul 15 05:51:10 PM PDT 24 Jul 15 05:51:14 PM PDT 24 888653608 ps
T575 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4001830557 Jul 15 05:50:59 PM PDT 24 Jul 15 05:51:01 PM PDT 24 56824249 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1294594357 Jul 15 05:50:56 PM PDT 24 Jul 15 05:50:59 PM PDT 24 507331974 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.621235239 Jul 15 05:50:58 PM PDT 24 Jul 15 05:50:59 PM PDT 24 73396956 ps
T578 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1769392554 Jul 15 05:51:04 PM PDT 24 Jul 15 05:51:09 PM PDT 24 653443611 ps
T579 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3845054924 Jul 15 05:50:51 PM PDT 24 Jul 15 05:50:54 PM PDT 24 197067125 ps
T580 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2553504151 Jul 15 05:51:20 PM PDT 24 Jul 15 05:51:22 PM PDT 24 129816436 ps
T581 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1368715905 Jul 15 05:51:14 PM PDT 24 Jul 15 05:51:19 PM PDT 24 534792706 ps
T582 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2834246164 Jul 15 05:51:05 PM PDT 24 Jul 15 05:51:08 PM PDT 24 301873000 ps
T583 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.224660189 Jul 15 05:51:21 PM PDT 24 Jul 15 05:51:23 PM PDT 24 241122841 ps
T584 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1161840143 Jul 15 05:51:19 PM PDT 24 Jul 15 05:51:22 PM PDT 24 461373156 ps
T76 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.707959364 Jul 15 05:51:06 PM PDT 24 Jul 15 05:51:11 PM PDT 24 920250898 ps
T585 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2624156459 Jul 15 05:51:22 PM PDT 24 Jul 15 05:51:24 PM PDT 24 91739626 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.684138249 Jul 15 05:50:51 PM PDT 24 Jul 15 05:50:53 PM PDT 24 100484638 ps
T587 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1762751252 Jul 15 05:50:56 PM PDT 24 Jul 15 05:50:58 PM PDT 24 129664362 ps
T588 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1869093411 Jul 15 05:50:51 PM PDT 24 Jul 15 05:50:53 PM PDT 24 166496797 ps
T589 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3213524736 Jul 15 05:51:12 PM PDT 24 Jul 15 05:51:17 PM PDT 24 473870844 ps
T590 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3459581125 Jul 15 05:51:14 PM PDT 24 Jul 15 05:51:16 PM PDT 24 62957670 ps
T591 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.592559332 Jul 15 05:51:14 PM PDT 24 Jul 15 05:51:16 PM PDT 24 86370198 ps
T592 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.583507265 Jul 15 05:51:10 PM PDT 24 Jul 15 05:51:12 PM PDT 24 81830001 ps
T593 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3033981980 Jul 15 05:51:20 PM PDT 24 Jul 15 05:51:22 PM PDT 24 166287131 ps
T77 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2274243892 Jul 15 05:51:13 PM PDT 24 Jul 15 05:51:17 PM PDT 24 775497071 ps
T594 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.448914361 Jul 15 05:51:05 PM PDT 24 Jul 15 05:51:08 PM PDT 24 184705297 ps
T595 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1871710957 Jul 15 05:51:19 PM PDT 24 Jul 15 05:51:21 PM PDT 24 119194879 ps
T596 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.216700720 Jul 15 05:51:22 PM PDT 24 Jul 15 05:51:24 PM PDT 24 74332983 ps
T597 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1505466203 Jul 15 05:51:03 PM PDT 24 Jul 15 05:51:05 PM PDT 24 141499692 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2107233705 Jul 15 05:50:48 PM PDT 24 Jul 15 05:50:53 PM PDT 24 882616083 ps
T599 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2271562717 Jul 15 05:51:01 PM PDT 24 Jul 15 05:51:03 PM PDT 24 126317311 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.733244771 Jul 15 05:50:59 PM PDT 24 Jul 15 05:51:02 PM PDT 24 437029887 ps
T601 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2520983991 Jul 15 05:51:11 PM PDT 24 Jul 15 05:51:16 PM PDT 24 965124362 ps
T602 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.417768035 Jul 15 05:51:04 PM PDT 24 Jul 15 05:51:06 PM PDT 24 71038740 ps
T603 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3094355545 Jul 15 05:51:23 PM PDT 24 Jul 15 05:51:24 PM PDT 24 69939478 ps
T604 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.588358672 Jul 15 05:51:11 PM PDT 24 Jul 15 05:51:13 PM PDT 24 181692460 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1905012304 Jul 15 05:50:57 PM PDT 24 Jul 15 05:51:01 PM PDT 24 272609408 ps
T606 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.137332186 Jul 15 05:50:55 PM PDT 24 Jul 15 05:51:01 PM PDT 24 481750583 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3911223302 Jul 15 05:51:03 PM PDT 24 Jul 15 05:51:05 PM PDT 24 137825457 ps
T608 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.34878201 Jul 15 05:51:01 PM PDT 24 Jul 15 05:51:03 PM PDT 24 85355206 ps
T609 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.908229705 Jul 15 05:51:12 PM PDT 24 Jul 15 05:51:15 PM PDT 24 215405975 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1411445046 Jul 15 05:50:57 PM PDT 24 Jul 15 05:50:59 PM PDT 24 193152958 ps
T611 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3501796069 Jul 15 05:50:59 PM PDT 24 Jul 15 05:51:01 PM PDT 24 96198690 ps
T612 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1450712240 Jul 15 05:50:56 PM PDT 24 Jul 15 05:50:58 PM PDT 24 99618917 ps
T613 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3803109984 Jul 15 05:51:09 PM PDT 24 Jul 15 05:51:11 PM PDT 24 60817504 ps
T614 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.346470525 Jul 15 05:51:19 PM PDT 24 Jul 15 05:51:21 PM PDT 24 181864143 ps
T615 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2229666817 Jul 15 05:51:12 PM PDT 24 Jul 15 05:51:14 PM PDT 24 175703308 ps
T616 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1016479858 Jul 15 05:50:58 PM PDT 24 Jul 15 05:51:00 PM PDT 24 496361203 ps
T617 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4280418883 Jul 15 05:51:11 PM PDT 24 Jul 15 05:51:13 PM PDT 24 63871862 ps
T618 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.959411278 Jul 15 05:51:21 PM PDT 24 Jul 15 05:51:23 PM PDT 24 120500035 ps
T619 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4095183100 Jul 15 05:51:00 PM PDT 24 Jul 15 05:51:03 PM PDT 24 205528775 ps
T620 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.170014532 Jul 15 05:51:21 PM PDT 24 Jul 15 05:51:24 PM PDT 24 169783684 ps

Test location /workspace/coverage/default/26.rstmgr_stress_all.1408887445
Short name T2
Test name
Test status
Simulation time 5015560981 ps
CPU time 19.06 seconds
Started Jul 15 05:52:30 PM PDT 24
Finished Jul 15 05:52:49 PM PDT 24
Peak memory 200360 kb
Host smart-fac5a82a-e393-4c2a-8326-f81ad9e1395f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408887445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1408887445
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2969129951
Short name T3
Test name
Test status
Simulation time 507241629 ps
CPU time 2.79 seconds
Started Jul 15 05:51:33 PM PDT 24
Finished Jul 15 05:51:36 PM PDT 24
Peak memory 200024 kb
Host smart-34a3e9b7-5b7a-4f4d-8fb6-7666cb56378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969129951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2969129951
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2743942879
Short name T4
Test name
Test status
Simulation time 1228674865 ps
CPU time 5.55 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 217688 kb
Host smart-bb0ba65b-a3d8-4ec1-bb85-9d46b825d6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743942879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2743942879
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.816832408
Short name T63
Test name
Test status
Simulation time 824821932 ps
CPU time 2.87 seconds
Started Jul 15 05:51:04 PM PDT 24
Finished Jul 15 05:51:08 PM PDT 24
Peak memory 200416 kb
Host smart-8f524b7d-3f8a-4a10-be90-feae92598117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816832408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
816832408
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3429840139
Short name T53
Test name
Test status
Simulation time 17563591476 ps
CPU time 26.37 seconds
Started Jul 15 05:51:43 PM PDT 24
Finished Jul 15 05:52:11 PM PDT 24
Peak memory 218128 kb
Host smart-893e1b85-e4ab-476b-a35a-38f31d2e8a21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429840139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3429840139
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.123425555
Short name T64
Test name
Test status
Simulation time 407206026 ps
CPU time 3.17 seconds
Started Jul 15 05:51:21 PM PDT 24
Finished Jul 15 05:51:25 PM PDT 24
Peak memory 216676 kb
Host smart-3b3dd0b3-e728-4363-ab4c-b03214b30cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123425555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.123425555
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1887529277
Short name T84
Test name
Test status
Simulation time 6260915929 ps
CPU time 21.62 seconds
Started Jul 15 05:53:05 PM PDT 24
Finished Jul 15 05:53:28 PM PDT 24
Peak memory 208620 kb
Host smart-23f9070c-c4d6-49ce-b9d4-627b5a45b8b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887529277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1887529277
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3550922703
Short name T141
Test name
Test status
Simulation time 58773214 ps
CPU time 0.73 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 199916 kb
Host smart-19f2324a-f0f8-42f0-b4b5-577aaf99f3de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550922703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3550922703
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1237276580
Short name T11
Test name
Test status
Simulation time 168776610 ps
CPU time 1.16 seconds
Started Jul 15 05:51:42 PM PDT 24
Finished Jul 15 05:51:44 PM PDT 24
Peak memory 200068 kb
Host smart-5495dc45-e37c-4f65-ab32-640a452bc9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237276580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1237276580
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.90487407
Short name T45
Test name
Test status
Simulation time 159787894 ps
CPU time 1.33 seconds
Started Jul 15 05:51:27 PM PDT 24
Finished Jul 15 05:51:29 PM PDT 24
Peak memory 200248 kb
Host smart-1e53c279-3cab-4024-89be-ec4cf25e00c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90487407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.90487407
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2074917284
Short name T35
Test name
Test status
Simulation time 1886466606 ps
CPU time 8.42 seconds
Started Jul 15 05:52:34 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 221660 kb
Host smart-982421cb-dafc-475e-aa10-458226539820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074917284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2074917284
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.410927031
Short name T78
Test name
Test status
Simulation time 1527830231 ps
CPU time 4.25 seconds
Started Jul 15 05:51:12 PM PDT 24
Finished Jul 15 05:51:17 PM PDT 24
Peak memory 200520 kb
Host smart-75cf82cf-5981-4b78-bdcf-5715ab933b13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410927031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.410927031
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.707959364
Short name T76
Test name
Test status
Simulation time 920250898 ps
CPU time 3.65 seconds
Started Jul 15 05:51:06 PM PDT 24
Finished Jul 15 05:51:11 PM PDT 24
Peak memory 200396 kb
Host smart-80c88709-b364-48f7-8e86-ca1c6e1b5a93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707959364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
707959364
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3126815917
Short name T13
Test name
Test status
Simulation time 2385333773 ps
CPU time 8.53 seconds
Started Jul 15 05:51:56 PM PDT 24
Finished Jul 15 05:52:05 PM PDT 24
Peak memory 217836 kb
Host smart-49489db3-6a71-4e57-80e3-5acb507ca190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126815917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3126815917
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3023009277
Short name T57
Test name
Test status
Simulation time 86791288 ps
CPU time 0.88 seconds
Started Jul 15 05:50:50 PM PDT 24
Finished Jul 15 05:50:51 PM PDT 24
Peak memory 200248 kb
Host smart-0ce9f564-5d7f-4d5f-8e9d-a32e1cf11403
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023009277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3023009277
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1061745829
Short name T19
Test name
Test status
Simulation time 133282778 ps
CPU time 0.86 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:31 PM PDT 24
Peak memory 199888 kb
Host smart-d105843c-2344-46eb-80a9-c4c094d9edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061745829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1061745829
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2876956922
Short name T30
Test name
Test status
Simulation time 244157224 ps
CPU time 1.17 seconds
Started Jul 15 05:51:55 PM PDT 24
Finished Jul 15 05:51:57 PM PDT 24
Peak memory 217372 kb
Host smart-0f61325a-647a-4f98-a8e7-59f968486438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876956922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2876956922
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2933852776
Short name T73
Test name
Test status
Simulation time 342583187 ps
CPU time 2.5 seconds
Started Jul 15 05:50:48 PM PDT 24
Finished Jul 15 05:50:52 PM PDT 24
Peak memory 208560 kb
Host smart-776477a6-ee53-4399-a2dd-08f4a28d382c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933852776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2933852776
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2274243892
Short name T77
Test name
Test status
Simulation time 775497071 ps
CPU time 3.08 seconds
Started Jul 15 05:51:13 PM PDT 24
Finished Jul 15 05:51:17 PM PDT 24
Peak memory 200400 kb
Host smart-8fc38fa2-14cd-4cf0-baa5-8fd4b35cb434
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274243892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2274243892
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1151834130
Short name T217
Test name
Test status
Simulation time 4961614773 ps
CPU time 22.08 seconds
Started Jul 15 05:51:57 PM PDT 24
Finished Jul 15 05:52:20 PM PDT 24
Peak memory 200472 kb
Host smart-8581ae72-5770-4816-a468-50cefc91f7fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151834130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1151834130
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1869093411
Short name T588
Test name
Test status
Simulation time 166496797 ps
CPU time 1.87 seconds
Started Jul 15 05:50:51 PM PDT 24
Finished Jul 15 05:50:53 PM PDT 24
Peak memory 200424 kb
Host smart-9c8c823d-1538-4d69-acae-b93f45210777
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869093411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
869093411
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3215111013
Short name T558
Test name
Test status
Simulation time 1023407828 ps
CPU time 5.46 seconds
Started Jul 15 05:50:51 PM PDT 24
Finished Jul 15 05:50:57 PM PDT 24
Peak memory 200476 kb
Host smart-d76cc96c-0145-4d50-9f00-7a6638c55508
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215111013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
215111013
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.684138249
Short name T586
Test name
Test status
Simulation time 100484638 ps
CPU time 0.87 seconds
Started Jul 15 05:50:51 PM PDT 24
Finished Jul 15 05:50:53 PM PDT 24
Peak memory 200116 kb
Host smart-f14f416a-ffad-4726-bcc8-db95bc05b686
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684138249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.684138249
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3735304302
Short name T564
Test name
Test status
Simulation time 184324003 ps
CPU time 1.26 seconds
Started Jul 15 05:50:51 PM PDT 24
Finished Jul 15 05:50:53 PM PDT 24
Peak memory 208576 kb
Host smart-48e9ce23-3999-4564-ab71-8125fa5ea4a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735304302 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3735304302
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3845054924
Short name T579
Test name
Test status
Simulation time 197067125 ps
CPU time 1.5 seconds
Started Jul 15 05:50:51 PM PDT 24
Finished Jul 15 05:50:54 PM PDT 24
Peak memory 200360 kb
Host smart-cc2f0cf0-9ee4-48bb-ae4e-7f9e15e83c1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845054924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3845054924
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3527931910
Short name T61
Test name
Test status
Simulation time 288372742 ps
CPU time 2.02 seconds
Started Jul 15 05:50:48 PM PDT 24
Finished Jul 15 05:50:52 PM PDT 24
Peak memory 208512 kb
Host smart-6d2e1c20-e6f7-4b4f-a27b-b6c2bb5a6b72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527931910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3527931910
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2107233705
Short name T598
Test name
Test status
Simulation time 882616083 ps
CPU time 3.29 seconds
Started Jul 15 05:50:48 PM PDT 24
Finished Jul 15 05:50:53 PM PDT 24
Peak memory 200508 kb
Host smart-54440ed0-9d31-4ef9-8aa4-227e9eaf7c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107233705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2107233705
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.733244771
Short name T600
Test name
Test status
Simulation time 437029887 ps
CPU time 2.65 seconds
Started Jul 15 05:50:59 PM PDT 24
Finished Jul 15 05:51:02 PM PDT 24
Peak memory 208548 kb
Host smart-4f0543d5-d0b6-4a31-b751-faf5034952f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733244771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.733244771
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1905012304
Short name T605
Test name
Test status
Simulation time 272609408 ps
CPU time 3.26 seconds
Started Jul 15 05:50:57 PM PDT 24
Finished Jul 15 05:51:01 PM PDT 24
Peak memory 200396 kb
Host smart-34ab98e3-f5cc-467f-8426-9a149cadb4d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905012304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
905012304
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3630271635
Short name T560
Test name
Test status
Simulation time 92790877 ps
CPU time 0.82 seconds
Started Jul 15 05:50:55 PM PDT 24
Finished Jul 15 05:50:57 PM PDT 24
Peak memory 200200 kb
Host smart-08fae588-4937-44bd-b2db-2acb49cbb5c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630271635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
630271635
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2064791179
Short name T546
Test name
Test status
Simulation time 145118828 ps
CPU time 1.29 seconds
Started Jul 15 05:50:59 PM PDT 24
Finished Jul 15 05:51:01 PM PDT 24
Peak memory 208568 kb
Host smart-49b1aa90-22e9-430c-826c-08958cc053aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064791179 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2064791179
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3501796069
Short name T611
Test name
Test status
Simulation time 96198690 ps
CPU time 0.89 seconds
Started Jul 15 05:50:59 PM PDT 24
Finished Jul 15 05:51:01 PM PDT 24
Peak memory 200248 kb
Host smart-07c4465d-e36b-4965-ae2c-d361b1765c13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501796069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3501796069
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2236984852
Short name T106
Test name
Test status
Simulation time 76818651 ps
CPU time 0.95 seconds
Started Jul 15 05:50:58 PM PDT 24
Finished Jul 15 05:50:59 PM PDT 24
Peak memory 200280 kb
Host smart-b5c18ad1-db6c-4636-9473-794f8009d6e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236984852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2236984852
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1294594357
Short name T576
Test name
Test status
Simulation time 507331974 ps
CPU time 1.88 seconds
Started Jul 15 05:50:56 PM PDT 24
Finished Jul 15 05:50:59 PM PDT 24
Peak memory 200424 kb
Host smart-ed406de1-f25c-4c98-980a-7b29d3a939ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294594357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1294594357
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.448914361
Short name T594
Test name
Test status
Simulation time 184705297 ps
CPU time 1.28 seconds
Started Jul 15 05:51:05 PM PDT 24
Finished Jul 15 05:51:08 PM PDT 24
Peak memory 208552 kb
Host smart-07552fb0-66f3-4ef4-97aa-bbff096fe785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448914361 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.448914361
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4280418883
Short name T617
Test name
Test status
Simulation time 63871862 ps
CPU time 0.85 seconds
Started Jul 15 05:51:11 PM PDT 24
Finished Jul 15 05:51:13 PM PDT 24
Peak memory 200204 kb
Host smart-e673945b-1ff1-4802-be5a-4235c819aea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280418883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4280418883
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3076557393
Short name T569
Test name
Test status
Simulation time 80449041 ps
CPU time 1.03 seconds
Started Jul 15 05:51:10 PM PDT 24
Finished Jul 15 05:51:11 PM PDT 24
Peak memory 200272 kb
Host smart-7141b35e-82fb-491d-a1cb-dda1a3c51e5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076557393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3076557393
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2834246164
Short name T582
Test name
Test status
Simulation time 301873000 ps
CPU time 2.33 seconds
Started Jul 15 05:51:05 PM PDT 24
Finished Jul 15 05:51:08 PM PDT 24
Peak memory 208580 kb
Host smart-b948f58d-9984-44ce-a1f4-3dbd7581b6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834246164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2834246164
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2520983991
Short name T601
Test name
Test status
Simulation time 965124362 ps
CPU time 3.07 seconds
Started Jul 15 05:51:11 PM PDT 24
Finished Jul 15 05:51:16 PM PDT 24
Peak memory 200460 kb
Host smart-cdfc2676-fcf3-400e-a903-72c433d90e41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520983991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2520983991
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2229666817
Short name T615
Test name
Test status
Simulation time 175703308 ps
CPU time 1.56 seconds
Started Jul 15 05:51:12 PM PDT 24
Finished Jul 15 05:51:14 PM PDT 24
Peak memory 208640 kb
Host smart-9aaf52eb-1eca-4e98-b8ad-b4bdc5c276d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229666817 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2229666817
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2149189891
Short name T94
Test name
Test status
Simulation time 91233381 ps
CPU time 0.93 seconds
Started Jul 15 05:51:13 PM PDT 24
Finished Jul 15 05:51:15 PM PDT 24
Peak memory 200224 kb
Host smart-0c86d312-ef9c-43d1-bfd8-ca9d1d8b2299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149189891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2149189891
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.908229705
Short name T609
Test name
Test status
Simulation time 215405975 ps
CPU time 1.52 seconds
Started Jul 15 05:51:12 PM PDT 24
Finished Jul 15 05:51:15 PM PDT 24
Peak memory 200300 kb
Host smart-8866cefb-4ba6-448e-8325-c04713b10d0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908229705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.908229705
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3411672045
Short name T567
Test name
Test status
Simulation time 202656658 ps
CPU time 1.78 seconds
Started Jul 15 05:51:05 PM PDT 24
Finished Jul 15 05:51:08 PM PDT 24
Peak memory 208504 kb
Host smart-92fc1803-c134-4fd9-8765-5e826563b4ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411672045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3411672045
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3448730754
Short name T561
Test name
Test status
Simulation time 883320880 ps
CPU time 3.33 seconds
Started Jul 15 05:51:13 PM PDT 24
Finished Jul 15 05:51:17 PM PDT 24
Peak memory 200396 kb
Host smart-cb8a8989-40c7-4e2d-b3df-b7c35917ea02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448730754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3448730754
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.588358672
Short name T604
Test name
Test status
Simulation time 181692460 ps
CPU time 1.28 seconds
Started Jul 15 05:51:11 PM PDT 24
Finished Jul 15 05:51:13 PM PDT 24
Peak memory 208600 kb
Host smart-21b543f4-368f-48dc-80d3-b6ba0f69c338
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588358672 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.588358672
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.874552827
Short name T550
Test name
Test status
Simulation time 77991066 ps
CPU time 0.82 seconds
Started Jul 15 05:51:13 PM PDT 24
Finished Jul 15 05:51:15 PM PDT 24
Peak memory 200196 kb
Host smart-0d6f6d3a-a2e2-4810-854e-137868b0cffc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874552827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.874552827
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.104633673
Short name T105
Test name
Test status
Simulation time 201073960 ps
CPU time 1.51 seconds
Started Jul 15 05:51:12 PM PDT 24
Finished Jul 15 05:51:15 PM PDT 24
Peak memory 200404 kb
Host smart-3390696e-08aa-4cb9-b67b-66a435290420
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104633673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.104633673
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3431632448
Short name T60
Test name
Test status
Simulation time 124911945 ps
CPU time 1.72 seconds
Started Jul 15 05:51:11 PM PDT 24
Finished Jul 15 05:51:14 PM PDT 24
Peak memory 212156 kb
Host smart-0b398aaf-7066-4a58-a1fb-9c7c1809fd46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431632448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3431632448
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3918802552
Short name T68
Test name
Test status
Simulation time 112322642 ps
CPU time 1.06 seconds
Started Jul 15 05:51:11 PM PDT 24
Finished Jul 15 05:51:13 PM PDT 24
Peak memory 200316 kb
Host smart-e8db976d-8631-4048-8c37-08d112b51b25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918802552 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3918802552
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3459581125
Short name T590
Test name
Test status
Simulation time 62957670 ps
CPU time 0.8 seconds
Started Jul 15 05:51:14 PM PDT 24
Finished Jul 15 05:51:16 PM PDT 24
Peak memory 200048 kb
Host smart-4e346d16-9735-4d68-a702-1422ca532a1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459581125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3459581125
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.592559332
Short name T591
Test name
Test status
Simulation time 86370198 ps
CPU time 1.02 seconds
Started Jul 15 05:51:14 PM PDT 24
Finished Jul 15 05:51:16 PM PDT 24
Peak memory 200096 kb
Host smart-054763de-fcfc-496a-8cb2-15a70d86b63f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592559332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.592559332
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1368715905
Short name T581
Test name
Test status
Simulation time 534792706 ps
CPU time 4.16 seconds
Started Jul 15 05:51:14 PM PDT 24
Finished Jul 15 05:51:19 PM PDT 24
Peak memory 208552 kb
Host smart-a192eeeb-4250-4448-b712-f21625cb67e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368715905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1368715905
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.354556639
Short name T136
Test name
Test status
Simulation time 481441867 ps
CPU time 2.01 seconds
Started Jul 15 05:51:11 PM PDT 24
Finished Jul 15 05:51:14 PM PDT 24
Peak memory 200424 kb
Host smart-fee5c72c-e8f2-44f4-b82f-d7c512f986e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354556639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.354556639
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3204783357
Short name T559
Test name
Test status
Simulation time 110863226 ps
CPU time 1.15 seconds
Started Jul 15 05:51:11 PM PDT 24
Finished Jul 15 05:51:13 PM PDT 24
Peak memory 208544 kb
Host smart-6359c19d-c874-4529-ac16-3c4c4eb9480e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204783357 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3204783357
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.583507265
Short name T592
Test name
Test status
Simulation time 81830001 ps
CPU time 0.84 seconds
Started Jul 15 05:51:10 PM PDT 24
Finished Jul 15 05:51:12 PM PDT 24
Peak memory 200236 kb
Host smart-beb7e727-ef61-4df5-99c4-808107c0f134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583507265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.583507265
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1217494564
Short name T571
Test name
Test status
Simulation time 130902360 ps
CPU time 1.15 seconds
Started Jul 15 05:51:12 PM PDT 24
Finished Jul 15 05:51:14 PM PDT 24
Peak memory 200236 kb
Host smart-d4332881-db56-45f1-aed0-721200fbc8fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217494564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1217494564
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3213524736
Short name T589
Test name
Test status
Simulation time 473870844 ps
CPU time 3.04 seconds
Started Jul 15 05:51:12 PM PDT 24
Finished Jul 15 05:51:17 PM PDT 24
Peak memory 208412 kb
Host smart-c25a8734-41cf-4863-ade4-0072639a98c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213524736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3213524736
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.959411278
Short name T618
Test name
Test status
Simulation time 120500035 ps
CPU time 1.34 seconds
Started Jul 15 05:51:21 PM PDT 24
Finished Jul 15 05:51:23 PM PDT 24
Peak memory 208384 kb
Host smart-21bf5e42-2f72-41c1-b27d-3ceede46e195
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959411278 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.959411278
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3407879168
Short name T101
Test name
Test status
Simulation time 65979888 ps
CPU time 0.82 seconds
Started Jul 15 05:51:26 PM PDT 24
Finished Jul 15 05:51:28 PM PDT 24
Peak memory 200204 kb
Host smart-5b32d113-5b0d-4ffd-9bc0-51f34aabcc8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407879168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3407879168
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2624156459
Short name T585
Test name
Test status
Simulation time 91739626 ps
CPU time 1.02 seconds
Started Jul 15 05:51:22 PM PDT 24
Finished Jul 15 05:51:24 PM PDT 24
Peak memory 200180 kb
Host smart-7f01e5b5-9801-475c-89fb-e6dbe09ae9e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624156459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2624156459
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3154714577
Short name T553
Test name
Test status
Simulation time 257315254 ps
CPU time 1.83 seconds
Started Jul 15 05:51:22 PM PDT 24
Finished Jul 15 05:51:25 PM PDT 24
Peak memory 208556 kb
Host smart-a59d73f4-6622-4efb-93c8-49d8b64431e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154714577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3154714577
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.64655793
Short name T134
Test name
Test status
Simulation time 422793125 ps
CPU time 1.91 seconds
Started Jul 15 05:51:22 PM PDT 24
Finished Jul 15 05:51:25 PM PDT 24
Peak memory 200460 kb
Host smart-6367074c-3dd1-4feb-b91d-7446a3b50d85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64655793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.64655793
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2571480144
Short name T547
Test name
Test status
Simulation time 165232971 ps
CPU time 1.19 seconds
Started Jul 15 05:51:21 PM PDT 24
Finished Jul 15 05:51:23 PM PDT 24
Peak memory 208540 kb
Host smart-bf5a0cd6-3ffb-4f1d-a847-70716e362af8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571480144 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2571480144
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3094355545
Short name T603
Test name
Test status
Simulation time 69939478 ps
CPU time 0.75 seconds
Started Jul 15 05:51:23 PM PDT 24
Finished Jul 15 05:51:24 PM PDT 24
Peak memory 200052 kb
Host smart-7e3ac038-20e3-420e-aff9-49c904272af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094355545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3094355545
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3314736394
Short name T108
Test name
Test status
Simulation time 228495718 ps
CPU time 1.61 seconds
Started Jul 15 05:51:20 PM PDT 24
Finished Jul 15 05:51:22 PM PDT 24
Peak memory 200388 kb
Host smart-3af9627f-2444-4d99-aa22-d19c66136d9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314736394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3314736394
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.54900994
Short name T79
Test name
Test status
Simulation time 927120201 ps
CPU time 3.46 seconds
Started Jul 15 05:51:20 PM PDT 24
Finished Jul 15 05:51:24 PM PDT 24
Peak memory 200344 kb
Host smart-b4e44fb7-a747-4c33-b355-a589a5dd9387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54900994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.54900994
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3033981980
Short name T593
Test name
Test status
Simulation time 166287131 ps
CPU time 1.45 seconds
Started Jul 15 05:51:20 PM PDT 24
Finished Jul 15 05:51:22 PM PDT 24
Peak memory 208680 kb
Host smart-1605614d-cc6d-457e-8c52-afa41f2219b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033981980 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3033981980
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3162700568
Short name T548
Test name
Test status
Simulation time 61741809 ps
CPU time 0.86 seconds
Started Jul 15 05:51:20 PM PDT 24
Finished Jul 15 05:51:21 PM PDT 24
Peak memory 200112 kb
Host smart-d012e8ff-832d-49dd-bbce-399fb8fd4fa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162700568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3162700568
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2553504151
Short name T580
Test name
Test status
Simulation time 129816436 ps
CPU time 1.09 seconds
Started Jul 15 05:51:20 PM PDT 24
Finished Jul 15 05:51:22 PM PDT 24
Peak memory 200188 kb
Host smart-15e790d1-7cd5-4212-87cd-5ef48e22f1d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553504151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2553504151
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4198905925
Short name T80
Test name
Test status
Simulation time 207533465 ps
CPU time 1.69 seconds
Started Jul 15 05:51:20 PM PDT 24
Finished Jul 15 05:51:23 PM PDT 24
Peak memory 200424 kb
Host smart-646155eb-d1d1-44fb-980b-0c4fb483e279
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198905925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4198905925
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.564374638
Short name T137
Test name
Test status
Simulation time 410789756 ps
CPU time 1.81 seconds
Started Jul 15 05:51:24 PM PDT 24
Finished Jul 15 05:51:27 PM PDT 24
Peak memory 200388 kb
Host smart-4f3e7328-8c49-4e4e-bfbe-9060ab18b828
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564374638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.564374638
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3646091479
Short name T573
Test name
Test status
Simulation time 185455107 ps
CPU time 1.88 seconds
Started Jul 15 05:51:21 PM PDT 24
Finished Jul 15 05:51:24 PM PDT 24
Peak memory 213360 kb
Host smart-58e2e8d1-5cca-41b1-b421-5071e26ea03f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646091479 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3646091479
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1616884491
Short name T544
Test name
Test status
Simulation time 66317248 ps
CPU time 0.78 seconds
Started Jul 15 05:51:21 PM PDT 24
Finished Jul 15 05:51:24 PM PDT 24
Peak memory 200240 kb
Host smart-e994cc26-0e7d-4aec-826a-14823cb17014
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616884491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1616884491
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1871710957
Short name T595
Test name
Test status
Simulation time 119194879 ps
CPU time 1.15 seconds
Started Jul 15 05:51:19 PM PDT 24
Finished Jul 15 05:51:21 PM PDT 24
Peak memory 200324 kb
Host smart-9a39afd8-2daf-4783-a30b-27a8832f2696
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871710957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1871710957
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.170014532
Short name T620
Test name
Test status
Simulation time 169783684 ps
CPU time 2.46 seconds
Started Jul 15 05:51:21 PM PDT 24
Finished Jul 15 05:51:24 PM PDT 24
Peak memory 208520 kb
Host smart-5f6075ec-ec4d-4c1d-83e2-fc9203fbf172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170014532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.170014532
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1161840143
Short name T584
Test name
Test status
Simulation time 461373156 ps
CPU time 1.79 seconds
Started Jul 15 05:51:19 PM PDT 24
Finished Jul 15 05:51:22 PM PDT 24
Peak memory 200456 kb
Host smart-9a2dad2c-08b5-451d-955c-fd1ce3e0a297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161840143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1161840143
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.346470525
Short name T614
Test name
Test status
Simulation time 181864143 ps
CPU time 1.29 seconds
Started Jul 15 05:51:19 PM PDT 24
Finished Jul 15 05:51:21 PM PDT 24
Peak memory 208536 kb
Host smart-77902660-38fc-4710-8c6b-123a1d0df09f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346470525 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.346470525
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.216700720
Short name T596
Test name
Test status
Simulation time 74332983 ps
CPU time 0.91 seconds
Started Jul 15 05:51:22 PM PDT 24
Finished Jul 15 05:51:24 PM PDT 24
Peak memory 200244 kb
Host smart-c0a7fc3b-e15f-49ca-b50d-4353ab2bebd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216700720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.216700720
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2962435998
Short name T562
Test name
Test status
Simulation time 123161890 ps
CPU time 1.22 seconds
Started Jul 15 05:51:21 PM PDT 24
Finished Jul 15 05:51:24 PM PDT 24
Peak memory 200280 kb
Host smart-3c0f2186-0b2f-4d7c-b2ad-36f8f7652d35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962435998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2962435998
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.224660189
Short name T583
Test name
Test status
Simulation time 241122841 ps
CPU time 1.79 seconds
Started Jul 15 05:51:21 PM PDT 24
Finished Jul 15 05:51:23 PM PDT 24
Peak memory 208520 kb
Host smart-66f0b64e-8ff9-4a98-8ec4-ebf9994897d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224660189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.224660189
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.948471381
Short name T555
Test name
Test status
Simulation time 473942585 ps
CPU time 2.02 seconds
Started Jul 15 05:51:21 PM PDT 24
Finished Jul 15 05:51:24 PM PDT 24
Peak memory 200472 kb
Host smart-168009dc-20ff-426d-8701-7f8763c1b4cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948471381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.948471381
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4095183100
Short name T619
Test name
Test status
Simulation time 205528775 ps
CPU time 1.68 seconds
Started Jul 15 05:51:00 PM PDT 24
Finished Jul 15 05:51:03 PM PDT 24
Peak memory 200396 kb
Host smart-d663e283-33c9-493c-96cc-5f8d3356777e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095183100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.4
095183100
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2932380014
Short name T557
Test name
Test status
Simulation time 477985528 ps
CPU time 6.2 seconds
Started Jul 15 05:50:56 PM PDT 24
Finished Jul 15 05:51:02 PM PDT 24
Peak memory 216000 kb
Host smart-e7f6f8ef-5b91-4097-bba2-eeb245c6d323
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932380014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
932380014
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2271562717
Short name T599
Test name
Test status
Simulation time 126317311 ps
CPU time 1 seconds
Started Jul 15 05:51:01 PM PDT 24
Finished Jul 15 05:51:03 PM PDT 24
Peak memory 200420 kb
Host smart-3a39a789-805c-4118-a980-182f27e1db1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271562717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
271562717
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.418300905
Short name T88
Test name
Test status
Simulation time 179363641 ps
CPU time 1.67 seconds
Started Jul 15 05:51:00 PM PDT 24
Finished Jul 15 05:51:03 PM PDT 24
Peak memory 208640 kb
Host smart-9861b5b2-da3c-4a38-9816-b6b785e9c0ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418300905 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.418300905
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1393945634
Short name T568
Test name
Test status
Simulation time 64658926 ps
CPU time 0.77 seconds
Started Jul 15 05:51:00 PM PDT 24
Finished Jul 15 05:51:01 PM PDT 24
Peak memory 200048 kb
Host smart-a7b8ec69-f747-4871-a5d4-8473cf775953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393945634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1393945634
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1105150329
Short name T103
Test name
Test status
Simulation time 144950665 ps
CPU time 1.15 seconds
Started Jul 15 05:50:58 PM PDT 24
Finished Jul 15 05:51:00 PM PDT 24
Peak memory 200284 kb
Host smart-5ea43004-2a1b-4995-adc4-44bd0b8d7b76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105150329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1105150329
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2439972847
Short name T566
Test name
Test status
Simulation time 179484992 ps
CPU time 2.62 seconds
Started Jul 15 05:50:56 PM PDT 24
Finished Jul 15 05:50:59 PM PDT 24
Peak memory 208560 kb
Host smart-63b7dd0d-40c4-4a7f-a831-07eb596a5e48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439972847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2439972847
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1225951887
Short name T72
Test name
Test status
Simulation time 420960321 ps
CPU time 1.78 seconds
Started Jul 15 05:50:56 PM PDT 24
Finished Jul 15 05:50:58 PM PDT 24
Peak memory 200312 kb
Host smart-8bee3325-5c79-464d-9c79-5e50245e8abb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225951887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1225951887
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1044583220
Short name T139
Test name
Test status
Simulation time 147022777 ps
CPU time 1.82 seconds
Started Jul 15 05:50:56 PM PDT 24
Finished Jul 15 05:50:59 PM PDT 24
Peak memory 200364 kb
Host smart-4afaaaa7-77a8-4761-97b8-9d62c930b6c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044583220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
044583220
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.137332186
Short name T606
Test name
Test status
Simulation time 481750583 ps
CPU time 5.73 seconds
Started Jul 15 05:50:55 PM PDT 24
Finished Jul 15 05:51:01 PM PDT 24
Peak memory 200348 kb
Host smart-efbcc1d6-9e9f-4f37-84f9-5fa76d987099
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137332186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.137332186
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1450712240
Short name T612
Test name
Test status
Simulation time 99618917 ps
CPU time 0.85 seconds
Started Jul 15 05:50:56 PM PDT 24
Finished Jul 15 05:50:58 PM PDT 24
Peak memory 200252 kb
Host smart-bcce5c57-84a8-4f7b-bd76-e8a28f23dfe4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450712240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
450712240
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1411445046
Short name T610
Test name
Test status
Simulation time 193152958 ps
CPU time 1.32 seconds
Started Jul 15 05:50:57 PM PDT 24
Finished Jul 15 05:50:59 PM PDT 24
Peak memory 208560 kb
Host smart-7c252a32-7d5e-494a-a63d-3541bb59585e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411445046 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1411445046
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4001830557
Short name T575
Test name
Test status
Simulation time 56824249 ps
CPU time 0.75 seconds
Started Jul 15 05:50:59 PM PDT 24
Finished Jul 15 05:51:01 PM PDT 24
Peak memory 200136 kb
Host smart-1b2cd033-20e7-4a14-bece-c2ebd1859ccf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001830557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4001830557
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1464092919
Short name T109
Test name
Test status
Simulation time 115666078 ps
CPU time 1.38 seconds
Started Jul 15 05:50:56 PM PDT 24
Finished Jul 15 05:50:58 PM PDT 24
Peak memory 200460 kb
Host smart-b928d9e5-c6ea-449d-a441-1cd8585a1da5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464092919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1464092919
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.365905527
Short name T74
Test name
Test status
Simulation time 483608553 ps
CPU time 3.43 seconds
Started Jul 15 05:50:56 PM PDT 24
Finished Jul 15 05:51:01 PM PDT 24
Peak memory 208488 kb
Host smart-4c29aaa1-7713-4d72-9870-9719b2f23a42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365905527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.365905527
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1346994444
Short name T71
Test name
Test status
Simulation time 414580936 ps
CPU time 1.9 seconds
Started Jul 15 05:50:58 PM PDT 24
Finished Jul 15 05:51:01 PM PDT 24
Peak memory 200452 kb
Host smart-6e1643a0-31e3-4472-86c0-47de4ed19799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346994444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1346994444
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2671103246
Short name T59
Test name
Test status
Simulation time 162158647 ps
CPU time 2.16 seconds
Started Jul 15 05:51:00 PM PDT 24
Finished Jul 15 05:51:03 PM PDT 24
Peak memory 208540 kb
Host smart-6f868964-9662-4830-9aa2-f85ddedac19c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671103246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
671103246
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.92397632
Short name T545
Test name
Test status
Simulation time 790863338 ps
CPU time 4.39 seconds
Started Jul 15 05:50:59 PM PDT 24
Finished Jul 15 05:51:04 PM PDT 24
Peak memory 200248 kb
Host smart-91ed5f98-f4a5-4984-8666-d7fae27d7c7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92397632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.92397632
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.754661307
Short name T56
Test name
Test status
Simulation time 130775093 ps
CPU time 0.92 seconds
Started Jul 15 05:50:58 PM PDT 24
Finished Jul 15 05:51:00 PM PDT 24
Peak memory 200164 kb
Host smart-ae85e7eb-0d85-453f-bcef-b2322f5b4f52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754661307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.754661307
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1762751252
Short name T587
Test name
Test status
Simulation time 129664362 ps
CPU time 1.03 seconds
Started Jul 15 05:50:56 PM PDT 24
Finished Jul 15 05:50:58 PM PDT 24
Peak memory 200316 kb
Host smart-097ed2cc-9c8e-44b3-bfa2-297af8c47ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762751252 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1762751252
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.621235239
Short name T577
Test name
Test status
Simulation time 73396956 ps
CPU time 0.8 seconds
Started Jul 15 05:50:58 PM PDT 24
Finished Jul 15 05:50:59 PM PDT 24
Peak memory 200212 kb
Host smart-2788bce6-fdc3-43a7-996e-bba9cebadd3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621235239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.621235239
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.427433264
Short name T104
Test name
Test status
Simulation time 141739839 ps
CPU time 1.1 seconds
Started Jul 15 05:51:01 PM PDT 24
Finished Jul 15 05:51:03 PM PDT 24
Peak memory 200176 kb
Host smart-3d7977ad-72a3-41e4-8437-8c22d4b8b464
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427433264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.427433264
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3571817317
Short name T554
Test name
Test status
Simulation time 382666911 ps
CPU time 2.83 seconds
Started Jul 15 05:50:57 PM PDT 24
Finished Jul 15 05:51:01 PM PDT 24
Peak memory 208636 kb
Host smart-bc721494-9afc-4b51-82ac-cc4f6b2f10a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571817317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3571817317
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1016479858
Short name T616
Test name
Test status
Simulation time 496361203 ps
CPU time 1.9 seconds
Started Jul 15 05:50:58 PM PDT 24
Finished Jul 15 05:51:00 PM PDT 24
Peak memory 200416 kb
Host smart-6cfb9082-e036-4953-a7df-e3838df4a452
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016479858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1016479858
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4222563867
Short name T572
Test name
Test status
Simulation time 138648176 ps
CPU time 1.14 seconds
Started Jul 15 05:51:06 PM PDT 24
Finished Jul 15 05:51:08 PM PDT 24
Peak memory 209668 kb
Host smart-899ae595-758b-4a8a-8baa-c4a9304e824b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222563867 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.4222563867
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.34878201
Short name T608
Test name
Test status
Simulation time 85355206 ps
CPU time 0.88 seconds
Started Jul 15 05:51:01 PM PDT 24
Finished Jul 15 05:51:03 PM PDT 24
Peak memory 200112 kb
Host smart-46ee20bf-3caf-4e5f-a796-0ded8e5baaac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34878201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.34878201
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.932712059
Short name T102
Test name
Test status
Simulation time 222279178 ps
CPU time 1.64 seconds
Started Jul 15 05:51:11 PM PDT 24
Finished Jul 15 05:51:14 PM PDT 24
Peak memory 200396 kb
Host smart-ee9eefcb-41cf-4532-9e6d-856f2f5f258c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932712059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.932712059
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.245791994
Short name T549
Test name
Test status
Simulation time 583660254 ps
CPU time 3.67 seconds
Started Jul 15 05:51:01 PM PDT 24
Finished Jul 15 05:51:05 PM PDT 24
Peak memory 208524 kb
Host smart-d8ec37ae-b31a-47c5-8842-2ec42f8fe884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245791994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.245791994
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3423933939
Short name T135
Test name
Test status
Simulation time 778032020 ps
CPU time 2.78 seconds
Started Jul 15 05:50:56 PM PDT 24
Finished Jul 15 05:51:00 PM PDT 24
Peak memory 200396 kb
Host smart-1d256654-40a4-488c-9f35-b7e2b05d6e63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423933939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3423933939
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.799464504
Short name T87
Test name
Test status
Simulation time 183987583 ps
CPU time 1.8 seconds
Started Jul 15 05:51:03 PM PDT 24
Finished Jul 15 05:51:05 PM PDT 24
Peak memory 208516 kb
Host smart-8e151b41-9905-4672-9e03-3ca139d78b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799464504 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.799464504
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3803109984
Short name T613
Test name
Test status
Simulation time 60817504 ps
CPU time 0.8 seconds
Started Jul 15 05:51:09 PM PDT 24
Finished Jul 15 05:51:11 PM PDT 24
Peak memory 200212 kb
Host smart-9d3db506-171e-4dab-a7fc-5b94cdcc1234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803109984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3803109984
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1670728883
Short name T556
Test name
Test status
Simulation time 78402821 ps
CPU time 0.96 seconds
Started Jul 15 05:51:03 PM PDT 24
Finished Jul 15 05:51:05 PM PDT 24
Peak memory 200284 kb
Host smart-00e48021-be33-4255-a789-624d8422c88a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670728883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1670728883
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1696061260
Short name T75
Test name
Test status
Simulation time 183414588 ps
CPU time 2.54 seconds
Started Jul 15 05:51:12 PM PDT 24
Finished Jul 15 05:51:16 PM PDT 24
Peak memory 216508 kb
Host smart-f2de1b5a-7365-4fd0-a6e9-2c1c13cd9861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696061260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1696061260
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3787654169
Short name T138
Test name
Test status
Simulation time 888653608 ps
CPU time 3.22 seconds
Started Jul 15 05:51:10 PM PDT 24
Finished Jul 15 05:51:14 PM PDT 24
Peak memory 200480 kb
Host smart-f5a1bd0a-60c2-434c-aa4f-f31f218533b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787654169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3787654169
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1434390959
Short name T551
Test name
Test status
Simulation time 122816004 ps
CPU time 1.17 seconds
Started Jul 15 05:51:03 PM PDT 24
Finished Jul 15 05:51:06 PM PDT 24
Peak memory 208444 kb
Host smart-f8b1c574-27ce-4a1d-8556-1de0497a25b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434390959 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1434390959
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2379565059
Short name T107
Test name
Test status
Simulation time 67027167 ps
CPU time 0.84 seconds
Started Jul 15 05:51:04 PM PDT 24
Finished Jul 15 05:51:06 PM PDT 24
Peak memory 200236 kb
Host smart-9dea5758-0f56-4467-877f-83ad34316fd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379565059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2379565059
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3911223302
Short name T607
Test name
Test status
Simulation time 137825457 ps
CPU time 1.09 seconds
Started Jul 15 05:51:03 PM PDT 24
Finished Jul 15 05:51:05 PM PDT 24
Peak memory 200232 kb
Host smart-a65cbd8d-363e-4371-b203-b1830a0036d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911223302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3911223302
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.136238700
Short name T62
Test name
Test status
Simulation time 118989531 ps
CPU time 1.69 seconds
Started Jul 15 05:51:10 PM PDT 24
Finished Jul 15 05:51:12 PM PDT 24
Peak memory 208540 kb
Host smart-21742be2-51ea-47f1-9fad-0750b9093f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136238700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.136238700
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1923203475
Short name T552
Test name
Test status
Simulation time 161483519 ps
CPU time 1.5 seconds
Started Jul 15 05:51:03 PM PDT 24
Finished Jul 15 05:51:06 PM PDT 24
Peak memory 208744 kb
Host smart-702cc245-2616-4d29-8acf-dfe892e35763
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923203475 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1923203475
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.417768035
Short name T602
Test name
Test status
Simulation time 71038740 ps
CPU time 0.85 seconds
Started Jul 15 05:51:04 PM PDT 24
Finished Jul 15 05:51:06 PM PDT 24
Peak memory 200248 kb
Host smart-7086dc2b-fbac-4d7f-9373-62f8aa2a2797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417768035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.417768035
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2077939694
Short name T565
Test name
Test status
Simulation time 115658747 ps
CPU time 1.04 seconds
Started Jul 15 05:51:05 PM PDT 24
Finished Jul 15 05:51:07 PM PDT 24
Peak memory 200180 kb
Host smart-e6106caa-0f33-4dca-901a-30fecc841c1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077939694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2077939694
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1769392554
Short name T578
Test name
Test status
Simulation time 653443611 ps
CPU time 4.11 seconds
Started Jul 15 05:51:04 PM PDT 24
Finished Jul 15 05:51:09 PM PDT 24
Peak memory 208544 kb
Host smart-5a52565f-8439-4958-96ef-aa31970babfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769392554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1769392554
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.925803973
Short name T563
Test name
Test status
Simulation time 806570064 ps
CPU time 2.92 seconds
Started Jul 15 05:51:06 PM PDT 24
Finished Jul 15 05:51:10 PM PDT 24
Peak memory 200380 kb
Host smart-421a7a6c-2bbd-4333-a46c-28a6f5317e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925803973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
925803973
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2259572526
Short name T58
Test name
Test status
Simulation time 94540285 ps
CPU time 0.91 seconds
Started Jul 15 05:51:03 PM PDT 24
Finished Jul 15 05:51:05 PM PDT 24
Peak memory 200340 kb
Host smart-0f1a261c-4bd4-404c-a3aa-1e0eaaa67c29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259572526 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2259572526
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3520735137
Short name T574
Test name
Test status
Simulation time 90775185 ps
CPU time 0.98 seconds
Started Jul 15 05:51:09 PM PDT 24
Finished Jul 15 05:51:11 PM PDT 24
Peak memory 200212 kb
Host smart-26709ab5-2041-41b4-9f2e-3cd48cec7cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520735137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3520735137
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1505466203
Short name T597
Test name
Test status
Simulation time 141499692 ps
CPU time 1.19 seconds
Started Jul 15 05:51:03 PM PDT 24
Finished Jul 15 05:51:05 PM PDT 24
Peak memory 200308 kb
Host smart-35c457ce-e38a-41d2-bb98-0a89422b78a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505466203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1505466203
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2753357964
Short name T570
Test name
Test status
Simulation time 156197801 ps
CPU time 2.36 seconds
Started Jul 15 05:51:04 PM PDT 24
Finished Jul 15 05:51:07 PM PDT 24
Peak memory 200352 kb
Host smart-96aa042a-cde6-4e3f-9f34-7203f3f49073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753357964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2753357964
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.4194778653
Short name T335
Test name
Test status
Simulation time 67070929 ps
CPU time 0.8 seconds
Started Jul 15 05:51:28 PM PDT 24
Finished Jul 15 05:51:30 PM PDT 24
Peak memory 199856 kb
Host smart-dc33e84f-b82c-46f0-89a3-801ab7d54717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194778653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4194778653
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.859139656
Short name T279
Test name
Test status
Simulation time 1876670579 ps
CPU time 7.23 seconds
Started Jul 15 05:51:31 PM PDT 24
Finished Jul 15 05:51:39 PM PDT 24
Peak memory 221664 kb
Host smart-99f05599-ff64-4115-bbfe-069c894fe364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859139656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.859139656
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3403728740
Short name T377
Test name
Test status
Simulation time 244404959 ps
CPU time 1.17 seconds
Started Jul 15 05:51:33 PM PDT 24
Finished Jul 15 05:51:35 PM PDT 24
Peak memory 217416 kb
Host smart-2d024e13-d193-4993-ae7b-a5f911359f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403728740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3403728740
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2313217267
Short name T388
Test name
Test status
Simulation time 109581695 ps
CPU time 0.8 seconds
Started Jul 15 05:51:21 PM PDT 24
Finished Jul 15 05:51:22 PM PDT 24
Peak memory 199844 kb
Host smart-97316eda-527c-44e8-aad5-d590b320b8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313217267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2313217267
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.852667437
Short name T236
Test name
Test status
Simulation time 1481419177 ps
CPU time 6.84 seconds
Started Jul 15 05:51:33 PM PDT 24
Finished Jul 15 05:51:40 PM PDT 24
Peak memory 200304 kb
Host smart-6774b0b9-a6fa-4be4-a953-1881f1571cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852667437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.852667437
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3883081406
Short name T65
Test name
Test status
Simulation time 8307174591 ps
CPU time 13.73 seconds
Started Jul 15 05:51:26 PM PDT 24
Finished Jul 15 05:51:40 PM PDT 24
Peak memory 217240 kb
Host smart-2ac88778-ff52-41ff-8167-8f2f02205d8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883081406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3883081406
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3090951981
Short name T401
Test name
Test status
Simulation time 109745394 ps
CPU time 1.05 seconds
Started Jul 15 05:51:32 PM PDT 24
Finished Jul 15 05:51:34 PM PDT 24
Peak memory 200256 kb
Host smart-528f4a7e-fde8-47e9-a30a-27c27589721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090951981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3090951981
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1525645402
Short name T318
Test name
Test status
Simulation time 197274539 ps
CPU time 1.39 seconds
Started Jul 15 05:51:20 PM PDT 24
Finished Jul 15 05:51:22 PM PDT 24
Peak memory 200244 kb
Host smart-992c24a4-eca3-4d7a-a664-6db7926ab658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525645402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1525645402
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.660765229
Short name T408
Test name
Test status
Simulation time 3150505598 ps
CPU time 15.79 seconds
Started Jul 15 05:51:32 PM PDT 24
Finished Jul 15 05:51:49 PM PDT 24
Peak memory 208520 kb
Host smart-eed1fa0f-16b4-4639-9c79-481499fa15fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660765229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.660765229
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2421195141
Short name T376
Test name
Test status
Simulation time 377652393 ps
CPU time 2.24 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:32 PM PDT 24
Peak memory 200064 kb
Host smart-3e44904e-4599-45f5-93f9-d89d4e040237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421195141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2421195141
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2835889966
Short name T540
Test name
Test status
Simulation time 131398876 ps
CPU time 1.03 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:31 PM PDT 24
Peak memory 200036 kb
Host smart-d6e3164e-ba88-4b4d-b4e2-967845b4af8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835889966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2835889966
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2128269180
Short name T212
Test name
Test status
Simulation time 54244218 ps
CPU time 0.76 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:31 PM PDT 24
Peak memory 199808 kb
Host smart-d1214a6b-f1b9-4c66-ac83-01c013d65587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128269180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2128269180
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.594497970
Short name T454
Test name
Test status
Simulation time 1904207613 ps
CPU time 7.44 seconds
Started Jul 15 05:51:28 PM PDT 24
Finished Jul 15 05:51:36 PM PDT 24
Peak memory 217144 kb
Host smart-60a07e7a-aa14-494f-8757-ef41a55a1cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594497970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.594497970
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2292153414
Short name T387
Test name
Test status
Simulation time 244028768 ps
CPU time 1.11 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:31 PM PDT 24
Peak memory 217428 kb
Host smart-6aae41aa-9de1-4d01-820d-bc24bc6b40d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292153414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2292153414
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1510007900
Short name T494
Test name
Test status
Simulation time 1638414074 ps
CPU time 6.46 seconds
Started Jul 15 05:51:33 PM PDT 24
Finished Jul 15 05:51:40 PM PDT 24
Peak memory 200384 kb
Host smart-61b3d90a-608b-4682-aace-4300840749d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510007900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1510007900
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.4192910600
Short name T70
Test name
Test status
Simulation time 19863849834 ps
CPU time 29.36 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:59 PM PDT 24
Peak memory 217232 kb
Host smart-a416cd43-a869-408f-a521-a34676632e04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192910600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4192910600
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2594554300
Short name T244
Test name
Test status
Simulation time 112981604 ps
CPU time 1.08 seconds
Started Jul 15 05:51:28 PM PDT 24
Finished Jul 15 05:51:30 PM PDT 24
Peak memory 200076 kb
Host smart-153f91c1-39d4-484d-a1f6-9e4771175176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594554300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2594554300
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1210268576
Short name T299
Test name
Test status
Simulation time 212242334 ps
CPU time 1.54 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:31 PM PDT 24
Peak memory 200296 kb
Host smart-efc35c5d-a9cd-41f0-8a22-6785bcb6b33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210268576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1210268576
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.708408678
Short name T263
Test name
Test status
Simulation time 1630842795 ps
CPU time 6.29 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:37 PM PDT 24
Peak memory 200324 kb
Host smart-c54c0d9d-c298-478b-9280-22185423119c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708408678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.708408678
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2351033074
Short name T122
Test name
Test status
Simulation time 58870898 ps
CPU time 0.73 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 199884 kb
Host smart-8224de01-2ba7-46d9-a553-4062a866900c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351033074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2351033074
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3463235078
Short name T243
Test name
Test status
Simulation time 1225784051 ps
CPU time 5.47 seconds
Started Jul 15 05:51:52 PM PDT 24
Finished Jul 15 05:51:59 PM PDT 24
Peak memory 221648 kb
Host smart-00940b5f-9374-44b6-8182-1c2d25a1e0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463235078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3463235078
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2146925006
Short name T405
Test name
Test status
Simulation time 244941750 ps
CPU time 1.12 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:52 PM PDT 24
Peak memory 217432 kb
Host smart-8a92c797-2007-43d4-8f2c-ea4ab8b7d0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146925006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2146925006
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4169115079
Short name T289
Test name
Test status
Simulation time 112582519 ps
CPU time 0.83 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:52 PM PDT 24
Peak memory 199916 kb
Host smart-dd080f1f-e437-4172-be17-d8c694085277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169115079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4169115079
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1777594506
Short name T132
Test name
Test status
Simulation time 1576581757 ps
CPU time 5.74 seconds
Started Jul 15 05:51:50 PM PDT 24
Finished Jul 15 05:51:58 PM PDT 24
Peak memory 200348 kb
Host smart-aa6d184d-0540-4657-a986-f1d47a9a8ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777594506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1777594506
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3011168092
Short name T161
Test name
Test status
Simulation time 170366395 ps
CPU time 1.3 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 200104 kb
Host smart-ce2ddc04-9999-47f0-9b05-0cd403552fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011168092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3011168092
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1825190639
Short name T347
Test name
Test status
Simulation time 194194094 ps
CPU time 1.39 seconds
Started Jul 15 05:51:52 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 200324 kb
Host smart-cb3e95c9-7b72-4da3-8864-4ddf5c721c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825190639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1825190639
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1495513451
Short name T524
Test name
Test status
Simulation time 8104895565 ps
CPU time 37.56 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:52:26 PM PDT 24
Peak memory 208628 kb
Host smart-19f4fe5f-b153-4e9f-908d-7405550f65a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495513451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1495513451
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3130759635
Short name T485
Test name
Test status
Simulation time 137076701 ps
CPU time 1.69 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 200140 kb
Host smart-fe7421af-7916-4054-9760-bf88be420b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130759635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3130759635
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2880247626
Short name T182
Test name
Test status
Simulation time 267332545 ps
CPU time 1.46 seconds
Started Jul 15 05:51:48 PM PDT 24
Finished Jul 15 05:51:52 PM PDT 24
Peak memory 200108 kb
Host smart-dd627511-6ba0-4cd1-a7bf-5510ad227dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880247626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2880247626
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1047140228
Short name T499
Test name
Test status
Simulation time 73078475 ps
CPU time 0.81 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:51:54 PM PDT 24
Peak memory 199776 kb
Host smart-23943b59-4160-4bd1-a1c9-6edec8c87fc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047140228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1047140228
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.574320283
Short name T465
Test name
Test status
Simulation time 1895338788 ps
CPU time 7.97 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:52:01 PM PDT 24
Peak memory 221676 kb
Host smart-725bd4f1-e835-4ff9-b9e2-346c3d997bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574320283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.574320283
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1451940553
Short name T346
Test name
Test status
Simulation time 244315958 ps
CPU time 1.17 seconds
Started Jul 15 05:51:52 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 216664 kb
Host smart-23e18f03-9984-41ec-a763-e963b408df00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451940553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1451940553
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1384370367
Short name T474
Test name
Test status
Simulation time 117321956 ps
CPU time 0.81 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:51 PM PDT 24
Peak memory 199892 kb
Host smart-41ae928a-dfe7-4bcc-b1ed-45a6ffd01c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384370367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1384370367
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2380796140
Short name T100
Test name
Test status
Simulation time 1546794664 ps
CPU time 6.2 seconds
Started Jul 15 05:51:50 PM PDT 24
Finished Jul 15 05:51:58 PM PDT 24
Peak memory 200324 kb
Host smart-044d6d8d-cd0a-4e86-908e-125c9476ddba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380796140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2380796140
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3677702055
Short name T534
Test name
Test status
Simulation time 147992475 ps
CPU time 1.23 seconds
Started Jul 15 05:51:52 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 199280 kb
Host smart-b4ff73c7-5d63-410b-956e-d4e04868eec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677702055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3677702055
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3215333773
Short name T14
Test name
Test status
Simulation time 244607854 ps
CPU time 1.68 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 200172 kb
Host smart-e0aa983e-2a29-427a-9b98-a00ea84557ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215333773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3215333773
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1544173470
Short name T417
Test name
Test status
Simulation time 1402657658 ps
CPU time 6.73 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 208616 kb
Host smart-afc25e9c-bf5d-4705-9c6c-38d9768d5c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544173470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1544173470
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3240596176
Short name T362
Test name
Test status
Simulation time 124366993 ps
CPU time 1.6 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:51:50 PM PDT 24
Peak memory 208220 kb
Host smart-5331cc10-1293-4d68-962a-2110d9af933e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240596176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3240596176
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2172646373
Short name T389
Test name
Test status
Simulation time 66039926 ps
CPU time 0.81 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:51:54 PM PDT 24
Peak memory 200008 kb
Host smart-5ee0e3d5-641e-451b-8f6a-cb64723c2185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172646373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2172646373
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4011631112
Short name T516
Test name
Test status
Simulation time 66159919 ps
CPU time 0.76 seconds
Started Jul 15 05:51:54 PM PDT 24
Finished Jul 15 05:51:56 PM PDT 24
Peak memory 199876 kb
Host smart-3886f3a4-03e5-41d0-bbfb-af9297bb0249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011631112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4011631112
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1662628472
Short name T368
Test name
Test status
Simulation time 243612124 ps
CPU time 1.1 seconds
Started Jul 15 05:51:58 PM PDT 24
Finished Jul 15 05:52:00 PM PDT 24
Peak memory 217428 kb
Host smart-42be13c5-0c9c-4de0-8375-3219a9aa3a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662628472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1662628472
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.516821881
Short name T431
Test name
Test status
Simulation time 158986516 ps
CPU time 0.83 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:51:54 PM PDT 24
Peak memory 199884 kb
Host smart-d9e6385a-d98b-404f-888b-8765fb1aabc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516821881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.516821881
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1732058766
Short name T330
Test name
Test status
Simulation time 1614917116 ps
CPU time 6.01 seconds
Started Jul 15 05:51:55 PM PDT 24
Finished Jul 15 05:52:02 PM PDT 24
Peak memory 200340 kb
Host smart-06a21bce-11d9-4718-9f6b-cbb8d3b98325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732058766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1732058766
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3655728821
Short name T314
Test name
Test status
Simulation time 186858440 ps
CPU time 1.31 seconds
Started Jul 15 05:51:54 PM PDT 24
Finished Jul 15 05:51:56 PM PDT 24
Peak memory 200072 kb
Host smart-b8630548-5236-43c1-a89a-b5303324b90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655728821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3655728821
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2483415442
Short name T525
Test name
Test status
Simulation time 201408055 ps
CPU time 1.4 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 200192 kb
Host smart-bf267545-fdbe-44c4-a0a0-964d9d3d037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483415442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2483415442
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3195828775
Short name T97
Test name
Test status
Simulation time 4454987844 ps
CPU time 20.07 seconds
Started Jul 15 05:51:58 PM PDT 24
Finished Jul 15 05:52:19 PM PDT 24
Peak memory 200428 kb
Host smart-210b01b5-b55c-4b1e-ac89-35d285adb84b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195828775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3195828775
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1136942215
Short name T310
Test name
Test status
Simulation time 384941999 ps
CPU time 2.07 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 200136 kb
Host smart-005542bb-740c-4ea9-9a8d-f2a836e5ba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136942215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1136942215
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2620060548
Short name T415
Test name
Test status
Simulation time 84605366 ps
CPU time 0.94 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 200016 kb
Host smart-fd18f06c-98c4-4e07-a1bc-d30da9cda35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620060548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2620060548
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.4050649441
Short name T203
Test name
Test status
Simulation time 80915738 ps
CPU time 0.82 seconds
Started Jul 15 05:51:59 PM PDT 24
Finished Jul 15 05:52:01 PM PDT 24
Peak memory 199684 kb
Host smart-0d6965a9-4b9d-4095-b410-82de95308406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050649441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.4050649441
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3656164815
Short name T422
Test name
Test status
Simulation time 1899128655 ps
CPU time 6.89 seconds
Started Jul 15 05:51:54 PM PDT 24
Finished Jul 15 05:52:02 PM PDT 24
Peak memory 217604 kb
Host smart-cc84da1a-7455-48e6-8b3a-e2a677c9b24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656164815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3656164815
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2679879046
Short name T462
Test name
Test status
Simulation time 134946361 ps
CPU time 0.81 seconds
Started Jul 15 05:51:54 PM PDT 24
Finished Jul 15 05:51:56 PM PDT 24
Peak memory 199888 kb
Host smart-90211e4f-af2b-40b7-8e9c-203421a457c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679879046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2679879046
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2936928187
Short name T458
Test name
Test status
Simulation time 1840468121 ps
CPU time 7.49 seconds
Started Jul 15 05:51:56 PM PDT 24
Finished Jul 15 05:52:04 PM PDT 24
Peak memory 200236 kb
Host smart-8c098763-f65a-4e08-bd60-40efc0eb1860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936928187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2936928187
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2431155236
Short name T29
Test name
Test status
Simulation time 150316394 ps
CPU time 1.1 seconds
Started Jul 15 05:51:58 PM PDT 24
Finished Jul 15 05:52:00 PM PDT 24
Peak memory 200072 kb
Host smart-bb12a361-1260-48a4-8fee-e62c0d6f7c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431155236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2431155236
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1872838330
Short name T85
Test name
Test status
Simulation time 202912679 ps
CPU time 1.48 seconds
Started Jul 15 05:51:59 PM PDT 24
Finished Jul 15 05:52:02 PM PDT 24
Peak memory 200232 kb
Host smart-594e95ed-b895-4f87-93ee-73f6b3b50898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872838330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1872838330
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3157314568
Short name T307
Test name
Test status
Simulation time 342691271 ps
CPU time 2.28 seconds
Started Jul 15 05:51:55 PM PDT 24
Finished Jul 15 05:51:58 PM PDT 24
Peak memory 200100 kb
Host smart-10f8fadd-8377-4629-bc53-c0cd47718be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157314568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3157314568
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4086611362
Short name T210
Test name
Test status
Simulation time 86107268 ps
CPU time 0.87 seconds
Started Jul 15 05:51:59 PM PDT 24
Finished Jul 15 05:52:01 PM PDT 24
Peak memory 200092 kb
Host smart-dc668873-40b5-467d-8a95-5d6f4e8490dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086611362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4086611362
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.826606269
Short name T158
Test name
Test status
Simulation time 80191901 ps
CPU time 0.83 seconds
Started Jul 15 05:51:55 PM PDT 24
Finished Jul 15 05:51:57 PM PDT 24
Peak memory 199772 kb
Host smart-5ce279ad-fe18-465d-ad0c-f7c83fa5939b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826606269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.826606269
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3327755841
Short name T40
Test name
Test status
Simulation time 1239586284 ps
CPU time 5.46 seconds
Started Jul 15 05:51:59 PM PDT 24
Finished Jul 15 05:52:05 PM PDT 24
Peak memory 221608 kb
Host smart-0e218f71-ca59-4b45-9db7-cab7e47d8769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327755841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3327755841
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3420325138
Short name T189
Test name
Test status
Simulation time 244122300 ps
CPU time 1.06 seconds
Started Jul 15 05:51:59 PM PDT 24
Finished Jul 15 05:52:01 PM PDT 24
Peak memory 217260 kb
Host smart-3ec7b677-6a02-44e2-876e-89b0b09a15da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420325138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3420325138
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4230898423
Short name T294
Test name
Test status
Simulation time 211231675 ps
CPU time 0.94 seconds
Started Jul 15 05:51:54 PM PDT 24
Finished Jul 15 05:51:56 PM PDT 24
Peak memory 199892 kb
Host smart-e2bdfd3d-6799-49fa-8b3c-336a546d1bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230898423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4230898423
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1693908608
Short name T535
Test name
Test status
Simulation time 1657923650 ps
CPU time 6.22 seconds
Started Jul 15 05:51:59 PM PDT 24
Finished Jul 15 05:52:07 PM PDT 24
Peak memory 200384 kb
Host smart-caf57ed7-c7d0-466c-ad27-100fdf16aea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693908608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1693908608
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1090792919
Short name T453
Test name
Test status
Simulation time 155278526 ps
CPU time 1.09 seconds
Started Jul 15 05:51:56 PM PDT 24
Finished Jul 15 05:51:58 PM PDT 24
Peak memory 200008 kb
Host smart-9b248bd2-2fcc-403d-b2ee-5d88f7d6e2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090792919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1090792919
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4193853767
Short name T325
Test name
Test status
Simulation time 246199416 ps
CPU time 1.52 seconds
Started Jul 15 05:51:55 PM PDT 24
Finished Jul 15 05:51:58 PM PDT 24
Peak memory 200312 kb
Host smart-dfe143eb-0ee4-4ffb-8860-d86e7429b323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193853767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4193853767
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.4095280895
Short name T111
Test name
Test status
Simulation time 5850084084 ps
CPU time 22.96 seconds
Started Jul 15 05:51:57 PM PDT 24
Finished Jul 15 05:52:21 PM PDT 24
Peak memory 210244 kb
Host smart-31ef14dc-6acf-4ec8-92fa-66e0c26bbad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095280895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.4095280895
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3340464752
Short name T278
Test name
Test status
Simulation time 442990388 ps
CPU time 2.57 seconds
Started Jul 15 05:51:54 PM PDT 24
Finished Jul 15 05:51:58 PM PDT 24
Peak memory 200156 kb
Host smart-bd8a44e8-1e3b-467e-93ba-c19d58211d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340464752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3340464752
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.60139202
Short name T240
Test name
Test status
Simulation time 138613518 ps
CPU time 1.08 seconds
Started Jul 15 05:51:57 PM PDT 24
Finished Jul 15 05:51:59 PM PDT 24
Peak memory 200112 kb
Host smart-34f585df-5948-470b-823c-d034c35be0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60139202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.60139202
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2729925537
Short name T501
Test name
Test status
Simulation time 88025066 ps
CPU time 0.87 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:05 PM PDT 24
Peak memory 199840 kb
Host smart-5cc53d47-afac-4f2b-abb6-17654727d9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729925537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2729925537
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1352047
Short name T41
Test name
Test status
Simulation time 1215408509 ps
CPU time 5.43 seconds
Started Jul 15 05:51:59 PM PDT 24
Finished Jul 15 05:52:05 PM PDT 24
Peak memory 217772 kb
Host smart-e67e281c-70d8-424e-bfcf-7b3023784448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1352047
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1838007731
Short name T466
Test name
Test status
Simulation time 244158656 ps
CPU time 1.1 seconds
Started Jul 15 05:52:01 PM PDT 24
Finished Jul 15 05:52:03 PM PDT 24
Peak memory 217408 kb
Host smart-150bab20-58dc-492c-b978-eff677fb1b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838007731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1838007731
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2524936909
Short name T260
Test name
Test status
Simulation time 176497202 ps
CPU time 0.89 seconds
Started Jul 15 05:51:58 PM PDT 24
Finished Jul 15 05:52:00 PM PDT 24
Peak memory 199884 kb
Host smart-88167f14-bbe2-40ed-addd-25db6206161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524936909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2524936909
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1044849656
Short name T445
Test name
Test status
Simulation time 979453520 ps
CPU time 5.51 seconds
Started Jul 15 05:51:55 PM PDT 24
Finished Jul 15 05:52:02 PM PDT 24
Peak memory 200392 kb
Host smart-253d677f-733b-4b96-bd67-0b73315dc6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044849656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1044849656
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.256998088
Short name T334
Test name
Test status
Simulation time 98821371 ps
CPU time 1.06 seconds
Started Jul 15 05:51:59 PM PDT 24
Finished Jul 15 05:52:00 PM PDT 24
Peak memory 200076 kb
Host smart-2a6261a8-8281-4e7c-863f-64ddfafb0bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256998088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.256998088
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3770188910
Short name T428
Test name
Test status
Simulation time 199071733 ps
CPU time 1.33 seconds
Started Jul 15 05:51:59 PM PDT 24
Finished Jul 15 05:52:02 PM PDT 24
Peak memory 200276 kb
Host smart-4cdc93f0-6279-46db-8693-d9f20f54db70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770188910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3770188910
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1979259604
Short name T410
Test name
Test status
Simulation time 6510000376 ps
CPU time 22.77 seconds
Started Jul 15 05:52:02 PM PDT 24
Finished Jul 15 05:52:26 PM PDT 24
Peak memory 200388 kb
Host smart-8073a7dd-ae9c-42ca-bbcd-bdf606ebb4e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979259604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1979259604
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.796068081
Short name T471
Test name
Test status
Simulation time 398124204 ps
CPU time 2.53 seconds
Started Jul 15 05:51:56 PM PDT 24
Finished Jul 15 05:51:59 PM PDT 24
Peak memory 200140 kb
Host smart-2086c027-9c8b-4801-850d-f99b494963a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796068081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.796068081
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1026074898
Short name T205
Test name
Test status
Simulation time 240000117 ps
CPU time 1.49 seconds
Started Jul 15 05:51:55 PM PDT 24
Finished Jul 15 05:51:57 PM PDT 24
Peak memory 200048 kb
Host smart-ebdf29ca-d043-481c-a170-925eed5acf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026074898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1026074898
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.546621707
Short name T119
Test name
Test status
Simulation time 75608348 ps
CPU time 0.8 seconds
Started Jul 15 05:52:04 PM PDT 24
Finished Jul 15 05:52:07 PM PDT 24
Peak memory 199896 kb
Host smart-f2fac490-73b2-44b2-855b-5eae2454a811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546621707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.546621707
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2100329832
Short name T38
Test name
Test status
Simulation time 1234175448 ps
CPU time 5.5 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:09 PM PDT 24
Peak memory 217368 kb
Host smart-1158169c-7178-4617-8397-ef345660babf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100329832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2100329832
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.220517393
Short name T172
Test name
Test status
Simulation time 244869270 ps
CPU time 1.11 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:06 PM PDT 24
Peak memory 217372 kb
Host smart-2a68b054-235b-4991-b9e3-b556de86110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220517393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.220517393
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3478929421
Short name T17
Test name
Test status
Simulation time 192065949 ps
CPU time 0.91 seconds
Started Jul 15 05:52:01 PM PDT 24
Finished Jul 15 05:52:02 PM PDT 24
Peak memory 199916 kb
Host smart-a325b931-3831-4576-9af9-ebd795990679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478929421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3478929421
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2098277863
Short name T331
Test name
Test status
Simulation time 808203215 ps
CPU time 4.44 seconds
Started Jul 15 05:52:04 PM PDT 24
Finished Jul 15 05:52:10 PM PDT 24
Peak memory 200364 kb
Host smart-18e9e483-ee45-4c5e-a62b-19850dbde13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098277863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2098277863
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3753330847
Short name T354
Test name
Test status
Simulation time 143824160 ps
CPU time 1.19 seconds
Started Jul 15 05:52:04 PM PDT 24
Finished Jul 15 05:52:06 PM PDT 24
Peak memory 200076 kb
Host smart-4b95fe5c-e517-4e0d-9b70-c0a310175d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753330847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3753330847
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1853621680
Short name T385
Test name
Test status
Simulation time 123733417 ps
CPU time 1.23 seconds
Started Jul 15 05:52:01 PM PDT 24
Finished Jul 15 05:52:04 PM PDT 24
Peak memory 200288 kb
Host smart-6d75075e-f3d4-4b8b-9d57-33e899776096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853621680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1853621680
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2630397623
Short name T373
Test name
Test status
Simulation time 1961214865 ps
CPU time 8.83 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:13 PM PDT 24
Peak memory 209528 kb
Host smart-380e00d1-9b2e-45ec-a076-640a41e7d3d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630397623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2630397623
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3267907386
Short name T155
Test name
Test status
Simulation time 364362890 ps
CPU time 2.31 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:07 PM PDT 24
Peak memory 200056 kb
Host smart-2ef1f258-db5d-4443-bdc0-90739eab1fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267907386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3267907386
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.4271747380
Short name T492
Test name
Test status
Simulation time 80034043 ps
CPU time 0.88 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:05 PM PDT 24
Peak memory 200056 kb
Host smart-f016d3d3-2ab1-4011-bce7-565890cbed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271747380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.4271747380
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3379706102
Short name T475
Test name
Test status
Simulation time 67161699 ps
CPU time 0.77 seconds
Started Jul 15 05:52:02 PM PDT 24
Finished Jul 15 05:52:03 PM PDT 24
Peak memory 199800 kb
Host smart-07168aba-da7e-4607-8043-72ab850ea56a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379706102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3379706102
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3197795816
Short name T283
Test name
Test status
Simulation time 1230949710 ps
CPU time 5.66 seconds
Started Jul 15 05:52:05 PM PDT 24
Finished Jul 15 05:52:12 PM PDT 24
Peak memory 221376 kb
Host smart-0fab0ca2-a7cd-4780-84bc-caabcf091095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197795816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3197795816
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.266931253
Short name T537
Test name
Test status
Simulation time 244408612 ps
CPU time 1.07 seconds
Started Jul 15 05:52:02 PM PDT 24
Finished Jul 15 05:52:04 PM PDT 24
Peak memory 217540 kb
Host smart-59301d30-e01c-4b64-a9fc-644aeb312d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266931253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.266931253
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.4271405945
Short name T18
Test name
Test status
Simulation time 119652034 ps
CPU time 0.8 seconds
Started Jul 15 05:52:04 PM PDT 24
Finished Jul 15 05:52:06 PM PDT 24
Peak memory 199920 kb
Host smart-bc38a2a4-e281-4053-9d6c-7c25d0e1bc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271405945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4271405945
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.623082713
Short name T460
Test name
Test status
Simulation time 1264449974 ps
CPU time 4.89 seconds
Started Jul 15 05:52:02 PM PDT 24
Finished Jul 15 05:52:07 PM PDT 24
Peak memory 200352 kb
Host smart-02c22c6a-c14e-4614-b138-8f45d50797f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623082713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.623082713
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3807964607
Short name T157
Test name
Test status
Simulation time 177198871 ps
CPU time 1.2 seconds
Started Jul 15 05:52:01 PM PDT 24
Finished Jul 15 05:52:02 PM PDT 24
Peak memory 200108 kb
Host smart-eadf95ef-ab09-4c39-a16b-fe92b80fd5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807964607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3807964607
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1754883542
Short name T185
Test name
Test status
Simulation time 121749919 ps
CPU time 1.22 seconds
Started Jul 15 05:52:04 PM PDT 24
Finished Jul 15 05:52:06 PM PDT 24
Peak memory 200276 kb
Host smart-13989469-715e-45a2-a097-a22b25d4114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754883542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1754883542
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3893789507
Short name T430
Test name
Test status
Simulation time 6225033877 ps
CPU time 22.71 seconds
Started Jul 15 05:52:05 PM PDT 24
Finished Jul 15 05:52:30 PM PDT 24
Peak memory 200432 kb
Host smart-af8ccf74-d047-483d-a82d-af6507d4f2eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893789507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3893789507
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3801066102
Short name T257
Test name
Test status
Simulation time 157121440 ps
CPU time 2.04 seconds
Started Jul 15 05:52:02 PM PDT 24
Finished Jul 15 05:52:05 PM PDT 24
Peak memory 200016 kb
Host smart-c8ba5143-e168-48b8-982d-942d5ac80629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801066102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3801066102
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.545058487
Short name T305
Test name
Test status
Simulation time 87617277 ps
CPU time 0.8 seconds
Started Jul 15 05:52:04 PM PDT 24
Finished Jul 15 05:52:06 PM PDT 24
Peak memory 200092 kb
Host smart-919e38f6-f6f6-4a6d-9675-b8098ce79b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545058487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.545058487
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2754725725
Short name T322
Test name
Test status
Simulation time 73564627 ps
CPU time 0.83 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:04 PM PDT 24
Peak memory 199868 kb
Host smart-d42da4db-f246-4718-b3e7-4de686c01709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754725725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2754725725
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.162205445
Short name T231
Test name
Test status
Simulation time 1228958881 ps
CPU time 6.11 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:11 PM PDT 24
Peak memory 217536 kb
Host smart-edce723f-9e5a-4ac6-ac25-3d6aee800203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162205445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.162205445
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2133153140
Short name T328
Test name
Test status
Simulation time 244289200 ps
CPU time 1.07 seconds
Started Jul 15 05:52:07 PM PDT 24
Finished Jul 15 05:52:09 PM PDT 24
Peak memory 217444 kb
Host smart-355b73bc-f7e6-4ebd-b5cf-d518fa789192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133153140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2133153140
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1018289900
Short name T21
Test name
Test status
Simulation time 108911912 ps
CPU time 0.83 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:06 PM PDT 24
Peak memory 199916 kb
Host smart-ddfed4bf-71ef-4a53-82be-8a600c2a6f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018289900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1018289900
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1899185377
Short name T133
Test name
Test status
Simulation time 858416369 ps
CPU time 4.52 seconds
Started Jul 15 05:52:02 PM PDT 24
Finished Jul 15 05:52:08 PM PDT 24
Peak memory 200376 kb
Host smart-91e1be44-868f-4d84-90df-965fb7566e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899185377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1899185377
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1442565941
Short name T285
Test name
Test status
Simulation time 94612842 ps
CPU time 1.02 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:06 PM PDT 24
Peak memory 200048 kb
Host smart-4117eabb-f421-4bec-9b0a-132b9cefcaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442565941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1442565941
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1197135229
Short name T393
Test name
Test status
Simulation time 244946642 ps
CPU time 1.51 seconds
Started Jul 15 05:52:04 PM PDT 24
Finished Jul 15 05:52:07 PM PDT 24
Peak memory 200300 kb
Host smart-1fb1fc0d-36ec-40e5-939c-be6941acadfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197135229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1197135229
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3425031800
Short name T440
Test name
Test status
Simulation time 2877087082 ps
CPU time 13.4 seconds
Started Jul 15 05:52:02 PM PDT 24
Finished Jul 15 05:52:17 PM PDT 24
Peak memory 208628 kb
Host smart-8b75c334-f857-4f22-a34f-0c1582ff2ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425031800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3425031800
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.4055204942
Short name T470
Test name
Test status
Simulation time 124993010 ps
CPU time 1.63 seconds
Started Jul 15 05:52:04 PM PDT 24
Finished Jul 15 05:52:07 PM PDT 24
Peak memory 200104 kb
Host smart-380ad842-9146-40b9-abea-a3a7ecc506e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055204942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.4055204942
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2846574315
Short name T382
Test name
Test status
Simulation time 96901283 ps
CPU time 0.96 seconds
Started Jul 15 05:52:01 PM PDT 24
Finished Jul 15 05:52:02 PM PDT 24
Peak memory 200004 kb
Host smart-5eefc1aa-60ff-4e4a-b3e2-c1e5d1d058e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846574315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2846574315
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1883704774
Short name T175
Test name
Test status
Simulation time 68948222 ps
CPU time 0.78 seconds
Started Jul 15 05:52:09 PM PDT 24
Finished Jul 15 05:52:11 PM PDT 24
Peak memory 199804 kb
Host smart-646df0f8-3250-4108-bdb9-3a5e79f2d8a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883704774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1883704774
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2021466543
Short name T367
Test name
Test status
Simulation time 1222499766 ps
CPU time 6.03 seconds
Started Jul 15 05:52:08 PM PDT 24
Finished Jul 15 05:52:14 PM PDT 24
Peak memory 217776 kb
Host smart-512362cd-989c-4e4a-bf5b-4b429a82a11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021466543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2021466543
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.888981173
Short name T523
Test name
Test status
Simulation time 244317122 ps
CPU time 1.1 seconds
Started Jul 15 05:52:08 PM PDT 24
Finished Jul 15 05:52:10 PM PDT 24
Peak memory 217444 kb
Host smart-455edd5c-3183-447e-945b-cca2e8978fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888981173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.888981173
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.201829258
Short name T526
Test name
Test status
Simulation time 160650297 ps
CPU time 0.85 seconds
Started Jul 15 05:52:05 PM PDT 24
Finished Jul 15 05:52:07 PM PDT 24
Peak memory 199884 kb
Host smart-f85b7a20-1402-42cb-bbfd-6fb629bb969b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201829258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.201829258
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1003283222
Short name T194
Test name
Test status
Simulation time 1360495082 ps
CPU time 6.16 seconds
Started Jul 15 05:52:07 PM PDT 24
Finished Jul 15 05:52:14 PM PDT 24
Peak memory 200336 kb
Host smart-ff416d90-1d69-4033-90ee-67d4e6016314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003283222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1003283222
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3150689748
Short name T482
Test name
Test status
Simulation time 92124177 ps
CPU time 0.97 seconds
Started Jul 15 05:52:08 PM PDT 24
Finished Jul 15 05:52:10 PM PDT 24
Peak memory 200044 kb
Host smart-0b7d85cb-3d62-4480-8a22-a2ddf4bda6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150689748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3150689748
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2843746376
Short name T448
Test name
Test status
Simulation time 233523140 ps
CPU time 1.49 seconds
Started Jul 15 05:52:03 PM PDT 24
Finished Jul 15 05:52:07 PM PDT 24
Peak memory 200284 kb
Host smart-b2ab3f47-f152-4151-8bb7-fdb96a2f9fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843746376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2843746376
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1296215540
Short name T353
Test name
Test status
Simulation time 6889666066 ps
CPU time 30.6 seconds
Started Jul 15 05:52:09 PM PDT 24
Finished Jul 15 05:52:40 PM PDT 24
Peak memory 208600 kb
Host smart-589f65c1-fb0c-4e14-97a2-e662430e158c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296215540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1296215540
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.430688828
Short name T81
Test name
Test status
Simulation time 364989081 ps
CPU time 2.51 seconds
Started Jul 15 05:52:14 PM PDT 24
Finished Jul 15 05:52:17 PM PDT 24
Peak memory 200272 kb
Host smart-ca036270-d1ae-42f4-b984-b54ca536e3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430688828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.430688828
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2409961773
Short name T483
Test name
Test status
Simulation time 112414857 ps
CPU time 1.03 seconds
Started Jul 15 05:52:08 PM PDT 24
Finished Jul 15 05:52:10 PM PDT 24
Peak memory 200036 kb
Host smart-de7d8e32-a368-428c-bc7b-15569d2c3b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409961773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2409961773
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.295597464
Short name T191
Test name
Test status
Simulation time 72656195 ps
CPU time 0.81 seconds
Started Jul 15 05:51:31 PM PDT 24
Finished Jul 15 05:51:33 PM PDT 24
Peak memory 199876 kb
Host smart-9b53771b-c4ac-42af-9f4d-c5c0c4ec1787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295597464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.295597464
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3181215350
Short name T491
Test name
Test status
Simulation time 1894554885 ps
CPU time 7.53 seconds
Started Jul 15 05:51:28 PM PDT 24
Finished Jul 15 05:51:37 PM PDT 24
Peak memory 217332 kb
Host smart-b8baa38d-e113-4d0a-a021-8984dadff177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181215350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3181215350
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3307996150
Short name T153
Test name
Test status
Simulation time 243942025 ps
CPU time 1.22 seconds
Started Jul 15 05:51:30 PM PDT 24
Finished Jul 15 05:51:32 PM PDT 24
Peak memory 217396 kb
Host smart-bbe9b878-592f-46d5-baf1-abbb8d9ff2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307996150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3307996150
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3703047127
Short name T200
Test name
Test status
Simulation time 128040265 ps
CPU time 0.82 seconds
Started Jul 15 05:51:27 PM PDT 24
Finished Jul 15 05:51:29 PM PDT 24
Peak memory 199856 kb
Host smart-3440a926-f870-4615-9526-07d844223327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703047127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3703047127
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2007392493
Short name T112
Test name
Test status
Simulation time 1593208538 ps
CPU time 5.82 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:35 PM PDT 24
Peak memory 200196 kb
Host smart-dad58af2-0642-4df2-ac14-65bd1bc60dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007392493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2007392493
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1326789036
Short name T69
Test name
Test status
Simulation time 16521793009 ps
CPU time 31.52 seconds
Started Jul 15 05:51:32 PM PDT 24
Finished Jul 15 05:52:04 PM PDT 24
Peak memory 217244 kb
Host smart-cc01c7ba-7834-46b1-a8fb-0c2d1ccbba5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326789036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1326789036
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2796697559
Short name T168
Test name
Test status
Simulation time 159618455 ps
CPU time 1.14 seconds
Started Jul 15 05:51:27 PM PDT 24
Finished Jul 15 05:51:29 PM PDT 24
Peak memory 200064 kb
Host smart-ada17d77-0bad-4b4b-a9c1-507007f577c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796697559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2796697559
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3363537281
Short name T441
Test name
Test status
Simulation time 110280740 ps
CPU time 1.2 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:31 PM PDT 24
Peak memory 200132 kb
Host smart-01774b9e-54db-4d89-8cb7-bc063511a52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363537281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3363537281
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.421359935
Short name T477
Test name
Test status
Simulation time 6221203065 ps
CPU time 21.09 seconds
Started Jul 15 05:51:28 PM PDT 24
Finished Jul 15 05:51:51 PM PDT 24
Peak memory 200420 kb
Host smart-3785bad2-732a-4a0e-b865-a3fddc761bee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421359935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.421359935
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2390113646
Short name T204
Test name
Test status
Simulation time 341659709 ps
CPU time 2.12 seconds
Started Jul 15 05:51:30 PM PDT 24
Finished Jul 15 05:51:33 PM PDT 24
Peak memory 208284 kb
Host smart-e01211a8-1ce5-4309-be2d-18863fcfaecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390113646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2390113646
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1054276684
Short name T31
Test name
Test status
Simulation time 178446868 ps
CPU time 1.26 seconds
Started Jul 15 05:51:28 PM PDT 24
Finished Jul 15 05:51:30 PM PDT 24
Peak memory 200000 kb
Host smart-37d09440-dee7-4997-9261-0a971930a91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054276684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1054276684
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.449279212
Short name T288
Test name
Test status
Simulation time 63079693 ps
CPU time 0.78 seconds
Started Jul 15 05:52:10 PM PDT 24
Finished Jul 15 05:52:12 PM PDT 24
Peak memory 199892 kb
Host smart-1af4df36-a735-4bb5-9f04-18bc2a2013bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449279212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.449279212
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3267749042
Short name T277
Test name
Test status
Simulation time 1217914324 ps
CPU time 5.6 seconds
Started Jul 15 05:52:10 PM PDT 24
Finished Jul 15 05:52:16 PM PDT 24
Peak memory 217544 kb
Host smart-c79b84df-8897-412b-8d55-08b852dcdccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267749042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3267749042
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1725483175
Short name T402
Test name
Test status
Simulation time 247613858 ps
CPU time 1.08 seconds
Started Jul 15 05:52:08 PM PDT 24
Finished Jul 15 05:52:09 PM PDT 24
Peak memory 217464 kb
Host smart-1f9e78fb-7fb4-4737-abf5-70bff6a6ce4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725483175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1725483175
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.66010642
Short name T543
Test name
Test status
Simulation time 135235171 ps
CPU time 0.81 seconds
Started Jul 15 05:52:10 PM PDT 24
Finished Jul 15 05:52:11 PM PDT 24
Peak memory 199856 kb
Host smart-d849d102-1972-4242-b2cb-0c841121fb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66010642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.66010642
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.837931691
Short name T399
Test name
Test status
Simulation time 1003667940 ps
CPU time 4.72 seconds
Started Jul 15 05:52:11 PM PDT 24
Finished Jul 15 05:52:16 PM PDT 24
Peak memory 200392 kb
Host smart-ec0053b8-eee8-49df-9e14-8430b22790a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837931691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.837931691
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2546746349
Short name T461
Test name
Test status
Simulation time 178856286 ps
CPU time 1.2 seconds
Started Jul 15 05:52:09 PM PDT 24
Finished Jul 15 05:52:11 PM PDT 24
Peak memory 199996 kb
Host smart-4d04c689-253e-4225-9118-dd6539732487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546746349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2546746349
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3481639267
Short name T206
Test name
Test status
Simulation time 120105406 ps
CPU time 1.25 seconds
Started Jul 15 05:52:07 PM PDT 24
Finished Jul 15 05:52:09 PM PDT 24
Peak memory 200224 kb
Host smart-26a6e141-a741-42ad-8f45-18a38a3df2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481639267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3481639267
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2634474322
Short name T241
Test name
Test status
Simulation time 4879737199 ps
CPU time 22.45 seconds
Started Jul 15 05:52:08 PM PDT 24
Finished Jul 15 05:52:31 PM PDT 24
Peak memory 200400 kb
Host smart-78092a0f-a948-4c59-93c0-36eb1660a579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634474322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2634474322
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1995451647
Short name T201
Test name
Test status
Simulation time 372248084 ps
CPU time 2.37 seconds
Started Jul 15 05:52:10 PM PDT 24
Finished Jul 15 05:52:13 PM PDT 24
Peak memory 200068 kb
Host smart-56c3d42f-9937-4303-9347-ac423d6bf16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995451647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1995451647
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2404159298
Short name T28
Test name
Test status
Simulation time 82025990 ps
CPU time 0.84 seconds
Started Jul 15 05:52:09 PM PDT 24
Finished Jul 15 05:52:11 PM PDT 24
Peak memory 200060 kb
Host smart-cf85d397-710b-4b60-a69b-ea9c1afe0bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404159298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2404159298
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.520326596
Short name T455
Test name
Test status
Simulation time 64821842 ps
CPU time 0.78 seconds
Started Jul 15 05:52:14 PM PDT 24
Finished Jul 15 05:52:15 PM PDT 24
Peak memory 199872 kb
Host smart-a5095820-fecd-4270-9c61-52c915f03647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520326596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.520326596
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1145301958
Short name T48
Test name
Test status
Simulation time 1229285921 ps
CPU time 6.16 seconds
Started Jul 15 05:52:12 PM PDT 24
Finished Jul 15 05:52:19 PM PDT 24
Peak memory 221668 kb
Host smart-1fbbaa68-f9bc-4942-b5b0-01465419d2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145301958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1145301958
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1059955927
Short name T218
Test name
Test status
Simulation time 244039032 ps
CPU time 1.04 seconds
Started Jul 15 05:52:12 PM PDT 24
Finished Jul 15 05:52:13 PM PDT 24
Peak memory 217428 kb
Host smart-0d928302-da34-4224-9c29-fa48abe9c7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059955927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1059955927
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.924030473
Short name T351
Test name
Test status
Simulation time 67415122 ps
CPU time 0.76 seconds
Started Jul 15 05:52:13 PM PDT 24
Finished Jul 15 05:52:14 PM PDT 24
Peak memory 199892 kb
Host smart-cbe9f7d0-4ae8-4133-a5a3-dc95e4f1afc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924030473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.924030473
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2211071702
Short name T531
Test name
Test status
Simulation time 770779779 ps
CPU time 4.31 seconds
Started Jul 15 05:52:09 PM PDT 24
Finished Jul 15 05:52:14 PM PDT 24
Peak memory 200356 kb
Host smart-4cd7ce32-b7db-46aa-aff4-f414cd6f16e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211071702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2211071702
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1834390707
Short name T326
Test name
Test status
Simulation time 96948951 ps
CPU time 0.98 seconds
Started Jul 15 05:52:15 PM PDT 24
Finished Jul 15 05:52:16 PM PDT 24
Peak memory 200084 kb
Host smart-89060b00-e6f2-44ca-9d7f-7c54d19a574c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834390707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1834390707
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3828659671
Short name T219
Test name
Test status
Simulation time 193372638 ps
CPU time 1.41 seconds
Started Jul 15 05:52:11 PM PDT 24
Finished Jul 15 05:52:13 PM PDT 24
Peak memory 200228 kb
Host smart-d8130e2d-f9b0-4db9-ab55-4496c110435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828659671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3828659671
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1228977518
Short name T333
Test name
Test status
Simulation time 6519791377 ps
CPU time 31.67 seconds
Started Jul 15 05:52:11 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 208572 kb
Host smart-c3bf9423-8924-4d9d-b25f-d9c33ecb6abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228977518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1228977518
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2646061785
Short name T364
Test name
Test status
Simulation time 123121727 ps
CPU time 1.64 seconds
Started Jul 15 05:52:11 PM PDT 24
Finished Jul 15 05:52:14 PM PDT 24
Peak memory 208296 kb
Host smart-90ba427b-2969-4ad3-9c29-7af7f827abb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646061785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2646061785
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1358491015
Short name T178
Test name
Test status
Simulation time 113610390 ps
CPU time 1.03 seconds
Started Jul 15 05:52:11 PM PDT 24
Finished Jul 15 05:52:13 PM PDT 24
Peak memory 200032 kb
Host smart-58c05c8a-81a9-43c0-b679-bf8014133adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358491015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1358491015
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.857877855
Short name T147
Test name
Test status
Simulation time 65658105 ps
CPU time 0.75 seconds
Started Jul 15 05:52:18 PM PDT 24
Finished Jul 15 05:52:19 PM PDT 24
Peak memory 199928 kb
Host smart-95a9e875-fb4a-4bcd-9e92-96d8eafdff59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857877855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.857877855
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.4268039472
Short name T469
Test name
Test status
Simulation time 1871463852 ps
CPU time 6.94 seconds
Started Jul 15 05:52:16 PM PDT 24
Finished Jul 15 05:52:23 PM PDT 24
Peak memory 217728 kb
Host smart-05820e60-e32c-472a-bf25-02fc258e2222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268039472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.4268039472
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1260530047
Short name T120
Test name
Test status
Simulation time 243282598 ps
CPU time 1.19 seconds
Started Jul 15 05:52:17 PM PDT 24
Finished Jul 15 05:52:19 PM PDT 24
Peak memory 217484 kb
Host smart-52a57278-739c-4092-993e-bb979c9a6a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260530047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1260530047
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1254885553
Short name T25
Test name
Test status
Simulation time 110980213 ps
CPU time 0.84 seconds
Started Jul 15 05:52:09 PM PDT 24
Finished Jul 15 05:52:10 PM PDT 24
Peak memory 199884 kb
Host smart-ba918f3a-38ca-49d2-a70a-e658f08be378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254885553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1254885553
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1887138509
Short name T484
Test name
Test status
Simulation time 1841221193 ps
CPU time 8.17 seconds
Started Jul 15 05:52:17 PM PDT 24
Finished Jul 15 05:52:26 PM PDT 24
Peak memory 200384 kb
Host smart-e46c6881-dd9b-4155-983b-f6c974dea76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887138509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1887138509
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3269540600
Short name T363
Test name
Test status
Simulation time 98947245 ps
CPU time 1.08 seconds
Started Jul 15 05:52:21 PM PDT 24
Finished Jul 15 05:52:22 PM PDT 24
Peak memory 200260 kb
Host smart-1e2b0bd1-c678-4aa0-8331-f803029475a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269540600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3269540600
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3250498365
Short name T259
Test name
Test status
Simulation time 261997840 ps
CPU time 1.69 seconds
Started Jul 15 05:52:09 PM PDT 24
Finished Jul 15 05:52:11 PM PDT 24
Peak memory 200296 kb
Host smart-f8492c26-ef73-4f25-b61d-9be83b49728a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250498365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3250498365
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3964979670
Short name T500
Test name
Test status
Simulation time 8358764156 ps
CPU time 35.53 seconds
Started Jul 15 05:52:16 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 208560 kb
Host smart-24457943-bd7f-4994-ac3a-4abbcfc3f98d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964979670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3964979670
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.343210201
Short name T8
Test name
Test status
Simulation time 260070544 ps
CPU time 1.82 seconds
Started Jul 15 05:52:18 PM PDT 24
Finished Jul 15 05:52:20 PM PDT 24
Peak memory 200092 kb
Host smart-1fed862a-f36a-4737-a796-692d88564f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343210201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.343210201
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.814520524
Short name T391
Test name
Test status
Simulation time 81993707 ps
CPU time 0.83 seconds
Started Jul 15 05:52:16 PM PDT 24
Finished Jul 15 05:52:17 PM PDT 24
Peak memory 200088 kb
Host smart-c2853ab9-9d1f-445b-8710-5a64076f2460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814520524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.814520524
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1482250327
Short name T273
Test name
Test status
Simulation time 76202884 ps
CPU time 0.88 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:26 PM PDT 24
Peak memory 199844 kb
Host smart-bca7c337-c3ba-4ee5-943b-2a4a422ad715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482250327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1482250327
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3737915452
Short name T502
Test name
Test status
Simulation time 1223507981 ps
CPU time 5.39 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:30 PM PDT 24
Peak memory 221660 kb
Host smart-1dd2a936-f2c8-4940-b470-ec2e8394aeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737915452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3737915452
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.790776359
Short name T444
Test name
Test status
Simulation time 244745564 ps
CPU time 1.01 seconds
Started Jul 15 05:52:22 PM PDT 24
Finished Jul 15 05:52:23 PM PDT 24
Peak memory 217468 kb
Host smart-9cdd3907-8349-47e5-8625-bd2149710f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790776359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.790776359
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.601788570
Short name T529
Test name
Test status
Simulation time 160030632 ps
CPU time 0.85 seconds
Started Jul 15 05:52:17 PM PDT 24
Finished Jul 15 05:52:18 PM PDT 24
Peak memory 199916 kb
Host smart-dd8d5193-071e-4301-ac1d-88f5c0bb4a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601788570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.601788570
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2376800902
Short name T316
Test name
Test status
Simulation time 1734247249 ps
CPU time 6.72 seconds
Started Jul 15 05:52:16 PM PDT 24
Finished Jul 15 05:52:24 PM PDT 24
Peak memory 200348 kb
Host smart-dabf24d5-576c-46b0-a29d-0ed9a4f65f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376800902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2376800902
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.441730932
Short name T118
Test name
Test status
Simulation time 100493969 ps
CPU time 1.01 seconds
Started Jul 15 05:52:18 PM PDT 24
Finished Jul 15 05:52:19 PM PDT 24
Peak memory 200092 kb
Host smart-3debd493-1b1e-40b0-a053-f45cc0372a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441730932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.441730932
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.86312740
Short name T128
Test name
Test status
Simulation time 251076519 ps
CPU time 1.53 seconds
Started Jul 15 05:52:16 PM PDT 24
Finished Jul 15 05:52:18 PM PDT 24
Peak memory 200280 kb
Host smart-da4c81e6-c2ac-4409-8d22-cd7efdedc490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86312740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.86312740
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.830800134
Short name T504
Test name
Test status
Simulation time 124609310 ps
CPU time 0.98 seconds
Started Jul 15 05:52:27 PM PDT 24
Finished Jul 15 05:52:28 PM PDT 24
Peak memory 199900 kb
Host smart-6a36c2a3-6a23-4f58-84f6-178e5b16f62c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830800134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.830800134
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3246430619
Short name T312
Test name
Test status
Simulation time 123165358 ps
CPU time 1.6 seconds
Started Jul 15 05:52:15 PM PDT 24
Finished Jul 15 05:52:17 PM PDT 24
Peak memory 208264 kb
Host smart-cc93ac1e-1d1f-4d96-ac76-9c84db805a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246430619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3246430619
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3763942513
Short name T513
Test name
Test status
Simulation time 90536672 ps
CPU time 0.86 seconds
Started Jul 15 05:52:16 PM PDT 24
Finished Jul 15 05:52:17 PM PDT 24
Peak memory 200052 kb
Host smart-c429632e-8b2c-4a31-ad74-f1cf5e25ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763942513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3763942513
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3269797058
Short name T287
Test name
Test status
Simulation time 90572079 ps
CPU time 0.81 seconds
Started Jul 15 05:52:22 PM PDT 24
Finished Jul 15 05:52:23 PM PDT 24
Peak memory 199740 kb
Host smart-40ebf32a-3e90-4e6d-bf90-e5955475b61a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269797058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3269797058
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.221826983
Short name T280
Test name
Test status
Simulation time 1220413989 ps
CPU time 6.01 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:31 PM PDT 24
Peak memory 217704 kb
Host smart-efddf7d3-35b6-4dc5-923c-99255a270dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221826983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.221826983
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2128988147
Short name T286
Test name
Test status
Simulation time 243319041 ps
CPU time 1.2 seconds
Started Jul 15 05:52:25 PM PDT 24
Finished Jul 15 05:52:27 PM PDT 24
Peak memory 217492 kb
Host smart-ea6a51be-3202-43de-8756-dff25a5c3c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128988147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2128988147
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2874375531
Short name T234
Test name
Test status
Simulation time 196873329 ps
CPU time 0.93 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:26 PM PDT 24
Peak memory 199836 kb
Host smart-f5e3bb35-68ef-4393-b277-059d50a2d37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874375531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2874375531
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3886336254
Short name T98
Test name
Test status
Simulation time 883619597 ps
CPU time 4.48 seconds
Started Jul 15 05:52:23 PM PDT 24
Finished Jul 15 05:52:28 PM PDT 24
Peak memory 200264 kb
Host smart-fec278e9-b43c-4e70-ba20-e059c54609bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886336254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3886336254
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3386101777
Short name T148
Test name
Test status
Simulation time 111612400 ps
CPU time 1.05 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:26 PM PDT 24
Peak memory 200104 kb
Host smart-f2617d06-6567-4c33-a789-ce388bdfa179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386101777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3386101777
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4222340360
Short name T6
Test name
Test status
Simulation time 125491926 ps
CPU time 1.23 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:26 PM PDT 24
Peak memory 200324 kb
Host smart-642b332b-255b-4a1d-abb9-2a3afbf6f050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222340360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4222340360
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2618099521
Short name T86
Test name
Test status
Simulation time 6961802837 ps
CPU time 31.96 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:56 PM PDT 24
Peak memory 208512 kb
Host smart-73d12614-29d0-497e-907e-8eaadf4e7a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618099521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2618099521
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3674450612
Short name T371
Test name
Test status
Simulation time 127905774 ps
CPU time 1.58 seconds
Started Jul 15 05:52:26 PM PDT 24
Finished Jul 15 05:52:28 PM PDT 24
Peak memory 208268 kb
Host smart-06d5f7f5-4d20-4169-8dd8-9d0d1d9226c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674450612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3674450612
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1989378270
Short name T126
Test name
Test status
Simulation time 110912784 ps
CPU time 0.89 seconds
Started Jul 15 05:52:23 PM PDT 24
Finished Jul 15 05:52:25 PM PDT 24
Peak memory 200112 kb
Host smart-796d2cfa-39b5-42e2-9f3a-285e95426783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989378270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1989378270
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1289400237
Short name T187
Test name
Test status
Simulation time 56032456 ps
CPU time 0.77 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:25 PM PDT 24
Peak memory 199868 kb
Host smart-320c13a1-e194-4688-b790-8d93db2ccd6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289400237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1289400237
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1142010940
Short name T433
Test name
Test status
Simulation time 1899709823 ps
CPU time 7.26 seconds
Started Jul 15 05:52:23 PM PDT 24
Finished Jul 15 05:52:31 PM PDT 24
Peak memory 217736 kb
Host smart-f814971a-8c4c-41ff-adc8-4e3031f4f385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142010940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1142010940
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4169353558
Short name T281
Test name
Test status
Simulation time 243951999 ps
CPU time 1.14 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:26 PM PDT 24
Peak memory 217472 kb
Host smart-2ae00b0b-4938-42a7-9ad0-77f5cba97998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169353558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4169353558
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3021522489
Short name T437
Test name
Test status
Simulation time 122656693 ps
CPU time 0.84 seconds
Started Jul 15 05:52:27 PM PDT 24
Finished Jul 15 05:52:28 PM PDT 24
Peak memory 199932 kb
Host smart-35615ddc-5bee-44ff-9b58-55b9a897b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021522489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3021522489
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1934981076
Short name T463
Test name
Test status
Simulation time 881279834 ps
CPU time 4.51 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:30 PM PDT 24
Peak memory 200392 kb
Host smart-5778b105-8d1a-4be5-a79a-9f1bb50283ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934981076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1934981076
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2204743851
Short name T156
Test name
Test status
Simulation time 110198154 ps
CPU time 1.1 seconds
Started Jul 15 05:52:24 PM PDT 24
Finished Jul 15 05:52:25 PM PDT 24
Peak memory 200064 kb
Host smart-815fe427-ebab-407c-b689-a5ddb6d7ede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204743851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2204743851
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1342698048
Short name T423
Test name
Test status
Simulation time 255275724 ps
CPU time 1.54 seconds
Started Jul 15 05:52:25 PM PDT 24
Finished Jul 15 05:52:27 PM PDT 24
Peak memory 200272 kb
Host smart-2bff39f1-aa72-439d-8b55-f444a1070ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342698048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1342698048
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3130239137
Short name T296
Test name
Test status
Simulation time 5164158086 ps
CPU time 18.62 seconds
Started Jul 15 05:52:25 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 200404 kb
Host smart-8580c718-8bb6-4ed2-8dec-56256faa8053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130239137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3130239137
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1840533080
Short name T390
Test name
Test status
Simulation time 130577756 ps
CPU time 1.88 seconds
Started Jul 15 05:52:26 PM PDT 24
Finished Jul 15 05:52:29 PM PDT 24
Peak memory 208292 kb
Host smart-5cb2157b-b775-4e93-ad63-9482384f68c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840533080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1840533080
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.100587442
Short name T121
Test name
Test status
Simulation time 153737137 ps
CPU time 1.3 seconds
Started Jul 15 05:52:23 PM PDT 24
Finished Jul 15 05:52:25 PM PDT 24
Peak memory 200320 kb
Host smart-4535cbfa-360b-45ff-97fe-0f83aafc13e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100587442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.100587442
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2995560155
Short name T508
Test name
Test status
Simulation time 1230542058 ps
CPU time 5.33 seconds
Started Jul 15 05:52:34 PM PDT 24
Finished Jul 15 05:52:41 PM PDT 24
Peak memory 217528 kb
Host smart-d60787a1-59fe-4493-b03e-29f995980611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995560155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2995560155
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1642813981
Short name T436
Test name
Test status
Simulation time 243781619 ps
CPU time 1.17 seconds
Started Jul 15 05:52:31 PM PDT 24
Finished Jul 15 05:52:33 PM PDT 24
Peak memory 217456 kb
Host smart-b810ca88-15de-4258-8cd3-134140a4135e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642813981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1642813981
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2873883726
Short name T511
Test name
Test status
Simulation time 205457827 ps
CPU time 0.92 seconds
Started Jul 15 05:52:26 PM PDT 24
Finished Jul 15 05:52:28 PM PDT 24
Peak memory 199932 kb
Host smart-3c2fdb28-59cf-47b2-a5ce-00f16910d553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873883726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2873883726
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2045137522
Short name T282
Test name
Test status
Simulation time 1633207053 ps
CPU time 6.27 seconds
Started Jul 15 05:52:27 PM PDT 24
Finished Jul 15 05:52:34 PM PDT 24
Peak memory 200384 kb
Host smart-1a47d0b4-4fb0-490b-bd54-3a0e3f2aedb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045137522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2045137522
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3436630504
Short name T413
Test name
Test status
Simulation time 140315383 ps
CPU time 1.08 seconds
Started Jul 15 05:52:34 PM PDT 24
Finished Jul 15 05:52:37 PM PDT 24
Peak memory 200000 kb
Host smart-e792b223-0877-496f-9b3f-b4f623c24478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436630504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3436630504
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.621199596
Short name T290
Test name
Test status
Simulation time 117450499 ps
CPU time 1.15 seconds
Started Jul 15 05:52:25 PM PDT 24
Finished Jul 15 05:52:27 PM PDT 24
Peak memory 200300 kb
Host smart-740b65b1-d433-4647-a11e-020b3757e210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621199596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.621199596
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3976816440
Short name T542
Test name
Test status
Simulation time 136776952 ps
CPU time 1.84 seconds
Started Jul 15 05:52:30 PM PDT 24
Finished Jul 15 05:52:33 PM PDT 24
Peak memory 200100 kb
Host smart-89693999-6ea6-4320-8b28-967d14d58b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976816440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3976816440
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3176870221
Short name T420
Test name
Test status
Simulation time 108994161 ps
CPU time 0.97 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:36 PM PDT 24
Peak memory 200080 kb
Host smart-b1051b1d-7e21-447a-b6ca-4c0d4afb5c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176870221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3176870221
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2658021244
Short name T370
Test name
Test status
Simulation time 59661827 ps
CPU time 0.77 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:36 PM PDT 24
Peak memory 199876 kb
Host smart-8dabcc4e-11bf-437b-a0d6-2fc19224c605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658021244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2658021244
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1395472554
Short name T49
Test name
Test status
Simulation time 2193710284 ps
CPU time 8.25 seconds
Started Jul 15 05:52:34 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 217780 kb
Host smart-e1a8d19d-5815-403c-aaf6-e7a297ea96e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395472554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1395472554
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.4085885392
Short name T521
Test name
Test status
Simulation time 243443132 ps
CPU time 1.09 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:36 PM PDT 24
Peak memory 217468 kb
Host smart-9cfa3e22-d088-4da9-8f3f-ba7c838883c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085885392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.4085885392
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1162374943
Short name T207
Test name
Test status
Simulation time 188203815 ps
CPU time 0.97 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 199916 kb
Host smart-b43608ad-436d-403b-a107-65e5cb8f2d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162374943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1162374943
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1016222613
Short name T90
Test name
Test status
Simulation time 792909806 ps
CPU time 4.25 seconds
Started Jul 15 05:52:35 PM PDT 24
Finished Jul 15 05:52:40 PM PDT 24
Peak memory 200360 kb
Host smart-5976c7ab-0cad-4f5e-b541-61248a9162ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016222613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1016222613
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3535188756
Short name T131
Test name
Test status
Simulation time 178488425 ps
CPU time 1.32 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:36 PM PDT 24
Peak memory 200092 kb
Host smart-d95a385d-a64e-4f6d-b6b3-b0af41bcb545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535188756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3535188756
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.991868546
Short name T149
Test name
Test status
Simulation time 109773041 ps
CPU time 1.19 seconds
Started Jul 15 05:52:34 PM PDT 24
Finished Jul 15 05:52:37 PM PDT 24
Peak memory 199900 kb
Host smart-9781ea84-eee4-4ba4-9b54-e9e1345a2664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991868546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.991868546
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1227540278
Short name T42
Test name
Test status
Simulation time 11022152120 ps
CPU time 40.98 seconds
Started Jul 15 05:52:31 PM PDT 24
Finished Jul 15 05:53:13 PM PDT 24
Peak memory 208636 kb
Host smart-07614241-f1f0-46aa-a8d5-994ee7c566be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227540278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1227540278
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.119039101
Short name T395
Test name
Test status
Simulation time 288951126 ps
CPU time 1.96 seconds
Started Jul 15 05:52:30 PM PDT 24
Finished Jul 15 05:52:33 PM PDT 24
Peak memory 208296 kb
Host smart-97786825-a18b-4a93-b566-10798bb5438c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119039101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.119039101
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2420635130
Short name T262
Test name
Test status
Simulation time 172749235 ps
CPU time 1.37 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 200312 kb
Host smart-783d8206-1cc0-44ed-9f52-057c72b268a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420635130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2420635130
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3735757878
Short name T488
Test name
Test status
Simulation time 78815782 ps
CPU time 0.82 seconds
Started Jul 15 05:52:30 PM PDT 24
Finished Jul 15 05:52:32 PM PDT 24
Peak memory 199908 kb
Host smart-de6f17bf-5193-4c43-bf59-e7b135308712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735757878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3735757878
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.178551134
Short name T37
Test name
Test status
Simulation time 1903467914 ps
CPU time 7.11 seconds
Started Jul 15 05:52:37 PM PDT 24
Finished Jul 15 05:52:45 PM PDT 24
Peak memory 217900 kb
Host smart-8b6c2d91-99bc-49a0-ac31-272671fb3e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178551134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.178551134
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1746383928
Short name T360
Test name
Test status
Simulation time 243915950 ps
CPU time 1.17 seconds
Started Jul 15 05:52:34 PM PDT 24
Finished Jul 15 05:52:37 PM PDT 24
Peak memory 217456 kb
Host smart-c3872f41-274a-4be3-a80c-cb93213ae981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746383928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1746383928
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.902811858
Short name T493
Test name
Test status
Simulation time 136649982 ps
CPU time 0.83 seconds
Started Jul 15 05:52:31 PM PDT 24
Finished Jul 15 05:52:32 PM PDT 24
Peak memory 199876 kb
Host smart-301786d4-e520-4642-904c-06f2360aae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902811858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.902811858
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1070833080
Short name T12
Test name
Test status
Simulation time 1390915263 ps
CPU time 5.8 seconds
Started Jul 15 05:52:31 PM PDT 24
Finished Jul 15 05:52:38 PM PDT 24
Peak memory 200296 kb
Host smart-577a493e-fd18-462f-8258-d3f8c4b09ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070833080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1070833080
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1027471015
Short name T421
Test name
Test status
Simulation time 112820406 ps
CPU time 1.04 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:34 PM PDT 24
Peak memory 200104 kb
Host smart-517037e6-bba3-4d2e-a714-0a3ae8b9c233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027471015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1027471015
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1091736848
Short name T476
Test name
Test status
Simulation time 121869699 ps
CPU time 1.21 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:36 PM PDT 24
Peak memory 200256 kb
Host smart-80d665f5-309b-4c0e-85b2-22f723019877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091736848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1091736848
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1532453439
Short name T510
Test name
Test status
Simulation time 333247391 ps
CPU time 1.87 seconds
Started Jul 15 05:52:34 PM PDT 24
Finished Jul 15 05:52:37 PM PDT 24
Peak memory 199924 kb
Host smart-21095e9f-b8d8-4e0f-ae59-21c6922c7061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532453439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1532453439
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2620629820
Short name T456
Test name
Test status
Simulation time 281242165 ps
CPU time 2.05 seconds
Started Jul 15 05:52:34 PM PDT 24
Finished Jul 15 05:52:38 PM PDT 24
Peak memory 200096 kb
Host smart-30257ba1-ed51-46f6-a77a-9cf3055c4af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620629820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2620629820
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3517531896
Short name T173
Test name
Test status
Simulation time 122064730 ps
CPU time 0.97 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 200068 kb
Host smart-e094c393-96c9-449c-b3d1-d301bb361db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517531896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3517531896
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3367028003
Short name T349
Test name
Test status
Simulation time 73781087 ps
CPU time 0.8 seconds
Started Jul 15 05:52:35 PM PDT 24
Finished Jul 15 05:52:37 PM PDT 24
Peak memory 199880 kb
Host smart-59c1df11-b00a-4c2e-89d4-95756ff4d121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367028003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3367028003
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3764294682
Short name T252
Test name
Test status
Simulation time 245081645 ps
CPU time 1.1 seconds
Started Jul 15 05:52:31 PM PDT 24
Finished Jul 15 05:52:33 PM PDT 24
Peak memory 217372 kb
Host smart-398cc307-4c8c-46f3-b16c-822adc023859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764294682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3764294682
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1949677608
Short name T24
Test name
Test status
Simulation time 131535418 ps
CPU time 0.81 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 199936 kb
Host smart-9ae4e4db-8a4f-4ede-854c-2cd397afe959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949677608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1949677608
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.489012841
Short name T429
Test name
Test status
Simulation time 2038829170 ps
CPU time 7.54 seconds
Started Jul 15 05:52:31 PM PDT 24
Finished Jul 15 05:52:40 PM PDT 24
Peak memory 200360 kb
Host smart-190d10c3-97bd-4412-95d1-a73c3160c751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489012841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.489012841
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1109176342
Short name T123
Test name
Test status
Simulation time 149944778 ps
CPU time 1.18 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 200072 kb
Host smart-5c957c93-7ef8-4e23-9500-71819deae23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109176342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1109176342
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2285501727
Short name T432
Test name
Test status
Simulation time 249698551 ps
CPU time 1.56 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:36 PM PDT 24
Peak memory 200328 kb
Host smart-ca80deb5-590b-4785-b626-a154adb43014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285501727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2285501727
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3654443298
Short name T532
Test name
Test status
Simulation time 9308098557 ps
CPU time 32 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:53:05 PM PDT 24
Peak memory 200452 kb
Host smart-861d3009-483b-4f65-9362-9bc39a60bed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654443298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3654443298
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.20406662
Short name T406
Test name
Test status
Simulation time 117942396 ps
CPU time 1.52 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 200056 kb
Host smart-9bff064a-f8f8-4468-a198-2d3aca7893e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20406662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.20406662
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2650494767
Short name T301
Test name
Test status
Simulation time 79165463 ps
CPU time 0.78 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:34 PM PDT 24
Peak memory 200108 kb
Host smart-4a271d02-c668-4dab-a5e6-7348b2e749c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650494767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2650494767
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.475779314
Short name T320
Test name
Test status
Simulation time 69413178 ps
CPU time 0.8 seconds
Started Jul 15 05:51:44 PM PDT 24
Finished Jul 15 05:51:46 PM PDT 24
Peak memory 199896 kb
Host smart-86e066e5-5103-487f-b2b1-97f82f592c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475779314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.475779314
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2358167961
Short name T5
Test name
Test status
Simulation time 1227091047 ps
CPU time 5.41 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:56 PM PDT 24
Peak memory 217612 kb
Host smart-9577dd6b-ec4b-445c-baf1-df52c715a756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358167961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2358167961
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1196828680
Short name T186
Test name
Test status
Simulation time 244362712 ps
CPU time 1.15 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:51:47 PM PDT 24
Peak memory 217448 kb
Host smart-3e9181a6-6e46-4b4b-bd20-cd0293c97cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196828680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1196828680
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.474700332
Short name T20
Test name
Test status
Simulation time 118071815 ps
CPU time 0.83 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:31 PM PDT 24
Peak memory 199876 kb
Host smart-9017e623-9cbe-456d-9db9-1f787a3ef245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474700332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.474700332
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3292282859
Short name T366
Test name
Test status
Simulation time 1987959420 ps
CPU time 8.08 seconds
Started Jul 15 05:51:32 PM PDT 24
Finished Jul 15 05:51:41 PM PDT 24
Peak memory 200348 kb
Host smart-ec709aa2-c91a-49f5-9d34-9f2d291bd751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292282859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3292282859
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1264698605
Short name T381
Test name
Test status
Simulation time 248447022 ps
CPU time 1.52 seconds
Started Jul 15 05:51:30 PM PDT 24
Finished Jul 15 05:51:32 PM PDT 24
Peak memory 200312 kb
Host smart-4cc0b6ce-1ca4-4373-bed8-c56a43b8f465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264698605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1264698605
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2047754236
Short name T91
Test name
Test status
Simulation time 4966534688 ps
CPU time 16.28 seconds
Started Jul 15 05:51:44 PM PDT 24
Finished Jul 15 05:52:02 PM PDT 24
Peak memory 200428 kb
Host smart-a5af3421-cd14-40bb-876b-733c3a7302f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047754236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2047754236
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.744551031
Short name T315
Test name
Test status
Simulation time 370117108 ps
CPU time 2.31 seconds
Started Jul 15 05:51:29 PM PDT 24
Finished Jul 15 05:51:32 PM PDT 24
Peak memory 208204 kb
Host smart-ce97a1a8-8653-450c-abef-770be79504ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744551031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.744551031
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3032066824
Short name T124
Test name
Test status
Simulation time 262910612 ps
CPU time 1.5 seconds
Started Jul 15 05:51:31 PM PDT 24
Finished Jul 15 05:51:33 PM PDT 24
Peak memory 200112 kb
Host smart-593988e8-b316-4750-9ab4-854368be7af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032066824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3032066824
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.434271445
Short name T336
Test name
Test status
Simulation time 74406151 ps
CPU time 0.91 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 199912 kb
Host smart-0f1d0202-f588-4ae2-a986-7b43b4dbfb22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434271445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.434271445
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.617513243
Short name T464
Test name
Test status
Simulation time 1219418609 ps
CPU time 5.43 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:39 PM PDT 24
Peak memory 221628 kb
Host smart-10868e6d-1f5c-4bfc-afc9-8844627264a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617513243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.617513243
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1709181974
Short name T507
Test name
Test status
Simulation time 244582466 ps
CPU time 1.12 seconds
Started Jul 15 05:52:34 PM PDT 24
Finished Jul 15 05:52:37 PM PDT 24
Peak memory 217464 kb
Host smart-5595ebcf-9ac8-4b05-baa4-da479e651365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709181974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1709181974
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.826022202
Short name T213
Test name
Test status
Simulation time 117027622 ps
CPU time 0.83 seconds
Started Jul 15 05:52:35 PM PDT 24
Finished Jul 15 05:52:37 PM PDT 24
Peak memory 199868 kb
Host smart-c0f17963-b22b-49fc-83d4-98a2ddb50397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826022202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.826022202
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.4108697695
Short name T342
Test name
Test status
Simulation time 1616498541 ps
CPU time 6.43 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:41 PM PDT 24
Peak memory 200224 kb
Host smart-8a151b19-85dd-4557-b091-b5ed30951033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108697695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4108697695
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1349917060
Short name T188
Test name
Test status
Simulation time 150024712 ps
CPU time 1.13 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 200092 kb
Host smart-69bf9f06-2b7f-48b8-b897-0aa2ac51e2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349917060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1349917060
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.273686531
Short name T533
Test name
Test status
Simulation time 121745079 ps
CPU time 1.17 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 200284 kb
Host smart-59b04be1-70dd-4f11-862e-9163c8341aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273686531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.273686531
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2641400396
Short name T487
Test name
Test status
Simulation time 13208308826 ps
CPU time 48.85 seconds
Started Jul 15 05:52:31 PM PDT 24
Finished Jul 15 05:53:21 PM PDT 24
Peak memory 208560 kb
Host smart-0a50305b-e99d-4a58-9b57-b1e78a4f3de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641400396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2641400396
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.858360718
Short name T129
Test name
Test status
Simulation time 498487917 ps
CPU time 2.7 seconds
Started Jul 15 05:52:31 PM PDT 24
Finished Jul 15 05:52:35 PM PDT 24
Peak memory 200104 kb
Host smart-5af4479a-7273-45f4-9e9b-ac9880f6c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858360718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.858360718
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1080611124
Short name T539
Test name
Test status
Simulation time 131231071 ps
CPU time 1.15 seconds
Started Jul 15 05:52:37 PM PDT 24
Finished Jul 15 05:52:39 PM PDT 24
Peak memory 200260 kb
Host smart-f8441307-43b8-4f6a-94b0-34d5e9f3d02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080611124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1080611124
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3413173724
Short name T142
Test name
Test status
Simulation time 75441878 ps
CPU time 0.81 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 199872 kb
Host smart-dcdab197-3024-4a1f-84ea-2cfd5c931a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413173724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3413173724
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3595753573
Short name T27
Test name
Test status
Simulation time 1895876352 ps
CPU time 7.7 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:41 PM PDT 24
Peak memory 221600 kb
Host smart-d00c125c-e57d-4b53-a824-c39e94734c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595753573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3595753573
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3158551923
Short name T398
Test name
Test status
Simulation time 244247464 ps
CPU time 1.02 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:34 PM PDT 24
Peak memory 217456 kb
Host smart-b015e81b-cd5b-4fc3-a20d-394eb73b9a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158551923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3158551923
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3561320280
Short name T255
Test name
Test status
Simulation time 242287751 ps
CPU time 0.99 seconds
Started Jul 15 05:52:35 PM PDT 24
Finished Jul 15 05:52:37 PM PDT 24
Peak memory 199880 kb
Host smart-9c4b9cd0-d58a-4507-9935-6ecf1b4d4daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561320280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3561320280
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3109912048
Short name T374
Test name
Test status
Simulation time 1397504988 ps
CPU time 5.46 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:40 PM PDT 24
Peak memory 200240 kb
Host smart-a76d0bb9-110f-494b-9ca5-04ba39c50ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109912048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3109912048
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2525143880
Short name T274
Test name
Test status
Simulation time 96486347 ps
CPU time 1 seconds
Started Jul 15 05:52:36 PM PDT 24
Finished Jul 15 05:52:37 PM PDT 24
Peak memory 200072 kb
Host smart-7b2d4d75-9d38-43ec-ba86-6e8d8538af21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525143880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2525143880
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1971444561
Short name T517
Test name
Test status
Simulation time 118818837 ps
CPU time 1.23 seconds
Started Jul 15 05:52:33 PM PDT 24
Finished Jul 15 05:52:36 PM PDT 24
Peak memory 200244 kb
Host smart-b7dc347b-c2d2-4c7d-b62f-566a74c39aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971444561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1971444561
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.298297184
Short name T489
Test name
Test status
Simulation time 1698552074 ps
CPU time 8.6 seconds
Started Jul 15 05:52:38 PM PDT 24
Finished Jul 15 05:52:47 PM PDT 24
Peak memory 209876 kb
Host smart-f7933946-ae98-437c-acf1-ebd434b393dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298297184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.298297184
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1602467803
Short name T162
Test name
Test status
Simulation time 322577940 ps
CPU time 2.2 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:36 PM PDT 24
Peak memory 200060 kb
Host smart-0485ff9e-e439-45f0-9628-0ccc6b83f4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602467803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1602467803
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.363622472
Short name T166
Test name
Test status
Simulation time 129483826 ps
CPU time 1.08 seconds
Started Jul 15 05:52:32 PM PDT 24
Finished Jul 15 05:52:34 PM PDT 24
Peak memory 200108 kb
Host smart-81b0783b-c6a3-40f0-b71d-1e011c13417e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363622472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.363622472
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3850360194
Short name T266
Test name
Test status
Simulation time 69162836 ps
CPU time 0.77 seconds
Started Jul 15 05:52:44 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 199844 kb
Host smart-9782bf44-44f1-42db-b7b7-0aa6d54a1608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850360194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3850360194
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1454472448
Short name T34
Test name
Test status
Simulation time 2355883631 ps
CPU time 8.76 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:51 PM PDT 24
Peak memory 217860 kb
Host smart-616939d0-2734-4c14-a659-0245cf71a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454472448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1454472448
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1638600525
Short name T227
Test name
Test status
Simulation time 244286192 ps
CPU time 1.12 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 217456 kb
Host smart-a2019cef-08a5-4dce-9b03-2de84ad4598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638600525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1638600525
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3446729862
Short name T223
Test name
Test status
Simulation time 143938882 ps
CPU time 0.87 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 199916 kb
Host smart-0b35f7a0-8902-4c73-b731-9606922bddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446729862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3446729862
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.831837284
Short name T361
Test name
Test status
Simulation time 902906505 ps
CPU time 4.8 seconds
Started Jul 15 05:52:39 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 200252 kb
Host smart-592f653b-eb79-4dbb-84c6-10178d1c83ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831837284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.831837284
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.979436747
Short name T311
Test name
Test status
Simulation time 169742080 ps
CPU time 1.3 seconds
Started Jul 15 05:52:40 PM PDT 24
Finished Jul 15 05:52:42 PM PDT 24
Peak memory 200040 kb
Host smart-403af5ee-7ad2-49f8-b543-b4531f775bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979436747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.979436747
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1695747043
Short name T386
Test name
Test status
Simulation time 246121999 ps
CPU time 1.43 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 200308 kb
Host smart-ba7ea80f-058b-46ab-acdc-74d1dd4fde38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695747043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1695747043
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3204054438
Short name T329
Test name
Test status
Simulation time 514780044 ps
CPU time 2.92 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:52:48 PM PDT 24
Peak memory 200284 kb
Host smart-d7f61c32-aa38-4ad4-95aa-05d3d41ecbe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204054438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3204054438
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.158072056
Short name T409
Test name
Test status
Simulation time 144661280 ps
CPU time 1.73 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 200092 kb
Host smart-aa3f04f5-b975-448c-a163-a847c2898703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158072056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.158072056
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.547218554
Short name T235
Test name
Test status
Simulation time 107911796 ps
CPU time 0.94 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 200112 kb
Host smart-cdbe86dd-b096-456c-9b6a-0476542eaf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547218554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.547218554
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1360837556
Short name T160
Test name
Test status
Simulation time 82576617 ps
CPU time 0.84 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 199912 kb
Host smart-9024f153-ed84-47bf-ad43-359244eac9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360837556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1360837556
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.4124319182
Short name T271
Test name
Test status
Simulation time 1877047581 ps
CPU time 6.8 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 217468 kb
Host smart-c97de234-5660-4007-b516-72f1abdcd633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124319182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.4124319182
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3876756611
Short name T309
Test name
Test status
Simulation time 244484513 ps
CPU time 1.09 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 217464 kb
Host smart-ab7a63f1-db16-46c3-b9d5-e5b5bf4af2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876756611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3876756611
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2769153146
Short name T496
Test name
Test status
Simulation time 184442214 ps
CPU time 0.89 seconds
Started Jul 15 05:52:40 PM PDT 24
Finished Jul 15 05:52:41 PM PDT 24
Peak memory 199892 kb
Host smart-027613c1-d076-4875-aa6f-d0cc9b44d576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769153146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2769153146
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2437246340
Short name T110
Test name
Test status
Simulation time 1496454580 ps
CPU time 5.83 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:50 PM PDT 24
Peak memory 200364 kb
Host smart-0a4f8399-a646-4e12-a07c-abb496d2a68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437246340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2437246340
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2478572000
Short name T319
Test name
Test status
Simulation time 155157911 ps
CPU time 1.16 seconds
Started Jul 15 05:52:40 PM PDT 24
Finished Jul 15 05:52:42 PM PDT 24
Peak memory 199992 kb
Host smart-313de87d-6650-4710-af60-f6261e680285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478572000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2478572000
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1170842682
Short name T202
Test name
Test status
Simulation time 123772538 ps
CPU time 1.23 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:45 PM PDT 24
Peak memory 200324 kb
Host smart-6a08b42d-9a1f-4536-ad3a-8c9884c6d31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170842682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1170842682
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2710750986
Short name T220
Test name
Test status
Simulation time 2247595728 ps
CPU time 9.91 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 208580 kb
Host smart-1b618467-b500-4b99-b5ee-7f1322e6f6b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710750986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2710750986
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.588768906
Short name T467
Test name
Test status
Simulation time 119859995 ps
CPU time 1.6 seconds
Started Jul 15 05:52:40 PM PDT 24
Finished Jul 15 05:52:42 PM PDT 24
Peak memory 208284 kb
Host smart-00d49915-889e-4975-8b4b-d87da7961c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588768906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.588768906
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2510858475
Short name T265
Test name
Test status
Simulation time 184703600 ps
CPU time 1.18 seconds
Started Jul 15 05:52:40 PM PDT 24
Finished Jul 15 05:52:43 PM PDT 24
Peak memory 200116 kb
Host smart-843da161-4612-46c5-b3a1-b8d598dc760c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510858475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2510858475
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1975596436
Short name T9
Test name
Test status
Simulation time 71786087 ps
CPU time 0.8 seconds
Started Jul 15 05:52:44 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 199864 kb
Host smart-3d02833b-eb37-4cdd-a85b-7467742fe41f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975596436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1975596436
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1174688006
Short name T36
Test name
Test status
Simulation time 1229121638 ps
CPU time 5.66 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:50 PM PDT 24
Peak memory 217732 kb
Host smart-b73c178f-e857-47bd-8506-8d7328445620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174688006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1174688006
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.274503885
Short name T163
Test name
Test status
Simulation time 244618923 ps
CPU time 1.14 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:43 PM PDT 24
Peak memory 217344 kb
Host smart-a4af06bf-5460-46eb-8f0e-b11524d0eb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274503885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.274503885
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3956874765
Short name T261
Test name
Test status
Simulation time 139774519 ps
CPU time 0.85 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:43 PM PDT 24
Peak memory 199856 kb
Host smart-3c9b6069-fbb1-4289-8317-54ac613d8be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956874765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3956874765
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2522625215
Short name T198
Test name
Test status
Simulation time 1711418405 ps
CPU time 6.91 seconds
Started Jul 15 05:52:44 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 200328 kb
Host smart-d051e7be-bb84-4b0a-85ff-f6094769fe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522625215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2522625215
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1769671738
Short name T522
Test name
Test status
Simulation time 108414719 ps
CPU time 1.01 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:45 PM PDT 24
Peak memory 200040 kb
Host smart-cae7f654-b04a-4f70-820d-f7858aa973eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769671738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1769671738
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3838715315
Short name T468
Test name
Test status
Simulation time 227863737 ps
CPU time 1.4 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 200232 kb
Host smart-b7e52ce2-ea87-4d46-9b1c-ca43878198a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838715315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3838715315
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.310982075
Short name T246
Test name
Test status
Simulation time 2227718637 ps
CPU time 8.62 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:51 PM PDT 24
Peak memory 200368 kb
Host smart-5d40866f-d618-4b4a-98d9-59799ba80c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310982075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.310982075
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3066162302
Short name T338
Test name
Test status
Simulation time 336290264 ps
CPU time 2.18 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 208320 kb
Host smart-18f0b6ad-fa74-4edc-9a1a-791a8c222b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066162302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3066162302
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.970322265
Short name T268
Test name
Test status
Simulation time 81283338 ps
CPU time 0.85 seconds
Started Jul 15 05:52:40 PM PDT 24
Finished Jul 15 05:52:42 PM PDT 24
Peak memory 200068 kb
Host smart-f75d12f2-5a9e-43a8-8b0e-17f743dc8345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970322265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.970322265
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3772244531
Short name T150
Test name
Test status
Simulation time 62403886 ps
CPU time 0.72 seconds
Started Jul 15 05:52:44 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 199912 kb
Host smart-6b5517ad-5413-414a-84ee-cd9e714c591e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772244531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3772244531
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2267031902
Short name T51
Test name
Test status
Simulation time 1884967586 ps
CPU time 7.29 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:49 PM PDT 24
Peak memory 217684 kb
Host smart-9102dd3b-064c-410f-bcea-234def89bbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267031902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2267031902
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4021859543
Short name T1
Test name
Test status
Simulation time 244746799 ps
CPU time 1.12 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 217428 kb
Host smart-166b1fd8-d5fa-4cbd-aceb-bdce90a4c550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021859543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4021859543
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2961186548
Short name T275
Test name
Test status
Simulation time 185911755 ps
CPU time 0.85 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 199892 kb
Host smart-901a994c-7054-4647-9b88-fbed415d3bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961186548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2961186548
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2316659582
Short name T184
Test name
Test status
Simulation time 1559254462 ps
CPU time 6.76 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:51 PM PDT 24
Peak memory 200376 kb
Host smart-4e87f3ac-9f54-40d5-9f52-4bb41555ddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316659582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2316659582
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1407138721
Short name T44
Test name
Test status
Simulation time 173398187 ps
CPU time 1.23 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 200068 kb
Host smart-045c7657-4afa-4bfe-b80e-321189bc5540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407138721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1407138721
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1819420835
Short name T237
Test name
Test status
Simulation time 247199816 ps
CPU time 1.48 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:43 PM PDT 24
Peak memory 200232 kb
Host smart-2a0988ee-bc03-4fa3-b0a7-c65d4d5cb9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819420835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1819420835
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.48139527
Short name T403
Test name
Test status
Simulation time 3702526949 ps
CPU time 14.22 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:58 PM PDT 24
Peak memory 208532 kb
Host smart-0adde4bd-8f92-4efa-9f1e-c44d745a3844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48139527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.48139527
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1001933332
Short name T267
Test name
Test status
Simulation time 112957581 ps
CPU time 1.52 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 200100 kb
Host smart-2d9a25fa-9721-408e-9453-fd34c20f495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001933332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1001933332
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.943492446
Short name T451
Test name
Test status
Simulation time 64690398 ps
CPU time 0.78 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 200108 kb
Host smart-530516e3-3395-410e-8d36-eacdbb27e604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943492446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.943492446
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2176667514
Short name T416
Test name
Test status
Simulation time 72950625 ps
CPU time 0.8 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:45 PM PDT 24
Peak memory 199916 kb
Host smart-d80b369b-ab7a-4fff-9392-5ae767aaaa27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176667514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2176667514
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.139236642
Short name T372
Test name
Test status
Simulation time 2172795195 ps
CPU time 7.7 seconds
Started Jul 15 05:52:47 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 217704 kb
Host smart-6784309c-0145-4b27-8fad-ef8ddf72eddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139236642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.139236642
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3265727296
Short name T341
Test name
Test status
Simulation time 244081355 ps
CPU time 1.08 seconds
Started Jul 15 05:52:44 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 217452 kb
Host smart-fa89ebac-c84a-4811-a5af-c7c026b0c702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265727296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3265727296
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2277614822
Short name T242
Test name
Test status
Simulation time 84450907 ps
CPU time 0.81 seconds
Started Jul 15 05:52:47 PM PDT 24
Finished Jul 15 05:52:48 PM PDT 24
Peak memory 199764 kb
Host smart-9b11e247-e7b7-4cf9-8bf8-90e25bca15c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277614822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2277614822
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.4006182451
Short name T221
Test name
Test status
Simulation time 1823584684 ps
CPU time 6.65 seconds
Started Jul 15 05:52:44 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 200388 kb
Host smart-51ea8ce5-370d-4d3a-865f-ee8fd147956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006182451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.4006182451
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2230738106
Short name T33
Test name
Test status
Simulation time 111666666 ps
CPU time 1.03 seconds
Started Jul 15 05:52:47 PM PDT 24
Finished Jul 15 05:52:49 PM PDT 24
Peak memory 200088 kb
Host smart-fea2b4a9-14c5-4868-a8da-fb1f18247386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230738106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2230738106
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3197199499
Short name T171
Test name
Test status
Simulation time 192539633 ps
CPU time 1.4 seconds
Started Jul 15 05:52:41 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 200292 kb
Host smart-68c7b32d-28f9-46ae-b83a-68109428d5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197199499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3197199499
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3758734716
Short name T344
Test name
Test status
Simulation time 5147276414 ps
CPU time 18.64 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:53:04 PM PDT 24
Peak memory 200404 kb
Host smart-57573fe0-d727-4c53-a825-40867b51f281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758734716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3758734716
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3052176444
Short name T253
Test name
Test status
Simulation time 280829712 ps
CPU time 1.87 seconds
Started Jul 15 05:52:44 PM PDT 24
Finished Jul 15 05:52:47 PM PDT 24
Peak memory 200136 kb
Host smart-8a69f338-c0eb-4df4-ac7f-3d5bcdf4909e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052176444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3052176444
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.4104508582
Short name T449
Test name
Test status
Simulation time 211824047 ps
CPU time 1.26 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:45 PM PDT 24
Peak memory 200048 kb
Host smart-59b43826-ab58-4960-bbdd-1806025f5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104508582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.4104508582
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2428177926
Short name T503
Test name
Test status
Simulation time 58700953 ps
CPU time 0.74 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:52:57 PM PDT 24
Peak memory 199884 kb
Host smart-69e666f0-3f26-45fd-b3c6-6d5d9b51d88e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428177926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2428177926
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.305821253
Short name T323
Test name
Test status
Simulation time 1888964962 ps
CPU time 8.35 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:53:03 PM PDT 24
Peak memory 221648 kb
Host smart-208349a6-2b68-44ce-9f5b-e6784d47f347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305821253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.305821253
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1626272192
Short name T452
Test name
Test status
Simulation time 243953129 ps
CPU time 1.11 seconds
Started Jul 15 05:52:58 PM PDT 24
Finished Jul 15 05:53:01 PM PDT 24
Peak memory 216740 kb
Host smart-e3bd39b8-c158-49fc-b640-fb908d19428c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626272192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1626272192
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2509310509
Short name T190
Test name
Test status
Simulation time 211275241 ps
CPU time 0.95 seconds
Started Jul 15 05:52:45 PM PDT 24
Finished Jul 15 05:52:47 PM PDT 24
Peak memory 199880 kb
Host smart-cdb1c1ac-c485-402f-b349-1d22d43a37de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509310509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2509310509
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1568741273
Short name T113
Test name
Test status
Simulation time 1749009728 ps
CPU time 6.76 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 200388 kb
Host smart-1c424fca-7de8-4ba3-83e3-899f69ea944b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568741273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1568741273
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1393665538
Short name T216
Test name
Test status
Simulation time 178914962 ps
CPU time 1.19 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 200036 kb
Host smart-0f871905-b96a-4b5e-a226-0a7a5bf79407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393665538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1393665538
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3608173234
Short name T411
Test name
Test status
Simulation time 112870058 ps
CPU time 1.16 seconds
Started Jul 15 05:52:43 PM PDT 24
Finished Jul 15 05:52:46 PM PDT 24
Peak memory 200356 kb
Host smart-70c26c83-058a-4d7e-985e-ebccf111b4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608173234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3608173234
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1971117777
Short name T396
Test name
Test status
Simulation time 8145479238 ps
CPU time 29.83 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:53:26 PM PDT 24
Peak memory 200356 kb
Host smart-87a0fe2a-a7e7-43ac-8a2d-48c44398866c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971117777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1971117777
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1409087102
Short name T214
Test name
Test status
Simulation time 154452841 ps
CPU time 2 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:52:56 PM PDT 24
Peak memory 200036 kb
Host smart-7d27902c-644b-41ea-b9c2-be539540c5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409087102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1409087102
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.206329623
Short name T434
Test name
Test status
Simulation time 120039232 ps
CPU time 0.97 seconds
Started Jul 15 05:52:42 PM PDT 24
Finished Jul 15 05:52:44 PM PDT 24
Peak memory 200072 kb
Host smart-8a67d702-c270-4dc2-931f-8c7e142688f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206329623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.206329623
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.551709551
Short name T352
Test name
Test status
Simulation time 73247150 ps
CPU time 0.84 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 199896 kb
Host smart-897487c4-435f-4b14-aedf-c6612767dcc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551709551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.551709551
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3999983622
Short name T303
Test name
Test status
Simulation time 1228198024 ps
CPU time 5.84 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 217220 kb
Host smart-cc7ea46a-3b8b-4258-9bca-82db09e04874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999983622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3999983622
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2300544745
Short name T165
Test name
Test status
Simulation time 244608741 ps
CPU time 1.17 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:52:56 PM PDT 24
Peak memory 217456 kb
Host smart-a73ab8a2-baf4-4d23-98af-3abc573cbae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300544745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2300544745
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3368736980
Short name T514
Test name
Test status
Simulation time 110745446 ps
CPU time 0.81 seconds
Started Jul 15 05:52:50 PM PDT 24
Finished Jul 15 05:52:51 PM PDT 24
Peak memory 199892 kb
Host smart-f2aef77c-dca6-48fe-b106-389e2478a108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368736980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3368736980
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3408950695
Short name T407
Test name
Test status
Simulation time 1531340716 ps
CPU time 5.73 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 200344 kb
Host smart-170a89da-ae83-44cc-a0e6-912cbb25084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408950695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3408950695
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.103672929
Short name T297
Test name
Test status
Simulation time 149154900 ps
CPU time 1.2 seconds
Started Jul 15 05:52:50 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 200080 kb
Host smart-8ea8804b-ca53-4c01-b931-af63c1309135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103672929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.103672929
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1021052700
Short name T177
Test name
Test status
Simulation time 204702216 ps
CPU time 1.39 seconds
Started Jul 15 05:52:54 PM PDT 24
Finished Jul 15 05:52:56 PM PDT 24
Peak memory 200232 kb
Host smart-99842bc8-928e-4a78-8a4f-911574e98b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021052700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1021052700
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3450174942
Short name T99
Test name
Test status
Simulation time 4177846458 ps
CPU time 13.77 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:53:12 PM PDT 24
Peak memory 200416 kb
Host smart-12fa0987-01e3-4730-ac1e-600b8b7ad567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450174942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3450174942
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2261511999
Short name T239
Test name
Test status
Simulation time 335940389 ps
CPU time 2.3 seconds
Started Jul 15 05:52:51 PM PDT 24
Finished Jul 15 05:52:54 PM PDT 24
Peak memory 208356 kb
Host smart-84f02bc7-9b58-4187-867f-1c73fa719126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261511999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2261511999
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3372957509
Short name T195
Test name
Test status
Simulation time 90365193 ps
CPU time 0.89 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 200072 kb
Host smart-1a0d6801-1afc-4a9b-863e-a84d0cb85c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372957509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3372957509
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3359366848
Short name T193
Test name
Test status
Simulation time 66201832 ps
CPU time 0.83 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 199912 kb
Host smart-bd39fa6f-dfce-4711-9ffe-f1e5d3399c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359366848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3359366848
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2280672817
Short name T143
Test name
Test status
Simulation time 243482001 ps
CPU time 1.07 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:52:58 PM PDT 24
Peak memory 217464 kb
Host smart-9c0d770c-d656-418e-bef3-e154ba75deee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280672817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2280672817
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3129671120
Short name T419
Test name
Test status
Simulation time 209239245 ps
CPU time 0.89 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 199904 kb
Host smart-4f8f65db-ec12-43bd-9200-1d698ab27485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129671120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3129671120
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3255761536
Short name T95
Test name
Test status
Simulation time 746995054 ps
CPU time 4.14 seconds
Started Jul 15 05:52:51 PM PDT 24
Finished Jul 15 05:52:56 PM PDT 24
Peak memory 200308 kb
Host smart-f9e54d6c-a98f-4e6c-a5f8-76f17d1c798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255761536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3255761536
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3958055009
Short name T509
Test name
Test status
Simulation time 149905999 ps
CPU time 1.18 seconds
Started Jul 15 05:52:54 PM PDT 24
Finished Jul 15 05:52:56 PM PDT 24
Peak memory 200016 kb
Host smart-3985a260-624c-4b71-8ca2-81161c8b936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958055009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3958055009
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.719653612
Short name T247
Test name
Test status
Simulation time 245027874 ps
CPU time 1.57 seconds
Started Jul 15 05:52:50 PM PDT 24
Finished Jul 15 05:52:53 PM PDT 24
Peak memory 200256 kb
Host smart-4d829ed1-a556-4607-8b0f-fe0ef8bdc1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719653612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.719653612
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.965970931
Short name T512
Test name
Test status
Simulation time 8910190076 ps
CPU time 36.3 seconds
Started Jul 15 05:52:50 PM PDT 24
Finished Jul 15 05:53:27 PM PDT 24
Peak memory 200360 kb
Host smart-d0a43ddb-19db-47d5-954a-b24cefc4a9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965970931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.965970931
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1287467223
Short name T375
Test name
Test status
Simulation time 535658373 ps
CPU time 2.79 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 200104 kb
Host smart-428a6f0f-8cd1-4bf8-951e-2c4ae7ff2e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287467223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1287467223
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3844980220
Short name T438
Test name
Test status
Simulation time 96108858 ps
CPU time 0.95 seconds
Started Jul 15 05:52:50 PM PDT 24
Finished Jul 15 05:52:51 PM PDT 24
Peak memory 200068 kb
Host smart-4917c060-dff7-4e5f-875e-ec0f1ffc3bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844980220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3844980220
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.878153131
Short name T264
Test name
Test status
Simulation time 68826573 ps
CPU time 0.84 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:51:47 PM PDT 24
Peak memory 199776 kb
Host smart-04f38c2f-4df3-448d-a0cd-dcd2419ffd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878153131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.878153131
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2011341372
Short name T230
Test name
Test status
Simulation time 1911708001 ps
CPU time 7.38 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:51:54 PM PDT 24
Peak memory 221656 kb
Host smart-14a65392-6f30-4230-81de-1ec1ee574973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011341372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2011341372
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1129068104
Short name T528
Test name
Test status
Simulation time 243064566 ps
CPU time 1.09 seconds
Started Jul 15 05:51:46 PM PDT 24
Finished Jul 15 05:51:48 PM PDT 24
Peak memory 217432 kb
Host smart-457a72bb-40fe-41dc-8186-541aaa19d049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129068104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1129068104
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.996645020
Short name T302
Test name
Test status
Simulation time 214540660 ps
CPU time 0.88 seconds
Started Jul 15 05:51:42 PM PDT 24
Finished Jul 15 05:51:44 PM PDT 24
Peak memory 199904 kb
Host smart-4f399be7-42a4-4413-802d-04b37928b748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996645020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.996645020
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1609208657
Short name T211
Test name
Test status
Simulation time 1069538946 ps
CPU time 4.81 seconds
Started Jul 15 05:51:48 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 200296 kb
Host smart-b135bb37-a953-4aea-a956-e5a7a4db4ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609208657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1609208657
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3665346392
Short name T66
Test name
Test status
Simulation time 16532085342 ps
CPU time 30.81 seconds
Started Jul 15 05:51:44 PM PDT 24
Finished Jul 15 05:52:16 PM PDT 24
Peak memory 217200 kb
Host smart-5b49dd09-82dc-4deb-9d50-dbe5ee045f36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665346392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3665346392
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.267113517
Short name T321
Test name
Test status
Simulation time 146786391 ps
CPU time 1.1 seconds
Started Jul 15 05:51:43 PM PDT 24
Finished Jul 15 05:51:46 PM PDT 24
Peak memory 200028 kb
Host smart-7c356c83-b40d-48ed-a2a4-2766c076e5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267113517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.267113517
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1652894936
Short name T117
Test name
Test status
Simulation time 191576717 ps
CPU time 1.44 seconds
Started Jul 15 05:51:43 PM PDT 24
Finished Jul 15 05:51:45 PM PDT 24
Peak memory 200136 kb
Host smart-3cd9a985-a79d-4002-b9f5-f460a196def9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652894936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1652894936
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1914589272
Short name T530
Test name
Test status
Simulation time 6220072479 ps
CPU time 26.21 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:52:13 PM PDT 24
Peak memory 208608 kb
Host smart-f50e6320-a64d-4ca5-bb6f-a88414dcf47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914589272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1914589272
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1991170435
Short name T308
Test name
Test status
Simulation time 245745633 ps
CPU time 1.88 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:51:49 PM PDT 24
Peak memory 200116 kb
Host smart-17a1dc1a-a15f-4323-b880-e2b0136c52e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991170435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1991170435
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.360347953
Short name T520
Test name
Test status
Simulation time 72827428 ps
CPU time 0.82 seconds
Started Jul 15 05:51:44 PM PDT 24
Finished Jul 15 05:51:46 PM PDT 24
Peak memory 200076 kb
Host smart-522144a8-a431-49ea-9eed-e0b1d9313c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360347953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.360347953
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3889128309
Short name T152
Test name
Test status
Simulation time 61450161 ps
CPU time 0.73 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:52:54 PM PDT 24
Peak memory 199512 kb
Host smart-2111848c-b3ff-43f9-86c6-e184a7910272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889128309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3889128309
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2214352188
Short name T298
Test name
Test status
Simulation time 2189624676 ps
CPU time 7.85 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:53:02 PM PDT 24
Peak memory 217804 kb
Host smart-0f0c1db2-c200-460b-b46c-86a70b7ee8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214352188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2214352188
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.466095675
Short name T233
Test name
Test status
Simulation time 243649477 ps
CPU time 1.1 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 217476 kb
Host smart-38754c26-330f-4128-861c-c8509ca15022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466095675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.466095675
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.274070165
Short name T340
Test name
Test status
Simulation time 178439154 ps
CPU time 0.98 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 199880 kb
Host smart-ea716ae6-968a-436d-84fb-004b75f86a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274070165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.274070165
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4218155448
Short name T183
Test name
Test status
Simulation time 1319384554 ps
CPU time 5.33 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:53:03 PM PDT 24
Peak memory 200392 kb
Host smart-9399338d-ce96-47df-804e-cbca9a70ed57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218155448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4218155448
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1980537467
Short name T215
Test name
Test status
Simulation time 171822493 ps
CPU time 1.18 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 200068 kb
Host smart-ac1ef7f5-e11d-47eb-a03c-d395f08d16e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980537467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1980537467
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1054409120
Short name T47
Test name
Test status
Simulation time 129655056 ps
CPU time 1.21 seconds
Started Jul 15 05:52:51 PM PDT 24
Finished Jul 15 05:52:54 PM PDT 24
Peak memory 200296 kb
Host smart-99ce9630-32e5-46de-b5e7-65e959da2c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054409120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1054409120
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2568641880
Short name T254
Test name
Test status
Simulation time 3458468696 ps
CPU time 13.04 seconds
Started Jul 15 05:52:51 PM PDT 24
Finished Jul 15 05:53:05 PM PDT 24
Peak memory 210020 kb
Host smart-7029c0cc-0388-48c2-916a-427bdf01bc29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568641880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2568641880
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.812891447
Short name T332
Test name
Test status
Simulation time 147772936 ps
CPU time 1.84 seconds
Started Jul 15 05:52:50 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 200080 kb
Host smart-812089b9-06fb-4086-8799-a810cd582ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812891447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.812891447
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3921542583
Short name T425
Test name
Test status
Simulation time 76526968 ps
CPU time 0.85 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:52:57 PM PDT 24
Peak memory 200076 kb
Host smart-1dab6cab-af4f-4a66-aadc-4a9eb46dee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921542583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3921542583
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1083118390
Short name T145
Test name
Test status
Simulation time 71787488 ps
CPU time 0.82 seconds
Started Jul 15 05:52:50 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 199860 kb
Host smart-11c17013-4dbe-4a3f-b3bf-fc6bc23f71ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083118390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1083118390
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2605572119
Short name T54
Test name
Test status
Simulation time 2171508778 ps
CPU time 7.94 seconds
Started Jul 15 05:52:51 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 217088 kb
Host smart-5a7588f4-3345-4141-af03-2a874d908306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605572119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2605572119
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.124523987
Short name T480
Test name
Test status
Simulation time 243666567 ps
CPU time 1.11 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 217488 kb
Host smart-917ac913-cf6d-4d3c-9ccf-05ccaafc51b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124523987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.124523987
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.478415828
Short name T16
Test name
Test status
Simulation time 183575387 ps
CPU time 0.88 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 199864 kb
Host smart-f24e2b61-cb01-477b-9480-ad7169220015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478415828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.478415828
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1676672861
Short name T541
Test name
Test status
Simulation time 1643215665 ps
CPU time 6.83 seconds
Started Jul 15 05:52:51 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 200264 kb
Host smart-030e7754-afbe-4263-bb8a-91a0c5777472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676672861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1676672861
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.387814241
Short name T447
Test name
Test status
Simulation time 157451146 ps
CPU time 1.12 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 200116 kb
Host smart-54aa4203-90c6-4e1b-8840-557c1df20b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387814241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.387814241
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2278907282
Short name T337
Test name
Test status
Simulation time 115453970 ps
CPU time 1.17 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 199856 kb
Host smart-5dc86af9-2534-45e0-901e-2bc63de472ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278907282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2278907282
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3098232162
Short name T249
Test name
Test status
Simulation time 3119468019 ps
CPU time 14.74 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:53:10 PM PDT 24
Peak memory 200396 kb
Host smart-39e18cf7-97c4-4b08-8c83-2146331ddcf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098232162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3098232162
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.591408938
Short name T127
Test name
Test status
Simulation time 505533719 ps
CPU time 2.82 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:52:56 PM PDT 24
Peak memory 200136 kb
Host smart-9bdeed88-c084-4462-9eb8-c39bbd2db132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591408938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.591408938
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3405449826
Short name T443
Test name
Test status
Simulation time 102165528 ps
CPU time 0.93 seconds
Started Jul 15 05:52:50 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 200072 kb
Host smart-7f2f8a29-01c4-4967-a324-48c3a309bcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405449826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3405449826
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3441780065
Short name T151
Test name
Test status
Simulation time 79574533 ps
CPU time 0.79 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 199880 kb
Host smart-da5c0ab5-7687-484a-9c52-5896ed8dafd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441780065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3441780065
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1532795454
Short name T50
Test name
Test status
Simulation time 1228117536 ps
CPU time 6.12 seconds
Started Jul 15 05:52:53 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 216876 kb
Host smart-71712e19-028b-4fdc-87bb-fea7ca355276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532795454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1532795454
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1284723555
Short name T418
Test name
Test status
Simulation time 244164810 ps
CPU time 1.1 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 217400 kb
Host smart-c50ae270-0bff-4f36-88ce-88754626c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284723555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1284723555
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.4006636687
Short name T317
Test name
Test status
Simulation time 244982926 ps
CPU time 0.94 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:52:54 PM PDT 24
Peak memory 199924 kb
Host smart-e2df00e2-a609-4378-93ae-181662d461b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006636687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.4006636687
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3529240623
Short name T89
Test name
Test status
Simulation time 811662614 ps
CPU time 3.97 seconds
Started Jul 15 05:52:51 PM PDT 24
Finished Jul 15 05:52:56 PM PDT 24
Peak memory 200316 kb
Host smart-91dcd905-d284-4061-bb78-29c15fc3fa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529240623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3529240623
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1864025868
Short name T392
Test name
Test status
Simulation time 112689960 ps
CPU time 1 seconds
Started Jul 15 05:52:57 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 200080 kb
Host smart-92aaebe2-c5ed-4c0c-940e-41ec1307fdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864025868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1864025868
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.4291583386
Short name T196
Test name
Test status
Simulation time 109745642 ps
CPU time 1.13 seconds
Started Jul 15 05:52:50 PM PDT 24
Finished Jul 15 05:52:52 PM PDT 24
Peak memory 200252 kb
Host smart-02249ce0-a715-4fb9-8f54-a29b19935c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291583386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.4291583386
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3603216137
Short name T384
Test name
Test status
Simulation time 5939040241 ps
CPU time 22.69 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:53:17 PM PDT 24
Peak memory 200424 kb
Host smart-7fe0d0bc-a496-475c-bc9f-5168322d691f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603216137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3603216137
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2240435651
Short name T536
Test name
Test status
Simulation time 308991137 ps
CPU time 2.11 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 200140 kb
Host smart-15bd9c3f-cc69-4994-bca9-fc35e9ccc317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240435651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2240435651
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1003770711
Short name T199
Test name
Test status
Simulation time 162283088 ps
CPU time 1.27 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 200312 kb
Host smart-e140772b-0a48-4e67-9764-c415ddaea690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003770711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1003770711
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2411408056
Short name T490
Test name
Test status
Simulation time 69580529 ps
CPU time 0.77 seconds
Started Jul 15 05:52:58 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 199900 kb
Host smart-f45b5d1e-62c5-4d62-984b-746e9af219b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411408056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2411408056
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1656358519
Short name T39
Test name
Test status
Simulation time 1229291797 ps
CPU time 6.07 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:53:02 PM PDT 24
Peak memory 217788 kb
Host smart-4cfe9738-adce-40d2-9bc9-15008d7235ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656358519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1656358519
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2994331346
Short name T343
Test name
Test status
Simulation time 244606853 ps
CPU time 1.06 seconds
Started Jul 15 05:53:03 PM PDT 24
Finished Jul 15 05:53:05 PM PDT 24
Peak memory 217472 kb
Host smart-031a0dec-efa3-43b7-9a25-44d042cf4e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994331346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2994331346
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2886076762
Short name T250
Test name
Test status
Simulation time 190406261 ps
CPU time 0.89 seconds
Started Jul 15 05:52:51 PM PDT 24
Finished Jul 15 05:52:53 PM PDT 24
Peak memory 199856 kb
Host smart-019e5006-d221-4741-b664-dadb8cc440f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886076762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2886076762
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.516291807
Short name T473
Test name
Test status
Simulation time 1864759677 ps
CPU time 7.26 seconds
Started Jul 15 05:52:58 PM PDT 24
Finished Jul 15 05:53:07 PM PDT 24
Peak memory 199544 kb
Host smart-989aa90e-30c2-44ac-8736-a37329624306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516291807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.516291807
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1397044229
Short name T291
Test name
Test status
Simulation time 107064998 ps
CPU time 1.1 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:03 PM PDT 24
Peak memory 200080 kb
Host smart-f6d3456b-2465-4ad1-8f8f-950796669f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397044229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1397044229
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3785374857
Short name T486
Test name
Test status
Simulation time 238071835 ps
CPU time 1.43 seconds
Started Jul 15 05:52:52 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 200300 kb
Host smart-46715157-3971-438a-9968-c2cdd5253f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785374857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3785374857
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.260602968
Short name T114
Test name
Test status
Simulation time 11308447100 ps
CPU time 40.08 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:53:37 PM PDT 24
Peak memory 200424 kb
Host smart-61c4d4a0-854f-4c43-8745-2eb0ef28441b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260602968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.260602968
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2863259642
Short name T82
Test name
Test status
Simulation time 139328230 ps
CPU time 1.7 seconds
Started Jul 15 05:53:01 PM PDT 24
Finished Jul 15 05:53:03 PM PDT 24
Peak memory 200080 kb
Host smart-73dee1dc-639f-46da-a021-a52c40767805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863259642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2863259642
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1140869477
Short name T497
Test name
Test status
Simulation time 68483552 ps
CPU time 0.77 seconds
Started Jul 15 05:52:51 PM PDT 24
Finished Jul 15 05:52:54 PM PDT 24
Peak memory 200048 kb
Host smart-66cc4abb-4e3a-4f26-89e7-339c6edb6c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140869477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1140869477
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.352355223
Short name T10
Test name
Test status
Simulation time 76861547 ps
CPU time 0.84 seconds
Started Jul 15 05:52:57 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 199828 kb
Host smart-c62b02eb-d479-4d82-881b-aedbac6a9261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352355223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.352355223
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.837136897
Short name T518
Test name
Test status
Simulation time 2352254940 ps
CPU time 8 seconds
Started Jul 15 05:53:01 PM PDT 24
Finished Jul 15 05:53:09 PM PDT 24
Peak memory 217792 kb
Host smart-21541a7d-df56-4ff9-89df-0452f15b8e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837136897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.837136897
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.691789860
Short name T245
Test name
Test status
Simulation time 244619360 ps
CPU time 1.14 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 217380 kb
Host smart-873043b9-911b-4ca6-b45e-9582c0c5e4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691789860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.691789860
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.4118796429
Short name T426
Test name
Test status
Simulation time 156773179 ps
CPU time 0.86 seconds
Started Jul 15 05:52:57 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 199924 kb
Host smart-cc00a785-7f1c-440d-9d9b-b4bfd340a7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118796429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4118796429
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3981544350
Short name T404
Test name
Test status
Simulation time 1532213741 ps
CPU time 6.13 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:53:02 PM PDT 24
Peak memory 200364 kb
Host smart-e882f40f-cd2a-4119-bdda-ecc107a13a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981544350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3981544350
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.466034637
Short name T345
Test name
Test status
Simulation time 106611655 ps
CPU time 1.05 seconds
Started Jul 15 05:53:01 PM PDT 24
Finished Jul 15 05:53:03 PM PDT 24
Peak memory 200096 kb
Host smart-19bc191c-a652-4ca0-bcaa-4745c2041a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466034637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.466034637
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.761090943
Short name T170
Test name
Test status
Simulation time 117204477 ps
CPU time 1.24 seconds
Started Jul 15 05:52:57 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 200372 kb
Host smart-2398e6d8-20b6-4bee-ba08-c34ada293b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761090943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.761090943
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2801951512
Short name T355
Test name
Test status
Simulation time 4766647920 ps
CPU time 18.33 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:53:17 PM PDT 24
Peak memory 208600 kb
Host smart-24f3b6fc-3bad-49f2-a502-5a2446bbf676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801951512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2801951512
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1413722491
Short name T479
Test name
Test status
Simulation time 126363333 ps
CPU time 1.66 seconds
Started Jul 15 05:52:58 PM PDT 24
Finished Jul 15 05:53:01 PM PDT 24
Peak memory 200124 kb
Host smart-d315d73f-f09d-43ca-8f74-b270a6a088e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413722491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1413722491
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.4048849034
Short name T15
Test name
Test status
Simulation time 67982920 ps
CPU time 0.8 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:52:58 PM PDT 24
Peak memory 200048 kb
Host smart-9687fd7e-62f8-4702-97e7-8ea7e4cf17a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048849034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.4048849034
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1381012520
Short name T208
Test name
Test status
Simulation time 88824347 ps
CPU time 0.83 seconds
Started Jul 15 05:52:57 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 199860 kb
Host smart-034448e2-5e41-486a-9acb-4d99a2d471f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381012520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1381012520
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1648857946
Short name T359
Test name
Test status
Simulation time 2363541214 ps
CPU time 8.02 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:53:04 PM PDT 24
Peak memory 221740 kb
Host smart-e3a94419-c349-4936-b0f5-e9b6517e0e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648857946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1648857946
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4101330817
Short name T481
Test name
Test status
Simulation time 244113070 ps
CPU time 1.12 seconds
Started Jul 15 05:53:03 PM PDT 24
Finished Jul 15 05:53:05 PM PDT 24
Peak memory 217468 kb
Host smart-01e991d3-e4ab-4597-b692-c342bf33a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101330817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4101330817
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2995216146
Short name T22
Test name
Test status
Simulation time 95863509 ps
CPU time 0.8 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:03 PM PDT 24
Peak memory 199900 kb
Host smart-439cab3f-7129-4c7f-900c-4df8e28d7ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995216146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2995216146
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2248421080
Short name T96
Test name
Test status
Simulation time 1042465645 ps
CPU time 5.55 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:53:02 PM PDT 24
Peak memory 200320 kb
Host smart-1a8b8a63-8e76-402b-94c5-14c145057849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248421080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2248421080
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.89519838
Short name T181
Test name
Test status
Simulation time 100740400 ps
CPU time 1.16 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:04 PM PDT 24
Peak memory 200080 kb
Host smart-e686f73a-495c-43bf-bedf-0220ed39e368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89519838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.89519838
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2471048191
Short name T270
Test name
Test status
Simulation time 125287605 ps
CPU time 1.25 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 200372 kb
Host smart-a63072dd-4382-4013-b970-a4433777a95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471048191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2471048191
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.731143537
Short name T272
Test name
Test status
Simulation time 155193888 ps
CPU time 1.19 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 200104 kb
Host smart-e46f1bd6-acec-47f6-8ed6-23c581dee475
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731143537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.731143537
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1529395968
Short name T498
Test name
Test status
Simulation time 138911976 ps
CPU time 1.82 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:05 PM PDT 24
Peak memory 200064 kb
Host smart-e5b2d9a0-ad28-4af8-b155-eb484c3f74b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529395968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1529395968
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.793448185
Short name T116
Test name
Test status
Simulation time 280775435 ps
CPU time 1.63 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 200312 kb
Host smart-6fca444f-4131-4f4b-8b37-7fe1df19a362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793448185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.793448185
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3466101965
Short name T519
Test name
Test status
Simulation time 65106230 ps
CPU time 0.81 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:05 PM PDT 24
Peak memory 199864 kb
Host smart-32f2c544-4dfc-4563-b259-c59b51979f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466101965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3466101965
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.848779289
Short name T380
Test name
Test status
Simulation time 1895829164 ps
CPU time 7.46 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:53:04 PM PDT 24
Peak memory 221672 kb
Host smart-11c298a1-6b65-4161-a5fe-afd7d1054d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848779289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.848779289
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2194419400
Short name T394
Test name
Test status
Simulation time 244616841 ps
CPU time 1.21 seconds
Started Jul 15 05:52:57 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 217436 kb
Host smart-049e2bd0-877f-4022-b892-e5359915727b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194419400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2194419400
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1855014881
Short name T369
Test name
Test status
Simulation time 156737563 ps
CPU time 0.83 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:04 PM PDT 24
Peak memory 199884 kb
Host smart-973202a2-fd9f-4178-8b22-0ef764ecffe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855014881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1855014881
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1254822415
Short name T93
Test name
Test status
Simulation time 1507367007 ps
CPU time 5.92 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:53:04 PM PDT 24
Peak memory 200360 kb
Host smart-c7a11cb4-8d6e-4502-a0bb-0574dea16693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254822415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1254822415
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3846123269
Short name T174
Test name
Test status
Simulation time 108485346 ps
CPU time 1.04 seconds
Started Jul 15 05:52:57 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 200108 kb
Host smart-30642395-38a6-4e8b-8e30-997af0346350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846123269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3846123269
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3157954172
Short name T478
Test name
Test status
Simulation time 261331817 ps
CPU time 1.46 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:05 PM PDT 24
Peak memory 200176 kb
Host smart-b7dbe2e7-7e03-40cb-877f-2614647a89ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157954172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3157954172
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3315865958
Short name T327
Test name
Test status
Simulation time 8809438156 ps
CPU time 28.43 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:32 PM PDT 24
Peak memory 208496 kb
Host smart-b8ad37f0-4945-451c-94ba-3e992b05beed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315865958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3315865958
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2905758232
Short name T180
Test name
Test status
Simulation time 114203483 ps
CPU time 1.58 seconds
Started Jul 15 05:52:55 PM PDT 24
Finished Jul 15 05:52:57 PM PDT 24
Peak memory 200136 kb
Host smart-227e68e2-28d5-4418-8a8c-f0b4af5ba71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905758232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2905758232
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1546543366
Short name T435
Test name
Test status
Simulation time 266195053 ps
CPU time 1.64 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:04 PM PDT 24
Peak memory 200092 kb
Host smart-39e6b224-ebc5-4b4f-876c-dfe4e4ee4d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546543366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1546543366
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1659810263
Short name T397
Test name
Test status
Simulation time 65401039 ps
CPU time 0.76 seconds
Started Jul 15 05:53:05 PM PDT 24
Finished Jul 15 05:53:07 PM PDT 24
Peak memory 199864 kb
Host smart-74353504-70e2-4f6a-9342-5e967f8fff85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659810263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1659810263
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.655686259
Short name T324
Test name
Test status
Simulation time 1232834942 ps
CPU time 5.5 seconds
Started Jul 15 05:53:05 PM PDT 24
Finished Jul 15 05:53:11 PM PDT 24
Peak memory 216932 kb
Host smart-7d13eea3-c973-4b7e-b164-b0990dacc3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655686259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.655686259
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2073168797
Short name T495
Test name
Test status
Simulation time 244413815 ps
CPU time 1.1 seconds
Started Jul 15 05:53:05 PM PDT 24
Finished Jul 15 05:53:07 PM PDT 24
Peak memory 217376 kb
Host smart-026c96a6-1954-40f8-b942-2906c12d363a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073168797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2073168797
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3830186121
Short name T23
Test name
Test status
Simulation time 126237163 ps
CPU time 0.84 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:04 PM PDT 24
Peak memory 199900 kb
Host smart-62284f30-4dfd-4280-a004-144d2f9435c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830186121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3830186121
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3962922941
Short name T269
Test name
Test status
Simulation time 1138620335 ps
CPU time 4.5 seconds
Started Jul 15 05:52:58 PM PDT 24
Finished Jul 15 05:53:04 PM PDT 24
Peak memory 200528 kb
Host smart-98124369-3c0a-4bc7-8cdd-e83312cbe9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962922941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3962922941
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2924415164
Short name T383
Test name
Test status
Simulation time 156535279 ps
CPU time 1.2 seconds
Started Jul 15 05:53:06 PM PDT 24
Finished Jul 15 05:53:09 PM PDT 24
Peak memory 200260 kb
Host smart-c53bf067-eb6d-48eb-9a04-3ac260a49ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924415164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2924415164
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1893185932
Short name T414
Test name
Test status
Simulation time 192494157 ps
CPU time 1.46 seconds
Started Jul 15 05:53:01 PM PDT 24
Finished Jul 15 05:53:03 PM PDT 24
Peak memory 200276 kb
Host smart-eb066df7-e70b-4309-967d-a62a80b8a268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893185932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1893185932
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2198550512
Short name T350
Test name
Test status
Simulation time 4949774851 ps
CPU time 18.21 seconds
Started Jul 15 05:53:04 PM PDT 24
Finished Jul 15 05:53:24 PM PDT 24
Peak memory 200428 kb
Host smart-1e89e0ef-c028-417d-a71e-2bcddd394a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198550512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2198550512
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.582512761
Short name T130
Test name
Test status
Simulation time 452780185 ps
CPU time 2.58 seconds
Started Jul 15 05:53:03 PM PDT 24
Finished Jul 15 05:53:07 PM PDT 24
Peak memory 200072 kb
Host smart-c8af6c20-1406-48fb-9cd4-17ab4408cdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582512761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.582512761
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1670024387
Short name T125
Test name
Test status
Simulation time 110193994 ps
CPU time 0.91 seconds
Started Jul 15 05:52:56 PM PDT 24
Finished Jul 15 05:52:59 PM PDT 24
Peak memory 200092 kb
Host smart-9b87f593-d2bd-443f-bbf6-43beddbae4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670024387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1670024387
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3559307706
Short name T67
Test name
Test status
Simulation time 65733312 ps
CPU time 0.8 seconds
Started Jul 15 05:53:03 PM PDT 24
Finished Jul 15 05:53:06 PM PDT 24
Peak memory 199888 kb
Host smart-f3359285-14ec-485d-83d0-513e2b31034d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559307706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3559307706
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1012273858
Short name T357
Test name
Test status
Simulation time 1224492812 ps
CPU time 5.65 seconds
Started Jul 15 05:53:08 PM PDT 24
Finished Jul 15 05:53:14 PM PDT 24
Peak memory 217444 kb
Host smart-80bfeea7-9d78-4082-9d8f-f552ca9f7f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012273858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1012273858
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.439779730
Short name T258
Test name
Test status
Simulation time 244416282 ps
CPU time 1.06 seconds
Started Jul 15 05:53:08 PM PDT 24
Finished Jul 15 05:53:09 PM PDT 24
Peak memory 217484 kb
Host smart-21d82dbb-77e8-42df-99e3-ce59eb003a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439779730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.439779730
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2607773524
Short name T348
Test name
Test status
Simulation time 156904567 ps
CPU time 0.93 seconds
Started Jul 15 05:53:02 PM PDT 24
Finished Jul 15 05:53:05 PM PDT 24
Peak memory 199928 kb
Host smart-71a982e6-c758-4195-9eb3-fa44eeb88d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607773524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2607773524
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3449824686
Short name T457
Test name
Test status
Simulation time 1691582174 ps
CPU time 6.72 seconds
Started Jul 15 05:53:04 PM PDT 24
Finished Jul 15 05:53:12 PM PDT 24
Peak memory 200352 kb
Host smart-a7d180cf-d239-4018-95fe-a39d2e78b5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449824686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3449824686
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2060433868
Short name T43
Test name
Test status
Simulation time 114416399 ps
CPU time 1.06 seconds
Started Jul 15 05:53:05 PM PDT 24
Finished Jul 15 05:53:07 PM PDT 24
Peak memory 200108 kb
Host smart-1d881fc4-e5d3-4690-96ed-a9c6bd8999c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060433868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2060433868
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2565592517
Short name T176
Test name
Test status
Simulation time 205783387 ps
CPU time 1.32 seconds
Started Jul 15 05:53:08 PM PDT 24
Finished Jul 15 05:53:10 PM PDT 24
Peak memory 200300 kb
Host smart-d6934f7a-99d4-41c2-81df-e4f86c55b2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565592517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2565592517
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.4015169921
Short name T472
Test name
Test status
Simulation time 5085605183 ps
CPU time 19.19 seconds
Started Jul 15 05:53:04 PM PDT 24
Finished Jul 15 05:53:25 PM PDT 24
Peak memory 210712 kb
Host smart-abe0e700-ae56-4ca6-94f6-c0f07e4353de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015169921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4015169921
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3952690345
Short name T229
Test name
Test status
Simulation time 386499625 ps
CPU time 2.17 seconds
Started Jul 15 05:53:03 PM PDT 24
Finished Jul 15 05:53:07 PM PDT 24
Peak memory 200064 kb
Host smart-c1f70434-4c2a-4e4d-b8cd-25661c08477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952690345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3952690345
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3997536094
Short name T339
Test name
Test status
Simulation time 77527315 ps
CPU time 0.85 seconds
Started Jul 15 05:53:06 PM PDT 24
Finished Jul 15 05:53:08 PM PDT 24
Peak memory 200112 kb
Host smart-d74728da-07e7-4cf4-9431-89a8e8b4ad03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997536094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3997536094
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3208283546
Short name T146
Test name
Test status
Simulation time 85279589 ps
CPU time 0.78 seconds
Started Jul 15 05:53:05 PM PDT 24
Finished Jul 15 05:53:07 PM PDT 24
Peak memory 199888 kb
Host smart-7daa6a72-f662-4f8f-9cc4-a4317f4fd5d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208283546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3208283546
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.702564121
Short name T248
Test name
Test status
Simulation time 1220961166 ps
CPU time 5.28 seconds
Started Jul 15 05:53:08 PM PDT 24
Finished Jul 15 05:53:14 PM PDT 24
Peak memory 217748 kb
Host smart-80abd468-13dc-4545-87cc-4bdd76d0e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702564121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.702564121
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2460875065
Short name T238
Test name
Test status
Simulation time 244665933 ps
CPU time 1.15 seconds
Started Jul 15 05:53:05 PM PDT 24
Finished Jul 15 05:53:07 PM PDT 24
Peak memory 217444 kb
Host smart-74e94ff9-5daf-4bde-9c2c-f8cd7e4e3446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460875065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2460875065
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3196713807
Short name T293
Test name
Test status
Simulation time 213568132 ps
CPU time 0.9 seconds
Started Jul 15 05:53:06 PM PDT 24
Finished Jul 15 05:53:09 PM PDT 24
Peak memory 199904 kb
Host smart-d4a93a3e-1dfe-4996-b4af-9dc215e9148a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196713807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3196713807
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.4191153185
Short name T459
Test name
Test status
Simulation time 1075710438 ps
CPU time 4.5 seconds
Started Jul 15 05:53:03 PM PDT 24
Finished Jul 15 05:53:09 PM PDT 24
Peak memory 200344 kb
Host smart-9b301dfd-7eb0-4a81-8580-a7f5a303781d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191153185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.4191153185
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3487898091
Short name T197
Test name
Test status
Simulation time 103275072 ps
CPU time 1.05 seconds
Started Jul 15 05:53:03 PM PDT 24
Finished Jul 15 05:53:06 PM PDT 24
Peak memory 200092 kb
Host smart-cae5300a-d9a9-4153-8456-5751325d2d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487898091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3487898091
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2187969022
Short name T505
Test name
Test status
Simulation time 112983597 ps
CPU time 1.17 seconds
Started Jul 15 05:53:01 PM PDT 24
Finished Jul 15 05:53:03 PM PDT 24
Peak memory 200136 kb
Host smart-39e4aed4-c31d-4539-b757-8705c74911aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187969022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2187969022
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2798523606
Short name T228
Test name
Test status
Simulation time 119731899 ps
CPU time 1.47 seconds
Started Jul 15 05:53:05 PM PDT 24
Finished Jul 15 05:53:07 PM PDT 24
Peak memory 200012 kb
Host smart-46e1ee5c-5048-4962-acf6-39ac4b3a5160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798523606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2798523606
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1398322965
Short name T427
Test name
Test status
Simulation time 156534505 ps
CPU time 1.22 seconds
Started Jul 15 05:53:03 PM PDT 24
Finished Jul 15 05:53:06 PM PDT 24
Peak memory 200072 kb
Host smart-9222fdae-8ddf-4ff3-85db-521203824216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398322965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1398322965
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2015847687
Short name T144
Test name
Test status
Simulation time 66998507 ps
CPU time 0.8 seconds
Started Jul 15 05:51:44 PM PDT 24
Finished Jul 15 05:51:46 PM PDT 24
Peak memory 199868 kb
Host smart-22dd8ad4-35fd-4a3f-8059-8c575ffc3264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015847687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2015847687
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2449414931
Short name T55
Test name
Test status
Simulation time 1890382917 ps
CPU time 7.77 seconds
Started Jul 15 05:51:48 PM PDT 24
Finished Jul 15 05:51:57 PM PDT 24
Peak memory 229796 kb
Host smart-c00ddc88-731a-483b-a327-d65128bb4f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449414931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2449414931
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3126310796
Short name T164
Test name
Test status
Simulation time 244155693 ps
CPU time 1.22 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:51:48 PM PDT 24
Peak memory 217476 kb
Host smart-6fe53217-4280-4f6a-99ff-41dd54e31fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126310796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3126310796
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3391385114
Short name T379
Test name
Test status
Simulation time 107407097 ps
CPU time 0.78 seconds
Started Jul 15 05:51:43 PM PDT 24
Finished Jul 15 05:51:45 PM PDT 24
Peak memory 199920 kb
Host smart-1a6fa6b4-1d0f-4a46-94fb-5f58423b3710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391385114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3391385114
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1294585515
Short name T115
Test name
Test status
Simulation time 1423286684 ps
CPU time 5.92 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:51:52 PM PDT 24
Peak memory 200268 kb
Host smart-39c36188-e1dd-4b40-9729-89a1e697cb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294585515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1294585515
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2645144610
Short name T154
Test name
Test status
Simulation time 106689115 ps
CPU time 1.01 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:51:49 PM PDT 24
Peak memory 200108 kb
Host smart-c5635459-a259-4b47-93a7-028e24da85c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645144610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2645144610
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.848196125
Short name T167
Test name
Test status
Simulation time 205745864 ps
CPU time 1.39 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:51:48 PM PDT 24
Peak memory 200244 kb
Host smart-ec50af97-af6e-4b85-a305-f8fcab0e8388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848196125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.848196125
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2403204586
Short name T313
Test name
Test status
Simulation time 3757427732 ps
CPU time 16.88 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:52:04 PM PDT 24
Peak memory 208636 kb
Host smart-14ed8fb0-7fa4-41a1-a940-5216338cba0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403204586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2403204586
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3287000052
Short name T306
Test name
Test status
Simulation time 138495662 ps
CPU time 1.8 seconds
Started Jul 15 05:51:44 PM PDT 24
Finished Jul 15 05:51:47 PM PDT 24
Peak memory 200096 kb
Host smart-5684e8b0-087d-4251-901f-15c84a6f213b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287000052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3287000052
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3475605491
Short name T276
Test name
Test status
Simulation time 243749034 ps
CPU time 1.41 seconds
Started Jul 15 05:51:44 PM PDT 24
Finished Jul 15 05:51:47 PM PDT 24
Peak memory 200312 kb
Host smart-46609e6a-4b7f-474b-8210-1ec829c24f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475605491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3475605491
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2276365206
Short name T251
Test name
Test status
Simulation time 71204212 ps
CPU time 0.8 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:52 PM PDT 24
Peak memory 199836 kb
Host smart-532fc133-28c0-4234-8225-1ef266ccf3db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276365206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2276365206
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2953465203
Short name T527
Test name
Test status
Simulation time 1218992109 ps
CPU time 5.64 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:51:54 PM PDT 24
Peak memory 217712 kb
Host smart-1bd6aa14-e486-4b7d-b373-217b94cfefab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953465203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2953465203
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2733338897
Short name T424
Test name
Test status
Simulation time 244357689 ps
CPU time 1.17 seconds
Started Jul 15 05:51:52 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 217340 kb
Host smart-82a2e4d8-1d30-4c68-a1cd-a0f3890dafe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733338897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2733338897
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2187355325
Short name T442
Test name
Test status
Simulation time 179282187 ps
CPU time 0.95 seconds
Started Jul 15 05:51:46 PM PDT 24
Finished Jul 15 05:51:48 PM PDT 24
Peak memory 199860 kb
Host smart-a3acb67a-0ecb-4811-9b76-e82d35b1f912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187355325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2187355325
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.4275804045
Short name T400
Test name
Test status
Simulation time 1477212914 ps
CPU time 6.66 seconds
Started Jul 15 05:51:44 PM PDT 24
Finished Jul 15 05:51:52 PM PDT 24
Peak memory 200276 kb
Host smart-5c898c1a-2e09-480b-8548-4b8146dbf1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275804045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4275804045
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.979495311
Short name T209
Test name
Test status
Simulation time 105532064 ps
CPU time 1 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:51:49 PM PDT 24
Peak memory 200112 kb
Host smart-acb8ab86-0494-4050-8ab1-03d233019497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979495311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.979495311
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.506525268
Short name T225
Test name
Test status
Simulation time 114788389 ps
CPU time 1.23 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:51:50 PM PDT 24
Peak memory 200320 kb
Host smart-7219baa1-5a6e-4d79-a467-a878ecb7d878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506525268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.506525268
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.4029881282
Short name T378
Test name
Test status
Simulation time 14832393936 ps
CPU time 49.17 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:52:36 PM PDT 24
Peak memory 208616 kb
Host smart-bac5cb37-6f45-45ef-8ea3-f6eaf2a2e609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029881282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.4029881282
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4126721379
Short name T26
Test name
Test status
Simulation time 144787431 ps
CPU time 1.93 seconds
Started Jul 15 05:51:48 PM PDT 24
Finished Jul 15 05:51:52 PM PDT 24
Peak memory 200008 kb
Host smart-4cbbf0b7-b62b-4f08-a014-b0b69a7ea63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126721379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4126721379
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3411593407
Short name T515
Test name
Test status
Simulation time 153313991 ps
CPU time 1.21 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:51:48 PM PDT 24
Peak memory 200068 kb
Host smart-92fd3b24-6a4a-44ac-b826-ab5b28db5d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411593407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3411593407
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.57235802
Short name T292
Test name
Test status
Simulation time 69982751 ps
CPU time 0.79 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:51:49 PM PDT 24
Peak memory 199900 kb
Host smart-7ff3a363-6198-4a4e-9986-e7789a527b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57235802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.57235802
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1158154098
Short name T356
Test name
Test status
Simulation time 1229047452 ps
CPU time 5.49 seconds
Started Jul 15 05:51:50 PM PDT 24
Finished Jul 15 05:51:57 PM PDT 24
Peak memory 217440 kb
Host smart-44733e5b-5192-4477-8093-beca7bf3b6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158154098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1158154098
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3282356919
Short name T32
Test name
Test status
Simulation time 244081127 ps
CPU time 1.06 seconds
Started Jul 15 05:51:50 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 217364 kb
Host smart-2e023992-18da-4a4e-a9ec-d4a7c5f4049f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282356919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3282356919
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3653063829
Short name T446
Test name
Test status
Simulation time 93982601 ps
CPU time 0.79 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:51 PM PDT 24
Peak memory 199888 kb
Host smart-f909c4ec-9b87-4eef-9819-b8789d064e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653063829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3653063829
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1113430545
Short name T365
Test name
Test status
Simulation time 889494962 ps
CPU time 4.01 seconds
Started Jul 15 05:51:50 PM PDT 24
Finished Jul 15 05:51:56 PM PDT 24
Peak memory 200392 kb
Host smart-f494fae0-ecd6-4c84-8981-b17a64d3b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113430545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1113430545
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1805725069
Short name T439
Test name
Test status
Simulation time 91771796 ps
CPU time 0.99 seconds
Started Jul 15 05:51:52 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 200256 kb
Host smart-597309b0-e9c5-430a-89e6-2d6acd8d2472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805725069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1805725069
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.189771989
Short name T538
Test name
Test status
Simulation time 254201177 ps
CPU time 1.55 seconds
Started Jul 15 05:51:52 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 200028 kb
Host smart-23a43c3e-1745-4226-9bdc-8b973be52d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189771989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.189771989
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1807962939
Short name T226
Test name
Test status
Simulation time 3438135054 ps
CPU time 17.17 seconds
Started Jul 15 05:51:45 PM PDT 24
Finished Jul 15 05:52:04 PM PDT 24
Peak memory 208584 kb
Host smart-4eb27e46-ec4f-43b1-9652-04b5484e0f4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807962939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1807962939
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.985833895
Short name T46
Test name
Test status
Simulation time 134660056 ps
CPU time 1.87 seconds
Started Jul 15 05:51:50 PM PDT 24
Finished Jul 15 05:51:54 PM PDT 24
Peak memory 200040 kb
Host smart-ed1a6590-802d-4c42-87d2-98c6946f659f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985833895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.985833895
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1605938358
Short name T159
Test name
Test status
Simulation time 66789827 ps
CPU time 0.76 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:51 PM PDT 24
Peak memory 200040 kb
Host smart-cdb4fabe-1b73-4bfa-9f3a-32b69762fde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605938358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1605938358
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.645916133
Short name T179
Test name
Test status
Simulation time 67947831 ps
CPU time 0.76 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:51:50 PM PDT 24
Peak memory 199888 kb
Host smart-4eaf1949-cff3-41c1-9610-1540fa02c80a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645916133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.645916133
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1670924270
Short name T52
Test name
Test status
Simulation time 1231874641 ps
CPU time 5.93 seconds
Started Jul 15 05:51:48 PM PDT 24
Finished Jul 15 05:51:56 PM PDT 24
Peak memory 217772 kb
Host smart-93c0d4de-7851-4949-aff8-ed75ba30596a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670924270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1670924270
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.807110828
Short name T295
Test name
Test status
Simulation time 244498404 ps
CPU time 1.04 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 217492 kb
Host smart-2736308d-fb26-4ff3-9b34-9f4fa878778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807110828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.807110828
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3903630968
Short name T358
Test name
Test status
Simulation time 191332713 ps
CPU time 0.92 seconds
Started Jul 15 05:51:48 PM PDT 24
Finished Jul 15 05:51:50 PM PDT 24
Peak memory 199868 kb
Host smart-b70678f8-0f65-4b11-b200-e43ae4355c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903630968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3903630968
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3390683631
Short name T506
Test name
Test status
Simulation time 699250475 ps
CPU time 4.18 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 200264 kb
Host smart-77744105-1b6e-4031-9e20-a391a7b40eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390683631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3390683631
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1770452292
Short name T412
Test name
Test status
Simulation time 148619240 ps
CPU time 1.17 seconds
Started Jul 15 05:51:50 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 200108 kb
Host smart-b5059035-491e-4823-936a-5f6c74dce921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770452292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1770452292
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.968605891
Short name T224
Test name
Test status
Simulation time 201366375 ps
CPU time 1.38 seconds
Started Jul 15 05:51:50 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 200196 kb
Host smart-6087879a-afee-4523-ab62-9744ce337816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968605891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.968605891
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3920565604
Short name T256
Test name
Test status
Simulation time 849449208 ps
CPU time 4.32 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:56 PM PDT 24
Peak memory 200332 kb
Host smart-dabf6d6f-c517-4f4f-acdc-e00428ccba5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920565604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3920565604
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.660101259
Short name T222
Test name
Test status
Simulation time 360859854 ps
CPU time 2.12 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 200104 kb
Host smart-21944a87-3a5c-4459-95ae-e06fc51725d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660101259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.660101259
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2669165544
Short name T192
Test name
Test status
Simulation time 76315088 ps
CPU time 0.83 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:51:49 PM PDT 24
Peak memory 200036 kb
Host smart-f1c8dff4-9196-411a-970f-e0361c805e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669165544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2669165544
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1649220589
Short name T169
Test name
Test status
Simulation time 79407673 ps
CPU time 0.79 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 199884 kb
Host smart-a380e6ef-fec9-45f3-b568-5c51e73648fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649220589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1649220589
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2983388505
Short name T300
Test name
Test status
Simulation time 1877716255 ps
CPU time 8.15 seconds
Started Jul 15 05:51:48 PM PDT 24
Finished Jul 15 05:51:58 PM PDT 24
Peak memory 221584 kb
Host smart-e2acae02-586a-4310-bf03-bc646160916b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983388505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2983388505
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2375511594
Short name T232
Test name
Test status
Simulation time 245993899 ps
CPU time 1.07 seconds
Started Jul 15 05:51:48 PM PDT 24
Finished Jul 15 05:51:51 PM PDT 24
Peak memory 217492 kb
Host smart-8aa4e6bd-7fb3-45f8-91ec-2bd75ac68744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375511594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2375511594
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2077779107
Short name T450
Test name
Test status
Simulation time 230820915 ps
CPU time 0.96 seconds
Started Jul 15 05:51:51 PM PDT 24
Finished Jul 15 05:51:54 PM PDT 24
Peak memory 199904 kb
Host smart-0dd02c94-485b-4f46-a057-9d198f5d9dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077779107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2077779107
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3464950142
Short name T92
Test name
Test status
Simulation time 678996865 ps
CPU time 3.43 seconds
Started Jul 15 05:51:48 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 200364 kb
Host smart-9b2aa749-6680-42ac-81f8-c3f183da0dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464950142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3464950142
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3732018935
Short name T7
Test name
Test status
Simulation time 102951767 ps
CPU time 1.01 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:51:52 PM PDT 24
Peak memory 200072 kb
Host smart-a52fdde9-fd98-49ac-9623-72837555a753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732018935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3732018935
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1281213576
Short name T304
Test name
Test status
Simulation time 204689613 ps
CPU time 1.41 seconds
Started Jul 15 05:51:47 PM PDT 24
Finished Jul 15 05:51:50 PM PDT 24
Peak memory 200280 kb
Host smart-ea2626f1-3dff-4b27-ae69-e57c9586d20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281213576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1281213576
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1636394856
Short name T83
Test name
Test status
Simulation time 3042803085 ps
CPU time 12.7 seconds
Started Jul 15 05:51:49 PM PDT 24
Finished Jul 15 05:52:03 PM PDT 24
Peak memory 208516 kb
Host smart-2f9a8c4c-580a-45af-8220-228a0a5391ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636394856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1636394856
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3529817907
Short name T284
Test name
Test status
Simulation time 542874440 ps
CPU time 2.96 seconds
Started Jul 15 05:51:50 PM PDT 24
Finished Jul 15 05:51:55 PM PDT 24
Peak memory 200120 kb
Host smart-84b1802f-c6d3-4dc3-b824-5fa9c2916ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529817907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3529817907
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2208139776
Short name T140
Test name
Test status
Simulation time 183441531 ps
CPU time 1.18 seconds
Started Jul 15 05:51:48 PM PDT 24
Finished Jul 15 05:51:51 PM PDT 24
Peak memory 200092 kb
Host smart-03a57a98-5671-430b-bbf1-7af79c50f847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208139776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2208139776
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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