Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8335

1

T3

18

T5

19

T8

20

auto[1]

11150

1

T3

83

T4

4

T5

82

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6020	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6647	1			T1	1		T2	1		T3	27
reset_info_cp[2]	3019	1			T3	16		T4	1		T5	19
reset_info_cp[4]	3875	1			T3	17		T4	1		T5	13
reset_info_cp[8]	92	1			T72	1		T31	1		T74	1
reset_info_cp[16]	115	1			T3	2		T8	1		T23	1
reset_info_cp[32]	105	1			T3	1		T5	1		T38	2
reset_info_cp[64]	107	1			T8	1		T9	1		T10	1
reset_info_cp[128]	125	1			T3	1		T5	1		T8	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3205	1			T3	18		T5	19		T8	20
reset_info_cp[1]	auto[1]	2822	1			T3	8		T4	1		T5	7
reset_info_cp[2]	auto[0]	940	1			T9	4		T11	8		T23	4
reset_info_cp[2]	auto[1]	2079	1			T3	16		T4	1		T5	19
reset_info_cp[4]	auto[0]	1410	1			T9	3		T11	6		T23	5
reset_info_cp[4]	auto[1]	2465	1			T3	17		T4	1		T5	13
reset_info_cp[8]	auto[0]	41	1			T72	1		T75	3		T87	1
reset_info_cp[8]	auto[1]	51	1			T31	1		T74	1		T32	1
reset_info_cp[16]	auto[0]	40	1			T23	1		T37	2		T75	2
reset_info_cp[16]	auto[1]	75	1			T3	2		T8	1		T37	1
reset_info_cp[32]	auto[0]	46	1			T38	1		T72	2		T74	2
reset_info_cp[32]	auto[1]	59	1			T3	1		T5	1		T38	1
reset_info_cp[64]	auto[0]	47	1			T9	1		T38	3		T72	1
reset_info_cp[64]	auto[1]	60	1			T8	1		T10	1		T37	1
reset_info_cp[128]	auto[0]	51	1			T11	1		T23	1		T38	1
reset_info_cp[128]	auto[1]	74	1			T3	1		T5	1		T8	1