Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T532 /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2970710922 Jul 16 07:22:34 PM PDT 24 Jul 16 07:23:17 PM PDT 24 244161983 ps
T533 /workspace/coverage/default/4.rstmgr_por_stretcher.2115009469 Jul 16 07:21:58 PM PDT 24 Jul 16 07:22:06 PM PDT 24 112540139 ps
T534 /workspace/coverage/default/6.rstmgr_alert_test.559945489 Jul 16 07:22:24 PM PDT 24 Jul 16 07:23:00 PM PDT 24 88949982 ps
T535 /workspace/coverage/default/9.rstmgr_stress_all.1058123592 Jul 16 07:22:34 PM PDT 24 Jul 16 07:23:33 PM PDT 24 5480739217 ps
T536 /workspace/coverage/default/43.rstmgr_stress_all.1864721906 Jul 16 07:24:40 PM PDT 24 Jul 16 07:26:07 PM PDT 24 9337305183 ps
T46 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3328365781 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:56 PM PDT 24 258620511 ps
T47 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2572578290 Jul 16 07:15:57 PM PDT 24 Jul 16 07:16:56 PM PDT 24 800955673 ps
T51 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3491200933 Jul 16 07:15:58 PM PDT 24 Jul 16 07:16:55 PM PDT 24 479330655 ps
T48 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2312305533 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:56 PM PDT 24 152452419 ps
T52 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2966693414 Jul 16 07:15:53 PM PDT 24 Jul 16 07:16:52 PM PDT 24 571207773 ps
T94 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2015492787 Jul 16 07:15:49 PM PDT 24 Jul 16 07:16:46 PM PDT 24 64954467 ps
T53 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2653738664 Jul 16 07:15:53 PM PDT 24 Jul 16 07:16:50 PM PDT 24 191453470 ps
T58 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.344942148 Jul 16 07:16:19 PM PDT 24 Jul 16 07:17:04 PM PDT 24 118860207 ps
T49 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3802006408 Jul 16 07:16:07 PM PDT 24 Jul 16 07:16:58 PM PDT 24 879988994 ps
T59 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.119798400 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:58 PM PDT 24 884496768 ps
T78 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2750692877 Jul 16 07:16:20 PM PDT 24 Jul 16 07:17:02 PM PDT 24 137657325 ps
T79 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.342014529 Jul 16 07:16:06 PM PDT 24 Jul 16 07:16:59 PM PDT 24 1118417709 ps
T80 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1322859788 Jul 16 07:15:49 PM PDT 24 Jul 16 07:16:46 PM PDT 24 186861765 ps
T95 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3907542288 Jul 16 07:16:18 PM PDT 24 Jul 16 07:17:02 PM PDT 24 57033833 ps
T81 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2974155587 Jul 16 07:15:57 PM PDT 24 Jul 16 07:16:53 PM PDT 24 305190692 ps
T82 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2525193105 Jul 16 07:16:05 PM PDT 24 Jul 16 07:16:56 PM PDT 24 217023097 ps
T537 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2339326057 Jul 16 07:16:14 PM PDT 24 Jul 16 07:17:01 PM PDT 24 73404812 ps
T83 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2004371386 Jul 16 07:16:48 PM PDT 24 Jul 16 07:17:13 PM PDT 24 300781549 ps
T538 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2297867449 Jul 16 07:15:57 PM PDT 24 Jul 16 07:16:52 PM PDT 24 124371182 ps
T96 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4248918478 Jul 16 07:15:42 PM PDT 24 Jul 16 07:16:40 PM PDT 24 98153353 ps
T539 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.118938431 Jul 16 07:16:04 PM PDT 24 Jul 16 07:16:58 PM PDT 24 783740898 ps
T97 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3438107422 Jul 16 07:16:18 PM PDT 24 Jul 16 07:17:03 PM PDT 24 133814128 ps
T540 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1215569551 Jul 16 07:16:05 PM PDT 24 Jul 16 07:16:57 PM PDT 24 131455163 ps
T541 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2026029607 Jul 16 07:16:09 PM PDT 24 Jul 16 07:16:57 PM PDT 24 275284382 ps
T542 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3984274956 Jul 16 07:15:49 PM PDT 24 Jul 16 07:16:48 PM PDT 24 773542391 ps
T543 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3715799247 Jul 16 07:15:54 PM PDT 24 Jul 16 07:16:52 PM PDT 24 800366632 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4277443637 Jul 16 07:15:39 PM PDT 24 Jul 16 07:16:39 PM PDT 24 466035002 ps
T98 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2414039605 Jul 16 07:15:37 PM PDT 24 Jul 16 07:16:34 PM PDT 24 86243279 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1580618053 Jul 16 07:15:50 PM PDT 24 Jul 16 07:16:48 PM PDT 24 195984065 ps
T108 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3756420081 Jul 16 07:15:57 PM PDT 24 Jul 16 07:16:53 PM PDT 24 425566748 ps
T99 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3410039605 Jul 16 07:15:49 PM PDT 24 Jul 16 07:16:46 PM PDT 24 79736600 ps
T100 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2345699466 Jul 16 07:16:02 PM PDT 24 Jul 16 07:16:53 PM PDT 24 251615280 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.280348187 Jul 16 07:15:38 PM PDT 24 Jul 16 07:16:37 PM PDT 24 471364611 ps
T547 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3644028066 Jul 16 07:15:57 PM PDT 24 Jul 16 07:16:53 PM PDT 24 123699495 ps
T548 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.102695093 Jul 16 07:15:50 PM PDT 24 Jul 16 07:16:47 PM PDT 24 233584260 ps
T549 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1281590366 Jul 16 07:15:51 PM PDT 24 Jul 16 07:16:48 PM PDT 24 147624021 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1620536966 Jul 16 07:15:59 PM PDT 24 Jul 16 07:16:53 PM PDT 24 222533862 ps
T101 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.448125405 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:55 PM PDT 24 80290648 ps
T551 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.163546026 Jul 16 07:16:06 PM PDT 24 Jul 16 07:16:57 PM PDT 24 181623679 ps
T552 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.842158315 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:56 PM PDT 24 110662226 ps
T553 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.437050415 Jul 16 07:16:20 PM PDT 24 Jul 16 07:17:05 PM PDT 24 192787003 ps
T554 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.398054399 Jul 16 07:16:20 PM PDT 24 Jul 16 07:17:05 PM PDT 24 186322663 ps
T555 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.678432354 Jul 16 07:16:01 PM PDT 24 Jul 16 07:16:56 PM PDT 24 220704725 ps
T556 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.860793806 Jul 16 07:16:15 PM PDT 24 Jul 16 07:17:02 PM PDT 24 285693077 ps
T557 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1027472070 Jul 16 07:15:54 PM PDT 24 Jul 16 07:16:49 PM PDT 24 140122110 ps
T558 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1009352014 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:55 PM PDT 24 83617647 ps
T559 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1897291168 Jul 16 07:15:54 PM PDT 24 Jul 16 07:16:53 PM PDT 24 485536193 ps
T560 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.769525936 Jul 16 07:15:57 PM PDT 24 Jul 16 07:16:51 PM PDT 24 69563949 ps
T561 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1351674254 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:55 PM PDT 24 122283474 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1770792015 Jul 16 07:15:40 PM PDT 24 Jul 16 07:16:39 PM PDT 24 565951693 ps
T563 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.616572905 Jul 16 07:16:19 PM PDT 24 Jul 16 07:17:04 PM PDT 24 247898498 ps
T564 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2103021586 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:55 PM PDT 24 72868284 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3018454438 Jul 16 07:15:59 PM PDT 24 Jul 16 07:16:53 PM PDT 24 143114491 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4215696649 Jul 16 07:15:59 PM PDT 24 Jul 16 07:16:53 PM PDT 24 124616469 ps
T567 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4031158293 Jul 16 07:16:01 PM PDT 24 Jul 16 07:16:56 PM PDT 24 127994532 ps
T102 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4093209913 Jul 16 07:16:00 PM PDT 24 Jul 16 07:16:55 PM PDT 24 994506572 ps
T568 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1922384684 Jul 16 07:16:19 PM PDT 24 Jul 16 07:17:04 PM PDT 24 254446020 ps
T569 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2850077386 Jul 16 07:15:41 PM PDT 24 Jul 16 07:16:39 PM PDT 24 115736119 ps
T86 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2853328844 Jul 16 07:16:00 PM PDT 24 Jul 16 07:16:53 PM PDT 24 66285963 ps
T570 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1800475334 Jul 16 07:15:56 PM PDT 24 Jul 16 07:16:51 PM PDT 24 197906636 ps
T571 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3481659099 Jul 16 07:15:58 PM PDT 24 Jul 16 07:16:54 PM PDT 24 348777633 ps
T572 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4211875364 Jul 16 07:15:54 PM PDT 24 Jul 16 07:16:49 PM PDT 24 74691655 ps
T573 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2552845296 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:56 PM PDT 24 140784067 ps
T574 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3155894876 Jul 16 07:16:15 PM PDT 24 Jul 16 07:17:01 PM PDT 24 80027724 ps
T575 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1851255695 Jul 16 07:16:04 PM PDT 24 Jul 16 07:16:56 PM PDT 24 171708263 ps
T103 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2637407365 Jul 16 07:15:55 PM PDT 24 Jul 16 07:16:50 PM PDT 24 426085391 ps
T105 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3020592657 Jul 16 07:16:02 PM PDT 24 Jul 16 07:16:53 PM PDT 24 480526051 ps
T576 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1562729441 Jul 16 07:16:02 PM PDT 24 Jul 16 07:16:52 PM PDT 24 64874364 ps
T577 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4162849267 Jul 16 07:16:15 PM PDT 24 Jul 16 07:17:01 PM PDT 24 122455349 ps
T578 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4212260284 Jul 16 07:16:18 PM PDT 24 Jul 16 07:17:02 PM PDT 24 183611399 ps
T579 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.929635664 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:56 PM PDT 24 131485430 ps
T580 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.315611435 Jul 16 07:16:19 PM PDT 24 Jul 16 07:17:04 PM PDT 24 152697553 ps
T581 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4254942624 Jul 16 07:15:54 PM PDT 24 Jul 16 07:16:49 PM PDT 24 133740500 ps
T582 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.92616661 Jul 16 07:16:01 PM PDT 24 Jul 16 07:16:53 PM PDT 24 111358739 ps
T583 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2921513965 Jul 16 07:16:05 PM PDT 24 Jul 16 07:16:57 PM PDT 24 248208251 ps
T584 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.985516145 Jul 16 07:16:01 PM PDT 24 Jul 16 07:16:56 PM PDT 24 57525190 ps
T585 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1061169392 Jul 16 07:16:06 PM PDT 24 Jul 16 07:16:56 PM PDT 24 80912531 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.61368621 Jul 16 07:15:41 PM PDT 24 Jul 16 07:16:39 PM PDT 24 149249058 ps
T587 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.543386491 Jul 16 07:16:04 PM PDT 24 Jul 16 07:16:57 PM PDT 24 598448476 ps
T588 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2275416964 Jul 16 07:15:57 PM PDT 24 Jul 16 07:16:51 PM PDT 24 83734890 ps
T109 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1033041033 Jul 16 07:16:09 PM PDT 24 Jul 16 07:16:58 PM PDT 24 902737668 ps
T589 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.384000046 Jul 16 07:16:15 PM PDT 24 Jul 16 07:17:00 PM PDT 24 82986124 ps
T590 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4125680405 Jul 16 07:16:18 PM PDT 24 Jul 16 07:17:02 PM PDT 24 65578154 ps
T110 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1408377530 Jul 16 07:16:15 PM PDT 24 Jul 16 07:17:03 PM PDT 24 795907179 ps
T591 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1305046449 Jul 16 07:15:53 PM PDT 24 Jul 16 07:16:48 PM PDT 24 62439032 ps
T592 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.636690590 Jul 16 07:16:01 PM PDT 24 Jul 16 07:16:56 PM PDT 24 63155387 ps
T593 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1807237029 Jul 16 07:15:51 PM PDT 24 Jul 16 07:16:47 PM PDT 24 73575475 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2810718352 Jul 16 07:15:50 PM PDT 24 Jul 16 07:16:47 PM PDT 24 209740025 ps
T104 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3191393939 Jul 16 07:15:56 PM PDT 24 Jul 16 07:16:52 PM PDT 24 425997160 ps
T595 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4172834223 Jul 16 07:16:18 PM PDT 24 Jul 16 07:17:03 PM PDT 24 108488555 ps
T596 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3057118702 Jul 16 07:16:15 PM PDT 24 Jul 16 07:17:01 PM PDT 24 124540488 ps
T597 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4017155154 Jul 16 07:16:09 PM PDT 24 Jul 16 07:16:58 PM PDT 24 357827578 ps
T598 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4065486368 Jul 16 07:15:41 PM PDT 24 Jul 16 07:16:46 PM PDT 24 1531539338 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3620642321 Jul 16 07:15:41 PM PDT 24 Jul 16 07:16:43 PM PDT 24 1034880204 ps
T600 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.953897834 Jul 16 07:16:18 PM PDT 24 Jul 16 07:17:03 PM PDT 24 178443608 ps
T601 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1901443798 Jul 16 07:15:58 PM PDT 24 Jul 16 07:16:53 PM PDT 24 130900325 ps
T602 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1710455314 Jul 16 07:16:04 PM PDT 24 Jul 16 07:16:56 PM PDT 24 111076731 ps
T603 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1257173762 Jul 16 07:16:20 PM PDT 24 Jul 16 07:17:03 PM PDT 24 144402806 ps
T604 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2959911208 Jul 16 07:15:42 PM PDT 24 Jul 16 07:16:41 PM PDT 24 158279193 ps
T605 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1264853371 Jul 16 07:16:20 PM PDT 24 Jul 16 07:17:05 PM PDT 24 473118097 ps
T606 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.224002260 Jul 16 07:16:08 PM PDT 24 Jul 16 07:16:57 PM PDT 24 470737771 ps
T607 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.322920413 Jul 16 07:15:50 PM PDT 24 Jul 16 07:16:48 PM PDT 24 791077197 ps
T608 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.56213464 Jul 16 07:16:19 PM PDT 24 Jul 16 07:17:03 PM PDT 24 63413671 ps
T609 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4288021467 Jul 16 07:15:58 PM PDT 24 Jul 16 07:16:52 PM PDT 24 103916352 ps
T610 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2684484531 Jul 16 07:16:07 PM PDT 24 Jul 16 07:16:56 PM PDT 24 69855370 ps
T611 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3096087799 Jul 16 07:15:49 PM PDT 24 Jul 16 07:16:47 PM PDT 24 461408196 ps
T612 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3825845323 Jul 16 07:16:03 PM PDT 24 Jul 16 07:16:56 PM PDT 24 119704174 ps
T613 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3145583547 Jul 16 07:16:06 PM PDT 24 Jul 16 07:16:57 PM PDT 24 221625697 ps
T614 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2126254651 Jul 16 07:16:01 PM PDT 24 Jul 16 07:16:58 PM PDT 24 1183869704 ps
T615 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1242558538 Jul 16 07:15:37 PM PDT 24 Jul 16 07:16:34 PM PDT 24 85114677 ps
T616 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3658878022 Jul 16 07:15:54 PM PDT 24 Jul 16 07:16:49 PM PDT 24 140610240 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2366908903 Jul 16 07:15:53 PM PDT 24 Jul 16 07:16:50 PM PDT 24 354406483 ps
T618 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4097265480 Jul 16 07:16:09 PM PDT 24 Jul 16 07:16:57 PM PDT 24 269070053 ps
T619 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.438420271 Jul 16 07:16:18 PM PDT 24 Jul 16 07:17:03 PM PDT 24 471582039 ps
T620 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3197296198 Jul 16 07:15:49 PM PDT 24 Jul 16 07:16:46 PM PDT 24 104743717 ps

Test location /workspace/coverage/default/40.rstmgr_stress_all.162231342
Short name T9
Test name
Test status
Simulation time 1436835800 ps
CPU time 6.24 seconds
Started Jul 16 07:24:33 PM PDT 24
Finished Jul 16 07:25:27 PM PDT 24
Peak memory 200488 kb
Host smart-7f9de320-1312-4e75-94bb-72eeb55b405a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162231342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.162231342
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.4235420802
Short name T2
Test name
Test status
Simulation time 336623089 ps
CPU time 2.05 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:16 PM PDT 24
Peak memory 200112 kb
Host smart-c89afdc6-78d7-43d2-b68c-d0b2c5720442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235420802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4235420802
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.342014529
Short name T79
Test name
Test status
Simulation time 1118417709 ps
CPU time 3.31 seconds
Started Jul 16 07:16:06 PM PDT 24
Finished Jul 16 07:16:59 PM PDT 24
Peak memory 200492 kb
Host smart-2709a15b-ce87-4fda-bc27-9cb8f8c4fa6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342014529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.342014529
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3436435747
Short name T3
Test name
Test status
Simulation time 1227451938 ps
CPU time 5.55 seconds
Started Jul 16 07:23:08 PM PDT 24
Finished Jul 16 07:23:46 PM PDT 24
Peak memory 217640 kb
Host smart-f98c588d-81d5-4792-aeb6-595ebd3f2867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436435747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3436435747
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.829827055
Short name T61
Test name
Test status
Simulation time 8406465829 ps
CPU time 12.35 seconds
Started Jul 16 07:21:40 PM PDT 24
Finished Jul 16 07:21:59 PM PDT 24
Peak memory 217092 kb
Host smart-31c30e91-f19d-46ec-8f25-0f365cfb72e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829827055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.829827055
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2974155587
Short name T81
Test name
Test status
Simulation time 305190692 ps
CPU time 2.01 seconds
Started Jul 16 07:15:57 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 208512 kb
Host smart-8f80655c-9117-47d2-a5a7-e149962695be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974155587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2974155587
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.451151539
Short name T75
Test name
Test status
Simulation time 14924696137 ps
CPU time 48.51 seconds
Started Jul 16 07:21:41 PM PDT 24
Finished Jul 16 07:22:37 PM PDT 24
Peak memory 208636 kb
Host smart-0b8b227f-eaf0-4384-8dde-5c0a185859f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451151539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.451151539
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2737231262
Short name T114
Test name
Test status
Simulation time 85365434 ps
CPU time 0.84 seconds
Started Jul 16 07:23:02 PM PDT 24
Finished Jul 16 07:23:39 PM PDT 24
Peak memory 199972 kb
Host smart-a3b9f67f-ac47-4d5a-974b-9fcf5ef19560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737231262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2737231262
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.310453787
Short name T5
Test name
Test status
Simulation time 2364515107 ps
CPU time 7.63 seconds
Started Jul 16 07:22:35 PM PDT 24
Finished Jul 16 07:23:26 PM PDT 24
Peak memory 221596 kb
Host smart-dfeda260-3d3b-4f90-b807-20f1aafba610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310453787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.310453787
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1195683874
Short name T4
Test name
Test status
Simulation time 170903910 ps
CPU time 1.13 seconds
Started Jul 16 07:22:36 PM PDT 24
Finished Jul 16 07:23:20 PM PDT 24
Peak memory 200152 kb
Host smart-0c7f9cef-2af1-4c71-81c4-c3ac5739fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195683874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1195683874
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3446815327
Short name T159
Test name
Test status
Simulation time 165413294 ps
CPU time 1.31 seconds
Started Jul 16 07:21:58 PM PDT 24
Finished Jul 16 07:22:07 PM PDT 24
Peak memory 200352 kb
Host smart-74f49f77-1567-4a77-845d-385bf53f8371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446815327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3446815327
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4277443637
Short name T544
Test name
Test status
Simulation time 466035002 ps
CPU time 3.3 seconds
Started Jul 16 07:15:39 PM PDT 24
Finished Jul 16 07:16:39 PM PDT 24
Peak memory 208664 kb
Host smart-b3e0d51f-78f7-497e-84f9-057cd2c0e646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277443637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.4277443637
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1264853371
Short name T605
Test name
Test status
Simulation time 473118097 ps
CPU time 1.84 seconds
Started Jul 16 07:16:20 PM PDT 24
Finished Jul 16 07:17:05 PM PDT 24
Peak memory 200544 kb
Host smart-841cb710-d1e0-4665-8e8c-178defe3dd5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264853371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1264853371
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1115217108
Short name T121
Test name
Test status
Simulation time 1906294887 ps
CPU time 7.22 seconds
Started Jul 16 07:21:40 PM PDT 24
Finished Jul 16 07:21:55 PM PDT 24
Peak memory 217724 kb
Host smart-0c8cbccc-87ab-4290-a807-6fe25defeef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115217108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1115217108
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2414039605
Short name T98
Test name
Test status
Simulation time 86243279 ps
CPU time 0.87 seconds
Started Jul 16 07:15:37 PM PDT 24
Finished Jul 16 07:16:34 PM PDT 24
Peak memory 200276 kb
Host smart-6347540c-c246-4648-bfd6-b3e59d6f2e05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414039605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2414039605
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1628665169
Short name T15
Test name
Test status
Simulation time 100029292 ps
CPU time 0.74 seconds
Started Jul 16 07:22:56 PM PDT 24
Finished Jul 16 07:23:36 PM PDT 24
Peak memory 199972 kb
Host smart-f1fc73ae-9c9d-49b0-a433-04a3bb854a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628665169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1628665169
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3111117461
Short name T32
Test name
Test status
Simulation time 1227416833 ps
CPU time 6.04 seconds
Started Jul 16 07:22:45 PM PDT 24
Finished Jul 16 07:23:34 PM PDT 24
Peak memory 217804 kb
Host smart-d0b57274-150f-4e09-b25f-8176c820f07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111117461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3111117461
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3020592657
Short name T105
Test name
Test status
Simulation time 480526051 ps
CPU time 1.85 seconds
Started Jul 16 07:16:02 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 200508 kb
Host smart-dc48fc76-040a-4a77-b6af-0923583ea1ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020592657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3020592657
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2959911208
Short name T604
Test name
Test status
Simulation time 158279193 ps
CPU time 2 seconds
Started Jul 16 07:15:42 PM PDT 24
Finished Jul 16 07:16:41 PM PDT 24
Peak memory 200364 kb
Host smart-7ca8bd7c-2736-440a-b245-4004b69bdee0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959911208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
959911208
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3620642321
Short name T599
Test name
Test status
Simulation time 1034880204 ps
CPU time 4.85 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:43 PM PDT 24
Peak memory 200416 kb
Host smart-738f396e-f689-4728-b313-2e63c1ef7027
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620642321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
620642321
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.61368621
Short name T586
Test name
Test status
Simulation time 149249058 ps
CPU time 0.95 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:39 PM PDT 24
Peak memory 200268 kb
Host smart-92ea509e-df9f-4f28-85fc-8ee6f02c99c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61368621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.61368621
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2850077386
Short name T569
Test name
Test status
Simulation time 115736119 ps
CPU time 0.96 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:39 PM PDT 24
Peak memory 200520 kb
Host smart-ee0f0030-ecf6-4231-8ade-6147a78633a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850077386 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2850077386
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4248918478
Short name T96
Test name
Test status
Simulation time 98153353 ps
CPU time 1.17 seconds
Started Jul 16 07:15:42 PM PDT 24
Finished Jul 16 07:16:40 PM PDT 24
Peak memory 200464 kb
Host smart-34cdbb56-d82e-4b22-90ed-5fd10796549e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248918478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.4248918478
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3984274956
Short name T542
Test name
Test status
Simulation time 773542391 ps
CPU time 2.65 seconds
Started Jul 16 07:15:49 PM PDT 24
Finished Jul 16 07:16:48 PM PDT 24
Peak memory 200440 kb
Host smart-366b72aa-e5c4-4fde-a9f4-5a0d9ff43081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984274956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3984274956
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2810718352
Short name T594
Test name
Test status
Simulation time 209740025 ps
CPU time 1.57 seconds
Started Jul 16 07:15:50 PM PDT 24
Finished Jul 16 07:16:47 PM PDT 24
Peak memory 200316 kb
Host smart-b6973ca8-307f-4728-90a1-64172fe6c476
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810718352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
810718352
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4065486368
Short name T598
Test name
Test status
Simulation time 1531539338 ps
CPU time 8.12 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:46 PM PDT 24
Peak memory 200652 kb
Host smart-434bfee7-2233-498f-870c-8ac0d6b49cef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065486368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.4
065486368
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3197296198
Short name T620
Test name
Test status
Simulation time 104743717 ps
CPU time 0.85 seconds
Started Jul 16 07:15:49 PM PDT 24
Finished Jul 16 07:16:46 PM PDT 24
Peak memory 200232 kb
Host smart-3306f4f8-804d-469c-b7b7-8575ee49014d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197296198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
197296198
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1580618053
Short name T545
Test name
Test status
Simulation time 195984065 ps
CPU time 1.21 seconds
Started Jul 16 07:15:50 PM PDT 24
Finished Jul 16 07:16:48 PM PDT 24
Peak memory 208572 kb
Host smart-ffb8faa9-9680-4096-aa02-ea54494bdfdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580618053 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1580618053
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2015492787
Short name T94
Test name
Test status
Simulation time 64954467 ps
CPU time 0.73 seconds
Started Jul 16 07:15:49 PM PDT 24
Finished Jul 16 07:16:46 PM PDT 24
Peak memory 200160 kb
Host smart-76ce5e6d-d96d-4e67-9f00-91f0684897b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015492787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2015492787
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1242558538
Short name T615
Test name
Test status
Simulation time 85114677 ps
CPU time 0.96 seconds
Started Jul 16 07:15:37 PM PDT 24
Finished Jul 16 07:16:34 PM PDT 24
Peak memory 200448 kb
Host smart-c5bee361-d423-4f98-8d84-60a704dd6fc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242558538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1242558538
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1770792015
Short name T562
Test name
Test status
Simulation time 565951693 ps
CPU time 3.54 seconds
Started Jul 16 07:15:40 PM PDT 24
Finished Jul 16 07:16:39 PM PDT 24
Peak memory 208780 kb
Host smart-e2cfff2f-d5be-4f13-978a-b55d23007ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770792015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1770792015
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.280348187
Short name T546
Test name
Test status
Simulation time 471364611 ps
CPU time 1.81 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:37 PM PDT 24
Peak memory 200492 kb
Host smart-392f0340-4594-45b7-9498-16d1ec2eb081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280348187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
280348187
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.163546026
Short name T551
Test name
Test status
Simulation time 181623679 ps
CPU time 1.69 seconds
Started Jul 16 07:16:06 PM PDT 24
Finished Jul 16 07:16:57 PM PDT 24
Peak memory 208864 kb
Host smart-7db6f4cb-8cdf-4515-8619-8c7d590fa0a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163546026 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.163546026
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.56213464
Short name T608
Test name
Test status
Simulation time 63413671 ps
CPU time 0.79 seconds
Started Jul 16 07:16:19 PM PDT 24
Finished Jul 16 07:17:03 PM PDT 24
Peak memory 200276 kb
Host smart-b4c71698-eb47-4446-873a-8cb1e024d803
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56213464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.56213464
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3438107422
Short name T97
Test name
Test status
Simulation time 133814128 ps
CPU time 1.14 seconds
Started Jul 16 07:16:18 PM PDT 24
Finished Jul 16 07:17:03 PM PDT 24
Peak memory 200320 kb
Host smart-feeaba23-cd00-4107-8199-0bfd3db9e9a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438107422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3438107422
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2004371386
Short name T83
Test name
Test status
Simulation time 300781549 ps
CPU time 2.1 seconds
Started Jul 16 07:16:48 PM PDT 24
Finished Jul 16 07:17:13 PM PDT 24
Peak memory 208616 kb
Host smart-a14c7113-b051-40d8-95d5-99fed05353f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004371386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2004371386
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.543386491
Short name T587
Test name
Test status
Simulation time 598448476 ps
CPU time 2.05 seconds
Started Jul 16 07:16:04 PM PDT 24
Finished Jul 16 07:16:57 PM PDT 24
Peak memory 200548 kb
Host smart-5fdee107-091a-42ec-89a8-2a316fefe589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543386491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.543386491
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2750692877
Short name T78
Test name
Test status
Simulation time 137657325 ps
CPU time 1.38 seconds
Started Jul 16 07:16:20 PM PDT 24
Finished Jul 16 07:17:02 PM PDT 24
Peak memory 208848 kb
Host smart-298ae3b3-ecb4-4cce-96e5-ce551982d242
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750692877 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2750692877
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4125680405
Short name T590
Test name
Test status
Simulation time 65578154 ps
CPU time 0.79 seconds
Started Jul 16 07:16:18 PM PDT 24
Finished Jul 16 07:17:02 PM PDT 24
Peak memory 200232 kb
Host smart-144c9dd6-39d2-4975-8aa2-cfba2d337681
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125680405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4125680405
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2312305533
Short name T48
Test name
Test status
Simulation time 152452419 ps
CPU time 1.16 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200336 kb
Host smart-945a2c28-ccc3-4e6d-babd-4f3526ea2d81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312305533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2312305533
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1215569551
Short name T540
Test name
Test status
Simulation time 131455163 ps
CPU time 1.78 seconds
Started Jul 16 07:16:05 PM PDT 24
Finished Jul 16 07:16:57 PM PDT 24
Peak memory 200440 kb
Host smart-c624a5ab-212e-4b34-8cc4-596345c7d5c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215569551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1215569551
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.224002260
Short name T606
Test name
Test status
Simulation time 470737771 ps
CPU time 1.84 seconds
Started Jul 16 07:16:08 PM PDT 24
Finished Jul 16 07:16:57 PM PDT 24
Peak memory 200480 kb
Host smart-acf8a022-d93a-49bf-853a-3fa4c69e9a77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224002260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.224002260
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.929635664
Short name T579
Test name
Test status
Simulation time 131485430 ps
CPU time 1.31 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 208552 kb
Host smart-07dee006-0546-4d61-bf0a-639166a9efd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929635664 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.929635664
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1009352014
Short name T558
Test name
Test status
Simulation time 83617647 ps
CPU time 0.87 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:55 PM PDT 24
Peak memory 200288 kb
Host smart-5ea11705-dba8-45a0-90dd-e0c624a1c29a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009352014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1009352014
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4097265480
Short name T618
Test name
Test status
Simulation time 269070053 ps
CPU time 1.6 seconds
Started Jul 16 07:16:09 PM PDT 24
Finished Jul 16 07:16:57 PM PDT 24
Peak memory 200016 kb
Host smart-875ddfbe-76a7-44f3-82be-61dcbdcb5d87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097265480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4097265480
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.92616661
Short name T582
Test name
Test status
Simulation time 111358739 ps
CPU time 1.4 seconds
Started Jul 16 07:16:01 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 208564 kb
Host smart-87838f31-a420-4ac4-9b41-6ef59c30d663
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92616661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.92616661
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2126254651
Short name T614
Test name
Test status
Simulation time 1183869704 ps
CPU time 3.54 seconds
Started Jul 16 07:16:01 PM PDT 24
Finished Jul 16 07:16:58 PM PDT 24
Peak memory 200540 kb
Host smart-a9c8975a-b458-47b1-8168-7cc63e097fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126254651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2126254651
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4212260284
Short name T578
Test name
Test status
Simulation time 183611399 ps
CPU time 1.26 seconds
Started Jul 16 07:16:18 PM PDT 24
Finished Jul 16 07:17:02 PM PDT 24
Peak memory 208640 kb
Host smart-8eec6e84-cc9c-4845-aec7-f25ccf3be79d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212260284 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4212260284
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3907542288
Short name T95
Test name
Test status
Simulation time 57033833 ps
CPU time 0.73 seconds
Started Jul 16 07:16:18 PM PDT 24
Finished Jul 16 07:17:02 PM PDT 24
Peak memory 200240 kb
Host smart-1f307bcd-cfd2-4ef6-a436-302b1ebe49e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907542288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3907542288
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2345699466
Short name T100
Test name
Test status
Simulation time 251615280 ps
CPU time 1.56 seconds
Started Jul 16 07:16:02 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 200472 kb
Host smart-c8c5cb65-539d-4027-afb1-a389bfe5b468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345699466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2345699466
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.398054399
Short name T554
Test name
Test status
Simulation time 186322663 ps
CPU time 2.55 seconds
Started Jul 16 07:16:20 PM PDT 24
Finished Jul 16 07:17:05 PM PDT 24
Peak memory 208696 kb
Host smart-e5ee6d67-51a2-44c2-b587-6e6e30d78fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398054399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.398054399
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3802006408
Short name T49
Test name
Test status
Simulation time 879988994 ps
CPU time 3.12 seconds
Started Jul 16 07:16:07 PM PDT 24
Finished Jul 16 07:16:58 PM PDT 24
Peak memory 200496 kb
Host smart-9412afa1-a0b6-4baf-8a67-ef88cae1b401
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802006408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3802006408
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.953897834
Short name T600
Test name
Test status
Simulation time 178443608 ps
CPU time 1.58 seconds
Started Jul 16 07:16:18 PM PDT 24
Finished Jul 16 07:17:03 PM PDT 24
Peak memory 208756 kb
Host smart-fae5f161-2dd0-4f89-a374-5bef1f031173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953897834 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.953897834
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.448125405
Short name T101
Test name
Test status
Simulation time 80290648 ps
CPU time 0.83 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:55 PM PDT 24
Peak memory 200232 kb
Host smart-1d495abb-5b47-4051-bcce-e2663f07a283
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448125405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.448125405
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1710455314
Short name T602
Test name
Test status
Simulation time 111076731 ps
CPU time 1.02 seconds
Started Jul 16 07:16:04 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200360 kb
Host smart-9462eab0-0172-4b12-9fd4-45b50f1a31f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710455314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1710455314
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.616572905
Short name T563
Test name
Test status
Simulation time 247898498 ps
CPU time 2.06 seconds
Started Jul 16 07:16:19 PM PDT 24
Finished Jul 16 07:17:04 PM PDT 24
Peak memory 208624 kb
Host smart-580a667f-142a-4a24-85f3-0bee006ac893
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616572905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.616572905
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.344942148
Short name T58
Test name
Test status
Simulation time 118860207 ps
CPU time 1.29 seconds
Started Jul 16 07:16:19 PM PDT 24
Finished Jul 16 07:17:04 PM PDT 24
Peak memory 208612 kb
Host smart-1590a986-5416-4338-87b6-92f0aa4d1b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344942148 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.344942148
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.985516145
Short name T584
Test name
Test status
Simulation time 57525190 ps
CPU time 0.76 seconds
Started Jul 16 07:16:01 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200268 kb
Host smart-a92213ac-45f0-41ef-a60e-4a19ed70a886
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985516145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.985516145
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3328365781
Short name T46
Test name
Test status
Simulation time 258620511 ps
CPU time 1.56 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200448 kb
Host smart-21ee3346-8855-4e33-a117-46e19c1c29d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328365781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3328365781
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2026029607
Short name T541
Test name
Test status
Simulation time 275284382 ps
CPU time 1.91 seconds
Started Jul 16 07:16:09 PM PDT 24
Finished Jul 16 07:16:57 PM PDT 24
Peak memory 216692 kb
Host smart-080f2a11-953d-4bcc-8fc5-e87fe229841f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026029607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2026029607
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.119798400
Short name T59
Test name
Test status
Simulation time 884496768 ps
CPU time 3.14 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:58 PM PDT 24
Peak memory 200520 kb
Host smart-73c432b5-591b-48e4-9ba0-7f70a8d2bb4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119798400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.119798400
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1851255695
Short name T575
Test name
Test status
Simulation time 171708263 ps
CPU time 1.58 seconds
Started Jul 16 07:16:04 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 208644 kb
Host smart-9e9b4b14-b60f-4dbd-ab8b-42a73f4fb858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851255695 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1851255695
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1061169392
Short name T585
Test name
Test status
Simulation time 80912531 ps
CPU time 0.84 seconds
Started Jul 16 07:16:06 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200212 kb
Host smart-0ccd1498-bfab-41c1-802f-325a4746abd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061169392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1061169392
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1922384684
Short name T568
Test name
Test status
Simulation time 254446020 ps
CPU time 1.59 seconds
Started Jul 16 07:16:19 PM PDT 24
Finished Jul 16 07:17:04 PM PDT 24
Peak memory 200540 kb
Host smart-b9e62ccb-a658-4852-83f4-c68519b3cb72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922384684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1922384684
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.315611435
Short name T580
Test name
Test status
Simulation time 152697553 ps
CPU time 1.96 seconds
Started Jul 16 07:16:19 PM PDT 24
Finished Jul 16 07:17:04 PM PDT 24
Peak memory 208636 kb
Host smart-cdf2e052-8fc9-43c9-a38c-7a76f807199b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315611435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.315611435
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3057118702
Short name T596
Test name
Test status
Simulation time 124540488 ps
CPU time 1.45 seconds
Started Jul 16 07:16:15 PM PDT 24
Finished Jul 16 07:17:01 PM PDT 24
Peak memory 213308 kb
Host smart-8c281a19-0edd-4c3d-ac1d-0c939bbe7960
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057118702 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3057118702
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2684484531
Short name T610
Test name
Test status
Simulation time 69855370 ps
CPU time 0.79 seconds
Started Jul 16 07:16:07 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200256 kb
Host smart-74a0c27d-9a9f-47f4-ae0e-ca73e00e5f37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684484531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2684484531
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2921513965
Short name T583
Test name
Test status
Simulation time 248208251 ps
CPU time 1.76 seconds
Started Jul 16 07:16:05 PM PDT 24
Finished Jul 16 07:16:57 PM PDT 24
Peak memory 200536 kb
Host smart-dc7951e1-2691-47f2-b006-5d6d8175fe2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921513965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2921513965
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4172834223
Short name T595
Test name
Test status
Simulation time 108488555 ps
CPU time 1.51 seconds
Started Jul 16 07:16:18 PM PDT 24
Finished Jul 16 07:17:03 PM PDT 24
Peak memory 210988 kb
Host smart-ab9a892c-eedd-44ea-aa21-6c0e85d8bb18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172834223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4172834223
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1033041033
Short name T109
Test name
Test status
Simulation time 902737668 ps
CPU time 3.05 seconds
Started Jul 16 07:16:09 PM PDT 24
Finished Jul 16 07:16:58 PM PDT 24
Peak memory 200420 kb
Host smart-fde383f8-5fe9-4f7a-aa09-caf444fa4ea9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033041033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1033041033
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.678432354
Short name T555
Test name
Test status
Simulation time 220704725 ps
CPU time 1.34 seconds
Started Jul 16 07:16:01 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 211312 kb
Host smart-d8d2f9f2-7931-46f0-a912-fcd58e970a41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678432354 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.678432354
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2339326057
Short name T537
Test name
Test status
Simulation time 73404812 ps
CPU time 0.81 seconds
Started Jul 16 07:16:14 PM PDT 24
Finished Jul 16 07:17:01 PM PDT 24
Peak memory 200180 kb
Host smart-ab999a9c-edc4-4f52-b0cc-ca3f48d21043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339326057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2339326057
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.384000046
Short name T589
Test name
Test status
Simulation time 82986124 ps
CPU time 0.99 seconds
Started Jul 16 07:16:15 PM PDT 24
Finished Jul 16 07:17:00 PM PDT 24
Peak memory 200216 kb
Host smart-dcf20d6b-58b7-45bc-af81-4acf4c9ff9df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384000046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.384000046
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4017155154
Short name T597
Test name
Test status
Simulation time 357827578 ps
CPU time 2.34 seconds
Started Jul 16 07:16:09 PM PDT 24
Finished Jul 16 07:16:58 PM PDT 24
Peak memory 208060 kb
Host smart-5e58d146-339f-4dfe-ad5b-ac1422c20ccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017155154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.4017155154
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.118938431
Short name T539
Test name
Test status
Simulation time 783740898 ps
CPU time 3.17 seconds
Started Jul 16 07:16:04 PM PDT 24
Finished Jul 16 07:16:58 PM PDT 24
Peak memory 200560 kb
Host smart-945cf7ba-4aac-44b8-a8f8-20c81a83278f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118938431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.118938431
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4162849267
Short name T577
Test name
Test status
Simulation time 122455349 ps
CPU time 1.38 seconds
Started Jul 16 07:16:15 PM PDT 24
Finished Jul 16 07:17:01 PM PDT 24
Peak memory 208616 kb
Host smart-057b48f0-432d-40cc-8f35-e3436a5df02d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162849267 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4162849267
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3155894876
Short name T574
Test name
Test status
Simulation time 80027724 ps
CPU time 0.82 seconds
Started Jul 16 07:16:15 PM PDT 24
Finished Jul 16 07:17:01 PM PDT 24
Peak memory 200208 kb
Host smart-061a5263-14de-41db-a62d-0c37ad857500
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155894876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3155894876
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1257173762
Short name T603
Test name
Test status
Simulation time 144402806 ps
CPU time 1.07 seconds
Started Jul 16 07:16:20 PM PDT 24
Finished Jul 16 07:17:03 PM PDT 24
Peak memory 200364 kb
Host smart-8674ddd5-9e35-416a-8ac9-b03278c47405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257173762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1257173762
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.860793806
Short name T556
Test name
Test status
Simulation time 285693077 ps
CPU time 2.18 seconds
Started Jul 16 07:16:15 PM PDT 24
Finished Jul 16 07:17:02 PM PDT 24
Peak memory 208568 kb
Host smart-76a3ef10-b608-465b-8b85-456bd2112d7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860793806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.860793806
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1408377530
Short name T110
Test name
Test status
Simulation time 795907179 ps
CPU time 2.86 seconds
Started Jul 16 07:16:15 PM PDT 24
Finished Jul 16 07:17:03 PM PDT 24
Peak memory 200388 kb
Host smart-92557281-2a4d-4d8f-bfc1-b3dd812fa33f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408377530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1408377530
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3481659099
Short name T571
Test name
Test status
Simulation time 348777633 ps
CPU time 2.29 seconds
Started Jul 16 07:15:58 PM PDT 24
Finished Jul 16 07:16:54 PM PDT 24
Peak memory 200356 kb
Host smart-53b08f59-da98-49cb-96f0-469c0addfd7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481659099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
481659099
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3715799247
Short name T543
Test name
Test status
Simulation time 800366632 ps
CPU time 4.19 seconds
Started Jul 16 07:15:54 PM PDT 24
Finished Jul 16 07:16:52 PM PDT 24
Peak memory 200428 kb
Host smart-a1ef8dd7-85d8-4ae3-9a08-dbd329222d0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715799247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
715799247
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4288021467
Short name T609
Test name
Test status
Simulation time 103916352 ps
CPU time 0.84 seconds
Started Jul 16 07:15:58 PM PDT 24
Finished Jul 16 07:16:52 PM PDT 24
Peak memory 200240 kb
Host smart-01099a22-f450-4a85-b87d-d09062e93563
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288021467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4
288021467
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3018454438
Short name T565
Test name
Test status
Simulation time 143114491 ps
CPU time 1.03 seconds
Started Jul 16 07:15:59 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 200348 kb
Host smart-e6cb3094-5110-4bc2-86db-19648376a934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018454438 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3018454438
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2853328844
Short name T86
Test name
Test status
Simulation time 66285963 ps
CPU time 0.82 seconds
Started Jul 16 07:16:00 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 200220 kb
Host smart-2b2014e7-f815-41ac-91a1-ff2b0fe0c6f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853328844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2853328844
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4215696649
Short name T566
Test name
Test status
Simulation time 124616469 ps
CPU time 1.13 seconds
Started Jul 16 07:15:59 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 200288 kb
Host smart-3e434413-107f-404c-ad98-39fe1b474c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215696649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.4215696649
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2653738664
Short name T53
Test name
Test status
Simulation time 191453470 ps
CPU time 2.73 seconds
Started Jul 16 07:15:53 PM PDT 24
Finished Jul 16 07:16:50 PM PDT 24
Peak memory 212380 kb
Host smart-fb7feacb-ec10-4400-ad34-09c72cf27a42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653738664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2653738664
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3096087799
Short name T611
Test name
Test status
Simulation time 461408196 ps
CPU time 2.07 seconds
Started Jul 16 07:15:49 PM PDT 24
Finished Jul 16 07:16:47 PM PDT 24
Peak memory 200492 kb
Host smart-5827b7ad-4db1-4fbb-916d-edfd88292a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096087799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3096087799
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2366908903
Short name T617
Test name
Test status
Simulation time 354406483 ps
CPU time 2.58 seconds
Started Jul 16 07:15:53 PM PDT 24
Finished Jul 16 07:16:50 PM PDT 24
Peak memory 209580 kb
Host smart-100ba672-2426-4c8c-b0b7-14e291d54bfb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366908903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
366908903
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2572578290
Short name T47
Test name
Test status
Simulation time 800955673 ps
CPU time 4.49 seconds
Started Jul 16 07:15:57 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200328 kb
Host smart-0994fd2b-2dab-4f1a-9583-bec630ba3a72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572578290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
572578290
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1281590366
Short name T549
Test name
Test status
Simulation time 147624021 ps
CPU time 1.01 seconds
Started Jul 16 07:15:51 PM PDT 24
Finished Jul 16 07:16:48 PM PDT 24
Peak memory 200112 kb
Host smart-6f876a25-0967-4952-8f19-3b709be52181
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281590366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
281590366
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1322859788
Short name T80
Test name
Test status
Simulation time 186861765 ps
CPU time 1.17 seconds
Started Jul 16 07:15:49 PM PDT 24
Finished Jul 16 07:16:46 PM PDT 24
Peak memory 200392 kb
Host smart-391adb8c-cfc5-46a5-994b-0c9e37e32607
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322859788 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1322859788
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.769525936
Short name T560
Test name
Test status
Simulation time 69563949 ps
CPU time 0.77 seconds
Started Jul 16 07:15:57 PM PDT 24
Finished Jul 16 07:16:51 PM PDT 24
Peak memory 200216 kb
Host smart-6f7c129d-9a22-456e-9f66-c18e3a0dd29e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769525936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.769525936
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3658878022
Short name T616
Test name
Test status
Simulation time 140610240 ps
CPU time 1.07 seconds
Started Jul 16 07:15:54 PM PDT 24
Finished Jul 16 07:16:49 PM PDT 24
Peak memory 200328 kb
Host smart-8776d68b-2e52-4ff6-96aa-aebf9cb81981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658878022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3658878022
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4093209913
Short name T102
Test name
Test status
Simulation time 994506572 ps
CPU time 3.03 seconds
Started Jul 16 07:16:00 PM PDT 24
Finished Jul 16 07:16:55 PM PDT 24
Peak memory 200436 kb
Host smart-0e8fd682-191c-4353-b509-8d1fb743c857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093209913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.4093209913
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.102695093
Short name T548
Test name
Test status
Simulation time 233584260 ps
CPU time 1.57 seconds
Started Jul 16 07:15:50 PM PDT 24
Finished Jul 16 07:16:47 PM PDT 24
Peak memory 200460 kb
Host smart-827d056f-5c1b-4580-9fb3-82b98cbf265f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102695093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.102695093
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1897291168
Short name T559
Test name
Test status
Simulation time 485536193 ps
CPU time 5.64 seconds
Started Jul 16 07:15:54 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 200388 kb
Host smart-577f657e-b2eb-4b42-a324-187ccd6e1bf1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897291168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
897291168
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1027472070
Short name T557
Test name
Test status
Simulation time 140122110 ps
CPU time 0.94 seconds
Started Jul 16 07:15:54 PM PDT 24
Finished Jul 16 07:16:49 PM PDT 24
Peak memory 200260 kb
Host smart-59a546a8-1a85-48bd-97e7-529ba3271a16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027472070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
027472070
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1800475334
Short name T570
Test name
Test status
Simulation time 197906636 ps
CPU time 1.2 seconds
Started Jul 16 07:15:56 PM PDT 24
Finished Jul 16 07:16:51 PM PDT 24
Peak memory 200220 kb
Host smart-6ba7e211-50f5-4b23-ac94-7969f9f41ae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800475334 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1800475334
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1305046449
Short name T591
Test name
Test status
Simulation time 62439032 ps
CPU time 0.79 seconds
Started Jul 16 07:15:53 PM PDT 24
Finished Jul 16 07:16:48 PM PDT 24
Peak memory 200220 kb
Host smart-88fff933-6125-4618-80fa-235801408758
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305046449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1305046449
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4254942624
Short name T581
Test name
Test status
Simulation time 133740500 ps
CPU time 1.12 seconds
Started Jul 16 07:15:54 PM PDT 24
Finished Jul 16 07:16:49 PM PDT 24
Peak memory 200312 kb
Host smart-bfc08c0e-58ac-404c-8fde-931de09fbb07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254942624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4254942624
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1620536966
Short name T550
Test name
Test status
Simulation time 222533862 ps
CPU time 1.81 seconds
Started Jul 16 07:15:59 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 216556 kb
Host smart-4ce00a89-42c9-413f-888a-fb5b9a1c460c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620536966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1620536966
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3191393939
Short name T104
Test name
Test status
Simulation time 425997160 ps
CPU time 1.67 seconds
Started Jul 16 07:15:56 PM PDT 24
Finished Jul 16 07:16:52 PM PDT 24
Peak memory 200400 kb
Host smart-a33456ce-a43a-43c2-ae36-846f19f4d2c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191393939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3191393939
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1901443798
Short name T601
Test name
Test status
Simulation time 130900325 ps
CPU time 1.41 seconds
Started Jul 16 07:15:58 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 208640 kb
Host smart-3ab3919e-3eba-42cd-a8c7-cf25bff99593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901443798 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1901443798
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4211875364
Short name T572
Test name
Test status
Simulation time 74691655 ps
CPU time 0.81 seconds
Started Jul 16 07:15:54 PM PDT 24
Finished Jul 16 07:16:49 PM PDT 24
Peak memory 200292 kb
Host smart-e042b5b0-27b2-438e-a7f8-59e52a14fc9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211875364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.4211875364
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3410039605
Short name T99
Test name
Test status
Simulation time 79736600 ps
CPU time 0.92 seconds
Started Jul 16 07:15:49 PM PDT 24
Finished Jul 16 07:16:46 PM PDT 24
Peak memory 200264 kb
Host smart-140c0df1-1576-4a16-b025-c07a0d219959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410039605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3410039605
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2966693414
Short name T52
Test name
Test status
Simulation time 571207773 ps
CPU time 3.77 seconds
Started Jul 16 07:15:53 PM PDT 24
Finished Jul 16 07:16:52 PM PDT 24
Peak memory 208648 kb
Host smart-5eeb411a-5552-4ccd-8fb4-b6063657ee42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966693414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2966693414
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2637407365
Short name T103
Test name
Test status
Simulation time 426085391 ps
CPU time 1.8 seconds
Started Jul 16 07:15:55 PM PDT 24
Finished Jul 16 07:16:50 PM PDT 24
Peak memory 200500 kb
Host smart-44f7ea6a-7270-4c93-9143-4fa230ca8c0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637407365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2637407365
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2297867449
Short name T538
Test name
Test status
Simulation time 124371182 ps
CPU time 1 seconds
Started Jul 16 07:15:57 PM PDT 24
Finished Jul 16 07:16:52 PM PDT 24
Peak memory 200272 kb
Host smart-7a30e3b4-d4f3-4e04-b25f-bf2b1eca8129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297867449 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2297867449
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1807237029
Short name T593
Test name
Test status
Simulation time 73575475 ps
CPU time 0.78 seconds
Started Jul 16 07:15:51 PM PDT 24
Finished Jul 16 07:16:47 PM PDT 24
Peak memory 200212 kb
Host smart-e067f51a-d3f8-4315-a810-3caf147276c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807237029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1807237029
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2275416964
Short name T588
Test name
Test status
Simulation time 83734890 ps
CPU time 0.93 seconds
Started Jul 16 07:15:57 PM PDT 24
Finished Jul 16 07:16:51 PM PDT 24
Peak memory 200280 kb
Host smart-a96d34f7-2414-4121-80d5-b5a745961575
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275416964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2275416964
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3491200933
Short name T51
Test name
Test status
Simulation time 479330655 ps
CPU time 3.44 seconds
Started Jul 16 07:15:58 PM PDT 24
Finished Jul 16 07:16:55 PM PDT 24
Peak memory 208536 kb
Host smart-4134ead1-3b0d-4410-b7a1-7512009d02e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491200933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3491200933
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.322920413
Short name T607
Test name
Test status
Simulation time 791077197 ps
CPU time 2.95 seconds
Started Jul 16 07:15:50 PM PDT 24
Finished Jul 16 07:16:48 PM PDT 24
Peak memory 200476 kb
Host smart-60dd1ec0-3fde-4c37-84d2-d7bb5b2fe1ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322920413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
322920413
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2525193105
Short name T82
Test name
Test status
Simulation time 217023097 ps
CPU time 1.49 seconds
Started Jul 16 07:16:05 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 208492 kb
Host smart-3ca70fe9-76cd-4175-baa5-ff6b4b54166f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525193105 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2525193105
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1562729441
Short name T576
Test name
Test status
Simulation time 64874364 ps
CPU time 0.84 seconds
Started Jul 16 07:16:02 PM PDT 24
Finished Jul 16 07:16:52 PM PDT 24
Peak memory 200244 kb
Host smart-48e6609d-e3e0-46da-9f38-1b516d255827
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562729441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1562729441
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2552845296
Short name T573
Test name
Test status
Simulation time 140784067 ps
CPU time 1.25 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200312 kb
Host smart-49f87120-994d-4b47-9986-12152505d58a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552845296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2552845296
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3644028066
Short name T547
Test name
Test status
Simulation time 123699495 ps
CPU time 1.62 seconds
Started Jul 16 07:15:57 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 208544 kb
Host smart-5fa63547-6902-4b59-97c8-28253201364c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644028066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3644028066
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3756420081
Short name T108
Test name
Test status
Simulation time 425566748 ps
CPU time 1.76 seconds
Started Jul 16 07:15:57 PM PDT 24
Finished Jul 16 07:16:53 PM PDT 24
Peak memory 200416 kb
Host smart-b0b7fc58-d23e-48fa-a599-4c10d031d737
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756420081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3756420081
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4031158293
Short name T567
Test name
Test status
Simulation time 127994532 ps
CPU time 1 seconds
Started Jul 16 07:16:01 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200408 kb
Host smart-61ac3464-2a8b-437e-9cb7-db6b33c10827
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031158293 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.4031158293
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.636690590
Short name T592
Test name
Test status
Simulation time 63155387 ps
CPU time 0.77 seconds
Started Jul 16 07:16:01 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200288 kb
Host smart-11eb6704-033b-4ae3-aece-af854919d7c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636690590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.636690590
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3825845323
Short name T612
Test name
Test status
Simulation time 119704174 ps
CPU time 1.09 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 200364 kb
Host smart-12faf9ca-12f9-4733-97d5-dea6dcc2ab8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825845323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3825845323
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.437050415
Short name T553
Test name
Test status
Simulation time 192787003 ps
CPU time 2.64 seconds
Started Jul 16 07:16:20 PM PDT 24
Finished Jul 16 07:17:05 PM PDT 24
Peak memory 208640 kb
Host smart-fe22772d-63b2-48d3-ab96-c524da8c4e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437050415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.437050415
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1351674254
Short name T561
Test name
Test status
Simulation time 122283474 ps
CPU time 1.38 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:55 PM PDT 24
Peak memory 208908 kb
Host smart-0a0c7115-5dc6-4c58-8ba4-3e9e49a7143e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351674254 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1351674254
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2103021586
Short name T564
Test name
Test status
Simulation time 72868284 ps
CPU time 0.77 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:55 PM PDT 24
Peak memory 200112 kb
Host smart-79e9b0a3-f9da-4844-96a1-57ef9c4a1779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103021586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2103021586
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3145583547
Short name T613
Test name
Test status
Simulation time 221625697 ps
CPU time 1.61 seconds
Started Jul 16 07:16:06 PM PDT 24
Finished Jul 16 07:16:57 PM PDT 24
Peak memory 200512 kb
Host smart-5b618ed1-bdd7-44cf-adf0-c22146b849e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145583547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3145583547
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.842158315
Short name T552
Test name
Test status
Simulation time 110662226 ps
CPU time 1.68 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:16:56 PM PDT 24
Peak memory 208616 kb
Host smart-ca9f0d5b-8093-487f-965d-815421f60b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842158315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.842158315
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.438420271
Short name T619
Test name
Test status
Simulation time 471582039 ps
CPU time 2.09 seconds
Started Jul 16 07:16:18 PM PDT 24
Finished Jul 16 07:17:03 PM PDT 24
Peak memory 200676 kb
Host smart-55aad58c-a396-4dda-9ea6-2d7218bfc399
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438420271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
438420271
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.733836698
Short name T531
Test name
Test status
Simulation time 82275379 ps
CPU time 0.79 seconds
Started Jul 16 07:21:42 PM PDT 24
Finished Jul 16 07:21:50 PM PDT 24
Peak memory 199944 kb
Host smart-75e15cd7-ac4c-4258-ae9e-6464a5552dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733836698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.733836698
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3674771868
Short name T319
Test name
Test status
Simulation time 1221918001 ps
CPU time 5.66 seconds
Started Jul 16 07:21:27 PM PDT 24
Finished Jul 16 07:21:37 PM PDT 24
Peak memory 217868 kb
Host smart-7b9de710-91ac-43d0-bd56-9e189cce0ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674771868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3674771868
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4291105978
Short name T301
Test name
Test status
Simulation time 245279831 ps
CPU time 0.99 seconds
Started Jul 16 07:21:39 PM PDT 24
Finished Jul 16 07:21:47 PM PDT 24
Peak memory 217540 kb
Host smart-b59688d6-d7af-4963-af42-41a50bb74e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291105978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4291105978
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4123780205
Short name T246
Test name
Test status
Simulation time 195736827 ps
CPU time 0.87 seconds
Started Jul 16 07:21:28 PM PDT 24
Finished Jul 16 07:21:34 PM PDT 24
Peak memory 199932 kb
Host smart-3de5ca92-a85a-4a65-b2a6-871256d5d39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123780205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4123780205
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2927183630
Short name T232
Test name
Test status
Simulation time 1399756779 ps
CPU time 5.55 seconds
Started Jul 16 07:21:28 PM PDT 24
Finished Jul 16 07:21:39 PM PDT 24
Peak memory 200604 kb
Host smart-f7168aac-d4e8-49e7-9d14-bfbe29be61d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927183630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2927183630
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2573589798
Short name T263
Test name
Test status
Simulation time 142244868 ps
CPU time 1.05 seconds
Started Jul 16 07:21:27 PM PDT 24
Finished Jul 16 07:21:33 PM PDT 24
Peak memory 200156 kb
Host smart-c63ae1eb-ca75-4b9e-8340-f0339bdb7d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573589798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2573589798
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2823326536
Short name T166
Test name
Test status
Simulation time 126482037 ps
CPU time 1.14 seconds
Started Jul 16 07:21:27 PM PDT 24
Finished Jul 16 07:21:33 PM PDT 24
Peak memory 200428 kb
Host smart-deaab07b-3839-4e94-afb5-1e7ce89cf279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823326536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2823326536
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3579482079
Short name T479
Test name
Test status
Simulation time 342123407 ps
CPU time 2.09 seconds
Started Jul 16 07:21:29 PM PDT 24
Finished Jul 16 07:21:37 PM PDT 24
Peak memory 200112 kb
Host smart-2d0b8abb-b810-4cd3-89cb-a7d939344d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579482079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3579482079
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2053665843
Short name T283
Test name
Test status
Simulation time 207525358 ps
CPU time 1.28 seconds
Started Jul 16 07:21:28 PM PDT 24
Finished Jul 16 07:21:34 PM PDT 24
Peak memory 200224 kb
Host smart-50b62e08-b30f-4dce-b200-0c8abba5c634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053665843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2053665843
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3573239002
Short name T332
Test name
Test status
Simulation time 69980694 ps
CPU time 0.76 seconds
Started Jul 16 07:21:41 PM PDT 24
Finished Jul 16 07:21:50 PM PDT 24
Peak memory 199944 kb
Host smart-42867fdf-13bd-4eb1-8064-0110b395eb4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573239002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3573239002
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1777946567
Short name T335
Test name
Test status
Simulation time 244234511 ps
CPU time 1.08 seconds
Started Jul 16 07:21:40 PM PDT 24
Finished Jul 16 07:21:48 PM PDT 24
Peak memory 217428 kb
Host smart-f3551683-fa61-4377-918a-688b19b3f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777946567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1777946567
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2945404103
Short name T418
Test name
Test status
Simulation time 89397854 ps
CPU time 0.76 seconds
Started Jul 16 07:21:40 PM PDT 24
Finished Jul 16 07:21:47 PM PDT 24
Peak memory 199892 kb
Host smart-5d10fdfd-79c5-4ccc-ab0c-e4b4236cf35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945404103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2945404103
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2482730044
Short name T230
Test name
Test status
Simulation time 1542249166 ps
CPU time 5.57 seconds
Started Jul 16 07:21:40 PM PDT 24
Finished Jul 16 07:21:53 PM PDT 24
Peak memory 200436 kb
Host smart-d716da5e-a2d7-402e-a454-2cf224415d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482730044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2482730044
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2990951408
Short name T60
Test name
Test status
Simulation time 17179550097 ps
CPU time 23.83 seconds
Started Jul 16 07:21:40 PM PDT 24
Finished Jul 16 07:22:10 PM PDT 24
Peak memory 217624 kb
Host smart-7ed778ac-f818-475c-a542-adf7bd326f10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990951408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2990951408
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1893580817
Short name T357
Test name
Test status
Simulation time 111938549 ps
CPU time 1.02 seconds
Started Jul 16 07:21:42 PM PDT 24
Finished Jul 16 07:21:50 PM PDT 24
Peak memory 200140 kb
Host smart-7faf4f4c-4fa9-4e93-84b2-b5df8f9cbff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893580817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1893580817
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1930793246
Short name T485
Test name
Test status
Simulation time 205697852 ps
CPU time 1.34 seconds
Started Jul 16 07:21:40 PM PDT 24
Finished Jul 16 07:21:49 PM PDT 24
Peak memory 200232 kb
Host smart-3c132a39-cd36-4284-b740-0d5a9fef09a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930793246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1930793246
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3494125642
Short name T274
Test name
Test status
Simulation time 12736932329 ps
CPU time 48.32 seconds
Started Jul 16 07:21:40 PM PDT 24
Finished Jul 16 07:22:36 PM PDT 24
Peak memory 208688 kb
Host smart-a0fa0a35-af31-4d17-beaf-c292897e31a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494125642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3494125642
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.658254212
Short name T343
Test name
Test status
Simulation time 354330449 ps
CPU time 2.15 seconds
Started Jul 16 07:21:41 PM PDT 24
Finished Jul 16 07:21:50 PM PDT 24
Peak memory 200088 kb
Host smart-1526fc77-df12-4901-a1ef-fbe0370f342d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658254212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.658254212
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2909572996
Short name T204
Test name
Test status
Simulation time 105941359 ps
CPU time 1.03 seconds
Started Jul 16 07:21:42 PM PDT 24
Finished Jul 16 07:21:50 PM PDT 24
Peak memory 200136 kb
Host smart-c1e021f9-b4d7-488a-a3f2-34cf492af47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909572996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2909572996
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.405370620
Short name T371
Test name
Test status
Simulation time 59414071 ps
CPU time 0.73 seconds
Started Jul 16 07:22:38 PM PDT 24
Finished Jul 16 07:23:22 PM PDT 24
Peak memory 199940 kb
Host smart-5881d8da-f250-45da-8112-2bf18a88701f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405370620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.405370620
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.4205119352
Short name T253
Test name
Test status
Simulation time 1223530741 ps
CPU time 5.61 seconds
Started Jul 16 07:22:36 PM PDT 24
Finished Jul 16 07:23:24 PM PDT 24
Peak memory 217516 kb
Host smart-92cea6a6-962e-4a29-8cd9-9c3f15bf21cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205119352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.4205119352
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.4223430976
Short name T292
Test name
Test status
Simulation time 244733903 ps
CPU time 1.03 seconds
Started Jul 16 07:22:35 PM PDT 24
Finished Jul 16 07:23:19 PM PDT 24
Peak memory 217540 kb
Host smart-4c17a8ee-373f-4d4d-ad55-bd1f98ff901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223430976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.4223430976
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.741840100
Short name T240
Test name
Test status
Simulation time 157737815 ps
CPU time 0.88 seconds
Started Jul 16 07:22:36 PM PDT 24
Finished Jul 16 07:23:19 PM PDT 24
Peak memory 199976 kb
Host smart-6d33f4bd-a624-474f-92e3-2ac11505af76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741840100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.741840100
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1222897561
Short name T286
Test name
Test status
Simulation time 917996246 ps
CPU time 4.82 seconds
Started Jul 16 07:22:36 PM PDT 24
Finished Jul 16 07:23:23 PM PDT 24
Peak memory 200412 kb
Host smart-45629d2d-19a8-4f1d-bc42-ddb54e0e3b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222897561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1222897561
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1377308187
Short name T278
Test name
Test status
Simulation time 195956325 ps
CPU time 1.36 seconds
Started Jul 16 07:22:38 PM PDT 24
Finished Jul 16 07:23:23 PM PDT 24
Peak memory 200380 kb
Host smart-49b4992a-0164-414d-b680-fd28b44d7f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377308187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1377308187
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3163319873
Short name T442
Test name
Test status
Simulation time 7698927681 ps
CPU time 28.63 seconds
Started Jul 16 07:22:36 PM PDT 24
Finished Jul 16 07:23:47 PM PDT 24
Peak memory 200392 kb
Host smart-83bcb05a-2671-48f7-bb4b-6841166ad869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163319873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3163319873
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1939010809
Short name T157
Test name
Test status
Simulation time 425319392 ps
CPU time 2.46 seconds
Started Jul 16 07:22:34 PM PDT 24
Finished Jul 16 07:23:18 PM PDT 24
Peak memory 208336 kb
Host smart-66214831-b80e-4205-a727-4e0fef04ca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939010809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1939010809
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2324257312
Short name T145
Test name
Test status
Simulation time 118786607 ps
CPU time 0.91 seconds
Started Jul 16 07:22:35 PM PDT 24
Finished Jul 16 07:23:19 PM PDT 24
Peak memory 200144 kb
Host smart-44de6290-60ec-4243-bbf8-cd98ccf6d55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324257312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2324257312
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3908088046
Short name T180
Test name
Test status
Simulation time 62401761 ps
CPU time 0.72 seconds
Started Jul 16 07:22:44 PM PDT 24
Finished Jul 16 07:23:28 PM PDT 24
Peak memory 199932 kb
Host smart-5b7ce5a8-9edd-45a7-a302-7147a06ec9c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908088046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3908088046
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2007679507
Short name T492
Test name
Test status
Simulation time 244444981 ps
CPU time 1.06 seconds
Started Jul 16 07:22:35 PM PDT 24
Finished Jul 16 07:23:19 PM PDT 24
Peak memory 217460 kb
Host smart-466b6642-6212-4c1d-a111-93f8cfba6f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007679507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2007679507
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.158541077
Short name T171
Test name
Test status
Simulation time 93277215 ps
CPU time 0.76 seconds
Started Jul 16 07:22:34 PM PDT 24
Finished Jul 16 07:23:17 PM PDT 24
Peak memory 199988 kb
Host smart-a68abb1a-fadc-473f-b08a-d4e7695d0f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158541077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.158541077
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1630464600
Short name T429
Test name
Test status
Simulation time 1721292823 ps
CPU time 5.88 seconds
Started Jul 16 07:22:34 PM PDT 24
Finished Jul 16 07:23:22 PM PDT 24
Peak memory 200604 kb
Host smart-9ff7c4cb-bf95-446f-a4c2-4823eb35a10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630464600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1630464600
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1627009211
Short name T402
Test name
Test status
Simulation time 95619573 ps
CPU time 0.98 seconds
Started Jul 16 07:22:39 PM PDT 24
Finished Jul 16 07:23:22 PM PDT 24
Peak memory 200144 kb
Host smart-01bb6aed-490c-47a1-9d51-b399cd80313b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627009211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1627009211
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3016320149
Short name T508
Test name
Test status
Simulation time 113702780 ps
CPU time 1.16 seconds
Started Jul 16 07:22:33 PM PDT 24
Finished Jul 16 07:23:17 PM PDT 24
Peak memory 200332 kb
Host smart-b8cffb9d-669f-44eb-89bb-391cd5c5f57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016320149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3016320149
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3911398053
Short name T383
Test name
Test status
Simulation time 3331399400 ps
CPU time 12.41 seconds
Started Jul 16 07:22:46 PM PDT 24
Finished Jul 16 07:23:41 PM PDT 24
Peak memory 200540 kb
Host smart-7fb968c2-7f8f-49a4-b953-ba2c7bfa2a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911398053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3911398053
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.421022424
Short name T220
Test name
Test status
Simulation time 308247178 ps
CPU time 2 seconds
Started Jul 16 07:22:35 PM PDT 24
Finished Jul 16 07:23:20 PM PDT 24
Peak memory 200112 kb
Host smart-2092e814-c803-43eb-bf4d-e419d8b37ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421022424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.421022424
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2030218732
Short name T516
Test name
Test status
Simulation time 118456079 ps
CPU time 0.97 seconds
Started Jul 16 07:22:34 PM PDT 24
Finished Jul 16 07:23:17 PM PDT 24
Peak memory 200112 kb
Host smart-0eb6195a-ae42-4658-bb60-beddd3453d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030218732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2030218732
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.564031129
Short name T441
Test name
Test status
Simulation time 67075401 ps
CPU time 0.83 seconds
Started Jul 16 07:22:45 PM PDT 24
Finished Jul 16 07:23:29 PM PDT 24
Peak memory 199976 kb
Host smart-4a77663e-c805-457d-9ca8-08d4267cb9d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564031129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.564031129
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2796791512
Short name T350
Test name
Test status
Simulation time 1227287373 ps
CPU time 5.45 seconds
Started Jul 16 07:22:44 PM PDT 24
Finished Jul 16 07:23:33 PM PDT 24
Peak memory 217556 kb
Host smart-77e81c68-cde3-4e7a-aede-5e9e37986fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796791512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2796791512
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.240206041
Short name T406
Test name
Test status
Simulation time 243816936 ps
CPU time 1.1 seconds
Started Jul 16 07:22:44 PM PDT 24
Finished Jul 16 07:23:26 PM PDT 24
Peak memory 217524 kb
Host smart-a76583d6-a4bf-4794-9520-b5488c66d2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240206041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.240206041
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2242387434
Short name T385
Test name
Test status
Simulation time 93114708 ps
CPU time 0.72 seconds
Started Jul 16 07:22:46 PM PDT 24
Finished Jul 16 07:23:30 PM PDT 24
Peak memory 199972 kb
Host smart-2b5d81d9-054f-48d5-9873-d67ae0ec1c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242387434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2242387434
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1414718226
Short name T271
Test name
Test status
Simulation time 1466968658 ps
CPU time 5.18 seconds
Started Jul 16 07:22:48 PM PDT 24
Finished Jul 16 07:23:35 PM PDT 24
Peak memory 200372 kb
Host smart-9b93bf50-ab57-4bea-a9e3-9db806f8b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414718226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1414718226
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1776939926
Short name T349
Test name
Test status
Simulation time 103775060 ps
CPU time 0.96 seconds
Started Jul 16 07:22:43 PM PDT 24
Finished Jul 16 07:23:28 PM PDT 24
Peak memory 200152 kb
Host smart-5a751764-0561-4709-8f69-393ce3a95e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776939926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1776939926
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3557709680
Short name T462
Test name
Test status
Simulation time 198406496 ps
CPU time 1.41 seconds
Started Jul 16 07:22:44 PM PDT 24
Finished Jul 16 07:23:29 PM PDT 24
Peak memory 200280 kb
Host smart-03df896f-5b19-4959-8c4e-ba48e463b796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557709680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3557709680
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1972601146
Short name T88
Test name
Test status
Simulation time 15753899313 ps
CPU time 57.14 seconds
Started Jul 16 07:22:44 PM PDT 24
Finished Jul 16 07:24:25 PM PDT 24
Peak memory 208732 kb
Host smart-37690124-0503-48a2-b23d-2dda84d947f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972601146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1972601146
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3757416135
Short name T44
Test name
Test status
Simulation time 463993312 ps
CPU time 2.5 seconds
Started Jul 16 07:22:44 PM PDT 24
Finished Jul 16 07:23:30 PM PDT 24
Peak memory 208344 kb
Host smart-f4e6a8a5-af9f-4f35-bc03-1d663af47c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757416135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3757416135
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3209656559
Short name T155
Test name
Test status
Simulation time 80567172 ps
CPU time 0.85 seconds
Started Jul 16 07:22:45 PM PDT 24
Finished Jul 16 07:23:30 PM PDT 24
Peak memory 200076 kb
Host smart-dc892dff-c07d-495c-b257-eac3a01c520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209656559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3209656559
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3221139344
Short name T214
Test name
Test status
Simulation time 62244265 ps
CPU time 0.71 seconds
Started Jul 16 07:23:04 PM PDT 24
Finished Jul 16 07:23:39 PM PDT 24
Peak memory 199968 kb
Host smart-b79c15ef-763d-4bac-9dc4-8cd738c12944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221139344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3221139344
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1581433531
Short name T370
Test name
Test status
Simulation time 244158718 ps
CPU time 1.05 seconds
Started Jul 16 07:23:00 PM PDT 24
Finished Jul 16 07:23:38 PM PDT 24
Peak memory 217536 kb
Host smart-2a82c81f-b156-436e-ac5d-c7c7aa119231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581433531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1581433531
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3298647660
Short name T425
Test name
Test status
Simulation time 127897114 ps
CPU time 0.78 seconds
Started Jul 16 07:22:46 PM PDT 24
Finished Jul 16 07:23:30 PM PDT 24
Peak memory 199980 kb
Host smart-3ad72e50-b67f-42e0-ab4c-2779dc261843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298647660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3298647660
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3250116238
Short name T257
Test name
Test status
Simulation time 1069662010 ps
CPU time 5.23 seconds
Started Jul 16 07:22:45 PM PDT 24
Finished Jul 16 07:23:34 PM PDT 24
Peak memory 200388 kb
Host smart-7e21b42d-4beb-48c1-a748-338280d28c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250116238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3250116238
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4103787444
Short name T447
Test name
Test status
Simulation time 185041842 ps
CPU time 1.16 seconds
Started Jul 16 07:22:43 PM PDT 24
Finished Jul 16 07:23:28 PM PDT 24
Peak memory 200072 kb
Host smart-b786fa1e-9cf3-4622-8b28-d04f0c7c9102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103787444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4103787444
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1751449860
Short name T239
Test name
Test status
Simulation time 123533835 ps
CPU time 1.12 seconds
Started Jul 16 07:22:45 PM PDT 24
Finished Jul 16 07:23:30 PM PDT 24
Peak memory 200328 kb
Host smart-5cd7d322-9d57-4798-958a-e2a7ab64a719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751449860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1751449860
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.974422475
Short name T172
Test name
Test status
Simulation time 9374692166 ps
CPU time 30.55 seconds
Started Jul 16 07:23:02 PM PDT 24
Finished Jul 16 07:24:07 PM PDT 24
Peak memory 200472 kb
Host smart-b6686d71-300a-4519-bd9b-0c2bb1b47543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974422475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.974422475
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1726394121
Short name T217
Test name
Test status
Simulation time 131948295 ps
CPU time 1.6 seconds
Started Jul 16 07:22:44 PM PDT 24
Finished Jul 16 07:23:30 PM PDT 24
Peak memory 208412 kb
Host smart-fa43fe12-a34d-4550-8634-856cf87d2c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726394121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1726394121
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1753612279
Short name T276
Test name
Test status
Simulation time 197073379 ps
CPU time 1.2 seconds
Started Jul 16 07:22:44 PM PDT 24
Finished Jul 16 07:23:29 PM PDT 24
Peak memory 200088 kb
Host smart-c64154a1-6d68-4411-a957-ff52f93b04c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753612279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1753612279
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3212790251
Short name T136
Test name
Test status
Simulation time 76022508 ps
CPU time 0.76 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:35 PM PDT 24
Peak memory 199924 kb
Host smart-266a1462-1f03-4a06-a40a-53caef7551ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212790251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3212790251
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2393353886
Short name T494
Test name
Test status
Simulation time 1222076564 ps
CPU time 6.09 seconds
Started Jul 16 07:22:58 PM PDT 24
Finished Jul 16 07:23:43 PM PDT 24
Peak memory 221684 kb
Host smart-0e489bc1-50bd-492b-99d4-10377e14ea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393353886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2393353886
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3408420626
Short name T242
Test name
Test status
Simulation time 244238209 ps
CPU time 1.02 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 217504 kb
Host smart-6ff5fe5a-ff94-4e04-936e-d0b209edc654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408420626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3408420626
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2283215352
Short name T471
Test name
Test status
Simulation time 216489646 ps
CPU time 0.9 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 199964 kb
Host smart-47131a1c-eba8-403b-a1a9-14b93c1ef507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283215352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2283215352
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.251881593
Short name T176
Test name
Test status
Simulation time 2095799155 ps
CPU time 7.24 seconds
Started Jul 16 07:22:55 PM PDT 24
Finished Jul 16 07:23:43 PM PDT 24
Peak memory 200392 kb
Host smart-b8f16729-c371-45c9-812c-90608efae613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251881593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.251881593
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.634331300
Short name T287
Test name
Test status
Simulation time 101284040 ps
CPU time 1.04 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 200100 kb
Host smart-af18563a-d7e5-425b-a222-049c4ad4c942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634331300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.634331300
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4114642199
Short name T119
Test name
Test status
Simulation time 191861017 ps
CPU time 1.38 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 200376 kb
Host smart-8c13cbe2-b391-46c1-839b-8c029e5c5b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114642199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4114642199
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1786995638
Short name T450
Test name
Test status
Simulation time 3517144778 ps
CPU time 16.33 seconds
Started Jul 16 07:23:02 PM PDT 24
Finished Jul 16 07:23:54 PM PDT 24
Peak memory 200500 kb
Host smart-7bd11808-8492-4dd1-a2fa-a4ec532e4158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786995638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1786995638
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3914683776
Short name T209
Test name
Test status
Simulation time 123491493 ps
CPU time 1.41 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 200148 kb
Host smart-8c0b490c-c957-4cf0-9d6c-5f926edf1712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914683776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3914683776
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3357428228
Short name T269
Test name
Test status
Simulation time 144906853 ps
CPU time 1.18 seconds
Started Jul 16 07:22:56 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 200176 kb
Host smart-44332cfe-b878-404d-af12-b038f4e013f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357428228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3357428228
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2048309858
Short name T36
Test name
Test status
Simulation time 1229783881 ps
CPU time 5.22 seconds
Started Jul 16 07:22:56 PM PDT 24
Finished Jul 16 07:23:40 PM PDT 24
Peak memory 217972 kb
Host smart-ca8dc496-c41d-428c-9a04-df3403a3192b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048309858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2048309858
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1100709137
Short name T474
Test name
Test status
Simulation time 245455851 ps
CPU time 1.01 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 218388 kb
Host smart-4ebed82b-f764-4777-a910-4ff9705398dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100709137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1100709137
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.931629952
Short name T458
Test name
Test status
Simulation time 219036129 ps
CPU time 0.88 seconds
Started Jul 16 07:22:59 PM PDT 24
Finished Jul 16 07:23:38 PM PDT 24
Peak memory 199980 kb
Host smart-acbffbc0-c0ed-42be-9fd2-b4c4b48bbe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931629952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.931629952
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3371141849
Short name T529
Test name
Test status
Simulation time 905963929 ps
CPU time 4.34 seconds
Started Jul 16 07:22:58 PM PDT 24
Finished Jul 16 07:23:40 PM PDT 24
Peak memory 200444 kb
Host smart-b738be2a-195f-4da0-82e3-50cd2eb544e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371141849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3371141849
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3817167326
Short name T236
Test name
Test status
Simulation time 151573354 ps
CPU time 1.11 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 200140 kb
Host smart-0f24821c-665e-4f04-b2ac-5c35de15fe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817167326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3817167326
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3439830928
Short name T201
Test name
Test status
Simulation time 191029959 ps
CPU time 1.29 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 200376 kb
Host smart-1c7c1f13-5e2e-48b1-826d-8c6ca52302e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439830928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3439830928
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3954773233
Short name T306
Test name
Test status
Simulation time 3613227993 ps
CPU time 16.85 seconds
Started Jul 16 07:22:58 PM PDT 24
Finished Jul 16 07:23:52 PM PDT 24
Peak memory 208700 kb
Host smart-47142fa4-a013-48fc-a26a-19cb02ec4c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954773233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3954773233
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.970803761
Short name T255
Test name
Test status
Simulation time 123115001 ps
CPU time 1.51 seconds
Started Jul 16 07:22:56 PM PDT 24
Finished Jul 16 07:23:38 PM PDT 24
Peak memory 208388 kb
Host smart-ba65f251-2124-4c68-a6f9-119ab9bf1a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970803761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.970803761
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1000992350
Short name T394
Test name
Test status
Simulation time 73110602 ps
CPU time 0.78 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 200088 kb
Host smart-0eb1d2a0-10cb-4cc6-828c-8b21c2dffeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000992350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1000992350
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.727083638
Short name T308
Test name
Test status
Simulation time 53661648 ps
CPU time 0.73 seconds
Started Jul 16 07:23:07 PM PDT 24
Finished Jul 16 07:23:41 PM PDT 24
Peak memory 199940 kb
Host smart-28ea08c0-cb0b-409a-a703-87233685576a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727083638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.727083638
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.4143252185
Short name T526
Test name
Test status
Simulation time 1232797124 ps
CPU time 5.91 seconds
Started Jul 16 07:22:56 PM PDT 24
Finished Jul 16 07:23:40 PM PDT 24
Peak memory 217812 kb
Host smart-822cee85-6921-4784-8181-f10acfde8090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143252185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4143252185
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2504745483
Short name T71
Test name
Test status
Simulation time 243911083 ps
CPU time 1.16 seconds
Started Jul 16 07:23:11 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 217540 kb
Host smart-fe2204f2-9ef3-4cb4-a45c-26fcec1f1b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504745483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2504745483
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2363634583
Short name T290
Test name
Test status
Simulation time 1549836292 ps
CPU time 6.14 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 200420 kb
Host smart-ee91aba4-a313-4c4b-aa16-8d02cd6b4d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363634583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2363634583
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.942509549
Short name T401
Test name
Test status
Simulation time 97531113 ps
CPU time 0.99 seconds
Started Jul 16 07:22:59 PM PDT 24
Finished Jul 16 07:23:38 PM PDT 24
Peak memory 200176 kb
Host smart-445cacba-dd99-4392-82c4-194bfc5fca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942509549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.942509549
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1379100696
Short name T161
Test name
Test status
Simulation time 129952878 ps
CPU time 1.18 seconds
Started Jul 16 07:22:57 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 200348 kb
Host smart-1f5e5f74-cfbf-4154-91b1-b00c00881072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379100696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1379100696
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2637259396
Short name T464
Test name
Test status
Simulation time 4587439117 ps
CPU time 17.49 seconds
Started Jul 16 07:23:07 PM PDT 24
Finished Jul 16 07:23:58 PM PDT 24
Peak memory 200508 kb
Host smart-3121fdb5-85da-4374-8def-155ed0ca8308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637259396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2637259396
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3567942034
Short name T303
Test name
Test status
Simulation time 138497199 ps
CPU time 1.6 seconds
Started Jul 16 07:22:58 PM PDT 24
Finished Jul 16 07:23:38 PM PDT 24
Peak memory 200132 kb
Host smart-9cebbd83-0c50-4355-889e-ecda91ca2f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567942034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3567942034
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1708513205
Short name T326
Test name
Test status
Simulation time 69855922 ps
CPU time 0.74 seconds
Started Jul 16 07:22:59 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 200164 kb
Host smart-ee68090a-9135-434e-bced-10e364ad6ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708513205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1708513205
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1723666252
Short name T124
Test name
Test status
Simulation time 78200541 ps
CPU time 0.85 seconds
Started Jul 16 07:23:08 PM PDT 24
Finished Jul 16 07:23:41 PM PDT 24
Peak memory 199952 kb
Host smart-c7ab0bbe-52a3-4f5f-9568-a8fc70957cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723666252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1723666252
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1933930688
Short name T512
Test name
Test status
Simulation time 2364845177 ps
CPU time 8.97 seconds
Started Jul 16 07:23:07 PM PDT 24
Finished Jul 16 07:23:50 PM PDT 24
Peak memory 217932 kb
Host smart-35d86c6e-24e8-4fce-bd81-fef89dff6720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933930688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1933930688
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1895288247
Short name T339
Test name
Test status
Simulation time 243909835 ps
CPU time 1.04 seconds
Started Jul 16 07:23:07 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 217508 kb
Host smart-5e6b7966-dd5b-4465-b518-f2e2d0d52627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895288247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1895288247
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1388084058
Short name T389
Test name
Test status
Simulation time 138692138 ps
CPU time 0.87 seconds
Started Jul 16 07:23:11 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 199968 kb
Host smart-56a80348-7c7c-4f62-b141-e28b9c9addb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388084058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1388084058
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.167558491
Short name T90
Test name
Test status
Simulation time 1867301743 ps
CPU time 6.55 seconds
Started Jul 16 07:23:11 PM PDT 24
Finished Jul 16 07:23:48 PM PDT 24
Peak memory 200340 kb
Host smart-cb6b700b-4ec0-4a1a-a661-26a4dc9b60b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167558491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.167558491
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.754322316
Short name T254
Test name
Test status
Simulation time 112946321 ps
CPU time 0.99 seconds
Started Jul 16 07:23:11 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 200084 kb
Host smart-f7be7f26-1d69-4041-bcef-f194b35abc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754322316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.754322316
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1213294657
Short name T13
Test name
Test status
Simulation time 195568631 ps
CPU time 1.31 seconds
Started Jul 16 07:23:07 PM PDT 24
Finished Jul 16 07:23:41 PM PDT 24
Peak memory 200384 kb
Host smart-80ba8d50-ccae-4baa-9749-fbfd5ef0de0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213294657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1213294657
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2305833683
Short name T186
Test name
Test status
Simulation time 128525287 ps
CPU time 1.01 seconds
Started Jul 16 07:23:11 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 200144 kb
Host smart-17e74bd2-295b-4ee3-a59f-5d41f5031d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305833683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2305833683
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1055801892
Short name T210
Test name
Test status
Simulation time 484152702 ps
CPU time 2.99 seconds
Started Jul 16 07:23:06 PM PDT 24
Finished Jul 16 07:23:43 PM PDT 24
Peak memory 200064 kb
Host smart-c448e8df-ed1c-49fb-9115-a136815197f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055801892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1055801892
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1193330628
Short name T499
Test name
Test status
Simulation time 105202114 ps
CPU time 0.95 seconds
Started Jul 16 07:23:09 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 200164 kb
Host smart-1df34105-acc4-4a4c-917e-fbfbcd26e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193330628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1193330628
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.308761247
Short name T362
Test name
Test status
Simulation time 70527158 ps
CPU time 0.75 seconds
Started Jul 16 07:23:07 PM PDT 24
Finished Jul 16 07:23:41 PM PDT 24
Peak memory 199976 kb
Host smart-9c549e1a-8a2d-4768-97a7-939e19a41897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308761247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.308761247
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.291445594
Short name T152
Test name
Test status
Simulation time 244282560 ps
CPU time 1.08 seconds
Started Jul 16 07:23:07 PM PDT 24
Finished Jul 16 07:23:41 PM PDT 24
Peak memory 217480 kb
Host smart-992dd42a-b6ed-422a-9fb0-f7c0d41ab020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291445594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.291445594
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.584281995
Short name T19
Test name
Test status
Simulation time 200398844 ps
CPU time 0.9 seconds
Started Jul 16 07:23:11 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 199956 kb
Host smart-1fe6bc74-2942-4823-b9cb-8f718bae8fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584281995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.584281995
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.4008538039
Short name T87
Test name
Test status
Simulation time 891951829 ps
CPU time 4.14 seconds
Started Jul 16 07:23:08 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 200448 kb
Host smart-85ab9682-51b9-4e41-8dc7-9e47ea45bdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008538039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.4008538039
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1200626465
Short name T452
Test name
Test status
Simulation time 111275035 ps
CPU time 1.03 seconds
Started Jul 16 07:23:08 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 200128 kb
Host smart-1146a08b-976d-4c1e-a1f8-138a19d07a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200626465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1200626465
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.535356667
Short name T379
Test name
Test status
Simulation time 125455578 ps
CPU time 1.16 seconds
Started Jul 16 07:23:08 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 200356 kb
Host smart-2db1152a-37fd-4096-a634-54efee53dec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535356667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.535356667
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1127869855
Short name T93
Test name
Test status
Simulation time 11448493628 ps
CPU time 36.36 seconds
Started Jul 16 07:23:11 PM PDT 24
Finished Jul 16 07:24:18 PM PDT 24
Peak memory 208596 kb
Host smart-cb43e84c-5726-40a8-86c0-3c5ba8ca8276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127869855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1127869855
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1820590227
Short name T312
Test name
Test status
Simulation time 124958455 ps
CPU time 1.49 seconds
Started Jul 16 07:23:08 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 200136 kb
Host smart-20ecc4f7-2256-498a-982b-b9b5ae126a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820590227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1820590227
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2445988064
Short name T384
Test name
Test status
Simulation time 76271574 ps
CPU time 0.78 seconds
Started Jul 16 07:23:07 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 200164 kb
Host smart-dbe9765e-5aeb-4c25-b352-d49f0c73540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445988064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2445988064
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2438770693
Short name T57
Test name
Test status
Simulation time 62286640 ps
CPU time 0.73 seconds
Started Jul 16 07:23:22 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 199756 kb
Host smart-e5245864-4b4b-4c9c-82e9-a9a409ff5798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438770693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2438770693
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2448432858
Short name T453
Test name
Test status
Simulation time 1232624922 ps
CPU time 5.49 seconds
Started Jul 16 07:23:19 PM PDT 24
Finished Jul 16 07:23:49 PM PDT 24
Peak memory 217712 kb
Host smart-6ccc52e4-e85d-4560-8cc3-c1aeacfb341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448432858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2448432858
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2428036156
Short name T408
Test name
Test status
Simulation time 243906390 ps
CPU time 1.15 seconds
Started Jul 16 07:23:21 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 217456 kb
Host smart-3803d9c1-5282-4847-930e-0305f23f0f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428036156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2428036156
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1157194757
Short name T142
Test name
Test status
Simulation time 163778530 ps
CPU time 0.9 seconds
Started Jul 16 07:23:11 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 199952 kb
Host smart-7ab306a7-b541-4e81-86c1-39f579edcc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157194757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1157194757
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2709427500
Short name T455
Test name
Test status
Simulation time 1664127338 ps
CPU time 6.27 seconds
Started Jul 16 07:23:06 PM PDT 24
Finished Jul 16 07:23:46 PM PDT 24
Peak memory 200436 kb
Host smart-9edd8e3e-d17b-443a-8a8a-271d34e4c01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709427500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2709427500
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2367937952
Short name T111
Test name
Test status
Simulation time 167238362 ps
CPU time 1.12 seconds
Started Jul 16 07:23:21 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 200140 kb
Host smart-55d5ead3-bd13-4b51-8388-99d6be409bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367937952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2367937952
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3366476167
Short name T368
Test name
Test status
Simulation time 195071929 ps
CPU time 1.37 seconds
Started Jul 16 07:23:11 PM PDT 24
Finished Jul 16 07:23:43 PM PDT 24
Peak memory 200356 kb
Host smart-54bfc4b5-27f8-484b-b9ab-0715a729913f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366476167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3366476167
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.4020414344
Short name T431
Test name
Test status
Simulation time 3219640680 ps
CPU time 11.3 seconds
Started Jul 16 07:23:20 PM PDT 24
Finished Jul 16 07:23:55 PM PDT 24
Peak memory 208668 kb
Host smart-c57d0b5f-71e9-4ec9-be93-920e859c12fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020414344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4020414344
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1704105586
Short name T423
Test name
Test status
Simulation time 147241419 ps
CPU time 1.91 seconds
Started Jul 16 07:23:18 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 200112 kb
Host smart-dc0bbabd-a186-4295-aaac-b50682f91896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704105586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1704105586
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3458776063
Short name T72
Test name
Test status
Simulation time 252330982 ps
CPU time 1.35 seconds
Started Jul 16 07:23:21 PM PDT 24
Finished Jul 16 07:23:46 PM PDT 24
Peak memory 200072 kb
Host smart-66caa708-fba4-485b-bb45-3f35ac74041f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458776063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3458776063
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1185623539
Short name T525
Test name
Test status
Simulation time 68815687 ps
CPU time 0.74 seconds
Started Jul 16 07:21:58 PM PDT 24
Finished Jul 16 07:22:06 PM PDT 24
Peak memory 199948 kb
Host smart-5f438b14-36d3-4cba-b98c-31962547c218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185623539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1185623539
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.602644610
Short name T35
Test name
Test status
Simulation time 1225962456 ps
CPU time 5.65 seconds
Started Jul 16 07:22:00 PM PDT 24
Finished Jul 16 07:22:13 PM PDT 24
Peak memory 221688 kb
Host smart-17c2b462-e6f4-427a-936f-52406324838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602644610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.602644610
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1551765105
Short name T133
Test name
Test status
Simulation time 243409497 ps
CPU time 1.05 seconds
Started Jul 16 07:21:59 PM PDT 24
Finished Jul 16 07:22:07 PM PDT 24
Peak memory 217452 kb
Host smart-93dcdd1c-3e07-477b-98e7-9b1f52e28835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551765105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1551765105
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3165679035
Short name T237
Test name
Test status
Simulation time 177947782 ps
CPU time 0.86 seconds
Started Jul 16 07:21:40 PM PDT 24
Finished Jul 16 07:21:48 PM PDT 24
Peak memory 199880 kb
Host smart-a6ea277c-5e23-4c85-9ab2-69867f858059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165679035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3165679035
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3777988590
Short name T510
Test name
Test status
Simulation time 1879166593 ps
CPU time 7.04 seconds
Started Jul 16 07:21:42 PM PDT 24
Finished Jul 16 07:21:57 PM PDT 24
Peak memory 200432 kb
Host smart-1ac70538-5305-466d-96d4-f3c4868d9786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777988590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3777988590
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1905764192
Short name T55
Test name
Test status
Simulation time 16519619001 ps
CPU time 28 seconds
Started Jul 16 07:22:00 PM PDT 24
Finished Jul 16 07:22:35 PM PDT 24
Peak memory 218332 kb
Host smart-8d572cdc-a8df-4440-88df-a73d54cddadc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905764192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1905764192
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.139849796
Short name T491
Test name
Test status
Simulation time 160189411 ps
CPU time 1.09 seconds
Started Jul 16 07:21:57 PM PDT 24
Finished Jul 16 07:22:05 PM PDT 24
Peak memory 200124 kb
Host smart-77f6bef4-a006-4ff3-abb6-973273027ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139849796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.139849796
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.4219247369
Short name T107
Test name
Test status
Simulation time 224651355 ps
CPU time 1.36 seconds
Started Jul 16 07:21:40 PM PDT 24
Finished Jul 16 07:21:49 PM PDT 24
Peak memory 200360 kb
Host smart-669cdc76-416a-4d58-b772-ba9ffe2f7e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219247369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4219247369
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.503822600
Short name T77
Test name
Test status
Simulation time 5844116933 ps
CPU time 25.18 seconds
Started Jul 16 07:22:00 PM PDT 24
Finished Jul 16 07:22:33 PM PDT 24
Peak memory 208692 kb
Host smart-c350c54d-997e-444e-86e7-ec5907a4b57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503822600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.503822600
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1836945357
Short name T275
Test name
Test status
Simulation time 324154663 ps
CPU time 2.02 seconds
Started Jul 16 07:21:58 PM PDT 24
Finished Jul 16 07:22:07 PM PDT 24
Peak memory 200188 kb
Host smart-c7a23092-8e24-4347-b657-ee27695fc183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836945357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1836945357
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1526971856
Short name T421
Test name
Test status
Simulation time 157906823 ps
CPU time 1.22 seconds
Started Jul 16 07:21:59 PM PDT 24
Finished Jul 16 07:22:07 PM PDT 24
Peak memory 200352 kb
Host smart-4cc2159b-28ad-409d-b84d-bc4dcfd4b4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526971856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1526971856
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3307607270
Short name T264
Test name
Test status
Simulation time 83665812 ps
CPU time 0.82 seconds
Started Jul 16 07:23:24 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 199968 kb
Host smart-f22cb2ff-abab-4042-8a70-392689404c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307607270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3307607270
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3462132128
Short name T475
Test name
Test status
Simulation time 2190128506 ps
CPU time 7.3 seconds
Started Jul 16 07:23:19 PM PDT 24
Finished Jul 16 07:23:51 PM PDT 24
Peak memory 229996 kb
Host smart-6fd55af7-f83f-4bf7-9f5e-f88566d37282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462132128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3462132128
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2656571544
Short name T168
Test name
Test status
Simulation time 244030693 ps
CPU time 1.1 seconds
Started Jul 16 07:23:23 PM PDT 24
Finished Jul 16 07:23:46 PM PDT 24
Peak memory 217536 kb
Host smart-f2b1a94a-56bf-4b16-988f-a74b9233a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656571544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2656571544
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2084023916
Short name T226
Test name
Test status
Simulation time 121445456 ps
CPU time 0.84 seconds
Started Jul 16 07:23:23 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 199928 kb
Host smart-ff09d585-a990-4fb3-98e0-6652cc25c3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084023916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2084023916
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3302054012
Short name T361
Test name
Test status
Simulation time 1456796598 ps
CPU time 5.25 seconds
Started Jul 16 07:23:20 PM PDT 24
Finished Jul 16 07:23:49 PM PDT 24
Peak memory 200436 kb
Host smart-dd6621be-f677-4249-bd1c-befa5f3fe57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302054012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3302054012
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.98300599
Short name T445
Test name
Test status
Simulation time 148873063 ps
CPU time 1.09 seconds
Started Jul 16 07:23:18 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 200176 kb
Host smart-506e5d92-8b9a-4598-b767-4d2cd1de8166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98300599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.98300599
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2415362745
Short name T410
Test name
Test status
Simulation time 107915911 ps
CPU time 1.14 seconds
Started Jul 16 07:23:19 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 200280 kb
Host smart-ac8381c3-9044-4937-bdb6-d0c13589e671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415362745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2415362745
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.592154692
Short name T340
Test name
Test status
Simulation time 11760841719 ps
CPU time 42.19 seconds
Started Jul 16 07:23:19 PM PDT 24
Finished Jul 16 07:24:26 PM PDT 24
Peak memory 200468 kb
Host smart-821ea266-33b3-4252-922b-69abb0b9fce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592154692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.592154692
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2958772438
Short name T249
Test name
Test status
Simulation time 275655401 ps
CPU time 1.83 seconds
Started Jul 16 07:23:19 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 200048 kb
Host smart-02a7fee0-f07a-41b3-8db6-90aa8d9ad39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958772438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2958772438
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1695337956
Short name T478
Test name
Test status
Simulation time 80874459 ps
CPU time 0.82 seconds
Started Jul 16 07:23:23 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 200160 kb
Host smart-713ad755-bc0f-407a-ad6d-e0dc3d266091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695337956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1695337956
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.4254716551
Short name T504
Test name
Test status
Simulation time 87497912 ps
CPU time 0.82 seconds
Started Jul 16 07:23:30 PM PDT 24
Finished Jul 16 07:23:49 PM PDT 24
Peak memory 199892 kb
Host smart-e24f3359-8337-4690-9a70-88d73b580279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254716551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.4254716551
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.758449266
Short name T337
Test name
Test status
Simulation time 1892507507 ps
CPU time 6.83 seconds
Started Jul 16 07:23:31 PM PDT 24
Finished Jul 16 07:23:55 PM PDT 24
Peak memory 217572 kb
Host smart-4eecd6b5-aadf-4a63-a1b3-d67edf9f69b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758449266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.758449266
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.933440152
Short name T509
Test name
Test status
Simulation time 244332641 ps
CPU time 1.02 seconds
Started Jul 16 07:23:33 PM PDT 24
Finished Jul 16 07:23:51 PM PDT 24
Peak memory 217456 kb
Host smart-fdfd6659-f7bb-4431-b695-958288edbb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933440152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.933440152
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1955372359
Short name T456
Test name
Test status
Simulation time 126730960 ps
CPU time 0.81 seconds
Started Jul 16 07:23:22 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 199852 kb
Host smart-41fd6292-d282-4dc2-b797-cbd8146abace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955372359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1955372359
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1802197377
Short name T198
Test name
Test status
Simulation time 1027823684 ps
CPU time 5.49 seconds
Started Jul 16 07:23:18 PM PDT 24
Finished Jul 16 07:23:48 PM PDT 24
Peak memory 200492 kb
Host smart-6577474a-829f-422e-94e2-1e3a0a8003da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802197377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1802197377
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4010039529
Short name T193
Test name
Test status
Simulation time 106534547 ps
CPU time 1.09 seconds
Started Jul 16 07:23:31 PM PDT 24
Finished Jul 16 07:23:49 PM PDT 24
Peak memory 200112 kb
Host smart-616025bc-268f-4f34-9369-51a44da9bffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010039529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.4010039529
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1064923726
Short name T170
Test name
Test status
Simulation time 263523213 ps
CPU time 1.5 seconds
Started Jul 16 07:23:18 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 200360 kb
Host smart-317d2c87-10d1-47ae-84ba-7f04f3583d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064923726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1064923726
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1995808430
Short name T446
Test name
Test status
Simulation time 5383444963 ps
CPU time 24.14 seconds
Started Jul 16 07:23:31 PM PDT 24
Finished Jul 16 07:24:12 PM PDT 24
Peak memory 209712 kb
Host smart-1c818a42-8ce2-44d3-9d91-b1f57221be1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995808430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1995808430
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3851789739
Short name T45
Test name
Test status
Simulation time 304193611 ps
CPU time 1.97 seconds
Started Jul 16 07:23:30 PM PDT 24
Finished Jul 16 07:23:50 PM PDT 24
Peak memory 208384 kb
Host smart-9f2fe12b-2279-476f-a3b9-ab8e6918d37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851789739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3851789739
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1971688577
Short name T185
Test name
Test status
Simulation time 128832410 ps
CPU time 1.05 seconds
Started Jul 16 07:23:31 PM PDT 24
Finished Jul 16 07:23:49 PM PDT 24
Peak memory 200164 kb
Host smart-bb48d036-978f-483f-8177-f371740cfa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971688577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1971688577
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2235308875
Short name T323
Test name
Test status
Simulation time 75455443 ps
CPU time 0.81 seconds
Started Jul 16 07:23:44 PM PDT 24
Finished Jul 16 07:23:58 PM PDT 24
Peak memory 199968 kb
Host smart-47c2c08a-ac0e-4607-b17f-9e3763c089b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235308875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2235308875
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.4178788606
Short name T27
Test name
Test status
Simulation time 2360125422 ps
CPU time 8.95 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:24:06 PM PDT 24
Peak memory 217916 kb
Host smart-02037070-322a-48f2-9df9-92d77d9c7d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178788606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.4178788606
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1766244964
Short name T434
Test name
Test status
Simulation time 243411632 ps
CPU time 1.09 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:23:57 PM PDT 24
Peak memory 217460 kb
Host smart-e839ff03-d3f0-452f-aa38-b281ef7c959b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766244964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1766244964
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3412153975
Short name T7
Test name
Test status
Simulation time 96826708 ps
CPU time 0.74 seconds
Started Jul 16 07:23:31 PM PDT 24
Finished Jul 16 07:23:49 PM PDT 24
Peak memory 199932 kb
Host smart-c57c87ae-8bfb-45b4-b1e0-4d74a8083c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412153975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3412153975
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3777427247
Short name T37
Test name
Test status
Simulation time 949586675 ps
CPU time 4.63 seconds
Started Jul 16 07:23:31 PM PDT 24
Finished Jul 16 07:23:52 PM PDT 24
Peak memory 200420 kb
Host smart-22296ef0-a488-455a-b6fa-37c36ae85891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777427247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3777427247
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1237191715
Short name T373
Test name
Test status
Simulation time 102443201 ps
CPU time 0.98 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:23:57 PM PDT 24
Peak memory 200108 kb
Host smart-852bfea0-a151-46fb-95ff-4b17f4addf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237191715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1237191715
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3019988387
Short name T338
Test name
Test status
Simulation time 244317734 ps
CPU time 1.39 seconds
Started Jul 16 07:23:29 PM PDT 24
Finished Jul 16 07:23:49 PM PDT 24
Peak memory 200452 kb
Host smart-c3801fe3-3480-4a08-b0ec-c0ed65d984ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019988387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3019988387
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.763820737
Short name T181
Test name
Test status
Simulation time 4866105504 ps
CPU time 21.97 seconds
Started Jul 16 07:23:44 PM PDT 24
Finished Jul 16 07:24:20 PM PDT 24
Peak memory 208668 kb
Host smart-c18950db-77ef-4580-8c31-0f2c36416fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763820737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.763820737
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1372080371
Short name T382
Test name
Test status
Simulation time 121192030 ps
CPU time 1.59 seconds
Started Jul 16 07:23:44 PM PDT 24
Finished Jul 16 07:23:59 PM PDT 24
Peak memory 208284 kb
Host smart-e0d1727c-4b3f-4ac4-b9bf-bcb29e6f2749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372080371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1372080371
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1020379537
Short name T367
Test name
Test status
Simulation time 77116570 ps
CPU time 0.78 seconds
Started Jul 16 07:23:44 PM PDT 24
Finished Jul 16 07:23:58 PM PDT 24
Peak memory 200172 kb
Host smart-2109b76a-d34a-4a0e-a44c-ac5b369a1d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020379537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1020379537
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1990536632
Short name T359
Test name
Test status
Simulation time 70331329 ps
CPU time 0.77 seconds
Started Jul 16 07:23:46 PM PDT 24
Finished Jul 16 07:24:03 PM PDT 24
Peak memory 199908 kb
Host smart-1493c0c8-242d-4619-84ce-5fe08957b3e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990536632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1990536632
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3884378673
Short name T427
Test name
Test status
Simulation time 1892047852 ps
CPU time 6.69 seconds
Started Jul 16 07:23:44 PM PDT 24
Finished Jul 16 07:24:04 PM PDT 24
Peak memory 216848 kb
Host smart-e20a3ee0-2e16-47f7-80c0-2c780a7ae3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884378673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3884378673
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3489057020
Short name T437
Test name
Test status
Simulation time 243819856 ps
CPU time 1.09 seconds
Started Jul 16 07:23:45 PM PDT 24
Finished Jul 16 07:23:59 PM PDT 24
Peak memory 217516 kb
Host smart-52d39a6b-2c84-4e54-ba19-8fd6404ce599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489057020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3489057020
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1710181910
Short name T513
Test name
Test status
Simulation time 156535135 ps
CPU time 0.84 seconds
Started Jul 16 07:23:46 PM PDT 24
Finished Jul 16 07:24:03 PM PDT 24
Peak memory 199964 kb
Host smart-4beb86ea-8729-4a65-831a-51a4c8fd4b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710181910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1710181910
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.580158058
Short name T205
Test name
Test status
Simulation time 934506600 ps
CPU time 4.82 seconds
Started Jul 16 07:23:46 PM PDT 24
Finished Jul 16 07:24:07 PM PDT 24
Peak memory 200404 kb
Host smart-ce04bce7-cea3-4dfe-822b-f908de882d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580158058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.580158058
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2418052230
Short name T123
Test name
Test status
Simulation time 141413503 ps
CPU time 1.05 seconds
Started Jul 16 07:23:44 PM PDT 24
Finished Jul 16 07:23:59 PM PDT 24
Peak memory 200148 kb
Host smart-1d9bad88-031f-4aea-acb2-2a504afca4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418052230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2418052230
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.210225018
Short name T134
Test name
Test status
Simulation time 254869804 ps
CPU time 1.51 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:23:58 PM PDT 24
Peak memory 200376 kb
Host smart-c3acfbf9-1e85-45cb-be9e-8860266d1132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210225018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.210225018
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3563309218
Short name T518
Test name
Test status
Simulation time 5231737168 ps
CPU time 19.55 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:24:16 PM PDT 24
Peak memory 208712 kb
Host smart-27cfee0c-0dba-4e0f-a22d-483dff91d58d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563309218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3563309218
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2003846193
Short name T451
Test name
Test status
Simulation time 307251507 ps
CPU time 2 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:23:59 PM PDT 24
Peak memory 200132 kb
Host smart-028870ed-1515-478d-8540-5042de30e61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003846193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2003846193
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1507774222
Short name T252
Test name
Test status
Simulation time 167274443 ps
CPU time 1.12 seconds
Started Jul 16 07:23:46 PM PDT 24
Finished Jul 16 07:24:03 PM PDT 24
Peak memory 200088 kb
Host smart-427be967-f097-4e5d-a44a-f69b9634b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507774222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1507774222
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1419407851
Short name T127
Test name
Test status
Simulation time 82663101 ps
CPU time 0.79 seconds
Started Jul 16 07:23:45 PM PDT 24
Finished Jul 16 07:24:00 PM PDT 24
Peak memory 199904 kb
Host smart-9521e77b-6ac4-4df8-9d83-eed58e96eb55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419407851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1419407851
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.260582053
Short name T397
Test name
Test status
Simulation time 1228163267 ps
CPU time 6.14 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:24:03 PM PDT 24
Peak memory 217824 kb
Host smart-4d75225a-904c-4951-ad2d-621281272c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260582053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.260582053
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3960648125
Short name T244
Test name
Test status
Simulation time 243619713 ps
CPU time 1.07 seconds
Started Jul 16 07:23:44 PM PDT 24
Finished Jul 16 07:23:59 PM PDT 24
Peak memory 217396 kb
Host smart-699c5683-92b5-4933-8f88-32a6a6ae5f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960648125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3960648125
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2823178670
Short name T207
Test name
Test status
Simulation time 206442695 ps
CPU time 0.95 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:23:58 PM PDT 24
Peak memory 199984 kb
Host smart-6256ac9a-f713-47ef-a4d6-c9b984e831bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823178670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2823178670
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1534884041
Short name T64
Test name
Test status
Simulation time 730790233 ps
CPU time 3.8 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:24:01 PM PDT 24
Peak memory 200444 kb
Host smart-6bb38edf-7745-484e-b84b-6b9a1410e952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534884041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1534884041
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2379278870
Short name T167
Test name
Test status
Simulation time 147324355 ps
CPU time 1.14 seconds
Started Jul 16 07:23:44 PM PDT 24
Finished Jul 16 07:23:59 PM PDT 24
Peak memory 200148 kb
Host smart-cbaaa22b-e08e-4ae6-a46c-2253a4f7f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379278870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2379278870
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2505591250
Short name T213
Test name
Test status
Simulation time 250787335 ps
CPU time 1.45 seconds
Started Jul 16 07:23:45 PM PDT 24
Finished Jul 16 07:24:01 PM PDT 24
Peak memory 200300 kb
Host smart-02c9846e-a4c9-4ded-8201-0794b7c74070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505591250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2505591250
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2862322834
Short name T216
Test name
Test status
Simulation time 6352421535 ps
CPU time 20.52 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:24:17 PM PDT 24
Peak memory 210316 kb
Host smart-64fe5bf6-9143-4bbb-b5a6-5c098843a934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862322834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2862322834
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2260759610
Short name T267
Test name
Test status
Simulation time 145483475 ps
CPU time 1.83 seconds
Started Jul 16 07:23:44 PM PDT 24
Finished Jul 16 07:23:59 PM PDT 24
Peak memory 200184 kb
Host smart-cb4004b7-8404-4502-9c77-17bf3a89dd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260759610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2260759610
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2014021180
Short name T125
Test name
Test status
Simulation time 91164465 ps
CPU time 0.89 seconds
Started Jul 16 07:23:43 PM PDT 24
Finished Jul 16 07:23:58 PM PDT 24
Peak memory 200172 kb
Host smart-01a999c5-be11-4371-99d1-17b39cd3b0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014021180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2014021180
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2643800350
Short name T117
Test name
Test status
Simulation time 79115993 ps
CPU time 0.79 seconds
Started Jul 16 07:23:59 PM PDT 24
Finished Jul 16 07:24:21 PM PDT 24
Peak memory 199972 kb
Host smart-94cd1ac9-5901-4370-bf3e-e96706d9c387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643800350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2643800350
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.558955724
Short name T473
Test name
Test status
Simulation time 1909705899 ps
CPU time 7.41 seconds
Started Jul 16 07:23:55 PM PDT 24
Finished Jul 16 07:24:20 PM PDT 24
Peak memory 221624 kb
Host smart-1504819c-d27d-456d-b1ef-472fae2c4f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558955724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.558955724
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4289972745
Short name T519
Test name
Test status
Simulation time 244537546 ps
CPU time 1.13 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:16 PM PDT 24
Peak memory 217524 kb
Host smart-f06ec782-e3c5-4f9e-a694-0aaeef02951c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289972745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4289972745
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1182348984
Short name T6
Test name
Test status
Simulation time 169608291 ps
CPU time 0.85 seconds
Started Jul 16 07:23:42 PM PDT 24
Finished Jul 16 07:23:57 PM PDT 24
Peak memory 200144 kb
Host smart-df988a7b-e787-4c1a-b881-a32db2064723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182348984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1182348984
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2387678906
Short name T147
Test name
Test status
Simulation time 1097840106 ps
CPU time 4.37 seconds
Started Jul 16 07:23:46 PM PDT 24
Finished Jul 16 07:24:06 PM PDT 24
Peak memory 200400 kb
Host smart-05e78f04-0c01-44d8-9fc0-4f9956439160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387678906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2387678906
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2008775140
Short name T151
Test name
Test status
Simulation time 100856795 ps
CPU time 0.99 seconds
Started Jul 16 07:23:59 PM PDT 24
Finished Jul 16 07:24:18 PM PDT 24
Peak memory 200092 kb
Host smart-26fbe81b-f589-414a-9d4c-f42029cec129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008775140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2008775140
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2629801331
Short name T467
Test name
Test status
Simulation time 109568761 ps
CPU time 1.21 seconds
Started Jul 16 07:23:45 PM PDT 24
Finished Jul 16 07:24:03 PM PDT 24
Peak memory 200304 kb
Host smart-f7a1b507-537d-4fda-82d8-5ce1c47c256d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629801331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2629801331
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3146672166
Short name T449
Test name
Test status
Simulation time 4653741112 ps
CPU time 16.42 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:33 PM PDT 24
Peak memory 208648 kb
Host smart-1e94c80b-8f29-4c8c-a379-761a08daf783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146672166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3146672166
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1919770235
Short name T344
Test name
Test status
Simulation time 344157161 ps
CPU time 2.08 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:17 PM PDT 24
Peak memory 200140 kb
Host smart-9ed0edd0-728d-4cf7-9345-4cb4229cf40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919770235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1919770235
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3238671448
Short name T139
Test name
Test status
Simulation time 114332513 ps
CPU time 1.09 seconds
Started Jul 16 07:23:56 PM PDT 24
Finished Jul 16 07:24:15 PM PDT 24
Peak memory 200128 kb
Host smart-746f3a83-1bb1-49dd-bb54-58d3a1e4af60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238671448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3238671448
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2392025015
Short name T341
Test name
Test status
Simulation time 79565477 ps
CPU time 0.82 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:15 PM PDT 24
Peak memory 199972 kb
Host smart-06a133cf-9510-48bd-bdd4-6f9093801893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392025015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2392025015
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2665860232
Short name T8
Test name
Test status
Simulation time 1227704853 ps
CPU time 5.64 seconds
Started Jul 16 07:24:00 PM PDT 24
Finished Jul 16 07:24:25 PM PDT 24
Peak memory 229876 kb
Host smart-7b5f0f68-c82b-40e5-ad92-1b4976d3fbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665860232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2665860232
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1343244656
Short name T250
Test name
Test status
Simulation time 244953759 ps
CPU time 1.07 seconds
Started Jul 16 07:23:56 PM PDT 24
Finished Jul 16 07:24:16 PM PDT 24
Peak memory 217524 kb
Host smart-4be7689b-b76d-4574-939e-6fa42134f81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343244656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1343244656
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2675768251
Short name T328
Test name
Test status
Simulation time 164360771 ps
CPU time 0.84 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:15 PM PDT 24
Peak memory 199968 kb
Host smart-a2380534-6a72-46d0-974d-2c798718cf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675768251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2675768251
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3199900123
Short name T24
Test name
Test status
Simulation time 892742007 ps
CPU time 4.69 seconds
Started Jul 16 07:23:56 PM PDT 24
Finished Jul 16 07:24:19 PM PDT 24
Peak memory 200436 kb
Host smart-bcbcfe26-7f5e-4a7c-980b-f28157ed1484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199900123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3199900123
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3515744340
Short name T70
Test name
Test status
Simulation time 183416582 ps
CPU time 1.17 seconds
Started Jul 16 07:23:55 PM PDT 24
Finished Jul 16 07:24:14 PM PDT 24
Peak memory 200168 kb
Host smart-f8fae0d7-a512-41e6-8aaf-1304bbdf7d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515744340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3515744340
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.667491657
Short name T520
Test name
Test status
Simulation time 261859326 ps
CPU time 1.54 seconds
Started Jul 16 07:23:59 PM PDT 24
Finished Jul 16 07:24:21 PM PDT 24
Peak memory 200324 kb
Host smart-bcfab464-24dd-4f6e-b257-4448319dfe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667491657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.667491657
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3115829485
Short name T470
Test name
Test status
Simulation time 125029887 ps
CPU time 1.01 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:15 PM PDT 24
Peak memory 200156 kb
Host smart-8e4f005b-625f-4893-8648-c4b9cb974421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115829485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3115829485
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.345210491
Short name T291
Test name
Test status
Simulation time 192994214 ps
CPU time 1.18 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:16 PM PDT 24
Peak memory 200132 kb
Host smart-1f8f3f56-1167-404a-a592-e673bae30657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345210491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.345210491
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1233396831
Short name T360
Test name
Test status
Simulation time 62939232 ps
CPU time 0.8 seconds
Started Jul 16 07:24:00 PM PDT 24
Finished Jul 16 07:24:22 PM PDT 24
Peak memory 199972 kb
Host smart-ef9b22b0-ce64-4d42-a2ed-20ad5b1b2be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233396831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1233396831
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1835120250
Short name T334
Test name
Test status
Simulation time 2150715398 ps
CPU time 7.36 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:22 PM PDT 24
Peak memory 217572 kb
Host smart-d3ee0b57-2f4e-4593-9e3e-59f58c89d2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835120250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1835120250
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.613333480
Short name T309
Test name
Test status
Simulation time 249242177 ps
CPU time 1.05 seconds
Started Jul 16 07:23:59 PM PDT 24
Finished Jul 16 07:24:21 PM PDT 24
Peak memory 217516 kb
Host smart-78f4bfac-35d4-4c98-a50c-826cae99f555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613333480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.613333480
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3802777591
Short name T372
Test name
Test status
Simulation time 196024512 ps
CPU time 0.9 seconds
Started Jul 16 07:23:56 PM PDT 24
Finished Jul 16 07:24:15 PM PDT 24
Peak memory 199980 kb
Host smart-890c4858-84dc-4212-b46a-4a76b7ecd043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802777591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3802777591
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3091142396
Short name T483
Test name
Test status
Simulation time 1591911121 ps
CPU time 6.54 seconds
Started Jul 16 07:23:58 PM PDT 24
Finished Jul 16 07:24:24 PM PDT 24
Peak memory 200428 kb
Host smart-8cb993ef-e166-4c75-b7aa-88a6f279c395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091142396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3091142396
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.234114120
Short name T131
Test name
Test status
Simulation time 144163497 ps
CPU time 1.12 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:16 PM PDT 24
Peak memory 200076 kb
Host smart-0e2af4b7-7c91-43d7-9888-706d9e8bf566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234114120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.234114120
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2368952095
Short name T66
Test name
Test status
Simulation time 245399015 ps
CPU time 1.46 seconds
Started Jul 16 07:23:59 PM PDT 24
Finished Jul 16 07:24:19 PM PDT 24
Peak memory 200264 kb
Host smart-3b9c2187-9f30-4212-ac3d-ed98dde02086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368952095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2368952095
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1753333757
Short name T268
Test name
Test status
Simulation time 995452039 ps
CPU time 4.6 seconds
Started Jul 16 07:23:57 PM PDT 24
Finished Jul 16 07:24:18 PM PDT 24
Peak memory 200424 kb
Host smart-d8729cd2-1f3d-40e5-9462-07ff51186d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753333757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1753333757
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2615480776
Short name T435
Test name
Test status
Simulation time 156245876 ps
CPU time 1.88 seconds
Started Jul 16 07:23:58 PM PDT 24
Finished Jul 16 07:24:20 PM PDT 24
Peak memory 200140 kb
Host smart-dc51921d-7a31-4896-94ec-16dae5d44f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615480776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2615480776
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2335578710
Short name T430
Test name
Test status
Simulation time 173580217 ps
CPU time 1.13 seconds
Started Jul 16 07:23:58 PM PDT 24
Finished Jul 16 07:24:18 PM PDT 24
Peak memory 200144 kb
Host smart-c5738ca1-ae84-46bc-91d0-b30f1927a56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335578710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2335578710
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.662538793
Short name T238
Test name
Test status
Simulation time 66372698 ps
CPU time 0.75 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:43 PM PDT 24
Peak memory 199948 kb
Host smart-009f1e4e-5a8f-4f5d-af06-8066dfb28fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662538793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.662538793
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1924745324
Short name T448
Test name
Test status
Simulation time 1894680457 ps
CPU time 7.78 seconds
Started Jul 16 07:24:00 PM PDT 24
Finished Jul 16 07:24:29 PM PDT 24
Peak memory 221732 kb
Host smart-d5fdf5be-b3ee-4e55-bcaf-c1cd7b76b140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924745324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1924745324
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.28194893
Short name T126
Test name
Test status
Simulation time 244868921 ps
CPU time 1.03 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:24:43 PM PDT 24
Peak memory 217532 kb
Host smart-04458c95-4772-4e45-9ce6-4fd8aed1aa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28194893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.28194893
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3715915012
Short name T212
Test name
Test status
Simulation time 132780357 ps
CPU time 0.81 seconds
Started Jul 16 07:23:58 PM PDT 24
Finished Jul 16 07:24:18 PM PDT 24
Peak memory 199984 kb
Host smart-519ae05a-15b3-4cee-b650-4f9aae4933e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715915012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3715915012
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.628240138
Short name T84
Test name
Test status
Simulation time 1497966991 ps
CPU time 5.4 seconds
Started Jul 16 07:23:58 PM PDT 24
Finished Jul 16 07:24:22 PM PDT 24
Peak memory 200384 kb
Host smart-f19a82af-a723-4918-adc3-89319984aeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628240138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.628240138
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2501663447
Short name T218
Test name
Test status
Simulation time 152989708 ps
CPU time 1.15 seconds
Started Jul 16 07:23:59 PM PDT 24
Finished Jul 16 07:24:21 PM PDT 24
Peak memory 200096 kb
Host smart-9e4dee5a-d8ab-44a9-a745-b841b90d2a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501663447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2501663447
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2669647622
Short name T222
Test name
Test status
Simulation time 114122793 ps
CPU time 1.21 seconds
Started Jul 16 07:23:59 PM PDT 24
Finished Jul 16 07:24:21 PM PDT 24
Peak memory 200332 kb
Host smart-fbfc15ba-14a5-4328-a1e1-a19ade79b1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669647622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2669647622
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2554376389
Short name T175
Test name
Test status
Simulation time 10217609761 ps
CPU time 37.7 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:25:20 PM PDT 24
Peak memory 208736 kb
Host smart-c1dcaaef-81bb-4ae9-a453-5d7741a3bdbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554376389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2554376389
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3301778530
Short name T388
Test name
Test status
Simulation time 337783236 ps
CPU time 2.38 seconds
Started Jul 16 07:23:58 PM PDT 24
Finished Jul 16 07:24:20 PM PDT 24
Peak memory 200188 kb
Host smart-ef74b215-cdcb-430b-b162-db7a5422fad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301778530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3301778530
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1555773727
Short name T261
Test name
Test status
Simulation time 230781235 ps
CPU time 1.33 seconds
Started Jul 16 07:23:56 PM PDT 24
Finished Jul 16 07:24:15 PM PDT 24
Peak memory 200088 kb
Host smart-818f80da-aed6-4d9d-a314-5e0e33ee1627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555773727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1555773727
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2116373282
Short name T426
Test name
Test status
Simulation time 67453844 ps
CPU time 0.77 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:24:43 PM PDT 24
Peak memory 199956 kb
Host smart-70eccc65-a1fa-49b0-83a3-9629ffdd2237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116373282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2116373282
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3184262028
Short name T247
Test name
Test status
Simulation time 2351172624 ps
CPU time 7.41 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:24:48 PM PDT 24
Peak memory 221848 kb
Host smart-e6c755dd-be61-40ce-a676-7fc18c92ca20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184262028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3184262028
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3945227302
Short name T439
Test name
Test status
Simulation time 243788354 ps
CPU time 1.14 seconds
Started Jul 16 07:24:13 PM PDT 24
Finished Jul 16 07:24:46 PM PDT 24
Peak memory 217500 kb
Host smart-ee52ff23-e470-4015-b114-b6278ee6cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945227302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3945227302
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.4031330070
Short name T256
Test name
Test status
Simulation time 106617900 ps
CPU time 0.76 seconds
Started Jul 16 07:24:10 PM PDT 24
Finished Jul 16 07:24:39 PM PDT 24
Peak memory 199984 kb
Host smart-3ead9373-151b-4db5-b41e-7610fdcdf559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031330070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.4031330070
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2481579882
Short name T85
Test name
Test status
Simulation time 1548618643 ps
CPU time 5.8 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:24:46 PM PDT 24
Peak memory 200408 kb
Host smart-5741952d-43c4-41c6-a8ab-34987fecf94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481579882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2481579882
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.699294575
Short name T154
Test name
Test status
Simulation time 178900124 ps
CPU time 1.21 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 200152 kb
Host smart-20f085c7-4006-4a9c-88ba-2199190b5cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699294575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.699294575
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.140301726
Short name T295
Test name
Test status
Simulation time 256042525 ps
CPU time 1.54 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:24:45 PM PDT 24
Peak memory 200356 kb
Host smart-7465a370-9399-41c7-bd55-892040e2ac05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140301726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.140301726
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.9336532
Short name T89
Test name
Test status
Simulation time 5480156690 ps
CPU time 19.24 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:25:02 PM PDT 24
Peak memory 200460 kb
Host smart-63b5d2d3-3a7e-4423-bd4e-bf42c0b6b9c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9336532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.9336532
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.110396423
Short name T480
Test name
Test status
Simulation time 436442010 ps
CPU time 2.35 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 200068 kb
Host smart-bda5c049-3539-44b6-a8e5-71e5367bf218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110396423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.110396423
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3563668007
Short name T304
Test name
Test status
Simulation time 228283495 ps
CPU time 1.37 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:24:40 PM PDT 24
Peak memory 200144 kb
Host smart-86c21ba2-e2ff-47da-a155-2eb88a4a16da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563668007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3563668007
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.4050671269
Short name T115
Test name
Test status
Simulation time 67624335 ps
CPU time 0.73 seconds
Started Jul 16 07:21:59 PM PDT 24
Finished Jul 16 07:22:06 PM PDT 24
Peak memory 199892 kb
Host smart-964e35a1-f53a-4a7b-8b59-144c4266f1ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050671269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.4050671269
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.298386922
Short name T347
Test name
Test status
Simulation time 1890961545 ps
CPU time 6.81 seconds
Started Jul 16 07:21:59 PM PDT 24
Finished Jul 16 07:22:12 PM PDT 24
Peak memory 221636 kb
Host smart-75629a3b-ae03-4c2a-9b56-e32a075011c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298386922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.298386922
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.309953512
Short name T294
Test name
Test status
Simulation time 245235722 ps
CPU time 1.09 seconds
Started Jul 16 07:21:58 PM PDT 24
Finished Jul 16 07:22:06 PM PDT 24
Peak memory 217424 kb
Host smart-5c586872-711a-48f5-ae81-25b945a9022e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309953512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.309953512
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.636353176
Short name T375
Test name
Test status
Simulation time 234703633 ps
CPU time 0.96 seconds
Started Jul 16 07:21:58 PM PDT 24
Finished Jul 16 07:22:06 PM PDT 24
Peak memory 199948 kb
Host smart-04d53a6b-0bf8-40e9-a065-78be20642c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636353176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.636353176
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.845776822
Short name T386
Test name
Test status
Simulation time 1608133893 ps
CPU time 5.83 seconds
Started Jul 16 07:21:57 PM PDT 24
Finished Jul 16 07:22:10 PM PDT 24
Peak memory 200392 kb
Host smart-ee5a121d-0a7e-49b8-b2ca-0148afb7d978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845776822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.845776822
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1566188942
Short name T56
Test name
Test status
Simulation time 8530008121 ps
CPU time 12.19 seconds
Started Jul 16 07:21:56 PM PDT 24
Finished Jul 16 07:22:16 PM PDT 24
Peak memory 217088 kb
Host smart-a339ef2d-2296-445e-8cc1-8de76e1909f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566188942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1566188942
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3935575592
Short name T322
Test name
Test status
Simulation time 149205368 ps
CPU time 1.11 seconds
Started Jul 16 07:21:59 PM PDT 24
Finished Jul 16 07:22:08 PM PDT 24
Peak memory 200148 kb
Host smart-d27ebcda-41e9-41c1-95d5-983923ed0c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935575592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3935575592
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3341826703
Short name T285
Test name
Test status
Simulation time 120569841 ps
CPU time 1.17 seconds
Started Jul 16 07:21:59 PM PDT 24
Finished Jul 16 07:22:07 PM PDT 24
Peak memory 200316 kb
Host smart-30f2d06d-dc8e-4e11-879a-5188cde29a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341826703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3341826703
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2359280682
Short name T293
Test name
Test status
Simulation time 9108936476 ps
CPU time 36.24 seconds
Started Jul 16 07:21:59 PM PDT 24
Finished Jul 16 07:22:43 PM PDT 24
Peak memory 208644 kb
Host smart-acaca0dd-73ff-4598-a0c9-129f07926fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359280682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2359280682
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.264666373
Short name T140
Test name
Test status
Simulation time 308737503 ps
CPU time 1.96 seconds
Started Jul 16 07:22:00 PM PDT 24
Finished Jul 16 07:22:09 PM PDT 24
Peak memory 200132 kb
Host smart-0442156b-60c0-4783-977e-0469b1a2dec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264666373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.264666373
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1747064887
Short name T307
Test name
Test status
Simulation time 53904503 ps
CPU time 0.72 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 199956 kb
Host smart-d9fa3219-6632-46b5-8ac0-b0d6ddb61ff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747064887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1747064887
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1703946329
Short name T29
Test name
Test status
Simulation time 1890721396 ps
CPU time 7.35 seconds
Started Jul 16 07:24:55 PM PDT 24
Finished Jul 16 07:25:58 PM PDT 24
Peak memory 217792 kb
Host smart-be09cb51-d6b3-49de-8204-95b55681363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703946329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1703946329
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.66560582
Short name T454
Test name
Test status
Simulation time 244944880 ps
CPU time 1.06 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 217440 kb
Host smart-02d58632-bfe5-498f-adcc-79b0cfe34fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66560582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.66560582
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.833278390
Short name T530
Test name
Test status
Simulation time 95361697 ps
CPU time 0.77 seconds
Started Jul 16 07:24:14 PM PDT 24
Finished Jul 16 07:24:47 PM PDT 24
Peak memory 199940 kb
Host smart-725a6a92-cd14-4519-a861-3dbdf3f94007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833278390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.833278390
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2901870335
Short name T502
Test name
Test status
Simulation time 1641752734 ps
CPU time 6.51 seconds
Started Jul 16 07:24:13 PM PDT 24
Finished Jul 16 07:24:52 PM PDT 24
Peak memory 200440 kb
Host smart-400376f3-9963-4582-88e8-132094e07c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901870335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2901870335
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3981962073
Short name T514
Test name
Test status
Simulation time 93276790 ps
CPU time 0.98 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:24:43 PM PDT 24
Peak memory 200060 kb
Host smart-44cf7702-f4eb-46c5-8192-72cb61464c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981962073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3981962073
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.159628001
Short name T465
Test name
Test status
Simulation time 204865645 ps
CPU time 1.34 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:24:42 PM PDT 24
Peak memory 200272 kb
Host smart-7783f99c-0dbc-4b27-85ab-7b7e176acf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159628001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.159628001
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2708270771
Short name T62
Test name
Test status
Simulation time 5521575398 ps
CPU time 25.45 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:25:06 PM PDT 24
Peak memory 208672 kb
Host smart-2a03150b-efe3-43ef-bc95-b295c3100006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708270771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2708270771
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2021220220
Short name T390
Test name
Test status
Simulation time 146868980 ps
CPU time 1.74 seconds
Started Jul 16 07:24:10 PM PDT 24
Finished Jul 16 07:24:42 PM PDT 24
Peak memory 200200 kb
Host smart-6077f7c7-fcf3-4d98-aabb-f5a07ea824ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021220220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2021220220
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2518179532
Short name T496
Test name
Test status
Simulation time 81082779 ps
CPU time 0.82 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 200164 kb
Host smart-3a982e86-004e-405f-9051-cf01b31213b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518179532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2518179532
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.760282496
Short name T472
Test name
Test status
Simulation time 59069862 ps
CPU time 0.73 seconds
Started Jul 16 07:24:13 PM PDT 24
Finished Jul 16 07:24:47 PM PDT 24
Peak memory 199884 kb
Host smart-fcf8102f-a0b3-40e4-bda9-44c64575f94c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760282496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.760282496
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.827408579
Short name T33
Test name
Test status
Simulation time 2357919277 ps
CPU time 7.69 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:51 PM PDT 24
Peak memory 217972 kb
Host smart-83109a74-d326-4d66-8155-6525d1ba2bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827408579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.827408579
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.145801997
Short name T298
Test name
Test status
Simulation time 243870001 ps
CPU time 1.03 seconds
Started Jul 16 07:24:14 PM PDT 24
Finished Jul 16 07:24:48 PM PDT 24
Peak memory 217456 kb
Host smart-09f0669d-b66d-49f2-bc42-99f5bc3478fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145801997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.145801997
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1853012702
Short name T503
Test name
Test status
Simulation time 135273595 ps
CPU time 0.84 seconds
Started Jul 16 07:24:14 PM PDT 24
Finished Jul 16 07:24:51 PM PDT 24
Peak memory 199952 kb
Host smart-263dcf59-3e8a-443b-a1bb-4e8a59035c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853012702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1853012702
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.877887235
Short name T156
Test name
Test status
Simulation time 1468007101 ps
CPU time 5.69 seconds
Started Jul 16 07:24:10 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 200648 kb
Host smart-361a307d-5642-4232-b216-59ab670d8dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877887235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.877887235
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1120608643
Short name T211
Test name
Test status
Simulation time 108778258 ps
CPU time 1 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:43 PM PDT 24
Peak memory 200156 kb
Host smart-075dbc57-1d08-45eb-a9db-afd6072a23a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120608643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1120608643
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.793266963
Short name T392
Test name
Test status
Simulation time 117732279 ps
CPU time 1.22 seconds
Started Jul 16 07:24:13 PM PDT 24
Finished Jul 16 07:24:47 PM PDT 24
Peak memory 200324 kb
Host smart-4c83f489-db9e-47e5-8dfe-41981cceec36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793266963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.793266963
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1888923949
Short name T481
Test name
Test status
Simulation time 4233184396 ps
CPU time 13.68 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:57 PM PDT 24
Peak memory 208696 kb
Host smart-741d2eb4-3003-4b9d-a99e-5fc6bd18fbc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888923949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1888923949
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.4227374561
Short name T528
Test name
Test status
Simulation time 146453011 ps
CPU time 1.65 seconds
Started Jul 16 07:24:10 PM PDT 24
Finished Jul 16 07:24:40 PM PDT 24
Peak memory 200052 kb
Host smart-67431a89-63e6-41d6-b13c-4fa0864b80ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227374561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.4227374561
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2596189764
Short name T260
Test name
Test status
Simulation time 76325551 ps
CPU time 0.79 seconds
Started Jul 16 07:24:10 PM PDT 24
Finished Jul 16 07:24:41 PM PDT 24
Peak memory 200108 kb
Host smart-8442a526-a0b7-4d75-a102-d90355852f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596189764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2596189764
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.4104630641
Short name T138
Test name
Test status
Simulation time 57910485 ps
CPU time 0.72 seconds
Started Jul 16 07:24:23 PM PDT 24
Finished Jul 16 07:25:02 PM PDT 24
Peak memory 199948 kb
Host smart-1a934ae9-3be4-4051-b48f-adb130c012aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104630641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.4104630641
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2643959592
Short name T413
Test name
Test status
Simulation time 2353260804 ps
CPU time 8.6 seconds
Started Jul 16 07:24:13 PM PDT 24
Finished Jul 16 07:24:55 PM PDT 24
Peak memory 221760 kb
Host smart-0a00d6ff-7849-4569-b8a0-8f72f0de1274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643959592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2643959592
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.402938974
Short name T69
Test name
Test status
Simulation time 244780037 ps
CPU time 1.02 seconds
Started Jul 16 07:24:11 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 217540 kb
Host smart-8ceb7b0b-3ee0-4170-8d8c-d7e4c2c83fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402938974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.402938974
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.426144485
Short name T16
Test name
Test status
Simulation time 135525535 ps
CPU time 0.81 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 199948 kb
Host smart-d48f33b0-82ef-45b3-8cc5-db507cd3d8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426144485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.426144485
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.653594514
Short name T196
Test name
Test status
Simulation time 1223948610 ps
CPU time 5.14 seconds
Started Jul 16 07:24:10 PM PDT 24
Finished Jul 16 07:24:45 PM PDT 24
Peak memory 200440 kb
Host smart-fa714fa0-e6fa-4648-8846-0297948a86ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653594514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.653594514
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2655664202
Short name T189
Test name
Test status
Simulation time 181695314 ps
CPU time 1.27 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 200176 kb
Host smart-5ee11ead-d6ed-4896-9cf0-f7b4f73f0814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655664202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2655664202
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1445415338
Short name T515
Test name
Test status
Simulation time 237072969 ps
CPU time 1.45 seconds
Started Jul 16 07:24:09 PM PDT 24
Finished Jul 16 07:24:37 PM PDT 24
Peak memory 200360 kb
Host smart-eb7cea80-7ec7-4f53-b608-90335df2a302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445415338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1445415338
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2873317021
Short name T38
Test name
Test status
Simulation time 5053570660 ps
CPU time 21.55 seconds
Started Jul 16 07:24:23 PM PDT 24
Finished Jul 16 07:25:23 PM PDT 24
Peak memory 208868 kb
Host smart-3d6a55e1-45ea-40d5-a8fa-ee31d071ee81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873317021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2873317021
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2270065019
Short name T169
Test name
Test status
Simulation time 343820133 ps
CPU time 2.17 seconds
Started Jul 16 07:24:09 PM PDT 24
Finished Jul 16 07:24:37 PM PDT 24
Peak memory 200152 kb
Host smart-efdfd107-49f8-4218-bd6d-22b8018096ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270065019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2270065019
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.4097942816
Short name T282
Test name
Test status
Simulation time 133662565 ps
CPU time 1.11 seconds
Started Jul 16 07:24:12 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 200080 kb
Host smart-5d853102-dd8e-49d0-a403-dc0fbb926023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097942816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.4097942816
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.11800554
Short name T184
Test name
Test status
Simulation time 56152203 ps
CPU time 0.71 seconds
Started Jul 16 07:24:23 PM PDT 24
Finished Jul 16 07:25:02 PM PDT 24
Peak memory 199988 kb
Host smart-9121a17d-c093-44fe-bd56-0eb3bac544be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11800554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.11800554
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3839354870
Short name T40
Test name
Test status
Simulation time 2354346705 ps
CPU time 8.72 seconds
Started Jul 16 07:24:22 PM PDT 24
Finished Jul 16 07:25:10 PM PDT 24
Peak memory 221732 kb
Host smart-07bbf0aa-7a49-4be0-973a-8cb102cd2ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839354870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3839354870
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2930905744
Short name T403
Test name
Test status
Simulation time 243941106 ps
CPU time 1.1 seconds
Started Jul 16 07:24:22 PM PDT 24
Finished Jul 16 07:24:59 PM PDT 24
Peak memory 217540 kb
Host smart-d52ceb92-9b1b-4726-9c2e-7d027aa05bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930905744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2930905744
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.779516738
Short name T235
Test name
Test status
Simulation time 207321837 ps
CPU time 0.88 seconds
Started Jul 16 07:24:23 PM PDT 24
Finished Jul 16 07:25:05 PM PDT 24
Peak memory 199972 kb
Host smart-e49307a6-5143-478b-b641-f1b5002425fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779516738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.779516738
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.128235326
Short name T352
Test name
Test status
Simulation time 875362065 ps
CPU time 4.27 seconds
Started Jul 16 07:24:24 PM PDT 24
Finished Jul 16 07:25:10 PM PDT 24
Peak memory 200440 kb
Host smart-5d26d811-636f-486f-901a-68f49025ee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128235326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.128235326
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2280552422
Short name T497
Test name
Test status
Simulation time 139816528 ps
CPU time 1.1 seconds
Started Jul 16 07:24:24 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 200108 kb
Host smart-3093bb47-74a4-4c61-b441-376f33a0226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280552422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2280552422
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.4180195104
Short name T206
Test name
Test status
Simulation time 198447099 ps
CPU time 1.41 seconds
Started Jul 16 07:24:24 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 200348 kb
Host smart-8a0d124e-b388-4ed9-bfa2-a8cc8bff9a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180195104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.4180195104
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.791238266
Short name T311
Test name
Test status
Simulation time 14017568368 ps
CPU time 42.95 seconds
Started Jul 16 07:24:24 PM PDT 24
Finished Jul 16 07:25:49 PM PDT 24
Peak memory 200400 kb
Host smart-edc11d73-7866-4087-a7e9-69309aac7686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791238266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.791238266
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.727169084
Short name T225
Test name
Test status
Simulation time 143573548 ps
CPU time 1.8 seconds
Started Jul 16 07:24:23 PM PDT 24
Finished Jul 16 07:25:03 PM PDT 24
Peak memory 200192 kb
Host smart-27fafa1b-4847-40f0-94d6-b64fc0ade416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727169084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.727169084
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2785432110
Short name T279
Test name
Test status
Simulation time 162698488 ps
CPU time 1.19 seconds
Started Jul 16 07:24:25 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 200412 kb
Host smart-99403ae0-9b73-45bb-b89d-665f3ee2dc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785432110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2785432110
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3068148089
Short name T310
Test name
Test status
Simulation time 77331353 ps
CPU time 0.84 seconds
Started Jul 16 07:24:27 PM PDT 24
Finished Jul 16 07:25:11 PM PDT 24
Peak memory 199888 kb
Host smart-dd0d04cb-58eb-4e61-87ca-78ba18f7241b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068148089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3068148089
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3308930243
Short name T281
Test name
Test status
Simulation time 1223173796 ps
CPU time 5.24 seconds
Started Jul 16 07:24:26 PM PDT 24
Finished Jul 16 07:25:14 PM PDT 24
Peak memory 221652 kb
Host smart-7eba1a6f-c784-407d-acb5-40fbc4900512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308930243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3308930243
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3950898956
Short name T320
Test name
Test status
Simulation time 244286771 ps
CPU time 1.05 seconds
Started Jul 16 07:24:25 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 217512 kb
Host smart-6bef031a-a5eb-4d92-9ad0-25bb72fb5e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950898956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3950898956
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.445074916
Short name T21
Test name
Test status
Simulation time 184165173 ps
CPU time 0.91 seconds
Started Jul 16 07:24:23 PM PDT 24
Finished Jul 16 07:25:03 PM PDT 24
Peak memory 199928 kb
Host smart-aff564d7-63c1-49b7-84f2-70c61114ecd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445074916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.445074916
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1727147374
Short name T353
Test name
Test status
Simulation time 1479127783 ps
CPU time 6.19 seconds
Started Jul 16 07:24:25 PM PDT 24
Finished Jul 16 07:25:12 PM PDT 24
Peak memory 200420 kb
Host smart-43c06cf4-24ec-4218-9671-2c2700789997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727147374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1727147374
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.507833922
Short name T116
Test name
Test status
Simulation time 146863928 ps
CPU time 1.1 seconds
Started Jul 16 07:24:26 PM PDT 24
Finished Jul 16 07:25:11 PM PDT 24
Peak memory 200156 kb
Host smart-7bc1517c-f188-42e6-95a1-f5cd793cb0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507833922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.507833922
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.578474330
Short name T524
Test name
Test status
Simulation time 247107632 ps
CPU time 1.43 seconds
Started Jul 16 07:24:23 PM PDT 24
Finished Jul 16 07:25:03 PM PDT 24
Peak memory 200308 kb
Host smart-3df06170-bbd8-4b5d-a944-30153a6dea63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578474330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.578474330
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.486635022
Short name T336
Test name
Test status
Simulation time 7242455398 ps
CPU time 26.71 seconds
Started Jul 16 07:24:27 PM PDT 24
Finished Jul 16 07:25:36 PM PDT 24
Peak memory 200408 kb
Host smart-7e8cff5b-1237-4b10-9913-5250c268ba38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486635022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.486635022
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1622217971
Short name T143
Test name
Test status
Simulation time 395988129 ps
CPU time 2.16 seconds
Started Jul 16 07:24:26 PM PDT 24
Finished Jul 16 07:25:12 PM PDT 24
Peak memory 200184 kb
Host smart-5dcf6cfe-383b-4817-bcb6-98ae3a2716fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622217971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1622217971
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3321440576
Short name T342
Test name
Test status
Simulation time 73156853 ps
CPU time 0.78 seconds
Started Jul 16 07:24:26 PM PDT 24
Finished Jul 16 07:25:09 PM PDT 24
Peak memory 200144 kb
Host smart-63a3df2e-35f3-42f5-8e64-97e54d043a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321440576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3321440576
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2388337582
Short name T428
Test name
Test status
Simulation time 66788666 ps
CPU time 0.71 seconds
Started Jul 16 07:24:25 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 199916 kb
Host smart-5a9a171c-ae67-4905-a6c2-309d34de50c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388337582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2388337582
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2843789703
Short name T404
Test name
Test status
Simulation time 1889716461 ps
CPU time 7.14 seconds
Started Jul 16 07:24:29 PM PDT 24
Finished Jul 16 07:25:21 PM PDT 24
Peak memory 221644 kb
Host smart-9ebdc347-a306-4f20-b4de-0bb921b1f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843789703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2843789703
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.674059890
Short name T150
Test name
Test status
Simulation time 244903571 ps
CPU time 1.04 seconds
Started Jul 16 07:24:32 PM PDT 24
Finished Jul 16 07:25:20 PM PDT 24
Peak memory 217552 kb
Host smart-39f8f2ed-6f08-41cb-8fec-c3be091a1cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674059890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.674059890
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2379172276
Short name T234
Test name
Test status
Simulation time 184248658 ps
CPU time 0.85 seconds
Started Jul 16 07:24:27 PM PDT 24
Finished Jul 16 07:25:11 PM PDT 24
Peak memory 199932 kb
Host smart-7a3c9eaf-eab5-41a3-b4ba-c6bcc58368ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379172276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2379172276
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.423404335
Short name T277
Test name
Test status
Simulation time 1020917915 ps
CPU time 4.67 seconds
Started Jul 16 07:24:24 PM PDT 24
Finished Jul 16 07:25:10 PM PDT 24
Peak memory 200316 kb
Host smart-415ee9fc-a3e3-435c-afed-7f83bf612db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423404335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.423404335
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.103571660
Short name T202
Test name
Test status
Simulation time 153695995 ps
CPU time 1.09 seconds
Started Jul 16 07:24:25 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 200076 kb
Host smart-c0001457-84b8-44fe-aa6c-580b96b23ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103571660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.103571660
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1440745301
Short name T377
Test name
Test status
Simulation time 197023420 ps
CPU time 1.37 seconds
Started Jul 16 07:24:26 PM PDT 24
Finished Jul 16 07:25:10 PM PDT 24
Peak memory 200308 kb
Host smart-b5b47bdb-1642-403e-8a46-d02586e6fcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440745301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1440745301
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.766066507
Short name T346
Test name
Test status
Simulation time 3343972027 ps
CPU time 12.9 seconds
Started Jul 16 07:24:26 PM PDT 24
Finished Jul 16 07:25:22 PM PDT 24
Peak memory 200416 kb
Host smart-d12481d3-4e63-4a0c-84ea-2c5acdf6537d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766066507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.766066507
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.503196888
Short name T325
Test name
Test status
Simulation time 141996035 ps
CPU time 1.79 seconds
Started Jul 16 07:24:28 PM PDT 24
Finished Jul 16 07:25:12 PM PDT 24
Peak memory 200168 kb
Host smart-bfb97433-bdb4-485e-bacc-a445c7dd2530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503196888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.503196888
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3865104084
Short name T129
Test name
Test status
Simulation time 85030776 ps
CPU time 0.87 seconds
Started Jul 16 07:24:27 PM PDT 24
Finished Jul 16 07:25:11 PM PDT 24
Peak memory 200176 kb
Host smart-f9d196a5-d5a9-4914-a621-80b79e3786b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865104084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3865104084
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2345489851
Short name T345
Test name
Test status
Simulation time 88989878 ps
CPU time 0.77 seconds
Started Jul 16 07:24:28 PM PDT 24
Finished Jul 16 07:25:12 PM PDT 24
Peak memory 199936 kb
Host smart-06724539-427a-484c-b1fa-ebd693c18591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345489851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2345489851
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3968896679
Short name T495
Test name
Test status
Simulation time 1886220496 ps
CPU time 6.72 seconds
Started Jul 16 07:24:27 PM PDT 24
Finished Jul 16 07:25:17 PM PDT 24
Peak memory 217728 kb
Host smart-44ea93c5-7ef7-47e3-9896-43867ae745b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968896679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3968896679
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1221229970
Short name T299
Test name
Test status
Simulation time 244152685 ps
CPU time 1.1 seconds
Started Jul 16 07:24:30 PM PDT 24
Finished Jul 16 07:25:15 PM PDT 24
Peak memory 217500 kb
Host smart-6121e6f3-50f2-4128-8da5-32e7e828fe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221229970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1221229970
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.271051321
Short name T391
Test name
Test status
Simulation time 198361117 ps
CPU time 0.86 seconds
Started Jul 16 07:24:26 PM PDT 24
Finished Jul 16 07:25:10 PM PDT 24
Peak memory 199900 kb
Host smart-a87f06ed-7997-4f68-91af-116bda3653c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271051321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.271051321
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.140935952
Short name T460
Test name
Test status
Simulation time 1083832409 ps
CPU time 5.33 seconds
Started Jul 16 07:24:30 PM PDT 24
Finished Jul 16 07:25:20 PM PDT 24
Peak memory 200412 kb
Host smart-35222f89-9b5c-41e9-a73f-37f4f88c36da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140935952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.140935952
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3737361574
Short name T130
Test name
Test status
Simulation time 103825900 ps
CPU time 0.94 seconds
Started Jul 16 07:24:26 PM PDT 24
Finished Jul 16 07:25:10 PM PDT 24
Peak memory 200072 kb
Host smart-44e56ecb-346a-4d49-9605-daea807d265c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737361574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3737361574
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.454158689
Short name T165
Test name
Test status
Simulation time 110032358 ps
CPU time 1.16 seconds
Started Jul 16 07:24:32 PM PDT 24
Finished Jul 16 07:25:19 PM PDT 24
Peak memory 200404 kb
Host smart-c14c9dd3-2d3b-403e-a10d-103e0bed1f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454158689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.454158689
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3053323537
Short name T11
Test name
Test status
Simulation time 3922144502 ps
CPU time 15.07 seconds
Started Jul 16 07:24:28 PM PDT 24
Finished Jul 16 07:25:26 PM PDT 24
Peak memory 208664 kb
Host smart-8af73671-b45d-43d4-acca-2bcc1a525c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053323537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3053323537
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1625103762
Short name T331
Test name
Test status
Simulation time 147855907 ps
CPU time 1.68 seconds
Started Jul 16 07:24:26 PM PDT 24
Finished Jul 16 07:25:11 PM PDT 24
Peak memory 200188 kb
Host smart-ab89c430-b699-465a-972c-67f2ac5c2e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625103762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1625103762
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2568857799
Short name T266
Test name
Test status
Simulation time 88946880 ps
CPU time 0.84 seconds
Started Jul 16 07:24:32 PM PDT 24
Finished Jul 16 07:25:20 PM PDT 24
Peak memory 200176 kb
Host smart-4f944523-9041-4adc-8a8d-f76b9549aab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568857799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2568857799
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2883087523
Short name T65
Test name
Test status
Simulation time 98158066 ps
CPU time 0.88 seconds
Started Jul 16 07:24:23 PM PDT 24
Finished Jul 16 07:25:02 PM PDT 24
Peak memory 199888 kb
Host smart-b35c9506-470a-4afe-a2d1-d179f8517b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883087523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2883087523
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3269067841
Short name T10
Test name
Test status
Simulation time 1881174799 ps
CPU time 7.92 seconds
Started Jul 16 07:24:27 PM PDT 24
Finished Jul 16 07:25:18 PM PDT 24
Peak memory 221764 kb
Host smart-2a5b76c7-432a-49ad-b654-d92a1288e0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269067841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3269067841
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3186278542
Short name T272
Test name
Test status
Simulation time 245022928 ps
CPU time 1.01 seconds
Started Jul 16 07:24:27 PM PDT 24
Finished Jul 16 07:25:12 PM PDT 24
Peak memory 217544 kb
Host smart-c8d00fa2-7dde-4d67-b8f7-2a9d5dea00e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186278542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3186278542
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1526043610
Short name T228
Test name
Test status
Simulation time 189206911 ps
CPU time 0.87 seconds
Started Jul 16 07:24:32 PM PDT 24
Finished Jul 16 07:25:19 PM PDT 24
Peak memory 199984 kb
Host smart-4a735857-b253-4b94-83ab-ba32302038f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526043610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1526043610
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2900175597
Short name T251
Test name
Test status
Simulation time 991626588 ps
CPU time 5.04 seconds
Started Jul 16 07:24:27 PM PDT 24
Finished Jul 16 07:25:15 PM PDT 24
Peak memory 200400 kb
Host smart-fd304960-6edb-4a67-8b34-eca450e15ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900175597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2900175597
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1368880340
Short name T444
Test name
Test status
Simulation time 144033006 ps
CPU time 1.08 seconds
Started Jul 16 07:24:29 PM PDT 24
Finished Jul 16 07:25:15 PM PDT 24
Peak memory 200168 kb
Host smart-e7261ea2-d30e-4c5b-8815-507dc2500837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368880340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1368880340
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3282283655
Short name T396
Test name
Test status
Simulation time 245856493 ps
CPU time 1.46 seconds
Started Jul 16 07:24:25 PM PDT 24
Finished Jul 16 07:25:08 PM PDT 24
Peak memory 200300 kb
Host smart-ec18f118-add4-45c4-a2d0-10d4df18eacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282283655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3282283655
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1407097317
Short name T270
Test name
Test status
Simulation time 2351476233 ps
CPU time 9.29 seconds
Started Jul 16 07:24:25 PM PDT 24
Finished Jul 16 07:25:16 PM PDT 24
Peak memory 216800 kb
Host smart-97420d76-31b0-4e5e-ba3c-3d40ef354fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407097317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1407097317
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1668690457
Short name T68
Test name
Test status
Simulation time 156272282 ps
CPU time 1.87 seconds
Started Jul 16 07:24:30 PM PDT 24
Finished Jul 16 07:25:16 PM PDT 24
Peak memory 200160 kb
Host smart-7462805c-e2c3-4ae2-a9e2-747e004cd38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668690457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1668690457
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2869976034
Short name T273
Test name
Test status
Simulation time 84327445 ps
CPU time 0.85 seconds
Started Jul 16 07:24:27 PM PDT 24
Finished Jul 16 07:25:11 PM PDT 24
Peak memory 200156 kb
Host smart-6d633aee-410b-40a2-bd79-64f09e0396f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869976034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2869976034
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1700226339
Short name T374
Test name
Test status
Simulation time 76987133 ps
CPU time 0.8 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:29 PM PDT 24
Peak memory 199948 kb
Host smart-9f9dc447-d455-4f15-b64b-ac2932d7735c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700226339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1700226339
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.948846447
Short name T31
Test name
Test status
Simulation time 1229205924 ps
CPU time 5.35 seconds
Started Jul 16 07:24:33 PM PDT 24
Finished Jul 16 07:25:26 PM PDT 24
Peak memory 217812 kb
Host smart-1126097b-e344-45d7-8de7-b91fb75a0c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948846447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.948846447
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2628059085
Short name T432
Test name
Test status
Simulation time 243955378 ps
CPU time 1.09 seconds
Started Jul 16 07:24:35 PM PDT 24
Finished Jul 16 07:25:26 PM PDT 24
Peak memory 217456 kb
Host smart-b2ac3bc2-8e96-4d22-aff9-5d90ace97d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628059085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2628059085
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.14494573
Short name T18
Test name
Test status
Simulation time 112868544 ps
CPU time 0.77 seconds
Started Jul 16 07:24:25 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 199948 kb
Host smart-6f142ace-7b48-41ef-95e3-a91f4fca601f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14494573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.14494573
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.76751104
Short name T173
Test name
Test status
Simulation time 801825238 ps
CPU time 4.35 seconds
Started Jul 16 07:24:25 PM PDT 24
Finished Jul 16 07:25:11 PM PDT 24
Peak memory 200344 kb
Host smart-b04c1c22-7c34-4c8f-a291-1434d865e5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76751104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.76751104
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2726033179
Short name T522
Test name
Test status
Simulation time 186872440 ps
CPU time 1.14 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:30 PM PDT 24
Peak memory 200120 kb
Host smart-774eda95-870a-45dd-9667-27fc1ce66017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726033179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2726033179
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.392953588
Short name T487
Test name
Test status
Simulation time 197995494 ps
CPU time 1.41 seconds
Started Jul 16 07:24:24 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 200328 kb
Host smart-1325e3fe-d787-4480-8064-d0db14072820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392953588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.392953588
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3083475029
Short name T63
Test name
Test status
Simulation time 1028795749 ps
CPU time 4.42 seconds
Started Jul 16 07:24:33 PM PDT 24
Finished Jul 16 07:25:25 PM PDT 24
Peak memory 200440 kb
Host smart-917c589b-58e6-4f49-b32d-90940d0d890c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083475029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3083475029
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1782749128
Short name T296
Test name
Test status
Simulation time 139071610 ps
CPU time 1.72 seconds
Started Jul 16 07:24:35 PM PDT 24
Finished Jul 16 07:25:27 PM PDT 24
Peak memory 200156 kb
Host smart-7f9cc9a3-d173-44ca-99e7-fc9b08badf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782749128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1782749128
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2762878265
Short name T67
Test name
Test status
Simulation time 65063235 ps
CPU time 0.8 seconds
Started Jul 16 07:25:10 PM PDT 24
Finished Jul 16 07:26:08 PM PDT 24
Peak memory 200072 kb
Host smart-23ec0a6d-b64a-4dc8-b8c5-72ed560038f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762878265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2762878265
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2511048349
Short name T113
Test name
Test status
Simulation time 73915288 ps
CPU time 0.78 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:27 PM PDT 24
Peak memory 199952 kb
Host smart-ae1ba554-64c0-4585-8565-3ac4d857f1d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511048349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2511048349
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1962295910
Short name T358
Test name
Test status
Simulation time 2187706649 ps
CPU time 7.78 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:36 PM PDT 24
Peak memory 221812 kb
Host smart-5ae57bc4-7339-44e9-a4a0-0111e9bf6c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962295910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1962295910
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1124597727
Short name T120
Test name
Test status
Simulation time 244659444 ps
CPU time 1.04 seconds
Started Jul 16 07:24:35 PM PDT 24
Finished Jul 16 07:25:27 PM PDT 24
Peak memory 217524 kb
Host smart-9b3dc6bd-b640-4468-9569-696e5dd6278f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124597727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1124597727
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.595514923
Short name T227
Test name
Test status
Simulation time 89074491 ps
CPU time 0.73 seconds
Started Jul 16 07:24:34 PM PDT 24
Finished Jul 16 07:25:22 PM PDT 24
Peak memory 199972 kb
Host smart-551471f8-cc03-47ad-9919-73cf8716edcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595514923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.595514923
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3921509919
Short name T477
Test name
Test status
Simulation time 841073425 ps
CPU time 4.38 seconds
Started Jul 16 07:24:34 PM PDT 24
Finished Jul 16 07:25:25 PM PDT 24
Peak memory 200392 kb
Host smart-162734ff-436d-4b37-bf6c-94347b9f31cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921509919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3921509919
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2567317253
Short name T182
Test name
Test status
Simulation time 153233939 ps
CPU time 1.15 seconds
Started Jul 16 07:24:33 PM PDT 24
Finished Jul 16 07:25:22 PM PDT 24
Peak memory 200160 kb
Host smart-033a5149-fc8f-4648-9eaa-791350d95914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567317253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2567317253
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.868055735
Short name T523
Test name
Test status
Simulation time 201196088 ps
CPU time 1.38 seconds
Started Jul 16 07:24:34 PM PDT 24
Finished Jul 16 07:25:22 PM PDT 24
Peak memory 200376 kb
Host smart-926dc59a-d854-4171-9e68-6087f62929f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868055735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.868055735
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2188506031
Short name T92
Test name
Test status
Simulation time 10393827696 ps
CPU time 36.93 seconds
Started Jul 16 07:24:36 PM PDT 24
Finished Jul 16 07:26:03 PM PDT 24
Peak memory 210284 kb
Host smart-32ab7ec4-cc7a-44df-8c63-97cda7232928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188506031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2188506031
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.154003849
Short name T158
Test name
Test status
Simulation time 342278903 ps
CPU time 1.95 seconds
Started Jul 16 07:24:35 PM PDT 24
Finished Jul 16 07:25:27 PM PDT 24
Peak memory 200348 kb
Host smart-9928df5e-1477-4a4c-9079-1c950440431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154003849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.154003849
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3795514023
Short name T197
Test name
Test status
Simulation time 90941176 ps
CPU time 0.84 seconds
Started Jul 16 07:24:34 PM PDT 24
Finished Jul 16 07:25:20 PM PDT 24
Peak memory 200112 kb
Host smart-cfd36f1a-de47-4383-81c3-8a187669b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795514023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3795514023
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4096947167
Short name T440
Test name
Test status
Simulation time 66980717 ps
CPU time 0.69 seconds
Started Jul 16 07:22:11 PM PDT 24
Finished Jul 16 07:22:20 PM PDT 24
Peak memory 199988 kb
Host smart-547029fe-b2f1-4b86-b4d8-93064b4ad2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096947167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4096947167
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1616149758
Short name T262
Test name
Test status
Simulation time 2355959430 ps
CPU time 7.98 seconds
Started Jul 16 07:22:09 PM PDT 24
Finished Jul 16 07:22:24 PM PDT 24
Peak memory 221788 kb
Host smart-90567bca-f985-4a38-9eb0-594d938b465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616149758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1616149758
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4213130297
Short name T416
Test name
Test status
Simulation time 243703409 ps
CPU time 1.1 seconds
Started Jul 16 07:22:10 PM PDT 24
Finished Jul 16 07:22:17 PM PDT 24
Peak memory 217540 kb
Host smart-04f87766-9aef-4183-89fa-96978ae63366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213130297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4213130297
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2115009469
Short name T533
Test name
Test status
Simulation time 112540139 ps
CPU time 0.76 seconds
Started Jul 16 07:21:58 PM PDT 24
Finished Jul 16 07:22:06 PM PDT 24
Peak memory 199964 kb
Host smart-c948978b-9128-403d-a3dd-8d423a14b702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115009469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2115009469
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.332279724
Short name T174
Test name
Test status
Simulation time 747334083 ps
CPU time 3.88 seconds
Started Jul 16 07:22:00 PM PDT 24
Finished Jul 16 07:22:11 PM PDT 24
Peak memory 200472 kb
Host smart-a8eec4e8-c3f4-419c-999b-f5a8103b7aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332279724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.332279724
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3174275656
Short name T54
Test name
Test status
Simulation time 17723787972 ps
CPU time 25.44 seconds
Started Jul 16 07:22:12 PM PDT 24
Finished Jul 16 07:22:48 PM PDT 24
Peak memory 217484 kb
Host smart-1926a914-6482-404f-b85c-3bf1ce7d0303
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174275656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3174275656
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1046131545
Short name T317
Test name
Test status
Simulation time 104814203 ps
CPU time 0.95 seconds
Started Jul 16 07:22:14 PM PDT 24
Finished Jul 16 07:22:29 PM PDT 24
Peak memory 200140 kb
Host smart-c8ecaeb0-f226-4d50-816a-c7b77df65e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046131545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1046131545
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1811542457
Short name T289
Test name
Test status
Simulation time 237695523 ps
CPU time 1.36 seconds
Started Jul 16 07:21:57 PM PDT 24
Finished Jul 16 07:22:05 PM PDT 24
Peak memory 200328 kb
Host smart-2fabb597-7771-47ad-9eb8-75fc6f6f8a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811542457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1811542457
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1295881069
Short name T223
Test name
Test status
Simulation time 6354668603 ps
CPU time 19.91 seconds
Started Jul 16 07:22:11 PM PDT 24
Finished Jul 16 07:22:40 PM PDT 24
Peak memory 208764 kb
Host smart-a2b12893-af52-4537-bf48-90f1c497cfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295881069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1295881069
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1719339854
Short name T420
Test name
Test status
Simulation time 459859482 ps
CPU time 2.41 seconds
Started Jul 16 07:22:10 PM PDT 24
Finished Jul 16 07:22:20 PM PDT 24
Peak memory 200192 kb
Host smart-730394b5-e0f8-478f-aec1-0debfe1884f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719339854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1719339854
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2605827838
Short name T302
Test name
Test status
Simulation time 130076915 ps
CPU time 1.01 seconds
Started Jul 16 07:22:11 PM PDT 24
Finished Jul 16 07:22:20 PM PDT 24
Peak memory 200124 kb
Host smart-d9c94675-3c5b-4a9b-8216-c37853ed4f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605827838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2605827838
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2600962201
Short name T137
Test name
Test status
Simulation time 75153265 ps
CPU time 0.77 seconds
Started Jul 16 07:24:42 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 199584 kb
Host smart-acc3b2d9-4966-42da-ac48-ee4f572fd3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600962201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2600962201
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.4089091653
Short name T443
Test name
Test status
Simulation time 1236715202 ps
CPU time 5.22 seconds
Started Jul 16 07:24:39 PM PDT 24
Finished Jul 16 07:25:33 PM PDT 24
Peak memory 217804 kb
Host smart-57938078-72c5-4302-a801-9128cb5cb4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089091653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.4089091653
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.721882356
Short name T241
Test name
Test status
Simulation time 244119104 ps
CPU time 1.08 seconds
Started Jul 16 07:24:42 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 217240 kb
Host smart-fedc4031-b078-404d-998c-7f4aed65a0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721882356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.721882356
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2734883748
Short name T424
Test name
Test status
Simulation time 198898019 ps
CPU time 0.94 seconds
Started Jul 16 07:24:35 PM PDT 24
Finished Jul 16 07:25:26 PM PDT 24
Peak memory 199964 kb
Host smart-851e9770-d0f8-422c-bf81-a9ba9e6f3ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734883748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2734883748
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.19434561
Short name T409
Test name
Test status
Simulation time 1616410723 ps
CPU time 5.73 seconds
Started Jul 16 07:24:36 PM PDT 24
Finished Jul 16 07:25:31 PM PDT 24
Peak memory 200432 kb
Host smart-92e741d1-7b76-48fd-946e-96264fa2bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19434561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.19434561
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4139150044
Short name T381
Test name
Test status
Simulation time 96531721 ps
CPU time 0.97 seconds
Started Jul 16 07:24:39 PM PDT 24
Finished Jul 16 07:25:29 PM PDT 24
Peak memory 200164 kb
Host smart-704a7453-dbb5-4679-8e3f-8ccace458add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139150044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4139150044
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1802045339
Short name T505
Test name
Test status
Simulation time 190951844 ps
CPU time 1.34 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:30 PM PDT 24
Peak memory 200336 kb
Host smart-643dd1b2-8b28-4101-b15b-67de1aedc3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802045339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1802045339
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2272492148
Short name T191
Test name
Test status
Simulation time 281442861 ps
CPU time 1.81 seconds
Started Jul 16 07:24:33 PM PDT 24
Finished Jul 16 07:25:22 PM PDT 24
Peak memory 200148 kb
Host smart-eb5e5a84-75a1-45d7-930a-e0e40040ac1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272492148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2272492148
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1931042706
Short name T200
Test name
Test status
Simulation time 136328842 ps
CPU time 1.06 seconds
Started Jul 16 07:24:33 PM PDT 24
Finished Jul 16 07:25:22 PM PDT 24
Peak memory 200176 kb
Host smart-b7ff39b9-78d8-4100-a9e5-a64f2f1e28a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931042706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1931042706
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.4211118867
Short name T199
Test name
Test status
Simulation time 70200797 ps
CPU time 0.75 seconds
Started Jul 16 07:24:35 PM PDT 24
Finished Jul 16 07:25:24 PM PDT 24
Peak memory 199880 kb
Host smart-e95f08ca-b0c0-4b57-8c55-15810143787c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211118867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.4211118867
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2757162667
Short name T387
Test name
Test status
Simulation time 1880673273 ps
CPU time 7.06 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:36 PM PDT 24
Peak memory 217792 kb
Host smart-fd6d8697-2d7e-4cde-9ba2-7ab936cdbced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757162667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2757162667
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3488862767
Short name T39
Test name
Test status
Simulation time 244863205 ps
CPU time 1.05 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:29 PM PDT 24
Peak memory 217568 kb
Host smart-46893dd4-dbdb-43af-bb97-727ba7fc3881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488862767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3488862767
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2476409617
Short name T329
Test name
Test status
Simulation time 186370256 ps
CPU time 0.85 seconds
Started Jul 16 07:24:42 PM PDT 24
Finished Jul 16 07:25:34 PM PDT 24
Peak memory 199960 kb
Host smart-8a89db25-1654-4dba-8c43-20ed4f508e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476409617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2476409617
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1482286850
Short name T466
Test name
Test status
Simulation time 907287784 ps
CPU time 4.44 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:33 PM PDT 24
Peak memory 200428 kb
Host smart-3b3af60f-ea82-4f2e-8fef-872f20eff082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482286850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1482286850
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1006402180
Short name T215
Test name
Test status
Simulation time 138698554 ps
CPU time 1.11 seconds
Started Jul 16 07:24:42 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 200144 kb
Host smart-5970b862-74cb-480c-ba75-c34bbf86181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006402180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1006402180
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1706957387
Short name T190
Test name
Test status
Simulation time 226579164 ps
CPU time 1.36 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:29 PM PDT 24
Peak memory 200336 kb
Host smart-279df35b-c46e-436e-bfc7-1a3b4c4d88ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706957387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1706957387
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1774291034
Short name T314
Test name
Test status
Simulation time 5380941448 ps
CPU time 22.03 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:51 PM PDT 24
Peak memory 200456 kb
Host smart-8d6c0e5a-a4e2-43b5-8564-0612ba1af481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774291034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1774291034
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2355727545
Short name T300
Test name
Test status
Simulation time 125070437 ps
CPU time 1.62 seconds
Started Jul 16 07:24:36 PM PDT 24
Finished Jul 16 07:25:27 PM PDT 24
Peak memory 200108 kb
Host smart-cd62c7a0-3af6-471d-91ea-e5f94addead8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355727545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2355727545
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2582393788
Short name T476
Test name
Test status
Simulation time 286992097 ps
CPU time 1.44 seconds
Started Jul 16 07:24:34 PM PDT 24
Finished Jul 16 07:25:22 PM PDT 24
Peak memory 200404 kb
Host smart-d3d4b448-cb99-44a7-8b75-68096f21a4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582393788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2582393788
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.4135347630
Short name T233
Test name
Test status
Simulation time 85404264 ps
CPU time 0.82 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:29 PM PDT 24
Peak memory 199928 kb
Host smart-b94748cd-ae15-4f03-b14d-54444796dbcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135347630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.4135347630
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.91076024
Short name T26
Test name
Test status
Simulation time 2373762763 ps
CPU time 7.75 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:36 PM PDT 24
Peak memory 217944 kb
Host smart-871ee4d6-337d-4507-a860-6f08e3049ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91076024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.91076024
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1236743944
Short name T356
Test name
Test status
Simulation time 244785035 ps
CPU time 1.02 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:26 PM PDT 24
Peak memory 217520 kb
Host smart-1ddc3b17-1dd0-4d5c-b96f-c0bf713b26fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236743944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1236743944
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.392021653
Short name T500
Test name
Test status
Simulation time 166617997 ps
CPU time 0.81 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:29 PM PDT 24
Peak memory 199952 kb
Host smart-6c80b849-1468-45ef-8a52-f6e3068ec16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392021653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.392021653
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1898389156
Short name T400
Test name
Test status
Simulation time 1829791759 ps
CPU time 6.52 seconds
Started Jul 16 07:24:39 PM PDT 24
Finished Jul 16 07:25:35 PM PDT 24
Peak memory 200436 kb
Host smart-095ac982-be5d-4717-8206-ae0db3777827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898389156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1898389156
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1370920000
Short name T144
Test name
Test status
Simulation time 94942990 ps
CPU time 1 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:30 PM PDT 24
Peak memory 200064 kb
Host smart-8ead2d36-8dab-4979-bc50-d6016dd5b963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370920000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1370920000
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2718986722
Short name T297
Test name
Test status
Simulation time 200778506 ps
CPU time 1.45 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:30 PM PDT 24
Peak memory 200388 kb
Host smart-4238c2bd-fffd-4f7d-bed0-2cf9c2236155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718986722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2718986722
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1847066812
Short name T192
Test name
Test status
Simulation time 219899945 ps
CPU time 1.49 seconds
Started Jul 16 07:24:42 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 208532 kb
Host smart-47e8cdd2-a3d4-475e-a80d-cf1e6091e16d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847066812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1847066812
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1014519729
Short name T351
Test name
Test status
Simulation time 298446215 ps
CPU time 1.93 seconds
Started Jul 16 07:24:39 PM PDT 24
Finished Jul 16 07:25:30 PM PDT 24
Peak memory 208368 kb
Host smart-e2589378-6b36-4afc-9047-5c458529dfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014519729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1014519729
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.122624402
Short name T73
Test name
Test status
Simulation time 183454102 ps
CPU time 1.1 seconds
Started Jul 16 07:24:36 PM PDT 24
Finished Jul 16 07:25:27 PM PDT 24
Peak memory 200124 kb
Host smart-1dbd93c6-2312-498c-ab31-2130f849cba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122624402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.122624402
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3090942048
Short name T407
Test name
Test status
Simulation time 121650005 ps
CPU time 0.85 seconds
Started Jul 16 07:24:39 PM PDT 24
Finished Jul 16 07:25:32 PM PDT 24
Peak memory 199932 kb
Host smart-d671c7a9-e33d-4bc0-a05e-5344f658cdd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090942048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3090942048
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2148387195
Short name T488
Test name
Test status
Simulation time 1893748799 ps
CPU time 6.71 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:34 PM PDT 24
Peak memory 221740 kb
Host smart-aeff44b5-4e44-4918-b894-df2384a902f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148387195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2148387195
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.87546178
Short name T14
Test name
Test status
Simulation time 244537261 ps
CPU time 1.02 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:29 PM PDT 24
Peak memory 217560 kb
Host smart-ee28f086-3acd-45d5-bdd1-a37cc4488b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87546178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.87546178
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.320045007
Short name T160
Test name
Test status
Simulation time 166652873 ps
CPU time 0.91 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:29 PM PDT 24
Peak memory 199956 kb
Host smart-a29bae54-375d-497d-a286-359148fa3af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320045007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.320045007
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3171643807
Short name T354
Test name
Test status
Simulation time 886085031 ps
CPU time 4.4 seconds
Started Jul 16 07:24:32 PM PDT 24
Finished Jul 16 07:25:24 PM PDT 24
Peak memory 200440 kb
Host smart-35e8f98d-6b7f-47aa-aca4-98ee79f7e8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171643807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3171643807
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3827252394
Short name T436
Test name
Test status
Simulation time 149247381 ps
CPU time 1.14 seconds
Started Jul 16 07:24:34 PM PDT 24
Finished Jul 16 07:25:22 PM PDT 24
Peak memory 200068 kb
Host smart-8926b23d-1189-4390-a233-57021350b682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827252394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3827252394
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.4139311756
Short name T507
Test name
Test status
Simulation time 256818321 ps
CPU time 1.53 seconds
Started Jul 16 07:24:33 PM PDT 24
Finished Jul 16 07:25:22 PM PDT 24
Peak memory 200288 kb
Host smart-6a08d05d-6ad8-43c3-b0bd-1c5ec5936522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139311756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.4139311756
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1864721906
Short name T536
Test name
Test status
Simulation time 9337305183 ps
CPU time 34.93 seconds
Started Jul 16 07:24:40 PM PDT 24
Finished Jul 16 07:26:07 PM PDT 24
Peak memory 200456 kb
Host smart-3eee6973-2e08-47be-9c1e-642f1e4cc0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864721906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1864721906
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2366201796
Short name T521
Test name
Test status
Simulation time 131036091 ps
CPU time 1.54 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:27 PM PDT 24
Peak memory 208396 kb
Host smart-f25d700e-a967-47e4-9b28-3406bf5e5458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366201796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2366201796
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2177442939
Short name T259
Test name
Test status
Simulation time 100814717 ps
CPU time 0.92 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:30 PM PDT 24
Peak memory 200104 kb
Host smart-15fdf97a-0b50-4237-9007-3bbe4ec2fd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177442939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2177442939
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2273957223
Short name T321
Test name
Test status
Simulation time 69235929 ps
CPU time 0.77 seconds
Started Jul 16 07:24:40 PM PDT 24
Finished Jul 16 07:25:33 PM PDT 24
Peak memory 199964 kb
Host smart-cdd1545b-1bf8-4674-aa2e-c123cb7f26b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273957223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2273957223
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.922222458
Short name T30
Test name
Test status
Simulation time 1227121477 ps
CPU time 5.51 seconds
Started Jul 16 07:24:40 PM PDT 24
Finished Jul 16 07:25:38 PM PDT 24
Peak memory 217784 kb
Host smart-21716d71-5d71-47d3-bdc5-6b4606a4260e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922222458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.922222458
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1003326557
Short name T265
Test name
Test status
Simulation time 243908236 ps
CPU time 1.03 seconds
Started Jul 16 07:24:38 PM PDT 24
Finished Jul 16 07:25:30 PM PDT 24
Peak memory 217548 kb
Host smart-38783aeb-222e-4b59-a24d-0575bff4eee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003326557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1003326557
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2111751169
Short name T164
Test name
Test status
Simulation time 138150346 ps
CPU time 0.76 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:26 PM PDT 24
Peak memory 199952 kb
Host smart-5f315a15-cb39-4c9f-bbb3-7f497f618ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111751169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2111751169
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1025015358
Short name T316
Test name
Test status
Simulation time 747742873 ps
CPU time 3.48 seconds
Started Jul 16 07:24:39 PM PDT 24
Finished Jul 16 07:25:35 PM PDT 24
Peak memory 200448 kb
Host smart-ad175fa4-ee8e-4d71-90b1-41604ee2b982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025015358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1025015358
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2796403323
Short name T398
Test name
Test status
Simulation time 105483467 ps
CPU time 0.96 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:29 PM PDT 24
Peak memory 200140 kb
Host smart-dbf33e57-55aa-456d-ba3b-40c06fdc74c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796403323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2796403323
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3265543102
Short name T118
Test name
Test status
Simulation time 200701842 ps
CPU time 1.36 seconds
Started Jul 16 07:24:39 PM PDT 24
Finished Jul 16 07:25:30 PM PDT 24
Peak memory 200404 kb
Host smart-208d8997-5701-44bd-af7d-781a8b3ebb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265543102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3265543102
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.4192018018
Short name T224
Test name
Test status
Simulation time 5312151822 ps
CPU time 21.99 seconds
Started Jul 16 07:24:39 PM PDT 24
Finished Jul 16 07:25:53 PM PDT 24
Peak memory 210412 kb
Host smart-03a8392d-3611-4ae1-a738-6e17e8fb7d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192018018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.4192018018
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4176760648
Short name T468
Test name
Test status
Simulation time 153415374 ps
CPU time 1.84 seconds
Started Jul 16 07:24:40 PM PDT 24
Finished Jul 16 07:25:35 PM PDT 24
Peak memory 200196 kb
Host smart-26ad898b-936c-4273-b760-2be707746f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176760648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4176760648
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.884373033
Short name T438
Test name
Test status
Simulation time 161576788 ps
CPU time 1.09 seconds
Started Jul 16 07:24:40 PM PDT 24
Finished Jul 16 07:25:34 PM PDT 24
Peak memory 200168 kb
Host smart-57646e4b-065e-4c44-9dbb-ea6253d7d03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884373033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.884373033
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.707685444
Short name T412
Test name
Test status
Simulation time 59784944 ps
CPU time 0.72 seconds
Started Jul 16 07:24:45 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 199960 kb
Host smart-20671cc9-225c-4860-a47a-303028c10775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707685444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.707685444
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1656103242
Short name T399
Test name
Test status
Simulation time 1224497549 ps
CPU time 5.88 seconds
Started Jul 16 07:24:47 PM PDT 24
Finished Jul 16 07:25:47 PM PDT 24
Peak memory 216896 kb
Host smart-155bfb09-055b-4f73-87e1-45520a2aee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656103242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1656103242
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1335755416
Short name T245
Test name
Test status
Simulation time 244038963 ps
CPU time 1.08 seconds
Started Jul 16 07:24:43 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 217496 kb
Host smart-d6d1ecf9-0ad1-487a-a3bd-853361fb6418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335755416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1335755416
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1422756440
Short name T20
Test name
Test status
Simulation time 128815499 ps
CPU time 0.83 seconds
Started Jul 16 07:24:34 PM PDT 24
Finished Jul 16 07:25:21 PM PDT 24
Peak memory 199968 kb
Host smart-82fd86a8-7edd-4f74-a525-905867d6fc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422756440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1422756440
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.4263462419
Short name T501
Test name
Test status
Simulation time 1843548244 ps
CPU time 6.91 seconds
Started Jul 16 07:24:39 PM PDT 24
Finished Jul 16 07:25:38 PM PDT 24
Peak memory 200492 kb
Host smart-ca7694f5-a774-4e74-8d63-234ce6b116ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263462419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.4263462419
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1124326890
Short name T422
Test name
Test status
Simulation time 110197014 ps
CPU time 1 seconds
Started Jul 16 07:24:35 PM PDT 24
Finished Jul 16 07:25:26 PM PDT 24
Peak memory 200252 kb
Host smart-1561f218-2784-49bb-a8ee-c4702f5e44ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124326890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1124326890
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4153136301
Short name T411
Test name
Test status
Simulation time 195658578 ps
CPU time 1.25 seconds
Started Jul 16 07:24:34 PM PDT 24
Finished Jul 16 07:25:24 PM PDT 24
Peak memory 200452 kb
Host smart-245b39c7-e630-4bbc-8df9-51268b9a79f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153136301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4153136301
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2050900913
Short name T380
Test name
Test status
Simulation time 2131415966 ps
CPU time 7.14 seconds
Started Jul 16 07:24:42 PM PDT 24
Finished Jul 16 07:25:45 PM PDT 24
Peak memory 208672 kb
Host smart-be91157a-c948-4771-a180-7f5097676294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050900913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2050900913
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1568784474
Short name T284
Test name
Test status
Simulation time 147070069 ps
CPU time 1.81 seconds
Started Jul 16 07:24:37 PM PDT 24
Finished Jul 16 07:25:30 PM PDT 24
Peak memory 200168 kb
Host smart-11671d92-84a5-4a99-a601-b3a91e0b7941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568784474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1568784474
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3994641836
Short name T517
Test name
Test status
Simulation time 287993862 ps
CPU time 1.57 seconds
Started Jul 16 07:24:35 PM PDT 24
Finished Jul 16 07:25:23 PM PDT 24
Peak memory 200540 kb
Host smart-0681e6ca-e8bd-463e-80fb-dd75a380e34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994641836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3994641836
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1578190111
Short name T12
Test name
Test status
Simulation time 58774633 ps
CPU time 0.83 seconds
Started Jul 16 07:24:43 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 199960 kb
Host smart-98a80f34-89b3-402e-8f26-bb1851b84d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578190111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1578190111
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.713672579
Short name T135
Test name
Test status
Simulation time 1231496928 ps
CPU time 5.27 seconds
Started Jul 16 07:24:45 PM PDT 24
Finished Jul 16 07:25:44 PM PDT 24
Peak memory 221736 kb
Host smart-4aaf571b-cdf3-4773-b1a6-669cbb8068d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713672579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.713672579
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2930290881
Short name T229
Test name
Test status
Simulation time 244946795 ps
CPU time 1.07 seconds
Started Jul 16 07:24:44 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 217540 kb
Host smart-62eb6a7c-4289-41d0-ad9b-0a2b349e2f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930290881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2930290881
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2017398972
Short name T243
Test name
Test status
Simulation time 241199731 ps
CPU time 1.01 seconds
Started Jul 16 07:24:45 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 199980 kb
Host smart-db841f8e-667b-45a8-ba56-fff9d1325e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017398972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2017398972
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1516733329
Short name T393
Test name
Test status
Simulation time 1727955131 ps
CPU time 6.85 seconds
Started Jul 16 07:24:43 PM PDT 24
Finished Jul 16 07:25:45 PM PDT 24
Peak memory 200460 kb
Host smart-306bb157-8b27-4a20-a43f-6981223f412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516733329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1516733329
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1274879196
Short name T378
Test name
Test status
Simulation time 170817155 ps
CPU time 1.16 seconds
Started Jul 16 07:24:43 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200136 kb
Host smart-33ec6f6c-5690-4831-8894-9dda52850f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274879196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1274879196
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3183569977
Short name T366
Test name
Test status
Simulation time 188330685 ps
CPU time 1.3 seconds
Started Jul 16 07:24:44 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200348 kb
Host smart-1b7973b4-7b96-4624-95fc-a615f75f5ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183569977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3183569977
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2984283840
Short name T194
Test name
Test status
Simulation time 4567690461 ps
CPU time 16.5 seconds
Started Jul 16 07:24:47 PM PDT 24
Finished Jul 16 07:25:57 PM PDT 24
Peak memory 208676 kb
Host smart-8dba2b3d-e725-4aaf-a96a-9ae8301d7028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984283840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2984283840
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.499830369
Short name T469
Test name
Test status
Simulation time 121791397 ps
CPU time 1.5 seconds
Started Jul 16 07:24:43 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200180 kb
Host smart-0ac81064-66c0-4f1f-a51d-62ec4ad5044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499830369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.499830369
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4078850599
Short name T506
Test name
Test status
Simulation time 156289328 ps
CPU time 1.19 seconds
Started Jul 16 07:24:43 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200408 kb
Host smart-d93a543d-0673-4aee-8c68-06b7a327dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078850599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4078850599
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1591936396
Short name T493
Test name
Test status
Simulation time 78940304 ps
CPU time 0.78 seconds
Started Jul 16 07:24:45 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 199956 kb
Host smart-78e30f63-9c2c-4cf6-9075-75a7ad7831a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591936396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1591936396
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1937491799
Short name T34
Test name
Test status
Simulation time 2358915349 ps
CPU time 7.9 seconds
Started Jul 16 07:24:42 PM PDT 24
Finished Jul 16 07:25:41 PM PDT 24
Peak memory 217904 kb
Host smart-2e07fd08-be56-44b1-b46a-dabc9c32d5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937491799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1937491799
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1370357313
Short name T463
Test name
Test status
Simulation time 244947434 ps
CPU time 1.13 seconds
Started Jul 16 07:24:43 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 217472 kb
Host smart-1c3e894b-f2f6-4fac-a003-ab240c5a2b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370357313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1370357313
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.455769558
Short name T457
Test name
Test status
Simulation time 102906172 ps
CPU time 0.78 seconds
Started Jul 16 07:24:42 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 199892 kb
Host smart-bfa07d88-f0cc-4fbc-96e2-0a8da6ebe8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455769558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.455769558
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2324258930
Short name T106
Test name
Test status
Simulation time 2005676242 ps
CPU time 6.7 seconds
Started Jul 16 07:24:48 PM PDT 24
Finished Jul 16 07:25:47 PM PDT 24
Peak memory 200424 kb
Host smart-f88bc02c-be4d-4e63-a02c-af6cd96e5cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324258930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2324258930
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3759078709
Short name T153
Test name
Test status
Simulation time 170833281 ps
CPU time 1.19 seconds
Started Jul 16 07:24:44 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200148 kb
Host smart-295822dd-a50d-462b-b449-0951281ecf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759078709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3759078709
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2043867272
Short name T146
Test name
Test status
Simulation time 114329284 ps
CPU time 1.15 seconds
Started Jul 16 07:24:44 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200348 kb
Host smart-14059c83-ad98-4cf7-ba0a-0b881d46d759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043867272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2043867272
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3808288612
Short name T288
Test name
Test status
Simulation time 2238218862 ps
CPU time 8.28 seconds
Started Jul 16 07:24:45 PM PDT 24
Finished Jul 16 07:25:47 PM PDT 24
Peak memory 208728 kb
Host smart-e298100b-86f3-4470-80c9-53b87ba6701e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808288612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3808288612
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.608650216
Short name T395
Test name
Test status
Simulation time 282983391 ps
CPU time 1.83 seconds
Started Jul 16 07:24:43 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200140 kb
Host smart-59965c59-fc5c-43d6-b9a6-b7e5746f8ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608650216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.608650216
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1928696773
Short name T498
Test name
Test status
Simulation time 147696239 ps
CPU time 1.05 seconds
Started Jul 16 07:24:43 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200188 kb
Host smart-00b29a2b-0e82-488d-a8c5-c43786287466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928696773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1928696773
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.957658969
Short name T122
Test name
Test status
Simulation time 64700500 ps
CPU time 0.71 seconds
Started Jul 16 07:24:45 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 200056 kb
Host smart-67e079e2-a63e-4fd0-9e94-26e13e75846d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957658969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.957658969
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1879722392
Short name T28
Test name
Test status
Simulation time 2358920199 ps
CPU time 7.75 seconds
Started Jul 16 07:24:44 PM PDT 24
Finished Jul 16 07:25:46 PM PDT 24
Peak memory 217288 kb
Host smart-93e97672-de4d-4657-a5b8-89855c3bef48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879722392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1879722392
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.507553279
Short name T527
Test name
Test status
Simulation time 244450943 ps
CPU time 1.03 seconds
Started Jul 16 07:24:48 PM PDT 24
Finished Jul 16 07:25:42 PM PDT 24
Peak memory 217504 kb
Host smart-f2f0bc11-9a68-4d2b-b5af-f54c29d0ab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507553279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.507553279
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2334250347
Short name T419
Test name
Test status
Simulation time 140151252 ps
CPU time 0.81 seconds
Started Jul 16 07:24:42 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 199984 kb
Host smart-f8228edf-5163-4d5b-aae7-1f3e6bc8709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334250347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2334250347
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4276021981
Short name T187
Test name
Test status
Simulation time 1534129336 ps
CPU time 6.83 seconds
Started Jul 16 07:24:39 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 200456 kb
Host smart-cddf5c1e-2efa-4a2b-bec9-506d58bbbde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276021981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4276021981
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3224898829
Short name T132
Test name
Test status
Simulation time 169897495 ps
CPU time 1.15 seconds
Started Jul 16 07:24:44 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 200148 kb
Host smart-6ae62647-ba4a-406b-b875-bc7279501a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224898829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3224898829
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1879045608
Short name T50
Test name
Test status
Simulation time 253357132 ps
CPU time 1.42 seconds
Started Jul 16 07:24:48 PM PDT 24
Finished Jul 16 07:25:42 PM PDT 24
Peak memory 200320 kb
Host smart-c1d0a07a-d100-447b-ba8d-6856afde249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879045608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1879045608
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2607346295
Short name T128
Test name
Test status
Simulation time 4009393675 ps
CPU time 16.42 seconds
Started Jul 16 07:24:48 PM PDT 24
Finished Jul 16 07:25:57 PM PDT 24
Peak memory 208676 kb
Host smart-a896e43c-ace6-4f93-b50c-c80c34b87915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607346295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2607346295
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3995555861
Short name T178
Test name
Test status
Simulation time 122790179 ps
CPU time 1.51 seconds
Started Jul 16 07:24:46 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200144 kb
Host smart-32d980f1-0457-4cc2-8c91-b3881735fad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995555861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3995555861
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2831268925
Short name T333
Test name
Test status
Simulation time 111707373 ps
CPU time 0.96 seconds
Started Jul 16 07:24:41 PM PDT 24
Finished Jul 16 07:25:33 PM PDT 24
Peak memory 200152 kb
Host smart-7987ac46-8a6f-450b-b5ed-61fcf201a2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831268925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2831268925
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2616189029
Short name T1
Test name
Test status
Simulation time 68819336 ps
CPU time 0.77 seconds
Started Jul 16 07:24:55 PM PDT 24
Finished Jul 16 07:25:51 PM PDT 24
Peak memory 199940 kb
Host smart-19d13542-dd5a-4820-ad9e-64ff93e38d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616189029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2616189029
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.4064853147
Short name T318
Test name
Test status
Simulation time 2376420368 ps
CPU time 7.57 seconds
Started Jul 16 07:24:54 PM PDT 24
Finished Jul 16 07:25:57 PM PDT 24
Peak memory 217988 kb
Host smart-c30663f7-32a6-41ca-8183-9af2469f665d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064853147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.4064853147
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3622683608
Short name T203
Test name
Test status
Simulation time 244368995 ps
CPU time 1.04 seconds
Started Jul 16 07:24:54 PM PDT 24
Finished Jul 16 07:25:51 PM PDT 24
Peak memory 217524 kb
Host smart-7956b54d-2bdd-4239-820f-c78fb3b10dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622683608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3622683608
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.195973643
Short name T415
Test name
Test status
Simulation time 159702543 ps
CPU time 0.8 seconds
Started Jul 16 07:24:45 PM PDT 24
Finished Jul 16 07:25:39 PM PDT 24
Peak memory 199960 kb
Host smart-87a4b02b-35b9-48b7-bafe-71e9ab8fb815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195973643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.195973643
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2977362256
Short name T324
Test name
Test status
Simulation time 1684545672 ps
CPU time 6.39 seconds
Started Jul 16 07:24:44 PM PDT 24
Finished Jul 16 07:25:45 PM PDT 24
Peak memory 200404 kb
Host smart-ba348ff7-42a3-49da-b6a1-45f72ac51566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977362256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2977362256
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1652351673
Short name T183
Test name
Test status
Simulation time 167033599 ps
CPU time 1.06 seconds
Started Jul 16 07:24:48 PM PDT 24
Finished Jul 16 07:25:42 PM PDT 24
Peak memory 200100 kb
Host smart-d936892f-319c-4561-a092-70ff32a9def0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652351673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1652351673
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1172010878
Short name T376
Test name
Test status
Simulation time 253362659 ps
CPU time 1.52 seconds
Started Jul 16 07:24:45 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200340 kb
Host smart-fade03ee-d174-4db0-9eca-5a6040c42b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172010878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1172010878
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.850620958
Short name T179
Test name
Test status
Simulation time 8305060069 ps
CPU time 28.44 seconds
Started Jul 16 07:24:54 PM PDT 24
Finished Jul 16 07:26:17 PM PDT 24
Peak memory 200420 kb
Host smart-252d382a-5571-4c34-9d1b-4aaf481440be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850620958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.850620958
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2538855292
Short name T363
Test name
Test status
Simulation time 120158750 ps
CPU time 1.53 seconds
Started Jul 16 07:24:46 PM PDT 24
Finished Jul 16 07:25:41 PM PDT 24
Peak memory 208280 kb
Host smart-6d535d08-6c20-4a98-942a-99033a4b1234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538855292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2538855292
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3122040512
Short name T148
Test name
Test status
Simulation time 143368502 ps
CPU time 1.14 seconds
Started Jul 16 07:24:43 PM PDT 24
Finished Jul 16 07:25:40 PM PDT 24
Peak memory 200112 kb
Host smart-f156f47f-5b70-4ff5-9a63-b790abe7d0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122040512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3122040512
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1363182965
Short name T489
Test name
Test status
Simulation time 91699987 ps
CPU time 0.89 seconds
Started Jul 16 07:22:10 PM PDT 24
Finished Jul 16 07:22:19 PM PDT 24
Peak memory 199956 kb
Host smart-fe9d2c50-cb7c-400c-973d-dd8634c19ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363182965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1363182965
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3913425122
Short name T327
Test name
Test status
Simulation time 2369666304 ps
CPU time 8.39 seconds
Started Jul 16 07:22:15 PM PDT 24
Finished Jul 16 07:22:41 PM PDT 24
Peak memory 217764 kb
Host smart-04161b81-6686-4f08-b07a-2f234eabcc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913425122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3913425122
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.4255297870
Short name T313
Test name
Test status
Simulation time 244991845 ps
CPU time 1.06 seconds
Started Jul 16 07:22:10 PM PDT 24
Finished Jul 16 07:22:18 PM PDT 24
Peak memory 217464 kb
Host smart-3714fa4e-a885-44c5-bb3e-49f8fed7013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255297870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.4255297870
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3642742896
Short name T414
Test name
Test status
Simulation time 190080752 ps
CPU time 0.93 seconds
Started Jul 16 07:22:11 PM PDT 24
Finished Jul 16 07:22:20 PM PDT 24
Peak memory 199972 kb
Host smart-869473dd-5c1f-4034-aa1d-eebf22ee715f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642742896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3642742896
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3739841173
Short name T305
Test name
Test status
Simulation time 1552466266 ps
CPU time 5.67 seconds
Started Jul 16 07:22:15 PM PDT 24
Finished Jul 16 07:22:38 PM PDT 24
Peak memory 200368 kb
Host smart-082066f5-96ba-4b41-8d8e-5737a46f5001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739841173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3739841173
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3087086635
Short name T149
Test name
Test status
Simulation time 107161241 ps
CPU time 1 seconds
Started Jul 16 07:22:10 PM PDT 24
Finished Jul 16 07:22:19 PM PDT 24
Peak memory 200092 kb
Host smart-a2c03ccc-de4a-4a9d-bb25-446e8fcbfe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087086635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3087086635
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3199480100
Short name T231
Test name
Test status
Simulation time 201522833 ps
CPU time 1.31 seconds
Started Jul 16 07:22:11 PM PDT 24
Finished Jul 16 07:22:19 PM PDT 24
Peak memory 200292 kb
Host smart-035815fe-6d3e-4a9f-a7ab-11734c6dc1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199480100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3199480100
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.543671371
Short name T23
Test name
Test status
Simulation time 3062050663 ps
CPU time 10.56 seconds
Started Jul 16 07:22:12 PM PDT 24
Finished Jul 16 07:22:32 PM PDT 24
Peak memory 208708 kb
Host smart-ee5b40c8-0453-4f6d-9e28-eddbcee445a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543671371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.543671371
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3220672325
Short name T219
Test name
Test status
Simulation time 461323143 ps
CPU time 2.47 seconds
Started Jul 16 07:22:10 PM PDT 24
Finished Jul 16 07:22:19 PM PDT 24
Peak memory 208356 kb
Host smart-2486d9aa-4fe4-4f5d-903c-1da2a0801aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220672325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3220672325
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1933626330
Short name T459
Test name
Test status
Simulation time 169036531 ps
CPU time 1.25 seconds
Started Jul 16 07:22:15 PM PDT 24
Finished Jul 16 07:22:34 PM PDT 24
Peak memory 200360 kb
Host smart-872adc46-4328-4751-94cf-50f77f570ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933626330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1933626330
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.559945489
Short name T534
Test name
Test status
Simulation time 88949982 ps
CPU time 0.86 seconds
Started Jul 16 07:22:24 PM PDT 24
Finished Jul 16 07:23:00 PM PDT 24
Peak memory 200036 kb
Host smart-ac1c6536-02d0-4053-ac37-887e91738955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559945489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.559945489
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2565512450
Short name T41
Test name
Test status
Simulation time 2178957531 ps
CPU time 7.38 seconds
Started Jul 16 07:22:12 PM PDT 24
Finished Jul 16 07:22:29 PM PDT 24
Peak memory 217776 kb
Host smart-37265a1b-fba4-4e06-996a-3c443a2d0a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565512450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2565512450
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1716724090
Short name T162
Test name
Test status
Simulation time 244947057 ps
CPU time 1.06 seconds
Started Jul 16 07:22:11 PM PDT 24
Finished Jul 16 07:22:20 PM PDT 24
Peak memory 217692 kb
Host smart-6a2f543e-be92-48bf-a230-1867d11d4080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716724090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1716724090
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3790935188
Short name T355
Test name
Test status
Simulation time 156784817 ps
CPU time 0.83 seconds
Started Jul 16 07:22:15 PM PDT 24
Finished Jul 16 07:22:31 PM PDT 24
Peak memory 199972 kb
Host smart-f2a96fbb-6ed2-4d2b-990a-c0f84bd2fe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790935188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3790935188
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.982861861
Short name T433
Test name
Test status
Simulation time 1599671626 ps
CPU time 5.52 seconds
Started Jul 16 07:22:15 PM PDT 24
Finished Jul 16 07:22:36 PM PDT 24
Peak memory 200432 kb
Host smart-9d4b9e24-9a21-416e-9178-fa6e51fbf4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982861861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.982861861
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1285454025
Short name T188
Test name
Test status
Simulation time 176576302 ps
CPU time 1.23 seconds
Started Jul 16 07:22:10 PM PDT 24
Finished Jul 16 07:22:19 PM PDT 24
Peak memory 200172 kb
Host smart-b8d93216-8fef-4673-ae18-96027bd8fa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285454025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1285454025
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.622931570
Short name T258
Test name
Test status
Simulation time 109776811 ps
CPU time 1.14 seconds
Started Jul 16 07:22:12 PM PDT 24
Finished Jul 16 07:22:23 PM PDT 24
Peak memory 200384 kb
Host smart-8b6388c4-dd7e-4170-8c35-3447c804bbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622931570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.622931570
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2874881011
Short name T74
Test name
Test status
Simulation time 8657007757 ps
CPU time 29.52 seconds
Started Jul 16 07:22:15 PM PDT 24
Finished Jul 16 07:23:00 PM PDT 24
Peak memory 200432 kb
Host smart-39e18fb5-916f-44ed-a6ea-8fe86028350b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874881011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2874881011
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1746582004
Short name T163
Test name
Test status
Simulation time 384489658 ps
CPU time 2.54 seconds
Started Jul 16 07:22:12 PM PDT 24
Finished Jul 16 07:22:24 PM PDT 24
Peak memory 200144 kb
Host smart-5086350c-4af8-4354-891e-d99cd810a42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746582004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1746582004
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2289306888
Short name T208
Test name
Test status
Simulation time 151203237 ps
CPU time 1.18 seconds
Started Jul 16 07:22:11 PM PDT 24
Finished Jul 16 07:22:19 PM PDT 24
Peak memory 200144 kb
Host smart-50dd5d45-5bd4-4d5b-8042-c5b3df4f5a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289306888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2289306888
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1606919893
Short name T348
Test name
Test status
Simulation time 70864102 ps
CPU time 0.78 seconds
Started Jul 16 07:22:22 PM PDT 24
Finished Jul 16 07:22:55 PM PDT 24
Peak memory 199948 kb
Host smart-1c14c117-97dc-495e-a143-829467aaa3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606919893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1606919893
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2017318770
Short name T417
Test name
Test status
Simulation time 1887162483 ps
CPU time 7.09 seconds
Started Jul 16 07:22:22 PM PDT 24
Finished Jul 16 07:23:01 PM PDT 24
Peak memory 221676 kb
Host smart-9c904d2e-f241-47a2-be82-a6eabf13369f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017318770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2017318770
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3550993522
Short name T490
Test name
Test status
Simulation time 244406666 ps
CPU time 1.03 seconds
Started Jul 16 07:22:22 PM PDT 24
Finished Jul 16 07:22:55 PM PDT 24
Peak memory 217692 kb
Host smart-78567567-4053-4952-bf5c-997a09590410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550993522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3550993522
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2261644615
Short name T17
Test name
Test status
Simulation time 205783219 ps
CPU time 0.93 seconds
Started Jul 16 07:22:23 PM PDT 24
Finished Jul 16 07:22:59 PM PDT 24
Peak memory 199980 kb
Host smart-d41c901d-5bd8-4efb-bc8d-af8ba2e8d7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261644615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2261644615
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1834480319
Short name T511
Test name
Test status
Simulation time 959505894 ps
CPU time 4.85 seconds
Started Jul 16 07:22:23 PM PDT 24
Finished Jul 16 07:23:04 PM PDT 24
Peak memory 200424 kb
Host smart-925b96c9-dc74-4070-ab3e-5866c758cdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834480319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1834480319
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1433646033
Short name T330
Test name
Test status
Simulation time 171490469 ps
CPU time 1.14 seconds
Started Jul 16 07:22:21 PM PDT 24
Finished Jul 16 07:22:55 PM PDT 24
Peak memory 200120 kb
Host smart-307ee12b-a749-4fa7-9e51-a2d4ff7a9157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433646033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1433646033
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2196174905
Short name T315
Test name
Test status
Simulation time 202189105 ps
CPU time 1.37 seconds
Started Jul 16 07:22:22 PM PDT 24
Finished Jul 16 07:22:55 PM PDT 24
Peak memory 200280 kb
Host smart-6c8a6509-04cf-4d10-be1a-2cde1453bee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196174905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2196174905
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3944798211
Short name T482
Test name
Test status
Simulation time 3263090320 ps
CPU time 15.26 seconds
Started Jul 16 07:22:23 PM PDT 24
Finished Jul 16 07:23:14 PM PDT 24
Peak memory 200416 kb
Host smart-14833062-9a79-46d5-ab64-64caea1085ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944798211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3944798211
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.4013837509
Short name T76
Test name
Test status
Simulation time 137366360 ps
CPU time 1.73 seconds
Started Jul 16 07:22:23 PM PDT 24
Finished Jul 16 07:23:00 PM PDT 24
Peak memory 200192 kb
Host smart-2ec077a1-50f2-4fb3-82da-1e67d36f48d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013837509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.4013837509
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.214640676
Short name T112
Test name
Test status
Simulation time 133236937 ps
CPU time 1.01 seconds
Started Jul 16 07:22:23 PM PDT 24
Finished Jul 16 07:22:59 PM PDT 24
Peak memory 200160 kb
Host smart-f03da4e9-adf7-4427-92aa-8b26982fafe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214640676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.214640676
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1700395385
Short name T461
Test name
Test status
Simulation time 79565224 ps
CPU time 0.8 seconds
Started Jul 16 07:22:22 PM PDT 24
Finished Jul 16 07:22:55 PM PDT 24
Peak memory 199964 kb
Host smart-9d879320-ce6a-4cce-8424-502401f59202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700395385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1700395385
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.533704043
Short name T25
Test name
Test status
Simulation time 2367465377 ps
CPU time 7.94 seconds
Started Jul 16 07:22:23 PM PDT 24
Finished Jul 16 07:23:06 PM PDT 24
Peak memory 217964 kb
Host smart-3da95248-43a7-4812-bdd6-a8c7a5e385e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533704043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.533704043
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3047579968
Short name T405
Test name
Test status
Simulation time 244077018 ps
CPU time 1.12 seconds
Started Jul 16 07:22:24 PM PDT 24
Finished Jul 16 07:23:00 PM PDT 24
Peak memory 217580 kb
Host smart-9d7c3bfc-abd5-4b86-905e-3461e2238b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047579968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3047579968
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1988248424
Short name T141
Test name
Test status
Simulation time 170899691 ps
CPU time 0.82 seconds
Started Jul 16 07:22:22 PM PDT 24
Finished Jul 16 07:22:55 PM PDT 24
Peak memory 199980 kb
Host smart-7c6b8856-728a-48c1-84d3-41d28dc1675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988248424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1988248424
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2514924023
Short name T195
Test name
Test status
Simulation time 998699584 ps
CPU time 4.52 seconds
Started Jul 16 07:22:23 PM PDT 24
Finished Jul 16 07:23:02 PM PDT 24
Peak memory 200296 kb
Host smart-f44695a9-007e-4615-8f79-8200c48ce2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514924023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2514924023
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.867561886
Short name T280
Test name
Test status
Simulation time 162038159 ps
CPU time 1.11 seconds
Started Jul 16 07:22:23 PM PDT 24
Finished Jul 16 07:23:00 PM PDT 24
Peak memory 200156 kb
Host smart-0b46aa25-9131-4b7e-97d9-e3f947a0f3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867561886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.867561886
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.881606920
Short name T43
Test name
Test status
Simulation time 235667405 ps
CPU time 1.56 seconds
Started Jul 16 07:22:24 PM PDT 24
Finished Jul 16 07:23:04 PM PDT 24
Peak memory 200344 kb
Host smart-74b4b862-8f09-4cf1-8ccb-08527242b5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881606920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.881606920
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4180538477
Short name T486
Test name
Test status
Simulation time 4662309949 ps
CPU time 14.84 seconds
Started Jul 16 07:22:24 PM PDT 24
Finished Jul 16 07:23:17 PM PDT 24
Peak memory 200508 kb
Host smart-1f10b8bc-8914-49ec-91f5-7c01eb402050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180538477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4180538477
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1703831803
Short name T248
Test name
Test status
Simulation time 371569365 ps
CPU time 2.16 seconds
Started Jul 16 07:22:23 PM PDT 24
Finished Jul 16 07:23:01 PM PDT 24
Peak memory 208308 kb
Host smart-5f6d10d6-87bb-4de1-bda8-6a8d127941a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703831803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1703831803
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.229175453
Short name T484
Test name
Test status
Simulation time 79979880 ps
CPU time 0.78 seconds
Started Jul 16 07:22:24 PM PDT 24
Finished Jul 16 07:23:03 PM PDT 24
Peak memory 200172 kb
Host smart-a5682406-609f-4683-9295-33f025b7d594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229175453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.229175453
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3267292128
Short name T364
Test name
Test status
Simulation time 54039183 ps
CPU time 0.71 seconds
Started Jul 16 07:22:33 PM PDT 24
Finished Jul 16 07:23:16 PM PDT 24
Peak memory 199936 kb
Host smart-198bfb7d-3fd5-4f1b-96c0-4f1cabacbb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267292128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3267292128
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4038521346
Short name T42
Test name
Test status
Simulation time 1223199360 ps
CPU time 5.31 seconds
Started Jul 16 07:22:35 PM PDT 24
Finished Jul 16 07:23:23 PM PDT 24
Peak memory 221732 kb
Host smart-86df69d4-48b2-42d9-a90c-814ce6b37d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038521346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4038521346
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2970710922
Short name T532
Test name
Test status
Simulation time 244161983 ps
CPU time 1.04 seconds
Started Jul 16 07:22:34 PM PDT 24
Finished Jul 16 07:23:17 PM PDT 24
Peak memory 217516 kb
Host smart-53306f88-9d93-49a2-b138-b3cca7aed0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970710922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2970710922
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1414838589
Short name T22
Test name
Test status
Simulation time 123577320 ps
CPU time 0.79 seconds
Started Jul 16 07:22:24 PM PDT 24
Finished Jul 16 07:23:03 PM PDT 24
Peak memory 199928 kb
Host smart-793aba03-b691-49f3-9a83-6afb4dc255e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414838589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1414838589
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2445068793
Short name T91
Test name
Test status
Simulation time 1055372051 ps
CPU time 5.5 seconds
Started Jul 16 07:22:25 PM PDT 24
Finished Jul 16 07:23:08 PM PDT 24
Peak memory 200436 kb
Host smart-69a0dfbe-e4a2-4d74-95a3-6c13cfde9043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445068793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2445068793
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.624634151
Short name T369
Test name
Test status
Simulation time 114274079 ps
CPU time 1.11 seconds
Started Jul 16 07:22:38 PM PDT 24
Finished Jul 16 07:23:22 PM PDT 24
Peak memory 200156 kb
Host smart-3f2d1504-00b5-41b1-9004-83256d0e2038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624634151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.624634151
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2403366084
Short name T221
Test name
Test status
Simulation time 246581991 ps
CPU time 1.48 seconds
Started Jul 16 07:22:24 PM PDT 24
Finished Jul 16 07:23:00 PM PDT 24
Peak memory 200300 kb
Host smart-99d8f0b3-38c3-4e30-b992-a006fa72e85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403366084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2403366084
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1058123592
Short name T535
Test name
Test status
Simulation time 5480739217 ps
CPU time 17.02 seconds
Started Jul 16 07:22:34 PM PDT 24
Finished Jul 16 07:23:33 PM PDT 24
Peak memory 208684 kb
Host smart-c0c1d573-095c-4563-ae4b-74ec08d0a123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058123592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1058123592
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3978851883
Short name T177
Test name
Test status
Simulation time 113205326 ps
CPU time 1.48 seconds
Started Jul 16 07:22:35 PM PDT 24
Finished Jul 16 07:23:19 PM PDT 24
Peak memory 200188 kb
Host smart-2d9b79b0-827d-43e7-8d93-8c1e9b30f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978851883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3978851883
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1427304806
Short name T365
Test name
Test status
Simulation time 174826388 ps
CPU time 1.33 seconds
Started Jul 16 07:22:24 PM PDT 24
Finished Jul 16 07:23:00 PM PDT 24
Peak memory 200352 kb
Host smart-fbf03ed4-e35a-4a81-9f6f-12d82cec00a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427304806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1427304806
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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