Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8167

1

T1

19

T3

93

T4

17

auto[1]

10951

1

T1

82

T3

98

T4

84

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5913	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6405	1			T1	27		T2	1		T3	62
reset_info_cp[2]	2988	1			T1	17		T3	26		T4	14
reset_info_cp[4]	3854	1			T1	15		T3	48		T4	20
reset_info_cp[8]	107	1			T1	1		T3	1		T20	1
reset_info_cp[16]	118	1			T3	1		T4	2		T6	1
reset_info_cp[32]	123	1			T6	1		T20	1		T57	3
reset_info_cp[64]	118	1			T1	1		T3	1		T8	1
reset_info_cp[128]	112	1			T1	1		T3	1		T4	3

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3092	1			T1	19		T3	31		T4	17
reset_info_cp[1]	auto[1]	2693	1			T1	7		T3	30		T4	9
reset_info_cp[2]	auto[0]	973	1			T3	11		T20	6		T21	6
reset_info_cp[2]	auto[1]	2015	1			T1	17		T3	15		T4	14
reset_info_cp[4]	auto[0]	1380	1			T3	21		T20	4		T21	3
reset_info_cp[4]	auto[1]	2474	1			T1	15		T3	27		T4	20
reset_info_cp[8]	auto[0]	46	1			T20	1		T23	1		T38	1
reset_info_cp[8]	auto[1]	61	1			T1	1		T3	1		T47	1
reset_info_cp[16]	auto[0]	44	1			T101	2		T118	1		T130	2
reset_info_cp[16]	auto[1]	74	1			T3	1		T4	2		T6	1
reset_info_cp[32]	auto[0]	57	1			T20	1		T57	2		T37	1
reset_info_cp[32]	auto[1]	66	1			T6	1		T57	1		T24	1
reset_info_cp[64]	auto[0]	45	1			T21	1		T57	1		T47	1
reset_info_cp[64]	auto[1]	73	1			T1	1		T3	1		T8	1
reset_info_cp[128]	auto[0]	55	1			T3	1		T57	1		T38	2
reset_info_cp[128]	auto[1]	57	1			T1	1		T4	3		T6	1