Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T535 /workspace/coverage/default/47.rstmgr_smoke.1499820197 Jul 17 07:13:12 PM PDT 24 Jul 17 07:13:36 PM PDT 24 249648488 ps
T536 /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2639188586 Jul 17 07:11:35 PM PDT 24 Jul 17 07:11:42 PM PDT 24 121787678 ps
T537 /workspace/coverage/default/18.rstmgr_alert_test.2908856383 Jul 17 07:11:37 PM PDT 24 Jul 17 07:11:49 PM PDT 24 67655475 ps
T538 /workspace/coverage/default/20.rstmgr_stress_all.261616807 Jul 17 07:11:40 PM PDT 24 Jul 17 07:12:00 PM PDT 24 1552419514 ps
T539 /workspace/coverage/default/27.rstmgr_sw_rst.311059175 Jul 17 07:11:42 PM PDT 24 Jul 17 07:11:57 PM PDT 24 159817479 ps
T53 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3785834045 Jul 17 06:02:40 PM PDT 24 Jul 17 06:02:43 PM PDT 24 486778423 ps
T58 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3497937489 Jul 17 06:02:25 PM PDT 24 Jul 17 06:02:29 PM PDT 24 183235290 ps
T54 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2104546613 Jul 17 06:02:57 PM PDT 24 Jul 17 06:02:59 PM PDT 24 206314121 ps
T55 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1596659415 Jul 17 06:04:18 PM PDT 24 Jul 17 06:04:22 PM PDT 24 265290256 ps
T75 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3233850583 Jul 17 06:02:25 PM PDT 24 Jul 17 06:02:27 PM PDT 24 229570047 ps
T59 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1188564265 Jul 17 06:04:01 PM PDT 24 Jul 17 06:04:03 PM PDT 24 149194575 ps
T127 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2147874833 Jul 17 06:02:11 PM PDT 24 Jul 17 06:02:13 PM PDT 24 84277419 ps
T107 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1208009274 Jul 17 06:02:11 PM PDT 24 Jul 17 06:02:13 PM PDT 24 102985230 ps
T88 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4028754271 Jul 17 06:02:27 PM PDT 24 Jul 17 06:02:30 PM PDT 24 117065179 ps
T108 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3055663945 Jul 17 06:02:28 PM PDT 24 Jul 17 06:02:31 PM PDT 24 229326577 ps
T60 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4102350329 Jul 17 06:04:18 PM PDT 24 Jul 17 06:04:21 PM PDT 24 300457498 ps
T80 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3754927907 Jul 17 06:04:12 PM PDT 24 Jul 17 06:04:13 PM PDT 24 94783401 ps
T77 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.734673577 Jul 17 06:04:17 PM PDT 24 Jul 17 06:04:20 PM PDT 24 222703355 ps
T61 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2130271799 Jul 17 06:04:17 PM PDT 24 Jul 17 06:04:21 PM PDT 24 833374909 ps
T109 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1628781965 Jul 17 06:03:52 PM PDT 24 Jul 17 06:03:54 PM PDT 24 68832509 ps
T110 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3120417303 Jul 17 06:04:02 PM PDT 24 Jul 17 06:04:04 PM PDT 24 72648667 ps
T86 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.979566082 Jul 17 06:04:19 PM PDT 24 Jul 17 06:04:21 PM PDT 24 134619151 ps
T111 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3136248179 Jul 17 06:02:24 PM PDT 24 Jul 17 06:02:26 PM PDT 24 117248383 ps
T76 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2804747768 Jul 17 06:02:12 PM PDT 24 Jul 17 06:02:16 PM PDT 24 508527093 ps
T112 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2346460904 Jul 17 06:04:23 PM PDT 24 Jul 17 06:04:24 PM PDT 24 72538425 ps
T113 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1437323947 Jul 17 06:02:31 PM PDT 24 Jul 17 06:02:32 PM PDT 24 54908341 ps
T74 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2131966138 Jul 17 06:02:38 PM PDT 24 Jul 17 06:02:41 PM PDT 24 891952639 ps
T114 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3812589245 Jul 17 06:04:18 PM PDT 24 Jul 17 06:04:20 PM PDT 24 64288173 ps
T79 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.426914772 Jul 17 06:04:17 PM PDT 24 Jul 17 06:04:20 PM PDT 24 239580106 ps
T87 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4272373886 Jul 17 06:04:11 PM PDT 24 Jul 17 06:04:15 PM PDT 24 776336239 ps
T78 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1849627672 Jul 17 06:04:12 PM PDT 24 Jul 17 06:04:14 PM PDT 24 233458929 ps
T540 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3224246777 Jul 17 06:02:16 PM PDT 24 Jul 17 06:02:18 PM PDT 24 432535421 ps
T115 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3360312112 Jul 17 06:02:52 PM PDT 24 Jul 17 06:02:54 PM PDT 24 81616946 ps
T541 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.378311075 Jul 17 06:02:54 PM PDT 24 Jul 17 06:02:56 PM PDT 24 203500579 ps
T542 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3814606914 Jul 17 06:04:12 PM PDT 24 Jul 17 06:04:13 PM PDT 24 72689813 ps
T81 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3259554904 Jul 17 06:04:18 PM PDT 24 Jul 17 06:04:22 PM PDT 24 780282008 ps
T84 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.590511579 Jul 17 06:02:25 PM PDT 24 Jul 17 06:02:29 PM PDT 24 781578417 ps
T543 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4212940461 Jul 17 06:02:15 PM PDT 24 Jul 17 06:02:17 PM PDT 24 136992756 ps
T85 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3601616200 Jul 17 06:03:50 PM PDT 24 Jul 17 06:03:53 PM PDT 24 395583038 ps
T544 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1807582578 Jul 17 06:04:11 PM PDT 24 Jul 17 06:04:13 PM PDT 24 166042041 ps
T545 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.237403136 Jul 17 06:02:17 PM PDT 24 Jul 17 06:02:18 PM PDT 24 103650641 ps
T546 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.158340147 Jul 17 06:02:42 PM PDT 24 Jul 17 06:02:43 PM PDT 24 81404407 ps
T82 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3038352109 Jul 17 06:03:54 PM PDT 24 Jul 17 06:03:58 PM PDT 24 1004157392 ps
T547 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2856774336 Jul 17 06:03:57 PM PDT 24 Jul 17 06:03:59 PM PDT 24 243870955 ps
T548 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1075843873 Jul 17 06:02:55 PM PDT 24 Jul 17 06:02:57 PM PDT 24 82938137 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3391461075 Jul 17 06:04:19 PM PDT 24 Jul 17 06:04:21 PM PDT 24 237023523 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3142877854 Jul 17 06:02:27 PM PDT 24 Jul 17 06:02:31 PM PDT 24 969159874 ps
T551 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1869860688 Jul 17 06:04:12 PM PDT 24 Jul 17 06:04:15 PM PDT 24 143816931 ps
T552 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.301661124 Jul 17 06:03:59 PM PDT 24 Jul 17 06:04:00 PM PDT 24 81118336 ps
T553 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3157054791 Jul 17 06:04:02 PM PDT 24 Jul 17 06:04:05 PM PDT 24 174487837 ps
T554 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1841698695 Jul 17 06:02:32 PM PDT 24 Jul 17 06:02:34 PM PDT 24 141609070 ps
T555 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4246075115 Jul 17 06:04:13 PM PDT 24 Jul 17 06:04:15 PM PDT 24 107662334 ps
T556 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1712476748 Jul 17 06:02:32 PM PDT 24 Jul 17 06:02:34 PM PDT 24 155408975 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3343124472 Jul 17 06:02:26 PM PDT 24 Jul 17 06:02:28 PM PDT 24 56123155 ps
T558 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.263509142 Jul 17 06:02:57 PM PDT 24 Jul 17 06:03:01 PM PDT 24 935413296 ps
T126 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.7756589 Jul 17 06:02:25 PM PDT 24 Jul 17 06:02:28 PM PDT 24 418951022 ps
T559 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1338164463 Jul 17 06:04:13 PM PDT 24 Jul 17 06:04:15 PM PDT 24 78821317 ps
T560 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4172725163 Jul 17 06:02:40 PM PDT 24 Jul 17 06:02:43 PM PDT 24 137366252 ps
T561 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3906516700 Jul 17 06:02:25 PM PDT 24 Jul 17 06:02:28 PM PDT 24 200163075 ps
T562 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3361672596 Jul 17 06:02:59 PM PDT 24 Jul 17 06:03:03 PM PDT 24 882953143 ps
T563 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.240139040 Jul 17 06:02:28 PM PDT 24 Jul 17 06:02:31 PM PDT 24 174111163 ps
T564 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1343952579 Jul 17 06:04:02 PM PDT 24 Jul 17 06:04:04 PM PDT 24 78694994 ps
T565 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3408860740 Jul 17 06:02:29 PM PDT 24 Jul 17 06:02:32 PM PDT 24 127161465 ps
T566 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1872051377 Jul 17 06:02:25 PM PDT 24 Jul 17 06:02:29 PM PDT 24 270945459 ps
T567 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3308233113 Jul 17 06:04:16 PM PDT 24 Jul 17 06:04:18 PM PDT 24 117575368 ps
T568 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.769535669 Jul 17 06:04:18 PM PDT 24 Jul 17 06:04:20 PM PDT 24 98790399 ps
T569 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1471073428 Jul 17 06:04:20 PM PDT 24 Jul 17 06:04:23 PM PDT 24 435751538 ps
T570 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.706703930 Jul 17 06:02:25 PM PDT 24 Jul 17 06:02:27 PM PDT 24 105621962 ps
T571 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3303840524 Jul 17 06:02:36 PM PDT 24 Jul 17 06:02:41 PM PDT 24 592038847 ps
T572 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.719133394 Jul 17 06:02:28 PM PDT 24 Jul 17 06:02:40 PM PDT 24 2281432718 ps
T573 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1828636901 Jul 17 06:03:52 PM PDT 24 Jul 17 06:03:54 PM PDT 24 437960410 ps
T574 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.879798032 Jul 17 06:02:55 PM PDT 24 Jul 17 06:02:57 PM PDT 24 195523247 ps
T575 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3612521087 Jul 17 06:02:15 PM PDT 24 Jul 17 06:02:22 PM PDT 24 480870717 ps
T576 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1746474761 Jul 17 06:02:24 PM PDT 24 Jul 17 06:02:26 PM PDT 24 498275274 ps
T577 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1511210970 Jul 17 06:04:22 PM PDT 24 Jul 17 06:04:24 PM PDT 24 230606208 ps
T578 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3290173791 Jul 17 06:04:16 PM PDT 24 Jul 17 06:04:18 PM PDT 24 190911574 ps
T579 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.728243659 Jul 17 06:02:13 PM PDT 24 Jul 17 06:02:15 PM PDT 24 94162897 ps
T580 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.595684335 Jul 17 06:03:48 PM PDT 24 Jul 17 06:03:50 PM PDT 24 239498786 ps
T581 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4251721834 Jul 17 06:03:48 PM PDT 24 Jul 17 06:03:57 PM PDT 24 1551926346 ps
T582 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2960515405 Jul 17 06:02:25 PM PDT 24 Jul 17 06:02:27 PM PDT 24 250447954 ps
T583 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.334677546 Jul 17 06:02:24 PM PDT 24 Jul 17 06:02:26 PM PDT 24 105289936 ps
T584 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3026968864 Jul 17 06:02:26 PM PDT 24 Jul 17 06:02:28 PM PDT 24 121741415 ps
T585 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.615340322 Jul 17 06:02:28 PM PDT 24 Jul 17 06:02:32 PM PDT 24 158748586 ps
T586 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3361121999 Jul 17 06:04:02 PM PDT 24 Jul 17 06:04:04 PM PDT 24 63898040 ps
T587 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3815914924 Jul 17 06:04:18 PM PDT 24 Jul 17 06:04:20 PM PDT 24 83364435 ps
T588 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1236991193 Jul 17 06:02:24 PM PDT 24 Jul 17 06:02:26 PM PDT 24 64620124 ps
T589 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1684599206 Jul 17 06:02:27 PM PDT 24 Jul 17 06:02:29 PM PDT 24 126531196 ps
T590 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1129350479 Jul 17 06:02:19 PM PDT 24 Jul 17 06:02:22 PM PDT 24 904570746 ps
T591 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4012100906 Jul 17 06:04:19 PM PDT 24 Jul 17 06:04:22 PM PDT 24 166690923 ps
T592 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2918778514 Jul 17 06:04:18 PM PDT 24 Jul 17 06:04:20 PM PDT 24 144911095 ps
T593 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4231850707 Jul 17 06:04:17 PM PDT 24 Jul 17 06:04:22 PM PDT 24 1173755831 ps
T594 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.734250016 Jul 17 06:03:48 PM PDT 24 Jul 17 06:03:50 PM PDT 24 232408681 ps
T83 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3491036083 Jul 17 06:03:59 PM PDT 24 Jul 17 06:04:03 PM PDT 24 772919466 ps
T595 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1058638054 Jul 17 06:02:17 PM PDT 24 Jul 17 06:02:18 PM PDT 24 61870125 ps
T596 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.71976991 Jul 17 06:03:59 PM PDT 24 Jul 17 06:04:02 PM PDT 24 126827918 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3027965501 Jul 17 06:02:24 PM PDT 24 Jul 17 06:02:26 PM PDT 24 93486849 ps
T598 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.807601310 Jul 17 06:04:18 PM PDT 24 Jul 17 06:04:20 PM PDT 24 210114598 ps
T104 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.82667177 Jul 17 06:04:15 PM PDT 24 Jul 17 06:04:17 PM PDT 24 81828636 ps
T599 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.526049224 Jul 17 06:02:27 PM PDT 24 Jul 17 06:02:31 PM PDT 24 494209945 ps
T600 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4046513817 Jul 17 06:04:15 PM PDT 24 Jul 17 06:04:17 PM PDT 24 64612991 ps
T601 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.490346147 Jul 17 06:02:28 PM PDT 24 Jul 17 06:02:31 PM PDT 24 203285222 ps
T602 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1490514616 Jul 17 06:02:25 PM PDT 24 Jul 17 06:02:29 PM PDT 24 479027447 ps
T603 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2457972384 Jul 17 06:02:38 PM PDT 24 Jul 17 06:02:40 PM PDT 24 228981734 ps
T604 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2035531267 Jul 17 06:02:26 PM PDT 24 Jul 17 06:02:28 PM PDT 24 56240599 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1840562975 Jul 17 06:02:11 PM PDT 24 Jul 17 06:02:14 PM PDT 24 449858977 ps
T606 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1681797228 Jul 17 06:04:12 PM PDT 24 Jul 17 06:04:14 PM PDT 24 184690354 ps
T607 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3248188725 Jul 17 06:03:49 PM PDT 24 Jul 17 06:03:53 PM PDT 24 177777287 ps
T608 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.785212503 Jul 17 06:04:17 PM PDT 24 Jul 17 06:04:18 PM PDT 24 100327156 ps
T609 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2451781818 Jul 17 06:02:28 PM PDT 24 Jul 17 06:02:31 PM PDT 24 179956710 ps
T610 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3985366563 Jul 17 06:04:12 PM PDT 24 Jul 17 06:04:14 PM PDT 24 215360193 ps
T611 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1604228124 Jul 17 06:02:26 PM PDT 24 Jul 17 06:02:28 PM PDT 24 75996858 ps
T612 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2246319954 Jul 17 06:02:26 PM PDT 24 Jul 17 06:02:28 PM PDT 24 131239617 ps
T613 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1417165569 Jul 17 06:02:16 PM PDT 24 Jul 17 06:02:19 PM PDT 24 471697216 ps
T614 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3559184825 Jul 17 06:02:26 PM PDT 24 Jul 17 06:02:28 PM PDT 24 62497693 ps
T615 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2100546412 Jul 17 06:04:18 PM PDT 24 Jul 17 06:04:20 PM PDT 24 76530078 ps
T616 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.550611816 Jul 17 06:02:24 PM PDT 24 Jul 17 06:02:28 PM PDT 24 205911297 ps
T617 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4036676389 Jul 17 06:02:27 PM PDT 24 Jul 17 06:02:31 PM PDT 24 790903911 ps
T618 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1048388832 Jul 17 06:02:24 PM PDT 24 Jul 17 06:02:26 PM PDT 24 147454565 ps
T619 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.639492931 Jul 17 06:03:49 PM PDT 24 Jul 17 06:03:52 PM PDT 24 353033841 ps
T620 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3610196130 Jul 17 06:04:12 PM PDT 24 Jul 17 06:04:15 PM PDT 24 178689487 ps

Test location /workspace/coverage/default/1.rstmgr_stress_all.2706531584
Short name T3
Test name
Test status
Simulation time 3200630012 ps
CPU time 14.28 seconds
Started Jul 17 07:10:56 PM PDT 24
Finished Jul 17 07:11:11 PM PDT 24
Peak memory 200424 kb
Host smart-f34a39b3-d8ac-411b-85a7-1255dbc7b713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706531584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2706531584
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3413232414
Short name T56
Test name
Test status
Simulation time 199817265 ps
CPU time 1.36 seconds
Started Jul 17 07:13:09 PM PDT 24
Finished Jul 17 07:13:29 PM PDT 24
Peak memory 200356 kb
Host smart-680300ff-1d16-4d76-85af-177152d696e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413232414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3413232414
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1188564265
Short name T59
Test name
Test status
Simulation time 149194575 ps
CPU time 1.36 seconds
Started Jul 17 06:04:01 PM PDT 24
Finished Jul 17 06:04:03 PM PDT 24
Peak memory 208612 kb
Host smart-9e204d10-b739-4fe2-8ddc-62ce473507b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188564265 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1188564265
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.665420540
Short name T64
Test name
Test status
Simulation time 8351224894 ps
CPU time 13.44 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:24 PM PDT 24
Peak memory 217248 kb
Host smart-afe2f79b-8933-4fba-93e7-5b108d454fce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665420540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.665420540
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3600012061
Short name T50
Test name
Test status
Simulation time 534534092 ps
CPU time 2.73 seconds
Started Jul 17 07:13:06 PM PDT 24
Finished Jul 17 07:13:17 PM PDT 24
Peak memory 200192 kb
Host smart-a83d4549-f1a0-47c8-a5a9-b52ea27ab5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600012061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3600012061
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1266231719
Short name T6
Test name
Test status
Simulation time 1896872379 ps
CPU time 6.8 seconds
Started Jul 17 07:13:14 PM PDT 24
Finished Jul 17 07:13:48 PM PDT 24
Peak memory 217820 kb
Host smart-1e546933-c60e-4cb7-b616-295b7b6254ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266231719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1266231719
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2131966138
Short name T74
Test name
Test status
Simulation time 891952639 ps
CPU time 3.13 seconds
Started Jul 17 06:02:38 PM PDT 24
Finished Jul 17 06:02:41 PM PDT 24
Peak memory 200480 kb
Host smart-a915088c-e0ca-4dcc-82ec-40ba160fbc45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131966138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2131966138
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1970010289
Short name T36
Test name
Test status
Simulation time 85578825 ps
CPU time 0.82 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 199948 kb
Host smart-c0b545a9-e315-46f1-ba45-a3ba6db2e475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970010289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1970010289
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1632208864
Short name T118
Test name
Test status
Simulation time 13255186437 ps
CPU time 39.34 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:46 PM PDT 24
Peak memory 208716 kb
Host smart-59b2dc59-ff4c-4c9b-ba20-a69db6220c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632208864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1632208864
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3497937489
Short name T58
Test name
Test status
Simulation time 183235290 ps
CPU time 2.58 seconds
Started Jul 17 06:02:25 PM PDT 24
Finished Jul 17 06:02:29 PM PDT 24
Peak memory 208620 kb
Host smart-f895f051-dbc4-410d-be83-60a3701973a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497937489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3497937489
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3494214260
Short name T144
Test name
Test status
Simulation time 172789713 ps
CPU time 1.22 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 200128 kb
Host smart-db155a30-0e1a-4e64-9a42-0aa247f1d6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494214260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3494214260
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1050354015
Short name T26
Test name
Test status
Simulation time 1885126808 ps
CPU time 7.05 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:44 PM PDT 24
Peak memory 217816 kb
Host smart-581f3a71-1990-446e-aa5d-5a9e82885d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050354015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1050354015
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2412695947
Short name T57
Test name
Test status
Simulation time 204319688 ps
CPU time 1.36 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 200160 kb
Host smart-416a5bd6-bfaa-4f46-9ad0-1123b7dec90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412695947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2412695947
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3408392659
Short name T4
Test name
Test status
Simulation time 1897081204 ps
CPU time 7.15 seconds
Started Jul 17 07:13:01 PM PDT 24
Finished Jul 17 07:13:09 PM PDT 24
Peak memory 221132 kb
Host smart-bc2c528b-5411-46af-93e0-25ec57109bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408392659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3408392659
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3491036083
Short name T83
Test name
Test status
Simulation time 772919466 ps
CPU time 2.83 seconds
Started Jul 17 06:03:59 PM PDT 24
Finished Jul 17 06:04:03 PM PDT 24
Peak memory 200556 kb
Host smart-a990a4ec-4825-467b-95e3-9cc4b541b602
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491036083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3491036083
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3136248179
Short name T111
Test name
Test status
Simulation time 117248383 ps
CPU time 1.15 seconds
Started Jul 17 06:02:24 PM PDT 24
Finished Jul 17 06:02:26 PM PDT 24
Peak memory 200368 kb
Host smart-9c9a9d16-7dc0-4243-b62e-03f3264b3edf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136248179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3136248179
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3143829428
Short name T15
Test name
Test status
Simulation time 125858862 ps
CPU time 0.77 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:38 PM PDT 24
Peak memory 200044 kb
Host smart-ae6e7c96-fbe3-46fb-b94f-4d01c07595d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143829428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3143829428
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3381442791
Short name T143
Test name
Test status
Simulation time 244613556 ps
CPU time 1.03 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:41 PM PDT 24
Peak memory 217512 kb
Host smart-ba1e3206-cfd7-4715-b1a0-ec51126d372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381442791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3381442791
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3785834045
Short name T53
Test name
Test status
Simulation time 486778423 ps
CPU time 2.01 seconds
Started Jul 17 06:02:40 PM PDT 24
Finished Jul 17 06:02:43 PM PDT 24
Peak memory 200536 kb
Host smart-e85a6e0c-a2ca-43c0-be93-6d38ce9f3f5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785834045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3785834045
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1369040675
Short name T201
Test name
Test status
Simulation time 113658647 ps
CPU time 1.43 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 200212 kb
Host smart-a76202a3-4a5e-4538-a418-eadf48be8913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369040675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1369040675
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.639492931
Short name T619
Test name
Test status
Simulation time 353033841 ps
CPU time 2.43 seconds
Started Jul 17 06:03:49 PM PDT 24
Finished Jul 17 06:03:52 PM PDT 24
Peak memory 200468 kb
Host smart-d3c53563-3eae-4a4d-a363-56f516aec404
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639492931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.639492931
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4251721834
Short name T581
Test name
Test status
Simulation time 1551926346 ps
CPU time 8.56 seconds
Started Jul 17 06:03:48 PM PDT 24
Finished Jul 17 06:03:57 PM PDT 24
Peak memory 200380 kb
Host smart-1690e941-c9ce-47ae-b938-823071875d10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251721834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.4
251721834
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.237403136
Short name T545
Test name
Test status
Simulation time 103650641 ps
CPU time 0.82 seconds
Started Jul 17 06:02:17 PM PDT 24
Finished Jul 17 06:02:18 PM PDT 24
Peak memory 200164 kb
Host smart-de143852-f25c-464d-8cd1-0e7ab1aecfc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237403136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.237403136
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.979566082
Short name T86
Test name
Test status
Simulation time 134619151 ps
CPU time 1.05 seconds
Started Jul 17 06:04:19 PM PDT 24
Finished Jul 17 06:04:21 PM PDT 24
Peak memory 208552 kb
Host smart-662d22ee-2c99-45f4-94a1-9f212454f904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979566082 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.979566082
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1058638054
Short name T595
Test name
Test status
Simulation time 61870125 ps
CPU time 0.73 seconds
Started Jul 17 06:02:17 PM PDT 24
Finished Jul 17 06:02:18 PM PDT 24
Peak memory 200148 kb
Host smart-b2e50e31-c83d-4d77-9d35-7b51213fbdf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058638054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1058638054
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.734250016
Short name T594
Test name
Test status
Simulation time 232408681 ps
CPU time 1.51 seconds
Started Jul 17 06:03:48 PM PDT 24
Finished Jul 17 06:03:50 PM PDT 24
Peak memory 200460 kb
Host smart-598f757f-b2ea-4989-ac0d-bb5796018264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734250016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.734250016
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2804747768
Short name T76
Test name
Test status
Simulation time 508527093 ps
CPU time 3.19 seconds
Started Jul 17 06:02:12 PM PDT 24
Finished Jul 17 06:02:16 PM PDT 24
Peak memory 208560 kb
Host smart-f7428103-5682-454d-bd16-8620f4f6dad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804747768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2804747768
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1129350479
Short name T590
Test name
Test status
Simulation time 904570746 ps
CPU time 2.95 seconds
Started Jul 17 06:02:19 PM PDT 24
Finished Jul 17 06:02:22 PM PDT 24
Peak memory 200480 kb
Host smart-69a2a484-57f2-4fca-ab7d-ffdbc92b0ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129350479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1129350479
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3391461075
Short name T549
Test name
Test status
Simulation time 237023523 ps
CPU time 1.68 seconds
Started Jul 17 06:04:19 PM PDT 24
Finished Jul 17 06:04:21 PM PDT 24
Peak memory 200440 kb
Host smart-e377c8c0-54aa-4a6f-b4a5-61d1c52f7867
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391461075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
391461075
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1596659415
Short name T55
Test name
Test status
Simulation time 265290256 ps
CPU time 3.14 seconds
Started Jul 17 06:04:18 PM PDT 24
Finished Jul 17 06:04:22 PM PDT 24
Peak memory 200432 kb
Host smart-1337a727-3369-4cb0-9344-8ed5acac99e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596659415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
596659415
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2918778514
Short name T592
Test name
Test status
Simulation time 144911095 ps
CPU time 0.95 seconds
Started Jul 17 06:04:18 PM PDT 24
Finished Jul 17 06:04:20 PM PDT 24
Peak memory 200304 kb
Host smart-9575a0e4-dc72-4061-861b-fff293418397
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918778514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
918778514
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.807601310
Short name T598
Test name
Test status
Simulation time 210114598 ps
CPU time 1.3 seconds
Started Jul 17 06:04:18 PM PDT 24
Finished Jul 17 06:04:20 PM PDT 24
Peak memory 208616 kb
Host smart-0757a8de-c707-4288-b914-28696375bf52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807601310 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.807601310
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.728243659
Short name T579
Test name
Test status
Simulation time 94162897 ps
CPU time 0.91 seconds
Started Jul 17 06:02:13 PM PDT 24
Finished Jul 17 06:02:15 PM PDT 24
Peak memory 200292 kb
Host smart-d2ce4a36-7d68-417d-bfc2-66aaab32109c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728243659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.728243659
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.595684335
Short name T580
Test name
Test status
Simulation time 239498786 ps
CPU time 1.62 seconds
Started Jul 17 06:03:48 PM PDT 24
Finished Jul 17 06:03:50 PM PDT 24
Peak memory 200460 kb
Host smart-3e6a750f-cc42-48a5-986d-e8592657efa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595684335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.595684335
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3601616200
Short name T85
Test name
Test status
Simulation time 395583038 ps
CPU time 2.76 seconds
Started Jul 17 06:03:50 PM PDT 24
Finished Jul 17 06:03:53 PM PDT 24
Peak memory 211356 kb
Host smart-1964d3f0-f51c-46ff-8dfa-fcd6e3e688c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601616200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3601616200
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1840562975
Short name T605
Test name
Test status
Simulation time 449858977 ps
CPU time 1.73 seconds
Started Jul 17 06:02:11 PM PDT 24
Finished Jul 17 06:02:14 PM PDT 24
Peak memory 200448 kb
Host smart-8c8ef679-9971-4308-90e1-2608e9e348c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840562975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1840562975
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1712476748
Short name T556
Test name
Test status
Simulation time 155408975 ps
CPU time 1.44 seconds
Started Jul 17 06:02:32 PM PDT 24
Finished Jul 17 06:02:34 PM PDT 24
Peak memory 208764 kb
Host smart-5b1dc301-93bb-4131-becf-1e78950c5f2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712476748 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1712476748
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3814606914
Short name T542
Test name
Test status
Simulation time 72689813 ps
CPU time 0.78 seconds
Started Jul 17 06:04:12 PM PDT 24
Finished Jul 17 06:04:13 PM PDT 24
Peak memory 200276 kb
Host smart-eb0eae4d-b08d-48d9-80fb-d866e86f9b48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814606914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3814606914
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1048388832
Short name T618
Test name
Test status
Simulation time 147454565 ps
CPU time 2.04 seconds
Started Jul 17 06:02:24 PM PDT 24
Finished Jul 17 06:02:26 PM PDT 24
Peak memory 208612 kb
Host smart-4ec8a633-d421-45eb-849a-4b2a38d561f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048388832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1048388832
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1746474761
Short name T576
Test name
Test status
Simulation time 498275274 ps
CPU time 2.15 seconds
Started Jul 17 06:02:24 PM PDT 24
Finished Jul 17 06:02:26 PM PDT 24
Peak memory 200476 kb
Host smart-911656a2-ffed-4b6a-a7da-805330240b1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746474761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1746474761
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.240139040
Short name T563
Test name
Test status
Simulation time 174111163 ps
CPU time 1.18 seconds
Started Jul 17 06:02:28 PM PDT 24
Finished Jul 17 06:02:31 PM PDT 24
Peak memory 208540 kb
Host smart-1874084c-8335-43a9-8b43-3833ef58c929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240139040 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.240139040
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2035531267
Short name T604
Test name
Test status
Simulation time 56240599 ps
CPU time 0.75 seconds
Started Jul 17 06:02:26 PM PDT 24
Finished Jul 17 06:02:28 PM PDT 24
Peak memory 200232 kb
Host smart-c31c2845-3cf6-4d16-9e8c-729e4c2934b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035531267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2035531267
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1841698695
Short name T554
Test name
Test status
Simulation time 141609070 ps
CPU time 1.43 seconds
Started Jul 17 06:02:32 PM PDT 24
Finished Jul 17 06:02:34 PM PDT 24
Peak memory 200492 kb
Host smart-5bb22d61-3806-483c-9850-bd031657f271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841698695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1841698695
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3408860740
Short name T565
Test name
Test status
Simulation time 127161465 ps
CPU time 1.68 seconds
Started Jul 17 06:02:29 PM PDT 24
Finished Jul 17 06:02:32 PM PDT 24
Peak memory 211012 kb
Host smart-a08c51ad-a1d1-443f-9196-7062e56ca7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408860740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3408860740
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1828636901
Short name T573
Test name
Test status
Simulation time 437960410 ps
CPU time 1.75 seconds
Started Jul 17 06:03:52 PM PDT 24
Finished Jul 17 06:03:54 PM PDT 24
Peak memory 200492 kb
Host smart-0a94f467-655d-4c23-ab2c-7dd3ff35a3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828636901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1828636901
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1681797228
Short name T606
Test name
Test status
Simulation time 184690354 ps
CPU time 1.24 seconds
Started Jul 17 06:04:12 PM PDT 24
Finished Jul 17 06:04:14 PM PDT 24
Peak memory 209008 kb
Host smart-4e081179-4e07-4ea3-aa93-13b2282b623e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681797228 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1681797228
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1628781965
Short name T109
Test name
Test status
Simulation time 68832509 ps
CPU time 0.89 seconds
Started Jul 17 06:03:52 PM PDT 24
Finished Jul 17 06:03:54 PM PDT 24
Peak memory 200292 kb
Host smart-60ca50cf-19d0-4f5c-9aeb-f05c7d51b789
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628781965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1628781965
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4172725163
Short name T560
Test name
Test status
Simulation time 137366252 ps
CPU time 1.41 seconds
Started Jul 17 06:02:40 PM PDT 24
Finished Jul 17 06:02:43 PM PDT 24
Peak memory 200460 kb
Host smart-098e7462-b624-427b-ba74-a23191563154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172725163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4172725163
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4012100906
Short name T591
Test name
Test status
Simulation time 166690923 ps
CPU time 2.36 seconds
Started Jul 17 06:04:19 PM PDT 24
Finished Jul 17 06:04:22 PM PDT 24
Peak memory 216748 kb
Host smart-adc83e5c-1a51-4d94-82cd-2387ba4dfec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012100906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.4012100906
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4036676389
Short name T617
Test name
Test status
Simulation time 790903911 ps
CPU time 3.05 seconds
Started Jul 17 06:02:27 PM PDT 24
Finished Jul 17 06:02:31 PM PDT 24
Peak memory 200504 kb
Host smart-192d906a-779e-49bb-b288-722da828d95a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036676389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.4036676389
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3754927907
Short name T80
Test name
Test status
Simulation time 94783401 ps
CPU time 1 seconds
Started Jul 17 06:04:12 PM PDT 24
Finished Jul 17 06:04:13 PM PDT 24
Peak memory 200416 kb
Host smart-6be3441f-9a85-4db6-b7d2-8d5009897321
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754927907 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3754927907
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3812589245
Short name T114
Test name
Test status
Simulation time 64288173 ps
CPU time 0.76 seconds
Started Jul 17 06:04:18 PM PDT 24
Finished Jul 17 06:04:20 PM PDT 24
Peak memory 200128 kb
Host smart-ab354b35-78e7-4da4-8372-81aae43b3f74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812589245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3812589245
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.158340147
Short name T546
Test name
Test status
Simulation time 81404407 ps
CPU time 1.03 seconds
Started Jul 17 06:02:42 PM PDT 24
Finished Jul 17 06:02:43 PM PDT 24
Peak memory 200260 kb
Host smart-5c207e7b-fe8b-4831-ae61-582081ef19fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158340147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.158340147
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3303840524
Short name T571
Test name
Test status
Simulation time 592038847 ps
CPU time 3.82 seconds
Started Jul 17 06:02:36 PM PDT 24
Finished Jul 17 06:02:41 PM PDT 24
Peak memory 212244 kb
Host smart-ee28f75d-05fc-472c-a34f-ef52130f6809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303840524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3303840524
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3290173791
Short name T578
Test name
Test status
Simulation time 190911574 ps
CPU time 1.75 seconds
Started Jul 17 06:04:16 PM PDT 24
Finished Jul 17 06:04:18 PM PDT 24
Peak memory 208904 kb
Host smart-ac0d810a-1513-461a-9ebc-8f0647da5255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290173791 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3290173791
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.82667177
Short name T104
Test name
Test status
Simulation time 81828636 ps
CPU time 0.85 seconds
Started Jul 17 06:04:15 PM PDT 24
Finished Jul 17 06:04:17 PM PDT 24
Peak memory 200228 kb
Host smart-1570f919-125e-4fa0-a530-9bc3028dd577
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82667177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.82667177
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2346460904
Short name T112
Test name
Test status
Simulation time 72538425 ps
CPU time 0.98 seconds
Started Jul 17 06:04:23 PM PDT 24
Finished Jul 17 06:04:24 PM PDT 24
Peak memory 200348 kb
Host smart-052eeab4-9e8a-4a04-9e94-27a7dc903b99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346460904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2346460904
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2856774336
Short name T547
Test name
Test status
Simulation time 243870955 ps
CPU time 2 seconds
Started Jul 17 06:03:57 PM PDT 24
Finished Jul 17 06:03:59 PM PDT 24
Peak memory 208592 kb
Host smart-2e22f2f1-0063-41ad-b111-d003d8b53064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856774336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2856774336
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1807582578
Short name T544
Test name
Test status
Simulation time 166042041 ps
CPU time 1.45 seconds
Started Jul 17 06:04:11 PM PDT 24
Finished Jul 17 06:04:13 PM PDT 24
Peak memory 209108 kb
Host smart-f737282c-33e0-4786-a615-6ca69423196b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807582578 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1807582578
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4046513817
Short name T600
Test name
Test status
Simulation time 64612991 ps
CPU time 0.75 seconds
Started Jul 17 06:04:15 PM PDT 24
Finished Jul 17 06:04:17 PM PDT 24
Peak memory 200228 kb
Host smart-14940084-2a9d-48c4-8cb1-02b562fecfc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046513817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.4046513817
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4246075115
Short name T555
Test name
Test status
Simulation time 107662334 ps
CPU time 1.22 seconds
Started Jul 17 06:04:13 PM PDT 24
Finished Jul 17 06:04:15 PM PDT 24
Peak memory 200372 kb
Host smart-178197f3-160e-4c49-b374-e8d6bfa8b644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246075115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.4246075115
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.71976991
Short name T596
Test name
Test status
Simulation time 126827918 ps
CPU time 1.84 seconds
Started Jul 17 06:03:59 PM PDT 24
Finished Jul 17 06:04:02 PM PDT 24
Peak memory 210956 kb
Host smart-ddafb250-8631-4785-b591-2e62d7cb7f83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71976991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.71976991
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4272373886
Short name T87
Test name
Test status
Simulation time 776336239 ps
CPU time 2.82 seconds
Started Jul 17 06:04:11 PM PDT 24
Finished Jul 17 06:04:15 PM PDT 24
Peak memory 200488 kb
Host smart-0dd87be6-a9f8-4314-ab41-0413d28d29cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272373886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.4272373886
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2104546613
Short name T54
Test name
Test status
Simulation time 206314121 ps
CPU time 1.25 seconds
Started Jul 17 06:02:57 PM PDT 24
Finished Jul 17 06:02:59 PM PDT 24
Peak memory 208552 kb
Host smart-49da89f4-65d3-4745-873f-467ae4e06351
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104546613 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2104546613
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.301661124
Short name T552
Test name
Test status
Simulation time 81118336 ps
CPU time 0.91 seconds
Started Jul 17 06:03:59 PM PDT 24
Finished Jul 17 06:04:00 PM PDT 24
Peak memory 200264 kb
Host smart-22de1fde-bfda-4199-9326-c3c48253073b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301661124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.301661124
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3308233113
Short name T567
Test name
Test status
Simulation time 117575368 ps
CPU time 1.13 seconds
Started Jul 17 06:04:16 PM PDT 24
Finished Jul 17 06:04:18 PM PDT 24
Peak memory 200540 kb
Host smart-7b533631-0ead-4bcf-b4f5-56785127d0cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308233113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3308233113
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2457972384
Short name T603
Test name
Test status
Simulation time 228981734 ps
CPU time 1.72 seconds
Started Jul 17 06:02:38 PM PDT 24
Finished Jul 17 06:02:40 PM PDT 24
Peak memory 208512 kb
Host smart-8fa87549-0b73-47fe-9574-a1c22d1fd4b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457972384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2457972384
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.785212503
Short name T608
Test name
Test status
Simulation time 100327156 ps
CPU time 0.88 seconds
Started Jul 17 06:04:17 PM PDT 24
Finished Jul 17 06:04:18 PM PDT 24
Peak memory 200352 kb
Host smart-734fdc75-f4f6-4ea9-8535-7d5698eeb7cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785212503 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.785212503
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3360312112
Short name T115
Test name
Test status
Simulation time 81616946 ps
CPU time 0.8 seconds
Started Jul 17 06:02:52 PM PDT 24
Finished Jul 17 06:02:54 PM PDT 24
Peak memory 200276 kb
Host smart-bb9eabd6-46fb-4398-a937-81d2bb220ff9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360312112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3360312112
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1511210970
Short name T577
Test name
Test status
Simulation time 230606208 ps
CPU time 1.62 seconds
Started Jul 17 06:04:22 PM PDT 24
Finished Jul 17 06:04:24 PM PDT 24
Peak memory 200480 kb
Host smart-e0cf8602-bef0-4757-8ae7-775bf13fcd02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511210970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1511210970
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3610196130
Short name T620
Test name
Test status
Simulation time 178689487 ps
CPU time 2.63 seconds
Started Jul 17 06:04:12 PM PDT 24
Finished Jul 17 06:04:15 PM PDT 24
Peak memory 208600 kb
Host smart-6b379dd9-eebc-4bbd-86e9-c12edc409b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610196130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3610196130
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.263509142
Short name T558
Test name
Test status
Simulation time 935413296 ps
CPU time 3.22 seconds
Started Jul 17 06:02:57 PM PDT 24
Finished Jul 17 06:03:01 PM PDT 24
Peak memory 200436 kb
Host smart-cd6d717f-5aa0-43dc-b0cf-9ad1e8aa6cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263509142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.263509142
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.769535669
Short name T568
Test name
Test status
Simulation time 98790399 ps
CPU time 1.02 seconds
Started Jul 17 06:04:18 PM PDT 24
Finished Jul 17 06:04:20 PM PDT 24
Peak memory 210296 kb
Host smart-2f399ea4-6c5a-418f-8a49-091d58cd4518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769535669 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.769535669
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3815914924
Short name T587
Test name
Test status
Simulation time 83364435 ps
CPU time 0.84 seconds
Started Jul 17 06:04:18 PM PDT 24
Finished Jul 17 06:04:20 PM PDT 24
Peak memory 199956 kb
Host smart-b3362a1d-3d8a-45ab-96ad-a4fb49b5fb5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815914924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3815914924
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.378311075
Short name T541
Test name
Test status
Simulation time 203500579 ps
CPU time 1.59 seconds
Started Jul 17 06:02:54 PM PDT 24
Finished Jul 17 06:02:56 PM PDT 24
Peak memory 200420 kb
Host smart-c0003770-a0b6-4700-bb09-2a6c5358101e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378311075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.378311075
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.734673577
Short name T77
Test name
Test status
Simulation time 222703355 ps
CPU time 1.7 seconds
Started Jul 17 06:04:17 PM PDT 24
Finished Jul 17 06:04:20 PM PDT 24
Peak memory 200336 kb
Host smart-f2dccddb-3fdb-4d80-9db2-d79eeeac1a75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734673577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.734673577
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3361672596
Short name T562
Test name
Test status
Simulation time 882953143 ps
CPU time 3.28 seconds
Started Jul 17 06:02:59 PM PDT 24
Finished Jul 17 06:03:03 PM PDT 24
Peak memory 200508 kb
Host smart-aa9d12d3-e074-4c64-a5ae-2990e00f5fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361672596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3361672596
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.879798032
Short name T574
Test name
Test status
Simulation time 195523247 ps
CPU time 1.36 seconds
Started Jul 17 06:02:55 PM PDT 24
Finished Jul 17 06:02:57 PM PDT 24
Peak memory 208784 kb
Host smart-d949d990-efac-49d7-9377-e365648ec962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879798032 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.879798032
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1075843873
Short name T548
Test name
Test status
Simulation time 82938137 ps
CPU time 0.95 seconds
Started Jul 17 06:02:55 PM PDT 24
Finished Jul 17 06:02:57 PM PDT 24
Peak memory 200212 kb
Host smart-a426e77b-4eaf-47e2-a4a8-02562b53360d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075843873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1075843873
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2100546412
Short name T615
Test name
Test status
Simulation time 76530078 ps
CPU time 0.97 seconds
Started Jul 17 06:04:18 PM PDT 24
Finished Jul 17 06:04:20 PM PDT 24
Peak memory 200352 kb
Host smart-8862e9ee-8ce7-49b4-bed3-b100897b626d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100546412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2100546412
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1869860688
Short name T551
Test name
Test status
Simulation time 143816931 ps
CPU time 2.22 seconds
Started Jul 17 06:04:12 PM PDT 24
Finished Jul 17 06:04:15 PM PDT 24
Peak memory 208612 kb
Host smart-7010fd1a-2f95-421c-989d-55a626721a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869860688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1869860688
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3259554904
Short name T81
Test name
Test status
Simulation time 780282008 ps
CPU time 3.07 seconds
Started Jul 17 06:04:18 PM PDT 24
Finished Jul 17 06:04:22 PM PDT 24
Peak memory 200548 kb
Host smart-53827f48-e253-4126-a57f-2fa2408c656d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259554904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3259554904
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1417165569
Short name T613
Test name
Test status
Simulation time 471697216 ps
CPU time 2.6 seconds
Started Jul 17 06:02:16 PM PDT 24
Finished Jul 17 06:02:19 PM PDT 24
Peak memory 200456 kb
Host smart-903263c2-b6d2-41e7-8c15-6f59b1fcc428
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417165569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
417165569
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3612521087
Short name T575
Test name
Test status
Simulation time 480870717 ps
CPU time 5.69 seconds
Started Jul 17 06:02:15 PM PDT 24
Finished Jul 17 06:02:22 PM PDT 24
Peak memory 200392 kb
Host smart-4436fdb2-9b72-46b1-ac47-cd55f9351e93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612521087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
612521087
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4212940461
Short name T543
Test name
Test status
Simulation time 136992756 ps
CPU time 0.97 seconds
Started Jul 17 06:02:15 PM PDT 24
Finished Jul 17 06:02:17 PM PDT 24
Peak memory 200264 kb
Host smart-f1e37a99-b8ae-4c8b-80ad-c8913ef91af2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212940461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4
212940461
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2451781818
Short name T609
Test name
Test status
Simulation time 179956710 ps
CPU time 1.26 seconds
Started Jul 17 06:02:28 PM PDT 24
Finished Jul 17 06:02:31 PM PDT 24
Peak memory 200336 kb
Host smart-5561f7d7-bb18-431c-9494-f7d6166e9f0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451781818 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2451781818
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2147874833
Short name T127
Test name
Test status
Simulation time 84277419 ps
CPU time 0.96 seconds
Started Jul 17 06:02:11 PM PDT 24
Finished Jul 17 06:02:13 PM PDT 24
Peak memory 200268 kb
Host smart-4be27024-f2de-46e7-9c39-bcde4083b58f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147874833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2147874833
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1208009274
Short name T107
Test name
Test status
Simulation time 102985230 ps
CPU time 1.34 seconds
Started Jul 17 06:02:11 PM PDT 24
Finished Jul 17 06:02:13 PM PDT 24
Peak memory 200536 kb
Host smart-dd00835e-9e73-442e-9ce3-04d7b2f7c918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208009274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1208009274
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3248188725
Short name T607
Test name
Test status
Simulation time 177777287 ps
CPU time 2.6 seconds
Started Jul 17 06:03:49 PM PDT 24
Finished Jul 17 06:03:53 PM PDT 24
Peak memory 208584 kb
Host smart-8e187bee-743f-4a0a-b017-104b95e3a99f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248188725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3248188725
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3224246777
Short name T540
Test name
Test status
Simulation time 432535421 ps
CPU time 1.76 seconds
Started Jul 17 06:02:16 PM PDT 24
Finished Jul 17 06:02:18 PM PDT 24
Peak memory 200480 kb
Host smart-849e0b00-f160-41ac-acd3-56708f2ca849
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224246777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3224246777
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.615340322
Short name T585
Test name
Test status
Simulation time 158748586 ps
CPU time 1.99 seconds
Started Jul 17 06:02:28 PM PDT 24
Finished Jul 17 06:02:32 PM PDT 24
Peak memory 200376 kb
Host smart-b124a37c-d3ae-47e4-8284-001000ddbb68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615340322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.615340322
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4231850707
Short name T593
Test name
Test status
Simulation time 1173755831 ps
CPU time 5.28 seconds
Started Jul 17 06:04:17 PM PDT 24
Finished Jul 17 06:04:22 PM PDT 24
Peak memory 200580 kb
Host smart-77f05237-f5f0-495a-8cd4-cca4a7cfe781
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231850707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.4
231850707
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.334677546
Short name T583
Test name
Test status
Simulation time 105289936 ps
CPU time 0.81 seconds
Started Jul 17 06:02:24 PM PDT 24
Finished Jul 17 06:02:26 PM PDT 24
Peak memory 200136 kb
Host smart-d927b074-66e0-48f9-b408-38116aafbba0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334677546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.334677546
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3026968864
Short name T584
Test name
Test status
Simulation time 121741415 ps
CPU time 1 seconds
Started Jul 17 06:02:26 PM PDT 24
Finished Jul 17 06:02:28 PM PDT 24
Peak memory 200408 kb
Host smart-7d48680d-0183-4627-8184-ba6fce488ead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026968864 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3026968864
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3343124472
Short name T557
Test name
Test status
Simulation time 56123155 ps
CPU time 0.83 seconds
Started Jul 17 06:02:26 PM PDT 24
Finished Jul 17 06:02:28 PM PDT 24
Peak memory 200272 kb
Host smart-bc5f44a7-e840-4474-adb4-2ea7ea4f74bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343124472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3343124472
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3233850583
Short name T75
Test name
Test status
Simulation time 229570047 ps
CPU time 1.5 seconds
Started Jul 17 06:02:25 PM PDT 24
Finished Jul 17 06:02:27 PM PDT 24
Peak memory 200472 kb
Host smart-39da8ae7-8964-4837-817c-4c2971ecec07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233850583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3233850583
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.7756589
Short name T126
Test name
Test status
Simulation time 418951022 ps
CPU time 1.88 seconds
Started Jul 17 06:02:25 PM PDT 24
Finished Jul 17 06:02:28 PM PDT 24
Peak memory 200404 kb
Host smart-f98ba037-a6e4-48c7-8843-3b9c176cf1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7756589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.7756589
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3906516700
Short name T561
Test name
Test status
Simulation time 200163075 ps
CPU time 1.55 seconds
Started Jul 17 06:02:25 PM PDT 24
Finished Jul 17 06:02:28 PM PDT 24
Peak memory 200456 kb
Host smart-0c5a478d-3937-4645-a7bf-014df667d8da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906516700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
906516700
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.719133394
Short name T572
Test name
Test status
Simulation time 2281432718 ps
CPU time 10.46 seconds
Started Jul 17 06:02:28 PM PDT 24
Finished Jul 17 06:02:40 PM PDT 24
Peak memory 200496 kb
Host smart-3075b754-e75a-4efc-a410-b492119ba710
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719133394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.719133394
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3027965501
Short name T597
Test name
Test status
Simulation time 93486849 ps
CPU time 0.84 seconds
Started Jul 17 06:02:24 PM PDT 24
Finished Jul 17 06:02:26 PM PDT 24
Peak memory 200212 kb
Host smart-2beb7576-492b-4a43-8696-afe95bcf9405
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027965501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
027965501
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1684599206
Short name T589
Test name
Test status
Simulation time 126531196 ps
CPU time 1.07 seconds
Started Jul 17 06:02:27 PM PDT 24
Finished Jul 17 06:02:29 PM PDT 24
Peak memory 200356 kb
Host smart-e6578657-dde7-42cd-b781-ccdff54a2d25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684599206 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1684599206
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1236991193
Short name T588
Test name
Test status
Simulation time 64620124 ps
CPU time 0.83 seconds
Started Jul 17 06:02:24 PM PDT 24
Finished Jul 17 06:02:26 PM PDT 24
Peak memory 200276 kb
Host smart-5772d3c8-a37d-457e-b03c-ae62bbfc5abf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236991193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1236991193
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3055663945
Short name T108
Test name
Test status
Simulation time 229326577 ps
CPU time 1.46 seconds
Started Jul 17 06:02:28 PM PDT 24
Finished Jul 17 06:02:31 PM PDT 24
Peak memory 200392 kb
Host smart-be35133c-7aab-4962-9244-98445a56b4d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055663945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3055663945
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.550611816
Short name T616
Test name
Test status
Simulation time 205911297 ps
CPU time 2.77 seconds
Started Jul 17 06:02:24 PM PDT 24
Finished Jul 17 06:02:28 PM PDT 24
Peak memory 216728 kb
Host smart-2ce452f1-fb3c-4f0d-b09e-940ef9e89d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550611816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.550611816
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3142877854
Short name T550
Test name
Test status
Simulation time 969159874 ps
CPU time 3.05 seconds
Started Jul 17 06:02:27 PM PDT 24
Finished Jul 17 06:02:31 PM PDT 24
Peak memory 200572 kb
Host smart-0bd8705e-2094-4f1e-9a44-ed2282baf397
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142877854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3142877854
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3985366563
Short name T610
Test name
Test status
Simulation time 215360193 ps
CPU time 1.38 seconds
Started Jul 17 06:04:12 PM PDT 24
Finished Jul 17 06:04:14 PM PDT 24
Peak memory 208612 kb
Host smart-0df2ae3c-5953-4640-8754-fcf112439350
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985366563 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3985366563
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1343952579
Short name T564
Test name
Test status
Simulation time 78694994 ps
CPU time 0.89 seconds
Started Jul 17 06:04:02 PM PDT 24
Finished Jul 17 06:04:04 PM PDT 24
Peak memory 200232 kb
Host smart-60da2120-3f12-4ac1-abb3-304bcee0b1f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343952579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1343952579
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3120417303
Short name T110
Test name
Test status
Simulation time 72648667 ps
CPU time 0.93 seconds
Started Jul 17 06:04:02 PM PDT 24
Finished Jul 17 06:04:04 PM PDT 24
Peak memory 200296 kb
Host smart-9fc77059-c2f4-4e9f-9954-6cee6b2c38dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120417303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3120417303
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1872051377
Short name T566
Test name
Test status
Simulation time 270945459 ps
CPU time 1.97 seconds
Started Jul 17 06:02:25 PM PDT 24
Finished Jul 17 06:02:29 PM PDT 24
Peak memory 216852 kb
Host smart-77217a92-cc73-4e5b-bb0e-cf3cb67283d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872051377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1872051377
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3038352109
Short name T82
Test name
Test status
Simulation time 1004157392 ps
CPU time 3.22 seconds
Started Jul 17 06:03:54 PM PDT 24
Finished Jul 17 06:03:58 PM PDT 24
Peak memory 200484 kb
Host smart-04663e71-58b0-4a4f-8421-c45d6c62b525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038352109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3038352109
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.490346147
Short name T601
Test name
Test status
Simulation time 203285222 ps
CPU time 1.39 seconds
Started Jul 17 06:02:28 PM PDT 24
Finished Jul 17 06:02:31 PM PDT 24
Peak memory 208552 kb
Host smart-1f8ccbea-837f-4e3d-afeb-a0ac3e417338
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490346147 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.490346147
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3361121999
Short name T586
Test name
Test status
Simulation time 63898040 ps
CPU time 0.82 seconds
Started Jul 17 06:04:02 PM PDT 24
Finished Jul 17 06:04:04 PM PDT 24
Peak memory 200232 kb
Host smart-454d0af5-37bb-4b84-bd96-35fdaac24f09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361121999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3361121999
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1338164463
Short name T559
Test name
Test status
Simulation time 78821317 ps
CPU time 0.96 seconds
Started Jul 17 06:04:13 PM PDT 24
Finished Jul 17 06:04:15 PM PDT 24
Peak memory 200340 kb
Host smart-0c4ff537-775a-408b-a312-47b44020fa56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338164463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1338164463
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.426914772
Short name T79
Test name
Test status
Simulation time 239580106 ps
CPU time 1.84 seconds
Started Jul 17 06:04:17 PM PDT 24
Finished Jul 17 06:04:20 PM PDT 24
Peak memory 210704 kb
Host smart-e3cb865a-9130-4cd4-b477-5114796a1db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426914772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.426914772
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.590511579
Short name T84
Test name
Test status
Simulation time 781578417 ps
CPU time 2.81 seconds
Started Jul 17 06:02:25 PM PDT 24
Finished Jul 17 06:02:29 PM PDT 24
Peak memory 200496 kb
Host smart-5fceb8c1-ccf0-4aaf-b110-192cfffce08e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590511579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
590511579
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3157054791
Short name T553
Test name
Test status
Simulation time 174487837 ps
CPU time 1.73 seconds
Started Jul 17 06:04:02 PM PDT 24
Finished Jul 17 06:04:05 PM PDT 24
Peak memory 208744 kb
Host smart-438a3ffc-203a-4b6f-900f-a6840c49e507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157054791 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3157054791
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1604228124
Short name T611
Test name
Test status
Simulation time 75996858 ps
CPU time 0.82 seconds
Started Jul 17 06:02:26 PM PDT 24
Finished Jul 17 06:02:28 PM PDT 24
Peak memory 200280 kb
Host smart-06ba1986-9c88-434e-999d-32580e066e39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604228124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1604228124
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2246319954
Short name T612
Test name
Test status
Simulation time 131239617 ps
CPU time 1.14 seconds
Started Jul 17 06:02:26 PM PDT 24
Finished Jul 17 06:02:28 PM PDT 24
Peak memory 200360 kb
Host smart-d8ef7b3a-273e-422a-bd2e-91c2f0ef6c8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246319954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2246319954
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1849627672
Short name T78
Test name
Test status
Simulation time 233458929 ps
CPU time 1.88 seconds
Started Jul 17 06:04:12 PM PDT 24
Finished Jul 17 06:04:14 PM PDT 24
Peak memory 216716 kb
Host smart-adf674f5-88c0-43bd-a187-c7e76d5e644a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849627672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1849627672
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2130271799
Short name T61
Test name
Test status
Simulation time 833374909 ps
CPU time 2.76 seconds
Started Jul 17 06:04:17 PM PDT 24
Finished Jul 17 06:04:21 PM PDT 24
Peak memory 200408 kb
Host smart-7ff791d0-c8f8-429f-aa3e-b478c1ac35bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130271799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2130271799
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3559184825
Short name T614
Test name
Test status
Simulation time 62497693 ps
CPU time 0.86 seconds
Started Jul 17 06:02:26 PM PDT 24
Finished Jul 17 06:02:28 PM PDT 24
Peak memory 200232 kb
Host smart-46864dbe-416b-4955-b5b0-c8cfacec7572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559184825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3559184825
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.706703930
Short name T570
Test name
Test status
Simulation time 105621962 ps
CPU time 1.28 seconds
Started Jul 17 06:02:25 PM PDT 24
Finished Jul 17 06:02:27 PM PDT 24
Peak memory 200484 kb
Host smart-c889b1ef-21de-42e7-be6b-dc0f02598abe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706703930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.706703930
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4102350329
Short name T60
Test name
Test status
Simulation time 300457498 ps
CPU time 1.94 seconds
Started Jul 17 06:04:18 PM PDT 24
Finished Jul 17 06:04:21 PM PDT 24
Peak memory 208548 kb
Host smart-e9bc0053-bd6d-4c33-a806-6c8e1a90fd7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102350329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.4102350329
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1490514616
Short name T602
Test name
Test status
Simulation time 479027447 ps
CPU time 2.09 seconds
Started Jul 17 06:02:25 PM PDT 24
Finished Jul 17 06:02:29 PM PDT 24
Peak memory 200484 kb
Host smart-ddb1a553-7ba2-4c04-b94d-c38f702a727b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490514616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1490514616
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4028754271
Short name T88
Test name
Test status
Simulation time 117065179 ps
CPU time 1.04 seconds
Started Jul 17 06:02:27 PM PDT 24
Finished Jul 17 06:02:30 PM PDT 24
Peak memory 200352 kb
Host smart-079a5ad4-f304-431a-a676-5c53adffdf04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028754271 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.4028754271
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1437323947
Short name T113
Test name
Test status
Simulation time 54908341 ps
CPU time 0.7 seconds
Started Jul 17 06:02:31 PM PDT 24
Finished Jul 17 06:02:32 PM PDT 24
Peak memory 200224 kb
Host smart-e6ec02a3-f7dc-4078-b614-a41d25ecf07b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437323947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1437323947
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2960515405
Short name T582
Test name
Test status
Simulation time 250447954 ps
CPU time 1.51 seconds
Started Jul 17 06:02:25 PM PDT 24
Finished Jul 17 06:02:27 PM PDT 24
Peak memory 208676 kb
Host smart-f334b8de-9555-447e-bce9-848db6b1c72e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960515405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2960515405
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1471073428
Short name T569
Test name
Test status
Simulation time 435751538 ps
CPU time 2.78 seconds
Started Jul 17 06:04:20 PM PDT 24
Finished Jul 17 06:04:23 PM PDT 24
Peak memory 208620 kb
Host smart-b614ba44-da64-4669-a411-5cfaa45108f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471073428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1471073428
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.526049224
Short name T599
Test name
Test status
Simulation time 494209945 ps
CPU time 1.94 seconds
Started Jul 17 06:02:27 PM PDT 24
Finished Jul 17 06:02:31 PM PDT 24
Peak memory 200412 kb
Host smart-acfb6930-6bc1-4589-b1e1-53904f963b75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526049224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
526049224
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.4142399765
Short name T386
Test name
Test status
Simulation time 81702003 ps
CPU time 0.81 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 200016 kb
Host smart-710e5b76-e581-4b1e-8b6a-53163a4d567e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142399765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4142399765
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3701540065
Short name T461
Test name
Test status
Simulation time 1231167746 ps
CPU time 5.4 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:17 PM PDT 24
Peak memory 217508 kb
Host smart-47ede2b3-ad3f-409f-b079-e1f82d95d60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701540065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3701540065
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2134149454
Short name T164
Test name
Test status
Simulation time 245083122 ps
CPU time 1.06 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:13 PM PDT 24
Peak memory 217552 kb
Host smart-8c94e3b4-e819-406a-b6d3-00fd07bf8803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134149454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2134149454
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4118050008
Short name T525
Test name
Test status
Simulation time 190619900 ps
CPU time 0.91 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 199972 kb
Host smart-7c6c3719-a973-4a7a-805b-b8f3330104ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118050008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4118050008
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1235025628
Short name T228
Test name
Test status
Simulation time 845334311 ps
CPU time 4.23 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:15 PM PDT 24
Peak memory 200412 kb
Host smart-ccb48725-70c8-4565-a97c-d66fa03313ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235025628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1235025628
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3161462163
Short name T397
Test name
Test status
Simulation time 112496758 ps
CPU time 0.98 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:11 PM PDT 24
Peak memory 200160 kb
Host smart-742d278c-ef39-4a88-8db0-80d1dbf4fb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161462163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3161462163
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3233933536
Short name T518
Test name
Test status
Simulation time 119314976 ps
CPU time 1.11 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:11 PM PDT 24
Peak memory 200380 kb
Host smart-d6df126f-fdab-45b1-a139-e40603b5c7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233933536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3233933536
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1267242993
Short name T342
Test name
Test status
Simulation time 950453367 ps
CPU time 4.67 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:16 PM PDT 24
Peak memory 200424 kb
Host smart-1a2e744f-f22a-4a69-b989-dd28b431a241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267242993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1267242993
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2495334920
Short name T203
Test name
Test status
Simulation time 382821092 ps
CPU time 2.27 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:13 PM PDT 24
Peak memory 200192 kb
Host smart-1675a453-02f2-49f6-8add-d14f56ebc10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495334920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2495334920
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3378765239
Short name T413
Test name
Test status
Simulation time 121118775 ps
CPU time 1.05 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:11 PM PDT 24
Peak memory 200156 kb
Host smart-8c613a8a-f107-4029-a509-e1dd82784c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378765239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3378765239
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2220076359
Short name T317
Test name
Test status
Simulation time 73938362 ps
CPU time 0.78 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 199956 kb
Host smart-73a62b09-cb2e-4073-a171-122e3d7438b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220076359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2220076359
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3747664350
Short name T468
Test name
Test status
Simulation time 1228840934 ps
CPU time 5.86 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:18 PM PDT 24
Peak memory 217544 kb
Host smart-fb60cb1c-e74a-45fc-82c6-4847193a23a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747664350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3747664350
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2131699410
Short name T503
Test name
Test status
Simulation time 244360356 ps
CPU time 1.1 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 217544 kb
Host smart-4bd02f87-016d-4862-a6cb-42f37faa76b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131699410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2131699410
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3149044464
Short name T431
Test name
Test status
Simulation time 183953013 ps
CPU time 0.89 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 199964 kb
Host smart-0e84d342-5ed2-4e75-a94a-1a2fee91e6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149044464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3149044464
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3140462630
Short name T106
Test name
Test status
Simulation time 694454508 ps
CPU time 3.71 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:15 PM PDT 24
Peak memory 200432 kb
Host smart-388d017e-9487-45f6-81f0-648fb5516a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140462630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3140462630
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3070043055
Short name T65
Test name
Test status
Simulation time 8429481518 ps
CPU time 12.61 seconds
Started Jul 17 07:10:55 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 217160 kb
Host smart-bc98abbb-668c-465b-97fd-ef4cded636dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070043055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3070043055
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2192009348
Short name T334
Test name
Test status
Simulation time 173989371 ps
CPU time 1.13 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 200224 kb
Host smart-29001e1a-148f-4cf0-baaf-0daec5cdcd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192009348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2192009348
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1841697518
Short name T223
Test name
Test status
Simulation time 122788548 ps
CPU time 1.23 seconds
Started Jul 17 07:11:02 PM PDT 24
Finished Jul 17 07:11:06 PM PDT 24
Peak memory 200304 kb
Host smart-5072af27-bf28-4044-a13c-bbe268430097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841697518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1841697518
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.263169746
Short name T182
Test name
Test status
Simulation time 301202131 ps
CPU time 1.56 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 200432 kb
Host smart-da4f9886-1394-443c-97cd-312eb99f9d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263169746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.263169746
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2876921081
Short name T215
Test name
Test status
Simulation time 85115614 ps
CPU time 0.79 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:42 PM PDT 24
Peak memory 200028 kb
Host smart-eb25e4ac-a2d6-4677-8b36-40aca54ccfa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876921081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2876921081
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3392287771
Short name T380
Test name
Test status
Simulation time 1875746013 ps
CPU time 7.15 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:46 PM PDT 24
Peak memory 216956 kb
Host smart-57dd26d4-2fbe-4e39-821a-73c3f0438dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392287771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3392287771
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1397943837
Short name T507
Test name
Test status
Simulation time 244365667 ps
CPU time 1.03 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:43 PM PDT 24
Peak memory 217460 kb
Host smart-54750dd8-11d2-4774-badc-16c09d9c9d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397943837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1397943837
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.576455296
Short name T133
Test name
Test status
Simulation time 77781335 ps
CPU time 0.71 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:38 PM PDT 24
Peak memory 199836 kb
Host smart-bc59177f-f4b3-4537-8247-cfea344cd141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576455296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.576455296
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.687039483
Short name T415
Test name
Test status
Simulation time 2061466222 ps
CPU time 6.94 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200352 kb
Host smart-7f09ea25-d17a-4e32-85df-2c63643767f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687039483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.687039483
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1510674645
Short name T214
Test name
Test status
Simulation time 157707528 ps
CPU time 1.13 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:38 PM PDT 24
Peak memory 200164 kb
Host smart-b8ac1394-9c64-4ea7-9255-f866e42bac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510674645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1510674645
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.439854722
Short name T246
Test name
Test status
Simulation time 185417271 ps
CPU time 1.31 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:38 PM PDT 24
Peak memory 200208 kb
Host smart-652d8f40-b35d-4424-bb1e-e25313273551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439854722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.439854722
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.94522863
Short name T438
Test name
Test status
Simulation time 3866319118 ps
CPU time 16.32 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:12:00 PM PDT 24
Peak memory 200392 kb
Host smart-9b2aeeb8-f622-45a7-96c3-68a19afd7f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94522863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.94522863
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3864508343
Short name T270
Test name
Test status
Simulation time 314623036 ps
CPU time 2.23 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 199596 kb
Host smart-10faf165-df1a-4b8f-8775-b1c4ee14456b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864508343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3864508343
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2210833749
Short name T398
Test name
Test status
Simulation time 185832732 ps
CPU time 1.21 seconds
Started Jul 17 07:11:33 PM PDT 24
Finished Jul 17 07:11:35 PM PDT 24
Peak memory 200160 kb
Host smart-fdba255b-29c4-47dc-8cce-64746b8bbf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210833749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2210833749
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1795544451
Short name T187
Test name
Test status
Simulation time 81205693 ps
CPU time 0.77 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 199948 kb
Host smart-fb90995b-6da0-41f8-ac3f-b676e4d4cbc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795544451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1795544451
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.247349182
Short name T196
Test name
Test status
Simulation time 243788181 ps
CPU time 1.1 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:41 PM PDT 24
Peak memory 217420 kb
Host smart-5967928d-d9fc-4dda-93c1-6a96f13b07a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247349182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.247349182
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.471209067
Short name T210
Test name
Test status
Simulation time 212829317 ps
CPU time 0.92 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:36 PM PDT 24
Peak memory 199976 kb
Host smart-cee0da83-74ec-44eb-bfe3-3c5501b3a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471209067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.471209067
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1387801477
Short name T229
Test name
Test status
Simulation time 712786829 ps
CPU time 3.57 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 200420 kb
Host smart-28019fd0-4ef1-46e2-8343-af038fa8ef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387801477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1387801477
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2359521253
Short name T475
Test name
Test status
Simulation time 150154399 ps
CPU time 1.14 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:46 PM PDT 24
Peak memory 200152 kb
Host smart-f6568911-b422-4381-8758-7b11d13e0eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359521253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2359521253
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2069012542
Short name T285
Test name
Test status
Simulation time 245112953 ps
CPU time 1.44 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:43 PM PDT 24
Peak memory 200356 kb
Host smart-4f9d908c-630d-439e-84de-1f4d66987e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069012542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2069012542
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3238699955
Short name T67
Test name
Test status
Simulation time 4883812837 ps
CPU time 21.53 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:12:02 PM PDT 24
Peak memory 208676 kb
Host smart-2f7d3d37-340e-4039-9873-fbba92102218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238699955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3238699955
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2040461471
Short name T183
Test name
Test status
Simulation time 378376007 ps
CPU time 2.4 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 200148 kb
Host smart-39c132f0-4446-46bf-9de8-1ff3943361fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040461471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2040461471
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1035030280
Short name T513
Test name
Test status
Simulation time 173025774 ps
CPU time 1.11 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:36 PM PDT 24
Peak memory 200176 kb
Host smart-3f7d2207-3750-401b-baae-3520ac4b64c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035030280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1035030280
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2941748129
Short name T191
Test name
Test status
Simulation time 56704153 ps
CPU time 0.72 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 199948 kb
Host smart-3b68c96f-601f-44ae-896d-75ac477334bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941748129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2941748129
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3574823184
Short name T122
Test name
Test status
Simulation time 1888497540 ps
CPU time 6.93 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 217608 kb
Host smart-62c9c896-0b7a-4252-b6ad-9e12c8c81cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574823184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3574823184
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2619390311
Short name T314
Test name
Test status
Simulation time 243783323 ps
CPU time 1.04 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:45 PM PDT 24
Peak memory 217528 kb
Host smart-83763f0e-f828-4116-a9f5-e49293501678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619390311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2619390311
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.49058327
Short name T347
Test name
Test status
Simulation time 170541423 ps
CPU time 0.89 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:41 PM PDT 24
Peak memory 199956 kb
Host smart-ae5fe072-9148-48d2-a16e-40e50ef78346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49058327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.49058327
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.4257150000
Short name T257
Test name
Test status
Simulation time 1845042250 ps
CPU time 6.55 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:44 PM PDT 24
Peak memory 200404 kb
Host smart-349305fe-2a66-404c-b9be-a83ab6b03593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257150000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.4257150000
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1283067474
Short name T330
Test name
Test status
Simulation time 177616558 ps
CPU time 1.16 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:45 PM PDT 24
Peak memory 200220 kb
Host smart-62bed4c4-8d2a-4970-b7c9-fea67e0669af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283067474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1283067474
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3924653225
Short name T283
Test name
Test status
Simulation time 203325470 ps
CPU time 1.4 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:44 PM PDT 24
Peak memory 200344 kb
Host smart-42340e70-8e44-4a8c-9b2f-17f0a02c2f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924653225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3924653225
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1173772481
Short name T296
Test name
Test status
Simulation time 1106339482 ps
CPU time 4.9 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:41 PM PDT 24
Peak memory 200236 kb
Host smart-989f55c5-16f3-4522-9411-50759dd3e044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173772481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1173772481
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1612563998
Short name T206
Test name
Test status
Simulation time 391456042 ps
CPU time 2.1 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:46 PM PDT 24
Peak memory 199664 kb
Host smart-a28a7352-c799-4e1a-ba44-5f2f952ced34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612563998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1612563998
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3649635854
Short name T392
Test name
Test status
Simulation time 173695422 ps
CPU time 1.28 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:50 PM PDT 24
Peak memory 200344 kb
Host smart-72fc9482-8970-4aac-81ba-ad6817582aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649635854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3649635854
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1490057104
Short name T293
Test name
Test status
Simulation time 78774684 ps
CPU time 0.76 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:45 PM PDT 24
Peak memory 199948 kb
Host smart-1d8eabe9-43ab-4369-930d-11092c1e0287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490057104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1490057104
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2888314593
Short name T31
Test name
Test status
Simulation time 1227032015 ps
CPU time 5.56 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:50 PM PDT 24
Peak memory 221772 kb
Host smart-f3ac0081-9957-46f3-ac89-042dedf12bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888314593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2888314593
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.773018192
Short name T251
Test name
Test status
Simulation time 244739589 ps
CPU time 1.06 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:37 PM PDT 24
Peak memory 217488 kb
Host smart-51150928-68cd-4304-85a2-e06be09ec7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773018192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.773018192
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1611558367
Short name T102
Test name
Test status
Simulation time 1818008850 ps
CPU time 7.69 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 200428 kb
Host smart-6a7db6a8-fa09-4ec0-8251-50d8443dc91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611558367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1611558367
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1917219043
Short name T9
Test name
Test status
Simulation time 196730776 ps
CPU time 1.27 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:42 PM PDT 24
Peak memory 200332 kb
Host smart-8f628ed2-56fc-41be-907c-96f2b15ed062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917219043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1917219043
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1173263019
Short name T350
Test name
Test status
Simulation time 3102224504 ps
CPU time 13.43 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:12:02 PM PDT 24
Peak memory 200520 kb
Host smart-8f8c5bee-7877-4033-9c81-81164cd5ecdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173263019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1173263019
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1883039281
Short name T248
Test name
Test status
Simulation time 123789358 ps
CPU time 1.66 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:52 PM PDT 24
Peak memory 208264 kb
Host smart-76eeba8f-aaf9-443f-8209-46c3cf04b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883039281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1883039281
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1045161921
Short name T401
Test name
Test status
Simulation time 136202208 ps
CPU time 1.01 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 200152 kb
Host smart-59d1d0a4-07ae-4fcf-8c30-b6c0bfa5f826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045161921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1045161921
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3241551435
Short name T138
Test name
Test status
Simulation time 70697894 ps
CPU time 0.79 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 199960 kb
Host smart-4f9c065a-da7e-4c97-8963-6b0cb48b799a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241551435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3241551435
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1910155346
Short name T24
Test name
Test status
Simulation time 1226258244 ps
CPU time 5.86 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 217020 kb
Host smart-8b031d20-3b68-4960-a0e0-36786062e30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910155346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1910155346
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3104194576
Short name T488
Test name
Test status
Simulation time 244482469 ps
CPU time 1.11 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 217424 kb
Host smart-14cffa63-c7d6-41c2-b37d-1a8bb9fc7603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104194576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3104194576
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3799273358
Short name T274
Test name
Test status
Simulation time 132039374 ps
CPU time 0.89 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:41 PM PDT 24
Peak memory 199892 kb
Host smart-533c6d7e-f667-42a4-94da-4223060b3c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799273358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3799273358
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2402735047
Short name T369
Test name
Test status
Simulation time 1120954413 ps
CPU time 5.3 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 200424 kb
Host smart-b12b06a9-3d3a-4fa8-99da-545a73b24014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402735047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2402735047
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3543051592
Short name T534
Test name
Test status
Simulation time 100355109 ps
CPU time 1.02 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200152 kb
Host smart-e47c5d7f-835e-4115-a076-f4df64d20167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543051592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3543051592
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3729499405
Short name T272
Test name
Test status
Simulation time 208662979 ps
CPU time 1.32 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:44 PM PDT 24
Peak memory 200320 kb
Host smart-2f962caf-7457-42e9-b605-8b20636dc195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729499405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3729499405
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1832312777
Short name T116
Test name
Test status
Simulation time 8934315759 ps
CPU time 28.74 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:12:20 PM PDT 24
Peak memory 208656 kb
Host smart-5dc30d2b-e9cd-418f-a24b-3fd8ff11707d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832312777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1832312777
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.578875924
Short name T375
Test name
Test status
Simulation time 414832521 ps
CPU time 2.14 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:39 PM PDT 24
Peak memory 208224 kb
Host smart-26166506-04fe-4713-b4a2-02cf84a5f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578875924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.578875924
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.546693502
Short name T462
Test name
Test status
Simulation time 102236035 ps
CPU time 0.95 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:41 PM PDT 24
Peak memory 200144 kb
Host smart-9312cbbf-3180-48da-b114-8d0e34cc82ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546693502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.546693502
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.875749171
Short name T256
Test name
Test status
Simulation time 1890413660 ps
CPU time 7.5 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:02 PM PDT 24
Peak memory 217744 kb
Host smart-63ff6144-30df-4d0d-ab72-d33ec106bc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875749171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.875749171
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1278857883
Short name T192
Test name
Test status
Simulation time 244917644 ps
CPU time 1.01 seconds
Started Jul 17 07:11:26 PM PDT 24
Finished Jul 17 07:11:27 PM PDT 24
Peak memory 217628 kb
Host smart-97742cf5-9410-4609-b3f9-131680b7ebcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278857883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1278857883
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3548475760
Short name T422
Test name
Test status
Simulation time 158374829 ps
CPU time 0.86 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 199976 kb
Host smart-71f669cd-a9d5-491e-a904-810649f74466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548475760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3548475760
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2786442253
Short name T176
Test name
Test status
Simulation time 831914206 ps
CPU time 4.26 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:52 PM PDT 24
Peak memory 200424 kb
Host smart-f5462fa8-9435-4a3b-9137-fc1ca30d5ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786442253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2786442253
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3661169258
Short name T453
Test name
Test status
Simulation time 141536843 ps
CPU time 1.09 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:50 PM PDT 24
Peak memory 200132 kb
Host smart-8838bf98-be07-4163-bab4-6adaa68c97c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661169258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3661169258
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.181455180
Short name T212
Test name
Test status
Simulation time 247982452 ps
CPU time 1.47 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200152 kb
Host smart-b5f72dcd-3872-40a5-b2c8-d1dfd63ed684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181455180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.181455180
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3406817722
Short name T429
Test name
Test status
Simulation time 1910296230 ps
CPU time 9 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:12:00 PM PDT 24
Peak memory 209728 kb
Host smart-cd84160f-84b8-40c5-927b-42a75ff2f515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406817722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3406817722
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.194919599
Short name T378
Test name
Test status
Simulation time 134693148 ps
CPU time 1.61 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 208572 kb
Host smart-9592cfe4-6c4f-46c2-98f1-ca32af16d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194919599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.194919599
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3049589555
Short name T130
Test name
Test status
Simulation time 235498889 ps
CPU time 1.52 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 200356 kb
Host smart-f0ff5822-741f-4475-8cf0-8f424969d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049589555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3049589555
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1682570011
Short name T498
Test name
Test status
Simulation time 64609706 ps
CPU time 0.75 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 199960 kb
Host smart-a96b9ff4-ef0f-4525-b11c-b89b93c8e4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682570011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1682570011
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.213725984
Short name T29
Test name
Test status
Simulation time 2371714174 ps
CPU time 7.99 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:59 PM PDT 24
Peak memory 217932 kb
Host smart-0ad0df77-0536-41d3-8678-9d2d9b211786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213725984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.213725984
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2991527065
Short name T181
Test name
Test status
Simulation time 244739401 ps
CPU time 1.09 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 217368 kb
Host smart-bc499c7e-4d13-4565-ad66-d1b4e0eba05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991527065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2991527065
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1197602162
Short name T10
Test name
Test status
Simulation time 170868992 ps
CPU time 0.88 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 199956 kb
Host smart-242cf47c-198b-430f-8d4e-ce15eacc7072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197602162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1197602162
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3827900797
Short name T339
Test name
Test status
Simulation time 1429375925 ps
CPU time 5.79 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200472 kb
Host smart-1f03574d-409e-49b2-993d-084bed48edac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827900797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3827900797
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3941872766
Short name T383
Test name
Test status
Simulation time 185735036 ps
CPU time 1.2 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:56 PM PDT 24
Peak memory 200112 kb
Host smart-808f8559-5d9a-45f3-8379-f8f5a53ec73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941872766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3941872766
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2236831332
Short name T351
Test name
Test status
Simulation time 231498590 ps
CPU time 1.46 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 200332 kb
Host smart-619ed638-68fd-4c82-b4e9-00004de33df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236831332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2236831332
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2489885522
Short name T435
Test name
Test status
Simulation time 4171233596 ps
CPU time 18.43 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:12 PM PDT 24
Peak memory 200484 kb
Host smart-a6dbd958-7972-4f0c-95ef-392cc174ce8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489885522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2489885522
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1266412543
Short name T308
Test name
Test status
Simulation time 279026075 ps
CPU time 1.78 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 199972 kb
Host smart-61f1d3a9-d93a-47d6-a41b-ae3cd8fb82f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266412543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1266412543
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2559493189
Short name T244
Test name
Test status
Simulation time 207025476 ps
CPU time 1.24 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:52 PM PDT 24
Peak memory 200088 kb
Host smart-7176b53a-0ba4-480c-8ed9-3bc115423ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559493189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2559493189
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.328361338
Short name T304
Test name
Test status
Simulation time 65653437 ps
CPU time 0.71 seconds
Started Jul 17 07:11:43 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 199948 kb
Host smart-bfe26186-c780-44c4-8764-e91bca8f1ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328361338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.328361338
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.7312386
Short name T414
Test name
Test status
Simulation time 1882210108 ps
CPU time 8.11 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:12:03 PM PDT 24
Peak memory 216804 kb
Host smart-9165f4d9-200a-418e-8e6b-928068deb9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7312386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.7312386
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2061978296
Short name T463
Test name
Test status
Simulation time 244291938 ps
CPU time 1.02 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 217364 kb
Host smart-20a0ce17-3fd4-425f-a3f1-c453b65ba121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061978296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2061978296
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3129145811
Short name T532
Test name
Test status
Simulation time 115856802 ps
CPU time 0.79 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 199976 kb
Host smart-a204aeba-8e36-40c6-8e2a-58a4c1df7ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129145811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3129145811
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2758627371
Short name T117
Test name
Test status
Simulation time 2033806222 ps
CPU time 7.09 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:02 PM PDT 24
Peak memory 200420 kb
Host smart-d18b8498-2f3d-4a2f-90e0-adaa45b07850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758627371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2758627371
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1484077738
Short name T528
Test name
Test status
Simulation time 143537101 ps
CPU time 1.1 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:56 PM PDT 24
Peak memory 200116 kb
Host smart-b75db4ea-c554-47e7-a143-901faa1afe9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484077738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1484077738
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3063942076
Short name T358
Test name
Test status
Simulation time 209402240 ps
CPU time 1.39 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 200204 kb
Host smart-9e4379a3-e8cb-4423-bf03-6a06acc9ce42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063942076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3063942076
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1227655076
Short name T361
Test name
Test status
Simulation time 3909566213 ps
CPU time 15.98 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:10 PM PDT 24
Peak memory 208536 kb
Host smart-79744bcc-5dfd-4bf6-8239-2ec834a89b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227655076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1227655076
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.308296034
Short name T279
Test name
Test status
Simulation time 325792147 ps
CPU time 2.1 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:56 PM PDT 24
Peak memory 200204 kb
Host smart-09fac831-88b7-456b-b7e9-83dcccc8f2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308296034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.308296034
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2030186418
Short name T169
Test name
Test status
Simulation time 141898649 ps
CPU time 1.01 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:52 PM PDT 24
Peak memory 200136 kb
Host smart-8eaa328a-8638-4064-bdc3-4b5f95278e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030186418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2030186418
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2908856383
Short name T537
Test name
Test status
Simulation time 67655475 ps
CPU time 0.73 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 199948 kb
Host smart-5742ea10-7ec3-4509-bb6e-69ec5d7e0ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908856383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2908856383
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2194412992
Short name T476
Test name
Test status
Simulation time 1215588783 ps
CPU time 5.74 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 217844 kb
Host smart-6d03883d-75a0-4f97-a62a-7afea39f8807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194412992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2194412992
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1537540132
Short name T156
Test name
Test status
Simulation time 94325894 ps
CPU time 0.74 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 200132 kb
Host smart-37a12aaf-3cfa-41aa-99ab-0d7743f68e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537540132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1537540132
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2937768884
Short name T523
Test name
Test status
Simulation time 709999217 ps
CPU time 3.68 seconds
Started Jul 17 07:11:44 PM PDT 24
Finished Jul 17 07:12:01 PM PDT 24
Peak memory 200420 kb
Host smart-f1c4cf41-f5e1-4ccf-815c-0c50637e08d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937768884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2937768884
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2210007250
Short name T303
Test name
Test status
Simulation time 104829849 ps
CPU time 1.06 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:45 PM PDT 24
Peak memory 200140 kb
Host smart-b7919b00-3400-4711-b4cb-4af33d4eb477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210007250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2210007250
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2650108182
Short name T185
Test name
Test status
Simulation time 254317889 ps
CPU time 1.48 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200524 kb
Host smart-a217011e-5392-4dcd-94a0-78f68078f3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650108182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2650108182
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2162070678
Short name T379
Test name
Test status
Simulation time 6931966312 ps
CPU time 23.65 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:12:10 PM PDT 24
Peak memory 208724 kb
Host smart-f038e353-805c-4ee1-ad89-7bfd0a5efb1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162070678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2162070678
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1629338194
Short name T411
Test name
Test status
Simulation time 328911025 ps
CPU time 2.15 seconds
Started Jul 17 07:11:44 PM PDT 24
Finished Jul 17 07:11:59 PM PDT 24
Peak memory 200160 kb
Host smart-98c4db8d-300d-41d8-8ec4-ad5fb99a8a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629338194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1629338194
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.808540002
Short name T237
Test name
Test status
Simulation time 90315574 ps
CPU time 0.88 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200156 kb
Host smart-b5f78445-d484-442e-ac1a-5bcecc8e4206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808540002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.808540002
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1805603366
Short name T163
Test name
Test status
Simulation time 70238022 ps
CPU time 0.76 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200124 kb
Host smart-c210a763-ece9-47d9-9eda-57fd3963429c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805603366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1805603366
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.634153088
Short name T45
Test name
Test status
Simulation time 1906969912 ps
CPU time 7.8 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 217804 kb
Host smart-e6c56c54-c44c-4d9b-9572-7c29a0cedb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634153088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.634153088
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.592076531
Short name T235
Test name
Test status
Simulation time 244274732 ps
CPU time 1.04 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:50 PM PDT 24
Peak memory 217496 kb
Host smart-f674b595-22e2-43a5-b4b6-1ea21bb45370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592076531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.592076531
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.222508395
Short name T297
Test name
Test status
Simulation time 174831583 ps
CPU time 0.86 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 199960 kb
Host smart-c783d85d-2055-48ee-9809-154ef233da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222508395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.222508395
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3099321362
Short name T20
Test name
Test status
Simulation time 1129787715 ps
CPU time 4.63 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 200476 kb
Host smart-966a90d9-4cd2-473b-b586-bf5ae0e00f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099321362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3099321362
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3760393907
Short name T139
Test name
Test status
Simulation time 113868195 ps
CPU time 1 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 200136 kb
Host smart-30a4167f-a46a-49d2-a45c-e00eeb84d015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760393907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3760393907
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3726524222
Short name T328
Test name
Test status
Simulation time 254904052 ps
CPU time 1.57 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 200316 kb
Host smart-8e8f00b4-d5ea-46e1-b24c-6af1121fa316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726524222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3726524222
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3492405492
Short name T96
Test name
Test status
Simulation time 3445066518 ps
CPU time 15.23 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:12:05 PM PDT 24
Peak memory 200456 kb
Host smart-0c7449a5-7b46-4f70-8a97-7128b662ec57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492405492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3492405492
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3916232190
Short name T389
Test name
Test status
Simulation time 127456910 ps
CPU time 1.59 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:45 PM PDT 24
Peak memory 208320 kb
Host smart-3f2282a0-7aea-484e-b717-ea98891f2cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916232190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3916232190
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1690272259
Short name T457
Test name
Test status
Simulation time 90666150 ps
CPU time 0.82 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:42 PM PDT 24
Peak memory 200140 kb
Host smart-5c7f2c9e-c41e-4276-a13b-4916df6b9398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690272259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1690272259
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.783864252
Short name T34
Test name
Test status
Simulation time 93023596 ps
CPU time 0.83 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 200036 kb
Host smart-e483c3db-47dd-4319-a080-6256bab2661a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783864252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.783864252
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3383653651
Short name T32
Test name
Test status
Simulation time 1220631706 ps
CPU time 6.11 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 221748 kb
Host smart-8284c5ae-be19-4b6f-9bda-0a194e9e4ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383653651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3383653651
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3893934786
Short name T209
Test name
Test status
Simulation time 247441671 ps
CPU time 1.15 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:10 PM PDT 24
Peak memory 217508 kb
Host smart-8afb6bf8-5067-4049-abbe-5d5e890a03b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893934786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3893934786
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1420341046
Short name T366
Test name
Test status
Simulation time 208356583 ps
CPU time 0.98 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 199948 kb
Host smart-af5a9221-2240-4d3a-bcc1-2cdd32d99c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420341046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1420341046
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2431229279
Short name T259
Test name
Test status
Simulation time 1748256493 ps
CPU time 6.02 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:08 PM PDT 24
Peak memory 200392 kb
Host smart-5b92bb36-8849-4be9-8e0f-8431ebd8603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431229279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2431229279
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1447740992
Short name T66
Test name
Test status
Simulation time 8362310522 ps
CPU time 13.97 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:15 PM PDT 24
Peak memory 217164 kb
Host smart-ef02395f-082b-446f-b0b0-869d58411e9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447740992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1447740992
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3532984464
Short name T329
Test name
Test status
Simulation time 145699283 ps
CPU time 1.06 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 200140 kb
Host smart-0c43be47-1fe5-4860-826c-8d67072f486c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532984464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3532984464
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.443497646
Short name T456
Test name
Test status
Simulation time 229819269 ps
CPU time 1.38 seconds
Started Jul 17 07:10:55 PM PDT 24
Finished Jul 17 07:10:58 PM PDT 24
Peak memory 200368 kb
Host smart-de8d269f-86d6-4d9a-8bdb-c026c80488de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443497646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.443497646
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1145913974
Short name T218
Test name
Test status
Simulation time 1533206313 ps
CPU time 6.06 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:14 PM PDT 24
Peak memory 200472 kb
Host smart-8beef27f-b085-49e6-a7df-b242b8bbdb18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145913974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1145913974
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3891162239
Short name T52
Test name
Test status
Simulation time 490859602 ps
CPU time 2.47 seconds
Started Jul 17 07:10:56 PM PDT 24
Finished Jul 17 07:10:59 PM PDT 24
Peak memory 200148 kb
Host smart-960bdfe5-22bb-4273-a0f2-b5972c7cc586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891162239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3891162239
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1719465584
Short name T340
Test name
Test status
Simulation time 286574960 ps
CPU time 1.52 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:10 PM PDT 24
Peak memory 200360 kb
Host smart-8369c804-3a15-4d5f-822d-44c29c2cb08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719465584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1719465584
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.77853410
Short name T493
Test name
Test status
Simulation time 72982159 ps
CPU time 0.8 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:52 PM PDT 24
Peak memory 199916 kb
Host smart-9232dd1f-f913-449a-af71-ce2a1bf976ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77853410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.77853410
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.886199971
Short name T444
Test name
Test status
Simulation time 1222211059 ps
CPU time 5.41 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:59 PM PDT 24
Peak memory 229920 kb
Host smart-9694d6ee-480d-4564-ba00-c90af0a65435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886199971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.886199971
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1393523668
Short name T529
Test name
Test status
Simulation time 244486572 ps
CPU time 1.11 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 217524 kb
Host smart-d0b876b6-5d16-4244-a428-ab8482bf3154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393523668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1393523668
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.938868833
Short name T193
Test name
Test status
Simulation time 169156724 ps
CPU time 0.87 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200140 kb
Host smart-7db30751-1689-486a-8a73-a6f34b95d616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938868833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.938868833
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2353773544
Short name T402
Test name
Test status
Simulation time 1554162611 ps
CPU time 6.25 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 200408 kb
Host smart-20277956-ae4f-4b24-ade5-de5cffa7ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353773544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2353773544
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2367483614
Short name T489
Test name
Test status
Simulation time 116313841 ps
CPU time 0.96 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 200136 kb
Host smart-6a6573bf-6d54-40ea-8d56-7685333152a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367483614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2367483614
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1356984577
Short name T265
Test name
Test status
Simulation time 194206181 ps
CPU time 1.33 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 200344 kb
Host smart-88ac816c-e267-4249-821d-520412a6b45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356984577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1356984577
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.261616807
Short name T538
Test name
Test status
Simulation time 1552419514 ps
CPU time 6.91 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:00 PM PDT 24
Peak memory 208588 kb
Host smart-1eca0afb-dc30-4e20-91c7-d58c81d15055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261616807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.261616807
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.4049951376
Short name T470
Test name
Test status
Simulation time 144956829 ps
CPU time 1.87 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 200332 kb
Host smart-38f26503-d67f-4b73-9075-7ad2cf514fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049951376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.4049951376
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3500925685
Short name T492
Test name
Test status
Simulation time 86070415 ps
CPU time 0.81 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 199944 kb
Host smart-97815481-4cb0-4ba4-885c-400ade718a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500925685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3500925685
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2577730029
Short name T42
Test name
Test status
Simulation time 1900755997 ps
CPU time 7.31 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:12:02 PM PDT 24
Peak memory 217408 kb
Host smart-47c9e983-90c5-45e0-a824-f9e94c24c309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577730029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2577730029
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.726136200
Short name T239
Test name
Test status
Simulation time 244997382 ps
CPU time 1.01 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 217524 kb
Host smart-0a548777-29d4-4b9b-b301-b13fa10eb97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726136200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.726136200
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2386331878
Short name T469
Test name
Test status
Simulation time 221498620 ps
CPU time 0.91 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 199984 kb
Host smart-e732d78b-039a-4573-993d-82de62c14ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386331878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2386331878
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.234600964
Short name T416
Test name
Test status
Simulation time 762860588 ps
CPU time 3.62 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 200420 kb
Host smart-52547812-4d7a-4acc-8540-e321fba745a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234600964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.234600964
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2713285414
Short name T123
Test name
Test status
Simulation time 97444921 ps
CPU time 0.94 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 200160 kb
Host smart-66128f53-4f81-41c8-89e6-a514ae982191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713285414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2713285414
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.4165782607
Short name T424
Test name
Test status
Simulation time 199820063 ps
CPU time 1.29 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:56 PM PDT 24
Peak memory 200268 kb
Host smart-48f7d1f9-81e2-443c-94b9-1eefe8e014b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165782607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.4165782607
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3280429436
Short name T486
Test name
Test status
Simulation time 5414329854 ps
CPU time 23.65 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:12:15 PM PDT 24
Peak memory 210404 kb
Host smart-9a5262ff-51a4-4929-883f-dda3701a5a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280429436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3280429436
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.21204832
Short name T445
Test name
Test status
Simulation time 360109268 ps
CPU time 2.28 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:56 PM PDT 24
Peak memory 200188 kb
Host smart-ca502124-1566-4aee-8c7e-6bf4e4563e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21204832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.21204832
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2825315584
Short name T154
Test name
Test status
Simulation time 71941453 ps
CPU time 0.77 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 200160 kb
Host smart-866ea547-a8ec-47fb-98b7-63aa1b7a5e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825315584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2825315584
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2256821798
Short name T46
Test name
Test status
Simulation time 68122154 ps
CPU time 0.75 seconds
Started Jul 17 07:11:44 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 199960 kb
Host smart-e2fc8754-6afc-444d-94f8-963823571a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256821798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2256821798
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.719797437
Short name T43
Test name
Test status
Simulation time 1234708352 ps
CPU time 6.01 seconds
Started Jul 17 07:11:43 PM PDT 24
Finished Jul 17 07:12:03 PM PDT 24
Peak memory 217840 kb
Host smart-cb9a23d8-77a6-4a32-8a0e-cc00a287c152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719797437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.719797437
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2392398001
Short name T147
Test name
Test status
Simulation time 243735412 ps
CPU time 1.13 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 217732 kb
Host smart-61419e2e-c461-4b61-9d42-d1c4886e896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392398001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2392398001
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.112750011
Short name T391
Test name
Test status
Simulation time 117028023 ps
CPU time 0.78 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 199828 kb
Host smart-2aa4992b-7d89-490b-80a2-9ef465c4fc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112750011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.112750011
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2181433968
Short name T419
Test name
Test status
Simulation time 1323540255 ps
CPU time 5.02 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 200304 kb
Host smart-6697bb20-4bd2-4cd4-88be-0f5790be5e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181433968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2181433968
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3724338459
Short name T142
Test name
Test status
Simulation time 151828115 ps
CPU time 1.06 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200036 kb
Host smart-086d2789-e7b1-45b5-a85c-fe69cc2771b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724338459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3724338459
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3122099701
Short name T430
Test name
Test status
Simulation time 124707185 ps
CPU time 1.21 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 200396 kb
Host smart-49346468-2634-4da1-b50c-ccb497d35dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122099701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3122099701
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1386803659
Short name T101
Test name
Test status
Simulation time 5798824809 ps
CPU time 23.3 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:12:18 PM PDT 24
Peak memory 208856 kb
Host smart-a91d7cde-4c3a-4f0b-a85d-41c2ca7eaa89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386803659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1386803659
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3541670663
Short name T236
Test name
Test status
Simulation time 124280038 ps
CPU time 1.53 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200016 kb
Host smart-1fcc2e17-b3f6-408e-80f7-8d35ee119da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541670663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3541670663
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.4191324189
Short name T124
Test name
Test status
Simulation time 118774375 ps
CPU time 0.91 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 200016 kb
Host smart-d1ea9bf0-bbef-4d04-9528-006c09cf2667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191324189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.4191324189
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3720707774
Short name T500
Test name
Test status
Simulation time 77647286 ps
CPU time 0.84 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 199924 kb
Host smart-777e8684-49b3-4454-a493-d6f9f9dbf3d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720707774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3720707774
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2310344930
Short name T25
Test name
Test status
Simulation time 1883513162 ps
CPU time 7.72 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:50 PM PDT 24
Peak memory 221632 kb
Host smart-8513f899-1d06-43d3-8e18-1d98c2502302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310344930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2310344930
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4010745684
Short name T345
Test name
Test status
Simulation time 244414930 ps
CPU time 1.09 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 217504 kb
Host smart-fbaa2661-b9cc-48be-bbb5-5637d4ef57bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010745684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4010745684
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.351090554
Short name T269
Test name
Test status
Simulation time 193610963 ps
CPU time 0.89 seconds
Started Jul 17 07:11:43 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 199976 kb
Host smart-09902825-f5c6-423f-aff7-d592cf90f502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351090554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.351090554
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2421779592
Short name T311
Test name
Test status
Simulation time 1717501489 ps
CPU time 6.63 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:12:02 PM PDT 24
Peak memory 200592 kb
Host smart-e15a5856-4d2b-40fa-976e-3920d469357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421779592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2421779592
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3427825440
Short name T481
Test name
Test status
Simulation time 142666044 ps
CPU time 1.06 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:44 PM PDT 24
Peak memory 200140 kb
Host smart-97f6c804-b944-4ab8-822c-495473eb54aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427825440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3427825440
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.236382295
Short name T72
Test name
Test status
Simulation time 235150756 ps
CPU time 1.42 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200528 kb
Host smart-294f62c2-7d56-4934-93bd-1820a0198073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236382295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.236382295
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.4268973064
Short name T495
Test name
Test status
Simulation time 461987714 ps
CPU time 2.33 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:45 PM PDT 24
Peak memory 200212 kb
Host smart-c6d5d5a5-cece-487a-9fd8-58ab6c30a2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268973064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.4268973064
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2502204776
Short name T302
Test name
Test status
Simulation time 318705077 ps
CPU time 2.15 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:46 PM PDT 24
Peak memory 200200 kb
Host smart-022d0901-4324-4c39-bbcb-31db6ca2bd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502204776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2502204776
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.482788562
Short name T332
Test name
Test status
Simulation time 63241613 ps
CPU time 0.75 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:46 PM PDT 24
Peak memory 200140 kb
Host smart-3cb8d904-3f18-4314-9f9d-c346c72fd33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482788562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.482788562
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2032387302
Short name T134
Test name
Test status
Simulation time 71655542 ps
CPU time 0.78 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 199932 kb
Host smart-6ea4425e-0967-44f5-882e-83c16473e7ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032387302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2032387302
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1358816298
Short name T273
Test name
Test status
Simulation time 1896832179 ps
CPU time 7.84 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:56 PM PDT 24
Peak memory 217800 kb
Host smart-67b3bd62-4f66-44d6-8341-df3842ec12cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358816298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1358816298
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.154004214
Short name T266
Test name
Test status
Simulation time 243578336 ps
CPU time 1.17 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 217532 kb
Host smart-bdb11fbe-06a8-40fb-a3ad-04925e0f92b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154004214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.154004214
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2815714468
Short name T301
Test name
Test status
Simulation time 101731721 ps
CPU time 0.77 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:37 PM PDT 24
Peak memory 199968 kb
Host smart-bc8cf0cc-0d12-4e82-8401-435f3b728586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815714468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2815714468
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.624259001
Short name T509
Test name
Test status
Simulation time 1086671348 ps
CPU time 4.21 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:42 PM PDT 24
Peak memory 200420 kb
Host smart-b655e7a0-03f6-4a08-bf66-0fc1ddaef6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624259001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.624259001
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1502783795
Short name T400
Test name
Test status
Simulation time 104320231 ps
CPU time 1.02 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 200148 kb
Host smart-c99b6612-3ef3-4322-a55f-799f81bbd611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502783795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1502783795
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3602859918
Short name T234
Test name
Test status
Simulation time 117355346 ps
CPU time 1.12 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 200364 kb
Host smart-75a5f271-a155-46d4-a40a-9f72dc6e2382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602859918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3602859918
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3230661708
Short name T23
Test name
Test status
Simulation time 4589311495 ps
CPU time 15.75 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:12:04 PM PDT 24
Peak memory 200292 kb
Host smart-90d35887-42b4-4313-9b77-539ee7817a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230661708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3230661708
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3369028680
Short name T305
Test name
Test status
Simulation time 281743168 ps
CPU time 1.97 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:41 PM PDT 24
Peak memory 200148 kb
Host smart-ba8a69dc-404a-4b7f-b730-8bff139c6203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369028680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3369028680
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2227200547
Short name T363
Test name
Test status
Simulation time 233081340 ps
CPU time 1.45 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 200140 kb
Host smart-d5cb39b0-3591-409b-936a-5387abc29490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227200547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2227200547
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3904771553
Short name T324
Test name
Test status
Simulation time 77066783 ps
CPU time 0.78 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 199956 kb
Host smart-bf8c84a9-a287-4917-a3b9-04ec77be2d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904771553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3904771553
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.383908518
Short name T48
Test name
Test status
Simulation time 1219716923 ps
CPU time 6 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 217320 kb
Host smart-67b400f4-48ec-4215-ad9f-41ee83d74549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383908518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.383908518
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1798659521
Short name T387
Test name
Test status
Simulation time 244701345 ps
CPU time 1.04 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 217436 kb
Host smart-aa03e16d-57f4-4b24-b114-a41edcee8aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798659521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1798659521
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3575548868
Short name T367
Test name
Test status
Simulation time 231160720 ps
CPU time 0.9 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 199952 kb
Host smart-9d1ef61d-7cfc-46e8-aede-a0c6b201b10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575548868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3575548868
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2754577027
Short name T514
Test name
Test status
Simulation time 916658468 ps
CPU time 4.75 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 200392 kb
Host smart-30afacd6-f69c-4632-808b-23839e00487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754577027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2754577027
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1832884223
Short name T128
Test name
Test status
Simulation time 190566437 ps
CPU time 1.18 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 200128 kb
Host smart-3b55f9a7-24d3-4df3-a20d-3f4dfff4e4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832884223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1832884223
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1003935282
Short name T148
Test name
Test status
Simulation time 116652977 ps
CPU time 1.16 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 200572 kb
Host smart-b4fbb1f9-2b18-4b38-8518-5b1960238603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003935282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1003935282
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1952771726
Short name T465
Test name
Test status
Simulation time 6934465387 ps
CPU time 29.58 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:12:21 PM PDT 24
Peak memory 209752 kb
Host smart-7675d0a5-5a63-4ec9-ad41-a3cd158cfc7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952771726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1952771726
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2224142235
Short name T200
Test name
Test status
Simulation time 128943659 ps
CPU time 1.59 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200148 kb
Host smart-59bd55dd-c769-490b-ae9e-bfb2acad75aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224142235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2224142235
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1009769247
Short name T258
Test name
Test status
Simulation time 135610970 ps
CPU time 1.1 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 200160 kb
Host smart-324e2f65-125f-461c-ad66-0af000c771da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009769247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1009769247
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2046531802
Short name T121
Test name
Test status
Simulation time 84773894 ps
CPU time 0.84 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 199708 kb
Host smart-9dc016b5-33a6-4d3e-8fd1-e0cc73bf1d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046531802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2046531802
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1145058502
Short name T506
Test name
Test status
Simulation time 1880090778 ps
CPU time 7.04 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:00 PM PDT 24
Peak memory 217624 kb
Host smart-ed4b2339-8603-4911-9477-35514972a004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145058502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1145058502
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2415519468
Short name T136
Test name
Test status
Simulation time 244614994 ps
CPU time 1.04 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 217568 kb
Host smart-282593f4-cb17-41b9-a0ab-21d2d687007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415519468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2415519468
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.737742809
Short name T344
Test name
Test status
Simulation time 92239550 ps
CPU time 0.75 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:52 PM PDT 24
Peak memory 199912 kb
Host smart-9fe911dc-876b-41ee-b987-09dcfdfa3876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737742809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.737742809
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3934839439
Short name T37
Test name
Test status
Simulation time 1643700685 ps
CPU time 5.92 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:00 PM PDT 24
Peak memory 200280 kb
Host smart-4d83525a-a94a-4a50-b829-4c3ef96f92a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934839439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3934839439
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.140642838
Short name T207
Test name
Test status
Simulation time 102913366 ps
CPU time 0.96 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 200172 kb
Host smart-4dc50e78-5570-481b-8dd3-5b2d88eeb3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140642838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.140642838
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3348244947
Short name T522
Test name
Test status
Simulation time 192826359 ps
CPU time 1.31 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 200352 kb
Host smart-4d32d3ea-cad0-44f3-a1a2-1f3cb7b712c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348244947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3348244947
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3023652739
Short name T482
Test name
Test status
Simulation time 5991452194 ps
CPU time 21.45 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:15 PM PDT 24
Peak memory 200472 kb
Host smart-2b9a1bef-4b0b-47bb-8888-5c01f9b262ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023652739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3023652739
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1841899502
Short name T204
Test name
Test status
Simulation time 151612911 ps
CPU time 1.8 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 200160 kb
Host smart-71dd6e8b-b058-4910-9482-757b4e76ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841899502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1841899502
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3401940459
Short name T92
Test name
Test status
Simulation time 78247711 ps
CPU time 0.82 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:52 PM PDT 24
Peak memory 200100 kb
Host smart-d02efceb-4c15-41e3-afde-6ed57dcbbaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401940459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3401940459
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3437511575
Short name T428
Test name
Test status
Simulation time 79230687 ps
CPU time 0.79 seconds
Started Jul 17 07:11:43 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 199952 kb
Host smart-9912e4f7-41a3-4b9a-ab8f-844cbaec4299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437511575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3437511575
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3968123773
Short name T39
Test name
Test status
Simulation time 1224710270 ps
CPU time 5.67 seconds
Started Jul 17 07:11:43 PM PDT 24
Finished Jul 17 07:12:02 PM PDT 24
Peak memory 217824 kb
Host smart-eb296769-83f4-475c-849a-cb5c9acede17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968123773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3968123773
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3217806721
Short name T165
Test name
Test status
Simulation time 244868538 ps
CPU time 1.17 seconds
Started Jul 17 07:11:43 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 217516 kb
Host smart-5488b637-afe0-4fe3-8ffd-510c3a60564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217806721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3217806721
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2457330694
Short name T312
Test name
Test status
Simulation time 87121418 ps
CPU time 0.78 seconds
Started Jul 17 07:11:28 PM PDT 24
Finished Jul 17 07:11:30 PM PDT 24
Peak memory 200160 kb
Host smart-ae07e6bf-ba60-4218-8b7c-e6f62895ac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457330694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2457330694
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2495385214
Short name T365
Test name
Test status
Simulation time 1761043576 ps
CPU time 6.16 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:59 PM PDT 24
Peak memory 200300 kb
Host smart-7ddde32b-bdf5-4e73-ad47-d7ecc49d25af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495385214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2495385214
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3571077159
Short name T501
Test name
Test status
Simulation time 152863852 ps
CPU time 1.09 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200024 kb
Host smart-3a85e913-bafd-4b16-8fd4-2825d8f06be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571077159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3571077159
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2362081899
Short name T245
Test name
Test status
Simulation time 110407525 ps
CPU time 1.19 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200280 kb
Host smart-36d0f0cd-67f4-4bc9-8a2e-608f020d977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362081899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2362081899
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.182306104
Short name T71
Test name
Test status
Simulation time 5314158935 ps
CPU time 17.43 seconds
Started Jul 17 07:11:43 PM PDT 24
Finished Jul 17 07:12:14 PM PDT 24
Peak memory 200480 kb
Host smart-6df89dd5-dd87-41ec-adcf-05b8482d3359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182306104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.182306104
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.311059175
Short name T539
Test name
Test status
Simulation time 159817479 ps
CPU time 1.83 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200020 kb
Host smart-f2d0a513-c8dd-4933-a9d7-1c6d722d2d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311059175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.311059175
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1357523892
Short name T423
Test name
Test status
Simulation time 148037917 ps
CPU time 1.01 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:56 PM PDT 24
Peak memory 200032 kb
Host smart-b1e97d71-7a2e-4d1b-9e71-738897613e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357523892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1357523892
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3562742162
Short name T321
Test name
Test status
Simulation time 80749610 ps
CPU time 0.78 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 199956 kb
Host smart-e95b8b63-d55f-4ccd-a2a4-d1e945702ab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562742162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3562742162
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3156361624
Short name T250
Test name
Test status
Simulation time 2187467039 ps
CPU time 8.92 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 217872 kb
Host smart-fd6fd185-5265-4260-83dd-1ff0938de2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156361624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3156361624
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2391792955
Short name T263
Test name
Test status
Simulation time 245109157 ps
CPU time 1.09 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:50 PM PDT 24
Peak memory 217520 kb
Host smart-9313a105-95da-4b81-9426-dbf7133aec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391792955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2391792955
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2614283039
Short name T450
Test name
Test status
Simulation time 83700963 ps
CPU time 0.75 seconds
Started Jul 17 07:11:43 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 199980 kb
Host smart-8b666795-bc1d-4242-89fc-890e666768dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614283039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2614283039
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1566673405
Short name T427
Test name
Test status
Simulation time 979747218 ps
CPU time 4.81 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:12:00 PM PDT 24
Peak memory 200592 kb
Host smart-24875eeb-9cd2-43eb-8fff-7c630e735f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566673405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1566673405
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.508657647
Short name T211
Test name
Test status
Simulation time 141151919 ps
CPU time 1.09 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 200168 kb
Host smart-2e382c92-5ee7-4677-9bd3-ed861994298f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508657647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.508657647
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2822056034
Short name T315
Test name
Test status
Simulation time 114235501 ps
CPU time 1.12 seconds
Started Jul 17 07:11:43 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 200356 kb
Host smart-82344dc8-3a73-4c3d-936d-bfb40a21305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822056034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2822056034
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.990669483
Short name T157
Test name
Test status
Simulation time 4654160224 ps
CPU time 17.43 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 200468 kb
Host smart-23f691ea-1b02-4732-9eb2-b55db8ca0ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990669483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.990669483
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3492598149
Short name T158
Test name
Test status
Simulation time 296237060 ps
CPU time 1.9 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 208352 kb
Host smart-e615a79c-1d50-4f82-91f5-7fb1023f93f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492598149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3492598149
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3037796343
Short name T346
Test name
Test status
Simulation time 77359147 ps
CPU time 0.75 seconds
Started Jul 17 07:11:44 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 200172 kb
Host smart-fbde776d-e8cf-4a42-aeca-cd522a3f5f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037796343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3037796343
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3139803906
Short name T454
Test name
Test status
Simulation time 65954578 ps
CPU time 0.77 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 199920 kb
Host smart-2c0eb204-fb45-4a53-b7ec-c3585aaa1751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139803906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3139803906
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.400105155
Short name T27
Test name
Test status
Simulation time 2322463718 ps
CPU time 8.2 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:59 PM PDT 24
Peak memory 218060 kb
Host smart-724a22f7-10e4-43ea-80bf-a3bd4de9cf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400105155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.400105155
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2307978246
Short name T508
Test name
Test status
Simulation time 244541648 ps
CPU time 1.04 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 217664 kb
Host smart-eba8fd89-6448-44a3-8d4b-a58538bc6d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307978246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2307978246
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2264240404
Short name T153
Test name
Test status
Simulation time 74830003 ps
CPU time 0.72 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 199976 kb
Host smart-254ba636-3cae-4e03-9a42-b40154ea77d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264240404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2264240404
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.13479141
Short name T69
Test name
Test status
Simulation time 807827392 ps
CPU time 4.12 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:52 PM PDT 24
Peak memory 200476 kb
Host smart-abdc7219-31d0-4872-aa5a-f46b9f08b023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13479141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.13479141
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4160414951
Short name T370
Test name
Test status
Simulation time 141488732 ps
CPU time 1.1 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:52 PM PDT 24
Peak memory 200140 kb
Host smart-daa54b16-1e28-4e72-b59a-21e0f3959c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160414951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4160414951
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.304158556
Short name T49
Test name
Test status
Simulation time 205908550 ps
CPU time 1.38 seconds
Started Jul 17 07:11:32 PM PDT 24
Finished Jul 17 07:11:33 PM PDT 24
Peak memory 200340 kb
Host smart-67df4795-a7ff-4e24-8025-c96f63e22be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304158556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.304158556
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1720415519
Short name T47
Test name
Test status
Simulation time 4283115238 ps
CPU time 16.73 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:12:09 PM PDT 24
Peak memory 208672 kb
Host smart-56b2d40a-2850-4f67-a04c-da4d52c4f23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720415519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1720415519
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2727620543
Short name T271
Test name
Test status
Simulation time 131866728 ps
CPU time 1.6 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 200224 kb
Host smart-d1d856d3-5b32-4e75-8ed5-5944a6279995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727620543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2727620543
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.167178344
Short name T441
Test name
Test status
Simulation time 217206114 ps
CPU time 1.35 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200152 kb
Host smart-f50ff64b-e70a-4b7e-929a-85ef38c70136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167178344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.167178344
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3337865017
Short name T459
Test name
Test status
Simulation time 61900881 ps
CPU time 0.77 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:03 PM PDT 24
Peak memory 199968 kb
Host smart-8c1a7081-1d4f-4873-bf05-bb1fe9fa61ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337865017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3337865017
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1524301912
Short name T348
Test name
Test status
Simulation time 1225533964 ps
CPU time 6.18 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:18 PM PDT 24
Peak memory 221752 kb
Host smart-3b63d303-a848-47e7-812f-1a0c10cc78eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524301912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1524301912
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3668055050
Short name T294
Test name
Test status
Simulation time 244148665 ps
CPU time 1.19 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 217516 kb
Host smart-ad915bbd-bbfb-48aa-b899-ab3208700fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668055050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3668055050
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3122155617
Short name T349
Test name
Test status
Simulation time 110491712 ps
CPU time 0.78 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:08 PM PDT 24
Peak memory 199964 kb
Host smart-50b59fed-0855-4320-a9ba-ca9c89044bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122155617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3122155617
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3660960670
Short name T466
Test name
Test status
Simulation time 2007671630 ps
CPU time 7.98 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:16 PM PDT 24
Peak memory 199196 kb
Host smart-539a63d5-d471-4195-b996-128583c2d283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660960670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3660960670
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1747373657
Short name T63
Test name
Test status
Simulation time 8489682877 ps
CPU time 12.41 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:22 PM PDT 24
Peak memory 217744 kb
Host smart-c0927335-9397-41cc-be57-787aca31fd28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747373657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1747373657
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2592207773
Short name T412
Test name
Test status
Simulation time 105816648 ps
CPU time 1.05 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 200140 kb
Host smart-dad16318-1909-477e-839c-c66dcec3c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592207773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2592207773
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1033546813
Short name T406
Test name
Test status
Simulation time 199699296 ps
CPU time 1.43 seconds
Started Jul 17 07:11:02 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 200356 kb
Host smart-7fa87cd4-ec5f-43aa-9c9c-8d54f4b55408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033546813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1033546813
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.742118284
Short name T394
Test name
Test status
Simulation time 4355570474 ps
CPU time 15.83 seconds
Started Jul 17 07:12:10 PM PDT 24
Finished Jul 17 07:12:26 PM PDT 24
Peak memory 200496 kb
Host smart-f8c802d6-0e31-4f22-9f32-da5e533c1cc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742118284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.742118284
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.172765959
Short name T93
Test name
Test status
Simulation time 417156115 ps
CPU time 2.14 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:08 PM PDT 24
Peak memory 208356 kb
Host smart-a39b3fe2-af34-498d-8cbf-0626172fd100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172765959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.172765959
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3309463260
Short name T253
Test name
Test status
Simulation time 261111564 ps
CPU time 1.36 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 200144 kb
Host smart-4729d4ef-09dd-444e-90a5-f12d9ff9042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309463260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3309463260
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3439717003
Short name T360
Test name
Test status
Simulation time 70155907 ps
CPU time 0.74 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 199932 kb
Host smart-1c98b094-946d-443f-9835-c5de96a96dcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439717003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3439717003
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.52834240
Short name T242
Test name
Test status
Simulation time 2351040862 ps
CPU time 8.64 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:02 PM PDT 24
Peak memory 221780 kb
Host smart-0a507d65-805c-4691-9a27-e768b75a7682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52834240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.52834240
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.249864171
Short name T161
Test name
Test status
Simulation time 243498733 ps
CPU time 1.03 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 217508 kb
Host smart-76ad5568-bd36-468d-89b5-3136f12418b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249864171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.249864171
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3712247590
Short name T16
Test name
Test status
Simulation time 164791355 ps
CPU time 0.9 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:50 PM PDT 24
Peak memory 199968 kb
Host smart-eca4c632-c5c8-4a46-b14e-a9d4461ba41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712247590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3712247590
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3418622425
Short name T230
Test name
Test status
Simulation time 1892628497 ps
CPU time 7.09 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:59 PM PDT 24
Peak memory 200424 kb
Host smart-d4c5a676-8ce3-4476-ab62-f1a78052aed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418622425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3418622425
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1533774023
Short name T254
Test name
Test status
Simulation time 144121992 ps
CPU time 1.08 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 200096 kb
Host smart-bc7f96a8-49ee-4637-9104-f3b6eb75d2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533774023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1533774023
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2451772230
Short name T286
Test name
Test status
Simulation time 198239143 ps
CPU time 1.3 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200524 kb
Host smart-c9469477-9a7e-4b41-b12f-478410d21035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451772230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2451772230
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2814521220
Short name T120
Test name
Test status
Simulation time 10018944831 ps
CPU time 31.6 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:26 PM PDT 24
Peak memory 208724 kb
Host smart-1e969a5e-5474-4db4-8320-821c9d4c0bf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814521220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2814521220
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1521797607
Short name T381
Test name
Test status
Simulation time 142787541 ps
CPU time 1.68 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 200140 kb
Host smart-5d749b44-b4d1-45b0-9f8c-9cbedd8a34d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521797607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1521797607
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3383997503
Short name T483
Test name
Test status
Simulation time 69815236 ps
CPU time 0.75 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200160 kb
Host smart-fd804629-075e-41ea-8230-2dce565affc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383997503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3383997503
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2906621212
Short name T199
Test name
Test status
Simulation time 77901790 ps
CPU time 0.81 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:55 PM PDT 24
Peak memory 199816 kb
Host smart-e15e84fc-47da-49be-a4e4-7d2e1fed37b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906621212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2906621212
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1287667696
Short name T41
Test name
Test status
Simulation time 1912665912 ps
CPU time 7.43 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:12:03 PM PDT 24
Peak memory 217668 kb
Host smart-5088d93c-09d7-4842-8429-b449d0e92336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287667696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1287667696
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2272231945
Short name T141
Test name
Test status
Simulation time 244402897 ps
CPU time 1.13 seconds
Started Jul 17 07:11:29 PM PDT 24
Finished Jul 17 07:11:31 PM PDT 24
Peak memory 217760 kb
Host smart-09dbc593-0b9b-4d0b-a532-53f4d4a9b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272231945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2272231945
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2501678673
Short name T170
Test name
Test status
Simulation time 208541178 ps
CPU time 0.88 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 199832 kb
Host smart-21ea8709-85d0-440f-a449-aff9e9dee627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501678673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2501678673
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2275843839
Short name T172
Test name
Test status
Simulation time 1691255697 ps
CPU time 6.51 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:12:01 PM PDT 24
Peak memory 200356 kb
Host smart-12037f0f-e4d4-473d-8ea5-5b418ddda1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275843839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2275843839
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1697425011
Short name T151
Test name
Test status
Simulation time 171662677 ps
CPU time 1.15 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:56 PM PDT 24
Peak memory 199876 kb
Host smart-ccb2fcbe-20a2-4c98-9039-c653d3ace3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697425011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1697425011
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3026376451
Short name T194
Test name
Test status
Simulation time 199065565 ps
CPU time 1.39 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:54 PM PDT 24
Peak memory 200196 kb
Host smart-e53046dd-4af7-413c-8be4-93ed7bcd84fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026376451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3026376451
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3932421421
Short name T338
Test name
Test status
Simulation time 10685524202 ps
CPU time 39.28 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:12:32 PM PDT 24
Peak memory 200364 kb
Host smart-b7ddc088-9a41-4745-a056-8bc6a784eedb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932421421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3932421421
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2743014107
Short name T97
Test name
Test status
Simulation time 477028510 ps
CPU time 2.74 seconds
Started Jul 17 07:11:40 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200156 kb
Host smart-7b0df52e-214f-497d-aae8-fb04af0c61c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743014107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2743014107
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3928214539
Short name T38
Test name
Test status
Simulation time 168275297 ps
CPU time 1.22 seconds
Started Jul 17 07:11:39 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 200336 kb
Host smart-9d5831d0-9839-4202-b751-3d3d3b7834c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928214539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3928214539
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2867852616
Short name T448
Test name
Test status
Simulation time 85289970 ps
CPU time 0.78 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 199724 kb
Host smart-ba1c46a4-0751-41fa-8cc7-9cdda390365a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867852616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2867852616
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2793043691
Short name T300
Test name
Test status
Simulation time 1222831035 ps
CPU time 5.58 seconds
Started Jul 17 07:11:44 PM PDT 24
Finished Jul 17 07:12:03 PM PDT 24
Peak memory 217480 kb
Host smart-3f1095f0-2c5b-40fc-849d-2a56edf3d098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793043691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2793043691
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3399365666
Short name T220
Test name
Test status
Simulation time 243622628 ps
CPU time 1.1 seconds
Started Jul 17 07:11:44 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 217540 kb
Host smart-6c46799c-c860-48b2-b4dc-583001cdb09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399365666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3399365666
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3990222277
Short name T408
Test name
Test status
Simulation time 185743186 ps
CPU time 0.87 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 199968 kb
Host smart-a1bcf638-8d1c-4a27-910d-1615f32d00d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990222277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3990222277
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.632793688
Short name T385
Test name
Test status
Simulation time 1161878573 ps
CPU time 5.28 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:12:01 PM PDT 24
Peak memory 200320 kb
Host smart-2e2b6490-29c2-4585-ad8d-538e8cba6ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632793688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.632793688
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2579249119
Short name T516
Test name
Test status
Simulation time 108654472 ps
CPU time 0.96 seconds
Started Jul 17 07:11:44 PM PDT 24
Finished Jul 17 07:11:58 PM PDT 24
Peak memory 200164 kb
Host smart-d0f23d23-aafe-4dfc-819a-b79ff3c14658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579249119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2579249119
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.170162274
Short name T90
Test name
Test status
Simulation time 198072591 ps
CPU time 1.31 seconds
Started Jul 17 07:11:41 PM PDT 24
Finished Jul 17 07:11:56 PM PDT 24
Peak memory 200528 kb
Host smart-7cf3e628-f1a4-4d59-8cfe-f4f7d0191f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170162274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.170162274
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3975074573
Short name T213
Test name
Test status
Simulation time 8084587726 ps
CPU time 35.38 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:12:23 PM PDT 24
Peak memory 200476 kb
Host smart-3d692b63-2c17-434f-8d51-0c3b3268ec8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975074573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3975074573
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.790431302
Short name T352
Test name
Test status
Simulation time 360324546 ps
CPU time 2.35 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 200112 kb
Host smart-c3d37865-e33d-43cd-ab62-3401433ed6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790431302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.790431302
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3791076089
Short name T499
Test name
Test status
Simulation time 160981924 ps
CPU time 1.2 seconds
Started Jul 17 07:11:42 PM PDT 24
Finished Jul 17 07:11:57 PM PDT 24
Peak memory 200320 kb
Host smart-bd9fb73b-5893-42cd-ae1c-0368c46aa7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791076089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3791076089
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.897513400
Short name T393
Test name
Test status
Simulation time 71236008 ps
CPU time 0.79 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 199952 kb
Host smart-1836daab-b1ce-4c97-a241-cf0ebe9229e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897513400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.897513400
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2658837805
Short name T290
Test name
Test status
Simulation time 1227951387 ps
CPU time 5.5 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 217712 kb
Host smart-9ebe49ac-a034-4e71-8057-abdc8a992f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658837805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2658837805
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3102980445
Short name T89
Test name
Test status
Simulation time 244407657 ps
CPU time 1.02 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 217516 kb
Host smart-e43c075b-6ff4-4869-ace4-d1351fab7ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102980445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3102980445
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.551309820
Short name T399
Test name
Test status
Simulation time 122531555 ps
CPU time 0.8 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:42 PM PDT 24
Peak memory 199972 kb
Host smart-1ad79f41-1886-40af-8151-a06cfd389110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551309820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.551309820
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.587123
Short name T331
Test name
Test status
Simulation time 797819831 ps
CPU time 4.09 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:52 PM PDT 24
Peak memory 200428 kb
Host smart-ee4ffbbf-5d98-4a76-a6c2-81967d2aff28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.587123
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2570271846
Short name T255
Test name
Test status
Simulation time 153911241 ps
CPU time 1.07 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 200152 kb
Host smart-324eb19b-cad1-4b28-b124-cb86ced11ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570271846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2570271846
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2743175239
Short name T480
Test name
Test status
Simulation time 186987811 ps
CPU time 1.43 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200356 kb
Host smart-0a78b66e-e2d8-4b93-9231-56dcc5235769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743175239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2743175239
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.189316821
Short name T99
Test name
Test status
Simulation time 11140570024 ps
CPU time 36.56 seconds
Started Jul 17 07:11:38 PM PDT 24
Finished Jul 17 07:12:26 PM PDT 24
Peak memory 208676 kb
Host smart-894fb664-4a2f-4d62-91c6-804098f100a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189316821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.189316821
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1231282768
Short name T323
Test name
Test status
Simulation time 513875122 ps
CPU time 2.6 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 199940 kb
Host smart-4af74475-76a0-4ca9-a9b1-9bf1d0dfad11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231282768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1231282768
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.4124069037
Short name T479
Test name
Test status
Simulation time 76655018 ps
CPU time 0.8 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:46 PM PDT 24
Peak memory 200132 kb
Host smart-bf9eb7c5-07e9-4d0e-9183-f489ae294060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124069037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.4124069037
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3519633336
Short name T437
Test name
Test status
Simulation time 88332880 ps
CPU time 0.82 seconds
Started Jul 17 07:13:02 PM PDT 24
Finished Jul 17 07:13:05 PM PDT 24
Peak memory 199876 kb
Host smart-3eee0201-f06c-4ec8-a5f1-21a0b02906a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519633336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3519633336
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1096812109
Short name T373
Test name
Test status
Simulation time 1900925865 ps
CPU time 7.47 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:17 PM PDT 24
Peak memory 217804 kb
Host smart-6c97e1e9-e989-423d-8a64-46fa222ffce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096812109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1096812109
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2159885231
Short name T70
Test name
Test status
Simulation time 244330748 ps
CPU time 1.09 seconds
Started Jul 17 07:13:02 PM PDT 24
Finished Jul 17 07:13:04 PM PDT 24
Peak memory 217452 kb
Host smart-e3776334-16ff-43f2-8102-1e4f52da2ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159885231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2159885231
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2496102779
Short name T442
Test name
Test status
Simulation time 224482436 ps
CPU time 0.87 seconds
Started Jul 17 07:13:03 PM PDT 24
Finished Jul 17 07:13:06 PM PDT 24
Peak memory 199968 kb
Host smart-e02f9c47-b1e9-420f-ba34-052db9a9ee52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496102779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2496102779
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.373358766
Short name T289
Test name
Test status
Simulation time 1807505643 ps
CPU time 7.1 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:18 PM PDT 24
Peak memory 200408 kb
Host smart-10aa8277-f3f6-4522-a7d0-4f93406c9dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373358766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.373358766
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.283405305
Short name T410
Test name
Test status
Simulation time 103244463 ps
CPU time 1.02 seconds
Started Jul 17 07:13:06 PM PDT 24
Finished Jul 17 07:13:19 PM PDT 24
Peak memory 200148 kb
Host smart-e3f81430-856a-40eb-a782-6bc1acc7b559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283405305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.283405305
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.236251457
Short name T333
Test name
Test status
Simulation time 196116924 ps
CPU time 1.33 seconds
Started Jul 17 07:11:37 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200364 kb
Host smart-b80f9816-a76f-42ff-872d-60ae75f34419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236251457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.236251457
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3935241862
Short name T376
Test name
Test status
Simulation time 326452670 ps
CPU time 2.09 seconds
Started Jul 17 07:13:01 PM PDT 24
Finished Jul 17 07:13:05 PM PDT 24
Peak memory 200160 kb
Host smart-19adf9ea-2677-4fab-a7dd-49db8914797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935241862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3935241862
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.413438588
Short name T511
Test name
Test status
Simulation time 158457280 ps
CPU time 1.11 seconds
Started Jul 17 07:13:01 PM PDT 24
Finished Jul 17 07:13:03 PM PDT 24
Peak memory 200136 kb
Host smart-5f5a9d0a-c15e-45ce-b616-2f811202003a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413438588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.413438588
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3290620637
Short name T295
Test name
Test status
Simulation time 105874843 ps
CPU time 0.93 seconds
Started Jul 17 07:13:01 PM PDT 24
Finished Jul 17 07:13:03 PM PDT 24
Peak memory 199948 kb
Host smart-0665189d-a7d1-492c-9005-8260fb7f4289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290620637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3290620637
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3432867444
Short name T44
Test name
Test status
Simulation time 1900802691 ps
CPU time 6.73 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:16 PM PDT 24
Peak memory 217624 kb
Host smart-61d1a434-aa10-477d-bb2c-f2267405c8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432867444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3432867444
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2736830889
Short name T395
Test name
Test status
Simulation time 244820425 ps
CPU time 1.06 seconds
Started Jul 17 07:13:02 PM PDT 24
Finished Jul 17 07:13:04 PM PDT 24
Peak memory 217532 kb
Host smart-ac43bbc0-03dc-4a03-861d-d51273a6d48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736830889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2736830889
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.572175570
Short name T530
Test name
Test status
Simulation time 158858615 ps
CPU time 0.81 seconds
Started Jul 17 07:13:06 PM PDT 24
Finished Jul 17 07:13:17 PM PDT 24
Peak memory 199972 kb
Host smart-d0802b3e-bcf7-4027-89e1-361868f2eab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572175570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.572175570
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.951524415
Short name T417
Test name
Test status
Simulation time 1350741379 ps
CPU time 5.54 seconds
Started Jul 17 07:13:02 PM PDT 24
Finished Jul 17 07:13:09 PM PDT 24
Peak memory 200420 kb
Host smart-84f03c35-7439-440f-a82e-11f5603c94b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951524415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.951524415
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.545261362
Short name T149
Test name
Test status
Simulation time 142068076 ps
CPU time 1.09 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:08 PM PDT 24
Peak memory 200108 kb
Host smart-cf4203f5-1d5b-45e7-8029-6f069bfd3426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545261362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.545261362
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.51843491
Short name T388
Test name
Test status
Simulation time 197486330 ps
CPU time 1.52 seconds
Started Jul 17 07:13:00 PM PDT 24
Finished Jul 17 07:13:02 PM PDT 24
Peak memory 200364 kb
Host smart-0f8a56a0-4cad-4f5c-a858-a2f9a3b2e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51843491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.51843491
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.986469866
Short name T396
Test name
Test status
Simulation time 7265962315 ps
CPU time 23.94 seconds
Started Jul 17 07:13:00 PM PDT 24
Finished Jul 17 07:13:24 PM PDT 24
Peak memory 210632 kb
Host smart-52bfc0f7-444c-46e7-acfa-71ddf1edd405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986469866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.986469866
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3991026730
Short name T318
Test name
Test status
Simulation time 270157103 ps
CPU time 1.85 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:14 PM PDT 24
Peak memory 200176 kb
Host smart-f3ecce42-c7bb-44f6-b731-e706347ce9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991026730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3991026730
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1127725411
Short name T313
Test name
Test status
Simulation time 68772066 ps
CPU time 0.83 seconds
Started Jul 17 07:13:02 PM PDT 24
Finished Jul 17 07:13:04 PM PDT 24
Peak memory 200132 kb
Host smart-ad54fa73-21b4-44c2-846a-e638547d3564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127725411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1127725411
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.72681190
Short name T357
Test name
Test status
Simulation time 63908199 ps
CPU time 0.71 seconds
Started Jul 17 07:13:08 PM PDT 24
Finished Jul 17 07:13:25 PM PDT 24
Peak memory 199960 kb
Host smart-4367c0e6-250f-48f5-b454-3337a5df5862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72681190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.72681190
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3052783482
Short name T447
Test name
Test status
Simulation time 2188455009 ps
CPU time 7.88 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:17 PM PDT 24
Peak memory 221672 kb
Host smart-eee32d75-605e-40db-b8c2-4e99ac79adab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052783482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3052783482
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1515796646
Short name T137
Test name
Test status
Simulation time 244914775 ps
CPU time 1.03 seconds
Started Jul 17 07:13:03 PM PDT 24
Finished Jul 17 07:13:06 PM PDT 24
Peak memory 217432 kb
Host smart-60460c19-7374-42a4-b30c-ddceaf2e6417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515796646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1515796646
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3123608711
Short name T177
Test name
Test status
Simulation time 91987467 ps
CPU time 0.73 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:07 PM PDT 24
Peak memory 199968 kb
Host smart-af82061d-2cda-4cb8-a09a-cf9b9174b55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123608711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3123608711
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1993896051
Short name T354
Test name
Test status
Simulation time 1468541031 ps
CPU time 6.06 seconds
Started Jul 17 07:13:08 PM PDT 24
Finished Jul 17 07:13:31 PM PDT 24
Peak memory 200424 kb
Host smart-e88929cb-f691-4aa0-9acc-2ab2c0823802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993896051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1993896051
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2136152972
Short name T202
Test name
Test status
Simulation time 107619623 ps
CPU time 0.99 seconds
Started Jul 17 07:13:01 PM PDT 24
Finished Jul 17 07:13:03 PM PDT 24
Peak memory 200104 kb
Host smart-639ad6a0-8293-48bd-b077-4b70860f9ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136152972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2136152972
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2311372583
Short name T327
Test name
Test status
Simulation time 111150065 ps
CPU time 1.17 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:10 PM PDT 24
Peak memory 200352 kb
Host smart-7b5b145b-82bc-4954-9b5c-a90ed1e73882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311372583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2311372583
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1784401459
Short name T197
Test name
Test status
Simulation time 4635948822 ps
CPU time 16.88 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:26 PM PDT 24
Peak memory 200476 kb
Host smart-91fdb350-ac52-4081-8cf6-21437e9c27a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784401459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1784401459
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3214275545
Short name T341
Test name
Test status
Simulation time 268443607 ps
CPU time 1.87 seconds
Started Jul 17 07:13:03 PM PDT 24
Finished Jul 17 07:13:08 PM PDT 24
Peak memory 200168 kb
Host smart-b80a6d5c-f191-44a2-94c8-5397f52beb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214275545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3214275545
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.255665848
Short name T502
Test name
Test status
Simulation time 124650661 ps
CPU time 1.01 seconds
Started Jul 17 07:13:07 PM PDT 24
Finished Jul 17 07:13:21 PM PDT 24
Peak memory 200144 kb
Host smart-df939e38-7750-4e7a-941e-f5f2343d7e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255665848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.255665848
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1945427757
Short name T292
Test name
Test status
Simulation time 58402863 ps
CPU time 0.76 seconds
Started Jul 17 07:13:03 PM PDT 24
Finished Jul 17 07:13:05 PM PDT 24
Peak memory 199876 kb
Host smart-9915fc73-b6a9-4a91-817e-506dc3b004c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945427757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1945427757
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1102473490
Short name T372
Test name
Test status
Simulation time 1228467188 ps
CPU time 5.44 seconds
Started Jul 17 07:13:00 PM PDT 24
Finished Jul 17 07:13:06 PM PDT 24
Peak memory 221968 kb
Host smart-cbf47296-dfc5-4971-85eb-8475194b50ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102473490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1102473490
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4009663705
Short name T322
Test name
Test status
Simulation time 244042352 ps
CPU time 1.08 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:08 PM PDT 24
Peak memory 217572 kb
Host smart-eaa94e55-afc4-46df-bdf4-59742e0c7350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009663705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4009663705
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3229501213
Short name T152
Test name
Test status
Simulation time 125624114 ps
CPU time 0.79 seconds
Started Jul 17 07:13:03 PM PDT 24
Finished Jul 17 07:13:07 PM PDT 24
Peak memory 199964 kb
Host smart-026f696d-2fe0-4f54-8842-1cabda9a78d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229501213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3229501213
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.481072239
Short name T309
Test name
Test status
Simulation time 871241555 ps
CPU time 4.4 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:17 PM PDT 24
Peak memory 200460 kb
Host smart-06b567f4-c431-4fec-a99d-16607ac9ef24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481072239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.481072239
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3235108300
Short name T145
Test name
Test status
Simulation time 113738623 ps
CPU time 1.02 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:10 PM PDT 24
Peak memory 199996 kb
Host smart-e4db630c-bcee-496a-88cf-1dadc6074789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235108300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3235108300
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.837215855
Short name T8
Test name
Test status
Simulation time 259693631 ps
CPU time 1.55 seconds
Started Jul 17 07:13:08 PM PDT 24
Finished Jul 17 07:13:26 PM PDT 24
Peak memory 200356 kb
Host smart-47f75fc0-d840-437b-b47d-c2c713760407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837215855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.837215855
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1154904459
Short name T232
Test name
Test status
Simulation time 3624890196 ps
CPU time 16.67 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:27 PM PDT 24
Peak memory 208676 kb
Host smart-c6c3d8b8-e70d-44f4-86de-63774d83f008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154904459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1154904459
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.4238923482
Short name T505
Test name
Test status
Simulation time 339944513 ps
CPU time 1.94 seconds
Started Jul 17 07:13:09 PM PDT 24
Finished Jul 17 07:13:28 PM PDT 24
Peak memory 200168 kb
Host smart-14275b2e-3e76-40e3-a11e-6c8efac852dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238923482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.4238923482
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.4177132852
Short name T443
Test name
Test status
Simulation time 119616033 ps
CPU time 1 seconds
Started Jul 17 07:13:02 PM PDT 24
Finished Jul 17 07:13:04 PM PDT 24
Peak memory 200068 kb
Host smart-29578013-d859-4915-86f3-8e67c89c9a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177132852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.4177132852
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1047398786
Short name T368
Test name
Test status
Simulation time 83526273 ps
CPU time 0.82 seconds
Started Jul 17 07:13:01 PM PDT 24
Finished Jul 17 07:13:03 PM PDT 24
Peak memory 200188 kb
Host smart-74720d33-9c2c-4073-9cbf-27d152178ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047398786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1047398786
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4046535591
Short name T68
Test name
Test status
Simulation time 243609749 ps
CPU time 1.06 seconds
Started Jul 17 07:16:09 PM PDT 24
Finished Jul 17 07:16:11 PM PDT 24
Peak memory 217528 kb
Host smart-b930158e-d6f1-4521-a569-bcd249fd60e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046535591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.4046535591
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4013546677
Short name T205
Test name
Test status
Simulation time 179238047 ps
CPU time 0.89 seconds
Started Jul 17 07:13:02 PM PDT 24
Finished Jul 17 07:13:04 PM PDT 24
Peak memory 199916 kb
Host smart-31c28fa0-820e-4f52-a971-381c0c58de1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013546677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4013546677
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1008949150
Short name T497
Test name
Test status
Simulation time 1243745217 ps
CPU time 5.41 seconds
Started Jul 17 07:13:02 PM PDT 24
Finished Jul 17 07:13:09 PM PDT 24
Peak memory 200412 kb
Host smart-0b49ae40-549d-49d1-bf1b-cffb890d161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008949150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1008949150
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3442554491
Short name T439
Test name
Test status
Simulation time 111703733 ps
CPU time 0.98 seconds
Started Jul 17 07:13:00 PM PDT 24
Finished Jul 17 07:13:01 PM PDT 24
Peak memory 200156 kb
Host smart-80a04e1d-677a-4994-a715-5e9e4cf39c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442554491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3442554491
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3368029868
Short name T384
Test name
Test status
Simulation time 196535352 ps
CPU time 1.43 seconds
Started Jul 17 07:13:06 PM PDT 24
Finished Jul 17 07:13:18 PM PDT 24
Peak memory 200344 kb
Host smart-3c52d7dc-e7b2-4f79-a79a-153740a6dde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368029868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3368029868
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.64741077
Short name T287
Test name
Test status
Simulation time 5235275993 ps
CPU time 22.62 seconds
Started Jul 17 07:13:02 PM PDT 24
Finished Jul 17 07:13:26 PM PDT 24
Peak memory 208720 kb
Host smart-5696b26b-177f-403a-bea5-e82a42dcdb40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64741077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.64741077
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.4179746841
Short name T336
Test name
Test status
Simulation time 414233614 ps
CPU time 2.23 seconds
Started Jul 17 07:13:01 PM PDT 24
Finished Jul 17 07:13:04 PM PDT 24
Peak memory 208348 kb
Host smart-c01f741d-d020-4961-beda-38df02258d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179746841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4179746841
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4032486836
Short name T168
Test name
Test status
Simulation time 67789531 ps
CPU time 0.77 seconds
Started Jul 17 07:13:07 PM PDT 24
Finished Jul 17 07:13:23 PM PDT 24
Peak memory 200140 kb
Host smart-291dce94-9ef6-480e-a1b1-6a59bef41990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032486836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4032486836
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3049632612
Short name T247
Test name
Test status
Simulation time 85272121 ps
CPU time 0.79 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:12 PM PDT 24
Peak memory 199948 kb
Host smart-3135fdea-7c71-4148-ab72-de0568f18e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049632612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3049632612
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.568763524
Short name T359
Test name
Test status
Simulation time 2345180943 ps
CPU time 8.04 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:17 PM PDT 24
Peak memory 217796 kb
Host smart-ebce848b-1acb-40e3-b5bb-49dfffa1b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568763524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.568763524
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.607176035
Short name T460
Test name
Test status
Simulation time 244239662 ps
CPU time 1.04 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:10 PM PDT 24
Peak memory 217500 kb
Host smart-a1f318b9-0c6c-47b7-8690-9f1320badd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607176035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.607176035
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1337978202
Short name T520
Test name
Test status
Simulation time 195288624 ps
CPU time 0.93 seconds
Started Jul 17 07:13:06 PM PDT 24
Finished Jul 17 07:13:19 PM PDT 24
Peak memory 199964 kb
Host smart-b6b20d91-3ab4-4fd3-bd49-331d77a14619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337978202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1337978202
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2621223439
Short name T252
Test name
Test status
Simulation time 1676463094 ps
CPU time 5.9 seconds
Started Jul 17 07:13:03 PM PDT 24
Finished Jul 17 07:13:11 PM PDT 24
Peak memory 200432 kb
Host smart-26483c27-0952-49e6-930a-a39ac1b405b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621223439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2621223439
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2242883288
Short name T484
Test name
Test status
Simulation time 111166017 ps
CPU time 1.02 seconds
Started Jul 17 07:13:06 PM PDT 24
Finished Jul 17 07:13:19 PM PDT 24
Peak memory 200144 kb
Host smart-082b09dc-996c-49d3-9805-621cd8b607d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242883288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2242883288
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.270816250
Short name T198
Test name
Test status
Simulation time 195207353 ps
CPU time 1.33 seconds
Started Jul 17 07:13:06 PM PDT 24
Finished Jul 17 07:13:17 PM PDT 24
Peak memory 200344 kb
Host smart-f4836cc1-59e2-481c-9c6d-05e2b83d4a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270816250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.270816250
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.4211587592
Short name T433
Test name
Test status
Simulation time 3642735047 ps
CPU time 13.31 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:19 PM PDT 24
Peak memory 200440 kb
Host smart-ef0a986f-0c7b-485d-a6c4-d0b5949275bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211587592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.4211587592
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3943680934
Short name T521
Test name
Test status
Simulation time 110531571 ps
CPU time 1.34 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:15 PM PDT 24
Peak memory 200176 kb
Host smart-cc32823c-f3ea-48b2-9613-5c8fcecad9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943680934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3943680934
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4117241306
Short name T129
Test name
Test status
Simulation time 155702593 ps
CPU time 1.24 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:12 PM PDT 24
Peak memory 200372 kb
Host smart-5b7e2120-94ae-401e-8a09-ea7f5f4e3721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117241306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4117241306
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1969956673
Short name T2
Test name
Test status
Simulation time 52486786 ps
CPU time 0.79 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 199916 kb
Host smart-920b5cc5-5b61-4942-9db2-2ced600020b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969956673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1969956673
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2773270345
Short name T33
Test name
Test status
Simulation time 2378347618 ps
CPU time 8.7 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:17 PM PDT 24
Peak memory 220584 kb
Host smart-f9567816-7188-49a9-9c04-a6ee4b448f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773270345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2773270345
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2775273153
Short name T226
Test name
Test status
Simulation time 243616773 ps
CPU time 1.12 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 217504 kb
Host smart-d13619f2-d2f8-410f-8461-52742a4f63ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775273153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2775273153
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3199706753
Short name T260
Test name
Test status
Simulation time 109830913 ps
CPU time 0.84 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:11 PM PDT 24
Peak memory 199968 kb
Host smart-3f204e8d-1d98-42a7-896b-135829403a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199706753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3199706753
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4293633359
Short name T119
Test name
Test status
Simulation time 1603242180 ps
CPU time 5.85 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:16 PM PDT 24
Peak memory 200296 kb
Host smart-65f02c04-4815-4180-b231-38435945f046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293633359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4293633359
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1646175621
Short name T62
Test name
Test status
Simulation time 9724532862 ps
CPU time 14.8 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:23 PM PDT 24
Peak memory 217096 kb
Host smart-d0a31d36-4740-4f4f-9a95-40590af93080
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646175621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1646175621
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2103797021
Short name T299
Test name
Test status
Simulation time 173916217 ps
CPU time 1.21 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:10 PM PDT 24
Peak memory 200120 kb
Host smart-713e49b0-65b5-4935-886d-c822bfaa26e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103797021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2103797021
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.250989155
Short name T175
Test name
Test status
Simulation time 117649060 ps
CPU time 1.19 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 200364 kb
Host smart-2b35020b-9a82-414f-9fb4-3f16e57d78a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250989155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.250989155
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1382868614
Short name T284
Test name
Test status
Simulation time 5586210286 ps
CPU time 17.71 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:27 PM PDT 24
Peak memory 200500 kb
Host smart-ab7b18a3-7b53-4b90-8b96-c52b5498c11e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382868614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1382868614
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3651123958
Short name T166
Test name
Test status
Simulation time 537736069 ps
CPU time 2.72 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:13 PM PDT 24
Peak memory 200052 kb
Host smart-00f40440-9858-4e76-b7e9-2b4e47ea0130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651123958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3651123958
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2347346933
Short name T490
Test name
Test status
Simulation time 162787787 ps
CPU time 1.27 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:08 PM PDT 24
Peak memory 200356 kb
Host smart-3b2a1169-d05d-4630-8a0a-9b2f95d6a7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347346933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2347346933
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3499211330
Short name T310
Test name
Test status
Simulation time 73076114 ps
CPU time 0.78 seconds
Started Jul 17 07:13:08 PM PDT 24
Finished Jul 17 07:13:25 PM PDT 24
Peak memory 200028 kb
Host smart-4a7628d5-2116-4c64-9761-acaaf48b369c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499211330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3499211330
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3141982567
Short name T526
Test name
Test status
Simulation time 2163297873 ps
CPU time 7.92 seconds
Started Jul 17 07:13:08 PM PDT 24
Finished Jul 17 07:13:32 PM PDT 24
Peak memory 217872 kb
Host smart-1fcfa52a-75bf-4af5-8b7e-896847eb94c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141982567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3141982567
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2943042048
Short name T371
Test name
Test status
Simulation time 244694423 ps
CPU time 1.05 seconds
Started Jul 17 07:13:09 PM PDT 24
Finished Jul 17 07:13:27 PM PDT 24
Peak memory 217532 kb
Host smart-434feccd-4231-4ef4-8a5c-0448d6758587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943042048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2943042048
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3177540422
Short name T188
Test name
Test status
Simulation time 199819042 ps
CPU time 0.82 seconds
Started Jul 17 07:13:06 PM PDT 24
Finished Jul 17 07:13:20 PM PDT 24
Peak memory 199892 kb
Host smart-0eb3b03e-4ef1-48a7-afb5-b91e6257c200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177540422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3177540422
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.599343268
Short name T337
Test name
Test status
Simulation time 934172973 ps
CPU time 4.64 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:38 PM PDT 24
Peak memory 200404 kb
Host smart-a5cc12c7-c8ab-4fad-a425-f2fb7745a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599343268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.599343268
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3791225753
Short name T231
Test name
Test status
Simulation time 149994385 ps
CPU time 1.07 seconds
Started Jul 17 07:13:07 PM PDT 24
Finished Jul 17 07:13:24 PM PDT 24
Peak memory 200168 kb
Host smart-9ecdb63b-3035-4254-aef3-d38054d7f88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791225753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3791225753
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2248301093
Short name T222
Test name
Test status
Simulation time 111355023 ps
CPU time 1.15 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:13 PM PDT 24
Peak memory 200360 kb
Host smart-06d42328-9198-4706-b857-38aab005867c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248301093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2248301093
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2450876875
Short name T100
Test name
Test status
Simulation time 2656300992 ps
CPU time 12.46 seconds
Started Jul 17 07:13:09 PM PDT 24
Finished Jul 17 07:13:41 PM PDT 24
Peak memory 200460 kb
Host smart-b695e907-c18c-46f0-8867-06402186c98b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450876875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2450876875
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2429585922
Short name T278
Test name
Test status
Simulation time 275945126 ps
CPU time 1.85 seconds
Started Jul 17 07:13:08 PM PDT 24
Finished Jul 17 07:13:26 PM PDT 24
Peak memory 200072 kb
Host smart-8244faa8-2807-4dc8-9fe5-67fb1209fd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429585922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2429585922
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3021352658
Short name T227
Test name
Test status
Simulation time 155903580 ps
CPU time 1 seconds
Started Jul 17 07:13:06 PM PDT 24
Finished Jul 17 07:13:19 PM PDT 24
Peak memory 200172 kb
Host smart-a4d64f72-5aaa-45d8-89c0-26efde5b560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021352658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3021352658
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3522875103
Short name T160
Test name
Test status
Simulation time 72619467 ps
CPU time 0.78 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:33 PM PDT 24
Peak memory 199824 kb
Host smart-f3a95420-f13c-4875-a8ea-cae7c906227e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522875103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3522875103
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3734969570
Short name T35
Test name
Test status
Simulation time 2183506465 ps
CPU time 7.85 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:40 PM PDT 24
Peak memory 221776 kb
Host smart-c8350aa3-1a7e-46bc-824b-768bd742873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734969570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3734969570
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1337011638
Short name T276
Test name
Test status
Simulation time 243856860 ps
CPU time 1.05 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 217524 kb
Host smart-691c13a5-3582-4505-aa37-c48ccae7891c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337011638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1337011638
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4122121007
Short name T14
Test name
Test status
Simulation time 98286200 ps
CPU time 0.75 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 199964 kb
Host smart-f5148fbe-b83b-4889-90c7-e35d7ebad15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122121007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4122121007
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3013456351
Short name T472
Test name
Test status
Simulation time 740076472 ps
CPU time 3.84 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:39 PM PDT 24
Peak memory 200468 kb
Host smart-bb4541ec-9b63-4dd4-a284-5219248f88eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013456351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3013456351
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3583950110
Short name T233
Test name
Test status
Simulation time 136157775 ps
CPU time 1.03 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 200168 kb
Host smart-3cd0dcee-9f10-468a-9f3c-33c1f944aebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583950110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3583950110
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1268186426
Short name T95
Test name
Test status
Simulation time 202029817 ps
CPU time 1.32 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:31 PM PDT 24
Peak memory 200352 kb
Host smart-08845966-98c6-416f-98b6-39d360e407dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268186426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1268186426
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3899841556
Short name T517
Test name
Test status
Simulation time 6651994682 ps
CPU time 22.24 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:55 PM PDT 24
Peak memory 208552 kb
Host smart-842c4545-07cd-4d79-8ebc-c7122a529b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899841556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3899841556
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2730339550
Short name T451
Test name
Test status
Simulation time 386117765 ps
CPU time 2.08 seconds
Started Jul 17 07:13:09 PM PDT 24
Finished Jul 17 07:13:28 PM PDT 24
Peak memory 208428 kb
Host smart-f1385363-7db0-49b5-adf5-2511c6173570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730339550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2730339550
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3252831024
Short name T455
Test name
Test status
Simulation time 169189615 ps
CPU time 1.13 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 200160 kb
Host smart-b419fce8-a072-4170-a7db-e0895e78ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252831024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3252831024
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.576030719
Short name T326
Test name
Test status
Simulation time 70493461 ps
CPU time 0.78 seconds
Started Jul 17 07:13:23 PM PDT 24
Finished Jul 17 07:13:51 PM PDT 24
Peak memory 199928 kb
Host smart-f4fefaf5-f56d-4e2d-aefe-0178932a7898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576030719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.576030719
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2262183580
Short name T343
Test name
Test status
Simulation time 2363422908 ps
CPU time 8 seconds
Started Jul 17 07:13:12 PM PDT 24
Finished Jul 17 07:13:44 PM PDT 24
Peak memory 221852 kb
Host smart-d1f708b7-ad3a-4c6e-b521-be559f532346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262183580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2262183580
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.719812958
Short name T316
Test name
Test status
Simulation time 244582981 ps
CPU time 1.09 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:41 PM PDT 24
Peak memory 217768 kb
Host smart-b081be94-3c79-477e-9513-1ebaf3395175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719812958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.719812958
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.4122541159
Short name T11
Test name
Test status
Simulation time 110700945 ps
CPU time 0.83 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 199964 kb
Host smart-769fc152-61c8-4e4c-85ae-93530598a457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122541159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.4122541159
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3709709506
Short name T275
Test name
Test status
Simulation time 862779462 ps
CPU time 4.38 seconds
Started Jul 17 07:13:12 PM PDT 24
Finished Jul 17 07:13:41 PM PDT 24
Peak memory 200460 kb
Host smart-a42d550d-3502-4aaf-8f16-a082c1d957d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709709506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3709709506
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3008423905
Short name T178
Test name
Test status
Simulation time 148579245 ps
CPU time 1.06 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:36 PM PDT 24
Peak memory 200152 kb
Host smart-376ab87c-c343-4261-bbf2-c9a733ad2333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008423905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3008423905
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2213902685
Short name T173
Test name
Test status
Simulation time 229862007 ps
CPU time 1.33 seconds
Started Jul 17 07:13:09 PM PDT 24
Finished Jul 17 07:13:28 PM PDT 24
Peak memory 200236 kb
Host smart-e87182a2-ea73-4759-9980-7d08dd5ce763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213902685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2213902685
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3917731277
Short name T449
Test name
Test status
Simulation time 4165681837 ps
CPU time 14.91 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:56 PM PDT 24
Peak memory 200496 kb
Host smart-f96c20c8-4a97-4a4a-9450-cca1d131a405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917731277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3917731277
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3736917953
Short name T174
Test name
Test status
Simulation time 125537579 ps
CPU time 1.52 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 208416 kb
Host smart-8297f9d9-e411-4fbd-97d4-0cca763f6c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736917953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3736917953
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3957514519
Short name T282
Test name
Test status
Simulation time 188371719 ps
CPU time 1.27 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:35 PM PDT 24
Peak memory 200160 kb
Host smart-65638fc9-0353-4716-b71f-1617142cc656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957514519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3957514519
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1136893738
Short name T7
Test name
Test status
Simulation time 77616675 ps
CPU time 0.8 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:42 PM PDT 24
Peak memory 199968 kb
Host smart-b73ab7e8-505a-4747-b507-bf9f8bc0dd88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136893738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1136893738
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3846884401
Short name T1
Test name
Test status
Simulation time 1222336247 ps
CPU time 5.81 seconds
Started Jul 17 07:13:19 PM PDT 24
Finished Jul 17 07:13:53 PM PDT 24
Peak memory 217800 kb
Host smart-2e3e66e4-3c79-42fd-a3a2-fc728da1513a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846884401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3846884401
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3334455027
Short name T262
Test name
Test status
Simulation time 244238933 ps
CPU time 1 seconds
Started Jul 17 07:13:14 PM PDT 24
Finished Jul 17 07:13:43 PM PDT 24
Peak memory 217516 kb
Host smart-24c57439-0657-4a73-a91d-9decc327aeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334455027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3334455027
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.502051487
Short name T5
Test name
Test status
Simulation time 193443620 ps
CPU time 0.92 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:42 PM PDT 24
Peak memory 199960 kb
Host smart-dc2173f1-42fa-4ba5-90e9-77c19c0e7a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502051487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.502051487
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.738879342
Short name T524
Test name
Test status
Simulation time 1491877577 ps
CPU time 5.52 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:46 PM PDT 24
Peak memory 200484 kb
Host smart-be50c65c-ea40-42f4-b218-ed084e118400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738879342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.738879342
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1978334606
Short name T471
Test name
Test status
Simulation time 175022692 ps
CPU time 1.14 seconds
Started Jul 17 07:13:19 PM PDT 24
Finished Jul 17 07:13:49 PM PDT 24
Peak memory 200160 kb
Host smart-7b390746-0cea-4c39-b3d6-578c68c0b237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978334606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1978334606
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2271161302
Short name T40
Test name
Test status
Simulation time 259454126 ps
CPU time 1.52 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:42 PM PDT 24
Peak memory 200524 kb
Host smart-aed37cb2-cb7e-4299-b4b9-7476cbfd0a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271161302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2271161302
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3090870369
Short name T452
Test name
Test status
Simulation time 3626551349 ps
CPU time 13.61 seconds
Started Jul 17 07:13:25 PM PDT 24
Finished Jul 17 07:14:06 PM PDT 24
Peak memory 208708 kb
Host smart-bc76271c-2866-4b19-8357-dd9e859395e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090870369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3090870369
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.777629079
Short name T186
Test name
Test status
Simulation time 484918918 ps
CPU time 2.52 seconds
Started Jul 17 07:13:20 PM PDT 24
Finished Jul 17 07:13:51 PM PDT 24
Peak memory 200020 kb
Host smart-fde9e836-f77e-4bfa-9264-f7b260b14687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777629079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.777629079
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3292756131
Short name T225
Test name
Test status
Simulation time 188361340 ps
CPU time 1.19 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:43 PM PDT 24
Peak memory 200112 kb
Host smart-887f7071-3ccd-4dae-ad39-42b6b30d0f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292756131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3292756131
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3078527843
Short name T515
Test name
Test status
Simulation time 75449281 ps
CPU time 0.79 seconds
Started Jul 17 07:13:03 PM PDT 24
Finished Jul 17 07:13:07 PM PDT 24
Peak memory 199956 kb
Host smart-05d4bcca-d6cf-47f8-b542-74cc675ee501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078527843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3078527843
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1475183820
Short name T355
Test name
Test status
Simulation time 2166886348 ps
CPU time 7.82 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:21 PM PDT 24
Peak memory 217884 kb
Host smart-d7aa4d26-cc28-479e-9aeb-d869370cae20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475183820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1475183820
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2249931544
Short name T458
Test name
Test status
Simulation time 244664882 ps
CPU time 1.05 seconds
Started Jul 17 07:13:07 PM PDT 24
Finished Jul 17 07:13:24 PM PDT 24
Peak memory 217524 kb
Host smart-5d3d5d50-1c33-4d50-a57b-5a07546cd0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249931544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2249931544
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3625654232
Short name T17
Test name
Test status
Simulation time 177698624 ps
CPU time 0.91 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:10 PM PDT 24
Peak memory 199976 kb
Host smart-25e53370-530d-4ead-83fd-902e1b473d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625654232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3625654232
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1480762948
Short name T208
Test name
Test status
Simulation time 722324726 ps
CPU time 3.65 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:10 PM PDT 24
Peak memory 200460 kb
Host smart-51b560d6-df69-4072-9e72-65450e048943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480762948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1480762948
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1922807108
Short name T195
Test name
Test status
Simulation time 107495140 ps
CPU time 0.95 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:09 PM PDT 24
Peak memory 200104 kb
Host smart-0b934d1d-61da-4740-9e03-e3c5084c9be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922807108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1922807108
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2733667573
Short name T319
Test name
Test status
Simulation time 98233679 ps
CPU time 0.81 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:08 PM PDT 24
Peak memory 199952 kb
Host smart-e7eca3d0-59a7-47f5-9716-f9caf81a8036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733667573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2733667573
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3066872394
Short name T446
Test name
Test status
Simulation time 111992226 ps
CPU time 1.53 seconds
Started Jul 17 07:13:02 PM PDT 24
Finished Jul 17 07:13:06 PM PDT 24
Peak memory 200200 kb
Host smart-3648e016-caea-4879-98aa-c00beffbb674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066872394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3066872394
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3316142351
Short name T335
Test name
Test status
Simulation time 178648941 ps
CPU time 1.2 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:09 PM PDT 24
Peak memory 200168 kb
Host smart-22cf275d-a5a7-44ec-ae92-65030174c38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316142351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3316142351
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1261305591
Short name T135
Test name
Test status
Simulation time 68530398 ps
CPU time 0.71 seconds
Started Jul 17 07:13:08 PM PDT 24
Finished Jul 17 07:13:25 PM PDT 24
Peak memory 199952 kb
Host smart-fc7662b7-c146-4e4a-a159-dcc2d3e42f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261305591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1261305591
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.799772358
Short name T30
Test name
Test status
Simulation time 1213250869 ps
CPU time 5.45 seconds
Started Jul 17 07:13:07 PM PDT 24
Finished Jul 17 07:13:27 PM PDT 24
Peak memory 217612 kb
Host smart-cfab4877-ce67-4e1f-a216-ccd84de2b6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799772358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.799772358
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3749078524
Short name T13
Test name
Test status
Simulation time 244865060 ps
CPU time 1.02 seconds
Started Jul 17 07:13:08 PM PDT 24
Finished Jul 17 07:13:26 PM PDT 24
Peak memory 217532 kb
Host smart-0081fa5f-f535-4276-8e79-c3a25bc3a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749078524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3749078524
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3587271677
Short name T426
Test name
Test status
Simulation time 181160416 ps
CPU time 0.84 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 199976 kb
Host smart-c702a173-3e22-4a39-9eef-6adde4c655a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587271677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3587271677
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.798028641
Short name T504
Test name
Test status
Simulation time 1427657493 ps
CPU time 5.67 seconds
Started Jul 17 07:13:07 PM PDT 24
Finished Jul 17 07:13:28 PM PDT 24
Peak memory 200376 kb
Host smart-db1eaec1-ade0-44aa-88ea-9cdc44a6467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798028641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.798028641
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2912500096
Short name T281
Test name
Test status
Simulation time 181440125 ps
CPU time 1.14 seconds
Started Jul 17 07:13:08 PM PDT 24
Finished Jul 17 07:13:25 PM PDT 24
Peak memory 200164 kb
Host smart-c5aaab03-202f-4500-8c37-64e57339d0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912500096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2912500096
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1012067015
Short name T473
Test name
Test status
Simulation time 197328542 ps
CPU time 1.3 seconds
Started Jul 17 07:13:03 PM PDT 24
Finished Jul 17 07:13:07 PM PDT 24
Peak memory 200324 kb
Host smart-b2df24a9-20ec-482d-bb51-63585d928783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012067015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1012067015
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1257223138
Short name T510
Test name
Test status
Simulation time 3425557080 ps
CPU time 15.36 seconds
Started Jul 17 07:13:09 PM PDT 24
Finished Jul 17 07:13:42 PM PDT 24
Peak memory 208680 kb
Host smart-ffae410b-28b0-4104-805b-bd0da5b0db47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257223138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1257223138
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.554864153
Short name T51
Test name
Test status
Simulation time 138529274 ps
CPU time 1.76 seconds
Started Jul 17 07:13:07 PM PDT 24
Finished Jul 17 07:13:24 PM PDT 24
Peak memory 208448 kb
Host smart-af885151-c5d4-4604-a616-8609d198ece2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554864153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.554864153
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2926477381
Short name T432
Test name
Test status
Simulation time 130578204 ps
CPU time 1.02 seconds
Started Jul 17 07:13:07 PM PDT 24
Finished Jul 17 07:13:21 PM PDT 24
Peak memory 200084 kb
Host smart-ff9b1c9d-7444-4078-857f-c65a98d2a686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926477381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2926477381
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3699377439
Short name T404
Test name
Test status
Simulation time 70523144 ps
CPU time 0.72 seconds
Started Jul 17 07:13:17 PM PDT 24
Finished Jul 17 07:13:46 PM PDT 24
Peak memory 199952 kb
Host smart-0d699080-a437-4183-abe4-40ccfc9bcc01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699377439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3699377439
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.840526269
Short name T125
Test name
Test status
Simulation time 1884930637 ps
CPU time 7.3 seconds
Started Jul 17 07:13:09 PM PDT 24
Finished Jul 17 07:13:35 PM PDT 24
Peak memory 221708 kb
Host smart-1fc8dee7-a012-4384-8c0d-dc6a8ebca386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840526269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.840526269
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.4166061766
Short name T221
Test name
Test status
Simulation time 248193097 ps
CPU time 1.06 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 217400 kb
Host smart-b16e86c1-c218-41e2-9888-e3a469a8f1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166061766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.4166061766
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3572098507
Short name T217
Test name
Test status
Simulation time 88788507 ps
CPU time 0.73 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 199964 kb
Host smart-0bbb9f4e-c538-4548-933c-fb32cd169146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572098507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3572098507
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1242068807
Short name T512
Test name
Test status
Simulation time 962129714 ps
CPU time 4.86 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:38 PM PDT 24
Peak memory 200408 kb
Host smart-32348d9e-e3e8-4298-b319-26188f433a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242068807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1242068807
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.531056667
Short name T405
Test name
Test status
Simulation time 105994950 ps
CPU time 0.95 seconds
Started Jul 17 07:13:12 PM PDT 24
Finished Jul 17 07:13:37 PM PDT 24
Peak memory 200176 kb
Host smart-6b0e6ced-6d2a-4a54-9bca-d3a6c71bec5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531056667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.531056667
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3913405250
Short name T474
Test name
Test status
Simulation time 105689332 ps
CPU time 1.16 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:33 PM PDT 24
Peak memory 200400 kb
Host smart-aafe1c5e-c6b9-462b-bdb2-e095131cb59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913405250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3913405250
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.900187332
Short name T280
Test name
Test status
Simulation time 14583775542 ps
CPU time 53.71 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:14:27 PM PDT 24
Peak memory 208724 kb
Host smart-a4f2db75-2e39-4976-8a25-98938dda2a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900187332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.900187332
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3149679643
Short name T527
Test name
Test status
Simulation time 252866167 ps
CPU time 1.81 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:35 PM PDT 24
Peak memory 200148 kb
Host smart-863d85db-7e14-4afa-9331-49d2ce9cebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149679643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3149679643
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1603050087
Short name T320
Test name
Test status
Simulation time 237023638 ps
CPU time 1.41 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 200156 kb
Host smart-dd95bce1-afb3-4aeb-b901-53ccea379b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603050087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1603050087
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3403782949
Short name T467
Test name
Test status
Simulation time 67622120 ps
CPU time 0.71 seconds
Started Jul 17 07:13:12 PM PDT 24
Finished Jul 17 07:13:40 PM PDT 24
Peak memory 200128 kb
Host smart-33840ff5-cb59-459f-bd82-e379ec633cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403782949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3403782949
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3237196018
Short name T418
Test name
Test status
Simulation time 1896680552 ps
CPU time 7.06 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:48 PM PDT 24
Peak memory 218000 kb
Host smart-b2be3cf9-e6a9-48c6-b6d0-17d98a9ac5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237196018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3237196018
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1407826425
Short name T377
Test name
Test status
Simulation time 244081969 ps
CPU time 1.02 seconds
Started Jul 17 07:13:19 PM PDT 24
Finished Jul 17 07:13:49 PM PDT 24
Peak memory 217512 kb
Host smart-40bbb91a-fb6e-4dc3-b3e9-c1eb1ebe14f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407826425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1407826425
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.4065337726
Short name T477
Test name
Test status
Simulation time 215870676 ps
CPU time 0.91 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:33 PM PDT 24
Peak memory 199960 kb
Host smart-f0c8310a-002e-451b-96c1-85fcf80d8c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065337726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4065337726
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3631621655
Short name T434
Test name
Test status
Simulation time 2079723745 ps
CPU time 6.93 seconds
Started Jul 17 07:13:17 PM PDT 24
Finished Jul 17 07:13:52 PM PDT 24
Peak memory 200416 kb
Host smart-4375c2b8-33a3-43ee-9c75-5b10efb8a0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631621655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3631621655
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2195822473
Short name T243
Test name
Test status
Simulation time 177832826 ps
CPU time 1.19 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:36 PM PDT 24
Peak memory 200244 kb
Host smart-6ec90eb1-af03-4480-9bd3-1d116806cd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195822473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2195822473
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1499820197
Short name T535
Test name
Test status
Simulation time 249648488 ps
CPU time 1.45 seconds
Started Jul 17 07:13:12 PM PDT 24
Finished Jul 17 07:13:36 PM PDT 24
Peak memory 200348 kb
Host smart-95fc0fed-35ec-4f3c-b160-fc536fd3f207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499820197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1499820197
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1883515985
Short name T436
Test name
Test status
Simulation time 754777633 ps
CPU time 3.52 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:45 PM PDT 24
Peak memory 200132 kb
Host smart-8fb627dd-29b0-4a09-9da3-3ff0e81c6281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883515985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1883515985
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2323567343
Short name T353
Test name
Test status
Simulation time 314876582 ps
CPU time 2.02 seconds
Started Jul 17 07:13:10 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 200172 kb
Host smart-b1c66e50-4b11-4c61-9c75-c4c9ca2f7ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323567343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2323567343
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1662944277
Short name T238
Test name
Test status
Simulation time 120689457 ps
CPU time 1.1 seconds
Started Jul 17 07:13:11 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 200160 kb
Host smart-b468e09d-df12-4e9e-a75e-b67ac2933163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662944277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1662944277
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1882355940
Short name T131
Test name
Test status
Simulation time 103402069 ps
CPU time 0.8 seconds
Started Jul 17 07:13:14 PM PDT 24
Finished Jul 17 07:13:42 PM PDT 24
Peak memory 199940 kb
Host smart-3603ea23-60a3-40a8-b045-96d92b71f419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882355940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1882355940
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2046832195
Short name T298
Test name
Test status
Simulation time 243947936 ps
CPU time 1.14 seconds
Started Jul 17 07:13:19 PM PDT 24
Finished Jul 17 07:13:48 PM PDT 24
Peak memory 217500 kb
Host smart-dc21df61-1ab0-4153-a160-6bffc6fd84e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046832195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2046832195
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1868778003
Short name T140
Test name
Test status
Simulation time 105236135 ps
CPU time 0.75 seconds
Started Jul 17 07:13:12 PM PDT 24
Finished Jul 17 07:13:38 PM PDT 24
Peak memory 199972 kb
Host smart-d34b5a85-35f8-4101-8444-1657e218dc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868778003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1868778003
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1793435717
Short name T494
Test name
Test status
Simulation time 2031925854 ps
CPU time 6.89 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:47 PM PDT 24
Peak memory 200444 kb
Host smart-e11022b1-eab0-4a2a-8252-502438238044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793435717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1793435717
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3528126415
Short name T162
Test name
Test status
Simulation time 157734435 ps
CPU time 1.14 seconds
Started Jul 17 07:13:22 PM PDT 24
Finished Jul 17 07:13:51 PM PDT 24
Peak memory 200024 kb
Host smart-61262250-450c-4beb-beb9-27166dc97783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528126415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3528126415
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.4246594496
Short name T421
Test name
Test status
Simulation time 126149273 ps
CPU time 1.14 seconds
Started Jul 17 07:13:14 PM PDT 24
Finished Jul 17 07:13:43 PM PDT 24
Peak memory 200352 kb
Host smart-3ec5d772-f54b-44c8-b709-b20b30661ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246594496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.4246594496
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.4104215140
Short name T105
Test name
Test status
Simulation time 4890686168 ps
CPU time 23.76 seconds
Started Jul 17 07:13:26 PM PDT 24
Finished Jul 17 07:14:16 PM PDT 24
Peak memory 208660 kb
Host smart-4d8e859a-261a-44d1-9e63-6c3b12dc7b1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104215140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4104215140
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4116636693
Short name T179
Test name
Test status
Simulation time 423198112 ps
CPU time 2.18 seconds
Started Jul 17 07:13:14 PM PDT 24
Finished Jul 17 07:13:43 PM PDT 24
Peak memory 208336 kb
Host smart-436606cc-a290-436c-93c1-2d766ac74f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116636693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4116636693
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.797881469
Short name T374
Test name
Test status
Simulation time 83315076 ps
CPU time 0.8 seconds
Started Jul 17 07:13:13 PM PDT 24
Finished Jul 17 07:13:41 PM PDT 24
Peak memory 200112 kb
Host smart-f467c681-9786-4251-8069-1a8f323c4b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797881469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.797881469
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2154288292
Short name T407
Test name
Test status
Simulation time 70742784 ps
CPU time 0.77 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:08 PM PDT 24
Peak memory 199960 kb
Host smart-e87057eb-4469-48ce-9de4-7ecc50d3167b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154288292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2154288292
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3820205472
Short name T440
Test name
Test status
Simulation time 1217989674 ps
CPU time 5.45 seconds
Started Jul 17 07:13:05 PM PDT 24
Finished Jul 17 07:13:18 PM PDT 24
Peak memory 221696 kb
Host smart-5c2559e7-b8f9-4f48-8bbf-c8c8172b8897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820205472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3820205472
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1112054192
Short name T150
Test name
Test status
Simulation time 244028301 ps
CPU time 1.03 seconds
Started Jul 17 07:13:07 PM PDT 24
Finished Jul 17 07:13:21 PM PDT 24
Peak memory 217544 kb
Host smart-aa74fc63-5013-4af8-a657-d32e27738e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112054192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1112054192
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1478154274
Short name T132
Test name
Test status
Simulation time 129325312 ps
CPU time 0.79 seconds
Started Jul 17 07:13:09 PM PDT 24
Finished Jul 17 07:13:29 PM PDT 24
Peak memory 199964 kb
Host smart-1f3e9063-140f-4912-9553-905d03b6a979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478154274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1478154274
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3293616771
Short name T277
Test name
Test status
Simulation time 834822995 ps
CPU time 4.34 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:13 PM PDT 24
Peak memory 200460 kb
Host smart-2b4707d2-cf85-4f73-a2f9-1721b4725298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293616771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3293616771
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1064722476
Short name T496
Test name
Test status
Simulation time 157032940 ps
CPU time 1.19 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:08 PM PDT 24
Peak memory 200160 kb
Host smart-9f2a4bd7-9fd5-42db-97a4-111eaa89329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064722476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1064722476
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.773243662
Short name T155
Test name
Test status
Simulation time 117368581 ps
CPU time 1.16 seconds
Started Jul 17 07:13:15 PM PDT 24
Finished Jul 17 07:13:44 PM PDT 24
Peak memory 200356 kb
Host smart-2529274b-2d12-4a95-be24-9959e9597c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773243662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.773243662
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2662694357
Short name T240
Test name
Test status
Simulation time 10084481051 ps
CPU time 35.06 seconds
Started Jul 17 07:13:03 PM PDT 24
Finished Jul 17 07:13:40 PM PDT 24
Peak memory 200480 kb
Host smart-7c8b5722-fb92-4987-a4b8-5a7ae4d2031a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662694357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2662694357
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.143039837
Short name T91
Test name
Test status
Simulation time 164198949 ps
CPU time 1.26 seconds
Started Jul 17 07:13:04 PM PDT 24
Finished Jul 17 07:13:08 PM PDT 24
Peak memory 200312 kb
Host smart-0fa43389-0492-407e-9ac4-7dad2d4f1adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143039837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.143039837
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1281313529
Short name T531
Test name
Test status
Simulation time 87316996 ps
CPU time 0.84 seconds
Started Jul 17 07:10:58 PM PDT 24
Finished Jul 17 07:11:00 PM PDT 24
Peak memory 199864 kb
Host smart-c3ac8911-1daf-4963-9c68-3710edec7074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281313529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1281313529
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3745086288
Short name T356
Test name
Test status
Simulation time 1232242719 ps
CPU time 6.14 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:17 PM PDT 24
Peak memory 217868 kb
Host smart-4bf064f4-a087-465c-99c4-dbfaefb8bb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745086288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3745086288
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.437331611
Short name T73
Test name
Test status
Simulation time 244459075 ps
CPU time 1.27 seconds
Started Jul 17 07:10:59 PM PDT 24
Finished Jul 17 07:11:02 PM PDT 24
Peak memory 217508 kb
Host smart-f33e91d5-fa08-4ed0-a13f-52de66e379af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437331611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.437331611
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3337008262
Short name T12
Test name
Test status
Simulation time 133648030 ps
CPU time 0.83 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:13 PM PDT 24
Peak memory 199964 kb
Host smart-c9ff25a4-e2a4-460e-9ba8-2a0c5ce42a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337008262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3337008262
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3863022821
Short name T103
Test name
Test status
Simulation time 1101697408 ps
CPU time 5.12 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:17 PM PDT 24
Peak memory 200420 kb
Host smart-6dc46ff4-63b2-44f0-a89d-de56f3218bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863022821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3863022821
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2725157832
Short name T420
Test name
Test status
Simulation time 109198771 ps
CPU time 0.97 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:13 PM PDT 24
Peak memory 200140 kb
Host smart-ed2023c7-a761-4531-bc08-b93c3a44243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725157832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2725157832
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3905066453
Short name T264
Test name
Test status
Simulation time 187987131 ps
CPU time 1.33 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:13 PM PDT 24
Peak memory 200372 kb
Host smart-bcc6aefc-57eb-448d-a3b2-ad43bb1c955b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905066453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3905066453
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3638351891
Short name T485
Test name
Test status
Simulation time 11225126720 ps
CPU time 39.32 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:51 PM PDT 24
Peak memory 208668 kb
Host smart-b32ae7ed-a323-4597-8847-5e70e68ba0c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638351891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3638351891
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1072356690
Short name T249
Test name
Test status
Simulation time 412668578 ps
CPU time 2.27 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:14 PM PDT 24
Peak memory 200168 kb
Host smart-29d9d9a7-04df-433e-bf36-baf435c691a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072356690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1072356690
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3669351199
Short name T216
Test name
Test status
Simulation time 282654514 ps
CPU time 1.51 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:14 PM PDT 24
Peak memory 200140 kb
Host smart-63ae8c88-c276-44ac-a181-3e13efced5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669351199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3669351199
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3134599709
Short name T171
Test name
Test status
Simulation time 77321974 ps
CPU time 0.77 seconds
Started Jul 17 07:11:34 PM PDT 24
Finished Jul 17 07:11:36 PM PDT 24
Peak memory 199864 kb
Host smart-390ac1a7-db77-4930-bdbf-b63bd1c00c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134599709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3134599709
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1705719437
Short name T261
Test name
Test status
Simulation time 1908846509 ps
CPU time 6.72 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:14 PM PDT 24
Peak memory 217780 kb
Host smart-05e7e12c-d570-4f9a-9a1c-201212f2accc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705719437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1705719437
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2527194224
Short name T362
Test name
Test status
Simulation time 244985609 ps
CPU time 1.04 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:10 PM PDT 24
Peak memory 217532 kb
Host smart-a745f743-ea58-4cd8-9388-dfbd9dca9b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527194224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2527194224
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2133817871
Short name T19
Test name
Test status
Simulation time 99354959 ps
CPU time 0.81 seconds
Started Jul 17 07:10:57 PM PDT 24
Finished Jul 17 07:10:59 PM PDT 24
Peak memory 199856 kb
Host smart-d4a2cdd8-abab-45d6-93c2-5e6d70408566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133817871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2133817871
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3836198999
Short name T184
Test name
Test status
Simulation time 1607925603 ps
CPU time 6.8 seconds
Started Jul 17 07:10:58 PM PDT 24
Finished Jul 17 07:11:06 PM PDT 24
Peak memory 200400 kb
Host smart-6a94aca6-69e4-44d0-bdce-efd30bc4df17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836198999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3836198999
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.911515135
Short name T146
Test name
Test status
Simulation time 105067945 ps
CPU time 1.03 seconds
Started Jul 17 07:10:55 PM PDT 24
Finished Jul 17 07:10:58 PM PDT 24
Peak memory 200108 kb
Host smart-21d30cc3-793f-4dd1-b207-ea376f098ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911515135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.911515135
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.109586638
Short name T167
Test name
Test status
Simulation time 254858445 ps
CPU time 1.48 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:13 PM PDT 24
Peak memory 200352 kb
Host smart-b5ff9c1a-5d5a-42d1-b963-ad952ae115fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109586638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.109586638
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.114325926
Short name T306
Test name
Test status
Simulation time 7718676509 ps
CPU time 35.76 seconds
Started Jul 17 07:11:01 PM PDT 24
Finished Jul 17 07:11:39 PM PDT 24
Peak memory 208600 kb
Host smart-99d2986e-b253-4c0c-a0cb-bdf2a75ffd2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114325926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.114325926
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2179688014
Short name T464
Test name
Test status
Simulation time 372149585 ps
CPU time 2.28 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 200172 kb
Host smart-bdb676e5-4039-48f8-ac3f-f77158acc9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179688014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2179688014
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3976711889
Short name T491
Test name
Test status
Simulation time 126406167 ps
CPU time 0.92 seconds
Started Jul 17 07:10:56 PM PDT 24
Finished Jul 17 07:10:58 PM PDT 24
Peak memory 200156 kb
Host smart-ab41c0db-ac8c-48e8-8929-1e6a8ce44e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976711889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3976711889
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2368392670
Short name T425
Test name
Test status
Simulation time 81080838 ps
CPU time 0.82 seconds
Started Jul 17 07:11:33 PM PDT 24
Finished Jul 17 07:11:34 PM PDT 24
Peak memory 199964 kb
Host smart-2c0e3a69-87a6-49e0-bb4e-9bdc35a2abdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368392670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2368392670
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1240069912
Short name T291
Test name
Test status
Simulation time 1228130511 ps
CPU time 5.57 seconds
Started Jul 17 07:11:24 PM PDT 24
Finished Jul 17 07:11:30 PM PDT 24
Peak memory 217516 kb
Host smart-67a224ee-6892-4059-9bb9-85813d553e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240069912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1240069912
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4161806520
Short name T268
Test name
Test status
Simulation time 244534460 ps
CPU time 1.09 seconds
Started Jul 17 07:11:26 PM PDT 24
Finished Jul 17 07:11:28 PM PDT 24
Peak memory 217524 kb
Host smart-41c46201-57fe-4441-9da4-637c8c7153cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161806520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4161806520
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2558993292
Short name T180
Test name
Test status
Simulation time 152564681 ps
CPU time 0.83 seconds
Started Jul 17 07:11:26 PM PDT 24
Finished Jul 17 07:11:28 PM PDT 24
Peak memory 199956 kb
Host smart-8e344763-5b34-42b1-aa7a-5af61606e91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558993292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2558993292
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2796899197
Short name T21
Test name
Test status
Simulation time 1079415669 ps
CPU time 5.26 seconds
Started Jul 17 07:11:28 PM PDT 24
Finished Jul 17 07:11:34 PM PDT 24
Peak memory 200368 kb
Host smart-1b60990a-9369-4bfa-903f-d4e8fa8af931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796899197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2796899197
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3746723642
Short name T22
Test name
Test status
Simulation time 140576840 ps
CPU time 1.08 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:45 PM PDT 24
Peak memory 200168 kb
Host smart-da428bcf-965e-4818-9529-9fe8c4c3413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746723642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3746723642
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.735430778
Short name T98
Test name
Test status
Simulation time 198782500 ps
CPU time 1.35 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:44 PM PDT 24
Peak memory 200388 kb
Host smart-7b5321e6-9c47-4ced-8bcf-e7870404e222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735430778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.735430778
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3860127842
Short name T288
Test name
Test status
Simulation time 635087392 ps
CPU time 2.97 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:44 PM PDT 24
Peak memory 200356 kb
Host smart-301e8e63-3059-4fd5-b2fe-adfbf2a49031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860127842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3860127842
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3309519136
Short name T224
Test name
Test status
Simulation time 431404064 ps
CPU time 2.34 seconds
Started Jul 17 07:11:26 PM PDT 24
Finished Jul 17 07:11:29 PM PDT 24
Peak memory 200220 kb
Host smart-285dd490-2311-4964-8f86-7de6f26d2268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309519136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3309519136
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2639188586
Short name T536
Test name
Test status
Simulation time 121787678 ps
CPU time 0.96 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:42 PM PDT 24
Peak memory 200152 kb
Host smart-4650518a-a4f6-4831-82dc-268bc4409fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639188586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2639188586
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2006721135
Short name T219
Test name
Test status
Simulation time 80531366 ps
CPU time 0.84 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:41 PM PDT 24
Peak memory 199864 kb
Host smart-99539d79-83e0-4e3a-9e9d-d0d50be04906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006721135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2006721135
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3312991830
Short name T28
Test name
Test status
Simulation time 1900120761 ps
CPU time 7.97 seconds
Started Jul 17 07:11:31 PM PDT 24
Finished Jul 17 07:11:40 PM PDT 24
Peak memory 216856 kb
Host smart-075bfe34-ce0b-4e40-aae6-a6af95de842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312991830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3312991830
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3759098640
Short name T159
Test name
Test status
Simulation time 243990698 ps
CPU time 1.11 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:44 PM PDT 24
Peak memory 217436 kb
Host smart-c02799c1-44e7-4056-aa42-eb25d907dc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759098640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3759098640
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1422104196
Short name T409
Test name
Test status
Simulation time 83616219 ps
CPU time 0.71 seconds
Started Jul 17 07:11:24 PM PDT 24
Finished Jul 17 07:11:26 PM PDT 24
Peak memory 199948 kb
Host smart-759620b7-9fd2-4b02-94b6-888f3603f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422104196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1422104196
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3299875485
Short name T325
Test name
Test status
Simulation time 1879456174 ps
CPU time 6.91 seconds
Started Jul 17 07:11:32 PM PDT 24
Finished Jul 17 07:11:40 PM PDT 24
Peak memory 200408 kb
Host smart-4b3d8096-1917-45f1-b831-a2714f4ba826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299875485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3299875485
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1842086864
Short name T519
Test name
Test status
Simulation time 152528432 ps
CPU time 1.12 seconds
Started Jul 17 07:11:26 PM PDT 24
Finished Jul 17 07:11:28 PM PDT 24
Peak memory 200360 kb
Host smart-643149e3-3e8b-4438-ac68-7c467f1abf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842086864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1842086864
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3209627922
Short name T94
Test name
Test status
Simulation time 123081378 ps
CPU time 1.16 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 200360 kb
Host smart-124cedae-f6c1-4acc-9ee9-39126b5f5ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209627922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3209627922
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2173417873
Short name T403
Test name
Test status
Simulation time 934374905 ps
CPU time 3.86 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:49 PM PDT 24
Peak memory 200348 kb
Host smart-0975fe24-6c9b-4813-86b4-9a3ea6f77205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173417873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2173417873
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.845157784
Short name T189
Test name
Test status
Simulation time 114819476 ps
CPU time 1.4 seconds
Started Jul 17 07:11:32 PM PDT 24
Finished Jul 17 07:11:34 PM PDT 24
Peak memory 200164 kb
Host smart-7552d09d-f518-42fc-8d58-cd5c3d09ea78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845157784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.845157784
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.610445623
Short name T190
Test name
Test status
Simulation time 145108514 ps
CPU time 1.12 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:44 PM PDT 24
Peak memory 200180 kb
Host smart-62a5d910-68b7-4142-84ce-e5d12ffadeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610445623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.610445623
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3965900454
Short name T487
Test name
Test status
Simulation time 87071851 ps
CPU time 0.82 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:44 PM PDT 24
Peak memory 199924 kb
Host smart-d1cf830c-7e66-40ea-b86a-ea382de5871f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965900454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3965900454
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1096491147
Short name T382
Test name
Test status
Simulation time 1229420773 ps
CPU time 5.64 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:46 PM PDT 24
Peak memory 217736 kb
Host smart-d0150279-8e40-4a25-99dc-88cfd8ebc573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096491147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1096491147
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2448074243
Short name T390
Test name
Test status
Simulation time 245158969 ps
CPU time 1.09 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:40 PM PDT 24
Peak memory 217572 kb
Host smart-4c5915de-524a-4ed4-9d24-3d610580ea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448074243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2448074243
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2825140315
Short name T18
Test name
Test status
Simulation time 108791422 ps
CPU time 0.76 seconds
Started Jul 17 07:11:32 PM PDT 24
Finished Jul 17 07:11:34 PM PDT 24
Peak memory 199984 kb
Host smart-5a401837-0aba-4756-b6f9-60842d6261bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825140315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2825140315
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3278163324
Short name T267
Test name
Test status
Simulation time 782821449 ps
CPU time 4.12 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 200472 kb
Host smart-78826d1c-625c-4af1-929d-17432719e399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278163324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3278163324
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2677172586
Short name T241
Test name
Test status
Simulation time 183401010 ps
CPU time 1.31 seconds
Started Jul 17 07:11:33 PM PDT 24
Finished Jul 17 07:11:35 PM PDT 24
Peak memory 200156 kb
Host smart-bbc3cbfc-5143-4514-8978-c9d42cef9952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677172586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2677172586
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1019553092
Short name T364
Test name
Test status
Simulation time 114151540 ps
CPU time 1.12 seconds
Started Jul 17 07:11:36 PM PDT 24
Finished Jul 17 07:11:48 PM PDT 24
Peak memory 200404 kb
Host smart-1374876c-c256-47b3-9276-237d12173135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019553092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1019553092
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2578823037
Short name T533
Test name
Test status
Simulation time 2287086076 ps
CPU time 9.1 seconds
Started Jul 17 07:11:33 PM PDT 24
Finished Jul 17 07:11:43 PM PDT 24
Peak memory 208684 kb
Host smart-735e1e98-d273-4822-b394-94dfdc7c70c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578823037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2578823037
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1043284177
Short name T478
Test name
Test status
Simulation time 301496964 ps
CPU time 2.18 seconds
Started Jul 17 07:11:35 PM PDT 24
Finished Jul 17 07:11:43 PM PDT 24
Peak memory 208492 kb
Host smart-8cf491e3-596c-4923-b975-3c8186658b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043284177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1043284177
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2987353351
Short name T307
Test name
Test status
Simulation time 166068851 ps
CPU time 1.38 seconds
Started Jul 17 07:11:32 PM PDT 24
Finished Jul 17 07:11:34 PM PDT 24
Peak memory 200360 kb
Host smart-48f8f441-877f-4898-a5a4-44530dc36f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987353351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2987353351
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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