Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8220

1

T3

17

T6

29

T7

19

auto[1]

10993

1

T1

4

T3

1

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5956	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6476	1			T1	2		T2	1		T3	1
reset_info_cp[2]	2926	1			T1	1		T4	1		T6	8
reset_info_cp[4]	3926	1			T1	1		T4	1		T6	15
reset_info_cp[8]	120	1			T7	1		T9	1		T10	4
reset_info_cp[16]	122	1			T3	1		T6	1		T8	1
reset_info_cp[32]	95	1			T6	2		T7	1		T10	2
reset_info_cp[64]	102	1			T3	1		T6	1		T7	3
reset_info_cp[128]	110	1			T8	2		T9	1		T10	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3110	1			T6	6		T7	19		T8	52
reset_info_cp[1]	auto[1]	2746	1			T1	1		T4	1		T6	13
reset_info_cp[2]	auto[0]	918	1			T6	5		T8	24		T9	12
reset_info_cp[2]	auto[1]	2008	1			T1	1		T4	1		T6	3
reset_info_cp[4]	auto[0]	1421	1			T6	8		T8	35		T9	11
reset_info_cp[4]	auto[1]	2505	1			T1	1		T4	1		T6	7
reset_info_cp[8]	auto[0]	54	1			T9	1		T10	2		T46	1
reset_info_cp[8]	auto[1]	66	1			T7	1		T10	2		T34	2
reset_info_cp[16]	auto[0]	50	1			T3	1		T6	1		T8	1
reset_info_cp[16]	auto[1]	72	1			T20	1		T46	1		T80	6
reset_info_cp[32]	auto[0]	34	1			T10	1		T132	1		T135	2
reset_info_cp[32]	auto[1]	61	1			T6	2		T7	1		T10	1
reset_info_cp[64]	auto[0]	40	1			T3	1		T6	1		T8	1
reset_info_cp[64]	auto[1]	62	1			T7	3		T8	1		T9	1
reset_info_cp[128]	auto[0]	33	1			T79	1		T80	1		T132	1
reset_info_cp[128]	auto[1]	77	1			T8	2		T9	1		T10	2