Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T535 /workspace/coverage/default/37.rstmgr_alert_test.3164091695 Jul 18 05:59:47 PM PDT 24 Jul 18 05:59:58 PM PDT 24 76582794 ps
T536 /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1418050172 Jul 18 05:59:34 PM PDT 24 Jul 18 05:59:49 PM PDT 24 244615536 ps
T537 /workspace/coverage/default/42.rstmgr_reset.3175113002 Jul 18 05:59:49 PM PDT 24 Jul 18 06:00:06 PM PDT 24 1994495544 ps
T538 /workspace/coverage/default/42.rstmgr_smoke.2819106509 Jul 18 05:59:51 PM PDT 24 Jul 18 06:00:01 PM PDT 24 107826878 ps
T539 /workspace/coverage/default/48.rstmgr_sw_rst.1866539752 Jul 18 06:00:13 PM PDT 24 Jul 18 06:00:22 PM PDT 24 326984230 ps
T60 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1231501282 Jul 18 06:26:11 PM PDT 24 Jul 18 06:26:17 PM PDT 24 494742686 ps
T55 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1807264775 Jul 18 06:26:12 PM PDT 24 Jul 18 06:26:19 PM PDT 24 794950219 ps
T56 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.582767794 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:40 PM PDT 24 806169998 ps
T57 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.753867485 Jul 18 06:26:17 PM PDT 24 Jul 18 06:26:20 PM PDT 24 157986119 ps
T61 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.573247305 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:15 PM PDT 24 388459902 ps
T98 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2688239215 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:38 PM PDT 24 196246394 ps
T66 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.317382388 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:40 PM PDT 24 938380141 ps
T62 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1652040516 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:40 PM PDT 24 420983818 ps
T540 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.536232376 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:38 PM PDT 24 79748468 ps
T541 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1604017016 Jul 18 06:26:18 PM PDT 24 Jul 18 06:26:21 PM PDT 24 96790220 ps
T542 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2703030062 Jul 18 06:26:15 PM PDT 24 Jul 18 06:26:18 PM PDT 24 92358439 ps
T99 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1582333582 Jul 18 06:26:14 PM PDT 24 Jul 18 06:26:17 PM PDT 24 77940102 ps
T131 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4082120040 Jul 18 06:26:14 PM PDT 24 Jul 18 06:26:18 PM PDT 24 105825359 ps
T130 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1759019821 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:36 PM PDT 24 85196507 ps
T67 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1500259289 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:36 PM PDT 24 102025354 ps
T100 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3454358501 Jul 18 06:26:30 PM PDT 24 Jul 18 06:26:32 PM PDT 24 213540093 ps
T543 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3925007106 Jul 18 06:26:12 PM PDT 24 Jul 18 06:26:15 PM PDT 24 74956143 ps
T101 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1101925457 Jul 18 06:26:31 PM PDT 24 Jul 18 06:26:34 PM PDT 24 184068644 ps
T544 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2041559260 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:37 PM PDT 24 90782915 ps
T102 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.169785978 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:12 PM PDT 24 74818612 ps
T87 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2186054557 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:37 PM PDT 24 390743315 ps
T88 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.951084878 Jul 18 06:26:34 PM PDT 24 Jul 18 06:26:40 PM PDT 24 193073323 ps
T89 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1765997940 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:38 PM PDT 24 375704086 ps
T90 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.430430423 Jul 18 06:26:18 PM PDT 24 Jul 18 06:26:23 PM PDT 24 807994573 ps
T103 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.202897800 Jul 18 06:25:54 PM PDT 24 Jul 18 06:25:58 PM PDT 24 254399193 ps
T91 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3878951263 Jul 18 06:26:36 PM PDT 24 Jul 18 06:26:41 PM PDT 24 111897964 ps
T545 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.850657186 Jul 18 06:26:11 PM PDT 24 Jul 18 06:26:20 PM PDT 24 483032675 ps
T92 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4196881767 Jul 18 06:26:30 PM PDT 24 Jul 18 06:26:33 PM PDT 24 490037822 ps
T546 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4073404293 Jul 18 06:26:36 PM PDT 24 Jul 18 06:26:45 PM PDT 24 638289192 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1472355698 Jul 18 06:25:52 PM PDT 24 Jul 18 06:25:58 PM PDT 24 807739891 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2434025794 Jul 18 06:26:14 PM PDT 24 Jul 18 06:26:18 PM PDT 24 77317315 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1209191907 Jul 18 06:25:54 PM PDT 24 Jul 18 06:25:58 PM PDT 24 101026467 ps
T550 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2812803423 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:39 PM PDT 24 487990875 ps
T551 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3948786187 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:37 PM PDT 24 216320496 ps
T109 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2041141488 Jul 18 06:25:59 PM PDT 24 Jul 18 06:26:03 PM PDT 24 483119022 ps
T107 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.969830002 Jul 18 06:26:14 PM PDT 24 Jul 18 06:26:19 PM PDT 24 428036809 ps
T104 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1910581545 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:13 PM PDT 24 63239713 ps
T105 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2314694840 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:38 PM PDT 24 119113561 ps
T552 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3973587730 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:13 PM PDT 24 118025178 ps
T553 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2439138042 Jul 18 06:26:11 PM PDT 24 Jul 18 06:26:15 PM PDT 24 70037515 ps
T554 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1661723855 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:38 PM PDT 24 499494287 ps
T555 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1920285673 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:38 PM PDT 24 182162665 ps
T556 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3689827201 Jul 18 06:26:31 PM PDT 24 Jul 18 06:26:34 PM PDT 24 193205914 ps
T557 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.828332660 Jul 18 06:25:58 PM PDT 24 Jul 18 06:26:01 PM PDT 24 149316018 ps
T106 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4131037114 Jul 18 06:26:11 PM PDT 24 Jul 18 06:26:15 PM PDT 24 79582709 ps
T129 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1957796635 Jul 18 06:26:16 PM PDT 24 Jul 18 06:26:21 PM PDT 24 934699327 ps
T558 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.271358892 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:37 PM PDT 24 109166505 ps
T113 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1692241753 Jul 18 06:26:34 PM PDT 24 Jul 18 06:26:41 PM PDT 24 942579645 ps
T559 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.551532470 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:37 PM PDT 24 145323586 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2034396631 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:12 PM PDT 24 78151167 ps
T110 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1888259384 Jul 18 06:26:14 PM PDT 24 Jul 18 06:26:20 PM PDT 24 874376077 ps
T561 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1396567223 Jul 18 06:26:31 PM PDT 24 Jul 18 06:26:35 PM PDT 24 128745105 ps
T562 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.514107835 Jul 18 06:26:31 PM PDT 24 Jul 18 06:26:33 PM PDT 24 55271937 ps
T563 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4135578820 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:37 PM PDT 24 79860637 ps
T111 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2690409383 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:16 PM PDT 24 867379533 ps
T108 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1075484010 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:14 PM PDT 24 554026839 ps
T564 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1197466032 Jul 18 06:26:14 PM PDT 24 Jul 18 06:26:19 PM PDT 24 364907159 ps
T565 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2121650492 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:39 PM PDT 24 242650141 ps
T566 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1773507059 Jul 18 06:26:13 PM PDT 24 Jul 18 06:26:16 PM PDT 24 91202075 ps
T567 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.168163011 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:14 PM PDT 24 208280807 ps
T568 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1264331928 Jul 18 06:26:30 PM PDT 24 Jul 18 06:26:32 PM PDT 24 98283245 ps
T569 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2173083666 Jul 18 06:26:31 PM PDT 24 Jul 18 06:26:33 PM PDT 24 72693218 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.928601591 Jul 18 06:26:11 PM PDT 24 Jul 18 06:26:17 PM PDT 24 502941873 ps
T571 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.348409840 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:38 PM PDT 24 93623498 ps
T112 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.894960408 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:39 PM PDT 24 936669758 ps
T572 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1591608178 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:13 PM PDT 24 189821787 ps
T573 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1223244380 Jul 18 06:26:34 PM PDT 24 Jul 18 06:26:39 PM PDT 24 145666285 ps
T574 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3163648994 Jul 18 06:26:35 PM PDT 24 Jul 18 06:26:43 PM PDT 24 780082290 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2575542539 Jul 18 06:25:56 PM PDT 24 Jul 18 06:25:59 PM PDT 24 82441861 ps
T576 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1535715032 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:38 PM PDT 24 154035062 ps
T577 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4096584423 Jul 18 06:26:34 PM PDT 24 Jul 18 06:26:40 PM PDT 24 295409445 ps
T578 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.465731223 Jul 18 06:26:14 PM PDT 24 Jul 18 06:26:18 PM PDT 24 217746446 ps
T579 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1812781843 Jul 18 06:26:12 PM PDT 24 Jul 18 06:26:16 PM PDT 24 246083854 ps
T580 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1773138205 Jul 18 06:26:11 PM PDT 24 Jul 18 06:26:15 PM PDT 24 190162192 ps
T581 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2671987322 Jul 18 06:26:12 PM PDT 24 Jul 18 06:26:16 PM PDT 24 264329137 ps
T582 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.842644796 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:12 PM PDT 24 61902792 ps
T583 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2477738664 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:38 PM PDT 24 137904779 ps
T584 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4233256877 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:15 PM PDT 24 461788103 ps
T585 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3488985925 Jul 18 06:26:34 PM PDT 24 Jul 18 06:26:42 PM PDT 24 192440880 ps
T586 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1134945561 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:38 PM PDT 24 949086580 ps
T587 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1709856028 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:38 PM PDT 24 183322766 ps
T588 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1425911481 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:19 PM PDT 24 481491470 ps
T589 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.23534754 Jul 18 06:26:34 PM PDT 24 Jul 18 06:26:41 PM PDT 24 788668653 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3170592591 Jul 18 06:26:16 PM PDT 24 Jul 18 06:26:19 PM PDT 24 133035554 ps
T591 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2130929971 Jul 18 06:26:35 PM PDT 24 Jul 18 06:26:41 PM PDT 24 61235697 ps
T592 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2368525420 Jul 18 06:26:15 PM PDT 24 Jul 18 06:26:19 PM PDT 24 102540780 ps
T593 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2019666779 Jul 18 06:25:57 PM PDT 24 Jul 18 06:26:01 PM PDT 24 132445125 ps
T594 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1167211486 Jul 18 06:26:18 PM PDT 24 Jul 18 06:26:22 PM PDT 24 87781784 ps
T595 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2687646100 Jul 18 06:26:36 PM PDT 24 Jul 18 06:26:42 PM PDT 24 131231341 ps
T596 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.853939627 Jul 18 06:26:17 PM PDT 24 Jul 18 06:26:20 PM PDT 24 113912280 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.500201479 Jul 18 06:26:19 PM PDT 24 Jul 18 06:26:22 PM PDT 24 82081063 ps
T598 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1282653633 Jul 18 06:26:31 PM PDT 24 Jul 18 06:26:35 PM PDT 24 121440508 ps
T599 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3012288400 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:14 PM PDT 24 276122447 ps
T600 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3374533350 Jul 18 06:26:11 PM PDT 24 Jul 18 06:26:15 PM PDT 24 159666845 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2668912268 Jul 18 06:26:17 PM PDT 24 Jul 18 06:26:20 PM PDT 24 260995292 ps
T602 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3019107162 Jul 18 06:26:18 PM PDT 24 Jul 18 06:26:24 PM PDT 24 876835491 ps
T603 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.728377570 Jul 18 06:26:31 PM PDT 24 Jul 18 06:26:34 PM PDT 24 199368360 ps
T604 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2955475025 Jul 18 06:26:18 PM PDT 24 Jul 18 06:26:21 PM PDT 24 102444972 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.807506802 Jul 18 06:25:57 PM PDT 24 Jul 18 06:26:03 PM PDT 24 413952835 ps
T606 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2350465005 Jul 18 06:26:14 PM PDT 24 Jul 18 06:26:18 PM PDT 24 85114451 ps
T607 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3697225244 Jul 18 06:26:31 PM PDT 24 Jul 18 06:26:33 PM PDT 24 72939187 ps
T608 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2509823079 Jul 18 06:25:54 PM PDT 24 Jul 18 06:25:57 PM PDT 24 61568154 ps
T609 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4046955351 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:37 PM PDT 24 63078035 ps
T610 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1840407220 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:38 PM PDT 24 150813744 ps
T611 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2292696232 Jul 18 06:26:10 PM PDT 24 Jul 18 06:26:15 PM PDT 24 235068012 ps
T128 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.65633275 Jul 18 06:25:54 PM PDT 24 Jul 18 06:26:00 PM PDT 24 871825816 ps
T612 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.874504514 Jul 18 06:26:17 PM PDT 24 Jul 18 06:26:20 PM PDT 24 137494277 ps
T613 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3084980047 Jul 18 06:26:11 PM PDT 24 Jul 18 06:26:14 PM PDT 24 103315009 ps
T614 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3288058942 Jul 18 06:26:31 PM PDT 24 Jul 18 06:26:35 PM PDT 24 892501848 ps
T615 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2948907293 Jul 18 06:26:15 PM PDT 24 Jul 18 06:26:19 PM PDT 24 126488895 ps
T616 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2589831873 Jul 18 06:26:33 PM PDT 24 Jul 18 06:26:38 PM PDT 24 169872785 ps
T617 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1192392073 Jul 18 06:25:54 PM PDT 24 Jul 18 06:26:00 PM PDT 24 164275579 ps
T618 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2403291341 Jul 18 06:26:11 PM PDT 24 Jul 18 06:26:14 PM PDT 24 187241420 ps
T619 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3999206876 Jul 18 06:26:32 PM PDT 24 Jul 18 06:26:36 PM PDT 24 60023944 ps
T620 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3592837059 Jul 18 06:25:58 PM PDT 24 Jul 18 06:26:02 PM PDT 24 270874637 ps

Test location /workspace/coverage/default/37.rstmgr_stress_all.1298853958
Short name T10
Test name
Test status
Simulation time 11042210399 ps
CPU time 38.15 seconds
Started Jul 18 05:59:46 PM PDT 24
Finished Jul 18 06:00:35 PM PDT 24
Peak memory 208960 kb
Host smart-8ce126fe-3da6-4680-84ed-4f7233d38d53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298853958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1298853958
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3248026871
Short name T83
Test name
Test status
Simulation time 115024029 ps
CPU time 1.23 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 200664 kb
Host smart-831d815b-5b95-4da6-8596-012a8c91c30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248026871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3248026871
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.573247305
Short name T61
Test name
Test status
Simulation time 388459902 ps
CPU time 2.83 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:15 PM PDT 24
Peak memory 216648 kb
Host smart-3eeedf27-63b6-4733-a33b-72470b60cd62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573247305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.573247305
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3783249784
Short name T68
Test name
Test status
Simulation time 17216786963 ps
CPU time 24.81 seconds
Started Jul 18 05:58:50 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 218344 kb
Host smart-9f0fed8c-ba9f-47bd-8b27-4f01032ba1e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783249784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3783249784
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3965349143
Short name T125
Test name
Test status
Simulation time 394452833 ps
CPU time 2.28 seconds
Started Jul 18 05:59:54 PM PDT 24
Finished Jul 18 06:00:04 PM PDT 24
Peak memory 200484 kb
Host smart-e7680c69-b2b7-476a-a292-16a999da2437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965349143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3965349143
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2665119413
Short name T7
Test name
Test status
Simulation time 1226460153 ps
CPU time 6.02 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:36 PM PDT 24
Peak memory 216980 kb
Host smart-a1dea931-b7c7-4745-85f6-fccfbdfc1c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665119413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2665119413
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.582767794
Short name T56
Test name
Test status
Simulation time 806169998 ps
CPU time 2.99 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:40 PM PDT 24
Peak memory 200548 kb
Host smart-d4dfa85c-e1bb-423e-82fa-1386a5602339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582767794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.582767794
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.320157615
Short name T80
Test name
Test status
Simulation time 8510935354 ps
CPU time 38.37 seconds
Started Jul 18 05:58:58 PM PDT 24
Finished Jul 18 05:59:47 PM PDT 24
Peak memory 208892 kb
Host smart-7d169a0e-ccae-4d9a-9b16-db80a0c646c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320157615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.320157615
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1531597223
Short name T138
Test name
Test status
Simulation time 85624328 ps
CPU time 0.9 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200292 kb
Host smart-b5727985-7200-45de-a7d6-a2ad10f6b86b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531597223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1531597223
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2468236230
Short name T52
Test name
Test status
Simulation time 192029147 ps
CPU time 1.48 seconds
Started Jul 18 05:58:50 PM PDT 24
Finished Jul 18 05:58:55 PM PDT 24
Peak memory 200652 kb
Host smart-1192abce-9899-4e00-afd1-43d46273f2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468236230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2468236230
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.686255416
Short name T168
Test name
Test status
Simulation time 137191169 ps
CPU time 1.13 seconds
Started Jul 18 05:59:08 PM PDT 24
Finished Jul 18 05:59:15 PM PDT 24
Peak memory 200436 kb
Host smart-74a85a6f-b1d0-4e9f-a80e-259f7eb81b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686255416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.686255416
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1199543745
Short name T23
Test name
Test status
Simulation time 1898169346 ps
CPU time 7.15 seconds
Started Jul 18 05:58:59 PM PDT 24
Finished Jul 18 05:59:16 PM PDT 24
Peak memory 217668 kb
Host smart-f3664ab8-9c5d-4d20-975f-401ca6d0b38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199543745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1199543745
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.604441695
Short name T2
Test name
Test status
Simulation time 197623857 ps
CPU time 0.94 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200272 kb
Host smart-1180b363-0cb6-4419-ab98-32203fd886fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604441695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.604441695
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2798139270
Short name T114
Test name
Test status
Simulation time 1755671510 ps
CPU time 6.26 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:36 PM PDT 24
Peak memory 200728 kb
Host smart-8af6ec95-9935-4943-8b3f-892a583e79c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798139270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2798139270
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.531812736
Short name T51
Test name
Test status
Simulation time 2185382364 ps
CPU time 7.41 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:59:06 PM PDT 24
Peak memory 217528 kb
Host smart-b5e3222c-5183-4992-a401-0be3306106ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531812736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.531812736
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3592616567
Short name T132
Test name
Test status
Simulation time 159782746 ps
CPU time 1.27 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:01 PM PDT 24
Peak memory 200708 kb
Host smart-6cd0a513-e7af-44db-8ce1-fedd1673187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592616567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3592616567
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2690409383
Short name T111
Test name
Test status
Simulation time 867379533 ps
CPU time 3.32 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:16 PM PDT 24
Peak memory 200540 kb
Host smart-301efb37-3c77-496f-b2ed-0d72be136509
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690409383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2690409383
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.202897800
Short name T103
Test name
Test status
Simulation time 254399193 ps
CPU time 1.63 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:58 PM PDT 24
Peak memory 200620 kb
Host smart-d06f6ef5-4395-46a9-8bea-832e86182320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202897800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.202897800
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2186054557
Short name T87
Test name
Test status
Simulation time 390743315 ps
CPU time 2.57 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:37 PM PDT 24
Peak memory 208612 kb
Host smart-848c74fe-07f8-4250-b7d8-000669460def
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186054557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2186054557
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3592837059
Short name T620
Test name
Test status
Simulation time 270874637 ps
CPU time 1.7 seconds
Started Jul 18 06:25:58 PM PDT 24
Finished Jul 18 06:26:02 PM PDT 24
Peak memory 200312 kb
Host smart-20ee56ca-e427-44c2-b021-16f360d2b559
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592837059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
592837059
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1472355698
Short name T547
Test name
Test status
Simulation time 807739891 ps
CPU time 5.22 seconds
Started Jul 18 06:25:52 PM PDT 24
Finished Jul 18 06:25:58 PM PDT 24
Peak memory 200448 kb
Host smart-7c81929a-473c-4cba-a5d7-89c7f25663aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472355698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
472355698
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.828332660
Short name T557
Test name
Test status
Simulation time 149316018 ps
CPU time 0.97 seconds
Started Jul 18 06:25:58 PM PDT 24
Finished Jul 18 06:26:01 PM PDT 24
Peak memory 200248 kb
Host smart-212cf0f0-9613-4e10-bc8d-c4f623e916ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828332660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.828332660
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2019666779
Short name T593
Test name
Test status
Simulation time 132445125 ps
CPU time 1.01 seconds
Started Jul 18 06:25:57 PM PDT 24
Finished Jul 18 06:26:01 PM PDT 24
Peak memory 200408 kb
Host smart-6b732035-2c3a-4df6-9316-63f8e138ed76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019666779 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2019666779
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2509823079
Short name T608
Test name
Test status
Simulation time 61568154 ps
CPU time 0.86 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:57 PM PDT 24
Peak memory 200288 kb
Host smart-025ac348-cfbb-4792-8407-b02121d82166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509823079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2509823079
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1192392073
Short name T617
Test name
Test status
Simulation time 164275579 ps
CPU time 2.36 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:26:00 PM PDT 24
Peak memory 208632 kb
Host smart-8f02f260-f057-4e29-911b-659b00effa12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192392073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1192392073
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2041141488
Short name T109
Test name
Test status
Simulation time 483119022 ps
CPU time 1.89 seconds
Started Jul 18 06:25:59 PM PDT 24
Finished Jul 18 06:26:03 PM PDT 24
Peak memory 200436 kb
Host smart-5e00fd58-a1f9-49c7-8f1e-5f4e703e53a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041141488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2041141488
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4082120040
Short name T131
Test name
Test status
Simulation time 105825359 ps
CPU time 1.36 seconds
Started Jul 18 06:26:14 PM PDT 24
Finished Jul 18 06:26:18 PM PDT 24
Peak memory 200336 kb
Host smart-c7b7f00a-8454-4799-9505-eda1a95e2939
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082120040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.4
082120040
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3012288400
Short name T599
Test name
Test status
Simulation time 276122447 ps
CPU time 3.34 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:14 PM PDT 24
Peak memory 200456 kb
Host smart-21f1d85a-3ce4-4dde-b6cb-07fa2e220a2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012288400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
012288400
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1209191907
Short name T549
Test name
Test status
Simulation time 101026467 ps
CPU time 0.93 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:58 PM PDT 24
Peak memory 200164 kb
Host smart-20d5ed69-99aa-4fdc-9ed0-94425c67c099
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209191907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
209191907
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1591608178
Short name T572
Test name
Test status
Simulation time 189821787 ps
CPU time 1.29 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:13 PM PDT 24
Peak memory 208604 kb
Host smart-816bf7a4-d686-4cea-a941-81d34d7d5143
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591608178 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1591608178
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2575542539
Short name T575
Test name
Test status
Simulation time 82441861 ps
CPU time 0.87 seconds
Started Jul 18 06:25:56 PM PDT 24
Finished Jul 18 06:25:59 PM PDT 24
Peak memory 200236 kb
Host smart-5175d227-c850-443d-b91e-208c63c9dd5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575542539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2575542539
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2034396631
Short name T560
Test name
Test status
Simulation time 78151167 ps
CPU time 1.04 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:12 PM PDT 24
Peak memory 200340 kb
Host smart-4dd669d9-65fd-4894-bc4a-b21fd62a874a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034396631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2034396631
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.807506802
Short name T605
Test name
Test status
Simulation time 413952835 ps
CPU time 2.97 seconds
Started Jul 18 06:25:57 PM PDT 24
Finished Jul 18 06:26:03 PM PDT 24
Peak memory 208588 kb
Host smart-21b6c5be-e6b8-488d-99bc-fdf62f608fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807506802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.807506802
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.65633275
Short name T128
Test name
Test status
Simulation time 871825816 ps
CPU time 3.66 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:26:00 PM PDT 24
Peak memory 200496 kb
Host smart-e17a253a-4ae6-4d2b-8ee4-238c03f252e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65633275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.65633275
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1500259289
Short name T67
Test name
Test status
Simulation time 102025354 ps
CPU time 0.93 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:36 PM PDT 24
Peak memory 200340 kb
Host smart-b12d7099-3770-4d43-93f8-d415ff64450c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500259289 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1500259289
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1759019821
Short name T130
Test name
Test status
Simulation time 85196507 ps
CPU time 0.86 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:36 PM PDT 24
Peak memory 200260 kb
Host smart-6a9aae6f-187e-421d-9690-0df99a4ebf38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759019821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1759019821
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.271358892
Short name T558
Test name
Test status
Simulation time 109166505 ps
CPU time 1.31 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:37 PM PDT 24
Peak memory 200556 kb
Host smart-73e1c811-e17b-4af1-aae8-e65d54f0cea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271358892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.271358892
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2812803423
Short name T550
Test name
Test status
Simulation time 487990875 ps
CPU time 1.87 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:39 PM PDT 24
Peak memory 200508 kb
Host smart-603316c7-16cb-4492-b5ea-fe43e3d01829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812803423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2812803423
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2589831873
Short name T616
Test name
Test status
Simulation time 169872785 ps
CPU time 1.66 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 208728 kb
Host smart-b08f53da-e067-4d26-ac0e-4fc8f83aefcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589831873 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2589831873
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4046955351
Short name T609
Test name
Test status
Simulation time 63078035 ps
CPU time 0.87 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:37 PM PDT 24
Peak memory 200272 kb
Host smart-bd4a0425-4117-4023-acfe-93a754388a52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046955351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4046955351
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2121650492
Short name T565
Test name
Test status
Simulation time 242650141 ps
CPU time 1.57 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:39 PM PDT 24
Peak memory 200432 kb
Host smart-45be30f2-77a8-46a4-bd16-36d7dc92d9c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121650492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2121650492
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1396567223
Short name T561
Test name
Test status
Simulation time 128745105 ps
CPU time 2.13 seconds
Started Jul 18 06:26:31 PM PDT 24
Finished Jul 18 06:26:35 PM PDT 24
Peak memory 216732 kb
Host smart-45b75037-5f5c-4510-bb58-f0a86f1ee18c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396567223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1396567223
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.317382388
Short name T66
Test name
Test status
Simulation time 938380141 ps
CPU time 2.95 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:40 PM PDT 24
Peak memory 200564 kb
Host smart-71ae4303-f526-47b5-b886-fa8dbd8ad53c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317382388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.317382388
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.951084878
Short name T88
Test name
Test status
Simulation time 193073323 ps
CPU time 1.26 seconds
Started Jul 18 06:26:34 PM PDT 24
Finished Jul 18 06:26:40 PM PDT 24
Peak memory 200496 kb
Host smart-c0145311-efe3-41a0-a874-9438dcc58d26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951084878 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.951084878
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.514107835
Short name T562
Test name
Test status
Simulation time 55271937 ps
CPU time 0.78 seconds
Started Jul 18 06:26:31 PM PDT 24
Finished Jul 18 06:26:33 PM PDT 24
Peak memory 200268 kb
Host smart-63855397-b669-488d-b733-34b99d0f9331
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514107835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.514107835
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1282653633
Short name T598
Test name
Test status
Simulation time 121440508 ps
CPU time 1.12 seconds
Started Jul 18 06:26:31 PM PDT 24
Finished Jul 18 06:26:35 PM PDT 24
Peak memory 200236 kb
Host smart-482ef6f0-6d76-44b1-aa8a-288db3133b5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282653633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1282653633
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1661723855
Short name T554
Test name
Test status
Simulation time 499494287 ps
CPU time 3.69 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 200388 kb
Host smart-548a54a0-ddd1-4db6-a2e8-e5b9dac4cca7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661723855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1661723855
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3689827201
Short name T556
Test name
Test status
Simulation time 193205914 ps
CPU time 1.48 seconds
Started Jul 18 06:26:31 PM PDT 24
Finished Jul 18 06:26:34 PM PDT 24
Peak memory 208612 kb
Host smart-681822de-aef8-467b-bc1b-8ef3697fbf96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689827201 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3689827201
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2130929971
Short name T591
Test name
Test status
Simulation time 61235697 ps
CPU time 0.77 seconds
Started Jul 18 06:26:35 PM PDT 24
Finished Jul 18 06:26:41 PM PDT 24
Peak memory 200264 kb
Host smart-ceb83f89-b06b-422b-9eb8-a9bf55c86b04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130929971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2130929971
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1101925457
Short name T101
Test name
Test status
Simulation time 184068644 ps
CPU time 1.58 seconds
Started Jul 18 06:26:31 PM PDT 24
Finished Jul 18 06:26:34 PM PDT 24
Peak memory 200604 kb
Host smart-073f3858-c1af-4baf-ab8b-dfb644c5b22d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101925457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1101925457
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3948786187
Short name T551
Test name
Test status
Simulation time 216320496 ps
CPU time 1.94 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:37 PM PDT 24
Peak memory 208652 kb
Host smart-3b7293d6-acfa-457f-8112-85da18086e96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948786187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3948786187
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1692241753
Short name T113
Test name
Test status
Simulation time 942579645 ps
CPU time 3.34 seconds
Started Jul 18 06:26:34 PM PDT 24
Finished Jul 18 06:26:41 PM PDT 24
Peak memory 200476 kb
Host smart-097a51d1-9643-45be-bd18-8bbf37f99598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692241753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1692241753
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.728377570
Short name T603
Test name
Test status
Simulation time 199368360 ps
CPU time 1.38 seconds
Started Jul 18 06:26:31 PM PDT 24
Finished Jul 18 06:26:34 PM PDT 24
Peak memory 208636 kb
Host smart-b0339101-cba2-4361-94df-3a77a9620fbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728377570 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.728377570
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3697225244
Short name T607
Test name
Test status
Simulation time 72939187 ps
CPU time 0.8 seconds
Started Jul 18 06:26:31 PM PDT 24
Finished Jul 18 06:26:33 PM PDT 24
Peak memory 200264 kb
Host smart-349a10d0-30f2-432a-8e3a-034c696daa2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697225244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3697225244
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2688239215
Short name T98
Test name
Test status
Simulation time 196246394 ps
CPU time 1.41 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 200328 kb
Host smart-ad3ec6ea-1988-4a40-aafa-11dba6241b68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688239215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2688239215
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1652040516
Short name T62
Test name
Test status
Simulation time 420983818 ps
CPU time 3.01 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:40 PM PDT 24
Peak memory 208592 kb
Host smart-be3632f4-0bb4-4787-bc94-394a722d510f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652040516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1652040516
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1134945561
Short name T586
Test name
Test status
Simulation time 949086580 ps
CPU time 3.32 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 200472 kb
Host smart-1d5d5cb9-94ec-4e2a-bdbc-fc0084e8aa2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134945561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1134945561
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.551532470
Short name T559
Test name
Test status
Simulation time 145323586 ps
CPU time 1.31 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:37 PM PDT 24
Peak memory 208636 kb
Host smart-5f2d0e67-6b04-440e-a125-92e3bd09cc0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551532470 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.551532470
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.348409840
Short name T571
Test name
Test status
Simulation time 93623498 ps
CPU time 0.92 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 200268 kb
Host smart-b8129aa9-73c8-4889-8817-fc82cc55235c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348409840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.348409840
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1264331928
Short name T568
Test name
Test status
Simulation time 98283245 ps
CPU time 1.29 seconds
Started Jul 18 06:26:30 PM PDT 24
Finished Jul 18 06:26:32 PM PDT 24
Peak memory 200488 kb
Host smart-5e5acf7c-a747-4a51-9877-44e8708e0eef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264331928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1264331928
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3488985925
Short name T585
Test name
Test status
Simulation time 192440880 ps
CPU time 2.92 seconds
Started Jul 18 06:26:34 PM PDT 24
Finished Jul 18 06:26:42 PM PDT 24
Peak memory 208748 kb
Host smart-f76c6168-d25f-4bfc-818c-65b8c95aeae2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488985925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3488985925
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3163648994
Short name T574
Test name
Test status
Simulation time 780082290 ps
CPU time 2.98 seconds
Started Jul 18 06:26:35 PM PDT 24
Finished Jul 18 06:26:43 PM PDT 24
Peak memory 200540 kb
Host smart-4eb243c5-33c1-4ce9-8dbb-e1559bb1b353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163648994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3163648994
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1840407220
Short name T610
Test name
Test status
Simulation time 150813744 ps
CPU time 1.2 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 200744 kb
Host smart-071a703e-e4af-405f-831c-02dddf57abbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840407220 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1840407220
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3999206876
Short name T619
Test name
Test status
Simulation time 60023944 ps
CPU time 0.81 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:36 PM PDT 24
Peak memory 200268 kb
Host smart-bd2bbf67-f586-447b-a3f4-fa3d8784dd3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999206876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3999206876
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2477738664
Short name T583
Test name
Test status
Simulation time 137904779 ps
CPU time 1.12 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 200348 kb
Host smart-fd758200-72bd-44e4-ab5b-0b2c0fbd82f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477738664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2477738664
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4096584423
Short name T577
Test name
Test status
Simulation time 295409445 ps
CPU time 2.43 seconds
Started Jul 18 06:26:34 PM PDT 24
Finished Jul 18 06:26:40 PM PDT 24
Peak memory 208620 kb
Host smart-c7645dfb-292d-4933-a992-28a445fd2e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096584423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4096584423
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.894960408
Short name T112
Test name
Test status
Simulation time 936669758 ps
CPU time 3.21 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:39 PM PDT 24
Peak memory 200476 kb
Host smart-7cc43ae8-219d-466c-ade6-47e0e02a76e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894960408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.894960408
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1223244380
Short name T573
Test name
Test status
Simulation time 145666285 ps
CPU time 1.03 seconds
Started Jul 18 06:26:34 PM PDT 24
Finished Jul 18 06:26:39 PM PDT 24
Peak memory 200404 kb
Host smart-f28e012a-4ae9-4436-9ef8-ed7a2042ea0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223244380 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1223244380
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2041559260
Short name T544
Test name
Test status
Simulation time 90782915 ps
CPU time 0.87 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:37 PM PDT 24
Peak memory 200272 kb
Host smart-fa5542a5-ea7e-4f70-b5fa-84aba910f24a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041559260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2041559260
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2687646100
Short name T595
Test name
Test status
Simulation time 131231341 ps
CPU time 1.06 seconds
Started Jul 18 06:26:36 PM PDT 24
Finished Jul 18 06:26:42 PM PDT 24
Peak memory 200320 kb
Host smart-3479ee38-5f5d-4a9e-8e4c-abb999bf7717
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687646100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2687646100
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4073404293
Short name T546
Test name
Test status
Simulation time 638289192 ps
CPU time 4.39 seconds
Started Jul 18 06:26:36 PM PDT 24
Finished Jul 18 06:26:45 PM PDT 24
Peak memory 200392 kb
Host smart-7ec5f6ea-afa4-4166-af54-3eb6f59fe028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073404293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4073404293
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4196881767
Short name T92
Test name
Test status
Simulation time 490037822 ps
CPU time 2.28 seconds
Started Jul 18 06:26:30 PM PDT 24
Finished Jul 18 06:26:33 PM PDT 24
Peak memory 200452 kb
Host smart-a5b75453-4791-42f0-8412-2fa2d728db13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196881767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.4196881767
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1535715032
Short name T576
Test name
Test status
Simulation time 154035062 ps
CPU time 1.51 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 208828 kb
Host smart-30948c67-d67b-4d96-8740-e5433220fdf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535715032 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1535715032
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2173083666
Short name T569
Test name
Test status
Simulation time 72693218 ps
CPU time 0.8 seconds
Started Jul 18 06:26:31 PM PDT 24
Finished Jul 18 06:26:33 PM PDT 24
Peak memory 200208 kb
Host smart-e5220b4c-b03d-47d3-937f-f6247fb53f53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173083666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2173083666
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2314694840
Short name T105
Test name
Test status
Simulation time 119113561 ps
CPU time 1.47 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 200528 kb
Host smart-9ac3d877-44d4-4049-b871-72c2fc0a4e8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314694840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2314694840
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1709856028
Short name T587
Test name
Test status
Simulation time 183322766 ps
CPU time 2.73 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 211992 kb
Host smart-1605feee-6ebf-48cc-97f5-cb3565f6e2ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709856028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1709856028
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3288058942
Short name T614
Test name
Test status
Simulation time 892501848 ps
CPU time 3.33 seconds
Started Jul 18 06:26:31 PM PDT 24
Finished Jul 18 06:26:35 PM PDT 24
Peak memory 200460 kb
Host smart-3a8ae99b-19e7-4561-bde6-92cc26933c74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288058942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3288058942
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3878951263
Short name T91
Test name
Test status
Simulation time 111897964 ps
CPU time 0.97 seconds
Started Jul 18 06:26:36 PM PDT 24
Finished Jul 18 06:26:41 PM PDT 24
Peak memory 200400 kb
Host smart-e39cb359-c09c-4a30-8d14-747ba3df2241
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878951263 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3878951263
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.536232376
Short name T540
Test name
Test status
Simulation time 79748468 ps
CPU time 0.81 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 200268 kb
Host smart-0b552774-e11b-46e4-83d3-e91ac8422cde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536232376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.536232376
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3454358501
Short name T100
Test name
Test status
Simulation time 213540093 ps
CPU time 1.55 seconds
Started Jul 18 06:26:30 PM PDT 24
Finished Jul 18 06:26:32 PM PDT 24
Peak memory 200496 kb
Host smart-665a32ba-dcb9-4a63-9912-74eff835bf17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454358501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3454358501
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1765997940
Short name T89
Test name
Test status
Simulation time 375704086 ps
CPU time 2.86 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 208836 kb
Host smart-157d6593-b409-4b5f-8018-59faf6a3640b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765997940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1765997940
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.23534754
Short name T589
Test name
Test status
Simulation time 788668653 ps
CPU time 2.85 seconds
Started Jul 18 06:26:34 PM PDT 24
Finished Jul 18 06:26:41 PM PDT 24
Peak memory 200480 kb
Host smart-2966a819-2987-453d-befe-d46a2fdb4540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23534754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.23534754
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.168163011
Short name T567
Test name
Test status
Simulation time 208280807 ps
CPU time 1.58 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:14 PM PDT 24
Peak memory 200428 kb
Host smart-946db9a6-49a3-4d07-83c9-36296b8c50b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168163011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.168163011
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1425911481
Short name T588
Test name
Test status
Simulation time 481491470 ps
CPU time 6.18 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:19 PM PDT 24
Peak memory 200396 kb
Host smart-fb5c17d2-ce78-402b-b0ad-0fb4f3422447
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425911481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
425911481
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.874504514
Short name T612
Test name
Test status
Simulation time 137494277 ps
CPU time 0.98 seconds
Started Jul 18 06:26:17 PM PDT 24
Finished Jul 18 06:26:20 PM PDT 24
Peak memory 200288 kb
Host smart-d6efff91-155b-4c6f-a6a2-5968737e5509
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874504514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.874504514
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3374533350
Short name T600
Test name
Test status
Simulation time 159666845 ps
CPU time 1.33 seconds
Started Jul 18 06:26:11 PM PDT 24
Finished Jul 18 06:26:15 PM PDT 24
Peak memory 208608 kb
Host smart-c3eef894-97b4-4d60-ad47-7433bb41284d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374533350 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3374533350
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2434025794
Short name T548
Test name
Test status
Simulation time 77317315 ps
CPU time 0.8 seconds
Started Jul 18 06:26:14 PM PDT 24
Finished Jul 18 06:26:18 PM PDT 24
Peak memory 200268 kb
Host smart-7b4b1320-d186-4629-95ff-0fc3d31ae0f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434025794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2434025794
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2668912268
Short name T601
Test name
Test status
Simulation time 260995292 ps
CPU time 1.62 seconds
Started Jul 18 06:26:17 PM PDT 24
Finished Jul 18 06:26:20 PM PDT 24
Peak memory 198488 kb
Host smart-12015057-4abd-4c40-b68d-2cf776611cb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668912268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2668912268
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2948907293
Short name T615
Test name
Test status
Simulation time 126488895 ps
CPU time 1.77 seconds
Started Jul 18 06:26:15 PM PDT 24
Finished Jul 18 06:26:19 PM PDT 24
Peak memory 211028 kb
Host smart-8015f89a-d7e8-4d48-8b48-96dbcace11dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948907293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2948907293
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.969830002
Short name T107
Test name
Test status
Simulation time 428036809 ps
CPU time 1.77 seconds
Started Jul 18 06:26:14 PM PDT 24
Finished Jul 18 06:26:19 PM PDT 24
Peak memory 200476 kb
Host smart-11043a7a-2a40-421a-a021-edee426a3e13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969830002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
969830002
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1197466032
Short name T564
Test name
Test status
Simulation time 364907159 ps
CPU time 2.37 seconds
Started Jul 18 06:26:14 PM PDT 24
Finished Jul 18 06:26:19 PM PDT 24
Peak memory 200468 kb
Host smart-5e4495e2-e62f-42f8-85ec-955574660619
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197466032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
197466032
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.850657186
Short name T545
Test name
Test status
Simulation time 483032675 ps
CPU time 5.93 seconds
Started Jul 18 06:26:11 PM PDT 24
Finished Jul 18 06:26:20 PM PDT 24
Peak memory 200364 kb
Host smart-5aa9281a-2c7d-451a-893a-dd1ff3ef8846
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850657186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.850657186
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1604017016
Short name T541
Test name
Test status
Simulation time 96790220 ps
CPU time 0.83 seconds
Started Jul 18 06:26:18 PM PDT 24
Finished Jul 18 06:26:21 PM PDT 24
Peak memory 200028 kb
Host smart-b8d63682-35a8-419c-8147-f16f1a361691
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604017016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
604017016
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2403291341
Short name T618
Test name
Test status
Simulation time 187241420 ps
CPU time 1.24 seconds
Started Jul 18 06:26:11 PM PDT 24
Finished Jul 18 06:26:14 PM PDT 24
Peak memory 200576 kb
Host smart-c9bb16a1-1da7-4d2e-a947-5954e7e0399e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403291341 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2403291341
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1167211486
Short name T594
Test name
Test status
Simulation time 87781784 ps
CPU time 1 seconds
Started Jul 18 06:26:18 PM PDT 24
Finished Jul 18 06:26:22 PM PDT 24
Peak memory 200288 kb
Host smart-d1b373e9-438a-49fe-aa1c-3d33cce7f574
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167211486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1167211486
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.500201479
Short name T597
Test name
Test status
Simulation time 82081063 ps
CPU time 1.04 seconds
Started Jul 18 06:26:19 PM PDT 24
Finished Jul 18 06:26:22 PM PDT 24
Peak memory 200344 kb
Host smart-fda65cb9-1e8c-40da-89cc-18b35d755354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500201479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.500201479
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.928601591
Short name T570
Test name
Test status
Simulation time 502941873 ps
CPU time 3.7 seconds
Started Jul 18 06:26:11 PM PDT 24
Finished Jul 18 06:26:17 PM PDT 24
Peak memory 208600 kb
Host smart-423f8833-5f5f-4ea6-aedf-6a08eedaffc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928601591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.928601591
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.430430423
Short name T90
Test name
Test status
Simulation time 807994573 ps
CPU time 2.8 seconds
Started Jul 18 06:26:18 PM PDT 24
Finished Jul 18 06:26:23 PM PDT 24
Peak memory 200388 kb
Host smart-73efa632-ad57-45c4-8e63-04e7092706af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430430423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
430430423
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2671987322
Short name T581
Test name
Test status
Simulation time 264329137 ps
CPU time 1.74 seconds
Started Jul 18 06:26:12 PM PDT 24
Finished Jul 18 06:26:16 PM PDT 24
Peak memory 200360 kb
Host smart-ab4c575f-3f72-4b93-8614-8caac3b6f175
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671987322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
671987322
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1807264775
Short name T55
Test name
Test status
Simulation time 794950219 ps
CPU time 4.25 seconds
Started Jul 18 06:26:12 PM PDT 24
Finished Jul 18 06:26:19 PM PDT 24
Peak memory 200344 kb
Host smart-fdf99c2d-c517-4043-a541-1469552112be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807264775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
807264775
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2955475025
Short name T604
Test name
Test status
Simulation time 102444972 ps
CPU time 0.86 seconds
Started Jul 18 06:26:18 PM PDT 24
Finished Jul 18 06:26:21 PM PDT 24
Peak memory 200168 kb
Host smart-bff7ec3e-8daf-47c3-a97e-0a18aebd571a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955475025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
955475025
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3170592591
Short name T590
Test name
Test status
Simulation time 133035554 ps
CPU time 1.05 seconds
Started Jul 18 06:26:16 PM PDT 24
Finished Jul 18 06:26:19 PM PDT 24
Peak memory 200400 kb
Host smart-3033e567-5f42-45e8-b770-6f281efe6f1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170592591 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3170592591
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3925007106
Short name T543
Test name
Test status
Simulation time 74956143 ps
CPU time 0.85 seconds
Started Jul 18 06:26:12 PM PDT 24
Finished Jul 18 06:26:15 PM PDT 24
Peak memory 200176 kb
Host smart-300167b5-be87-4fc2-a4dd-3106a0799b7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925007106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3925007106
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.753867485
Short name T57
Test name
Test status
Simulation time 157986119 ps
CPU time 1.26 seconds
Started Jul 18 06:26:17 PM PDT 24
Finished Jul 18 06:26:20 PM PDT 24
Peak memory 200292 kb
Host smart-1d03dc98-67c1-48e7-8dcb-a7190c88af69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753867485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.753867485
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1231501282
Short name T60
Test name
Test status
Simulation time 494742686 ps
CPU time 3.66 seconds
Started Jul 18 06:26:11 PM PDT 24
Finished Jul 18 06:26:17 PM PDT 24
Peak memory 208664 kb
Host smart-ffee64e4-e53a-4ba4-b6db-25e169cda3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231501282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1231501282
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1957796635
Short name T129
Test name
Test status
Simulation time 934699327 ps
CPU time 3.36 seconds
Started Jul 18 06:26:16 PM PDT 24
Finished Jul 18 06:26:21 PM PDT 24
Peak memory 200468 kb
Host smart-a291de78-1b00-476c-84ce-401c18438b8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957796635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1957796635
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.465731223
Short name T578
Test name
Test status
Simulation time 217746446 ps
CPU time 1.38 seconds
Started Jul 18 06:26:14 PM PDT 24
Finished Jul 18 06:26:18 PM PDT 24
Peak memory 208612 kb
Host smart-bd77fe0d-ddc6-41f3-8044-8ca7e61b58dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465731223 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.465731223
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.842644796
Short name T582
Test name
Test status
Simulation time 61902792 ps
CPU time 0.8 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:12 PM PDT 24
Peak memory 200276 kb
Host smart-ede1a7d3-5348-4f39-817b-66f93b957bf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842644796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.842644796
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.169785978
Short name T102
Test name
Test status
Simulation time 74818612 ps
CPU time 0.88 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:12 PM PDT 24
Peak memory 200328 kb
Host smart-cf20b0f4-cc2e-46e0-b754-90373fc9594d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169785978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.169785978
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2292696232
Short name T611
Test name
Test status
Simulation time 235068012 ps
CPU time 3.72 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:15 PM PDT 24
Peak memory 208688 kb
Host smart-ad66e35e-988d-44ba-84e1-a5550a33124e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292696232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2292696232
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1888259384
Short name T110
Test name
Test status
Simulation time 874376077 ps
CPU time 3.47 seconds
Started Jul 18 06:26:14 PM PDT 24
Finished Jul 18 06:26:20 PM PDT 24
Peak memory 200476 kb
Host smart-c9a68620-5005-48a7-b969-c0afc8fdcfd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888259384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1888259384
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1773138205
Short name T580
Test name
Test status
Simulation time 190162192 ps
CPU time 1.32 seconds
Started Jul 18 06:26:11 PM PDT 24
Finished Jul 18 06:26:15 PM PDT 24
Peak memory 208604 kb
Host smart-2c71a74e-7c0d-4a93-bd59-1f53e62a2b06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773138205 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1773138205
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4131037114
Short name T106
Test name
Test status
Simulation time 79582709 ps
CPU time 0.82 seconds
Started Jul 18 06:26:11 PM PDT 24
Finished Jul 18 06:26:15 PM PDT 24
Peak memory 200276 kb
Host smart-930922db-edec-4e4e-a5d4-28ded6dbbb9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131037114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.4131037114
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1582333582
Short name T99
Test name
Test status
Simulation time 77940102 ps
CPU time 0.97 seconds
Started Jul 18 06:26:14 PM PDT 24
Finished Jul 18 06:26:17 PM PDT 24
Peak memory 200420 kb
Host smart-7f57c81b-af0a-42d3-9286-14fc0993545e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582333582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1582333582
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.853939627
Short name T596
Test name
Test status
Simulation time 113912280 ps
CPU time 1.65 seconds
Started Jul 18 06:26:17 PM PDT 24
Finished Jul 18 06:26:20 PM PDT 24
Peak memory 206684 kb
Host smart-db052b3e-6bd8-4830-8211-03e033aa3608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853939627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.853939627
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1075484010
Short name T108
Test name
Test status
Simulation time 554026839 ps
CPU time 2 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:14 PM PDT 24
Peak memory 200544 kb
Host smart-9fbdf74d-685d-45b6-b709-b60bb805f2da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075484010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1075484010
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3084980047
Short name T613
Test name
Test status
Simulation time 103315009 ps
CPU time 0.99 seconds
Started Jul 18 06:26:11 PM PDT 24
Finished Jul 18 06:26:14 PM PDT 24
Peak memory 208504 kb
Host smart-8f594684-268d-406f-b306-802b69dc3c30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084980047 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3084980047
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2703030062
Short name T542
Test name
Test status
Simulation time 92358439 ps
CPU time 0.96 seconds
Started Jul 18 06:26:15 PM PDT 24
Finished Jul 18 06:26:18 PM PDT 24
Peak memory 200292 kb
Host smart-e9170019-b033-472c-9bdd-cb44e5516e57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703030062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2703030062
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1812781843
Short name T579
Test name
Test status
Simulation time 246083854 ps
CPU time 1.6 seconds
Started Jul 18 06:26:12 PM PDT 24
Finished Jul 18 06:26:16 PM PDT 24
Peak memory 200432 kb
Host smart-063a1975-5db2-4cbe-9f08-129c522024a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812781843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1812781843
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2368525420
Short name T592
Test name
Test status
Simulation time 102540780 ps
CPU time 1.53 seconds
Started Jul 18 06:26:15 PM PDT 24
Finished Jul 18 06:26:19 PM PDT 24
Peak memory 208612 kb
Host smart-a224742a-f65b-4b77-9769-93a50bf505e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368525420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2368525420
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3973587730
Short name T552
Test name
Test status
Simulation time 118025178 ps
CPU time 1.4 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:13 PM PDT 24
Peak memory 208540 kb
Host smart-56b9d096-8a44-47d3-94c8-507f8b810d77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973587730 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3973587730
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1910581545
Short name T104
Test name
Test status
Simulation time 63239713 ps
CPU time 0.78 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:13 PM PDT 24
Peak memory 200284 kb
Host smart-0cd7b82e-1c4d-4422-a8e3-6237cc89c8bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910581545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1910581545
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2350465005
Short name T606
Test name
Test status
Simulation time 85114451 ps
CPU time 0.98 seconds
Started Jul 18 06:26:14 PM PDT 24
Finished Jul 18 06:26:18 PM PDT 24
Peak memory 200332 kb
Host smart-864f7f9a-150d-4cd4-ae98-069ab8610fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350465005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2350465005
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1773507059
Short name T566
Test name
Test status
Simulation time 91202075 ps
CPU time 1.29 seconds
Started Jul 18 06:26:13 PM PDT 24
Finished Jul 18 06:26:16 PM PDT 24
Peak memory 208460 kb
Host smart-70e0bcb6-243e-4927-b125-34967c3c2e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773507059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1773507059
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4233256877
Short name T584
Test name
Test status
Simulation time 461788103 ps
CPU time 2.07 seconds
Started Jul 18 06:26:10 PM PDT 24
Finished Jul 18 06:26:15 PM PDT 24
Peak memory 200504 kb
Host smart-3c56b1cb-9b3c-4ada-9395-70c81ab0db3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233256877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.4233256877
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1920285673
Short name T555
Test name
Test status
Simulation time 182162665 ps
CPU time 1.61 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:38 PM PDT 24
Peak memory 208740 kb
Host smart-d84a96b6-137f-4647-983b-6730d05ae453
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920285673 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1920285673
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2439138042
Short name T553
Test name
Test status
Simulation time 70037515 ps
CPU time 0.8 seconds
Started Jul 18 06:26:11 PM PDT 24
Finished Jul 18 06:26:15 PM PDT 24
Peak memory 200296 kb
Host smart-8d76fe2d-d245-4780-ad4d-5d0a3aa4c948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439138042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2439138042
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4135578820
Short name T563
Test name
Test status
Simulation time 79860637 ps
CPU time 1.07 seconds
Started Jul 18 06:26:32 PM PDT 24
Finished Jul 18 06:26:37 PM PDT 24
Peak memory 200412 kb
Host smart-45170f18-eed1-4640-943f-2bf3962b3f0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135578820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.4135578820
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3019107162
Short name T602
Test name
Test status
Simulation time 876835491 ps
CPU time 3.12 seconds
Started Jul 18 06:26:18 PM PDT 24
Finished Jul 18 06:26:24 PM PDT 24
Peak memory 200368 kb
Host smart-424558d5-de89-4263-88a1-d04aef318b63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019107162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3019107162
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2992231328
Short name T447
Test name
Test status
Simulation time 75741594 ps
CPU time 0.82 seconds
Started Jul 18 05:58:49 PM PDT 24
Finished Jul 18 05:58:52 PM PDT 24
Peak memory 200260 kb
Host smart-b495e005-7475-45ff-82d2-5adf166e6e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992231328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2992231328
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2192052462
Short name T22
Test name
Test status
Simulation time 1888423867 ps
CPU time 6.95 seconds
Started Jul 18 05:58:48 PM PDT 24
Finished Jul 18 05:58:58 PM PDT 24
Peak memory 229960 kb
Host smart-d860a0e5-28e1-4860-9ece-fb7736a0a89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192052462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2192052462
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2581065944
Short name T243
Test name
Test status
Simulation time 244665277 ps
CPU time 1.07 seconds
Started Jul 18 05:58:50 PM PDT 24
Finished Jul 18 05:58:53 PM PDT 24
Peak memory 217500 kb
Host smart-990ab37a-0581-40cf-9627-c2721e6bc9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581065944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2581065944
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3603572415
Short name T74
Test name
Test status
Simulation time 136369315 ps
CPU time 0.77 seconds
Started Jul 18 05:58:32 PM PDT 24
Finished Jul 18 05:58:42 PM PDT 24
Peak memory 200268 kb
Host smart-f9900f4a-6efc-4f05-ba26-63953932c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603572415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3603572415
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2253062289
Short name T459
Test name
Test status
Simulation time 694917595 ps
CPU time 4.19 seconds
Started Jul 18 05:58:40 PM PDT 24
Finished Jul 18 05:58:50 PM PDT 24
Peak memory 200736 kb
Host smart-a279091a-7bdf-47b0-941f-755223825058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253062289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2253062289
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2758345213
Short name T420
Test name
Test status
Simulation time 171955415 ps
CPU time 1.15 seconds
Started Jul 18 05:58:48 PM PDT 24
Finished Jul 18 05:58:51 PM PDT 24
Peak memory 200432 kb
Host smart-8b54cf59-82da-4b70-a826-77bbe319588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758345213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2758345213
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3173674888
Short name T269
Test name
Test status
Simulation time 223745723 ps
CPU time 1.44 seconds
Started Jul 18 05:58:38 PM PDT 24
Finished Jul 18 05:58:46 PM PDT 24
Peak memory 200664 kb
Host smart-fc3e3522-6f1b-4303-baf0-f6dc6ad06295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173674888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3173674888
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2955905025
Short name T478
Test name
Test status
Simulation time 4042697691 ps
CPU time 19.47 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 209048 kb
Host smart-9e26d357-3219-4240-b23a-4100a752248f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955905025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2955905025
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1429300940
Short name T414
Test name
Test status
Simulation time 157040295 ps
CPU time 1.89 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:03 PM PDT 24
Peak memory 200480 kb
Host smart-06789b5b-78f5-4b16-a082-0a13a80574c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429300940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1429300940
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.833524751
Short name T175
Test name
Test status
Simulation time 118455334 ps
CPU time 1.07 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:05 PM PDT 24
Peak memory 200476 kb
Host smart-79d51701-1d1e-4a4a-a233-3f70b87238b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833524751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.833524751
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2216566214
Short name T213
Test name
Test status
Simulation time 69613702 ps
CPU time 0.89 seconds
Started Jul 18 05:58:56 PM PDT 24
Finished Jul 18 05:59:06 PM PDT 24
Peak memory 200272 kb
Host smart-11c2a7bd-943b-447a-b442-aa8dd8020fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216566214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2216566214
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3031050765
Short name T312
Test name
Test status
Simulation time 244496289 ps
CPU time 1.07 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:58:59 PM PDT 24
Peak memory 217464 kb
Host smart-0699d5e4-0701-42b0-aa49-3dc309b4170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031050765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3031050765
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2089942283
Short name T373
Test name
Test status
Simulation time 107327124 ps
CPU time 0.82 seconds
Started Jul 18 05:58:49 PM PDT 24
Finished Jul 18 05:58:52 PM PDT 24
Peak memory 200280 kb
Host smart-b707b605-e3c7-4bb1-99c9-2c29178cc622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089942283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2089942283
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.625551043
Short name T365
Test name
Test status
Simulation time 1589627808 ps
CPU time 5.64 seconds
Started Jul 18 05:58:51 PM PDT 24
Finished Jul 18 05:59:00 PM PDT 24
Peak memory 200672 kb
Host smart-93fecc8d-9052-48b1-ae5f-6d39f9abb332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625551043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.625551043
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3388409728
Short name T69
Test name
Test status
Simulation time 17638794107 ps
CPU time 24.56 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:28 PM PDT 24
Peak memory 217540 kb
Host smart-abb0d736-5d49-4eee-997f-ab1e566ca579
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388409728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3388409728
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2916158440
Short name T237
Test name
Test status
Simulation time 106944849 ps
CPU time 1.01 seconds
Started Jul 18 05:58:49 PM PDT 24
Finished Jul 18 05:58:52 PM PDT 24
Peak memory 200244 kb
Host smart-0c8c7a28-0cbf-4e2e-b1f3-216e9cf78377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916158440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2916158440
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3352178266
Short name T46
Test name
Test status
Simulation time 3310550505 ps
CPU time 13.71 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:14 PM PDT 24
Peak memory 200720 kb
Host smart-e885a8dd-7239-41e7-adab-793d770fb2ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352178266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3352178266
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3204385078
Short name T219
Test name
Test status
Simulation time 334190631 ps
CPU time 2.06 seconds
Started Jul 18 05:58:49 PM PDT 24
Finished Jul 18 05:58:53 PM PDT 24
Peak memory 200280 kb
Host smart-056a19f2-5cf5-446a-ba61-fa11d2a1446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204385078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3204385078
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.176926427
Short name T336
Test name
Test status
Simulation time 66070824 ps
CPU time 0.81 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:25 PM PDT 24
Peak memory 200172 kb
Host smart-0d6fe4a2-27f8-4c28-8b7f-143d087d501d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176926427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.176926427
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3893023410
Short name T352
Test name
Test status
Simulation time 1223705267 ps
CPU time 5.83 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:24 PM PDT 24
Peak memory 217840 kb
Host smart-c4a41df0-89f7-446d-83b5-cdd43ddbff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893023410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3893023410
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.982656043
Short name T517
Test name
Test status
Simulation time 244610728 ps
CPU time 1.06 seconds
Started Jul 18 05:59:08 PM PDT 24
Finished Jul 18 05:59:15 PM PDT 24
Peak memory 217384 kb
Host smart-3cb08575-cb03-4d82-a791-415f48e0fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982656043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.982656043
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3112748177
Short name T311
Test name
Test status
Simulation time 111082879 ps
CPU time 0.81 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:01 PM PDT 24
Peak memory 200280 kb
Host smart-c70b780f-1592-49e9-81b7-25c7ea8d1afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112748177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3112748177
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3179053073
Short name T190
Test name
Test status
Simulation time 927962474 ps
CPU time 4.34 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:08 PM PDT 24
Peak memory 200740 kb
Host smart-b06b062f-1837-4896-9c58-bda74ecad122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179053073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3179053073
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.675217101
Short name T232
Test name
Test status
Simulation time 97026904 ps
CPU time 1.03 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 200440 kb
Host smart-a790a514-9d18-490e-a211-369dd7dc9381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675217101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.675217101
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2115698814
Short name T395
Test name
Test status
Simulation time 250704101 ps
CPU time 1.42 seconds
Started Jul 18 05:58:56 PM PDT 24
Finished Jul 18 05:59:07 PM PDT 24
Peak memory 200676 kb
Host smart-757c9315-e1bc-46ed-8388-f1a4cbc06408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115698814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2115698814
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3491106318
Short name T82
Test name
Test status
Simulation time 4122971342 ps
CPU time 19.85 seconds
Started Jul 18 05:59:10 PM PDT 24
Finished Jul 18 05:59:35 PM PDT 24
Peak memory 210584 kb
Host smart-2ff09b95-46b5-4c2f-a3dc-ab5688955ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491106318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3491106318
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1517251077
Short name T462
Test name
Test status
Simulation time 282448970 ps
CPU time 1.94 seconds
Started Jul 18 05:58:59 PM PDT 24
Finished Jul 18 05:59:10 PM PDT 24
Peak memory 200496 kb
Host smart-6b45ad5d-4e7a-4211-9e65-48173a7e34f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517251077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1517251077
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.4266709489
Short name T435
Test name
Test status
Simulation time 66990228 ps
CPU time 0.78 seconds
Started Jul 18 05:58:56 PM PDT 24
Finished Jul 18 05:59:06 PM PDT 24
Peak memory 200472 kb
Host smart-116237da-4384-4a3e-872d-dc2e1de7bbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266709489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.4266709489
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3795710204
Short name T38
Test name
Test status
Simulation time 76695433 ps
CPU time 0.83 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:24 PM PDT 24
Peak memory 200284 kb
Host smart-99bdfd29-5902-4352-83de-895401af1ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795710204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3795710204
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.9347600
Short name T490
Test name
Test status
Simulation time 1894845394 ps
CPU time 7.1 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 221436 kb
Host smart-e99730ff-7e27-4115-868f-834c9682aa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9347600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.9347600
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.554341502
Short name T137
Test name
Test status
Simulation time 243987577 ps
CPU time 1.14 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 05:59:28 PM PDT 24
Peak memory 217500 kb
Host smart-0b5a00bc-ebc4-44f0-b531-8b0f6eaf2dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554341502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.554341502
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1090272504
Short name T249
Test name
Test status
Simulation time 134406972 ps
CPU time 0.9 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:25 PM PDT 24
Peak memory 200168 kb
Host smart-9988ce29-cffc-4c27-8be9-5bbaf4b35535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090272504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1090272504
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.143447027
Short name T533
Test name
Test status
Simulation time 730580981 ps
CPU time 4.03 seconds
Started Jul 18 05:59:09 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 200728 kb
Host smart-a19fd08e-c32b-4636-80bd-92ae5b4b3027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143447027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.143447027
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2225989012
Short name T445
Test name
Test status
Simulation time 172538542 ps
CPU time 1.23 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:19 PM PDT 24
Peak memory 200464 kb
Host smart-8d2f9f7e-9777-4a8a-8335-7c071d51b4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225989012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2225989012
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.787720199
Short name T71
Test name
Test status
Simulation time 202123814 ps
CPU time 1.61 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:19 PM PDT 24
Peak memory 200668 kb
Host smart-8d4635cc-2353-40c1-8994-89960127703b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787720199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.787720199
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1929308639
Short name T81
Test name
Test status
Simulation time 2994726292 ps
CPU time 13.16 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:37 PM PDT 24
Peak memory 209016 kb
Host smart-a3df2644-6780-4069-9d78-53b78a8a1701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929308639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1929308639
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1567759507
Short name T266
Test name
Test status
Simulation time 387459579 ps
CPU time 2.15 seconds
Started Jul 18 05:59:13 PM PDT 24
Finished Jul 18 05:59:25 PM PDT 24
Peak memory 208736 kb
Host smart-a3e4b2ab-f10b-4575-87d6-b11fab5e9732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567759507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1567759507
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2092670025
Short name T227
Test name
Test status
Simulation time 85367431 ps
CPU time 0.88 seconds
Started Jul 18 05:59:09 PM PDT 24
Finished Jul 18 05:59:16 PM PDT 24
Peak memory 200444 kb
Host smart-33dc7df3-7072-4db6-a329-b6e0d852f1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092670025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2092670025
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3435911899
Short name T258
Test name
Test status
Simulation time 59616590 ps
CPU time 0.72 seconds
Started Jul 18 05:59:13 PM PDT 24
Finished Jul 18 05:59:22 PM PDT 24
Peak memory 200272 kb
Host smart-31fdb7b2-fe49-4b42-a493-590a73192f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435911899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3435911899
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2929415461
Short name T461
Test name
Test status
Simulation time 1884378318 ps
CPU time 7.14 seconds
Started Jul 18 05:59:13 PM PDT 24
Finished Jul 18 05:59:28 PM PDT 24
Peak memory 217808 kb
Host smart-c19c5bfb-ca60-419b-8209-85e41758449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929415461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2929415461
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1579005690
Short name T144
Test name
Test status
Simulation time 243577406 ps
CPU time 1.04 seconds
Started Jul 18 05:59:12 PM PDT 24
Finished Jul 18 05:59:21 PM PDT 24
Peak memory 217452 kb
Host smart-3fce2d6c-4805-4ed7-a3b7-8e8586b0f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579005690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1579005690
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2506054122
Short name T476
Test name
Test status
Simulation time 97700989 ps
CPU time 0.75 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 200300 kb
Host smart-b0be6b83-b90c-4dcb-aeb1-68a6f6ff1814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506054122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2506054122
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2278735185
Short name T147
Test name
Test status
Simulation time 1204910158 ps
CPU time 4.83 seconds
Started Jul 18 05:59:12 PM PDT 24
Finished Jul 18 05:59:24 PM PDT 24
Peak memory 200792 kb
Host smart-e2f97420-8d18-45d0-add2-4d30fbd6d04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278735185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2278735185
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.249610306
Short name T337
Test name
Test status
Simulation time 102079978 ps
CPU time 1.06 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 05:59:28 PM PDT 24
Peak memory 200464 kb
Host smart-10da9b31-2abd-4728-8cea-77cdb498be22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249610306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.249610306
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.162456415
Short name T224
Test name
Test status
Simulation time 261366090 ps
CPU time 1.58 seconds
Started Jul 18 05:59:12 PM PDT 24
Finished Jul 18 05:59:21 PM PDT 24
Peak memory 200692 kb
Host smart-2ca73a95-b31b-49a2-a608-cb9b76403818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162456415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.162456415
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2857400043
Short name T214
Test name
Test status
Simulation time 4811735063 ps
CPU time 22.48 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 05:59:50 PM PDT 24
Peak memory 208992 kb
Host smart-b2e58a00-e94f-41e3-ac16-0207924a6bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857400043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2857400043
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.4233436842
Short name T453
Test name
Test status
Simulation time 454068595 ps
CPU time 2.69 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:27 PM PDT 24
Peak memory 200472 kb
Host smart-d4babec4-e5e4-4bc0-8f0b-eb5af0d69820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233436842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.4233436842
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.4097015813
Short name T430
Test name
Test status
Simulation time 113698435 ps
CPU time 1.06 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200484 kb
Host smart-deb8aab0-7aee-40ec-b893-aa77e1ad5633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097015813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.4097015813
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.935169032
Short name T200
Test name
Test status
Simulation time 82898033 ps
CPU time 0.87 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 05:59:28 PM PDT 24
Peak memory 200232 kb
Host smart-c9577565-c1bd-447f-bbd5-f26e607b58a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935169032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.935169032
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.970196474
Short name T346
Test name
Test status
Simulation time 2177169879 ps
CPU time 7.29 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:38 PM PDT 24
Peak memory 217124 kb
Host smart-3a3771b1-951b-4b90-abb0-bf6df44bd8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970196474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.970196474
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.526526875
Short name T182
Test name
Test status
Simulation time 243791270 ps
CPU time 1.13 seconds
Started Jul 18 05:59:23 PM PDT 24
Finished Jul 18 05:59:36 PM PDT 24
Peak memory 217544 kb
Host smart-c7835dcf-47d0-4eb2-a733-565cfc5821c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526526875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.526526875
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3123580899
Short name T16
Test name
Test status
Simulation time 213574840 ps
CPU time 1 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:30 PM PDT 24
Peak memory 200272 kb
Host smart-d0fc73fb-aac2-4688-b2bd-586e0bc4094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123580899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3123580899
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3284448508
Short name T342
Test name
Test status
Simulation time 1267751772 ps
CPU time 5.18 seconds
Started Jul 18 05:59:15 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200784 kb
Host smart-08c8280e-6547-4ced-bf23-b689ddfc2116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284448508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3284448508
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2117232217
Short name T303
Test name
Test status
Simulation time 155160409 ps
CPU time 1.12 seconds
Started Jul 18 05:59:21 PM PDT 24
Finished Jul 18 05:59:35 PM PDT 24
Peak memory 200272 kb
Host smart-1d3af5f4-dca4-4302-8d3e-a6b9258069d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117232217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2117232217
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1495616970
Short name T386
Test name
Test status
Simulation time 118151091 ps
CPU time 1.19 seconds
Started Jul 18 05:59:13 PM PDT 24
Finished Jul 18 05:59:22 PM PDT 24
Peak memory 200672 kb
Host smart-decc8dfd-089a-4247-af24-33927871164a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495616970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1495616970
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3295140954
Short name T472
Test name
Test status
Simulation time 4547908456 ps
CPU time 19.45 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:50 PM PDT 24
Peak memory 200800 kb
Host smart-7b29ae3b-152e-4716-be84-22a3a6055c93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295140954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3295140954
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.662533390
Short name T512
Test name
Test status
Simulation time 147987142 ps
CPU time 1.83 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 200480 kb
Host smart-0989f8fd-7a89-4a94-83a4-a0d3219b89ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662533390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.662533390
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1966439237
Short name T534
Test name
Test status
Simulation time 131481998 ps
CPU time 0.97 seconds
Started Jul 18 05:59:17 PM PDT 24
Finished Jul 18 05:59:29 PM PDT 24
Peak memory 200484 kb
Host smart-ead243f2-e8e4-477d-b3bf-03fbfa4ca46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966439237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1966439237
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3085281803
Short name T248
Test name
Test status
Simulation time 71355386 ps
CPU time 0.77 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200260 kb
Host smart-267d953f-d31b-4056-af8b-a379e76cef4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085281803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3085281803
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2220743687
Short name T163
Test name
Test status
Simulation time 243745469 ps
CPU time 1.03 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 217480 kb
Host smart-6432ae47-9916-48ca-be33-4eb93e224acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220743687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2220743687
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1010989014
Short name T192
Test name
Test status
Simulation time 173191213 ps
CPU time 0.85 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200276 kb
Host smart-00e7c86f-10e9-41fe-86c6-c19ac34416db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010989014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1010989014
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2531826565
Short name T304
Test name
Test status
Simulation time 1464843083 ps
CPU time 6.68 seconds
Started Jul 18 05:59:20 PM PDT 24
Finished Jul 18 05:59:38 PM PDT 24
Peak memory 200728 kb
Host smart-399b6978-39a5-4f69-ab54-63ca36d25673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531826565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2531826565
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.239472153
Short name T371
Test name
Test status
Simulation time 147442637 ps
CPU time 1.09 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200464 kb
Host smart-ead31737-bdcc-4637-86f9-0ca617ba01cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239472153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.239472153
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1835025779
Short name T40
Test name
Test status
Simulation time 192071497 ps
CPU time 1.42 seconds
Started Jul 18 05:59:22 PM PDT 24
Finished Jul 18 05:59:36 PM PDT 24
Peak memory 200672 kb
Host smart-4d5e2f2e-fd12-4c3a-8e24-2e46fac496a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835025779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1835025779
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.4165395501
Short name T349
Test name
Test status
Simulation time 4095099819 ps
CPU time 13.72 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:44 PM PDT 24
Peak memory 209008 kb
Host smart-e683db6d-1a65-488c-8640-82540b3321eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165395501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.4165395501
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1330178002
Short name T350
Test name
Test status
Simulation time 117318840 ps
CPU time 1.47 seconds
Started Jul 18 05:59:21 PM PDT 24
Finished Jul 18 05:59:35 PM PDT 24
Peak memory 200468 kb
Host smart-ad907858-11dd-4960-a3fd-bf12ee2834b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330178002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1330178002
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2325403125
Short name T439
Test name
Test status
Simulation time 230874091 ps
CPU time 1.37 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 05:59:29 PM PDT 24
Peak memory 200620 kb
Host smart-321c3d2e-fe86-43cb-9ee1-c3b40cc12287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325403125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2325403125
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.890650385
Short name T402
Test name
Test status
Simulation time 78482010 ps
CPU time 0.77 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 200284 kb
Host smart-f8868d87-ae9b-4826-90b4-03cc2c88253f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890650385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.890650385
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3738968406
Short name T330
Test name
Test status
Simulation time 2348039728 ps
CPU time 8.71 seconds
Started Jul 18 05:59:08 PM PDT 24
Finished Jul 18 05:59:23 PM PDT 24
Peak memory 221824 kb
Host smart-93568783-3a84-4fd9-b506-1efe1dff8af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738968406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3738968406
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2668444970
Short name T419
Test name
Test status
Simulation time 244363200 ps
CPU time 1.04 seconds
Started Jul 18 05:59:12 PM PDT 24
Finished Jul 18 05:59:21 PM PDT 24
Peak memory 217516 kb
Host smart-99eb8d4b-3ea5-468b-8e47-566de4cbd912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668444970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2668444970
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2614336314
Short name T254
Test name
Test status
Simulation time 202990655 ps
CPU time 0.97 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 200256 kb
Host smart-d7a7627e-dbbe-4c49-9b4f-bd44cbb78e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614336314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2614336314
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1822123363
Short name T501
Test name
Test status
Simulation time 2105205782 ps
CPU time 7.22 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:38 PM PDT 24
Peak memory 200720 kb
Host smart-12476497-5897-4b51-a174-dbdd44f7a1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822123363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1822123363
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.14524820
Short name T437
Test name
Test status
Simulation time 171327910 ps
CPU time 1.12 seconds
Started Jul 18 05:59:21 PM PDT 24
Finished Jul 18 05:59:35 PM PDT 24
Peak memory 200476 kb
Host smart-7c881817-13ff-43ed-85e0-b83015bdbf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14524820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.14524820
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.674391731
Short name T500
Test name
Test status
Simulation time 229984978 ps
CPU time 1.46 seconds
Started Jul 18 05:59:22 PM PDT 24
Finished Jul 18 05:59:36 PM PDT 24
Peak memory 200660 kb
Host smart-4f33b300-fa3f-4761-9938-7f8aabdaceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674391731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.674391731
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3831771779
Short name T204
Test name
Test status
Simulation time 333207619 ps
CPU time 2.02 seconds
Started Jul 18 05:59:15 PM PDT 24
Finished Jul 18 05:59:27 PM PDT 24
Peak memory 200668 kb
Host smart-10dc93f0-e99b-47c9-b721-5bcc744a0272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831771779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3831771779
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2826538159
Short name T275
Test name
Test status
Simulation time 424190999 ps
CPU time 2.22 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:33 PM PDT 24
Peak memory 208692 kb
Host smart-25ba7904-9be5-45bd-a814-2b1cb69418cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826538159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2826538159
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1100824765
Short name T313
Test name
Test status
Simulation time 127066114 ps
CPU time 1.05 seconds
Started Jul 18 05:59:17 PM PDT 24
Finished Jul 18 05:59:29 PM PDT 24
Peak memory 200484 kb
Host smart-9b84deac-fb6d-4738-8322-730f3aaf8d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100824765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1100824765
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.957339391
Short name T458
Test name
Test status
Simulation time 75831505 ps
CPU time 0.77 seconds
Started Jul 18 05:59:10 PM PDT 24
Finished Jul 18 05:59:16 PM PDT 24
Peak memory 200208 kb
Host smart-5fa2158e-d2d8-4ce2-b712-adf01d734be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957339391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.957339391
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2847215362
Short name T29
Test name
Test status
Simulation time 1898382000 ps
CPU time 7.56 seconds
Started Jul 18 05:59:13 PM PDT 24
Finished Jul 18 05:59:30 PM PDT 24
Peak memory 221736 kb
Host smart-099f48fa-de99-400a-b71c-06b590854d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847215362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2847215362
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.108099529
Short name T234
Test name
Test status
Simulation time 251485052 ps
CPU time 1.01 seconds
Started Jul 18 05:59:15 PM PDT 24
Finished Jul 18 05:59:26 PM PDT 24
Peak memory 217416 kb
Host smart-b813637a-0604-4125-acbd-cd874176b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108099529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.108099529
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1331957701
Short name T287
Test name
Test status
Simulation time 171488706 ps
CPU time 0.88 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 200284 kb
Host smart-882bc31d-66df-4dcb-bd6e-c044dc408691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331957701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1331957701
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.728086101
Short name T133
Test name
Test status
Simulation time 767575721 ps
CPU time 3.68 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:21 PM PDT 24
Peak memory 200744 kb
Host smart-963eb208-555a-4c08-b280-9d41c740d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728086101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.728086101
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.920627168
Short name T383
Test name
Test status
Simulation time 102077396 ps
CPU time 1.02 seconds
Started Jul 18 05:59:13 PM PDT 24
Finished Jul 18 05:59:24 PM PDT 24
Peak memory 200488 kb
Host smart-f6da71c1-697e-4d03-9704-89b881de8c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920627168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.920627168
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2753214289
Short name T358
Test name
Test status
Simulation time 119439690 ps
CPU time 1.25 seconds
Started Jul 18 05:59:10 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 200676 kb
Host smart-9a4368ef-355e-46a1-99f6-cd775d0f842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753214289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2753214289
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.554761843
Short name T307
Test name
Test status
Simulation time 7079926122 ps
CPU time 32.42 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 06:00:00 PM PDT 24
Peak memory 208996 kb
Host smart-afc3ac3a-d7d6-41cc-80ce-06041f50cdbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554761843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.554761843
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3686235133
Short name T273
Test name
Test status
Simulation time 459325299 ps
CPU time 2.48 seconds
Started Jul 18 05:59:12 PM PDT 24
Finished Jul 18 05:59:21 PM PDT 24
Peak memory 200488 kb
Host smart-5c5acec2-6a72-4b6c-854a-9aae88de506f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686235133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3686235133
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.886402954
Short name T376
Test name
Test status
Simulation time 127571525 ps
CPU time 1.1 seconds
Started Jul 18 05:59:15 PM PDT 24
Finished Jul 18 05:59:27 PM PDT 24
Peak memory 200468 kb
Host smart-0434fdaf-8980-41dd-9d5d-8a7e1c78ac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886402954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.886402954
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2965041467
Short name T215
Test name
Test status
Simulation time 60154942 ps
CPU time 0.75 seconds
Started Jul 18 05:59:15 PM PDT 24
Finished Jul 18 05:59:27 PM PDT 24
Peak memory 200260 kb
Host smart-36f5fdd3-3ae5-450e-8b40-2e20e6b1d480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965041467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2965041467
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2635643835
Short name T327
Test name
Test status
Simulation time 1234001903 ps
CPU time 5.41 seconds
Started Jul 18 05:59:15 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 221752 kb
Host smart-022afdfe-1981-4a39-93b0-198d25544b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635643835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2635643835
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3699855170
Short name T422
Test name
Test status
Simulation time 243578543 ps
CPU time 1.21 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:24 PM PDT 24
Peak memory 217404 kb
Host smart-4aa52c3d-ab10-4756-9af7-32b293b4fc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699855170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3699855170
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1213867462
Short name T159
Test name
Test status
Simulation time 96534399 ps
CPU time 0.78 seconds
Started Jul 18 05:59:10 PM PDT 24
Finished Jul 18 05:59:17 PM PDT 24
Peak memory 200248 kb
Host smart-40ab9e52-ba33-428f-9ade-272aec402488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213867462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1213867462
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1318017298
Short name T410
Test name
Test status
Simulation time 1257924734 ps
CPU time 4.74 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 200732 kb
Host smart-d200e950-0245-477c-8741-6a57c1458297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318017298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1318017298
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2540789128
Short name T267
Test name
Test status
Simulation time 182579966 ps
CPU time 1.19 seconds
Started Jul 18 05:59:13 PM PDT 24
Finished Jul 18 05:59:24 PM PDT 24
Peak memory 200672 kb
Host smart-85e89bb7-0f54-4720-9d5d-f5769737a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540789128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2540789128
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2462931356
Short name T127
Test name
Test status
Simulation time 258190352 ps
CPU time 1.51 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:19 PM PDT 24
Peak memory 200696 kb
Host smart-7ce15c1f-892c-494d-8118-fc97176db8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462931356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2462931356
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.244793740
Short name T229
Test name
Test status
Simulation time 3737109273 ps
CPU time 14.25 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:39 PM PDT 24
Peak memory 216532 kb
Host smart-adddf690-e817-4bc3-a15c-bc25b2f3357c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244793740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.244793740
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1458123878
Short name T341
Test name
Test status
Simulation time 142873000 ps
CPU time 1.8 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:20 PM PDT 24
Peak memory 200468 kb
Host smart-880504c2-9a7f-4b95-b30d-3f4f5f71d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458123878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1458123878
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2658440044
Short name T139
Test name
Test status
Simulation time 158564704 ps
CPU time 1.11 seconds
Started Jul 18 05:59:09 PM PDT 24
Finished Jul 18 05:59:16 PM PDT 24
Peak memory 200392 kb
Host smart-d8d66322-67e4-48bc-b872-36a79dcf6d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658440044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2658440044
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2878243526
Short name T180
Test name
Test status
Simulation time 69692312 ps
CPU time 0.79 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 05:59:28 PM PDT 24
Peak memory 200232 kb
Host smart-11a8c14d-e84b-4280-b082-6c881b00451d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878243526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2878243526
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.758287203
Short name T492
Test name
Test status
Simulation time 1228085106 ps
CPU time 5.27 seconds
Started Jul 18 05:59:15 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 217468 kb
Host smart-edd28459-f174-4a62-a0c8-ce752ed4b33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758287203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.758287203
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2292827541
Short name T514
Test name
Test status
Simulation time 243991098 ps
CPU time 1.1 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 217484 kb
Host smart-8c7676cf-d8ae-4a43-ae46-f5bae73c7316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292827541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2292827541
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3717288727
Short name T15
Test name
Test status
Simulation time 148448053 ps
CPU time 0.83 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:23 PM PDT 24
Peak memory 200296 kb
Host smart-53e009e0-726b-46f6-9998-7db0ee86c7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717288727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3717288727
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1429346131
Short name T467
Test name
Test status
Simulation time 803114342 ps
CPU time 3.98 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:34 PM PDT 24
Peak memory 200724 kb
Host smart-047678d6-d96f-4c1d-af8c-b6ebe70b8735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429346131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1429346131
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2934571002
Short name T348
Test name
Test status
Simulation time 106997646 ps
CPU time 1 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200420 kb
Host smart-d9e5efc2-ed3d-4264-81d0-dda464530846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934571002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2934571002
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1078675008
Short name T510
Test name
Test status
Simulation time 204162954 ps
CPU time 1.36 seconds
Started Jul 18 05:59:15 PM PDT 24
Finished Jul 18 05:59:28 PM PDT 24
Peak memory 200660 kb
Host smart-df30d314-f31e-4ad5-a462-9d17cfd10269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078675008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1078675008
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.202804080
Short name T531
Test name
Test status
Simulation time 6234490695 ps
CPU time 20.89 seconds
Started Jul 18 05:59:21 PM PDT 24
Finished Jul 18 05:59:55 PM PDT 24
Peak memory 200644 kb
Host smart-66906348-09e7-4e1b-9f78-d7073b7c1cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202804080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.202804080
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.784714280
Short name T521
Test name
Test status
Simulation time 124863175 ps
CPU time 1.49 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200476 kb
Host smart-8d78702f-14cf-4ad3-b84b-ebc6b8eed21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784714280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.784714280
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.639312051
Short name T247
Test name
Test status
Simulation time 236916913 ps
CPU time 1.44 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 200664 kb
Host smart-ed62cfdc-0ae5-4977-ae57-6a84f2311093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639312051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.639312051
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1544856489
Short name T280
Test name
Test status
Simulation time 68733196 ps
CPU time 0.77 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200260 kb
Host smart-89ead7be-e3e2-4e82-8b32-4ddafe8828b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544856489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1544856489
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.4082634007
Short name T31
Test name
Test status
Simulation time 2182597642 ps
CPU time 7.82 seconds
Started Jul 18 05:59:25 PM PDT 24
Finished Jul 18 05:59:46 PM PDT 24
Peak memory 217844 kb
Host smart-6aa6a2a8-1821-49f5-9572-17391c814ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082634007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.4082634007
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2741321196
Short name T475
Test name
Test status
Simulation time 244192281 ps
CPU time 1.09 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 217452 kb
Host smart-89c615f5-c506-4482-8739-5ba7f3d1c789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741321196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2741321196
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3578095683
Short name T13
Test name
Test status
Simulation time 212701379 ps
CPU time 0.91 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 05:59:28 PM PDT 24
Peak memory 200228 kb
Host smart-c96f2311-51b0-4d18-bcb9-15a6db43b8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578095683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3578095683
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3877459394
Short name T432
Test name
Test status
Simulation time 94164856 ps
CPU time 0.96 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200456 kb
Host smart-de14ca9a-3219-4a7f-bac0-b79b23996a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877459394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3877459394
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.378298314
Short name T431
Test name
Test status
Simulation time 195074790 ps
CPU time 1.35 seconds
Started Jul 18 05:59:21 PM PDT 24
Finished Jul 18 05:59:35 PM PDT 24
Peak memory 200660 kb
Host smart-07a234a3-49fd-441d-85cf-c45e0014f175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378298314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.378298314
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1615808199
Short name T319
Test name
Test status
Simulation time 7110499454 ps
CPU time 24.12 seconds
Started Jul 18 05:59:21 PM PDT 24
Finished Jul 18 05:59:57 PM PDT 24
Peak memory 200788 kb
Host smart-237bf866-7042-40b6-b134-b2ba3a1fb6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615808199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1615808199
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1913942035
Short name T390
Test name
Test status
Simulation time 147788644 ps
CPU time 1.83 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200472 kb
Host smart-94550b59-f790-401b-a242-a819d53ae6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913942035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1913942035
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1987332639
Short name T179
Test name
Test status
Simulation time 253452491 ps
CPU time 1.39 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 200456 kb
Host smart-41687c0d-b05b-427c-9816-a4e8c900bc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987332639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1987332639
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1192870940
Short name T157
Test name
Test status
Simulation time 61313341 ps
CPU time 0.73 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:01 PM PDT 24
Peak memory 200064 kb
Host smart-2f23ce38-29ff-4a52-b7ce-24c8b9e06d3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192870940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1192870940
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4207861598
Short name T444
Test name
Test status
Simulation time 2181623907 ps
CPU time 7.74 seconds
Started Jul 18 05:58:52 PM PDT 24
Finished Jul 18 05:59:04 PM PDT 24
Peak memory 229912 kb
Host smart-328317a3-78f4-4dc7-971c-ac5c752b45f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207861598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4207861598
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2358177813
Short name T205
Test name
Test status
Simulation time 244529315 ps
CPU time 1.04 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:01 PM PDT 24
Peak memory 217408 kb
Host smart-45eaacf6-38bb-41ef-ba10-73fe3ed1d403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358177813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2358177813
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4276158616
Short name T166
Test name
Test status
Simulation time 202990214 ps
CPU time 0.92 seconds
Started Jul 18 05:58:47 PM PDT 24
Finished Jul 18 05:58:49 PM PDT 24
Peak memory 200188 kb
Host smart-de80d76e-af0c-41d6-a0e5-ae3532b11b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276158616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4276158616
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2109153085
Short name T117
Test name
Test status
Simulation time 2121181288 ps
CPU time 7.82 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:10 PM PDT 24
Peak memory 200740 kb
Host smart-28eb29fc-f882-47d9-9da9-496cfada4e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109153085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2109153085
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.41916002
Short name T64
Test name
Test status
Simulation time 8450517847 ps
CPU time 13.67 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:16 PM PDT 24
Peak memory 217572 kb
Host smart-e07ae2f8-a356-4e78-b3d3-3275488a7add
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41916002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.41916002
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3323283404
Short name T193
Test name
Test status
Simulation time 92404548 ps
CPU time 1.04 seconds
Started Jul 18 05:58:52 PM PDT 24
Finished Jul 18 05:58:58 PM PDT 24
Peak memory 200388 kb
Host smart-9b6ed579-af29-499f-8f02-5777f5d3bc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323283404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3323283404
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.4022583373
Short name T37
Test name
Test status
Simulation time 243609618 ps
CPU time 1.67 seconds
Started Jul 18 05:58:48 PM PDT 24
Finished Jul 18 05:58:52 PM PDT 24
Peak memory 200668 kb
Host smart-9d5fc326-337c-4d15-a28d-aa6853b4e592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022583373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4022583373
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1438373955
Short name T454
Test name
Test status
Simulation time 13596630132 ps
CPU time 47.77 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:59:46 PM PDT 24
Peak memory 200764 kb
Host smart-2eda697b-8318-4c07-9524-a2bad23b06d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438373955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1438373955
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.191484115
Short name T222
Test name
Test status
Simulation time 286773832 ps
CPU time 2.03 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:05 PM PDT 24
Peak memory 208604 kb
Host smart-bb18a308-8314-4b27-99c4-fd45a8f57e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191484115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.191484115
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.162437750
Short name T124
Test name
Test status
Simulation time 115105972 ps
CPU time 0.94 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:58:58 PM PDT 24
Peak memory 200476 kb
Host smart-63e538bf-1984-42f1-aa13-3a32fa24677f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162437750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.162437750
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.493626899
Short name T324
Test name
Test status
Simulation time 83203522 ps
CPU time 0.81 seconds
Started Jul 18 05:59:09 PM PDT 24
Finished Jul 18 05:59:15 PM PDT 24
Peak memory 200288 kb
Host smart-e8d5d731-a7dc-4208-be0b-802771034e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493626899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.493626899
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3089055840
Short name T520
Test name
Test status
Simulation time 1225620627 ps
CPU time 5.25 seconds
Started Jul 18 05:59:10 PM PDT 24
Finished Jul 18 05:59:22 PM PDT 24
Peak memory 221724 kb
Host smart-3bc850f8-f2b3-473f-9bdd-21ae04f2357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089055840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3089055840
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.775317049
Short name T449
Test name
Test status
Simulation time 244248736 ps
CPU time 1.27 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:26 PM PDT 24
Peak memory 217424 kb
Host smart-f4e493d9-9e4a-4adb-bf57-fa2bc8bc19eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775317049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.775317049
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.4189827109
Short name T18
Test name
Test status
Simulation time 204442814 ps
CPU time 0.97 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 200284 kb
Host smart-ba3b476b-5034-48fd-8834-b6e6b829764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189827109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.4189827109
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.4199751927
Short name T364
Test name
Test status
Simulation time 1682173176 ps
CPU time 6.23 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:37 PM PDT 24
Peak memory 200752 kb
Host smart-e6685d92-20a8-4894-a7ac-f933edee60ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199751927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.4199751927
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2408068820
Short name T308
Test name
Test status
Simulation time 252664124 ps
CPU time 1.53 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 200688 kb
Host smart-0d86651b-853d-4f38-952e-346908f55ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408068820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2408068820
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.119003648
Short name T250
Test name
Test status
Simulation time 1927217662 ps
CPU time 7.17 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:24 PM PDT 24
Peak memory 200812 kb
Host smart-1d5ba2dc-b447-478d-882b-d3140d72d62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119003648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.119003648
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.285644969
Short name T317
Test name
Test status
Simulation time 277332819 ps
CPU time 1.84 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 05:59:29 PM PDT 24
Peak memory 200472 kb
Host smart-f8355b38-ad7e-422b-b919-cdcfdfa647a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285644969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.285644969
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.875878522
Short name T440
Test name
Test status
Simulation time 202076338 ps
CPU time 1.27 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 200456 kb
Host smart-8e35462f-578b-48aa-9fc2-c22b7bcb17f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875878522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.875878522
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1534961907
Short name T316
Test name
Test status
Simulation time 85366513 ps
CPU time 0.87 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:24 PM PDT 24
Peak memory 200508 kb
Host smart-ec87e67e-7502-4878-96ae-b4e76914ab28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534961907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1534961907
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.4041782931
Short name T318
Test name
Test status
Simulation time 1237464786 ps
CPU time 5.47 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:24 PM PDT 24
Peak memory 217776 kb
Host smart-a6116aea-b9b5-45fe-bd64-397693295ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041782931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.4041782931
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2083778344
Short name T415
Test name
Test status
Simulation time 244161988 ps
CPU time 1.15 seconds
Started Jul 18 05:59:15 PM PDT 24
Finished Jul 18 05:59:27 PM PDT 24
Peak memory 217536 kb
Host smart-31c2a1e7-f7eb-4e24-946f-537f96a2a951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083778344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2083778344
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3512169978
Short name T463
Test name
Test status
Simulation time 112953625 ps
CPU time 0.75 seconds
Started Jul 18 05:59:13 PM PDT 24
Finished Jul 18 05:59:21 PM PDT 24
Peak memory 200276 kb
Host smart-fb1097d4-e551-48c6-8bfd-645732057963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512169978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3512169978
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.565534519
Short name T452
Test name
Test status
Simulation time 848445199 ps
CPU time 4.08 seconds
Started Jul 18 05:59:08 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 200716 kb
Host smart-96794cfe-3e8e-4b74-ae0f-099526959c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565534519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.565534519
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2995441160
Short name T522
Test name
Test status
Simulation time 145575249 ps
CPU time 1.08 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200460 kb
Host smart-3f044fe5-54c3-45ec-8255-9bc464d00b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995441160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2995441160
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3479498945
Short name T511
Test name
Test status
Simulation time 252375476 ps
CPU time 1.6 seconds
Started Jul 18 05:59:13 PM PDT 24
Finished Jul 18 05:59:23 PM PDT 24
Peak memory 200680 kb
Host smart-4eded660-abbc-4ff9-8fb2-fdd02a0755c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479498945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3479498945
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.75771147
Short name T226
Test name
Test status
Simulation time 5169072135 ps
CPU time 19.43 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:42 PM PDT 24
Peak memory 208992 kb
Host smart-fc0e77db-607e-46ad-ad04-9ed0635d740a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75771147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.75771147
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1954649424
Short name T73
Test name
Test status
Simulation time 131730983 ps
CPU time 1.62 seconds
Started Jul 18 05:59:12 PM PDT 24
Finished Jul 18 05:59:21 PM PDT 24
Peak memory 208716 kb
Host smart-f903cdab-7618-465c-9ad1-b825046f1d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954649424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1954649424
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.4237247849
Short name T79
Test name
Test status
Simulation time 101734038 ps
CPU time 0.94 seconds
Started Jul 18 05:59:10 PM PDT 24
Finished Jul 18 05:59:17 PM PDT 24
Peak memory 200532 kb
Host smart-832d6f1f-ae28-41b0-ae53-ad0a94a95e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237247849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.4237247849
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.102495595
Short name T201
Test name
Test status
Simulation time 62864487 ps
CPU time 0.83 seconds
Started Jul 18 05:59:13 PM PDT 24
Finished Jul 18 05:59:23 PM PDT 24
Peak memory 200300 kb
Host smart-ea20c417-e1a3-477d-93c0-887ee4ea2642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102495595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.102495595
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.278873057
Short name T49
Test name
Test status
Simulation time 2358003753 ps
CPU time 8.51 seconds
Started Jul 18 05:59:10 PM PDT 24
Finished Jul 18 05:59:25 PM PDT 24
Peak memory 221760 kb
Host smart-958d2b41-967f-4e2f-8672-d0013ab0772c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278873057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.278873057
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3042033392
Short name T220
Test name
Test status
Simulation time 244071751 ps
CPU time 1.06 seconds
Started Jul 18 05:59:17 PM PDT 24
Finished Jul 18 05:59:29 PM PDT 24
Peak memory 217508 kb
Host smart-cf73d61f-b7e0-4ac2-961a-8b976923dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042033392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3042033392
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1782099839
Short name T206
Test name
Test status
Simulation time 170162888 ps
CPU time 0.84 seconds
Started Jul 18 05:59:11 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 200308 kb
Host smart-b613f54f-714f-4a04-af8b-cb30dcc8a3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782099839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1782099839
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3620659863
Short name T211
Test name
Test status
Simulation time 797252911 ps
CPU time 4.37 seconds
Started Jul 18 05:59:16 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 200740 kb
Host smart-a7d79d88-ce1e-41b9-9602-af46c49037ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620659863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3620659863
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2146835326
Short name T392
Test name
Test status
Simulation time 147948322 ps
CPU time 1.14 seconds
Started Jul 18 05:59:15 PM PDT 24
Finished Jul 18 05:59:27 PM PDT 24
Peak memory 200452 kb
Host smart-9a5df703-c727-40ec-a8de-a4917891dcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146835326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2146835326
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3006188869
Short name T438
Test name
Test status
Simulation time 243780679 ps
CPU time 1.55 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:25 PM PDT 24
Peak memory 200876 kb
Host smart-819da08e-55ef-4ba3-9387-ec599058e704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006188869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3006188869
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3800965554
Short name T406
Test name
Test status
Simulation time 7895892644 ps
CPU time 25.68 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:56 PM PDT 24
Peak memory 208992 kb
Host smart-4196a085-b380-4860-a3dc-1e0e19c278f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800965554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3800965554
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2619497257
Short name T515
Test name
Test status
Simulation time 112407703 ps
CPU time 1.43 seconds
Started Jul 18 05:59:12 PM PDT 24
Finished Jul 18 05:59:20 PM PDT 24
Peak memory 200468 kb
Host smart-e306d1a3-f8da-437a-8ae9-cd8cefbfb3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619497257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2619497257
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3077404609
Short name T154
Test name
Test status
Simulation time 199830098 ps
CPU time 1.27 seconds
Started Jul 18 05:59:14 PM PDT 24
Finished Jul 18 05:59:24 PM PDT 24
Peak memory 200444 kb
Host smart-24c5e431-d298-4c85-98c4-7a7a2e4ced60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077404609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3077404609
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1402965594
Short name T156
Test name
Test status
Simulation time 74730262 ps
CPU time 0.76 seconds
Started Jul 18 05:59:25 PM PDT 24
Finished Jul 18 05:59:39 PM PDT 24
Peak memory 200276 kb
Host smart-dd54e6bb-b087-4804-813d-7aecb033c3f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402965594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1402965594
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.4012349723
Short name T293
Test name
Test status
Simulation time 1219131106 ps
CPU time 5.29 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:34 PM PDT 24
Peak memory 221688 kb
Host smart-e37398f5-afa0-48fe-890f-ae3235d67c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012349723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.4012349723
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1830094607
Short name T366
Test name
Test status
Simulation time 245498829 ps
CPU time 1.04 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 217476 kb
Host smart-fa7d2f72-fece-4699-92ae-47760318fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830094607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1830094607
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3470371683
Short name T284
Test name
Test status
Simulation time 180444999 ps
CPU time 0.87 seconds
Started Jul 18 05:59:21 PM PDT 24
Finished Jul 18 05:59:35 PM PDT 24
Peak memory 200280 kb
Host smart-27afd1ef-788f-4c06-9472-e77beb98a414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470371683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3470371683
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.859598552
Short name T72
Test name
Test status
Simulation time 1612542851 ps
CPU time 6.63 seconds
Started Jul 18 05:59:17 PM PDT 24
Finished Jul 18 05:59:35 PM PDT 24
Peak memory 200740 kb
Host smart-b4d74cb4-5da2-484a-889f-c9e53c1a39b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859598552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.859598552
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3285176710
Short name T136
Test name
Test status
Simulation time 101488073 ps
CPU time 1.02 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200424 kb
Host smart-3f86f3ed-3886-4a7d-9a69-9c79e52175a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285176710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3285176710
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.489032981
Short name T263
Test name
Test status
Simulation time 253024836 ps
CPU time 1.45 seconds
Started Jul 18 05:59:17 PM PDT 24
Finished Jul 18 05:59:30 PM PDT 24
Peak memory 200676 kb
Host smart-24591f72-417c-4f8e-a65e-e735e02fc4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489032981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.489032981
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3366117929
Short name T119
Test name
Test status
Simulation time 12897601263 ps
CPU time 48.33 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 200760 kb
Host smart-069c31d9-8131-41c1-b36d-3e58a6ae62c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366117929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3366117929
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2149467948
Short name T426
Test name
Test status
Simulation time 493127783 ps
CPU time 2.48 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 200476 kb
Host smart-3416bf5b-cc1e-4a6d-8e49-1d939c710f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149467948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2149467948
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3884203156
Short name T325
Test name
Test status
Simulation time 128068596 ps
CPU time 1.15 seconds
Started Jul 18 05:59:23 PM PDT 24
Finished Jul 18 05:59:36 PM PDT 24
Peak memory 200468 kb
Host smart-90751f1e-a1be-4b45-bf6d-be34b66bba48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884203156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3884203156
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.418931548
Short name T151
Test name
Test status
Simulation time 73535153 ps
CPU time 0.76 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:31 PM PDT 24
Peak memory 200276 kb
Host smart-9b33c590-00b2-4cb3-bd1d-648b32717145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418931548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.418931548
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1483189087
Short name T48
Test name
Test status
Simulation time 2372224931 ps
CPU time 8.17 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:39 PM PDT 24
Peak memory 217924 kb
Host smart-a27e316a-ff83-47eb-8e53-547ac20da694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483189087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1483189087
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4225170999
Short name T145
Test name
Test status
Simulation time 243783373 ps
CPU time 1.14 seconds
Started Jul 18 05:59:20 PM PDT 24
Finished Jul 18 05:59:34 PM PDT 24
Peak memory 217596 kb
Host smart-1a2cbefd-db32-4d81-80b8-5118e8ad5cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225170999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4225170999
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1107411492
Short name T245
Test name
Test status
Simulation time 190612053 ps
CPU time 0.92 seconds
Started Jul 18 05:59:18 PM PDT 24
Finished Jul 18 05:59:30 PM PDT 24
Peak memory 200200 kb
Host smart-cf5af717-07fe-441c-bdc2-09af7089b78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107411492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1107411492
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1911822261
Short name T356
Test name
Test status
Simulation time 924785804 ps
CPU time 4.63 seconds
Started Jul 18 05:59:21 PM PDT 24
Finished Jul 18 05:59:39 PM PDT 24
Peak memory 200728 kb
Host smart-128ca312-8660-4604-bcee-edfd81b75604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911822261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1911822261
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3966450908
Short name T152
Test name
Test status
Simulation time 105022391 ps
CPU time 1 seconds
Started Jul 18 05:59:21 PM PDT 24
Finished Jul 18 05:59:34 PM PDT 24
Peak memory 200448 kb
Host smart-4109ffb7-6fd6-4c01-a29a-2e4c095cc559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966450908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3966450908
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.324003234
Short name T185
Test name
Test status
Simulation time 204523078 ps
CPU time 1.39 seconds
Started Jul 18 05:59:21 PM PDT 24
Finished Jul 18 05:59:35 PM PDT 24
Peak memory 200660 kb
Host smart-a9e04876-8f6a-46b8-956c-702e980f328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324003234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.324003234
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.174927754
Short name T270
Test name
Test status
Simulation time 8260511934 ps
CPU time 36.47 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 06:00:07 PM PDT 24
Peak memory 209004 kb
Host smart-09f313a9-4e10-43b7-9e23-d233570f9061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174927754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.174927754
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1030114454
Short name T363
Test name
Test status
Simulation time 274792991 ps
CPU time 1.88 seconds
Started Jul 18 05:59:24 PM PDT 24
Finished Jul 18 05:59:39 PM PDT 24
Peak memory 200468 kb
Host smart-5ad84833-b3dd-42d1-aa6e-0152e4aff678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030114454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1030114454
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1687347641
Short name T3
Test name
Test status
Simulation time 164781597 ps
CPU time 1.28 seconds
Started Jul 18 05:59:19 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 200648 kb
Host smart-3f1f7564-cef6-4c2e-b962-a0476284421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687347641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1687347641
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1471659476
Short name T335
Test name
Test status
Simulation time 90203220 ps
CPU time 0.9 seconds
Started Jul 18 05:59:28 PM PDT 24
Finished Jul 18 05:59:43 PM PDT 24
Peak memory 200260 kb
Host smart-872a7b5a-2b54-4e84-8370-64948ddbeb5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471659476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1471659476
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.497619084
Short name T448
Test name
Test status
Simulation time 2162846459 ps
CPU time 8.14 seconds
Started Jul 18 05:59:26 PM PDT 24
Finished Jul 18 05:59:47 PM PDT 24
Peak memory 221560 kb
Host smart-fff991c6-e976-48d5-8ce7-b13e3177f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497619084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.497619084
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1052024396
Short name T428
Test name
Test status
Simulation time 243440738 ps
CPU time 1.06 seconds
Started Jul 18 05:59:26 PM PDT 24
Finished Jul 18 05:59:41 PM PDT 24
Peak memory 217504 kb
Host smart-19ef5cc1-bc49-4f16-8a2d-689fa6c30dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052024396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1052024396
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.415842602
Short name T473
Test name
Test status
Simulation time 193814466 ps
CPU time 0.96 seconds
Started Jul 18 05:59:25 PM PDT 24
Finished Jul 18 05:59:39 PM PDT 24
Peak memory 200344 kb
Host smart-56734777-e43d-4384-a0c6-98062347a4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415842602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.415842602
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3542201609
Short name T271
Test name
Test status
Simulation time 2023094943 ps
CPU time 7.89 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:54 PM PDT 24
Peak memory 200740 kb
Host smart-0b673cff-209f-4a9f-aebb-8711f98d19be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542201609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3542201609
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2867748449
Short name T208
Test name
Test status
Simulation time 160499168 ps
CPU time 1.11 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:46 PM PDT 24
Peak memory 200472 kb
Host smart-2b111ade-e172-4b38-ab4c-acb0f9519ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867748449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2867748449
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4052911352
Short name T377
Test name
Test status
Simulation time 201287331 ps
CPU time 1.37 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:24 PM PDT 24
Peak memory 200692 kb
Host smart-72bf6c7b-ced8-492d-85c4-0b80766a8ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052911352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4052911352
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1004622984
Short name T530
Test name
Test status
Simulation time 11436202464 ps
CPU time 44.78 seconds
Started Jul 18 05:59:26 PM PDT 24
Finished Jul 18 06:00:24 PM PDT 24
Peak memory 208924 kb
Host smart-28d8a83d-b4d3-4a04-a915-bade05127e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004622984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1004622984
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.519109178
Short name T186
Test name
Test status
Simulation time 148790707 ps
CPU time 1.88 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:49 PM PDT 24
Peak memory 200452 kb
Host smart-937d3c25-5731-42b8-a202-960e60d08896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519109178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.519109178
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2889316821
Short name T162
Test name
Test status
Simulation time 81990634 ps
CPU time 0.89 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:45 PM PDT 24
Peak memory 200456 kb
Host smart-baab94fc-9839-455d-a17f-2a2a6756b277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889316821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2889316821
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3865730920
Short name T305
Test name
Test status
Simulation time 81230097 ps
CPU time 0.85 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200276 kb
Host smart-485a8a10-f20d-40f9-98c9-cc0cf035385d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865730920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3865730920
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2385956168
Short name T27
Test name
Test status
Simulation time 2162956260 ps
CPU time 8.56 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:55 PM PDT 24
Peak memory 221804 kb
Host smart-3e620a9d-959a-47e1-9567-ea7c691b5c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385956168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2385956168
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3506269236
Short name T261
Test name
Test status
Simulation time 244749653 ps
CPU time 1.03 seconds
Started Jul 18 05:59:25 PM PDT 24
Finished Jul 18 05:59:39 PM PDT 24
Peak memory 217560 kb
Host smart-67198ff9-dbc8-4756-bef5-bb206c33bc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506269236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3506269236
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1107540560
Short name T471
Test name
Test status
Simulation time 99438861 ps
CPU time 0.74 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:46 PM PDT 24
Peak memory 200280 kb
Host smart-2ba9a119-c0d7-4270-9a1f-f10528bbdb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107540560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1107540560
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2924500689
Short name T209
Test name
Test status
Simulation time 806953458 ps
CPU time 4.1 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:50 PM PDT 24
Peak memory 200728 kb
Host smart-9e023cf0-39b6-4916-8eb4-03c5716442c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924500689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2924500689
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1524362881
Short name T436
Test name
Test status
Simulation time 182279952 ps
CPU time 1.21 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 05:59:44 PM PDT 24
Peak memory 200464 kb
Host smart-a2bc247d-9825-41c4-8787-473317cc19b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524362881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1524362881
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3397773149
Short name T302
Test name
Test status
Simulation time 115778882 ps
CPU time 1.2 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200688 kb
Host smart-d320c6d0-03e2-4804-8ca8-527805e95a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397773149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3397773149
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2101575798
Short name T116
Test name
Test status
Simulation time 8212633941 ps
CPU time 25.93 seconds
Started Jul 18 05:59:24 PM PDT 24
Finished Jul 18 06:00:03 PM PDT 24
Peak memory 200800 kb
Host smart-390c2349-d487-4573-8304-daaebb0e50b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101575798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2101575798
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2372975559
Short name T183
Test name
Test status
Simulation time 283955006 ps
CPU time 1.94 seconds
Started Jul 18 05:59:27 PM PDT 24
Finished Jul 18 05:59:42 PM PDT 24
Peak memory 200500 kb
Host smart-83d32a1a-6dfc-4a65-81ec-4fb84f558366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372975559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2372975559
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3423690901
Short name T122
Test name
Test status
Simulation time 217953815 ps
CPU time 1.29 seconds
Started Jul 18 05:59:26 PM PDT 24
Finished Jul 18 05:59:41 PM PDT 24
Peak memory 200532 kb
Host smart-b618447e-96be-4638-8b2c-d1cf79325488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423690901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3423690901
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1582661746
Short name T389
Test name
Test status
Simulation time 79235192 ps
CPU time 0.82 seconds
Started Jul 18 05:59:27 PM PDT 24
Finished Jul 18 05:59:42 PM PDT 24
Peak memory 200276 kb
Host smart-564087d7-f007-4745-8df6-9ee1a7ea4f34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582661746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1582661746
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.152256764
Short name T34
Test name
Test status
Simulation time 1215156831 ps
CPU time 5.8 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 05:59:49 PM PDT 24
Peak memory 217864 kb
Host smart-1bd6a2d6-1032-4203-b911-2faf2694ddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152256764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.152256764
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1136771697
Short name T498
Test name
Test status
Simulation time 244206554 ps
CPU time 1.1 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 217516 kb
Host smart-e139f0f5-409c-4fa2-9549-420832dfdae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136771697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1136771697
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3750063815
Short name T409
Test name
Test status
Simulation time 101406786 ps
CPU time 0.74 seconds
Started Jul 18 05:59:28 PM PDT 24
Finished Jul 18 05:59:42 PM PDT 24
Peak memory 200260 kb
Host smart-3638e7d9-382b-411f-be0d-c397716f17c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750063815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3750063815
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2682706668
Short name T279
Test name
Test status
Simulation time 868250130 ps
CPU time 4.5 seconds
Started Jul 18 05:59:34 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 200728 kb
Host smart-267299b5-9d34-4fd3-97ff-46cc8ef93e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682706668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2682706668
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.751288536
Short name T216
Test name
Test status
Simulation time 100318649 ps
CPU time 1.03 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200452 kb
Host smart-a501c5aa-7a91-475e-8635-3258974995d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751288536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.751288536
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1788411552
Short name T496
Test name
Test status
Simulation time 109650533 ps
CPU time 1.21 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 200716 kb
Host smart-00e77557-1910-4190-bca2-4c2c680ec6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788411552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1788411552
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.262948011
Short name T400
Test name
Test status
Simulation time 1844871500 ps
CPU time 7.43 seconds
Started Jul 18 05:59:30 PM PDT 24
Finished Jul 18 05:59:51 PM PDT 24
Peak memory 208936 kb
Host smart-b9f7aaa3-0f36-41b6-a971-14ef4c9ddd42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262948011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.262948011
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3703984551
Short name T331
Test name
Test status
Simulation time 120782804 ps
CPU time 1.59 seconds
Started Jul 18 05:59:30 PM PDT 24
Finished Jul 18 05:59:45 PM PDT 24
Peak memory 199600 kb
Host smart-2e340d6d-4156-4949-90d1-a69cbd4f1124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703984551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3703984551
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.4247441752
Short name T344
Test name
Test status
Simulation time 154117666 ps
CPU time 1.16 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:45 PM PDT 24
Peak memory 200464 kb
Host smart-6072b64f-38ff-4240-b0ac-59d1ae4ae5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247441752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.4247441752
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.422922350
Short name T223
Test name
Test status
Simulation time 71993788 ps
CPU time 0.8 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 200500 kb
Host smart-de9e25c6-96eb-4eac-9930-720d5f501c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422922350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.422922350
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1670045784
Short name T43
Test name
Test status
Simulation time 1891290854 ps
CPU time 7.08 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:54 PM PDT 24
Peak memory 221724 kb
Host smart-dded2ce5-6556-406a-8d07-114a118929b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670045784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1670045784
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2285643644
Short name T35
Test name
Test status
Simulation time 244322972 ps
CPU time 1.1 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 217508 kb
Host smart-a97582e7-88ae-40fe-98c5-ab75bfdc0ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285643644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2285643644
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.329301484
Short name T379
Test name
Test status
Simulation time 160324675 ps
CPU time 0.9 seconds
Started Jul 18 05:59:38 PM PDT 24
Finished Jul 18 05:59:53 PM PDT 24
Peak memory 200280 kb
Host smart-24d0a57f-5714-4f97-9516-264e21a8fa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329301484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.329301484
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.4015232574
Short name T519
Test name
Test status
Simulation time 1395915651 ps
CPU time 5.21 seconds
Started Jul 18 05:59:34 PM PDT 24
Finished Jul 18 05:59:54 PM PDT 24
Peak memory 200724 kb
Host smart-95644bed-a53f-419c-8d99-bfc6ffa6a8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015232574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.4015232574
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.708753323
Short name T323
Test name
Test status
Simulation time 103274056 ps
CPU time 1.03 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200464 kb
Host smart-d8df8c39-54d5-49b9-ab14-c986e7186764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708753323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.708753323
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1026775638
Short name T278
Test name
Test status
Simulation time 123526677 ps
CPU time 1.2 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200700 kb
Host smart-b6bbdaf8-c4ba-4444-8cf3-b5cb54e0a6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026775638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1026775638
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2945259708
Short name T326
Test name
Test status
Simulation time 11627655573 ps
CPU time 37.89 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 208996 kb
Host smart-8e21ee1a-1237-46cd-941b-4d2d34a7643b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945259708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2945259708
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2759961347
Short name T54
Test name
Test status
Simulation time 131818800 ps
CPU time 1.83 seconds
Started Jul 18 05:59:35 PM PDT 24
Finished Jul 18 05:59:51 PM PDT 24
Peak memory 200484 kb
Host smart-3258a122-ae75-4a46-805e-0e4b7e8edd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759961347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2759961347
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1805381628
Short name T172
Test name
Test status
Simulation time 64157273 ps
CPU time 0.8 seconds
Started Jul 18 05:59:27 PM PDT 24
Finished Jul 18 05:59:41 PM PDT 24
Peak memory 200472 kb
Host smart-42c6c556-6a79-4c12-82a2-1035f15fcb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805381628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1805381628
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3346090001
Short name T28
Test name
Test status
Simulation time 1231754389 ps
CPU time 5.39 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:53 PM PDT 24
Peak memory 216376 kb
Host smart-0ffa2b01-27aa-4c85-b3c6-d9087114b837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346090001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3346090001
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1530997425
Short name T408
Test name
Test status
Simulation time 244121155 ps
CPU time 1.08 seconds
Started Jul 18 05:59:35 PM PDT 24
Finished Jul 18 05:59:51 PM PDT 24
Peak memory 217504 kb
Host smart-a5633803-be69-4afa-b585-91431934f613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530997425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1530997425
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.285697612
Short name T310
Test name
Test status
Simulation time 82736795 ps
CPU time 0.73 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200276 kb
Host smart-2bb5144c-e206-4f64-8748-b0440aac603e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285697612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.285697612
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2823795869
Short name T120
Test name
Test status
Simulation time 1787953428 ps
CPU time 7.1 seconds
Started Jul 18 05:59:34 PM PDT 24
Finished Jul 18 05:59:55 PM PDT 24
Peak memory 200984 kb
Host smart-007f5d80-7d92-4ed9-91a9-396060ebc3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823795869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2823795869
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.803072700
Short name T532
Test name
Test status
Simulation time 167114841 ps
CPU time 1.17 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 199648 kb
Host smart-8e7c3acd-4640-4f67-b937-fd9ed9a2ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803072700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.803072700
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2581563336
Short name T523
Test name
Test status
Simulation time 204362832 ps
CPU time 1.48 seconds
Started Jul 18 05:59:35 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 200880 kb
Host smart-e8284e94-6291-481e-ad22-b96a51a7ef7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581563336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2581563336
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1467289084
Short name T86
Test name
Test status
Simulation time 2441172245 ps
CPU time 10.98 seconds
Started Jul 18 05:59:28 PM PDT 24
Finished Jul 18 05:59:53 PM PDT 24
Peak memory 200848 kb
Host smart-f3e1b3c9-253b-4817-a844-4940aa74908d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467289084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1467289084
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2427003738
Short name T239
Test name
Test status
Simulation time 468074721 ps
CPU time 2.53 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:50 PM PDT 24
Peak memory 200484 kb
Host smart-0503dbdd-6eda-4f3f-887a-9df2db461b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427003738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2427003738
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2845587671
Short name T123
Test name
Test status
Simulation time 98529747 ps
CPU time 0.92 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200256 kb
Host smart-4fb00f9d-e4cc-44bf-9ad2-3dd72fefe375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845587671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2845587671
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.98158621
Short name T339
Test name
Test status
Simulation time 72116078 ps
CPU time 0.8 seconds
Started Jul 18 05:58:51 PM PDT 24
Finished Jul 18 05:58:55 PM PDT 24
Peak memory 200200 kb
Host smart-48223557-379b-44f7-a11e-d7a6346f6fca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98158621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.98158621
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.4251158031
Short name T347
Test name
Test status
Simulation time 1229491028 ps
CPU time 5.97 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:05 PM PDT 24
Peak memory 221812 kb
Host smart-30d90200-4f76-44fc-be85-0903ff4815e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251158031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.4251158031
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1121226550
Short name T39
Test name
Test status
Simulation time 244704455 ps
CPU time 1.12 seconds
Started Jul 18 05:58:56 PM PDT 24
Finished Jul 18 05:59:06 PM PDT 24
Peak memory 217560 kb
Host smart-54df69a0-d426-4a7a-95de-86c913d89641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121226550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1121226550
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3727357023
Short name T282
Test name
Test status
Simulation time 182036905 ps
CPU time 0.94 seconds
Started Jul 18 05:58:51 PM PDT 24
Finished Jul 18 05:58:54 PM PDT 24
Peak memory 200204 kb
Host smart-3b9dc92b-6039-4060-b8d9-e686dbe8868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727357023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3727357023
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3923037555
Short name T499
Test name
Test status
Simulation time 1566385739 ps
CPU time 6 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:09 PM PDT 24
Peak memory 200776 kb
Host smart-05e0ce1d-356d-4619-a602-d9e44e35fb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923037555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3923037555
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1977681600
Short name T63
Test name
Test status
Simulation time 8398432409 ps
CPU time 13.12 seconds
Started Jul 18 05:58:51 PM PDT 24
Finished Jul 18 05:59:07 PM PDT 24
Peak memory 217188 kb
Host smart-96ca4e71-c724-4a10-9086-d52faac01760
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977681600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1977681600
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2049950945
Short name T4
Test name
Test status
Simulation time 103202211 ps
CPU time 1.05 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:58:58 PM PDT 24
Peak memory 200440 kb
Host smart-119e7645-47ff-436a-955f-ff8ae454c2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049950945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2049950945
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2445678009
Short name T369
Test name
Test status
Simulation time 257286438 ps
CPU time 1.51 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:04 PM PDT 24
Peak memory 200672 kb
Host smart-63c1605c-d657-4478-8a4d-13c6178a86d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445678009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2445678009
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.518918085
Short name T315
Test name
Test status
Simulation time 416371513 ps
CPU time 2.05 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:59:01 PM PDT 24
Peak memory 200684 kb
Host smart-d4d09b80-94bc-4f91-b39d-e8f794a69ce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518918085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.518918085
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3181662460
Short name T240
Test name
Test status
Simulation time 125120007 ps
CPU time 1.64 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:58:59 PM PDT 24
Peak memory 208640 kb
Host smart-86a532c3-7383-4ed4-9812-31e09655bd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181662460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3181662460
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3801648101
Short name T256
Test name
Test status
Simulation time 100748849 ps
CPU time 0.97 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:00 PM PDT 24
Peak memory 200448 kb
Host smart-bd9434ca-ce24-492e-96d3-244a6c1791fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801648101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3801648101
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.788483338
Short name T218
Test name
Test status
Simulation time 66116690 ps
CPU time 0.75 seconds
Started Jul 18 05:59:40 PM PDT 24
Finished Jul 18 05:59:55 PM PDT 24
Peak memory 200272 kb
Host smart-9381303c-9d87-4a0b-bff0-1770d9adc666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788483338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.788483338
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.619094796
Short name T375
Test name
Test status
Simulation time 1227342164 ps
CPU time 5.44 seconds
Started Jul 18 05:59:40 PM PDT 24
Finished Jul 18 06:00:00 PM PDT 24
Peak memory 221768 kb
Host smart-82f14a6d-dd07-49e2-a8c1-25d7e90de8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619094796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.619094796
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1418050172
Short name T536
Test name
Test status
Simulation time 244615536 ps
CPU time 1.1 seconds
Started Jul 18 05:59:34 PM PDT 24
Finished Jul 18 05:59:49 PM PDT 24
Peak memory 217476 kb
Host smart-3600a76e-036d-4e5d-916f-6b643d874418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418050172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1418050172
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3682350314
Short name T338
Test name
Test status
Simulation time 204322235 ps
CPU time 0.94 seconds
Started Jul 18 05:59:40 PM PDT 24
Finished Jul 18 05:59:55 PM PDT 24
Peak memory 200268 kb
Host smart-cce17c21-e570-42c2-8b09-2ec296f9aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682350314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3682350314
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.4246022602
Short name T6
Test name
Test status
Simulation time 971663320 ps
CPU time 4.62 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 05:59:56 PM PDT 24
Peak memory 200372 kb
Host smart-663a6912-aed6-4125-be59-1ae0a00bb667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246022602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4246022602
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.810212907
Short name T134
Test name
Test status
Simulation time 187450527 ps
CPU time 1.16 seconds
Started Jul 18 05:59:40 PM PDT 24
Finished Jul 18 05:59:55 PM PDT 24
Peak memory 200460 kb
Host smart-8ac4a4a2-f8b7-4bb6-9e85-1d118e67a7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810212907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.810212907
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.717256122
Short name T381
Test name
Test status
Simulation time 231317427 ps
CPU time 1.42 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 200588 kb
Host smart-c76afd90-01a8-47b6-9102-bf4b9bc2e216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717256122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.717256122
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2303540096
Short name T296
Test name
Test status
Simulation time 6378447614 ps
CPU time 23.91 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 06:00:07 PM PDT 24
Peak memory 200716 kb
Host smart-9433160d-aca3-4cd2-ab55-bdb44c95ecea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303540096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2303540096
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.143193295
Short name T403
Test name
Test status
Simulation time 254150922 ps
CPU time 1.86 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:46 PM PDT 24
Peak memory 200504 kb
Host smart-3864f97f-2f2d-4ea9-8bfb-6ff85152ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143193295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.143193295
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.360100388
Short name T297
Test name
Test status
Simulation time 190492681 ps
CPU time 1.2 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:47 PM PDT 24
Peak memory 200484 kb
Host smart-7e0dd673-48b3-4d0f-81f7-87880420192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360100388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.360100388
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3931802177
Short name T155
Test name
Test status
Simulation time 70081492 ps
CPU time 0.78 seconds
Started Jul 18 05:59:28 PM PDT 24
Finished Jul 18 05:59:43 PM PDT 24
Peak memory 200264 kb
Host smart-40b30f11-4607-489c-b003-db3096e65356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931802177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3931802177
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3632836445
Short name T41
Test name
Test status
Simulation time 2357709425 ps
CPU time 8.19 seconds
Started Jul 18 05:59:30 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 219728 kb
Host smart-1b469db8-06a5-4047-8e49-a62767a5ce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632836445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3632836445
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1706007484
Short name T45
Test name
Test status
Simulation time 243954183 ps
CPU time 1.08 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 05:59:44 PM PDT 24
Peak memory 217476 kb
Host smart-d5388543-a564-4d79-bf4b-0d97859dfeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706007484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1706007484
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1306122902
Short name T393
Test name
Test status
Simulation time 107529611 ps
CPU time 0.75 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:47 PM PDT 24
Peak memory 200288 kb
Host smart-e557551f-9199-4aef-91e3-6390b97e585a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306122902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1306122902
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.647710551
Short name T47
Test name
Test status
Simulation time 2012722864 ps
CPU time 7.51 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:54 PM PDT 24
Peak memory 200756 kb
Host smart-a921bcb6-706e-4510-afb9-9854aa9dd77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647710551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.647710551
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2228095930
Short name T246
Test name
Test status
Simulation time 151997284 ps
CPU time 1.12 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:46 PM PDT 24
Peak memory 200460 kb
Host smart-a1a6dad1-cccb-4c7c-874a-e012bd2f3087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228095930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2228095930
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.111431604
Short name T290
Test name
Test status
Simulation time 255499804 ps
CPU time 1.45 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200676 kb
Host smart-40bf42e5-a462-4dd0-b661-ae5765555393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111431604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.111431604
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2048283372
Short name T289
Test name
Test status
Simulation time 1638997504 ps
CPU time 6.38 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:54 PM PDT 24
Peak memory 209048 kb
Host smart-a52df2ff-5bc7-459c-87cb-a7c391a6dbdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048283372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2048283372
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1105714645
Short name T384
Test name
Test status
Simulation time 418114803 ps
CPU time 2.26 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:46 PM PDT 24
Peak memory 200472 kb
Host smart-d6a3ae1f-5987-4140-a64e-6693654a9742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105714645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1105714645
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1201092011
Short name T121
Test name
Test status
Simulation time 92732870 ps
CPU time 0.85 seconds
Started Jul 18 05:59:28 PM PDT 24
Finished Jul 18 05:59:43 PM PDT 24
Peak memory 200468 kb
Host smart-5f569788-f799-42a6-ac99-2520c4223d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201092011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1201092011
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3165671065
Short name T443
Test name
Test status
Simulation time 77063478 ps
CPU time 0.81 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200276 kb
Host smart-c2b1f1d6-fd38-4d98-856d-7c04d4b86a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165671065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3165671065
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1568903647
Short name T26
Test name
Test status
Simulation time 2158513879 ps
CPU time 7.8 seconds
Started Jul 18 05:59:30 PM PDT 24
Finished Jul 18 05:59:51 PM PDT 24
Peak memory 217836 kb
Host smart-e9de7180-6f32-424c-b6d6-9ad0479b5694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568903647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1568903647
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1963770580
Short name T427
Test name
Test status
Simulation time 244078635 ps
CPU time 1.18 seconds
Started Jul 18 05:59:38 PM PDT 24
Finished Jul 18 05:59:53 PM PDT 24
Peak memory 217548 kb
Host smart-ff845983-32fb-4cea-95ce-6802d641ea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963770580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1963770580
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1399671684
Short name T450
Test name
Test status
Simulation time 200955928 ps
CPU time 0.86 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 05:59:43 PM PDT 24
Peak memory 200296 kb
Host smart-98350ef8-616e-46c9-90ed-918dde48933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399671684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1399671684
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3656364814
Short name T388
Test name
Test status
Simulation time 2056414766 ps
CPU time 7.98 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:53 PM PDT 24
Peak memory 200740 kb
Host smart-b43d0f03-a58d-4f24-8a2a-4838a5da8501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656364814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3656364814
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1178881359
Short name T397
Test name
Test status
Simulation time 91438434 ps
CPU time 0.96 seconds
Started Jul 18 05:59:30 PM PDT 24
Finished Jul 18 05:59:44 PM PDT 24
Peak memory 200444 kb
Host smart-ec378e48-8dcc-4ee9-b83a-0a5a5724779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178881359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1178881359
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3106038243
Short name T495
Test name
Test status
Simulation time 108771764 ps
CPU time 1.22 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 05:59:44 PM PDT 24
Peak memory 200624 kb
Host smart-0f48cff8-bf6b-48e8-a7d2-d1e3aa9daf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106038243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3106038243
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.858872752
Short name T8
Test name
Test status
Simulation time 4637073084 ps
CPU time 20.36 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 06:00:11 PM PDT 24
Peak memory 209000 kb
Host smart-6de2247b-22eb-4c1f-98f6-c5d7a4b61c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858872752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.858872752
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4209091185
Short name T332
Test name
Test status
Simulation time 345862918 ps
CPU time 2.19 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:47 PM PDT 24
Peak memory 208680 kb
Host smart-3ad8278a-8d34-48e6-a7e1-af6cfe584f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209091185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4209091185
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1760910297
Short name T241
Test name
Test status
Simulation time 171662182 ps
CPU time 1.28 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:46 PM PDT 24
Peak memory 200708 kb
Host smart-679ee4ec-fa44-4181-94a5-2c4615a0ef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760910297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1760910297
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2238762382
Short name T32
Test name
Test status
Simulation time 61571573 ps
CPU time 0.74 seconds
Started Jul 18 05:59:34 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200276 kb
Host smart-e1c0abff-d0cd-46b6-b94b-b1916659ab4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238762382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2238762382
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1901199251
Short name T50
Test name
Test status
Simulation time 1226544467 ps
CPU time 5.29 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 217844 kb
Host smart-b0d86e36-ba3d-470c-b2b3-46bb70fc42cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901199251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1901199251
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1299961596
Short name T165
Test name
Test status
Simulation time 245412088 ps
CPU time 1.04 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 217512 kb
Host smart-10255848-8175-45e0-91e9-959eaad30f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299961596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1299961596
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.4282610656
Short name T19
Test name
Test status
Simulation time 154621916 ps
CPU time 0.89 seconds
Started Jul 18 05:59:27 PM PDT 24
Finished Jul 18 05:59:42 PM PDT 24
Peak memory 200256 kb
Host smart-cb643362-9f3b-4089-a517-46c4449e78b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282610656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.4282610656
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1681317704
Short name T217
Test name
Test status
Simulation time 1324048618 ps
CPU time 5.39 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 05:59:57 PM PDT 24
Peak memory 200744 kb
Host smart-e07719e7-56a0-49c8-91c8-2ce69af4add0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681317704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1681317704
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.952364107
Short name T153
Test name
Test status
Simulation time 151865757 ps
CPU time 1.13 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200464 kb
Host smart-2f265c91-5f96-4182-8d17-69d86127e123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952364107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.952364107
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1801288933
Short name T84
Test name
Test status
Simulation time 191448708 ps
CPU time 1.37 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:49 PM PDT 24
Peak memory 200676 kb
Host smart-8e01aea4-df01-456b-bab4-ed5108343aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801288933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1801288933
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2968177696
Short name T516
Test name
Test status
Simulation time 1444242934 ps
CPU time 7.76 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 05:59:59 PM PDT 24
Peak memory 208884 kb
Host smart-56fddae2-6b8b-451e-a513-34f4d08dbd56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968177696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2968177696
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2514030891
Short name T429
Test name
Test status
Simulation time 146321555 ps
CPU time 1.96 seconds
Started Jul 18 05:59:34 PM PDT 24
Finished Jul 18 05:59:50 PM PDT 24
Peak memory 200468 kb
Host smart-b4426004-c6ff-465a-b14f-d941ec7745f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514030891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2514030891
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.85691167
Short name T481
Test name
Test status
Simulation time 86450818 ps
CPU time 0.91 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 200476 kb
Host smart-d3785752-1f8d-4257-a3f6-58acc2e5c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85691167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.85691167
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3889252324
Short name T502
Test name
Test status
Simulation time 63738856 ps
CPU time 0.74 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 199844 kb
Host smart-41c1140a-dfa3-46ad-98ee-4f8ab46e06ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889252324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3889252324
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2759743801
Short name T334
Test name
Test status
Simulation time 2161304262 ps
CPU time 8.34 seconds
Started Jul 18 05:59:31 PM PDT 24
Finished Jul 18 05:59:53 PM PDT 24
Peak memory 217580 kb
Host smart-dac08b7f-10d5-4da5-b977-b72ae10104da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759743801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2759743801
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.81151484
Short name T210
Test name
Test status
Simulation time 245151037 ps
CPU time 1.05 seconds
Started Jul 18 05:59:38 PM PDT 24
Finished Jul 18 05:59:53 PM PDT 24
Peak memory 217412 kb
Host smart-d3bad3a4-50ec-48d7-a47f-50365ae6573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81151484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.81151484
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3884567103
Short name T485
Test name
Test status
Simulation time 1449958818 ps
CPU time 5.92 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 05:59:49 PM PDT 24
Peak memory 200708 kb
Host smart-1060e2d4-f23c-4f28-80bf-b97a44497736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884567103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3884567103
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.919503544
Short name T314
Test name
Test status
Simulation time 104694943 ps
CPU time 1.2 seconds
Started Jul 18 05:59:35 PM PDT 24
Finished Jul 18 05:59:51 PM PDT 24
Peak memory 200452 kb
Host smart-fc14dd45-b277-4a3e-8a19-78c448437905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919503544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.919503544
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3671811157
Short name T292
Test name
Test status
Simulation time 116572587 ps
CPU time 1.23 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:49 PM PDT 24
Peak memory 200716 kb
Host smart-5ff76409-d3b7-4710-8bf2-a2e668614323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671811157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3671811157
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.21811042
Short name T95
Test name
Test status
Simulation time 8031600337 ps
CPU time 28.94 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 06:00:22 PM PDT 24
Peak memory 209000 kb
Host smart-4063733e-9fd1-4765-9fea-8e177de5318d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21811042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.21811042
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1367882956
Short name T203
Test name
Test status
Simulation time 148166532 ps
CPU time 1.9 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:49 PM PDT 24
Peak memory 200328 kb
Host smart-615a8cc6-64d1-4c9b-8ee3-87052ea61dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367882956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1367882956
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2360383713
Short name T355
Test name
Test status
Simulation time 145156686 ps
CPU time 1.12 seconds
Started Jul 18 05:59:30 PM PDT 24
Finished Jul 18 05:59:44 PM PDT 24
Peak memory 200460 kb
Host smart-af29a3de-32af-46b8-a7dc-8fe7c83d88ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360383713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2360383713
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.416136194
Short name T446
Test name
Test status
Simulation time 88910524 ps
CPU time 0.85 seconds
Started Jul 18 05:59:34 PM PDT 24
Finished Jul 18 05:59:49 PM PDT 24
Peak memory 199472 kb
Host smart-652ca09c-376d-4092-a62d-e84cdeb2e03a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416136194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.416136194
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2547541517
Short name T42
Test name
Test status
Simulation time 1224082487 ps
CPU time 5.85 seconds
Started Jul 18 05:59:40 PM PDT 24
Finished Jul 18 06:00:01 PM PDT 24
Peak memory 217536 kb
Host smart-a1e48016-6389-4755-914f-868b2857007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547541517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2547541517
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2663430234
Short name T283
Test name
Test status
Simulation time 243780908 ps
CPU time 1.11 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 05:59:44 PM PDT 24
Peak memory 217492 kb
Host smart-705eaa56-4992-4a1f-a30e-30db0aabe12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663430234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2663430234
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3510879536
Short name T170
Test name
Test status
Simulation time 147115529 ps
CPU time 0.88 seconds
Started Jul 18 05:59:36 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 199812 kb
Host smart-89e7e900-845b-49fd-99da-8cffc1b9293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510879536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3510879536
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3924572770
Short name T527
Test name
Test status
Simulation time 1007987413 ps
CPU time 4.94 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 200800 kb
Host smart-3acaec43-3fce-4ac9-a4aa-c8826d4d3a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924572770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3924572770
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3373902271
Short name T469
Test name
Test status
Simulation time 103609212 ps
CPU time 1.05 seconds
Started Jul 18 05:59:40 PM PDT 24
Finished Jul 18 05:59:56 PM PDT 24
Peak memory 200004 kb
Host smart-ef928994-e9a2-4f89-b747-5e10cf520189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373902271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3373902271
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3012802885
Short name T173
Test name
Test status
Simulation time 111866437 ps
CPU time 1.26 seconds
Started Jul 18 05:59:40 PM PDT 24
Finished Jul 18 05:59:56 PM PDT 24
Peak memory 200672 kb
Host smart-b3b424f0-23bd-4a5a-b023-53fb3d1dc80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012802885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3012802885
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.938534344
Short name T197
Test name
Test status
Simulation time 246613618 ps
CPU time 1.41 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 05:59:44 PM PDT 24
Peak memory 200624 kb
Host smart-775c31dd-8134-43f4-94ae-3fdd3324284d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938534344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.938534344
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4101735862
Short name T321
Test name
Test status
Simulation time 334241098 ps
CPU time 2.18 seconds
Started Jul 18 05:59:34 PM PDT 24
Finished Jul 18 05:59:50 PM PDT 24
Peak memory 199632 kb
Host smart-05ce9c4f-5109-4a2d-8ab1-8d63d9f6b9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101735862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4101735862
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1076477302
Short name T295
Test name
Test status
Simulation time 99939827 ps
CPU time 0.99 seconds
Started Jul 18 05:59:34 PM PDT 24
Finished Jul 18 05:59:49 PM PDT 24
Peak memory 200460 kb
Host smart-79006031-8613-4447-ada0-94d9ef1fc623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076477302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1076477302
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.4136585530
Short name T497
Test name
Test status
Simulation time 72407706 ps
CPU time 0.82 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 06:00:00 PM PDT 24
Peak memory 200260 kb
Host smart-08e144cf-c904-438d-b8e8-b1c9587bda99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136585530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.4136585530
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2441989657
Short name T24
Test name
Test status
Simulation time 1214542327 ps
CPU time 5.28 seconds
Started Jul 18 05:59:26 PM PDT 24
Finished Jul 18 05:59:45 PM PDT 24
Peak memory 217816 kb
Host smart-7c361ad6-308d-46c5-9119-d7d3b56ea944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441989657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2441989657
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3627954477
Short name T36
Test name
Test status
Simulation time 244081001 ps
CPU time 1.13 seconds
Started Jul 18 05:59:27 PM PDT 24
Finished Jul 18 05:59:41 PM PDT 24
Peak memory 217568 kb
Host smart-64869417-854a-47f1-95b0-e12ff79c62c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627954477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3627954477
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2079473
Short name T161
Test name
Test status
Simulation time 149443221 ps
CPU time 0.84 seconds
Started Jul 18 05:59:34 PM PDT 24
Finished Jul 18 05:59:49 PM PDT 24
Peak memory 200264 kb
Host smart-e39d2c8f-dd10-41a5-a855-514af8b6bd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2079473
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1964960222
Short name T378
Test name
Test status
Simulation time 1684803775 ps
CPU time 6.55 seconds
Started Jul 18 05:59:30 PM PDT 24
Finished Jul 18 05:59:50 PM PDT 24
Peak memory 200776 kb
Host smart-34aca22a-eaef-4ff6-a165-bc33ad183232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964960222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1964960222
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.953223333
Short name T265
Test name
Test status
Simulation time 99539069 ps
CPU time 0.98 seconds
Started Jul 18 05:59:28 PM PDT 24
Finished Jul 18 05:59:43 PM PDT 24
Peak memory 200488 kb
Host smart-2cbb13d3-c948-4c80-8618-8895d3cab2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953223333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.953223333
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2626463706
Short name T299
Test name
Test status
Simulation time 191411471 ps
CPU time 1.35 seconds
Started Jul 18 05:59:35 PM PDT 24
Finished Jul 18 05:59:52 PM PDT 24
Peak memory 200680 kb
Host smart-79a06964-8bcc-4273-ac3a-c75d1b0ecc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626463706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2626463706
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2535527600
Short name T158
Test name
Test status
Simulation time 287367598 ps
CPU time 1.38 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 200476 kb
Host smart-4aa663eb-0fd1-4a6f-baf6-581e857cfa11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535527600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2535527600
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.32134511
Short name T367
Test name
Test status
Simulation time 134656321 ps
CPU time 1.7 seconds
Started Jul 18 05:59:32 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 208668 kb
Host smart-f5211160-a74f-4482-aaf3-8e656e3ff88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32134511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.32134511
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1100125044
Short name T188
Test name
Test status
Simulation time 212237708 ps
CPU time 1.28 seconds
Started Jul 18 05:59:29 PM PDT 24
Finished Jul 18 05:59:44 PM PDT 24
Peak memory 200200 kb
Host smart-1e886b7c-678c-4db9-a776-9a7c7e6043be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100125044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1100125044
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3164091695
Short name T535
Test name
Test status
Simulation time 76582794 ps
CPU time 0.79 seconds
Started Jul 18 05:59:47 PM PDT 24
Finished Jul 18 05:59:58 PM PDT 24
Peak memory 200292 kb
Host smart-3cd46133-502d-477e-9a0b-72f72dcbe47a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164091695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3164091695
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1985581289
Short name T77
Test name
Test status
Simulation time 1217207544 ps
CPU time 5.55 seconds
Started Jul 18 06:00:06 PM PDT 24
Finished Jul 18 06:00:16 PM PDT 24
Peak memory 221724 kb
Host smart-cb9b1662-f949-45fa-8c35-6a29bc56d8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985581289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1985581289
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4110482210
Short name T368
Test name
Test status
Simulation time 244743226 ps
CPU time 1.09 seconds
Started Jul 18 05:59:50 PM PDT 24
Finished Jul 18 06:00:00 PM PDT 24
Peak memory 217444 kb
Host smart-beee3ef2-3b87-4f22-895a-513f7b7ee70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110482210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4110482210
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1635822806
Short name T11
Test name
Test status
Simulation time 152787205 ps
CPU time 0.89 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 05:59:59 PM PDT 24
Peak memory 200272 kb
Host smart-39bcfc5b-b9c8-417a-93e5-272160e444bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635822806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1635822806
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2205465827
Short name T423
Test name
Test status
Simulation time 1342122791 ps
CPU time 5.64 seconds
Started Jul 18 06:00:02 PM PDT 24
Finished Jul 18 06:00:13 PM PDT 24
Peak memory 200744 kb
Host smart-a369c276-7935-4883-be69-a37883c8dbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205465827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2205465827
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2613106938
Short name T244
Test name
Test status
Simulation time 102748876 ps
CPU time 1.04 seconds
Started Jul 18 06:00:02 PM PDT 24
Finished Jul 18 06:00:08 PM PDT 24
Peak memory 200444 kb
Host smart-3fad68a8-bdc0-45a2-a2a5-45958cef90f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613106938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2613106938
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.692273082
Short name T503
Test name
Test status
Simulation time 260455286 ps
CPU time 1.54 seconds
Started Jul 18 05:59:51 PM PDT 24
Finished Jul 18 06:00:02 PM PDT 24
Peak memory 200744 kb
Host smart-1240b29d-0bd2-4ee3-a26a-06a82fd73606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692273082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.692273082
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.350131088
Short name T212
Test name
Test status
Simulation time 313207322 ps
CPU time 2.01 seconds
Started Jul 18 05:59:50 PM PDT 24
Finished Jul 18 06:00:01 PM PDT 24
Peak memory 208712 kb
Host smart-06bff805-fd81-402e-babb-cb1fa1247ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350131088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.350131088
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1991824957
Short name T484
Test name
Test status
Simulation time 119029269 ps
CPU time 1.06 seconds
Started Jul 18 06:00:10 PM PDT 24
Finished Jul 18 06:00:15 PM PDT 24
Peak memory 200472 kb
Host smart-9f168938-00bd-45fb-b68b-f71991b31710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991824957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1991824957
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.453760495
Short name T382
Test name
Test status
Simulation time 54147216 ps
CPU time 0.71 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 05:59:59 PM PDT 24
Peak memory 200264 kb
Host smart-8f07044d-e15e-48bc-9c13-84bb8e230a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453760495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.453760495
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3850425769
Short name T491
Test name
Test status
Simulation time 2185262179 ps
CPU time 7.35 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 217872 kb
Host smart-08d11dc3-6364-42a7-b87b-44a6730ae87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850425769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3850425769
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.201923231
Short name T276
Test name
Test status
Simulation time 244496182 ps
CPU time 1.03 seconds
Started Jul 18 05:59:46 PM PDT 24
Finished Jul 18 05:59:58 PM PDT 24
Peak memory 217560 kb
Host smart-040a31f9-420c-4b7b-8085-b87c3073ed64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201923231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.201923231
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.518317511
Short name T17
Test name
Test status
Simulation time 157277365 ps
CPU time 0.83 seconds
Started Jul 18 05:59:55 PM PDT 24
Finished Jul 18 06:00:03 PM PDT 24
Peak memory 200260 kb
Host smart-1c68a2c6-4cb4-41d7-8f86-39043f79df6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518317511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.518317511
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.573826491
Short name T416
Test name
Test status
Simulation time 933085292 ps
CPU time 4.18 seconds
Started Jul 18 05:59:51 PM PDT 24
Finished Jul 18 06:00:04 PM PDT 24
Peak memory 200744 kb
Host smart-7321f83d-9b5a-4d63-9887-b2d06714ea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573826491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.573826491
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2494098613
Short name T78
Test name
Test status
Simulation time 142068789 ps
CPU time 1.11 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 06:00:00 PM PDT 24
Peak memory 200676 kb
Host smart-e0d1f24f-b893-498b-8ea5-f0a157a0a248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494098613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2494098613
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2950236032
Short name T285
Test name
Test status
Simulation time 129615140 ps
CPU time 1.2 seconds
Started Jul 18 05:59:57 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 200668 kb
Host smart-b2d2f656-7fb9-43b9-a2be-d8b5c74e84fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950236032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2950236032
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.672232533
Short name T115
Test name
Test status
Simulation time 3760476812 ps
CPU time 15.31 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 06:00:14 PM PDT 24
Peak memory 208988 kb
Host smart-3d768122-ca24-488b-9d12-b77e184b48e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672232533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.672232533
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.198305975
Short name T486
Test name
Test status
Simulation time 467994175 ps
CPU time 2.5 seconds
Started Jul 18 06:00:02 PM PDT 24
Finished Jul 18 06:00:10 PM PDT 24
Peak memory 200484 kb
Host smart-fc7a195f-db70-485e-bd74-18421733399f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198305975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.198305975
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3812091029
Short name T189
Test name
Test status
Simulation time 101577655 ps
CPU time 0.98 seconds
Started Jul 18 05:59:59 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 200464 kb
Host smart-935be67c-b597-4c58-b977-b7daefb36693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812091029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3812091029
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.252009070
Short name T374
Test name
Test status
Simulation time 60118149 ps
CPU time 0.73 seconds
Started Jul 18 05:59:57 PM PDT 24
Finished Jul 18 06:00:05 PM PDT 24
Peak memory 200252 kb
Host smart-01c73d79-9e71-4dc1-8fdd-debe7834ec3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252009070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.252009070
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1380838459
Short name T281
Test name
Test status
Simulation time 2165005287 ps
CPU time 8.57 seconds
Started Jul 18 05:59:50 PM PDT 24
Finished Jul 18 06:00:08 PM PDT 24
Peak memory 217872 kb
Host smart-c00adf5a-3fc7-4afd-95eb-c95fa4cf3854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380838459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1380838459
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.85317655
Short name T359
Test name
Test status
Simulation time 243784760 ps
CPU time 1.09 seconds
Started Jul 18 06:00:00 PM PDT 24
Finished Jul 18 06:00:07 PM PDT 24
Peak memory 217488 kb
Host smart-c17b1635-60f1-4183-a5ca-f42f11b25396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85317655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.85317655
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3437307476
Short name T506
Test name
Test status
Simulation time 130482740 ps
CPU time 0.79 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 06:00:00 PM PDT 24
Peak memory 200248 kb
Host smart-00a33683-8a31-4c0b-b386-d81eda71bc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437307476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3437307476
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.4256900865
Short name T174
Test name
Test status
Simulation time 1405918338 ps
CPU time 6.1 seconds
Started Jul 18 05:59:51 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 200768 kb
Host smart-9899cc4f-5d79-4cf2-b12b-23b0d19322e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256900865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.4256900865
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1000718992
Short name T143
Test name
Test status
Simulation time 172622863 ps
CPU time 1.21 seconds
Started Jul 18 05:59:53 PM PDT 24
Finished Jul 18 06:00:02 PM PDT 24
Peak memory 200388 kb
Host smart-5e1ce9b6-c779-4a90-a53d-95f70187ea75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000718992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1000718992
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3259482482
Short name T399
Test name
Test status
Simulation time 246450220 ps
CPU time 1.61 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 06:00:00 PM PDT 24
Peak memory 200880 kb
Host smart-8985695a-53f1-48ed-9025-5b4360511530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259482482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3259482482
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1076815594
Short name T528
Test name
Test status
Simulation time 2627852771 ps
CPU time 11.43 seconds
Started Jul 18 06:00:04 PM PDT 24
Finished Jul 18 06:00:21 PM PDT 24
Peak memory 200828 kb
Host smart-f20197da-ae3d-450d-830b-0bf072d5a5ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076815594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1076815594
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.302185762
Short name T345
Test name
Test status
Simulation time 123998822 ps
CPU time 1.5 seconds
Started Jul 18 05:59:52 PM PDT 24
Finished Jul 18 06:00:02 PM PDT 24
Peak memory 200520 kb
Host smart-ba84be93-7840-42b0-8027-fd8689353b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302185762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.302185762
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2080134840
Short name T150
Test name
Test status
Simulation time 138858880 ps
CPU time 1.18 seconds
Started Jul 18 05:59:47 PM PDT 24
Finished Jul 18 05:59:58 PM PDT 24
Peak memory 200468 kb
Host smart-b63a0bfa-d1cc-4a95-b531-97b5568d17f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080134840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2080134840
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2432919776
Short name T253
Test name
Test status
Simulation time 86481182 ps
CPU time 0.8 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:01 PM PDT 24
Peak memory 200044 kb
Host smart-b9c19efe-a6eb-41bc-a653-10ee39b34e2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432919776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2432919776
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3514975774
Short name T509
Test name
Test status
Simulation time 2357089722 ps
CPU time 8.24 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:10 PM PDT 24
Peak memory 217808 kb
Host smart-6dc075d1-43be-4cfc-b53e-249d81a33d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514975774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3514975774
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1681320851
Short name T149
Test name
Test status
Simulation time 244026412 ps
CPU time 1.16 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:04 PM PDT 24
Peak memory 217580 kb
Host smart-2b32032f-a240-4d6b-a96d-b043b105a782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681320851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1681320851
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.563264755
Short name T457
Test name
Test status
Simulation time 74990770 ps
CPU time 0.72 seconds
Started Jul 18 05:58:51 PM PDT 24
Finished Jul 18 05:58:54 PM PDT 24
Peak memory 200260 kb
Host smart-0f4700d8-6927-4ff5-bf79-231b17c3421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563264755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.563264755
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1263455198
Short name T477
Test name
Test status
Simulation time 1037330513 ps
CPU time 5 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:07 PM PDT 24
Peak memory 200780 kb
Host smart-779264c6-363a-4611-9b03-c131daf9fba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263455198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1263455198
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2599528508
Short name T65
Test name
Test status
Simulation time 8279853093 ps
CPU time 14.6 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:18 PM PDT 24
Peak memory 217660 kb
Host smart-e67bf09a-32ba-4736-b810-edd4618ff77d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599528508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2599528508
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.421807227
Short name T493
Test name
Test status
Simulation time 113664170 ps
CPU time 1.03 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:58:58 PM PDT 24
Peak memory 200456 kb
Host smart-5e96924b-76af-4a52-a1af-820bb74ef31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421807227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.421807227
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.196826554
Short name T85
Test name
Test status
Simulation time 192282492 ps
CPU time 1.39 seconds
Started Jul 18 05:58:49 PM PDT 24
Finished Jul 18 05:58:52 PM PDT 24
Peak memory 200600 kb
Host smart-3f773508-796b-401c-a128-e9db2777785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196826554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.196826554
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.830148607
Short name T404
Test name
Test status
Simulation time 8080805442 ps
CPU time 34.02 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:36 PM PDT 24
Peak memory 208900 kb
Host smart-7554b4ae-4ba1-4a80-a3f8-13898cd9a185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830148607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.830148607
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2586093340
Short name T417
Test name
Test status
Simulation time 492115412 ps
CPU time 2.74 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:02 PM PDT 24
Peak memory 200392 kb
Host smart-62a74868-c98d-4107-a730-c1ad32042bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586093340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2586093340
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.368378884
Short name T268
Test name
Test status
Simulation time 136536344 ps
CPU time 1.21 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:00 PM PDT 24
Peak memory 200284 kb
Host smart-3447a384-8ba3-45ce-88fc-5303dbe4e6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368378884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.368378884
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1316841926
Short name T441
Test name
Test status
Simulation time 67445511 ps
CPU time 0.74 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 05:59:59 PM PDT 24
Peak memory 200276 kb
Host smart-1e92bf4f-3e89-4d62-9c98-15d6bb533a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316841926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1316841926
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.790259167
Short name T508
Test name
Test status
Simulation time 1891382739 ps
CPU time 6.86 seconds
Started Jul 18 05:59:47 PM PDT 24
Finished Jul 18 06:00:04 PM PDT 24
Peak memory 217812 kb
Host smart-4adba235-24b1-4a62-9d80-dac75be4c0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790259167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.790259167
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1477497274
Short name T142
Test name
Test status
Simulation time 244064572 ps
CPU time 1.1 seconds
Started Jul 18 05:59:51 PM PDT 24
Finished Jul 18 06:00:01 PM PDT 24
Peak memory 217504 kb
Host smart-bb04539e-a216-43e5-8f33-27453984c38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477497274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1477497274
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.172783764
Short name T14
Test name
Test status
Simulation time 165817981 ps
CPU time 0.89 seconds
Started Jul 18 05:59:52 PM PDT 24
Finished Jul 18 06:00:02 PM PDT 24
Peak memory 200264 kb
Host smart-2c09bcb1-2722-4fde-87f1-505256ced584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172783764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.172783764
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4245379345
Short name T251
Test name
Test status
Simulation time 651001010 ps
CPU time 3.59 seconds
Started Jul 18 05:59:52 PM PDT 24
Finished Jul 18 06:00:04 PM PDT 24
Peak memory 200808 kb
Host smart-0f87b7fa-8425-4c1d-aa1b-3284594c2f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245379345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4245379345
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1702998788
Short name T474
Test name
Test status
Simulation time 170656552 ps
CPU time 1.16 seconds
Started Jul 18 05:59:50 PM PDT 24
Finished Jul 18 06:00:00 PM PDT 24
Peak memory 200468 kb
Host smart-ad254710-dcb5-4496-a07b-b5ea4555c34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702998788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1702998788
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2494403978
Short name T479
Test name
Test status
Simulation time 115369008 ps
CPU time 1.19 seconds
Started Jul 18 06:00:00 PM PDT 24
Finished Jul 18 06:00:07 PM PDT 24
Peak memory 200676 kb
Host smart-23923e29-fed6-4cea-b815-23b8bea62d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494403978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2494403978
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3126873653
Short name T300
Test name
Test status
Simulation time 2860139252 ps
CPU time 13.18 seconds
Started Jul 18 06:00:04 PM PDT 24
Finished Jul 18 06:00:22 PM PDT 24
Peak memory 208992 kb
Host smart-44af3216-1aea-4e8a-a678-533693fea0b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126873653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3126873653
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.440234059
Short name T257
Test name
Test status
Simulation time 406816135 ps
CPU time 2.31 seconds
Started Jul 18 05:59:58 PM PDT 24
Finished Jul 18 06:00:07 PM PDT 24
Peak memory 200500 kb
Host smart-c6f7ed22-8085-4111-8452-e3bc34fbd826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440234059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.440234059
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2768426302
Short name T411
Test name
Test status
Simulation time 92122802 ps
CPU time 0.89 seconds
Started Jul 18 06:00:02 PM PDT 24
Finished Jul 18 06:00:08 PM PDT 24
Peak memory 200436 kb
Host smart-911c709d-8a63-42fe-b8e9-6295aa77b769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768426302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2768426302
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3100389126
Short name T468
Test name
Test status
Simulation time 78027569 ps
CPU time 0.82 seconds
Started Jul 18 06:00:02 PM PDT 24
Finished Jul 18 06:00:08 PM PDT 24
Peak memory 200276 kb
Host smart-4298f970-2860-4c97-bab1-29154281d78b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100389126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3100389126
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2856962114
Short name T455
Test name
Test status
Simulation time 1890971889 ps
CPU time 7.07 seconds
Started Jul 18 06:00:06 PM PDT 24
Finished Jul 18 06:00:17 PM PDT 24
Peak memory 217776 kb
Host smart-f6319f13-cdbf-436d-a575-791a706aa393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856962114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2856962114
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3279831343
Short name T405
Test name
Test status
Simulation time 244321788 ps
CPU time 1.06 seconds
Started Jul 18 05:59:52 PM PDT 24
Finished Jul 18 06:00:01 PM PDT 24
Peak memory 217488 kb
Host smart-add7b69c-b0c5-4ce2-ae31-8ef7f50b4393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279831343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3279831343
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1093713879
Short name T198
Test name
Test status
Simulation time 108230848 ps
CPU time 0.83 seconds
Started Jul 18 05:59:48 PM PDT 24
Finished Jul 18 05:59:59 PM PDT 24
Peak memory 200204 kb
Host smart-baee0848-d8f1-452a-bf6e-6c5f2c570d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093713879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1093713879
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2812140218
Short name T398
Test name
Test status
Simulation time 747736634 ps
CPU time 3.92 seconds
Started Jul 18 05:59:48 PM PDT 24
Finished Jul 18 06:00:02 PM PDT 24
Peak memory 200764 kb
Host smart-70262bf1-ae38-452b-8870-53e4be36e1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812140218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2812140218
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1798460322
Short name T195
Test name
Test status
Simulation time 101993857 ps
CPU time 1.05 seconds
Started Jul 18 05:59:58 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 200480 kb
Host smart-58283c30-aa41-414c-8066-5aa942730941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798460322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1798460322
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2122029873
Short name T126
Test name
Test status
Simulation time 236286046 ps
CPU time 1.46 seconds
Started Jul 18 05:59:45 PM PDT 24
Finished Jul 18 05:59:58 PM PDT 24
Peak memory 200664 kb
Host smart-ca557304-2f56-41cd-a83f-6e62fe5b3436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122029873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2122029873
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1329347032
Short name T252
Test name
Test status
Simulation time 7236422103 ps
CPU time 33.72 seconds
Started Jul 18 05:59:50 PM PDT 24
Finished Jul 18 06:00:33 PM PDT 24
Peak memory 200784 kb
Host smart-0bbc421e-7625-4aec-bebc-82593ebab046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329347032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1329347032
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3906236216
Short name T230
Test name
Test status
Simulation time 407950449 ps
CPU time 2.39 seconds
Started Jul 18 05:59:50 PM PDT 24
Finished Jul 18 06:00:02 PM PDT 24
Peak memory 200492 kb
Host smart-65bbd012-99c8-4cad-a741-2faa8552baa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906236216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3906236216
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2378903749
Short name T194
Test name
Test status
Simulation time 76607234 ps
CPU time 0.84 seconds
Started Jul 18 06:00:00 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 200488 kb
Host smart-18fc86a8-0102-484a-b393-c841bc9dcd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378903749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2378903749
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3438471153
Short name T146
Test name
Test status
Simulation time 88818781 ps
CPU time 0.89 seconds
Started Jul 18 06:00:03 PM PDT 24
Finished Jul 18 06:00:09 PM PDT 24
Peak memory 200300 kb
Host smart-1de7854a-0cd5-4fb5-bb9b-6389fac23bd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438471153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3438471153
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.866161526
Short name T529
Test name
Test status
Simulation time 1895719734 ps
CPU time 7.08 seconds
Started Jul 18 06:00:00 PM PDT 24
Finished Jul 18 06:00:13 PM PDT 24
Peak memory 221800 kb
Host smart-3a1bc5ba-4ca8-4732-8a07-b0b0b6d65042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866161526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.866161526
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.393966429
Short name T387
Test name
Test status
Simulation time 244202699 ps
CPU time 1.08 seconds
Started Jul 18 06:00:01 PM PDT 24
Finished Jul 18 06:00:07 PM PDT 24
Peak memory 217488 kb
Host smart-806f6006-314b-41a6-a8fe-d97cb5d4876f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393966429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.393966429
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2207549028
Short name T442
Test name
Test status
Simulation time 151989493 ps
CPU time 0.83 seconds
Started Jul 18 06:00:05 PM PDT 24
Finished Jul 18 06:00:11 PM PDT 24
Peak memory 200500 kb
Host smart-47a422a9-a003-406d-8194-90f29e11893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207549028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2207549028
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3175113002
Short name T537
Test name
Test status
Simulation time 1994495544 ps
CPU time 7.54 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 200780 kb
Host smart-e7d62d64-574e-494f-80da-e1acc35beb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175113002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3175113002
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3410087614
Short name T1
Test name
Test status
Simulation time 173040558 ps
CPU time 1.18 seconds
Started Jul 18 05:59:48 PM PDT 24
Finished Jul 18 05:59:59 PM PDT 24
Peak memory 200456 kb
Host smart-e3aa236e-1186-42ef-8706-3ce2659a428d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410087614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3410087614
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2819106509
Short name T538
Test name
Test status
Simulation time 107826878 ps
CPU time 1.2 seconds
Started Jul 18 05:59:51 PM PDT 24
Finished Jul 18 06:00:01 PM PDT 24
Peak memory 200696 kb
Host smart-fd93e0fa-c49c-4331-b292-4518e96f5c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819106509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2819106509
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4265041277
Short name T225
Test name
Test status
Simulation time 1162758069 ps
CPU time 5.64 seconds
Started Jul 18 05:59:47 PM PDT 24
Finished Jul 18 06:00:03 PM PDT 24
Peak memory 200784 kb
Host smart-a41fa24b-9d6b-4500-9cc1-d900ecff6913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265041277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4265041277
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.101249309
Short name T259
Test name
Test status
Simulation time 280156819 ps
CPU time 1.6 seconds
Started Jul 18 05:59:57 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 200456 kb
Host smart-ab597960-7409-4252-9c83-0a67211e9f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101249309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.101249309
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.470879280
Short name T44
Test name
Test status
Simulation time 89064557 ps
CPU time 0.89 seconds
Started Jul 18 05:59:51 PM PDT 24
Finished Jul 18 06:00:01 PM PDT 24
Peak memory 200344 kb
Host smart-9e5c2057-096b-47ac-a39b-cf533880df92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470879280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.470879280
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3757852414
Short name T487
Test name
Test status
Simulation time 2370057132 ps
CPU time 9.1 seconds
Started Jul 18 06:00:00 PM PDT 24
Finished Jul 18 06:00:15 PM PDT 24
Peak memory 217836 kb
Host smart-8cb5ee37-61f6-49df-9ef2-cfce6df84129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757852414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3757852414
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3507412274
Short name T425
Test name
Test status
Simulation time 245193408 ps
CPU time 1.11 seconds
Started Jul 18 06:00:00 PM PDT 24
Finished Jul 18 06:00:07 PM PDT 24
Peak memory 217436 kb
Host smart-560d9546-7655-4368-a66a-81255fdf5900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507412274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3507412274
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1311421152
Short name T340
Test name
Test status
Simulation time 184119067 ps
CPU time 0.94 seconds
Started Jul 18 05:59:48 PM PDT 24
Finished Jul 18 05:59:58 PM PDT 24
Peak memory 200272 kb
Host smart-25b3d951-ac05-4abd-be2f-34e930851fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311421152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1311421152
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2232114675
Short name T526
Test name
Test status
Simulation time 2098129978 ps
CPU time 8.08 seconds
Started Jul 18 05:59:56 PM PDT 24
Finished Jul 18 06:00:11 PM PDT 24
Peak memory 200724 kb
Host smart-4bf6a162-dc98-4298-b707-dafaa8705a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232114675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2232114675
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3628536160
Short name T264
Test name
Test status
Simulation time 108987479 ps
CPU time 1.06 seconds
Started Jul 18 05:59:57 PM PDT 24
Finished Jul 18 06:00:05 PM PDT 24
Peak memory 200464 kb
Host smart-78e97747-8be3-4952-b81c-233974ecc0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628536160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3628536160
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3893046607
Short name T184
Test name
Test status
Simulation time 112782949 ps
CPU time 1.27 seconds
Started Jul 18 05:59:50 PM PDT 24
Finished Jul 18 06:00:00 PM PDT 24
Peak memory 200676 kb
Host smart-5ad97df7-da28-42b4-a0a3-8d958e75a2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893046607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3893046607
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.437986948
Short name T507
Test name
Test status
Simulation time 3216380281 ps
CPU time 14.66 seconds
Started Jul 18 05:59:50 PM PDT 24
Finished Jul 18 06:00:14 PM PDT 24
Peak memory 200800 kb
Host smart-ea8b5d20-7cc8-40ed-b4d1-a09ab50de2c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437986948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.437986948
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.192530192
Short name T518
Test name
Test status
Simulation time 308831166 ps
CPU time 2.12 seconds
Started Jul 18 06:00:00 PM PDT 24
Finished Jul 18 06:00:08 PM PDT 24
Peak memory 208688 kb
Host smart-411a6841-c892-42f2-bf52-3acfb89db9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192530192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.192530192
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1796155345
Short name T288
Test name
Test status
Simulation time 156776683 ps
CPU time 1.26 seconds
Started Jul 18 06:00:03 PM PDT 24
Finished Jul 18 06:00:10 PM PDT 24
Peak memory 200676 kb
Host smart-dc87c343-f71b-4951-9b40-1f3c3e8f2ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796155345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1796155345
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1109489537
Short name T456
Test name
Test status
Simulation time 74397867 ps
CPU time 0.79 seconds
Started Jul 18 05:59:59 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 200280 kb
Host smart-14110c67-a57f-40a7-a538-4413b78e89e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109489537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1109489537
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.650928905
Short name T460
Test name
Test status
Simulation time 1895054491 ps
CPU time 7.57 seconds
Started Jul 18 06:00:02 PM PDT 24
Finished Jul 18 06:00:16 PM PDT 24
Peak memory 217420 kb
Host smart-98777963-1fb5-41bd-9ae3-a3dc5eb0962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650928905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.650928905
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2293120021
Short name T164
Test name
Test status
Simulation time 243994844 ps
CPU time 1.24 seconds
Started Jul 18 05:59:53 PM PDT 24
Finished Jul 18 06:00:02 PM PDT 24
Peak memory 217584 kb
Host smart-c58eded6-b8ed-4cbd-8129-85af1e4e7127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293120021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2293120021
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.855231833
Short name T12
Test name
Test status
Simulation time 198022548 ps
CPU time 0.88 seconds
Started Jul 18 05:59:48 PM PDT 24
Finished Jul 18 05:59:59 PM PDT 24
Peak memory 200276 kb
Host smart-a7d2daa7-8426-41a4-9f63-24acf52b21d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855231833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.855231833
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2147748492
Short name T20
Test name
Test status
Simulation time 1297211106 ps
CPU time 5.23 seconds
Started Jul 18 05:59:56 PM PDT 24
Finished Jul 18 06:00:09 PM PDT 24
Peak memory 200788 kb
Host smart-5b7f1328-d23f-4f71-9d73-874ca548521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147748492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2147748492
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3090882701
Short name T360
Test name
Test status
Simulation time 100148940 ps
CPU time 1.03 seconds
Started Jul 18 06:00:06 PM PDT 24
Finished Jul 18 06:00:12 PM PDT 24
Peak memory 200468 kb
Host smart-d05cf8da-8172-4f6e-9883-7b524c91e9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090882701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3090882701
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.351029590
Short name T70
Test name
Test status
Simulation time 254860781 ps
CPU time 1.54 seconds
Started Jul 18 06:00:06 PM PDT 24
Finished Jul 18 06:00:12 PM PDT 24
Peak memory 200680 kb
Host smart-57134ff6-91ce-4160-b690-111cfd885956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351029590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.351029590
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.566369397
Short name T309
Test name
Test status
Simulation time 2637340243 ps
CPU time 10.94 seconds
Started Jul 18 05:59:49 PM PDT 24
Finished Jul 18 06:00:10 PM PDT 24
Peak memory 200844 kb
Host smart-82e4bf59-267d-4c1a-8883-f055e312ed61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566369397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.566369397
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2664110583
Short name T53
Test name
Test status
Simulation time 388490891 ps
CPU time 2.61 seconds
Started Jul 18 05:59:51 PM PDT 24
Finished Jul 18 06:00:03 PM PDT 24
Peak memory 200488 kb
Host smart-6b927939-d614-494d-b8a2-8f0d22295412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664110583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2664110583
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1192034409
Short name T291
Test name
Test status
Simulation time 88575128 ps
CPU time 0.81 seconds
Started Jul 18 05:59:50 PM PDT 24
Finished Jul 18 06:00:00 PM PDT 24
Peak memory 200312 kb
Host smart-ea7355d2-2224-4c8c-9d69-3d30547b133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192034409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1192034409
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2231038296
Short name T160
Test name
Test status
Simulation time 59272800 ps
CPU time 0.77 seconds
Started Jul 18 05:59:51 PM PDT 24
Finished Jul 18 06:00:01 PM PDT 24
Peak memory 200288 kb
Host smart-3f1352d2-f527-40a6-aee8-d5ac019c463d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231038296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2231038296
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2546643587
Short name T434
Test name
Test status
Simulation time 1225410495 ps
CPU time 5.61 seconds
Started Jul 18 05:59:51 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 221744 kb
Host smart-f1ca2b43-ff4e-425a-9cba-4756e26349c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546643587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2546643587
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3556157448
Short name T274
Test name
Test status
Simulation time 244414145 ps
CPU time 1.04 seconds
Started Jul 18 05:59:54 PM PDT 24
Finished Jul 18 06:00:03 PM PDT 24
Peak memory 217472 kb
Host smart-bc4f2ae4-57c7-497d-be77-ad99b130fcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556157448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3556157448
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.239358410
Short name T176
Test name
Test status
Simulation time 217863335 ps
CPU time 0.9 seconds
Started Jul 18 06:00:02 PM PDT 24
Finished Jul 18 06:00:08 PM PDT 24
Peak memory 200280 kb
Host smart-44a2af1d-4f2c-4c8c-b499-6d5175737fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239358410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.239358410
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2224175089
Short name T93
Test name
Test status
Simulation time 1696077183 ps
CPU time 7.06 seconds
Started Jul 18 05:59:56 PM PDT 24
Finished Jul 18 06:00:11 PM PDT 24
Peak memory 200744 kb
Host smart-18c0d602-c9ea-4216-bd40-d05bc271ef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224175089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2224175089
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3453502174
Short name T401
Test name
Test status
Simulation time 100772669 ps
CPU time 1.05 seconds
Started Jul 18 05:59:53 PM PDT 24
Finished Jul 18 06:00:02 PM PDT 24
Peak memory 200480 kb
Host smart-ae60c4a8-0bb0-4f7c-ad27-729a168386f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453502174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3453502174
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3771402937
Short name T59
Test name
Test status
Simulation time 193742647 ps
CPU time 1.39 seconds
Started Jul 18 06:00:01 PM PDT 24
Finished Jul 18 06:00:08 PM PDT 24
Peak memory 200680 kb
Host smart-e1e3c2c3-65a3-4516-bf1e-254f6004911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771402937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3771402937
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.26100549
Short name T96
Test name
Test status
Simulation time 11960290901 ps
CPU time 44.59 seconds
Started Jul 18 06:00:06 PM PDT 24
Finished Jul 18 06:00:55 PM PDT 24
Peak memory 200812 kb
Host smart-6b7ff7a7-d654-410c-af0e-87d31c397c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26100549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.26100549
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.4230344337
Short name T228
Test name
Test status
Simulation time 379077206 ps
CPU time 2.32 seconds
Started Jul 18 06:00:03 PM PDT 24
Finished Jul 18 06:00:11 PM PDT 24
Peak memory 200472 kb
Host smart-7c7ca926-ac20-4ef9-90ef-d248f9393d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230344337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.4230344337
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3628461682
Short name T135
Test name
Test status
Simulation time 85152745 ps
CPU time 0.92 seconds
Started Jul 18 05:59:56 PM PDT 24
Finished Jul 18 06:00:04 PM PDT 24
Peak memory 200456 kb
Host smart-db31c7d7-cc9c-4728-9f2b-d0499a0986c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628461682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3628461682
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2331350705
Short name T329
Test name
Test status
Simulation time 70698661 ps
CPU time 0.81 seconds
Started Jul 18 06:00:06 PM PDT 24
Finished Jul 18 06:00:11 PM PDT 24
Peak memory 200300 kb
Host smart-d43e6ab4-79b6-4a04-a4da-be807ac9ac7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331350705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2331350705
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1734349516
Short name T178
Test name
Test status
Simulation time 2359710412 ps
CPU time 7.89 seconds
Started Jul 18 06:00:11 PM PDT 24
Finished Jul 18 06:00:23 PM PDT 24
Peak memory 221844 kb
Host smart-419b4c70-4208-459d-b77e-d28d6ea5ee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734349516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1734349516
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1090887600
Short name T196
Test name
Test status
Simulation time 244209339 ps
CPU time 1.14 seconds
Started Jul 18 05:59:53 PM PDT 24
Finished Jul 18 06:00:02 PM PDT 24
Peak memory 217516 kb
Host smart-f38844ad-6413-4218-893f-8326dbc26499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090887600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1090887600
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3174362788
Short name T362
Test name
Test status
Simulation time 121120195 ps
CPU time 0.83 seconds
Started Jul 18 05:59:55 PM PDT 24
Finished Jul 18 06:00:03 PM PDT 24
Peak memory 200276 kb
Host smart-7a9a8a4a-e2f1-4a2f-8377-8cffdc0c280a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174362788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3174362788
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2315461100
Short name T75
Test name
Test status
Simulation time 1792295341 ps
CPU time 6.55 seconds
Started Jul 18 06:00:02 PM PDT 24
Finished Jul 18 06:00:15 PM PDT 24
Peak memory 200796 kb
Host smart-fa765b20-90c6-4079-8949-cafd1f3fb40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315461100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2315461100
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1025728885
Short name T21
Test name
Test status
Simulation time 158575827 ps
CPU time 1.13 seconds
Started Jul 18 05:59:56 PM PDT 24
Finished Jul 18 06:00:05 PM PDT 24
Peak memory 200468 kb
Host smart-22924f5c-931c-4c76-8e31-e2bc832046e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025728885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1025728885
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.85144896
Short name T489
Test name
Test status
Simulation time 117164628 ps
CPU time 1.19 seconds
Started Jul 18 06:00:01 PM PDT 24
Finished Jul 18 06:00:08 PM PDT 24
Peak memory 200664 kb
Host smart-4ed99ac4-716a-458b-9185-5facc2b1c4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85144896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.85144896
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3236622539
Short name T298
Test name
Test status
Simulation time 2433591586 ps
CPU time 10.64 seconds
Started Jul 18 06:00:05 PM PDT 24
Finished Jul 18 06:00:21 PM PDT 24
Peak memory 200860 kb
Host smart-31e0d14a-051e-43ab-8f18-1c425cd99cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236622539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3236622539
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.632974993
Short name T407
Test name
Test status
Simulation time 290453390 ps
CPU time 1.99 seconds
Started Jul 18 05:59:57 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 208680 kb
Host smart-5eb82234-ce83-4474-a394-34b57894e90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632974993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.632974993
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.474416962
Short name T483
Test name
Test status
Simulation time 210662757 ps
CPU time 1.28 seconds
Started Jul 18 06:00:05 PM PDT 24
Finished Jul 18 06:00:11 PM PDT 24
Peak memory 200480 kb
Host smart-570f0ec6-9bc3-470a-a521-ff162e29b1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474416962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.474416962
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3904808692
Short name T396
Test name
Test status
Simulation time 88607118 ps
CPU time 0.85 seconds
Started Jul 18 06:00:20 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 200216 kb
Host smart-dd297ca9-35c4-46e5-978d-8a20a3fb98fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904808692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3904808692
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.989582111
Short name T354
Test name
Test status
Simulation time 1222963115 ps
CPU time 5.36 seconds
Started Jul 18 06:00:10 PM PDT 24
Finished Jul 18 06:00:20 PM PDT 24
Peak memory 217856 kb
Host smart-86c5d7b0-9236-4346-80fa-cddc934d426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989582111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.989582111
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1144988394
Short name T235
Test name
Test status
Simulation time 245027076 ps
CPU time 1.04 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 217540 kb
Host smart-0338a540-ad45-45b5-8b7c-7d30e3264407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144988394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1144988394
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3285266047
Short name T357
Test name
Test status
Simulation time 125321917 ps
CPU time 0.85 seconds
Started Jul 18 05:59:55 PM PDT 24
Finished Jul 18 06:00:04 PM PDT 24
Peak memory 200308 kb
Host smart-4786786d-8854-4ff7-a2fa-d87977d8aa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285266047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3285266047
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3752713536
Short name T353
Test name
Test status
Simulation time 1059490660 ps
CPU time 5.24 seconds
Started Jul 18 05:59:52 PM PDT 24
Finished Jul 18 06:00:05 PM PDT 24
Peak memory 200800 kb
Host smart-b86e7b3a-8dee-4653-9edb-c64cf623909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752713536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3752713536
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3770431732
Short name T221
Test name
Test status
Simulation time 108317421 ps
CPU time 0.98 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:23 PM PDT 24
Peak memory 200388 kb
Host smart-2471f4fd-cd15-41d9-bbdf-5abda1e57bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770431732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3770431732
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1763543299
Short name T451
Test name
Test status
Simulation time 127438741 ps
CPU time 1.31 seconds
Started Jul 18 05:59:55 PM PDT 24
Finished Jul 18 06:00:03 PM PDT 24
Peak memory 200700 kb
Host smart-ced0be51-1ef6-4064-ada5-076efd0e9d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763543299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1763543299
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.862912798
Short name T424
Test name
Test status
Simulation time 545539017 ps
CPU time 2.46 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:27 PM PDT 24
Peak memory 200680 kb
Host smart-057ab949-078e-4b1b-9467-e59e228e54f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862912798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.862912798
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2873827946
Short name T351
Test name
Test status
Simulation time 433120083 ps
CPU time 2.39 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:27 PM PDT 24
Peak memory 208676 kb
Host smart-da8798cf-739e-46bb-92d3-cfbd9a4463a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873827946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2873827946
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.134536317
Short name T391
Test name
Test status
Simulation time 218860591 ps
CPU time 1.37 seconds
Started Jul 18 06:00:13 PM PDT 24
Finished Jul 18 06:00:21 PM PDT 24
Peak memory 200464 kb
Host smart-12b7421b-b2a0-4d1a-bc3b-5f767f1f37c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134536317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.134536317
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1277652605
Short name T5
Test name
Test status
Simulation time 64064675 ps
CPU time 0.8 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 200248 kb
Host smart-59b8f833-c244-4d47-92fc-7579fd94c70d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277652605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1277652605
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3964758520
Short name T30
Test name
Test status
Simulation time 2351014070 ps
CPU time 9.24 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:33 PM PDT 24
Peak memory 217892 kb
Host smart-17f20723-0f54-44c5-bc7c-50c5fbb6bf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964758520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3964758520
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1098738481
Short name T513
Test name
Test status
Simulation time 245824307 ps
CPU time 1.02 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:27 PM PDT 24
Peak memory 217500 kb
Host smart-9a55d77c-bac2-4f3b-9a6c-67d26912e21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098738481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1098738481
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1520497797
Short name T167
Test name
Test status
Simulation time 201399472 ps
CPU time 1.01 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:30 PM PDT 24
Peak memory 200272 kb
Host smart-2ce21733-ac23-4932-beab-7a47699e12c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520497797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1520497797
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.428079670
Short name T233
Test name
Test status
Simulation time 870741780 ps
CPU time 4.12 seconds
Started Jul 18 06:00:19 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 200720 kb
Host smart-2b395d74-c394-40ea-8652-8c47f1e22f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428079670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.428079670
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2034015525
Short name T464
Test name
Test status
Simulation time 144735573 ps
CPU time 1.1 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:22 PM PDT 24
Peak memory 200484 kb
Host smart-64d9c8eb-ddae-4c92-bab8-b6dffd5f415a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034015525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2034015525
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.4156777701
Short name T118
Test name
Test status
Simulation time 11211701800 ps
CPU time 41.34 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:01:05 PM PDT 24
Peak memory 209856 kb
Host smart-a199b235-2649-497f-80ff-3c302b26b7d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156777701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4156777701
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1866539752
Short name T539
Test name
Test status
Simulation time 326984230 ps
CPU time 2.22 seconds
Started Jul 18 06:00:13 PM PDT 24
Finished Jul 18 06:00:22 PM PDT 24
Peak memory 200500 kb
Host smart-3c68322f-508f-4919-9c26-01d870f4ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866539752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1866539752
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.4066452353
Short name T177
Test name
Test status
Simulation time 148989185 ps
CPU time 1.21 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 200528 kb
Host smart-823fa6af-a006-47f6-9571-ddbb0eec4e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066452353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.4066452353
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.6355197
Short name T141
Test name
Test status
Simulation time 63898515 ps
CPU time 0.76 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:24 PM PDT 24
Peak memory 200256 kb
Host smart-1c37f844-97e1-4b62-ad1e-7c83dcfba729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6355197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.6355197
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1267885017
Short name T25
Test name
Test status
Simulation time 1215832340 ps
CPU time 5.27 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:33 PM PDT 24
Peak memory 221712 kb
Host smart-76c34d2a-b47d-4583-b418-aa2ca2326232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267885017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1267885017
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.771003361
Short name T465
Test name
Test status
Simulation time 244195836 ps
CPU time 1.08 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 217480 kb
Host smart-77d03763-93be-4a62-8795-9ecd7ddf06fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771003361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.771003361
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.393361111
Short name T470
Test name
Test status
Simulation time 143734862 ps
CPU time 0.91 seconds
Started Jul 18 06:00:30 PM PDT 24
Finished Jul 18 06:00:37 PM PDT 24
Peak memory 200296 kb
Host smart-e83d2c80-6795-46a5-9bf7-9cd465e13608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393361111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.393361111
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1912974099
Short name T148
Test name
Test status
Simulation time 1231000764 ps
CPU time 5.77 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:33 PM PDT 24
Peak memory 200768 kb
Host smart-b0116950-5388-4113-8d56-6957a48caea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912974099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1912974099
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1490409761
Short name T361
Test name
Test status
Simulation time 157958568 ps
CPU time 1.12 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 200388 kb
Host smart-58df2ad8-97a1-4bce-b271-4df18dd784d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490409761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1490409761
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1421931112
Short name T58
Test name
Test status
Simulation time 193874577 ps
CPU time 1.41 seconds
Started Jul 18 06:00:13 PM PDT 24
Finished Jul 18 06:00:20 PM PDT 24
Peak memory 200676 kb
Host smart-3832d025-aa63-4d1b-b684-0dc5d6417c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421931112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1421931112
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3731025486
Short name T255
Test name
Test status
Simulation time 1996248482 ps
CPU time 8.21 seconds
Started Jul 18 06:00:20 PM PDT 24
Finished Jul 18 06:00:39 PM PDT 24
Peak memory 208880 kb
Host smart-f2972676-85f3-4fcd-beb6-2b43a0a6012d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731025486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3731025486
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1668752980
Short name T380
Test name
Test status
Simulation time 391656738 ps
CPU time 2.86 seconds
Started Jul 18 06:00:32 PM PDT 24
Finished Jul 18 06:00:39 PM PDT 24
Peak memory 200488 kb
Host smart-6ed7e7f0-d2bb-4c8c-9291-507dabee18c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668752980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1668752980
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.336109961
Short name T187
Test name
Test status
Simulation time 137831419 ps
CPU time 1.02 seconds
Started Jul 18 06:00:12 PM PDT 24
Finished Jul 18 06:00:18 PM PDT 24
Peak memory 200472 kb
Host smart-d353aeb5-acc0-4591-83c5-42644abc37e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336109961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.336109961
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3202971172
Short name T333
Test name
Test status
Simulation time 60359521 ps
CPU time 0.72 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:59:00 PM PDT 24
Peak memory 200284 kb
Host smart-e2f8aadb-2b1a-4fc8-8cb6-d73203bc03dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202971172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3202971172
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.4147439433
Short name T525
Test name
Test status
Simulation time 1220549582 ps
CPU time 5.65 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:06 PM PDT 24
Peak memory 221776 kb
Host smart-3ce19786-8cb5-4ff4-99e8-9871909ef37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147439433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4147439433
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.811857350
Short name T504
Test name
Test status
Simulation time 243498461 ps
CPU time 1.18 seconds
Started Jul 18 05:58:58 PM PDT 24
Finished Jul 18 05:59:10 PM PDT 24
Peak memory 217584 kb
Host smart-6b928736-25e7-4733-8c82-fda110637b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811857350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.811857350
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1286209931
Short name T418
Test name
Test status
Simulation time 116151847 ps
CPU time 0.8 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:58:58 PM PDT 24
Peak memory 200340 kb
Host smart-649a8ee9-4dfc-45ac-8dca-0fc2c49e7030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286209931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1286209931
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3749501310
Short name T97
Test name
Test status
Simulation time 1217466419 ps
CPU time 5.13 seconds
Started Jul 18 05:58:52 PM PDT 24
Finished Jul 18 05:59:00 PM PDT 24
Peak memory 200724 kb
Host smart-b8d09561-27be-4fe9-82f0-cbd191a7ef90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749501310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3749501310
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3829887941
Short name T322
Test name
Test status
Simulation time 108198780 ps
CPU time 1.04 seconds
Started Jul 18 05:59:03 PM PDT 24
Finished Jul 18 05:59:11 PM PDT 24
Peak memory 200452 kb
Host smart-3198b8ab-14d3-46dd-a937-cff43905134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829887941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3829887941
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1585786738
Short name T494
Test name
Test status
Simulation time 109236042 ps
CPU time 1.28 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:03 PM PDT 24
Peak memory 200624 kb
Host smart-a42f8e86-2196-437b-9633-607eba0c2a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585786738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1585786738
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2001177853
Short name T343
Test name
Test status
Simulation time 2283218474 ps
CPU time 8.91 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:12 PM PDT 24
Peak memory 208996 kb
Host smart-5ec1df2e-5130-43ab-83fa-0e8e365f5819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001177853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2001177853
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3055882350
Short name T286
Test name
Test status
Simulation time 154541636 ps
CPU time 1.88 seconds
Started Jul 18 05:58:52 PM PDT 24
Finished Jul 18 05:58:57 PM PDT 24
Peak memory 200428 kb
Host smart-43698e07-950c-497c-969c-74983d1ccb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055882350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3055882350
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1822095053
Short name T294
Test name
Test status
Simulation time 116989545 ps
CPU time 1.1 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:01 PM PDT 24
Peak memory 200456 kb
Host smart-eae16cc9-eb8e-4cdc-8bc6-dd2ba199d24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822095053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1822095053
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1870532884
Short name T199
Test name
Test status
Simulation time 64731536 ps
CPU time 0.78 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:00 PM PDT 24
Peak memory 200216 kb
Host smart-8ad52fe3-249a-472d-99e6-a357d6b3a0bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870532884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1870532884
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3558725336
Short name T433
Test name
Test status
Simulation time 1876377501 ps
CPU time 7.08 seconds
Started Jul 18 05:58:57 PM PDT 24
Finished Jul 18 05:59:14 PM PDT 24
Peak memory 216224 kb
Host smart-dbdbdfe2-e1c1-4c36-a86b-c373bb39d11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558725336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3558725336
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.883417604
Short name T480
Test name
Test status
Simulation time 245280550 ps
CPU time 1.05 seconds
Started Jul 18 05:58:58 PM PDT 24
Finished Jul 18 05:59:09 PM PDT 24
Peak memory 217476 kb
Host smart-b50928cb-d03d-4333-8181-6c92150dad2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883417604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.883417604
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1493318305
Short name T272
Test name
Test status
Simulation time 210649391 ps
CPU time 0.91 seconds
Started Jul 18 05:58:58 PM PDT 24
Finished Jul 18 05:59:09 PM PDT 24
Peak memory 200152 kb
Host smart-2678d92a-c2e1-49f0-b577-b85cf37d4ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493318305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1493318305
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3122739194
Short name T421
Test name
Test status
Simulation time 1653340326 ps
CPU time 6.81 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:59:05 PM PDT 24
Peak memory 200696 kb
Host smart-b9e00648-5413-4023-8533-64a5c5e4bdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122739194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3122739194
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2433953664
Short name T181
Test name
Test status
Simulation time 141159023 ps
CPU time 1.19 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:02 PM PDT 24
Peak memory 200464 kb
Host smart-33a94b0b-1952-4036-a2ea-e21d91153be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433953664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2433953664
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2003067407
Short name T262
Test name
Test status
Simulation time 110999495 ps
CPU time 1.2 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:01 PM PDT 24
Peak memory 200676 kb
Host smart-adf81a3e-eac4-4f37-af79-0f7cfd638c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003067407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2003067407
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.288051362
Short name T260
Test name
Test status
Simulation time 129581623 ps
CPU time 1.72 seconds
Started Jul 18 05:58:59 PM PDT 24
Finished Jul 18 05:59:10 PM PDT 24
Peak memory 200408 kb
Host smart-79ec36b6-26c2-4d58-a05a-7eeef57c73c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288051362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.288051362
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2074770635
Short name T76
Test name
Test status
Simulation time 134815433 ps
CPU time 1.12 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:02 PM PDT 24
Peak memory 200468 kb
Host smart-dc6d6b0f-422f-4ada-b410-ac8157851a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074770635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2074770635
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2830967790
Short name T140
Test name
Test status
Simulation time 83484823 ps
CPU time 0.84 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:03 PM PDT 24
Peak memory 200272 kb
Host smart-f3019407-4496-4597-ba06-b99c44734fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830967790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2830967790
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2926423045
Short name T412
Test name
Test status
Simulation time 1896672440 ps
CPU time 7.76 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:11 PM PDT 24
Peak memory 217596 kb
Host smart-90eaecc6-6f97-45cd-a8a9-d021813fa415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926423045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2926423045
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2821662853
Short name T242
Test name
Test status
Simulation time 244625350 ps
CPU time 1.08 seconds
Started Jul 18 05:58:57 PM PDT 24
Finished Jul 18 05:59:07 PM PDT 24
Peak memory 217416 kb
Host smart-9df690cc-b2e4-452c-9c8e-e789691799d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821662853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2821662853
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.456098819
Short name T320
Test name
Test status
Simulation time 165606652 ps
CPU time 0.88 seconds
Started Jul 18 05:59:00 PM PDT 24
Finished Jul 18 05:59:10 PM PDT 24
Peak memory 200272 kb
Host smart-9bfb13fa-94a7-4493-9683-fc78c29a7482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456098819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.456098819
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1220308132
Short name T94
Test name
Test status
Simulation time 1917249522 ps
CPU time 7.62 seconds
Started Jul 18 05:58:57 PM PDT 24
Finished Jul 18 05:59:14 PM PDT 24
Peak memory 200756 kb
Host smart-bf7dfad7-17c3-4a29-aa1b-33adcc7cc339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220308132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1220308132
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2681523532
Short name T328
Test name
Test status
Simulation time 182738218 ps
CPU time 1.26 seconds
Started Jul 18 05:58:58 PM PDT 24
Finished Jul 18 05:59:09 PM PDT 24
Peak memory 200464 kb
Host smart-7c3b8eda-b976-421d-960d-a8e5548a9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681523532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2681523532
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3924522989
Short name T231
Test name
Test status
Simulation time 198239808 ps
CPU time 1.35 seconds
Started Jul 18 05:58:58 PM PDT 24
Finished Jul 18 05:59:10 PM PDT 24
Peak memory 200676 kb
Host smart-85771feb-5199-4607-954e-3b28cd0a96c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924522989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3924522989
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.4062718370
Short name T9
Test name
Test status
Simulation time 3438469236 ps
CPU time 14.93 seconds
Started Jul 18 05:58:58 PM PDT 24
Finished Jul 18 05:59:22 PM PDT 24
Peak memory 209012 kb
Host smart-6241da58-3d79-486c-aa53-02b415b20914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062718370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.4062718370
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1352188251
Short name T372
Test name
Test status
Simulation time 496903037 ps
CPU time 2.68 seconds
Started Jul 18 05:58:57 PM PDT 24
Finished Jul 18 05:59:08 PM PDT 24
Peak memory 200488 kb
Host smart-48ac0aee-7c8c-4cd2-b42b-60b3281dbe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352188251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1352188251
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3640981684
Short name T306
Test name
Test status
Simulation time 246998678 ps
CPU time 1.4 seconds
Started Jul 18 05:58:59 PM PDT 24
Finished Jul 18 05:59:10 PM PDT 24
Peak memory 200476 kb
Host smart-a759f6cb-476c-4ade-9834-cc1b1322f9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640981684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3640981684
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2003745268
Short name T277
Test name
Test status
Simulation time 60729641 ps
CPU time 0.76 seconds
Started Jul 18 05:58:56 PM PDT 24
Finished Jul 18 05:59:05 PM PDT 24
Peak memory 200272 kb
Host smart-caaf01a3-b985-43df-9749-62bd36bb59f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003745268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2003745268
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2572641080
Short name T202
Test name
Test status
Simulation time 244356858 ps
CPU time 1.04 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:02 PM PDT 24
Peak memory 217432 kb
Host smart-7df7bb9d-4a82-401d-9982-c81b15153ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572641080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2572641080
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.812038880
Short name T385
Test name
Test status
Simulation time 171913702 ps
CPU time 0.91 seconds
Started Jul 18 05:58:59 PM PDT 24
Finished Jul 18 05:59:09 PM PDT 24
Peak memory 200144 kb
Host smart-4ae70d76-649a-4add-b9e9-d7ad7323ea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812038880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.812038880
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2810339234
Short name T505
Test name
Test status
Simulation time 890671199 ps
CPU time 4.43 seconds
Started Jul 18 05:58:59 PM PDT 24
Finished Jul 18 05:59:13 PM PDT 24
Peak memory 200744 kb
Host smart-af80d518-cc05-409d-8db0-5cb32aa8bda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810339234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2810339234
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.342261989
Short name T236
Test name
Test status
Simulation time 176533567 ps
CPU time 1.27 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:04 PM PDT 24
Peak memory 200472 kb
Host smart-608b9243-9b69-44f9-b13d-8f61969b5d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342261989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.342261989
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2157850721
Short name T238
Test name
Test status
Simulation time 192691328 ps
CPU time 1.38 seconds
Started Jul 18 05:58:59 PM PDT 24
Finished Jul 18 05:59:10 PM PDT 24
Peak memory 200576 kb
Host smart-eac1ed5a-fe47-4926-94ec-21c2094db737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157850721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2157850721
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2480899378
Short name T466
Test name
Test status
Simulation time 3744057285 ps
CPU time 16.8 seconds
Started Jul 18 05:58:56 PM PDT 24
Finished Jul 18 05:59:22 PM PDT 24
Peak memory 209216 kb
Host smart-5aa31094-f1b4-436a-9788-e9da4ee5074c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480899378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2480899378
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3101665038
Short name T33
Test name
Test status
Simulation time 145152974 ps
CPU time 1.78 seconds
Started Jul 18 05:58:54 PM PDT 24
Finished Jul 18 05:59:04 PM PDT 24
Peak memory 208676 kb
Host smart-443a784f-bce5-4c83-9a62-2a0a515b4b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101665038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3101665038
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1269161533
Short name T191
Test name
Test status
Simulation time 66041211 ps
CPU time 0.78 seconds
Started Jul 18 05:58:58 PM PDT 24
Finished Jul 18 05:59:08 PM PDT 24
Peak memory 200368 kb
Host smart-c427d0b7-1cc0-46f7-8fa5-627aba7e8508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269161533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1269161533
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2144354769
Short name T394
Test name
Test status
Simulation time 71119896 ps
CPU time 0.86 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:04 PM PDT 24
Peak memory 200340 kb
Host smart-660cb78b-294c-416e-a187-1d2bf4b7a2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144354769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2144354769
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1512839964
Short name T482
Test name
Test status
Simulation time 2364592521 ps
CPU time 8.26 seconds
Started Jul 18 05:58:52 PM PDT 24
Finished Jul 18 05:59:05 PM PDT 24
Peak memory 217708 kb
Host smart-00a7dbba-3f1c-4a7e-a722-bdd17c4e4723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512839964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1512839964
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2885702624
Short name T370
Test name
Test status
Simulation time 244159854 ps
CPU time 1.17 seconds
Started Jul 18 05:58:59 PM PDT 24
Finished Jul 18 05:59:10 PM PDT 24
Peak memory 217532 kb
Host smart-c9268140-6f00-49c7-8a6a-cf9c11280d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885702624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2885702624
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2327666996
Short name T171
Test name
Test status
Simulation time 81742891 ps
CPU time 0.76 seconds
Started Jul 18 05:59:05 PM PDT 24
Finished Jul 18 05:59:13 PM PDT 24
Peak memory 200268 kb
Host smart-ed522473-96f5-41b4-8057-e73859d2ee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327666996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2327666996
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.893367448
Short name T207
Test name
Test status
Simulation time 1610917452 ps
CPU time 6.86 seconds
Started Jul 18 05:58:56 PM PDT 24
Finished Jul 18 05:59:12 PM PDT 24
Peak memory 200948 kb
Host smart-45afa79c-754b-4745-8364-86871acfb8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893367448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.893367448
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1751877587
Short name T413
Test name
Test status
Simulation time 192067328 ps
CPU time 1.2 seconds
Started Jul 18 05:58:56 PM PDT 24
Finished Jul 18 05:59:05 PM PDT 24
Peak memory 200468 kb
Host smart-ee7e1cdc-c071-47f4-86a0-5626fd05c4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751877587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1751877587
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4096655301
Short name T524
Test name
Test status
Simulation time 194441986 ps
CPU time 1.32 seconds
Started Jul 18 05:58:53 PM PDT 24
Finished Jul 18 05:58:58 PM PDT 24
Peak memory 200596 kb
Host smart-08a30e65-e32c-4475-90ac-d7cce9db344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096655301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4096655301
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1446018698
Short name T488
Test name
Test status
Simulation time 1725340510 ps
CPU time 6.84 seconds
Started Jul 18 05:58:59 PM PDT 24
Finished Jul 18 05:59:15 PM PDT 24
Peak memory 200796 kb
Host smart-b6e388b3-0a55-4f6d-8faf-d933ff1257ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446018698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1446018698
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2518643901
Short name T169
Test name
Test status
Simulation time 358914979 ps
CPU time 2.31 seconds
Started Jul 18 05:58:55 PM PDT 24
Finished Jul 18 05:59:06 PM PDT 24
Peak memory 200484 kb
Host smart-0a2d3beb-dae6-40ba-835a-3b0ae762519d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518643901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2518643901
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.723525958
Short name T301
Test name
Test status
Simulation time 250657972 ps
CPU time 1.47 seconds
Started Jul 18 05:58:57 PM PDT 24
Finished Jul 18 05:59:07 PM PDT 24
Peak memory 200928 kb
Host smart-f51f5cf9-ea10-47ed-89f5-17e08d89a605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723525958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.723525958
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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