Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8522

1

T5

19

T6

31

T11

4

auto[1]

11356

1

T1

4

T4

4

T5

82

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6052	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6710	1			T1	2		T2	1		T3	1
reset_info_cp[2]	3117	1			T1	1		T4	1		T5	18
reset_info_cp[4]	4028	1			T1	1		T4	1		T5	14
reset_info_cp[8]	103	1			T40	1		T26	2		T72	1
reset_info_cp[16]	106	1			T5	1		T11	1		T19	2
reset_info_cp[32]	118	1			T5	1		T6	1		T20	1
reset_info_cp[64]	128	1			T5	1		T24	1		T34	1
reset_info_cp[128]	135	1			T19	1		T24	1		T25	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3204	1			T5	19		T6	8		T19	43
reset_info_cp[1]	auto[1]	2887	1			T1	1		T4	1		T5	7
reset_info_cp[2]	auto[0]	971	1			T6	7		T19	17		T65	3
reset_info_cp[2]	auto[1]	2146	1			T1	1		T4	1		T5	18
reset_info_cp[4]	auto[0]	1475	1			T6	7		T19	19		T65	3
reset_info_cp[4]	auto[1]	2553	1			T1	1		T4	1		T5	14
reset_info_cp[8]	auto[0]	47	1			T73	1		T131	1		T76	1
reset_info_cp[8]	auto[1]	56	1			T40	1		T26	2		T72	1
reset_info_cp[16]	auto[0]	36	1			T19	1		T20	1		T22	1
reset_info_cp[16]	auto[1]	70	1			T5	1		T11	1		T19	1
reset_info_cp[32]	auto[0]	43	1			T6	1		T20	1		T132	1
reset_info_cp[32]	auto[1]	75	1			T5	1		T25	2		T68	1
reset_info_cp[64]	auto[0]	64	1			T34	1		T68	1		T72	1
reset_info_cp[64]	auto[1]	64	1			T5	1		T24	1		T26	1
reset_info_cp[128]	auto[0]	59	1			T19	1		T69	2		T73	2
reset_info_cp[128]	auto[1]	76	1			T24	1		T25	2		T26	1