Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.40 99.40 99.31 99.87 99.83 99.46 98.52


Total test records in report: 619
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.41702490 Jul 19 05:08:48 PM PDT 24 Jul 19 05:09:00 PM PDT 24 2370763072 ps
T537 /workspace/coverage/default/43.rstmgr_alert_test.3967018727 Jul 19 05:09:18 PM PDT 24 Jul 19 05:09:22 PM PDT 24 63497284 ps
T538 /workspace/coverage/default/29.rstmgr_stress_all.3008011044 Jul 19 05:08:41 PM PDT 24 Jul 19 05:09:00 PM PDT 24 3409557136 ps
T539 /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.50410812 Jul 19 05:08:39 PM PDT 24 Jul 19 05:08:51 PM PDT 24 2377726026 ps
T50 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2691051379 Jul 19 04:48:27 PM PDT 24 Jul 19 04:48:47 PM PDT 24 76401740 ps
T51 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1721512204 Jul 19 04:48:27 PM PDT 24 Jul 19 04:48:48 PM PDT 24 463784072 ps
T52 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1919198357 Jul 19 04:48:35 PM PDT 24 Jul 19 04:48:54 PM PDT 24 81412672 ps
T104 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2373665186 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 140985238 ps
T54 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1296132612 Jul 19 04:48:26 PM PDT 24 Jul 19 04:48:46 PM PDT 24 115524042 ps
T55 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.138930301 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 208697040 ps
T56 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.940285434 Jul 19 04:48:29 PM PDT 24 Jul 19 04:48:51 PM PDT 24 442370245 ps
T60 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3395749106 Jul 19 04:48:16 PM PDT 24 Jul 19 04:48:37 PM PDT 24 107077190 ps
T113 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3825606688 Jul 19 04:48:29 PM PDT 24 Jul 19 04:48:50 PM PDT 24 468573049 ps
T81 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3115271522 Jul 19 04:48:26 PM PDT 24 Jul 19 04:48:46 PM PDT 24 494650367 ps
T82 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.281626554 Jul 19 04:48:22 PM PDT 24 Jul 19 04:48:45 PM PDT 24 461208972 ps
T105 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4095842331 Jul 19 04:48:16 PM PDT 24 Jul 19 04:48:37 PM PDT 24 60203274 ps
T114 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2026032489 Jul 19 04:48:30 PM PDT 24 Jul 19 04:48:51 PM PDT 24 505371141 ps
T83 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3400298594 Jul 19 04:48:26 PM PDT 24 Jul 19 04:48:45 PM PDT 24 163866203 ps
T84 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2497513865 Jul 19 04:48:27 PM PDT 24 Jul 19 04:48:47 PM PDT 24 113781418 ps
T540 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3492257856 Jul 19 04:48:10 PM PDT 24 Jul 19 04:48:30 PM PDT 24 147907268 ps
T85 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.204495323 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 203821236 ps
T541 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3317697627 Jul 19 04:48:26 PM PDT 24 Jul 19 04:48:45 PM PDT 24 71564877 ps
T106 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2209473680 Jul 19 04:48:28 PM PDT 24 Jul 19 04:48:48 PM PDT 24 89648548 ps
T117 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2423746988 Jul 19 04:48:25 PM PDT 24 Jul 19 04:48:46 PM PDT 24 914631041 ps
T86 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1377161055 Jul 19 04:48:13 PM PDT 24 Jul 19 04:48:34 PM PDT 24 292954171 ps
T87 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4093817498 Jul 19 04:48:16 PM PDT 24 Jul 19 04:48:38 PM PDT 24 507453799 ps
T122 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.991178081 Jul 19 04:48:22 PM PDT 24 Jul 19 04:48:42 PM PDT 24 128606051 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3983484231 Jul 19 04:48:18 PM PDT 24 Jul 19 04:48:38 PM PDT 24 84980137 ps
T107 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2869720349 Jul 19 04:48:24 PM PDT 24 Jul 19 04:48:43 PM PDT 24 84782398 ps
T543 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1127339246 Jul 19 04:48:13 PM PDT 24 Jul 19 04:48:35 PM PDT 24 297577918 ps
T118 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.331335438 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:45 PM PDT 24 937290767 ps
T119 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.802559516 Jul 19 04:48:18 PM PDT 24 Jul 19 04:48:39 PM PDT 24 476362504 ps
T544 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.362211552 Jul 19 04:48:16 PM PDT 24 Jul 19 04:48:37 PM PDT 24 242123072 ps
T545 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1753265652 Jul 19 04:48:24 PM PDT 24 Jul 19 04:48:43 PM PDT 24 75694455 ps
T123 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.770613362 Jul 19 04:48:25 PM PDT 24 Jul 19 04:48:45 PM PDT 24 251949892 ps
T546 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3244843783 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 175191937 ps
T547 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1843831923 Jul 19 04:48:22 PM PDT 24 Jul 19 04:48:42 PM PDT 24 415829911 ps
T548 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2621584068 Jul 19 04:48:30 PM PDT 24 Jul 19 04:48:50 PM PDT 24 200485998 ps
T549 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1706548004 Jul 19 04:48:17 PM PDT 24 Jul 19 04:48:38 PM PDT 24 231368435 ps
T550 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1552779096 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:36 PM PDT 24 412958009 ps
T551 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3024673476 Jul 19 04:48:25 PM PDT 24 Jul 19 04:48:46 PM PDT 24 416111206 ps
T552 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3845036780 Jul 19 04:48:27 PM PDT 24 Jul 19 04:48:47 PM PDT 24 122526591 ps
T108 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2148865838 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 209789150 ps
T109 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3825498904 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 198987220 ps
T130 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2113966499 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 467251920 ps
T110 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1447708257 Jul 19 04:48:26 PM PDT 24 Jul 19 04:48:46 PM PDT 24 276324383 ps
T120 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4115429152 Jul 19 04:48:30 PM PDT 24 Jul 19 04:48:52 PM PDT 24 872584497 ps
T115 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1683753021 Jul 19 04:48:09 PM PDT 24 Jul 19 04:48:28 PM PDT 24 417527349 ps
T111 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.501304163 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:33 PM PDT 24 122447193 ps
T553 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.464412026 Jul 19 04:48:11 PM PDT 24 Jul 19 04:48:31 PM PDT 24 140077439 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.4011936023 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:34 PM PDT 24 184790014 ps
T555 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1989211282 Jul 19 04:48:19 PM PDT 24 Jul 19 04:48:39 PM PDT 24 102121886 ps
T112 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.768673790 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:33 PM PDT 24 74568528 ps
T556 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1795722592 Jul 19 04:48:20 PM PDT 24 Jul 19 04:48:40 PM PDT 24 185041496 ps
T557 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1513555017 Jul 19 04:48:34 PM PDT 24 Jul 19 04:48:53 PM PDT 24 76440487 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3902194398 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:42 PM PDT 24 1535998519 ps
T559 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1445230350 Jul 19 04:48:27 PM PDT 24 Jul 19 04:48:47 PM PDT 24 94323115 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3544816447 Jul 19 04:48:08 PM PDT 24 Jul 19 04:48:27 PM PDT 24 85984417 ps
T561 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3813500826 Jul 19 04:48:43 PM PDT 24 Jul 19 04:49:01 PM PDT 24 126414975 ps
T562 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3015583858 Jul 19 04:48:16 PM PDT 24 Jul 19 04:48:36 PM PDT 24 98278828 ps
T563 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2397464152 Jul 19 04:48:26 PM PDT 24 Jul 19 04:48:46 PM PDT 24 218482818 ps
T564 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.716152714 Jul 19 04:48:25 PM PDT 24 Jul 19 04:48:47 PM PDT 24 875487643 ps
T565 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2838191923 Jul 19 04:48:24 PM PDT 24 Jul 19 04:48:43 PM PDT 24 202079067 ps
T566 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1359261403 Jul 19 04:48:11 PM PDT 24 Jul 19 04:48:31 PM PDT 24 96697895 ps
T567 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4047619846 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:35 PM PDT 24 264874818 ps
T568 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1538079713 Jul 19 04:48:25 PM PDT 24 Jul 19 04:48:45 PM PDT 24 81815676 ps
T569 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3633040839 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:34 PM PDT 24 123328684 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1503748288 Jul 19 04:48:09 PM PDT 24 Jul 19 04:48:28 PM PDT 24 58858022 ps
T571 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2896566877 Jul 19 04:48:19 PM PDT 24 Jul 19 04:48:39 PM PDT 24 122333058 ps
T572 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1302254374 Jul 19 04:48:11 PM PDT 24 Jul 19 04:48:31 PM PDT 24 208817825 ps
T573 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1370143119 Jul 19 04:48:10 PM PDT 24 Jul 19 04:48:30 PM PDT 24 250365807 ps
T574 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1942596784 Jul 19 04:48:26 PM PDT 24 Jul 19 04:48:46 PM PDT 24 147987349 ps
T575 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3489532431 Jul 19 04:48:20 PM PDT 24 Jul 19 04:48:40 PM PDT 24 130397818 ps
T576 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.567231829 Jul 19 04:48:20 PM PDT 24 Jul 19 04:48:40 PM PDT 24 78037836 ps
T577 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1205290358 Jul 19 04:48:29 PM PDT 24 Jul 19 04:48:49 PM PDT 24 217027898 ps
T578 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.784732378 Jul 19 04:48:17 PM PDT 24 Jul 19 04:48:39 PM PDT 24 886335826 ps
T579 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3032576788 Jul 19 04:48:30 PM PDT 24 Jul 19 04:48:50 PM PDT 24 54026463 ps
T580 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1340874143 Jul 19 04:48:31 PM PDT 24 Jul 19 04:48:50 PM PDT 24 136985943 ps
T581 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3070471371 Jul 19 04:48:21 PM PDT 24 Jul 19 04:48:42 PM PDT 24 193497796 ps
T582 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4078142113 Jul 19 04:48:24 PM PDT 24 Jul 19 04:48:44 PM PDT 24 550667684 ps
T583 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3778322805 Jul 19 04:48:26 PM PDT 24 Jul 19 04:48:47 PM PDT 24 163872965 ps
T584 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2660950396 Jul 19 04:48:28 PM PDT 24 Jul 19 04:48:50 PM PDT 24 566193493 ps
T585 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1693776116 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 131320333 ps
T586 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3859019721 Jul 19 04:48:29 PM PDT 24 Jul 19 04:48:49 PM PDT 24 184288488 ps
T587 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2407436915 Jul 19 04:48:15 PM PDT 24 Jul 19 04:48:37 PM PDT 24 274233497 ps
T588 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4063671126 Jul 19 04:48:22 PM PDT 24 Jul 19 04:48:42 PM PDT 24 64035374 ps
T589 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.598379043 Jul 19 04:48:17 PM PDT 24 Jul 19 04:48:40 PM PDT 24 468774795 ps
T121 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.888239529 Jul 19 04:48:28 PM PDT 24 Jul 19 04:48:50 PM PDT 24 887333057 ps
T590 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2032615683 Jul 19 04:48:21 PM PDT 24 Jul 19 04:48:40 PM PDT 24 82041044 ps
T591 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.190770521 Jul 19 04:48:12 PM PDT 24 Jul 19 04:48:33 PM PDT 24 119915111 ps
T592 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1990000511 Jul 19 04:48:26 PM PDT 24 Jul 19 04:48:46 PM PDT 24 131106232 ps
T593 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1056613408 Jul 19 04:48:25 PM PDT 24 Jul 19 04:48:44 PM PDT 24 208274014 ps
T594 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2059625225 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 494902083 ps
T595 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1445502300 Jul 19 04:48:11 PM PDT 24 Jul 19 04:48:32 PM PDT 24 256708316 ps
T116 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3632521713 Jul 19 04:48:28 PM PDT 24 Jul 19 04:48:50 PM PDT 24 890827300 ps
T596 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3852533303 Jul 19 04:48:12 PM PDT 24 Jul 19 04:48:32 PM PDT 24 423535743 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2618426285 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:47 PM PDT 24 490818034 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1096870952 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:34 PM PDT 24 195248931 ps
T599 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.126239820 Jul 19 04:48:30 PM PDT 24 Jul 19 04:48:50 PM PDT 24 122288206 ps
T600 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3015651948 Jul 19 04:48:17 PM PDT 24 Jul 19 04:48:37 PM PDT 24 150739718 ps
T601 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.621787515 Jul 19 04:48:15 PM PDT 24 Jul 19 04:48:34 PM PDT 24 102368079 ps
T602 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2106200204 Jul 19 04:48:30 PM PDT 24 Jul 19 04:48:49 PM PDT 24 57203659 ps
T603 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4297435 Jul 19 04:48:32 PM PDT 24 Jul 19 04:48:51 PM PDT 24 196903015 ps
T604 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.923051191 Jul 19 04:48:16 PM PDT 24 Jul 19 04:48:36 PM PDT 24 59207923 ps
T605 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1238944789 Jul 19 04:48:20 PM PDT 24 Jul 19 04:48:40 PM PDT 24 147953826 ps
T606 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1564197089 Jul 19 04:48:16 PM PDT 24 Jul 19 04:48:37 PM PDT 24 95614650 ps
T607 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2461978489 Jul 19 04:48:10 PM PDT 24 Jul 19 04:48:29 PM PDT 24 110201009 ps
T608 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.130696180 Jul 19 04:48:28 PM PDT 24 Jul 19 04:48:49 PM PDT 24 152081965 ps
T609 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1886678865 Jul 19 04:48:26 PM PDT 24 Jul 19 04:48:45 PM PDT 24 187279145 ps
T610 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.4057558238 Jul 19 04:48:24 PM PDT 24 Jul 19 04:48:44 PM PDT 24 137080779 ps
T611 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.368366405 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 84694868 ps
T612 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.536878092 Jul 19 04:48:21 PM PDT 24 Jul 19 04:48:40 PM PDT 24 62582953 ps
T613 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.357744747 Jul 19 04:48:15 PM PDT 24 Jul 19 04:48:36 PM PDT 24 225238428 ps
T614 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4067311681 Jul 19 04:48:28 PM PDT 24 Jul 19 04:48:48 PM PDT 24 57781799 ps
T615 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1049431039 Jul 19 04:48:13 PM PDT 24 Jul 19 04:48:34 PM PDT 24 495153504 ps
T616 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1980835319 Jul 19 04:48:23 PM PDT 24 Jul 19 04:48:43 PM PDT 24 236571372 ps
T617 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1395444758 Jul 19 04:48:30 PM PDT 24 Jul 19 04:48:49 PM PDT 24 130079706 ps
T618 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1717283027 Jul 19 04:48:32 PM PDT 24 Jul 19 04:48:52 PM PDT 24 252273813 ps
T619 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.229569456 Jul 19 04:48:27 PM PDT 24 Jul 19 04:48:47 PM PDT 24 54617416 ps

Test location /workspace/coverage/default/31.rstmgr_reset.3277934969
Short name T6
Test name
Test status
Simulation time 1528951289 ps
CPU time 6.03 seconds
Started Jul 19 05:08:48 PM PDT 24
Finished Jul 19 05:08:57 PM PDT 24
Peak memory 200740 kb
Host smart-a4bf8197-b69c-43a3-854c-2886e1351108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277934969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3277934969
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3099777562
Short name T10
Test name
Test status
Simulation time 551905264 ps
CPU time 3.29 seconds
Started Jul 19 05:09:16 PM PDT 24
Finished Jul 19 05:09:23 PM PDT 24
Peak memory 200392 kb
Host smart-b3cd8286-753d-4ee2-b86a-0226e115259e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099777562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3099777562
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.887901277
Short name T26
Test name
Test status
Simulation time 1872504173 ps
CPU time 7.34 seconds
Started Jul 19 05:08:05 PM PDT 24
Finished Jul 19 05:08:13 PM PDT 24
Peak memory 221724 kb
Host smart-4cdbc11f-d253-4f48-bdda-f3804732936b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887901277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.887901277
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.138930301
Short name T55
Test name
Test status
Simulation time 208697040 ps
CPU time 1.31 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 208428 kb
Host smart-d769551e-d3cc-49e3-a21b-7061f477a754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138930301 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.138930301
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.734835790
Short name T37
Test name
Test status
Simulation time 16560583430 ps
CPU time 29.93 seconds
Started Jul 19 05:07:49 PM PDT 24
Finished Jul 19 05:08:22 PM PDT 24
Peak memory 217248 kb
Host smart-c66a2361-1f7a-42e5-ae4f-f5a52bd77f99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734835790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.734835790
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2423746988
Short name T117
Test name
Test status
Simulation time 914631041 ps
CPU time 3.01 seconds
Started Jul 19 04:48:25 PM PDT 24
Finished Jul 19 04:48:46 PM PDT 24
Peak memory 200348 kb
Host smart-42d040ca-5ba5-4758-82d8-2096142ac44a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423746988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2423746988
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.4195238455
Short name T76
Test name
Test status
Simulation time 7569266468 ps
CPU time 24.75 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:30 PM PDT 24
Peak memory 200852 kb
Host smart-542b5f8c-20b5-40f8-bdf4-889c87226d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195238455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.4195238455
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.281626554
Short name T82
Test name
Test status
Simulation time 461208972 ps
CPU time 3.38 seconds
Started Jul 19 04:48:22 PM PDT 24
Finished Jul 19 04:48:45 PM PDT 24
Peak memory 216632 kb
Host smart-4810c14f-a536-4191-9c0d-e5fe7ffb71e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281626554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.281626554
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1749481385
Short name T135
Test name
Test status
Simulation time 68194883 ps
CPU time 0.79 seconds
Started Jul 19 05:08:10 PM PDT 24
Finished Jul 19 05:08:15 PM PDT 24
Peak memory 200272 kb
Host smart-f238044b-3133-4d34-bc19-22275a384a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749481385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1749481385
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3847793779
Short name T25
Test name
Test status
Simulation time 1900174993 ps
CPU time 7.4 seconds
Started Jul 19 05:09:18 PM PDT 24
Finished Jul 19 05:09:29 PM PDT 24
Peak memory 217960 kb
Host smart-6f7710b0-e247-4bff-937c-28ca981f5be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847793779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3847793779
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.90058120
Short name T64
Test name
Test status
Simulation time 176499616 ps
CPU time 1.24 seconds
Started Jul 19 05:08:25 PM PDT 24
Finished Jul 19 05:08:29 PM PDT 24
Peak memory 200464 kb
Host smart-93688d4e-4b25-4470-a306-e4425c39f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90058120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.90058120
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.190169618
Short name T141
Test name
Test status
Simulation time 182739515 ps
CPU time 1.38 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:28 PM PDT 24
Peak memory 200656 kb
Host smart-49123422-7a2f-4837-bb7b-09aa5884a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190169618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.190169618
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3632521713
Short name T116
Test name
Test status
Simulation time 890827300 ps
CPU time 3.19 seconds
Started Jul 19 04:48:28 PM PDT 24
Finished Jul 19 04:48:50 PM PDT 24
Peak memory 200428 kb
Host smart-ef497a2c-aade-45d4-a5a8-fe58d1b24799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632521713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3632521713
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2828829389
Short name T32
Test name
Test status
Simulation time 2363846799 ps
CPU time 8.46 seconds
Started Jul 19 05:08:20 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 217820 kb
Host smart-a7be3d1b-92a2-4c99-86b1-6bce04cf04e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828829389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2828829389
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3778322805
Short name T583
Test name
Test status
Simulation time 163872965 ps
CPU time 2.5 seconds
Started Jul 19 04:48:26 PM PDT 24
Finished Jul 19 04:48:47 PM PDT 24
Peak memory 211848 kb
Host smart-e607d220-3f05-4838-8f99-56eeea0d005b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778322805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3778322805
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4095842331
Short name T105
Test name
Test status
Simulation time 60203274 ps
CPU time 0.73 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:37 PM PDT 24
Peak memory 200156 kb
Host smart-2c7d8a60-adae-470c-b2ae-e7204bf0fc39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095842331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.4095842331
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2248778030
Short name T2
Test name
Test status
Simulation time 171613060 ps
CPU time 0.83 seconds
Started Jul 19 05:08:15 PM PDT 24
Finished Jul 19 05:08:18 PM PDT 24
Peak memory 200268 kb
Host smart-c1cc1948-2542-4b44-8f06-83fe9c790a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248778030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2248778030
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2153034728
Short name T58
Test name
Test status
Simulation time 9817903959 ps
CPU time 15.69 seconds
Started Jul 19 05:07:47 PM PDT 24
Finished Jul 19 05:08:06 PM PDT 24
Peak memory 217152 kb
Host smart-328c7797-f13e-4789-b020-d10cc1a030d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153034728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2153034728
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.802559516
Short name T119
Test name
Test status
Simulation time 476362504 ps
CPU time 1.97 seconds
Started Jul 19 04:48:18 PM PDT 24
Finished Jul 19 04:48:39 PM PDT 24
Peak memory 200380 kb
Host smart-b7fb05e4-edda-4c53-8010-70925c9d1845
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802559516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
802559516
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.88377593
Short name T244
Test name
Test status
Simulation time 159524081 ps
CPU time 1.97 seconds
Started Jul 19 05:08:10 PM PDT 24
Finished Jul 19 05:08:16 PM PDT 24
Peak memory 200464 kb
Host smart-61aad2f2-5eb6-43c0-b259-4dca4439606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88377593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.88377593
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3492257856
Short name T540
Test name
Test status
Simulation time 147907268 ps
CPU time 1.97 seconds
Started Jul 19 04:48:10 PM PDT 24
Finished Jul 19 04:48:30 PM PDT 24
Peak memory 200416 kb
Host smart-734c0467-e5b5-495b-bb35-b50142eae02d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492257856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
492257856
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1127339246
Short name T543
Test name
Test status
Simulation time 297577918 ps
CPU time 3.24 seconds
Started Jul 19 04:48:13 PM PDT 24
Finished Jul 19 04:48:35 PM PDT 24
Peak memory 200264 kb
Host smart-581fdb60-94e7-423c-85e8-2af7ec62535a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127339246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
127339246
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3015583858
Short name T562
Test name
Test status
Simulation time 98278828 ps
CPU time 0.86 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:36 PM PDT 24
Peak memory 200212 kb
Host smart-27707143-7aaa-4a02-be73-2d454092148a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015583858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
015583858
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1096870952
Short name T598
Test name
Test status
Simulation time 195248931 ps
CPU time 1.27 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:34 PM PDT 24
Peak memory 200308 kb
Host smart-81178cf9-d494-4d29-a4ef-ae9b9bf331e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096870952 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1096870952
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.501304163
Short name T111
Test name
Test status
Simulation time 122447193 ps
CPU time 1.08 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:33 PM PDT 24
Peak memory 200244 kb
Host smart-da261142-b7c9-4cc1-8883-ddee1fc03c38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501304163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.501304163
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1445502300
Short name T595
Test name
Test status
Simulation time 256708316 ps
CPU time 1.94 seconds
Started Jul 19 04:48:11 PM PDT 24
Finished Jul 19 04:48:32 PM PDT 24
Peak memory 208492 kb
Host smart-5828ee5a-3897-4693-852f-98e5a2c74e04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445502300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1445502300
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3852533303
Short name T596
Test name
Test status
Simulation time 423535743 ps
CPU time 1.81 seconds
Started Jul 19 04:48:12 PM PDT 24
Finished Jul 19 04:48:32 PM PDT 24
Peak memory 200528 kb
Host smart-bae80ae7-fd0b-4318-a743-e6ee2a96c5c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852533303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3852533303
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.362211552
Short name T544
Test name
Test status
Simulation time 242123072 ps
CPU time 1.68 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:37 PM PDT 24
Peak memory 200560 kb
Host smart-6ed3e617-8dac-4036-97dd-ee9f2625e105
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362211552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.362211552
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4047619846
Short name T567
Test name
Test status
Simulation time 264874818 ps
CPU time 3.2 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:35 PM PDT 24
Peak memory 200384 kb
Host smart-e69a4c53-4118-4dec-8a7b-8116cf714637
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047619846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.4
047619846
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.621787515
Short name T601
Test name
Test status
Simulation time 102368079 ps
CPU time 0.84 seconds
Started Jul 19 04:48:15 PM PDT 24
Finished Jul 19 04:48:34 PM PDT 24
Peak memory 200216 kb
Host smart-85a24b57-d576-4793-868e-879dc9d04d83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621787515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.621787515
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3633040839
Short name T569
Test name
Test status
Simulation time 123328684 ps
CPU time 1.42 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:34 PM PDT 24
Peak memory 208620 kb
Host smart-1c3c5a13-e05a-4c39-91fc-473c2d96485e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633040839 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3633040839
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.768673790
Short name T112
Test name
Test status
Simulation time 74568528 ps
CPU time 0.84 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:33 PM PDT 24
Peak memory 200248 kb
Host smart-a15c72d5-7f94-48b2-8ddd-db8e68bddda6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768673790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.768673790
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.357744747
Short name T613
Test name
Test status
Simulation time 225238428 ps
CPU time 1.69 seconds
Started Jul 19 04:48:15 PM PDT 24
Finished Jul 19 04:48:36 PM PDT 24
Peak memory 200472 kb
Host smart-a0529d00-398c-4108-9e8b-11d0f64777ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357744747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.357744747
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.4011936023
Short name T554
Test name
Test status
Simulation time 184790014 ps
CPU time 1.59 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:34 PM PDT 24
Peak memory 208596 kb
Host smart-e76f93ff-51b0-4247-8578-ff1bf3ff1b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011936023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.4011936023
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3070471371
Short name T581
Test name
Test status
Simulation time 193497796 ps
CPU time 1.91 seconds
Started Jul 19 04:48:21 PM PDT 24
Finished Jul 19 04:48:42 PM PDT 24
Peak memory 208672 kb
Host smart-f033116e-526b-430f-884d-901d1f43c547
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070471371 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3070471371
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2691051379
Short name T50
Test name
Test status
Simulation time 76401740 ps
CPU time 0.85 seconds
Started Jul 19 04:48:27 PM PDT 24
Finished Jul 19 04:48:47 PM PDT 24
Peak memory 200260 kb
Host smart-a4c32f2e-d742-44bb-b47d-3aeb1ec5d020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691051379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2691051379
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1056613408
Short name T593
Test name
Test status
Simulation time 208274014 ps
CPU time 1.44 seconds
Started Jul 19 04:48:25 PM PDT 24
Finished Jul 19 04:48:44 PM PDT 24
Peak memory 200448 kb
Host smart-4a9f265e-156b-45a3-8841-8ea439cb798f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056613408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1056613408
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.991178081
Short name T122
Test name
Test status
Simulation time 128606051 ps
CPU time 1.72 seconds
Started Jul 19 04:48:22 PM PDT 24
Finished Jul 19 04:48:42 PM PDT 24
Peak memory 208588 kb
Host smart-47721453-3a7d-4c0b-8e25-e064e5a47332
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991178081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.991178081
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2059625225
Short name T594
Test name
Test status
Simulation time 494902083 ps
CPU time 1.88 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 200456 kb
Host smart-926ebf3b-1ee2-427d-bdb0-717997c43cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059625225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2059625225
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3845036780
Short name T552
Test name
Test status
Simulation time 122526591 ps
CPU time 0.98 seconds
Started Jul 19 04:48:27 PM PDT 24
Finished Jul 19 04:48:47 PM PDT 24
Peak memory 200316 kb
Host smart-ed0db293-979b-4a65-b846-0d7533ec4b2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845036780 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3845036780
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2209473680
Short name T106
Test name
Test status
Simulation time 89648548 ps
CPU time 0.87 seconds
Started Jul 19 04:48:28 PM PDT 24
Finished Jul 19 04:48:48 PM PDT 24
Peak memory 200148 kb
Host smart-f0d2a87d-cb8c-4a17-b0b9-d3cad9ea13e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209473680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2209473680
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1445230350
Short name T559
Test name
Test status
Simulation time 94323115 ps
CPU time 1.17 seconds
Started Jul 19 04:48:27 PM PDT 24
Finished Jul 19 04:48:47 PM PDT 24
Peak memory 200488 kb
Host smart-3d32ce74-7c5e-46a5-9341-2c5f029f0872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445230350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1445230350
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1942596784
Short name T574
Test name
Test status
Simulation time 147987349 ps
CPU time 2.2 seconds
Started Jul 19 04:48:26 PM PDT 24
Finished Jul 19 04:48:46 PM PDT 24
Peak memory 211720 kb
Host smart-8e8ccd4e-61cc-4021-b9c2-947d7a6067f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942596784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1942596784
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1843831923
Short name T547
Test name
Test status
Simulation time 415829911 ps
CPU time 1.78 seconds
Started Jul 19 04:48:22 PM PDT 24
Finished Jul 19 04:48:42 PM PDT 24
Peak memory 200456 kb
Host smart-00a3f3a2-9536-4309-a0cd-4a2543b44f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843831923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1843831923
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1693776116
Short name T585
Test name
Test status
Simulation time 131320333 ps
CPU time 1.57 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 208672 kb
Host smart-de8b9ff3-ae44-4334-ad70-270a706afdbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693776116 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1693776116
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.229569456
Short name T619
Test name
Test status
Simulation time 54617416 ps
CPU time 0.72 seconds
Started Jul 19 04:48:27 PM PDT 24
Finished Jul 19 04:48:47 PM PDT 24
Peak memory 200224 kb
Host smart-c5586281-d936-4f8e-bad9-7332ad9f8def
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229569456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.229569456
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1447708257
Short name T110
Test name
Test status
Simulation time 276324383 ps
CPU time 1.68 seconds
Started Jul 19 04:48:26 PM PDT 24
Finished Jul 19 04:48:46 PM PDT 24
Peak memory 200424 kb
Host smart-77819064-b60f-4130-be4f-ec863eebc39b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447708257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1447708257
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3024673476
Short name T551
Test name
Test status
Simulation time 416111206 ps
CPU time 2.52 seconds
Started Jul 19 04:48:25 PM PDT 24
Finished Jul 19 04:48:46 PM PDT 24
Peak memory 211580 kb
Host smart-bbe8ec41-7e53-4ce1-930e-2d55f1d5286d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024673476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3024673476
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.716152714
Short name T564
Test name
Test status
Simulation time 875487643 ps
CPU time 3.43 seconds
Started Jul 19 04:48:25 PM PDT 24
Finished Jul 19 04:48:47 PM PDT 24
Peak memory 200428 kb
Host smart-4478511d-cbe2-4b1d-ac96-92f15c4ee5d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716152714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.716152714
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3317697627
Short name T541
Test name
Test status
Simulation time 71564877 ps
CPU time 0.77 seconds
Started Jul 19 04:48:26 PM PDT 24
Finished Jul 19 04:48:45 PM PDT 24
Peak memory 200268 kb
Host smart-1cd42be0-02f8-4509-8c45-ac3a2ce29351
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317697627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3317697627
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1990000511
Short name T592
Test name
Test status
Simulation time 131106232 ps
CPU time 1.28 seconds
Started Jul 19 04:48:26 PM PDT 24
Finished Jul 19 04:48:46 PM PDT 24
Peak memory 200476 kb
Host smart-1df4067c-6a18-474b-a613-c9bf4fcd2c3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990000511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1990000511
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2497513865
Short name T84
Test name
Test status
Simulation time 113781418 ps
CPU time 1.45 seconds
Started Jul 19 04:48:27 PM PDT 24
Finished Jul 19 04:48:47 PM PDT 24
Peak memory 210988 kb
Host smart-676c853a-d3bb-4ac2-a443-59d2b4c3b159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497513865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2497513865
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2026032489
Short name T114
Test name
Test status
Simulation time 505371141 ps
CPU time 1.92 seconds
Started Jul 19 04:48:30 PM PDT 24
Finished Jul 19 04:48:51 PM PDT 24
Peak memory 200336 kb
Host smart-9cef0372-4692-413d-9649-36b86f85a4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026032489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2026032489
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2621584068
Short name T548
Test name
Test status
Simulation time 200485998 ps
CPU time 1.29 seconds
Started Jul 19 04:48:30 PM PDT 24
Finished Jul 19 04:48:50 PM PDT 24
Peak memory 208552 kb
Host smart-244f6eea-9c3b-4bcf-a54d-63d3e721600f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621584068 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2621584068
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4063671126
Short name T588
Test name
Test status
Simulation time 64035374 ps
CPU time 0.82 seconds
Started Jul 19 04:48:22 PM PDT 24
Finished Jul 19 04:48:42 PM PDT 24
Peak memory 200284 kb
Host smart-e62c0740-18ce-46dd-a553-76f895555937
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063671126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.4063671126
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2373665186
Short name T104
Test name
Test status
Simulation time 140985238 ps
CPU time 1.13 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 200352 kb
Host smart-8f12c602-df3a-4d97-a22b-04cd6deb55df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373665186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2373665186
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3115271522
Short name T81
Test name
Test status
Simulation time 494650367 ps
CPU time 1.86 seconds
Started Jul 19 04:48:26 PM PDT 24
Finished Jul 19 04:48:46 PM PDT 24
Peak memory 200476 kb
Host smart-6b2d5181-acca-48ba-9ead-f2e1bc702bec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115271522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3115271522
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2397464152
Short name T563
Test name
Test status
Simulation time 218482818 ps
CPU time 1.35 seconds
Started Jul 19 04:48:26 PM PDT 24
Finished Jul 19 04:48:46 PM PDT 24
Peak memory 208580 kb
Host smart-740ef523-5615-4235-b64b-00ea2b29b461
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397464152 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2397464152
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2869720349
Short name T107
Test name
Test status
Simulation time 84782398 ps
CPU time 0.87 seconds
Started Jul 19 04:48:24 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 200192 kb
Host smart-ce27c811-1a74-421f-8d08-1cb2b5b239de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869720349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2869720349
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3825498904
Short name T109
Test name
Test status
Simulation time 198987220 ps
CPU time 1.51 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 200492 kb
Host smart-27d25298-58be-4e69-abf2-3a7953976e9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825498904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3825498904
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1717283027
Short name T618
Test name
Test status
Simulation time 252273813 ps
CPU time 1.97 seconds
Started Jul 19 04:48:32 PM PDT 24
Finished Jul 19 04:48:52 PM PDT 24
Peak memory 208736 kb
Host smart-1ea00488-8da1-4bb4-8abd-6e3f0ee37d34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717283027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1717283027
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4115429152
Short name T120
Test name
Test status
Simulation time 872584497 ps
CPU time 2.99 seconds
Started Jul 19 04:48:30 PM PDT 24
Finished Jul 19 04:48:52 PM PDT 24
Peak memory 200508 kb
Host smart-7a83fb7b-cf6d-438a-9acb-4ef0260787f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115429152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.4115429152
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.126239820
Short name T599
Test name
Test status
Simulation time 122288206 ps
CPU time 1.1 seconds
Started Jul 19 04:48:30 PM PDT 24
Finished Jul 19 04:48:50 PM PDT 24
Peak memory 200268 kb
Host smart-feb1b5ac-6761-4778-b952-25312b3f5afa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126239820 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.126239820
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1513555017
Short name T557
Test name
Test status
Simulation time 76440487 ps
CPU time 0.82 seconds
Started Jul 19 04:48:34 PM PDT 24
Finished Jul 19 04:48:53 PM PDT 24
Peak memory 200248 kb
Host smart-222c1cc1-7b03-4192-8df3-514e3b6b88e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513555017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1513555017
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3489532431
Short name T575
Test name
Test status
Simulation time 130397818 ps
CPU time 1.39 seconds
Started Jul 19 04:48:20 PM PDT 24
Finished Jul 19 04:48:40 PM PDT 24
Peak memory 200476 kb
Host smart-601f5310-b0a3-4ceb-9271-b6d366694f23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489532431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3489532431
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.204495323
Short name T85
Test name
Test status
Simulation time 203821236 ps
CPU time 1.32 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 208560 kb
Host smart-37f760a9-cae9-4a9a-aed1-580fd09f50eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204495323 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.204495323
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1538079713
Short name T568
Test name
Test status
Simulation time 81815676 ps
CPU time 0.85 seconds
Started Jul 19 04:48:25 PM PDT 24
Finished Jul 19 04:48:45 PM PDT 24
Peak memory 200088 kb
Host smart-c6266584-15da-4d17-a4fc-060434a438b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538079713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1538079713
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1238944789
Short name T605
Test name
Test status
Simulation time 147953826 ps
CPU time 1.23 seconds
Started Jul 19 04:48:20 PM PDT 24
Finished Jul 19 04:48:40 PM PDT 24
Peak memory 200244 kb
Host smart-5e5f7f46-8a64-4328-a6eb-7152324d45af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238944789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1238944789
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2660950396
Short name T584
Test name
Test status
Simulation time 566193493 ps
CPU time 3.57 seconds
Started Jul 19 04:48:28 PM PDT 24
Finished Jul 19 04:48:50 PM PDT 24
Peak memory 208532 kb
Host smart-987df071-9fef-469b-90bb-969c9c61186c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660950396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2660950396
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3813500826
Short name T561
Test name
Test status
Simulation time 126414975 ps
CPU time 1.04 seconds
Started Jul 19 04:48:43 PM PDT 24
Finished Jul 19 04:49:01 PM PDT 24
Peak memory 200352 kb
Host smart-92cca754-2bd3-4fca-bde6-6fbd749c81fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813500826 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3813500826
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1919198357
Short name T52
Test name
Test status
Simulation time 81412672 ps
CPU time 0.88 seconds
Started Jul 19 04:48:35 PM PDT 24
Finished Jul 19 04:48:54 PM PDT 24
Peak memory 200112 kb
Host smart-55f735ac-9885-4358-b84c-655040f4cb49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919198357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1919198357
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1340874143
Short name T580
Test name
Test status
Simulation time 136985943 ps
CPU time 1.4 seconds
Started Jul 19 04:48:31 PM PDT 24
Finished Jul 19 04:48:50 PM PDT 24
Peak memory 200488 kb
Host smart-54afe09a-50c7-405b-a33f-6a89095e7cfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340874143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1340874143
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.770613362
Short name T123
Test name
Test status
Simulation time 251949892 ps
CPU time 1.9 seconds
Started Jul 19 04:48:25 PM PDT 24
Finished Jul 19 04:48:45 PM PDT 24
Peak memory 208660 kb
Host smart-1eb6e9d3-5982-4c85-bc6c-ed66cd5f1420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770613362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.770613362
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3825606688
Short name T113
Test name
Test status
Simulation time 468573049 ps
CPU time 1.91 seconds
Started Jul 19 04:48:29 PM PDT 24
Finished Jul 19 04:48:50 PM PDT 24
Peak memory 200620 kb
Host smart-e45e16c1-cc71-48b4-a0ca-4cc2ebcea910
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825606688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3825606688
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3859019721
Short name T586
Test name
Test status
Simulation time 184288488 ps
CPU time 1.2 seconds
Started Jul 19 04:48:29 PM PDT 24
Finished Jul 19 04:48:49 PM PDT 24
Peak memory 208504 kb
Host smart-0f57a7c3-7de1-46c4-8912-f00b7b46b7c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859019721 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3859019721
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3032576788
Short name T579
Test name
Test status
Simulation time 54026463 ps
CPU time 0.78 seconds
Started Jul 19 04:48:30 PM PDT 24
Finished Jul 19 04:48:50 PM PDT 24
Peak memory 200260 kb
Host smart-6cd4d108-e074-4b1d-bfcf-35e3827fcb6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032576788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3032576788
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1205290358
Short name T577
Test name
Test status
Simulation time 217027898 ps
CPU time 1.49 seconds
Started Jul 19 04:48:29 PM PDT 24
Finished Jul 19 04:48:49 PM PDT 24
Peak memory 200496 kb
Host smart-c781e572-974d-4986-a303-7f23f1008eb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205290358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1205290358
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.130696180
Short name T608
Test name
Test status
Simulation time 152081965 ps
CPU time 2.03 seconds
Started Jul 19 04:48:28 PM PDT 24
Finished Jul 19 04:48:49 PM PDT 24
Peak memory 208512 kb
Host smart-e81d30c6-3db9-40e7-b49f-6e8e0896741b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130696180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.130696180
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.888239529
Short name T121
Test name
Test status
Simulation time 887333057 ps
CPU time 2.9 seconds
Started Jul 19 04:48:28 PM PDT 24
Finished Jul 19 04:48:50 PM PDT 24
Peak memory 200524 kb
Host smart-3e84f954-587d-40ff-841b-3456875b0dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888239529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.888239529
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2461978489
Short name T607
Test name
Test status
Simulation time 110201009 ps
CPU time 1.33 seconds
Started Jul 19 04:48:10 PM PDT 24
Finished Jul 19 04:48:29 PM PDT 24
Peak memory 200252 kb
Host smart-1978b493-15f8-415a-b69d-587d66b2aa6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461978489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
461978489
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3902194398
Short name T558
Test name
Test status
Simulation time 1535998519 ps
CPU time 9.1 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:42 PM PDT 24
Peak memory 200396 kb
Host smart-cbbc749e-33f9-4818-85db-5553105b6662
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902194398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
902194398
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3983484231
Short name T542
Test name
Test status
Simulation time 84980137 ps
CPU time 0.84 seconds
Started Jul 19 04:48:18 PM PDT 24
Finished Jul 19 04:48:38 PM PDT 24
Peak memory 200208 kb
Host smart-ddb1c88e-ef06-490f-a10d-472ebc0e6424
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983484231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
983484231
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3395749106
Short name T60
Test name
Test status
Simulation time 107077190 ps
CPU time 1 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:37 PM PDT 24
Peak memory 208872 kb
Host smart-b9662465-25de-4775-8861-fab6d6a590d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395749106 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3395749106
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.536878092
Short name T612
Test name
Test status
Simulation time 62582953 ps
CPU time 0.77 seconds
Started Jul 19 04:48:21 PM PDT 24
Finished Jul 19 04:48:40 PM PDT 24
Peak memory 200176 kb
Host smart-071726ca-ab6b-443f-be70-2b927dc12334
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536878092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.536878092
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3544816447
Short name T560
Test name
Test status
Simulation time 85984417 ps
CPU time 1.06 seconds
Started Jul 19 04:48:08 PM PDT 24
Finished Jul 19 04:48:27 PM PDT 24
Peak memory 200204 kb
Host smart-64a05b0c-92e7-47b2-b0f0-495d9a24ebf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544816447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3544816447
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1552779096
Short name T550
Test name
Test status
Simulation time 412958009 ps
CPU time 3.06 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:36 PM PDT 24
Peak memory 208464 kb
Host smart-34e08fa4-f646-431d-9a5e-65f7a4a396b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552779096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1552779096
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1683753021
Short name T115
Test name
Test status
Simulation time 417527349 ps
CPU time 1.87 seconds
Started Jul 19 04:48:09 PM PDT 24
Finished Jul 19 04:48:28 PM PDT 24
Peak memory 200400 kb
Host smart-76b2fe5d-33de-415e-89f3-f5d776614f83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683753021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1683753021
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1706548004
Short name T549
Test name
Test status
Simulation time 231368435 ps
CPU time 1.65 seconds
Started Jul 19 04:48:17 PM PDT 24
Finished Jul 19 04:48:38 PM PDT 24
Peak memory 200288 kb
Host smart-0e98ef26-132f-45b1-8132-167d2aed0d2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706548004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
706548004
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2618426285
Short name T597
Test name
Test status
Simulation time 490818034 ps
CPU time 5.78 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:47 PM PDT 24
Peak memory 216728 kb
Host smart-58a17e2d-e39b-4538-b706-02fffb659512
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618426285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
618426285
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1989211282
Short name T555
Test name
Test status
Simulation time 102121886 ps
CPU time 0.82 seconds
Started Jul 19 04:48:19 PM PDT 24
Finished Jul 19 04:48:39 PM PDT 24
Peak memory 200112 kb
Host smart-2376522d-f878-4fb2-accd-f8289123f493
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989211282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
989211282
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1795722592
Short name T556
Test name
Test status
Simulation time 185041496 ps
CPU time 1.28 seconds
Started Jul 19 04:48:20 PM PDT 24
Finished Jul 19 04:48:40 PM PDT 24
Peak memory 200400 kb
Host smart-b8f3d6b9-80c1-4a10-a30f-1b6d287b4e4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795722592 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1795722592
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1503748288
Short name T570
Test name
Test status
Simulation time 58858022 ps
CPU time 0.84 seconds
Started Jul 19 04:48:09 PM PDT 24
Finished Jul 19 04:48:28 PM PDT 24
Peak memory 200284 kb
Host smart-160ffbcb-0e90-456f-b420-b79958d006b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503748288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1503748288
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1564197089
Short name T606
Test name
Test status
Simulation time 95614650 ps
CPU time 1.16 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:37 PM PDT 24
Peak memory 200448 kb
Host smart-89d80ab4-32b5-42ac-977d-d8e95dc34afb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564197089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1564197089
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1377161055
Short name T86
Test name
Test status
Simulation time 292954171 ps
CPU time 2.36 seconds
Started Jul 19 04:48:13 PM PDT 24
Finished Jul 19 04:48:34 PM PDT 24
Peak memory 208584 kb
Host smart-68f618f1-caca-47dd-a9f1-f574249f7560
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377161055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1377161055
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1049431039
Short name T615
Test name
Test status
Simulation time 495153504 ps
CPU time 2.14 seconds
Started Jul 19 04:48:13 PM PDT 24
Finished Jul 19 04:48:34 PM PDT 24
Peak memory 200272 kb
Host smart-2d856c5b-7cee-4b53-84c3-c57f1eaa19d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049431039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1049431039
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1302254374
Short name T572
Test name
Test status
Simulation time 208817825 ps
CPU time 1.52 seconds
Started Jul 19 04:48:11 PM PDT 24
Finished Jul 19 04:48:31 PM PDT 24
Peak memory 200416 kb
Host smart-cb26fe48-2dfc-4494-acd4-6ad0e5129933
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302254374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
302254374
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2407436915
Short name T587
Test name
Test status
Simulation time 274233497 ps
CPU time 3.01 seconds
Started Jul 19 04:48:15 PM PDT 24
Finished Jul 19 04:48:37 PM PDT 24
Peak memory 200168 kb
Host smart-5cabf67c-5e86-44fb-b3d8-f7f97f34f519
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407436915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
407436915
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3015651948
Short name T600
Test name
Test status
Simulation time 150739718 ps
CPU time 0.96 seconds
Started Jul 19 04:48:17 PM PDT 24
Finished Jul 19 04:48:37 PM PDT 24
Peak memory 200028 kb
Host smart-94546c96-8f86-4ed5-9cf7-6de31b40f652
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015651948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
015651948
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2896566877
Short name T571
Test name
Test status
Simulation time 122333058 ps
CPU time 1.2 seconds
Started Jul 19 04:48:19 PM PDT 24
Finished Jul 19 04:48:39 PM PDT 24
Peak memory 208500 kb
Host smart-bd7d312a-8cfa-42f0-8c53-b1b1782e4a9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896566877 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2896566877
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.923051191
Short name T604
Test name
Test status
Simulation time 59207923 ps
CPU time 0.74 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:36 PM PDT 24
Peak memory 200232 kb
Host smart-b1d5892b-d3ae-4b20-9b89-e313c1d9cb9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923051191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.923051191
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1359261403
Short name T566
Test name
Test status
Simulation time 96697895 ps
CPU time 1.18 seconds
Started Jul 19 04:48:11 PM PDT 24
Finished Jul 19 04:48:31 PM PDT 24
Peak memory 200480 kb
Host smart-93f2d47d-94e7-449e-b1f2-0650b11e8799
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359261403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1359261403
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.598379043
Short name T589
Test name
Test status
Simulation time 468774795 ps
CPU time 3.42 seconds
Started Jul 19 04:48:17 PM PDT 24
Finished Jul 19 04:48:40 PM PDT 24
Peak memory 208400 kb
Host smart-ae5fe730-812a-417f-9b60-b8dbe926aaa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598379043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.598379043
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4093817498
Short name T87
Test name
Test status
Simulation time 507453799 ps
CPU time 2.15 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:38 PM PDT 24
Peak memory 200432 kb
Host smart-b8aa5f85-8092-448d-8e61-f72856c58d91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093817498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.4093817498
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.464412026
Short name T553
Test name
Test status
Simulation time 140077439 ps
CPU time 1.11 seconds
Started Jul 19 04:48:11 PM PDT 24
Finished Jul 19 04:48:31 PM PDT 24
Peak memory 208616 kb
Host smart-4de2ba98-0e68-4f78-aa1a-0d85953e4ebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464412026 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.464412026
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.567231829
Short name T576
Test name
Test status
Simulation time 78037836 ps
CPU time 0.87 seconds
Started Jul 19 04:48:20 PM PDT 24
Finished Jul 19 04:48:40 PM PDT 24
Peak memory 200264 kb
Host smart-7cd6616d-23d2-4633-8800-7b3e40a7d8af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567231829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.567231829
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1370143119
Short name T573
Test name
Test status
Simulation time 250365807 ps
CPU time 1.55 seconds
Started Jul 19 04:48:10 PM PDT 24
Finished Jul 19 04:48:30 PM PDT 24
Peak memory 200456 kb
Host smart-bcc301bb-b6f3-444b-a146-e74c8e009558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370143119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1370143119
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.4057558238
Short name T610
Test name
Test status
Simulation time 137080779 ps
CPU time 1.81 seconds
Started Jul 19 04:48:24 PM PDT 24
Finished Jul 19 04:48:44 PM PDT 24
Peak memory 208392 kb
Host smart-14bc5fd7-e780-4f09-891a-863f09d98c52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057558238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.4057558238
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.784732378
Short name T578
Test name
Test status
Simulation time 886335826 ps
CPU time 3.05 seconds
Started Jul 19 04:48:17 PM PDT 24
Finished Jul 19 04:48:39 PM PDT 24
Peak memory 200288 kb
Host smart-9902d2f8-ce5f-4264-b120-b5e6d4562801
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784732378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
784732378
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3244843783
Short name T546
Test name
Test status
Simulation time 175191937 ps
CPU time 1.49 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 208772 kb
Host smart-24c316b1-d893-4db5-a4ca-54bfbbb8faec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244843783 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3244843783
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2106200204
Short name T602
Test name
Test status
Simulation time 57203659 ps
CPU time 0.75 seconds
Started Jul 19 04:48:30 PM PDT 24
Finished Jul 19 04:48:49 PM PDT 24
Peak memory 200100 kb
Host smart-ac01e063-4057-49db-8571-d330366275eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106200204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2106200204
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2148865838
Short name T108
Test name
Test status
Simulation time 209789150 ps
CPU time 1.61 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 200364 kb
Host smart-f305d40d-a496-47bd-815e-edeccacae041
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148865838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2148865838
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.190770521
Short name T591
Test name
Test status
Simulation time 119915111 ps
CPU time 1.61 seconds
Started Jul 19 04:48:12 PM PDT 24
Finished Jul 19 04:48:33 PM PDT 24
Peak memory 208652 kb
Host smart-b2fd1dae-52b5-4752-83ca-9a35447f997c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190770521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.190770521
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4078142113
Short name T582
Test name
Test status
Simulation time 550667684 ps
CPU time 1.99 seconds
Started Jul 19 04:48:24 PM PDT 24
Finished Jul 19 04:48:44 PM PDT 24
Peak memory 200440 kb
Host smart-ff050e50-e70e-4012-816d-355dc3a228af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078142113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.4078142113
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3400298594
Short name T83
Test name
Test status
Simulation time 163866203 ps
CPU time 1.44 seconds
Started Jul 19 04:48:26 PM PDT 24
Finished Jul 19 04:48:45 PM PDT 24
Peak memory 208712 kb
Host smart-4411754f-9f41-468e-b768-e83c8d9f1a3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400298594 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3400298594
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2032615683
Short name T590
Test name
Test status
Simulation time 82041044 ps
CPU time 0.94 seconds
Started Jul 19 04:48:21 PM PDT 24
Finished Jul 19 04:48:40 PM PDT 24
Peak memory 200284 kb
Host smart-37f9b5f6-890a-49e1-902c-d46965134e4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032615683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2032615683
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1980835319
Short name T616
Test name
Test status
Simulation time 236571372 ps
CPU time 1.61 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 200368 kb
Host smart-85724161-078f-47ec-85e2-c61c2c236997
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980835319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1980835319
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1296132612
Short name T54
Test name
Test status
Simulation time 115524042 ps
CPU time 1.6 seconds
Started Jul 19 04:48:26 PM PDT 24
Finished Jul 19 04:48:46 PM PDT 24
Peak memory 216736 kb
Host smart-62656d33-a9b2-47d1-818a-7d6f37c64964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296132612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1296132612
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2113966499
Short name T130
Test name
Test status
Simulation time 467251920 ps
CPU time 1.8 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 200556 kb
Host smart-e623a71e-7145-40a5-8963-ebd7df641c17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113966499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2113966499
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1886678865
Short name T609
Test name
Test status
Simulation time 187279145 ps
CPU time 1.26 seconds
Started Jul 19 04:48:26 PM PDT 24
Finished Jul 19 04:48:45 PM PDT 24
Peak memory 200384 kb
Host smart-b2ab2281-30b0-4042-9d5a-c687776bcf54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886678865 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1886678865
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4067311681
Short name T614
Test name
Test status
Simulation time 57781799 ps
CPU time 0.75 seconds
Started Jul 19 04:48:28 PM PDT 24
Finished Jul 19 04:48:48 PM PDT 24
Peak memory 200284 kb
Host smart-e6c05c92-7240-47af-ad18-a1bca17d30cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067311681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4067311681
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.368366405
Short name T611
Test name
Test status
Simulation time 84694868 ps
CPU time 0.95 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 200328 kb
Host smart-658929fb-eb67-40d0-b2b2-6798b3f293d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368366405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.368366405
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.940285434
Short name T56
Test name
Test status
Simulation time 442370245 ps
CPU time 2.75 seconds
Started Jul 19 04:48:29 PM PDT 24
Finished Jul 19 04:48:51 PM PDT 24
Peak memory 208528 kb
Host smart-885d3d5b-36ed-462b-babd-44eacefb40c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940285434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.940285434
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1721512204
Short name T51
Test name
Test status
Simulation time 463784072 ps
CPU time 1.72 seconds
Started Jul 19 04:48:27 PM PDT 24
Finished Jul 19 04:48:48 PM PDT 24
Peak memory 200448 kb
Host smart-1ae51f04-6c89-462e-8eee-8b22e9d1ab84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721512204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1721512204
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4297435
Short name T603
Test name
Test status
Simulation time 196903015 ps
CPU time 1.27 seconds
Started Jul 19 04:48:32 PM PDT 24
Finished Jul 19 04:48:51 PM PDT 24
Peak memory 200340 kb
Host smart-46b5f269-4724-4fae-9948-b04109b4c02d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4297435 -assert nopostproc +UVM_TESTNAME=rs
tmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.4297435
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1753265652
Short name T545
Test name
Test status
Simulation time 75694455 ps
CPU time 0.85 seconds
Started Jul 19 04:48:24 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 200240 kb
Host smart-03c56556-c427-43dd-9961-0fd36523a383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753265652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1753265652
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1395444758
Short name T617
Test name
Test status
Simulation time 130079706 ps
CPU time 1.26 seconds
Started Jul 19 04:48:30 PM PDT 24
Finished Jul 19 04:48:49 PM PDT 24
Peak memory 200392 kb
Host smart-4448f80d-22ab-4700-a344-b1e02b4315f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395444758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1395444758
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2838191923
Short name T565
Test name
Test status
Simulation time 202079067 ps
CPU time 1.45 seconds
Started Jul 19 04:48:24 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 200236 kb
Host smart-cfdaa245-b062-4c32-a7e9-b1940e65d8c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838191923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2838191923
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.331335438
Short name T118
Test name
Test status
Simulation time 937290767 ps
CPU time 3.08 seconds
Started Jul 19 04:48:23 PM PDT 24
Finished Jul 19 04:48:45 PM PDT 24
Peak memory 200412 kb
Host smart-a30f444e-a92e-4b0e-ac7d-d0768b1c8b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331335438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
331335438
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2890955113
Short name T156
Test name
Test status
Simulation time 55146479 ps
CPU time 0.72 seconds
Started Jul 19 05:07:47 PM PDT 24
Finished Jul 19 05:07:50 PM PDT 24
Peak memory 200284 kb
Host smart-bd37011a-9cc9-4eaf-9fd8-eb64cbe2ca60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890955113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2890955113
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.908746970
Short name T394
Test name
Test status
Simulation time 2187831458 ps
CPU time 8.11 seconds
Started Jul 19 05:07:49 PM PDT 24
Finished Jul 19 05:07:59 PM PDT 24
Peak memory 217868 kb
Host smart-a72da90a-62e3-4d29-8a3d-0d6e6858d8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908746970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.908746970
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2501068616
Short name T454
Test name
Test status
Simulation time 244733142 ps
CPU time 1.15 seconds
Started Jul 19 05:07:44 PM PDT 24
Finished Jul 19 05:07:48 PM PDT 24
Peak memory 217440 kb
Host smart-4af59c61-0420-426f-bffe-31ddd269d7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501068616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2501068616
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2247193627
Short name T298
Test name
Test status
Simulation time 156116087 ps
CPU time 0.92 seconds
Started Jul 19 05:07:43 PM PDT 24
Finished Jul 19 05:07:47 PM PDT 24
Peak memory 200256 kb
Host smart-381670f9-8224-4b74-a56d-535b56b04610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247193627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2247193627
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2361975509
Short name T268
Test name
Test status
Simulation time 1257248112 ps
CPU time 5 seconds
Started Jul 19 05:07:48 PM PDT 24
Finished Jul 19 05:07:56 PM PDT 24
Peak memory 200724 kb
Host smart-79769a3e-9243-4701-99fe-8d562c762899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361975509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2361975509
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2240255151
Short name T206
Test name
Test status
Simulation time 97237989 ps
CPU time 1.05 seconds
Started Jul 19 05:07:43 PM PDT 24
Finished Jul 19 05:07:48 PM PDT 24
Peak memory 200272 kb
Host smart-f2516620-39ef-4ba5-aace-077cdfac5e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240255151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2240255151
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3873925150
Short name T417
Test name
Test status
Simulation time 117109611 ps
CPU time 1.27 seconds
Started Jul 19 05:07:41 PM PDT 24
Finished Jul 19 05:07:45 PM PDT 24
Peak memory 200568 kb
Host smart-23ce09d9-1a73-4af3-b7bb-725bfa91c547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873925150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3873925150
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2563646495
Short name T533
Test name
Test status
Simulation time 19440812056 ps
CPU time 65.83 seconds
Started Jul 19 05:07:48 PM PDT 24
Finished Jul 19 05:08:56 PM PDT 24
Peak memory 208980 kb
Host smart-8960cc61-8ccc-4b0a-ab4b-105c33dee1d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563646495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2563646495
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.311873810
Short name T128
Test name
Test status
Simulation time 330453886 ps
CPU time 2.18 seconds
Started Jul 19 05:07:46 PM PDT 24
Finished Jul 19 05:07:51 PM PDT 24
Peak memory 200480 kb
Host smart-89a63bee-e9d4-4295-b6b5-18470f7b329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311873810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.311873810
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3562291537
Short name T322
Test name
Test status
Simulation time 114247597 ps
CPU time 1.02 seconds
Started Jul 19 05:07:45 PM PDT 24
Finished Jul 19 05:07:50 PM PDT 24
Peak memory 200464 kb
Host smart-cb135a9e-6b31-4dca-a904-66f428e64cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562291537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3562291537
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1842356608
Short name T373
Test name
Test status
Simulation time 81487497 ps
CPU time 0.83 seconds
Started Jul 19 05:07:49 PM PDT 24
Finished Jul 19 05:07:53 PM PDT 24
Peak memory 200272 kb
Host smart-6944e6d3-01e3-4661-92f3-44cf28031139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842356608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1842356608
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3577722927
Short name T42
Test name
Test status
Simulation time 2362415312 ps
CPU time 8.01 seconds
Started Jul 19 05:07:54 PM PDT 24
Finished Jul 19 05:08:04 PM PDT 24
Peak memory 217328 kb
Host smart-77a75b4a-7153-430c-a750-145625d6c5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577722927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3577722927
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2448245569
Short name T208
Test name
Test status
Simulation time 244107766 ps
CPU time 1.16 seconds
Started Jul 19 05:07:52 PM PDT 24
Finished Jul 19 05:07:56 PM PDT 24
Peak memory 217500 kb
Host smart-e421d90a-8982-4654-82d4-a12f236ff9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448245569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2448245569
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2919036495
Short name T387
Test name
Test status
Simulation time 187620867 ps
CPU time 0.93 seconds
Started Jul 19 05:07:50 PM PDT 24
Finished Jul 19 05:07:54 PM PDT 24
Peak memory 200156 kb
Host smart-a65ced02-bb3e-4327-b288-39e5fc888a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919036495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2919036495
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2825829735
Short name T162
Test name
Test status
Simulation time 1613660139 ps
CPU time 6.69 seconds
Started Jul 19 05:07:52 PM PDT 24
Finished Jul 19 05:08:01 PM PDT 24
Peak memory 200724 kb
Host smart-2bd59836-3a88-4c8f-96be-25fc6822483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825829735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2825829735
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.638520503
Short name T186
Test name
Test status
Simulation time 140398859 ps
CPU time 1.3 seconds
Started Jul 19 05:07:53 PM PDT 24
Finished Jul 19 05:07:57 PM PDT 24
Peak memory 200460 kb
Host smart-103bb971-e9df-41f7-bea0-03c31708819a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638520503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.638520503
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3898670208
Short name T459
Test name
Test status
Simulation time 188489315 ps
CPU time 1.42 seconds
Started Jul 19 05:07:54 PM PDT 24
Finished Jul 19 05:07:57 PM PDT 24
Peak memory 200672 kb
Host smart-b9b46c85-6fec-468d-b59b-73fac364f5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898670208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3898670208
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1371141351
Short name T210
Test name
Test status
Simulation time 7931715052 ps
CPU time 31.5 seconds
Started Jul 19 05:07:50 PM PDT 24
Finished Jul 19 05:08:24 PM PDT 24
Peak memory 200788 kb
Host smart-23fbf3d6-c137-4249-8a59-ce5a0d850f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371141351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1371141351
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1253677607
Short name T70
Test name
Test status
Simulation time 345082365 ps
CPU time 2.35 seconds
Started Jul 19 05:07:49 PM PDT 24
Finished Jul 19 05:07:54 PM PDT 24
Peak memory 200448 kb
Host smart-de8f4759-adda-464a-bb54-ef94ba5d0ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253677607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1253677607
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1617264088
Short name T368
Test name
Test status
Simulation time 289858052 ps
CPU time 1.52 seconds
Started Jul 19 05:07:51 PM PDT 24
Finished Jul 19 05:07:55 PM PDT 24
Peak memory 200656 kb
Host smart-6ab1cc52-0f8e-4f7a-bdc2-12c4038e18af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617264088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1617264088
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1778789724
Short name T46
Test name
Test status
Simulation time 1225631942 ps
CPU time 5.89 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:17 PM PDT 24
Peak memory 217456 kb
Host smart-a063917a-6129-46e1-904c-1ef1d5cf0c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778789724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1778789724
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.355563982
Short name T397
Test name
Test status
Simulation time 244576624 ps
CPU time 1.03 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:14 PM PDT 24
Peak memory 217424 kb
Host smart-b53ffb36-9068-4288-a245-67e13ae3a4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355563982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.355563982
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2115143296
Short name T310
Test name
Test status
Simulation time 124247055 ps
CPU time 0.83 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:11 PM PDT 24
Peak memory 200276 kb
Host smart-0d9448b7-f343-40f4-ac08-5867d20bd2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115143296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2115143296
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3227041394
Short name T98
Test name
Test status
Simulation time 823284678 ps
CPU time 4.26 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:15 PM PDT 24
Peak memory 200696 kb
Host smart-0798bb3e-d27e-40f3-a884-f1fb94bbe985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227041394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3227041394
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3583264832
Short name T381
Test name
Test status
Simulation time 146958139 ps
CPU time 1.15 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:14 PM PDT 24
Peak memory 200628 kb
Host smart-33a3fa7b-c931-490e-866c-7a9fdfd6299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583264832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3583264832
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2659386273
Short name T53
Test name
Test status
Simulation time 259111697 ps
CPU time 1.51 seconds
Started Jul 19 05:08:16 PM PDT 24
Finished Jul 19 05:08:21 PM PDT 24
Peak memory 200660 kb
Host smart-2733e0ec-a2a2-4334-ab9b-87adb9fd56df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659386273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2659386273
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3236760533
Short name T333
Test name
Test status
Simulation time 9854892546 ps
CPU time 39.19 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:51 PM PDT 24
Peak memory 209068 kb
Host smart-ad02e629-23fa-458c-818f-5efdb6ee0d1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236760533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3236760533
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.130564867
Short name T67
Test name
Test status
Simulation time 105525004 ps
CPU time 0.89 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:13 PM PDT 24
Peak memory 200448 kb
Host smart-1b065981-6f8c-4440-8ae9-75fae52f8426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130564867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.130564867
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2914126683
Short name T313
Test name
Test status
Simulation time 70413312 ps
CPU time 0.81 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:21 PM PDT 24
Peak memory 200260 kb
Host smart-577106ed-7319-4ec1-a4e1-a0b5c2c7c38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914126683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2914126683
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.622327468
Short name T30
Test name
Test status
Simulation time 1893995076 ps
CPU time 7.11 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:17 PM PDT 24
Peak memory 217008 kb
Host smart-80304de5-a374-473d-886c-7cb84822cb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622327468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.622327468
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2864721733
Short name T160
Test name
Test status
Simulation time 244154065 ps
CPU time 1.05 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:10 PM PDT 24
Peak memory 217572 kb
Host smart-002a51a1-29ed-4cb8-87a5-d502461fc49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864721733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2864721733
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2884137891
Short name T526
Test name
Test status
Simulation time 109999483 ps
CPU time 0.8 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:10 PM PDT 24
Peak memory 200256 kb
Host smart-a650247e-9a14-436e-bfef-90bac1909cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884137891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2884137891
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2883768842
Short name T215
Test name
Test status
Simulation time 1088537169 ps
CPU time 4.88 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:17 PM PDT 24
Peak memory 200696 kb
Host smart-bb004202-880d-49b3-a197-db71e9b8f6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883768842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2883768842
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1902745842
Short name T353
Test name
Test status
Simulation time 173073597 ps
CPU time 1.24 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:13 PM PDT 24
Peak memory 200384 kb
Host smart-2192eb86-a48f-4bbf-9f64-8cc1be4aad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902745842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1902745842
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3274134705
Short name T75
Test name
Test status
Simulation time 109945736 ps
CPU time 1.27 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:14 PM PDT 24
Peak memory 200612 kb
Host smart-48efdb8a-92db-4c0b-9986-94edaff54608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274134705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3274134705
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.976124732
Short name T227
Test name
Test status
Simulation time 3639476851 ps
CPU time 12.67 seconds
Started Jul 19 05:08:10 PM PDT 24
Finished Jul 19 05:08:26 PM PDT 24
Peak memory 200752 kb
Host smart-3e7e7e85-fec6-4b81-a181-55f0f6e8912a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976124732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.976124732
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2579970257
Short name T74
Test name
Test status
Simulation time 488410055 ps
CPU time 2.62 seconds
Started Jul 19 05:08:10 PM PDT 24
Finished Jul 19 05:08:15 PM PDT 24
Peak memory 200364 kb
Host smart-d9511410-e25e-4535-99aa-aed11cf7e1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579970257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2579970257
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1200755620
Short name T11
Test name
Test status
Simulation time 81819799 ps
CPU time 0.88 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:13 PM PDT 24
Peak memory 200452 kb
Host smart-4c065a37-0566-434c-8399-ee2ed5890c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200755620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1200755620
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1538990598
Short name T336
Test name
Test status
Simulation time 65821894 ps
CPU time 0.73 seconds
Started Jul 19 05:08:14 PM PDT 24
Finished Jul 19 05:08:17 PM PDT 24
Peak memory 200208 kb
Host smart-fe6f113f-e9a9-4a9e-84ae-90dd5611abd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538990598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1538990598
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.677400616
Short name T41
Test name
Test status
Simulation time 2358628931 ps
CPU time 9.42 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:19 PM PDT 24
Peak memory 217876 kb
Host smart-97f200e1-afda-4a83-867c-44ea36e5706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677400616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.677400616
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.660511142
Short name T487
Test name
Test status
Simulation time 244578078 ps
CPU time 1.05 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:20 PM PDT 24
Peak memory 217560 kb
Host smart-077d6f20-319e-4106-b180-d2412d4449b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660511142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.660511142
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.359213277
Short name T519
Test name
Test status
Simulation time 166204711 ps
CPU time 0.93 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:13 PM PDT 24
Peak memory 200272 kb
Host smart-e350d686-9dc4-4083-bc68-62c6d506fdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359213277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.359213277
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1595518736
Short name T421
Test name
Test status
Simulation time 1146079721 ps
CPU time 5.4 seconds
Started Jul 19 05:08:10 PM PDT 24
Finished Jul 19 05:08:19 PM PDT 24
Peak memory 200696 kb
Host smart-3a86549e-b72d-4713-9144-d36ae57bc3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595518736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1595518736
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3234168946
Short name T237
Test name
Test status
Simulation time 188190363 ps
CPU time 1.23 seconds
Started Jul 19 05:08:18 PM PDT 24
Finished Jul 19 05:08:22 PM PDT 24
Peak memory 200448 kb
Host smart-fccfb9e9-17e9-404e-8cab-3aecb842a96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234168946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3234168946
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3151384711
Short name T147
Test name
Test status
Simulation time 122708338 ps
CPU time 1.13 seconds
Started Jul 19 05:08:10 PM PDT 24
Finished Jul 19 05:08:15 PM PDT 24
Peak memory 200628 kb
Host smart-5d61bea7-6a00-460c-8e8a-6603630214d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151384711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3151384711
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.220292430
Short name T392
Test name
Test status
Simulation time 2400595393 ps
CPU time 11.99 seconds
Started Jul 19 05:08:11 PM PDT 24
Finished Jul 19 05:08:26 PM PDT 24
Peak memory 210272 kb
Host smart-14dfb36e-6fd1-496f-be2b-ae600110d206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220292430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.220292430
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1716816744
Short name T396
Test name
Test status
Simulation time 147563916 ps
CPU time 1.83 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:14 PM PDT 24
Peak memory 200640 kb
Host smart-b12516d8-e0c4-4461-a385-3c53f012646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716816744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1716816744
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.67374135
Short name T132
Test name
Test status
Simulation time 144485333 ps
CPU time 1.21 seconds
Started Jul 19 05:08:16 PM PDT 24
Finished Jul 19 05:08:20 PM PDT 24
Peak memory 200448 kb
Host smart-f56970cb-e68b-47da-859b-c494c73bbc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67374135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.67374135
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3148363612
Short name T133
Test name
Test status
Simulation time 60530084 ps
CPU time 0.71 seconds
Started Jul 19 05:08:18 PM PDT 24
Finished Jul 19 05:08:22 PM PDT 24
Peak memory 200260 kb
Host smart-bde4462f-da0a-4c9a-9ce0-55036c5b4c35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148363612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3148363612
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2055162875
Short name T44
Test name
Test status
Simulation time 244070216 ps
CPU time 1.19 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:29 PM PDT 24
Peak memory 217556 kb
Host smart-6cec43a6-aac4-4267-b56b-ac08f1548113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055162875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2055162875
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2836941523
Short name T472
Test name
Test status
Simulation time 1264258586 ps
CPU time 4.78 seconds
Started Jul 19 05:08:20 PM PDT 24
Finished Jul 19 05:08:27 PM PDT 24
Peak memory 200700 kb
Host smart-31cdafc3-44ef-48a3-8f81-03ffc8ebc4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836941523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2836941523
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3909807208
Short name T435
Test name
Test status
Simulation time 144273305 ps
CPU time 1.09 seconds
Started Jul 19 05:08:15 PM PDT 24
Finished Jul 19 05:08:19 PM PDT 24
Peak memory 200376 kb
Host smart-73728137-c13e-482d-978c-a79e7303f100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909807208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3909807208
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.190114405
Short name T520
Test name
Test status
Simulation time 119322584 ps
CPU time 1.29 seconds
Started Jul 19 05:08:15 PM PDT 24
Finished Jul 19 05:08:18 PM PDT 24
Peak memory 200680 kb
Host smart-4ae5bd0d-2cf8-489f-b3cb-fb5793d81140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190114405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.190114405
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3868545278
Short name T418
Test name
Test status
Simulation time 8196802539 ps
CPU time 29.49 seconds
Started Jul 19 05:08:14 PM PDT 24
Finished Jul 19 05:08:45 PM PDT 24
Peak memory 208960 kb
Host smart-633e8fe3-41bc-4a24-a624-83d45e48087f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868545278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3868545278
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1867440021
Short name T377
Test name
Test status
Simulation time 447239529 ps
CPU time 2.48 seconds
Started Jul 19 05:08:14 PM PDT 24
Finished Jul 19 05:08:19 PM PDT 24
Peak memory 200500 kb
Host smart-88b36dba-ba60-4f5f-b5ec-16859d85b3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867440021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1867440021
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2253948525
Short name T255
Test name
Test status
Simulation time 145272006 ps
CPU time 1.21 seconds
Started Jul 19 05:08:19 PM PDT 24
Finished Jul 19 05:08:23 PM PDT 24
Peak memory 200388 kb
Host smart-47d06f01-f90e-42ba-8dea-4064ac07cd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253948525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2253948525
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.343926549
Short name T463
Test name
Test status
Simulation time 80651845 ps
CPU time 0.87 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:20 PM PDT 24
Peak memory 200128 kb
Host smart-ab331532-dd17-4583-a9de-c05680b800b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343926549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.343926549
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.958916169
Short name T525
Test name
Test status
Simulation time 2174917074 ps
CPU time 9.64 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:30 PM PDT 24
Peak memory 217664 kb
Host smart-288018fb-0b4d-4c2b-9687-f62a26599e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958916169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.958916169
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2306106862
Short name T476
Test name
Test status
Simulation time 244870538 ps
CPU time 1.04 seconds
Started Jul 19 05:08:16 PM PDT 24
Finished Jul 19 05:08:19 PM PDT 24
Peak memory 217512 kb
Host smart-08cef376-4b68-4677-89f3-00ee8b151534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306106862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2306106862
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.487341303
Short name T427
Test name
Test status
Simulation time 110735485 ps
CPU time 0.78 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:27 PM PDT 24
Peak memory 200256 kb
Host smart-0f9f6484-606c-49a4-a2d5-a2619152de31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487341303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.487341303
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.771331080
Short name T258
Test name
Test status
Simulation time 955997958 ps
CPU time 4.77 seconds
Started Jul 19 05:08:15 PM PDT 24
Finished Jul 19 05:08:22 PM PDT 24
Peak memory 200728 kb
Host smart-dba9995c-efa6-44b5-9ff5-e48f317d599e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771331080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.771331080
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2599662342
Short name T203
Test name
Test status
Simulation time 177405215 ps
CPU time 1.2 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:21 PM PDT 24
Peak memory 200456 kb
Host smart-5b178e59-c884-45b3-8e0b-2e652bf28a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599662342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2599662342
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.523843278
Short name T304
Test name
Test status
Simulation time 191372173 ps
CPU time 1.45 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:22 PM PDT 24
Peak memory 200680 kb
Host smart-3271b294-d076-4b20-8403-a5602c00cbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523843278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.523843278
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3379582716
Short name T79
Test name
Test status
Simulation time 3048799445 ps
CPU time 13.23 seconds
Started Jul 19 05:08:26 PM PDT 24
Finished Jul 19 05:08:42 PM PDT 24
Peak memory 209020 kb
Host smart-72431223-3c8e-425a-b7d8-777a66c4aec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379582716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3379582716
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2035734654
Short name T440
Test name
Test status
Simulation time 293526878 ps
CPU time 1.93 seconds
Started Jul 19 05:08:16 PM PDT 24
Finished Jul 19 05:08:21 PM PDT 24
Peak memory 208660 kb
Host smart-f440011d-29f3-4f27-9c95-78c56a0abfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035734654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2035734654
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1257038930
Short name T224
Test name
Test status
Simulation time 217659424 ps
CPU time 1.39 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:21 PM PDT 24
Peak memory 200284 kb
Host smart-188b71db-50cb-410a-b0d7-015e4cf0270f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257038930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1257038930
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2661554470
Short name T273
Test name
Test status
Simulation time 61198806 ps
CPU time 0.71 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:27 PM PDT 24
Peak memory 200260 kb
Host smart-232b9ae2-1a91-4f73-9b43-fb6d377ae44b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661554470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2661554470
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3594025506
Short name T27
Test name
Test status
Simulation time 2168511256 ps
CPU time 8.39 seconds
Started Jul 19 05:08:25 PM PDT 24
Finished Jul 19 05:08:37 PM PDT 24
Peak memory 217648 kb
Host smart-9d903433-9e1d-4487-9e5c-5ab881d1e742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594025506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3594025506
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.871439359
Short name T374
Test name
Test status
Simulation time 246865655 ps
CPU time 1.1 seconds
Started Jul 19 05:08:16 PM PDT 24
Finished Jul 19 05:08:20 PM PDT 24
Peak memory 218432 kb
Host smart-96121ef6-ea3c-40c0-97de-512fadd1f6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871439359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.871439359
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3731937859
Short name T136
Test name
Test status
Simulation time 228368056 ps
CPU time 1.09 seconds
Started Jul 19 05:08:18 PM PDT 24
Finished Jul 19 05:08:22 PM PDT 24
Peak memory 200268 kb
Host smart-2a4fc1fa-fbe6-4269-a7c7-0ef81d797334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731937859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3731937859
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1586033150
Short name T277
Test name
Test status
Simulation time 1936421600 ps
CPU time 7.35 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:28 PM PDT 24
Peak memory 200644 kb
Host smart-57d2eb1d-55cf-4305-ab0a-68100d00161a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586033150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1586033150
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.638061212
Short name T481
Test name
Test status
Simulation time 146314802 ps
CPU time 1.21 seconds
Started Jul 19 05:08:19 PM PDT 24
Finished Jul 19 05:08:23 PM PDT 24
Peak memory 200464 kb
Host smart-a42a91c6-7c8f-45bf-b563-b866ec2f501a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638061212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.638061212
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2035965170
Short name T423
Test name
Test status
Simulation time 122743563 ps
CPU time 1.2 seconds
Started Jul 19 05:08:15 PM PDT 24
Finished Jul 19 05:08:18 PM PDT 24
Peak memory 200716 kb
Host smart-c962f0ff-ad01-4081-8b7e-9281d77209eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035965170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2035965170
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.4137250022
Short name T100
Test name
Test status
Simulation time 3917054011 ps
CPU time 15.96 seconds
Started Jul 19 05:08:20 PM PDT 24
Finished Jul 19 05:08:39 PM PDT 24
Peak memory 200712 kb
Host smart-288913b3-43b1-4414-925f-031b7c2e48c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137250022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.4137250022
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1074569866
Short name T319
Test name
Test status
Simulation time 145449929 ps
CPU time 1.74 seconds
Started Jul 19 05:08:25 PM PDT 24
Finished Jul 19 05:08:30 PM PDT 24
Peak memory 200468 kb
Host smart-1a201a78-d81b-4a2e-9384-3405f615a874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074569866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1074569866
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1523440251
Short name T154
Test name
Test status
Simulation time 145982328 ps
CPU time 1.11 seconds
Started Jul 19 05:08:16 PM PDT 24
Finished Jul 19 05:08:20 PM PDT 24
Peak memory 200276 kb
Host smart-61eb6ed0-c3f6-4bf6-a8f0-c1879481d272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523440251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1523440251
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2277098513
Short name T134
Test name
Test status
Simulation time 80372432 ps
CPU time 0.85 seconds
Started Jul 19 05:08:15 PM PDT 24
Finished Jul 19 05:08:18 PM PDT 24
Peak memory 200184 kb
Host smart-15267c98-cb94-4b07-8d41-ad011ff7ba6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277098513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2277098513
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3025528107
Short name T366
Test name
Test status
Simulation time 1904334089 ps
CPU time 7.3 seconds
Started Jul 19 05:08:25 PM PDT 24
Finished Jul 19 05:08:35 PM PDT 24
Peak memory 221728 kb
Host smart-32b47a82-26b3-47de-9696-4ed9b1768aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025528107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3025528107
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2748690718
Short name T323
Test name
Test status
Simulation time 244196523 ps
CPU time 1.05 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:21 PM PDT 24
Peak memory 217512 kb
Host smart-24e0faac-9a10-4c0c-a4b7-5ff2b0da4cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748690718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2748690718
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3136506667
Short name T265
Test name
Test status
Simulation time 227373710 ps
CPU time 0.91 seconds
Started Jul 19 05:08:18 PM PDT 24
Finished Jul 19 05:08:22 PM PDT 24
Peak memory 200268 kb
Host smart-6ddc46a8-07d4-49df-92f0-c7290d1664cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136506667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3136506667
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1611181616
Short name T275
Test name
Test status
Simulation time 792820617 ps
CPU time 3.95 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 200724 kb
Host smart-a75e73fe-4b64-4686-9a78-b0435a6f41ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611181616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1611181616
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3982615218
Short name T293
Test name
Test status
Simulation time 145492247 ps
CPU time 1.15 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:21 PM PDT 24
Peak memory 200464 kb
Host smart-66ba7419-201f-4836-866f-a7aa7636e9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982615218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3982615218
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4112214130
Short name T129
Test name
Test status
Simulation time 120484870 ps
CPU time 1.26 seconds
Started Jul 19 05:08:15 PM PDT 24
Finished Jul 19 05:08:18 PM PDT 24
Peak memory 200716 kb
Host smart-d2bc0308-6c76-4e53-8cbc-911717c2def0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112214130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4112214130
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3066403406
Short name T72
Test name
Test status
Simulation time 8775970350 ps
CPU time 33.78 seconds
Started Jul 19 05:08:19 PM PDT 24
Finished Jul 19 05:08:56 PM PDT 24
Peak memory 210092 kb
Host smart-ceb198b6-105c-4a57-9fd0-d67bd118b742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066403406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3066403406
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3347914635
Short name T429
Test name
Test status
Simulation time 110328367 ps
CPU time 1.41 seconds
Started Jul 19 05:08:18 PM PDT 24
Finished Jul 19 05:08:23 PM PDT 24
Peak memory 200436 kb
Host smart-80805d40-f57e-4fa3-a9c7-44ca4562fcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347914635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3347914635
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3995573103
Short name T171
Test name
Test status
Simulation time 99165129 ps
CPU time 0.86 seconds
Started Jul 19 05:08:25 PM PDT 24
Finished Jul 19 05:08:29 PM PDT 24
Peak memory 200444 kb
Host smart-bd865b3d-be15-4d7e-8b69-a2d7a2b53f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995573103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3995573103
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2801047988
Short name T191
Test name
Test status
Simulation time 84772621 ps
CPU time 0.8 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:28 PM PDT 24
Peak memory 200256 kb
Host smart-08f4cdc4-ff83-4920-8b24-7cd9f97b519d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801047988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2801047988
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1478319620
Short name T493
Test name
Test status
Simulation time 1894264008 ps
CPU time 7.06 seconds
Started Jul 19 05:08:15 PM PDT 24
Finished Jul 19 05:08:24 PM PDT 24
Peak memory 217800 kb
Host smart-139543e7-85ae-4c28-a628-9604eaadf526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478319620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1478319620
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2814210083
Short name T406
Test name
Test status
Simulation time 243496265 ps
CPU time 1.05 seconds
Started Jul 19 05:08:18 PM PDT 24
Finished Jul 19 05:08:22 PM PDT 24
Peak memory 217500 kb
Host smart-bea4f1a4-4cd9-45dc-a068-d37d29ffaedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814210083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2814210083
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3657868816
Short name T478
Test name
Test status
Simulation time 170033185 ps
CPU time 0.9 seconds
Started Jul 19 05:08:16 PM PDT 24
Finished Jul 19 05:08:20 PM PDT 24
Peak memory 200268 kb
Host smart-e14f6173-09a7-464c-9dfb-16a29f04b24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657868816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3657868816
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2161511196
Short name T152
Test name
Test status
Simulation time 1381915633 ps
CPU time 5.44 seconds
Started Jul 19 05:08:25 PM PDT 24
Finished Jul 19 05:08:34 PM PDT 24
Peak memory 200720 kb
Host smart-2f21f651-cb1a-49d5-9624-cebbbd130d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161511196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2161511196
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3669546045
Short name T180
Test name
Test status
Simulation time 175198986 ps
CPU time 1.19 seconds
Started Jul 19 05:08:16 PM PDT 24
Finished Jul 19 05:08:20 PM PDT 24
Peak memory 200348 kb
Host smart-6bfb9bf6-9808-4ccd-8e68-022f15effd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669546045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3669546045
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.4147721125
Short name T451
Test name
Test status
Simulation time 122828745 ps
CPU time 1.19 seconds
Started Jul 19 05:08:16 PM PDT 24
Finished Jul 19 05:08:20 PM PDT 24
Peak memory 200700 kb
Host smart-a24531d1-1457-42dd-8028-237eed80f3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147721125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.4147721125
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2945551949
Short name T338
Test name
Test status
Simulation time 4596189391 ps
CPU time 21.33 seconds
Started Jul 19 05:08:19 PM PDT 24
Finished Jul 19 05:08:43 PM PDT 24
Peak memory 208952 kb
Host smart-ee158574-ab9c-4c57-aee0-665785473d20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945551949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2945551949
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3643407779
Short name T461
Test name
Test status
Simulation time 354153675 ps
CPU time 2.09 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:23 PM PDT 24
Peak memory 200380 kb
Host smart-308faccd-2237-4bb5-ad93-b8f6344f8033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643407779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3643407779
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3980452144
Short name T324
Test name
Test status
Simulation time 196868160 ps
CPU time 1.32 seconds
Started Jul 19 05:08:14 PM PDT 24
Finished Jul 19 05:08:18 PM PDT 24
Peak memory 200368 kb
Host smart-2a888121-e443-4265-805f-e3ada24f2c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980452144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3980452144
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1419398605
Short name T198
Test name
Test status
Simulation time 58065204 ps
CPU time 0.72 seconds
Started Jul 19 05:08:22 PM PDT 24
Finished Jul 19 05:08:26 PM PDT 24
Peak memory 200276 kb
Host smart-100ab07c-25f1-4882-a5e3-e979ee76d469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419398605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1419398605
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2712112974
Short name T29
Test name
Test status
Simulation time 1897302506 ps
CPU time 6.79 seconds
Started Jul 19 05:08:23 PM PDT 24
Finished Jul 19 05:08:32 PM PDT 24
Peak memory 217348 kb
Host smart-1cb4f4f6-8d87-4dba-8e27-06f946a0ab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712112974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2712112974
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1697251433
Short name T213
Test name
Test status
Simulation time 243738540 ps
CPU time 1.04 seconds
Started Jul 19 05:08:23 PM PDT 24
Finished Jul 19 05:08:26 PM PDT 24
Peak memory 217468 kb
Host smart-59badac8-bdfd-48af-894f-bcf482f1902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697251433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1697251433
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.797227858
Short name T17
Test name
Test status
Simulation time 82280290 ps
CPU time 0.72 seconds
Started Jul 19 05:08:19 PM PDT 24
Finished Jul 19 05:08:23 PM PDT 24
Peak memory 200200 kb
Host smart-91a91ec0-ff4d-4194-8734-6bbe7fea6f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797227858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.797227858
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.4278225805
Short name T405
Test name
Test status
Simulation time 1542538390 ps
CPU time 6.92 seconds
Started Jul 19 05:08:19 PM PDT 24
Finished Jul 19 05:08:28 PM PDT 24
Peak memory 200656 kb
Host smart-d27fe17e-1708-456e-8963-9c8f0128dc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278225805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.4278225805
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.618014931
Short name T395
Test name
Test status
Simulation time 99775712 ps
CPU time 1.01 seconds
Started Jul 19 05:08:28 PM PDT 24
Finished Jul 19 05:08:32 PM PDT 24
Peak memory 200476 kb
Host smart-2a2ca315-f641-46df-b614-a0938283cb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618014931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.618014931
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1375574836
Short name T228
Test name
Test status
Simulation time 255819800 ps
CPU time 1.58 seconds
Started Jul 19 05:08:15 PM PDT 24
Finished Jul 19 05:08:19 PM PDT 24
Peak memory 200480 kb
Host smart-fc821d4c-a515-46de-92e3-43a479bb8079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375574836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1375574836
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1625138640
Short name T402
Test name
Test status
Simulation time 9379064706 ps
CPU time 31.15 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:57 PM PDT 24
Peak memory 208992 kb
Host smart-b3b29e5b-9127-42cb-8084-ce59b72e9973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625138640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1625138640
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2104456684
Short name T420
Test name
Test status
Simulation time 145618189 ps
CPU time 1.77 seconds
Started Jul 19 05:08:27 PM PDT 24
Finished Jul 19 05:08:32 PM PDT 24
Peak memory 208664 kb
Host smart-678f53ae-4bfd-4f99-be99-981d4a4084ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104456684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2104456684
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3961426587
Short name T151
Test name
Test status
Simulation time 113189893 ps
CPU time 0.92 seconds
Started Jul 19 05:08:23 PM PDT 24
Finished Jul 19 05:08:26 PM PDT 24
Peak memory 200636 kb
Host smart-4230e2fd-3a4a-4f58-a126-1badf3f31386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961426587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3961426587
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.4235488654
Short name T436
Test name
Test status
Simulation time 76787052 ps
CPU time 0.82 seconds
Started Jul 19 05:08:22 PM PDT 24
Finished Jul 19 05:08:25 PM PDT 24
Peak memory 200260 kb
Host smart-ff76240d-90ba-4795-a11f-85831ac0e452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235488654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4235488654
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.529125750
Short name T47
Test name
Test status
Simulation time 1215323115 ps
CPU time 6.39 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:33 PM PDT 24
Peak memory 230000 kb
Host smart-976858d1-8f2b-49ea-b170-a12555f346c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529125750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.529125750
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2305597563
Short name T166
Test name
Test status
Simulation time 243575332 ps
CPU time 1.13 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:28 PM PDT 24
Peak memory 217508 kb
Host smart-dffa568a-8fc3-4fba-bd73-475246e43d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305597563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2305597563
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2646905052
Short name T15
Test name
Test status
Simulation time 113947346 ps
CPU time 0.83 seconds
Started Jul 19 05:08:29 PM PDT 24
Finished Jul 19 05:08:32 PM PDT 24
Peak memory 199200 kb
Host smart-1f05a8fa-b855-48bd-9334-3f57e2c36b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646905052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2646905052
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3224798160
Short name T91
Test name
Test status
Simulation time 1935462478 ps
CPU time 6.83 seconds
Started Jul 19 05:08:22 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 200620 kb
Host smart-2d0a5bf9-a432-4185-b444-a38a4f8350fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224798160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3224798160
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1502135463
Short name T455
Test name
Test status
Simulation time 158747187 ps
CPU time 1.2 seconds
Started Jul 19 05:08:22 PM PDT 24
Finished Jul 19 05:08:25 PM PDT 24
Peak memory 200448 kb
Host smart-4aadc836-3fc9-4ac3-b8b2-fa72b329c8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502135463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1502135463
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3233155254
Short name T71
Test name
Test status
Simulation time 119231210 ps
CPU time 1.25 seconds
Started Jul 19 05:08:28 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 200636 kb
Host smart-7c9bdf86-024c-4b7c-be00-16557867f221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233155254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3233155254
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1197028833
Short name T155
Test name
Test status
Simulation time 401663236 ps
CPU time 2.09 seconds
Started Jul 19 05:08:26 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 200448 kb
Host smart-01d076e4-f43f-4177-8b1d-a7fec667dd7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197028833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1197028833
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2611126812
Short name T173
Test name
Test status
Simulation time 307695672 ps
CPU time 2.04 seconds
Started Jul 19 05:08:28 PM PDT 24
Finished Jul 19 05:08:33 PM PDT 24
Peak memory 208708 kb
Host smart-c3799b65-51fe-4ccc-961a-f8a3c2d75307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611126812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2611126812
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1959220000
Short name T354
Test name
Test status
Simulation time 276491489 ps
CPU time 1.48 seconds
Started Jul 19 05:08:29 PM PDT 24
Finished Jul 19 05:08:32 PM PDT 24
Peak memory 199488 kb
Host smart-7644199e-4078-4407-8095-9440a5dfb8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959220000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1959220000
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2172591152
Short name T308
Test name
Test status
Simulation time 88357120 ps
CPU time 0.92 seconds
Started Jul 19 05:07:52 PM PDT 24
Finished Jul 19 05:07:55 PM PDT 24
Peak memory 200260 kb
Host smart-13f21766-34a7-4d62-af99-41d4cb67c6cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172591152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2172591152
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.458005478
Short name T24
Test name
Test status
Simulation time 1227957999 ps
CPU time 5.69 seconds
Started Jul 19 05:07:50 PM PDT 24
Finished Jul 19 05:07:58 PM PDT 24
Peak memory 217784 kb
Host smart-5781714d-e455-4601-8f9a-d82570db58f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458005478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.458005478
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3390043513
Short name T473
Test name
Test status
Simulation time 243781315 ps
CPU time 1.13 seconds
Started Jul 19 05:07:50 PM PDT 24
Finished Jul 19 05:07:53 PM PDT 24
Peak memory 217508 kb
Host smart-442d097b-e218-4aba-87ae-59e821364314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390043513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3390043513
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2446234697
Short name T185
Test name
Test status
Simulation time 192527200 ps
CPU time 0.93 seconds
Started Jul 19 05:07:51 PM PDT 24
Finished Jul 19 05:07:54 PM PDT 24
Peak memory 200280 kb
Host smart-dfbfba79-a48b-4a99-8873-9e7b46aef33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446234697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2446234697
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3517113234
Short name T238
Test name
Test status
Simulation time 896207152 ps
CPU time 5.05 seconds
Started Jul 19 05:07:53 PM PDT 24
Finished Jul 19 05:08:00 PM PDT 24
Peak memory 200728 kb
Host smart-fbd32ddc-7c00-43e7-982f-c656e36b143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517113234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3517113234
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1699379328
Short name T57
Test name
Test status
Simulation time 16529128611 ps
CPU time 27.49 seconds
Started Jul 19 05:07:49 PM PDT 24
Finished Jul 19 05:08:19 PM PDT 24
Peak memory 217228 kb
Host smart-b40074ca-952b-438c-89af-522a724c63b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699379328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1699379328
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3691148079
Short name T398
Test name
Test status
Simulation time 146206510 ps
CPU time 1.24 seconds
Started Jul 19 05:07:54 PM PDT 24
Finished Jul 19 05:07:57 PM PDT 24
Peak memory 200460 kb
Host smart-f49eb802-9f98-44f2-9445-af9537183b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691148079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3691148079
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3697765496
Short name T501
Test name
Test status
Simulation time 248741410 ps
CPU time 1.58 seconds
Started Jul 19 05:07:49 PM PDT 24
Finished Jul 19 05:07:53 PM PDT 24
Peak memory 200584 kb
Host smart-5baef347-5fc5-4874-bcc5-98a73e883079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697765496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3697765496
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.734170669
Short name T466
Test name
Test status
Simulation time 11660031050 ps
CPU time 47.26 seconds
Started Jul 19 05:07:52 PM PDT 24
Finished Jul 19 05:08:42 PM PDT 24
Peak memory 217120 kb
Host smart-e9ab5a45-f412-457f-928f-0cb90a873a0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734170669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.734170669
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.808921362
Short name T282
Test name
Test status
Simulation time 369107642 ps
CPU time 2.49 seconds
Started Jul 19 05:07:49 PM PDT 24
Finished Jul 19 05:07:54 PM PDT 24
Peak memory 200448 kb
Host smart-3ca18d79-4a85-47bd-8d45-3124ef0133e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808921362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.808921362
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1164848156
Short name T131
Test name
Test status
Simulation time 145110559 ps
CPU time 1.18 seconds
Started Jul 19 05:07:50 PM PDT 24
Finished Jul 19 05:07:54 PM PDT 24
Peak memory 200448 kb
Host smart-d8981f2b-44a2-4a8a-bfa1-f9027306aae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164848156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1164848156
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3904455299
Short name T515
Test name
Test status
Simulation time 71283230 ps
CPU time 0.78 seconds
Started Jul 19 05:08:28 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 200260 kb
Host smart-7e546a43-9f84-4bd0-966f-e3535d85ded7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904455299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3904455299
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1958989400
Short name T259
Test name
Test status
Simulation time 1229330650 ps
CPU time 5.88 seconds
Started Jul 19 05:08:20 PM PDT 24
Finished Jul 19 05:08:29 PM PDT 24
Peak memory 221808 kb
Host smart-41470032-c78a-4bd9-9a03-3f73eaabec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958989400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1958989400
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1556271551
Short name T523
Test name
Test status
Simulation time 244828329 ps
CPU time 1.1 seconds
Started Jul 19 05:08:27 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 217564 kb
Host smart-89076076-7631-4fcb-bef1-8157d950c190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556271551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1556271551
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2602643204
Short name T460
Test name
Test status
Simulation time 223367181 ps
CPU time 0.95 seconds
Started Jul 19 05:08:28 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 200256 kb
Host smart-da0ca9b4-51f6-41fc-87a6-e70c21599866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602643204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2602643204
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3141178951
Short name T441
Test name
Test status
Simulation time 1649590334 ps
CPU time 6.68 seconds
Started Jul 19 05:08:21 PM PDT 24
Finished Jul 19 05:08:30 PM PDT 24
Peak memory 200728 kb
Host smart-d54ed2c4-aa55-46b6-9685-c420dd1c2b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141178951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3141178951
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2086452181
Short name T302
Test name
Test status
Simulation time 174947016 ps
CPU time 1.16 seconds
Started Jul 19 05:08:21 PM PDT 24
Finished Jul 19 05:08:25 PM PDT 24
Peak memory 200456 kb
Host smart-4aa617e5-4ceb-4c43-aa92-fdaec4fb7206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086452181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2086452181
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1846160669
Short name T330
Test name
Test status
Simulation time 197612984 ps
CPU time 1.37 seconds
Started Jul 19 05:08:25 PM PDT 24
Finished Jul 19 05:08:30 PM PDT 24
Peak memory 200664 kb
Host smart-05e8626e-f61c-4d91-8da5-0c4f55f8250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846160669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1846160669
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2082197816
Short name T345
Test name
Test status
Simulation time 6547448958 ps
CPU time 23.26 seconds
Started Jul 19 05:08:28 PM PDT 24
Finished Jul 19 05:08:54 PM PDT 24
Peak memory 200784 kb
Host smart-6d32db23-d554-4c28-bab7-9e33ce541c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082197816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2082197816
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.876673923
Short name T433
Test name
Test status
Simulation time 373155501 ps
CPU time 2.44 seconds
Started Jul 19 05:08:21 PM PDT 24
Finished Jul 19 05:08:26 PM PDT 24
Peak memory 200412 kb
Host smart-5a039c7b-d849-4391-a3af-13006e8c4684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876673923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.876673923
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.407581297
Short name T534
Test name
Test status
Simulation time 64522909 ps
CPU time 0.77 seconds
Started Jul 19 05:08:28 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 200288 kb
Host smart-508d8432-7344-4c4a-8b86-2a6230dcef00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407581297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.407581297
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2501656784
Short name T43
Test name
Test status
Simulation time 1229331237 ps
CPU time 5.96 seconds
Started Jul 19 05:08:22 PM PDT 24
Finished Jul 19 05:08:30 PM PDT 24
Peak memory 217680 kb
Host smart-414eef18-f6df-4a57-af2b-e64bb7b79751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501656784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2501656784
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2870563996
Short name T142
Test name
Test status
Simulation time 244237696 ps
CPU time 1.11 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:28 PM PDT 24
Peak memory 217444 kb
Host smart-0546eb92-e934-4e96-9ee8-95b57b1bfce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870563996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2870563996
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.782452581
Short name T506
Test name
Test status
Simulation time 124819490 ps
CPU time 0.84 seconds
Started Jul 19 05:08:23 PM PDT 24
Finished Jul 19 05:08:26 PM PDT 24
Peak memory 200268 kb
Host smart-93acb266-d6b0-4160-b83c-c82bffb4d795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782452581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.782452581
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.648873730
Short name T89
Test name
Test status
Simulation time 1202034477 ps
CPU time 5.25 seconds
Started Jul 19 05:08:23 PM PDT 24
Finished Jul 19 05:08:30 PM PDT 24
Peak memory 200652 kb
Host smart-6af92afb-aa4a-4b82-9a69-11d9b4ded5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648873730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.648873730
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3037709316
Short name T253
Test name
Test status
Simulation time 126904286 ps
CPU time 1.26 seconds
Started Jul 19 05:08:28 PM PDT 24
Finished Jul 19 05:08:32 PM PDT 24
Peak memory 200656 kb
Host smart-aa3949b1-69b1-4547-b21c-bc00b68ac96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037709316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3037709316
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3751018274
Short name T386
Test name
Test status
Simulation time 2789142414 ps
CPU time 14.5 seconds
Started Jul 19 05:08:28 PM PDT 24
Finished Jul 19 05:08:45 PM PDT 24
Peak memory 208984 kb
Host smart-1c0e6218-6f44-41ac-92c9-fbb7f282ebec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751018274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3751018274
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.369008646
Short name T170
Test name
Test status
Simulation time 135451020 ps
CPU time 1.69 seconds
Started Jul 19 05:08:23 PM PDT 24
Finished Jul 19 05:08:27 PM PDT 24
Peak memory 200396 kb
Host smart-34c20407-2f17-4669-badf-3a5bb9542861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369008646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.369008646
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1356514253
Short name T194
Test name
Test status
Simulation time 142123256 ps
CPU time 1.25 seconds
Started Jul 19 05:08:22 PM PDT 24
Finished Jul 19 05:08:25 PM PDT 24
Peak memory 200448 kb
Host smart-679be2f2-a4ca-46df-a29b-7358249f1b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356514253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1356514253
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3580247249
Short name T143
Test name
Test status
Simulation time 69825583 ps
CPU time 0.77 seconds
Started Jul 19 05:08:37 PM PDT 24
Finished Jul 19 05:08:39 PM PDT 24
Peak memory 200256 kb
Host smart-e05d9ce7-3562-4af3-bf4c-601c7642368e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580247249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3580247249
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3887581951
Short name T344
Test name
Test status
Simulation time 2357758883 ps
CPU time 7.9 seconds
Started Jul 19 05:08:27 PM PDT 24
Finished Jul 19 05:08:38 PM PDT 24
Peak memory 217844 kb
Host smart-78c98372-ea4e-4136-8cf0-403019551e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887581951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3887581951
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.4161802287
Short name T139
Test name
Test status
Simulation time 244026158 ps
CPU time 1.08 seconds
Started Jul 19 05:08:24 PM PDT 24
Finished Jul 19 05:08:28 PM PDT 24
Peak memory 217444 kb
Host smart-bf873839-32cb-4e6c-985e-c77b912a84bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161802287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.4161802287
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.900738472
Short name T140
Test name
Test status
Simulation time 184290804 ps
CPU time 0.86 seconds
Started Jul 19 05:08:25 PM PDT 24
Finished Jul 19 05:08:29 PM PDT 24
Peak memory 200228 kb
Host smart-23dad06e-f114-4f7a-b0e1-63260ccaa4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900738472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.900738472
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2116230031
Short name T488
Test name
Test status
Simulation time 635822050 ps
CPU time 3.86 seconds
Started Jul 19 05:08:29 PM PDT 24
Finished Jul 19 05:08:35 PM PDT 24
Peak memory 200696 kb
Host smart-7f461fcf-f0a2-4548-bc6a-477b593d7cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116230031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2116230031
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1558190400
Short name T513
Test name
Test status
Simulation time 178581771 ps
CPU time 1.18 seconds
Started Jul 19 05:08:26 PM PDT 24
Finished Jul 19 05:08:30 PM PDT 24
Peak memory 200420 kb
Host smart-0ccb9bea-baf0-4865-826a-08e98622fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558190400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1558190400
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.144450850
Short name T303
Test name
Test status
Simulation time 196833810 ps
CPU time 1.37 seconds
Started Jul 19 05:08:27 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 200660 kb
Host smart-30acd9d5-8e54-40fa-aa82-d6dcccd70204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144450850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.144450850
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.848465818
Short name T315
Test name
Test status
Simulation time 10016684714 ps
CPU time 40.23 seconds
Started Jul 19 05:08:23 PM PDT 24
Finished Jul 19 05:09:06 PM PDT 24
Peak memory 208992 kb
Host smart-d0370511-daae-4497-9c30-d6ff639af9df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848465818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.848465818
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3252879503
Short name T236
Test name
Test status
Simulation time 150904763 ps
CPU time 1.85 seconds
Started Jul 19 05:08:25 PM PDT 24
Finished Jul 19 05:08:30 PM PDT 24
Peak memory 200476 kb
Host smart-e7fb7540-d835-47b6-a881-7447f2c854c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252879503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3252879503
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2966175259
Short name T483
Test name
Test status
Simulation time 137914866 ps
CPU time 1.18 seconds
Started Jul 19 05:08:22 PM PDT 24
Finished Jul 19 05:08:25 PM PDT 24
Peak memory 200448 kb
Host smart-9d8e9e4c-eb0c-4b16-835d-e71fa8eb5310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966175259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2966175259
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1962033630
Short name T505
Test name
Test status
Simulation time 68533981 ps
CPU time 0.78 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:44 PM PDT 24
Peak memory 200272 kb
Host smart-90d56b3d-fc6d-4dff-82a6-f746def8a5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962033630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1962033630
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1520821416
Short name T448
Test name
Test status
Simulation time 2183130902 ps
CPU time 8.03 seconds
Started Jul 19 05:08:38 PM PDT 24
Finished Jul 19 05:08:49 PM PDT 24
Peak memory 217788 kb
Host smart-8cecd1fa-fa39-441c-8410-88be3a128f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520821416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1520821416
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.340894320
Short name T63
Test name
Test status
Simulation time 243695372 ps
CPU time 1.12 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:08:39 PM PDT 24
Peak memory 217560 kb
Host smart-aa224fe0-2201-42cb-9122-d9522229ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340894320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.340894320
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2183839189
Short name T288
Test name
Test status
Simulation time 101574407 ps
CPU time 0.81 seconds
Started Jul 19 05:08:37 PM PDT 24
Finished Jul 19 05:08:39 PM PDT 24
Peak memory 200260 kb
Host smart-a54a533f-b186-4df6-9557-6ba2ba945024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183839189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2183839189
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2877496457
Short name T507
Test name
Test status
Simulation time 1586594141 ps
CPU time 5.91 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:08:44 PM PDT 24
Peak memory 200696 kb
Host smart-694779f6-e413-4ea6-a948-c4709f227042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877496457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2877496457
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1816155424
Short name T299
Test name
Test status
Simulation time 147374782 ps
CPU time 1.1 seconds
Started Jul 19 05:08:38 PM PDT 24
Finished Jul 19 05:08:42 PM PDT 24
Peak memory 200464 kb
Host smart-ab3e6473-a53c-42bc-9c3e-21c72aa153a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816155424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1816155424
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.311526304
Short name T209
Test name
Test status
Simulation time 118452036 ps
CPU time 1.13 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:08:39 PM PDT 24
Peak memory 200604 kb
Host smart-f23c87f6-2c7c-48da-9256-2f66645adb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311526304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.311526304
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1263086766
Short name T491
Test name
Test status
Simulation time 2012583254 ps
CPU time 10.34 seconds
Started Jul 19 05:08:37 PM PDT 24
Finished Jul 19 05:08:49 PM PDT 24
Peak memory 208940 kb
Host smart-0747c863-d34e-457f-85dd-e419f03a2a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263086766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1263086766
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1885940572
Short name T223
Test name
Test status
Simulation time 297200994 ps
CPU time 1.91 seconds
Started Jul 19 05:08:41 PM PDT 24
Finished Jul 19 05:08:46 PM PDT 24
Peak memory 208660 kb
Host smart-3336a76b-22b5-40d1-ba91-762914daaf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885940572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1885940572
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1619886238
Short name T410
Test name
Test status
Simulation time 188034561 ps
CPU time 1.2 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:08:39 PM PDT 24
Peak memory 200428 kb
Host smart-e536a79f-2d76-4290-9935-3ba8bf03ebaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619886238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1619886238
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3038310915
Short name T419
Test name
Test status
Simulation time 75029174 ps
CPU time 0.78 seconds
Started Jul 19 05:08:37 PM PDT 24
Finished Jul 19 05:08:40 PM PDT 24
Peak memory 200248 kb
Host smart-294d9874-cf7c-4114-9795-8841a5851a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038310915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3038310915
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.236287771
Short name T45
Test name
Test status
Simulation time 1225299918 ps
CPU time 6.07 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:08:43 PM PDT 24
Peak memory 217680 kb
Host smart-3880ef3b-6726-45cc-9596-db3659d34796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236287771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.236287771
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.176838416
Short name T384
Test name
Test status
Simulation time 244039160 ps
CPU time 1.14 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:42 PM PDT 24
Peak memory 217440 kb
Host smart-0054caae-218f-489c-93fc-b9678b65d01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176838416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.176838416
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2574721141
Short name T94
Test name
Test status
Simulation time 140413310 ps
CPU time 0.84 seconds
Started Jul 19 05:08:38 PM PDT 24
Finished Jul 19 05:08:41 PM PDT 24
Peak memory 200276 kb
Host smart-ca7a5f84-d9b9-489e-a786-17c425fb98be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574721141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2574721141
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2939204657
Short name T352
Test name
Test status
Simulation time 1945249462 ps
CPU time 6.97 seconds
Started Jul 19 05:08:38 PM PDT 24
Finished Jul 19 05:08:48 PM PDT 24
Peak memory 200744 kb
Host smart-a614c395-a4bb-43c0-95df-0737f8b854e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939204657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2939204657
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3565975153
Short name T216
Test name
Test status
Simulation time 145776066 ps
CPU time 1.09 seconds
Started Jul 19 05:08:37 PM PDT 24
Finished Jul 19 05:08:40 PM PDT 24
Peak memory 200464 kb
Host smart-f03880d1-a020-4150-8d72-cff30d66d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565975153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3565975153
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.989813527
Short name T271
Test name
Test status
Simulation time 192566268 ps
CPU time 1.4 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:08:38 PM PDT 24
Peak memory 200640 kb
Host smart-32c9733e-50a2-4b66-bb37-e9e4e96d93b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989813527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.989813527
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2781171897
Short name T19
Test name
Test status
Simulation time 6981037708 ps
CPU time 27.38 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:09:05 PM PDT 24
Peak memory 200784 kb
Host smart-7fa68d93-4626-4a8f-8dc0-84f69202a1ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781171897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2781171897
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2591672488
Short name T263
Test name
Test status
Simulation time 155571158 ps
CPU time 1.96 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:45 PM PDT 24
Peak memory 200288 kb
Host smart-501751ff-8abd-41e5-b9d5-7439307151e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591672488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2591672488
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1719801358
Short name T531
Test name
Test status
Simulation time 87151215 ps
CPU time 0.87 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:08:37 PM PDT 24
Peak memory 200416 kb
Host smart-47ad7ff4-75fb-43a7-b838-0e4c3ba7966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719801358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1719801358
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1764944443
Short name T257
Test name
Test status
Simulation time 73316470 ps
CPU time 0.79 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:08:38 PM PDT 24
Peak memory 200208 kb
Host smart-dab5c9ea-3c24-4fb4-9a53-9b7c3bb8aaac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764944443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1764944443
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1563399654
Short name T337
Test name
Test status
Simulation time 1225739263 ps
CPU time 6.06 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:48 PM PDT 24
Peak memory 217816 kb
Host smart-8ea27484-2b38-4772-a4e5-a8f9747cb576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563399654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1563399654
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.595741005
Short name T305
Test name
Test status
Simulation time 249743291 ps
CPU time 1.07 seconds
Started Jul 19 05:08:34 PM PDT 24
Finished Jul 19 05:08:36 PM PDT 24
Peak memory 217528 kb
Host smart-d8ae518c-89b3-4666-85ca-87c404df496f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595741005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.595741005
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1285104190
Short name T518
Test name
Test status
Simulation time 131412753 ps
CPU time 0.82 seconds
Started Jul 19 05:08:38 PM PDT 24
Finished Jul 19 05:08:42 PM PDT 24
Peak memory 200264 kb
Host smart-b5cb75cd-e96e-46c1-9bad-f8cf32d73550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285104190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1285104190
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.479871361
Short name T264
Test name
Test status
Simulation time 800154506 ps
CPU time 4.07 seconds
Started Jul 19 05:08:38 PM PDT 24
Finished Jul 19 05:08:45 PM PDT 24
Peak memory 200724 kb
Host smart-feba9532-c0d1-4eb3-ae7f-519b4e664bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479871361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.479871361
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2493888936
Short name T413
Test name
Test status
Simulation time 137415458 ps
CPU time 1.1 seconds
Started Jul 19 05:08:38 PM PDT 24
Finished Jul 19 05:08:42 PM PDT 24
Peak memory 200464 kb
Host smart-0880fef6-db40-4e00-8d3e-b55844acf295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493888936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2493888936
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.98473766
Short name T240
Test name
Test status
Simulation time 244706085 ps
CPU time 1.68 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:08:40 PM PDT 24
Peak memory 200664 kb
Host smart-410a0e66-377d-4a92-9d40-9ad08c28b914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98473766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.98473766
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2192983198
Short name T99
Test name
Test status
Simulation time 11404379805 ps
CPU time 39.2 seconds
Started Jul 19 05:08:40 PM PDT 24
Finished Jul 19 05:09:22 PM PDT 24
Peak memory 200652 kb
Host smart-dce2061d-e7ef-46a1-9d7f-767f99d66e41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192983198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2192983198
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.304281902
Short name T445
Test name
Test status
Simulation time 305951823 ps
CPU time 2.16 seconds
Started Jul 19 05:08:38 PM PDT 24
Finished Jul 19 05:08:43 PM PDT 24
Peak memory 208688 kb
Host smart-c26e257b-c8a9-462d-8c47-820e2c44b18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304281902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.304281902
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2058885362
Short name T401
Test name
Test status
Simulation time 227119654 ps
CPU time 1.44 seconds
Started Jul 19 05:08:35 PM PDT 24
Finished Jul 19 05:08:37 PM PDT 24
Peak memory 200448 kb
Host smart-73d03daa-7500-4fd7-bd08-270849f660de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058885362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2058885362
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1454461247
Short name T36
Test name
Test status
Simulation time 56954225 ps
CPU time 0.76 seconds
Started Jul 19 05:08:42 PM PDT 24
Finished Jul 19 05:08:47 PM PDT 24
Peak memory 200232 kb
Host smart-b325d957-9443-4bba-ae32-8f4b1689b673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454461247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1454461247
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1838262400
Short name T40
Test name
Test status
Simulation time 2363766063 ps
CPU time 9.21 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:51 PM PDT 24
Peak memory 217852 kb
Host smart-47c09714-dc9f-496f-ba70-7205c0e18c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838262400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1838262400
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1785329166
Short name T182
Test name
Test status
Simulation time 244869926 ps
CPU time 1.06 seconds
Started Jul 19 05:08:35 PM PDT 24
Finished Jul 19 05:08:37 PM PDT 24
Peak memory 217492 kb
Host smart-f356da56-090e-4ad0-8d21-2a911fd343ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785329166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1785329166
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.4217415345
Short name T528
Test name
Test status
Simulation time 104364074 ps
CPU time 0.79 seconds
Started Jul 19 05:08:37 PM PDT 24
Finished Jul 19 05:08:40 PM PDT 24
Peak memory 200180 kb
Host smart-ec5038bd-41ae-45d3-81e8-7de44e61524b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217415345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.4217415345
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.218992861
Short name T254
Test name
Test status
Simulation time 745792887 ps
CPU time 4.05 seconds
Started Jul 19 05:08:37 PM PDT 24
Finished Jul 19 05:08:43 PM PDT 24
Peak memory 200744 kb
Host smart-5c0e8b22-527f-4db6-9abb-b3ac0d507b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218992861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.218992861
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2437351190
Short name T188
Test name
Test status
Simulation time 179985343 ps
CPU time 1.23 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:44 PM PDT 24
Peak memory 200460 kb
Host smart-10714ac9-2cfe-4a48-878a-16edc0eb9aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437351190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2437351190
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3132228705
Short name T252
Test name
Test status
Simulation time 110574185 ps
CPU time 1.31 seconds
Started Jul 19 05:08:38 PM PDT 24
Finished Jul 19 05:08:42 PM PDT 24
Peak memory 200672 kb
Host smart-1c5fbc71-2415-4305-9f06-def8ec52f666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132228705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3132228705
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3145873925
Short name T349
Test name
Test status
Simulation time 3567967306 ps
CPU time 14.83 seconds
Started Jul 19 05:08:36 PM PDT 24
Finished Jul 19 05:08:53 PM PDT 24
Peak memory 208956 kb
Host smart-fe6d22f9-ef06-4fad-a15c-29990b9b9a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145873925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3145873925
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1731354767
Short name T400
Test name
Test status
Simulation time 385615590 ps
CPU time 2.35 seconds
Started Jul 19 05:08:35 PM PDT 24
Finished Jul 19 05:08:38 PM PDT 24
Peak memory 200468 kb
Host smart-fc469302-f72a-4c43-9aad-007631c1161a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731354767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1731354767
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3273800051
Short name T283
Test name
Test status
Simulation time 146951875 ps
CPU time 1.2 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:44 PM PDT 24
Peak memory 200456 kb
Host smart-e0c6967b-5634-43c7-af50-a84d53e70156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273800051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3273800051
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2236799312
Short name T269
Test name
Test status
Simulation time 64701083 ps
CPU time 0.76 seconds
Started Jul 19 05:08:41 PM PDT 24
Finished Jul 19 05:08:46 PM PDT 24
Peak memory 200244 kb
Host smart-c53bf849-ea6c-4f96-b455-b76aa827c869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236799312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2236799312
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2124546919
Short name T31
Test name
Test status
Simulation time 2157882629 ps
CPU time 8.4 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:51 PM PDT 24
Peak memory 217560 kb
Host smart-4577dafe-b780-4f43-89d8-474ebbeb5d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124546919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2124546919
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.743692470
Short name T178
Test name
Test status
Simulation time 244945457 ps
CPU time 1.02 seconds
Started Jul 19 05:08:40 PM PDT 24
Finished Jul 19 05:08:45 PM PDT 24
Peak memory 217484 kb
Host smart-5e322c39-5e8a-422b-b990-5069911bd580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743692470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.743692470
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.802569679
Short name T496
Test name
Test status
Simulation time 199656864 ps
CPU time 0.89 seconds
Started Jul 19 05:08:41 PM PDT 24
Finished Jul 19 05:08:45 PM PDT 24
Peak memory 200260 kb
Host smart-a73f1e74-4bb7-4114-912f-e9b451b74449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802569679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.802569679
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.686532015
Short name T424
Test name
Test status
Simulation time 2143176720 ps
CPU time 7.85 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:51 PM PDT 24
Peak memory 200732 kb
Host smart-068a89c2-5446-49f9-8844-874035b8ba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686532015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.686532015
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3967047788
Short name T95
Test name
Test status
Simulation time 99448323 ps
CPU time 1.03 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:44 PM PDT 24
Peak memory 200376 kb
Host smart-25f145e4-9ab0-4755-bf30-dcac8f80579b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967047788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3967047788
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.333393718
Short name T157
Test name
Test status
Simulation time 120857614 ps
CPU time 1.33 seconds
Started Jul 19 05:08:43 PM PDT 24
Finished Jul 19 05:08:47 PM PDT 24
Peak memory 200668 kb
Host smart-c5bc0945-c399-4a7d-9f8e-52e946b9eb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333393718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.333393718
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1431076849
Short name T176
Test name
Test status
Simulation time 333530252 ps
CPU time 1.83 seconds
Started Jul 19 05:08:40 PM PDT 24
Finished Jul 19 05:08:45 PM PDT 24
Peak memory 200660 kb
Host smart-8e6808c9-e2e2-4b74-8313-9e6dfb80285e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431076849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1431076849
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1005011888
Short name T78
Test name
Test status
Simulation time 140859378 ps
CPU time 1.93 seconds
Started Jul 19 05:08:40 PM PDT 24
Finished Jul 19 05:08:46 PM PDT 24
Peak memory 200488 kb
Host smart-a644c6b9-d281-45f6-8a54-86cca8977a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005011888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1005011888
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.801302855
Short name T201
Test name
Test status
Simulation time 144405467 ps
CPU time 1.2 seconds
Started Jul 19 05:08:40 PM PDT 24
Finished Jul 19 05:08:45 PM PDT 24
Peak memory 200444 kb
Host smart-b4a90308-1ea3-4779-abaa-98ce5274e081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801302855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.801302855
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.389245723
Short name T207
Test name
Test status
Simulation time 62539378 ps
CPU time 0.78 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:44 PM PDT 24
Peak memory 200272 kb
Host smart-c31536dc-dbc9-4102-8e0a-44bc9ac8ced1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389245723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.389245723
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.50410812
Short name T539
Test name
Test status
Simulation time 2377726026 ps
CPU time 8.31 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:51 PM PDT 24
Peak memory 217844 kb
Host smart-30c3f474-eba1-4ba1-979c-b39cba641dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50410812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.50410812
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3393079972
Short name T164
Test name
Test status
Simulation time 244860040 ps
CPU time 1.03 seconds
Started Jul 19 05:08:40 PM PDT 24
Finished Jul 19 05:08:45 PM PDT 24
Peak memory 217436 kb
Host smart-c003e679-cba6-4241-aebb-a71fda58e19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393079972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3393079972
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4182080768
Short name T340
Test name
Test status
Simulation time 87287295 ps
CPU time 0.73 seconds
Started Jul 19 05:08:42 PM PDT 24
Finished Jul 19 05:08:46 PM PDT 24
Peak memory 200256 kb
Host smart-229f11ed-f1b1-4e8e-9aa4-f3bff97b712e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182080768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4182080768
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1571357554
Short name T102
Test name
Test status
Simulation time 804874014 ps
CPU time 4.41 seconds
Started Jul 19 05:08:42 PM PDT 24
Finished Jul 19 05:08:50 PM PDT 24
Peak memory 200692 kb
Host smart-552dda05-1f05-4c31-81d1-3ec0a0aa09e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571357554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1571357554
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3347940848
Short name T309
Test name
Test status
Simulation time 175487182 ps
CPU time 1.33 seconds
Started Jul 19 05:08:40 PM PDT 24
Finished Jul 19 05:08:45 PM PDT 24
Peak memory 200376 kb
Host smart-c348bbbb-bef3-4ad4-beb2-152344736290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347940848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3347940848
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1983758305
Short name T452
Test name
Test status
Simulation time 246624508 ps
CPU time 1.59 seconds
Started Jul 19 05:08:44 PM PDT 24
Finished Jul 19 05:08:49 PM PDT 24
Peak memory 200664 kb
Host smart-71b25fe3-3a2d-4cc9-b3c8-aee879e00d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983758305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1983758305
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2800213010
Short name T370
Test name
Test status
Simulation time 6274128658 ps
CPU time 28.14 seconds
Started Jul 19 05:08:42 PM PDT 24
Finished Jul 19 05:09:14 PM PDT 24
Peak memory 200788 kb
Host smart-28d50291-3598-4b7c-ad17-d0771aa0cef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800213010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2800213010
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1188707290
Short name T450
Test name
Test status
Simulation time 298201005 ps
CPU time 2.09 seconds
Started Jul 19 05:08:42 PM PDT 24
Finished Jul 19 05:08:48 PM PDT 24
Peak memory 208676 kb
Host smart-4f6bdc23-b9bc-4b76-b723-3a0cc1383a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188707290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1188707290
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2458949350
Short name T22
Test name
Test status
Simulation time 86578317 ps
CPU time 0.94 seconds
Started Jul 19 05:08:41 PM PDT 24
Finished Jul 19 05:08:46 PM PDT 24
Peak memory 200416 kb
Host smart-d579e3c8-e816-4f46-b2a0-8f57f6cc9152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458949350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2458949350
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.4074471074
Short name T285
Test name
Test status
Simulation time 72997854 ps
CPU time 0.74 seconds
Started Jul 19 05:08:43 PM PDT 24
Finished Jul 19 05:08:48 PM PDT 24
Peak memory 200264 kb
Host smart-859aab34-e04e-4b7e-8fd4-eb112af83e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074471074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.4074471074
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3200204059
Short name T327
Test name
Test status
Simulation time 2358666041 ps
CPU time 9.58 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:51 PM PDT 24
Peak memory 221812 kb
Host smart-7081e4b0-232d-412f-a1b9-010484d007a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200204059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3200204059
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2006543847
Short name T469
Test name
Test status
Simulation time 244617615 ps
CPU time 1.04 seconds
Started Jul 19 05:08:42 PM PDT 24
Finished Jul 19 05:08:47 PM PDT 24
Peak memory 217444 kb
Host smart-3a94f248-c61e-47de-8129-6174aa19e7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006543847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2006543847
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.982201221
Short name T331
Test name
Test status
Simulation time 114911521 ps
CPU time 0.76 seconds
Started Jul 19 05:08:42 PM PDT 24
Finished Jul 19 05:08:46 PM PDT 24
Peak memory 200232 kb
Host smart-07e609ed-4edd-4389-bd3a-e79bc3dac729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982201221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.982201221
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1749329160
Short name T124
Test name
Test status
Simulation time 1504287664 ps
CPU time 6.13 seconds
Started Jul 19 05:08:43 PM PDT 24
Finished Jul 19 05:08:52 PM PDT 24
Peak memory 200768 kb
Host smart-08e45421-1284-47da-9f93-d27f6eeaab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749329160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1749329160
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4056020637
Short name T522
Test name
Test status
Simulation time 152249781 ps
CPU time 1.17 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:44 PM PDT 24
Peak memory 200440 kb
Host smart-c5dfc10c-76e8-440d-a50d-6a2538495304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056020637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4056020637
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2400217257
Short name T77
Test name
Test status
Simulation time 123827804 ps
CPU time 1.23 seconds
Started Jul 19 05:08:37 PM PDT 24
Finished Jul 19 05:08:41 PM PDT 24
Peak memory 200660 kb
Host smart-97c2c959-24e0-4103-a43c-7415818f1b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400217257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2400217257
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3008011044
Short name T538
Test name
Test status
Simulation time 3409557136 ps
CPU time 14.81 seconds
Started Jul 19 05:08:41 PM PDT 24
Finished Jul 19 05:09:00 PM PDT 24
Peak memory 200788 kb
Host smart-c9ec381c-a34a-4dc0-9fa1-790cf4dc59bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008011044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3008011044
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.745776239
Short name T492
Test name
Test status
Simulation time 342748110 ps
CPU time 2.18 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:44 PM PDT 24
Peak memory 200436 kb
Host smart-bbfc202f-fb94-4bcc-9e89-5d59138841af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745776239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.745776239
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3075540565
Short name T35
Test name
Test status
Simulation time 76828003 ps
CPU time 0.88 seconds
Started Jul 19 05:08:39 PM PDT 24
Finished Jul 19 05:08:43 PM PDT 24
Peak memory 200468 kb
Host smart-2b5fdacb-ec30-44b0-9803-5099db870d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075540565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3075540565
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.4109245554
Short name T96
Test name
Test status
Simulation time 121404017 ps
CPU time 0.86 seconds
Started Jul 19 05:07:48 PM PDT 24
Finished Jul 19 05:07:51 PM PDT 24
Peak memory 200260 kb
Host smart-6867fd08-34c5-4547-801e-3a13c441256f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109245554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.4109245554
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.237679763
Short name T382
Test name
Test status
Simulation time 2340414777 ps
CPU time 8.68 seconds
Started Jul 19 05:07:53 PM PDT 24
Finished Jul 19 05:08:04 PM PDT 24
Peak memory 221832 kb
Host smart-806ff3a0-1bf2-4bd0-9362-c6004d4401d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237679763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.237679763
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3259349996
Short name T92
Test name
Test status
Simulation time 244000826 ps
CPU time 1.05 seconds
Started Jul 19 05:07:50 PM PDT 24
Finished Jul 19 05:07:53 PM PDT 24
Peak memory 217508 kb
Host smart-59801de8-a645-40a0-99f7-eb7d211ec708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259349996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3259349996
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2595784272
Short name T149
Test name
Test status
Simulation time 213942033 ps
CPU time 0.87 seconds
Started Jul 19 05:07:51 PM PDT 24
Finished Jul 19 05:07:54 PM PDT 24
Peak memory 200260 kb
Host smart-c568443b-7073-41dd-a0d6-0c779abe3fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595784272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2595784272
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.4164390301
Short name T174
Test name
Test status
Simulation time 1720380859 ps
CPU time 6.88 seconds
Started Jul 19 05:07:52 PM PDT 24
Finished Jul 19 05:08:01 PM PDT 24
Peak memory 200740 kb
Host smart-4bac1980-4e63-4cdf-a546-f717390e17a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164390301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4164390301
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.416236169
Short name T61
Test name
Test status
Simulation time 16884998518 ps
CPU time 23.71 seconds
Started Jul 19 05:07:52 PM PDT 24
Finished Jul 19 05:08:18 PM PDT 24
Peak memory 221688 kb
Host smart-7cb3a072-dffd-4ef2-abaa-aaf15643a522
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416236169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.416236169
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.882688152
Short name T453
Test name
Test status
Simulation time 155939011 ps
CPU time 1.12 seconds
Started Jul 19 05:07:51 PM PDT 24
Finished Jul 19 05:07:54 PM PDT 24
Peak memory 200432 kb
Host smart-0610964a-496c-4aa3-96e2-c03090cf1548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882688152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.882688152
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3608087674
Short name T343
Test name
Test status
Simulation time 193956627 ps
CPU time 1.51 seconds
Started Jul 19 05:07:51 PM PDT 24
Finished Jul 19 05:07:55 PM PDT 24
Peak memory 200628 kb
Host smart-e85aec83-8b1e-4ffe-a59f-6d84fac9664c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608087674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3608087674
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2207480205
Short name T126
Test name
Test status
Simulation time 9995734506 ps
CPU time 33.11 seconds
Started Jul 19 05:07:52 PM PDT 24
Finished Jul 19 05:08:27 PM PDT 24
Peak memory 209144 kb
Host smart-3d2510f7-da6f-424e-b9c1-bc4089edc070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207480205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2207480205
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.649990882
Short name T49
Test name
Test status
Simulation time 468032495 ps
CPU time 2.8 seconds
Started Jul 19 05:07:49 PM PDT 24
Finished Jul 19 05:07:54 PM PDT 24
Peak memory 200476 kb
Host smart-7bee1b5c-1017-4ae3-9fdd-8244de2e071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649990882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.649990882
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1845975114
Short name T172
Test name
Test status
Simulation time 139823939 ps
CPU time 1.13 seconds
Started Jul 19 05:07:52 PM PDT 24
Finished Jul 19 05:07:56 PM PDT 24
Peak memory 200372 kb
Host smart-a4fd5b88-6d46-4f7a-8c6f-624183f59141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845975114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1845975114
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.345320160
Short name T187
Test name
Test status
Simulation time 62779124 ps
CPU time 0.74 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:08:59 PM PDT 24
Peak memory 200156 kb
Host smart-0e79edb4-9f12-421a-9215-eac0ce5b444b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345320160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.345320160
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.4059149483
Short name T5
Test name
Test status
Simulation time 2173459187 ps
CPU time 8.11 seconds
Started Jul 19 05:08:44 PM PDT 24
Finished Jul 19 05:08:55 PM PDT 24
Peak memory 221796 kb
Host smart-48250bbc-7ecd-436c-bee3-862df5c3efa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059149483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.4059149483
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3141132337
Short name T390
Test name
Test status
Simulation time 244243603 ps
CPU time 1.1 seconds
Started Jul 19 05:08:50 PM PDT 24
Finished Jul 19 05:08:54 PM PDT 24
Peak memory 217584 kb
Host smart-7f816fe9-acc5-4ee3-ac44-f348972ade76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141132337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3141132337
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2847107641
Short name T495
Test name
Test status
Simulation time 142866815 ps
CPU time 0.86 seconds
Started Jul 19 05:08:51 PM PDT 24
Finished Jul 19 05:08:55 PM PDT 24
Peak memory 200264 kb
Host smart-185ae191-12f4-44b2-b550-ac86a67d57a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847107641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2847107641
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.994204836
Short name T307
Test name
Test status
Simulation time 701245242 ps
CPU time 3.68 seconds
Started Jul 19 05:08:48 PM PDT 24
Finished Jul 19 05:08:55 PM PDT 24
Peak memory 200736 kb
Host smart-9cd8bc99-84f6-489b-8099-610bef7b389b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994204836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.994204836
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3165104805
Short name T379
Test name
Test status
Simulation time 180738933 ps
CPU time 1.11 seconds
Started Jul 19 05:08:50 PM PDT 24
Finished Jul 19 05:08:54 PM PDT 24
Peak memory 200448 kb
Host smart-f584a47e-0b31-4d83-a213-5e8d3d48128c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165104805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3165104805
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1712029009
Short name T241
Test name
Test status
Simulation time 262073663 ps
CPU time 1.44 seconds
Started Jul 19 05:08:42 PM PDT 24
Finished Jul 19 05:08:47 PM PDT 24
Peak memory 200660 kb
Host smart-73791379-5ae2-4a79-a200-0dd8612362ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712029009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1712029009
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.91215557
Short name T218
Test name
Test status
Simulation time 8445633833 ps
CPU time 31.07 seconds
Started Jul 19 05:08:45 PM PDT 24
Finished Jul 19 05:09:20 PM PDT 24
Peak memory 209720 kb
Host smart-ef922b75-d89a-43f3-b936-df66f686ea43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91215557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.91215557
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4033463
Short name T355
Test name
Test status
Simulation time 143497369 ps
CPU time 1.72 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:08:58 PM PDT 24
Peak memory 200368 kb
Host smart-900de7d9-22a8-4738-8eaf-8726e99eb9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4033463
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.561987748
Short name T458
Test name
Test status
Simulation time 229112295 ps
CPU time 1.36 seconds
Started Jul 19 05:08:48 PM PDT 24
Finished Jul 19 05:08:53 PM PDT 24
Peak memory 200436 kb
Host smart-2039bc96-fc38-4673-b771-ef601019835c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561987748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.561987748
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2536054280
Short name T146
Test name
Test status
Simulation time 65648055 ps
CPU time 0.85 seconds
Started Jul 19 05:08:51 PM PDT 24
Finished Jul 19 05:08:55 PM PDT 24
Peak memory 200280 kb
Host smart-788ed9de-ad57-4e44-ae38-899eea20bcfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536054280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2536054280
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.41702490
Short name T536
Test name
Test status
Simulation time 2370763072 ps
CPU time 9.66 seconds
Started Jul 19 05:08:48 PM PDT 24
Finished Jul 19 05:09:00 PM PDT 24
Peak memory 217884 kb
Host smart-d2faceea-5837-4c61-b1c7-d79c00aa5d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41702490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.41702490
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2832038211
Short name T375
Test name
Test status
Simulation time 244696405 ps
CPU time 1.06 seconds
Started Jul 19 05:08:49 PM PDT 24
Finished Jul 19 05:08:53 PM PDT 24
Peak memory 217516 kb
Host smart-608f7fe0-6ae9-49c8-9acf-89b8be02352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832038211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2832038211
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1316485076
Short name T12
Test name
Test status
Simulation time 100283121 ps
CPU time 0.83 seconds
Started Jul 19 05:08:49 PM PDT 24
Finished Jul 19 05:08:53 PM PDT 24
Peak memory 200204 kb
Host smart-525499fe-aa2f-49ac-a3c4-3c2c958409de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316485076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1316485076
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.66404370
Short name T184
Test name
Test status
Simulation time 147159995 ps
CPU time 1.23 seconds
Started Jul 19 05:08:49 PM PDT 24
Finished Jul 19 05:08:54 PM PDT 24
Peak memory 200408 kb
Host smart-093f4554-a079-4e58-a14c-9a045b84199c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66404370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.66404370
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3492721721
Short name T529
Test name
Test status
Simulation time 208194199 ps
CPU time 1.5 seconds
Started Jul 19 05:08:50 PM PDT 24
Finished Jul 19 05:08:55 PM PDT 24
Peak memory 200652 kb
Host smart-a30c8cdf-bd31-4289-8804-2863ebaa0ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492721721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3492721721
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3034836906
Short name T301
Test name
Test status
Simulation time 7856292046 ps
CPU time 31.95 seconds
Started Jul 19 05:08:47 PM PDT 24
Finished Jul 19 05:09:22 PM PDT 24
Peak memory 200760 kb
Host smart-b01338f5-218d-4732-93ad-12541794a551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034836906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3034836906
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1095760229
Short name T270
Test name
Test status
Simulation time 426246049 ps
CPU time 2.16 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:09:00 PM PDT 24
Peak memory 208524 kb
Host smart-3e15094e-da70-4245-ac5c-bc8200c00077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095760229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1095760229
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2855843596
Short name T383
Test name
Test status
Simulation time 131244687 ps
CPU time 1.01 seconds
Started Jul 19 05:08:47 PM PDT 24
Finished Jul 19 05:08:51 PM PDT 24
Peak memory 200448 kb
Host smart-a80365ae-af45-4d50-b10a-08088d8b9b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855843596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2855843596
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3666382639
Short name T7
Test name
Test status
Simulation time 69492756 ps
CPU time 0.76 seconds
Started Jul 19 05:08:45 PM PDT 24
Finished Jul 19 05:08:49 PM PDT 24
Peak memory 200240 kb
Host smart-2a934b1e-533e-4993-87cc-567a389014a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666382639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3666382639
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.4125679490
Short name T221
Test name
Test status
Simulation time 1237872370 ps
CPU time 5.74 seconds
Started Jul 19 05:08:48 PM PDT 24
Finished Jul 19 05:08:56 PM PDT 24
Peak memory 217804 kb
Host smart-58fd4bc2-5faf-40b1-883c-2ce2cdb79284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125679490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.4125679490
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.241254381
Short name T193
Test name
Test status
Simulation time 244151329 ps
CPU time 1.02 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:08:59 PM PDT 24
Peak memory 217248 kb
Host smart-ab1248fd-1097-4491-a597-fdaa4649f7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241254381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.241254381
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2277615183
Short name T245
Test name
Test status
Simulation time 169614542 ps
CPU time 0.9 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:08:59 PM PDT 24
Peak memory 200156 kb
Host smart-3b04d81d-ebc0-45e0-8b4e-2db480113458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277615183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2277615183
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.280823449
Short name T90
Test name
Test status
Simulation time 1184379799 ps
CPU time 5.69 seconds
Started Jul 19 05:08:47 PM PDT 24
Finished Jul 19 05:08:56 PM PDT 24
Peak memory 200772 kb
Host smart-b0b54570-3c5b-4db1-8533-c57bac6eaabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280823449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.280823449
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.545780364
Short name T325
Test name
Test status
Simulation time 172245197 ps
CPU time 1.26 seconds
Started Jul 19 05:08:46 PM PDT 24
Finished Jul 19 05:08:50 PM PDT 24
Peak memory 200400 kb
Host smart-16af4212-f7e5-462d-ab29-893286a92271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545780364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.545780364
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2692580554
Short name T489
Test name
Test status
Simulation time 248652422 ps
CPU time 1.57 seconds
Started Jul 19 05:08:48 PM PDT 24
Finished Jul 19 05:08:52 PM PDT 24
Peak memory 200664 kb
Host smart-480da9c9-9089-4be7-9182-8329e81fa831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692580554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2692580554
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2271009226
Short name T426
Test name
Test status
Simulation time 4169932558 ps
CPU time 15.79 seconds
Started Jul 19 05:08:48 PM PDT 24
Finished Jul 19 05:09:07 PM PDT 24
Peak memory 200792 kb
Host smart-4639566b-2f31-4ae8-8943-d800d2a78ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271009226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2271009226
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.19208562
Short name T468
Test name
Test status
Simulation time 547363808 ps
CPU time 2.86 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:09:01 PM PDT 24
Peak memory 200276 kb
Host smart-20537496-e9be-4161-b306-603849937c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19208562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.19208562
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3848402035
Short name T294
Test name
Test status
Simulation time 155330463 ps
CPU time 1.25 seconds
Started Jul 19 05:08:51 PM PDT 24
Finished Jul 19 05:08:55 PM PDT 24
Peak memory 200668 kb
Host smart-33854ef9-fe87-417e-8264-e9e1725a2b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848402035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3848402035
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2911090054
Short name T220
Test name
Test status
Simulation time 64149870 ps
CPU time 0.76 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:00 PM PDT 24
Peak memory 200276 kb
Host smart-89bd6195-a88f-4ed8-a117-18ac3b9ca638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911090054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2911090054
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.921790588
Short name T33
Test name
Test status
Simulation time 1884838710 ps
CPU time 7.3 seconds
Started Jul 19 05:08:48 PM PDT 24
Finished Jul 19 05:08:58 PM PDT 24
Peak memory 229992 kb
Host smart-f7995c31-9822-4233-a751-11765cf541dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921790588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.921790588
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1970828006
Short name T321
Test name
Test status
Simulation time 244232019 ps
CPU time 1.1 seconds
Started Jul 19 05:08:58 PM PDT 24
Finished Jul 19 05:09:03 PM PDT 24
Peak memory 217440 kb
Host smart-3a88eb76-8fc6-4b74-acc0-32626b2c6806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970828006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1970828006
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1117734439
Short name T480
Test name
Test status
Simulation time 84953592 ps
CPU time 0.77 seconds
Started Jul 19 05:08:49 PM PDT 24
Finished Jul 19 05:08:53 PM PDT 24
Peak memory 200260 kb
Host smart-25ce3346-b100-4fba-add7-84dfb10fc018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117734439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1117734439
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3092230903
Short name T502
Test name
Test status
Simulation time 974204184 ps
CPU time 5.23 seconds
Started Jul 19 05:08:50 PM PDT 24
Finished Jul 19 05:08:59 PM PDT 24
Peak memory 200708 kb
Host smart-07484d86-59ef-4a41-9a5d-120d8639f59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092230903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3092230903
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3313636395
Short name T262
Test name
Test status
Simulation time 152404182 ps
CPU time 1.12 seconds
Started Jul 19 05:08:50 PM PDT 24
Finished Jul 19 05:08:54 PM PDT 24
Peak memory 200460 kb
Host smart-1a042972-8e19-4764-a43e-05acfa080f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313636395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3313636395
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.857661746
Short name T169
Test name
Test status
Simulation time 230190317 ps
CPU time 1.49 seconds
Started Jul 19 05:08:47 PM PDT 24
Finished Jul 19 05:08:51 PM PDT 24
Peak memory 200664 kb
Host smart-27e95b4f-ec87-431a-9b1c-34a9a5911a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857661746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.857661746
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1689242843
Short name T73
Test name
Test status
Simulation time 8530307370 ps
CPU time 30.94 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:09:29 PM PDT 24
Peak memory 200736 kb
Host smart-b2d4d3c5-e319-476f-81f4-a6820014e2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689242843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1689242843
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1220262879
Short name T535
Test name
Test status
Simulation time 472997855 ps
CPU time 2.63 seconds
Started Jul 19 05:08:46 PM PDT 24
Finished Jul 19 05:08:52 PM PDT 24
Peak memory 200464 kb
Host smart-536ec717-400d-4194-aa4c-8b54f4e059d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220262879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1220262879
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3724231021
Short name T280
Test name
Test status
Simulation time 154276885 ps
CPU time 1.28 seconds
Started Jul 19 05:08:49 PM PDT 24
Finished Jul 19 05:08:54 PM PDT 24
Peak memory 200624 kb
Host smart-5be1ff83-09b7-4216-ae05-63ad64a19367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724231021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3724231021
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3144290358
Short name T432
Test name
Test status
Simulation time 72872504 ps
CPU time 0.8 seconds
Started Jul 19 05:08:59 PM PDT 24
Finished Jul 19 05:09:03 PM PDT 24
Peak memory 200268 kb
Host smart-d1f63c1f-5356-4b9e-acda-fb815a2789e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144290358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3144290358
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1233714266
Short name T509
Test name
Test status
Simulation time 2175548437 ps
CPU time 8.09 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:08 PM PDT 24
Peak memory 221788 kb
Host smart-13a89601-3453-4228-9bac-becd7ced3d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233714266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1233714266
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3026821276
Short name T23
Test name
Test status
Simulation time 244913170 ps
CPU time 1.18 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:09:00 PM PDT 24
Peak memory 217572 kb
Host smart-e88a58b4-4d9e-496f-8170-edf152a5e813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026821276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3026821276
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2884922629
Short name T214
Test name
Test status
Simulation time 105857905 ps
CPU time 0.82 seconds
Started Jul 19 05:08:57 PM PDT 24
Finished Jul 19 05:09:02 PM PDT 24
Peak memory 200248 kb
Host smart-f897843c-75fd-4b98-be07-fbc78a016965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884922629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2884922629
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2059792921
Short name T320
Test name
Test status
Simulation time 1976249024 ps
CPU time 6.84 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:08 PM PDT 24
Peak memory 200728 kb
Host smart-9f8f3ce3-d968-44f8-a7cd-b4f9cb44756b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059792921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2059792921
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.395318476
Short name T300
Test name
Test status
Simulation time 166492889 ps
CPU time 1.3 seconds
Started Jul 19 05:09:00 PM PDT 24
Finished Jul 19 05:09:04 PM PDT 24
Peak memory 200452 kb
Host smart-2b89badc-3b25-465d-8fbc-e757c804abae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395318476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.395318476
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1845956578
Short name T150
Test name
Test status
Simulation time 109358046 ps
CPU time 1.26 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:01 PM PDT 24
Peak memory 200656 kb
Host smart-256cbd0b-b5fc-4847-94b6-1153e8392b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845956578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1845956578
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.859863679
Short name T428
Test name
Test status
Simulation time 5029071519 ps
CPU time 21.6 seconds
Started Jul 19 05:08:59 PM PDT 24
Finished Jul 19 05:09:24 PM PDT 24
Peak memory 200784 kb
Host smart-e7c87663-b1bf-4e9d-8980-3a177b1b0ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859863679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.859863679
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1697094389
Short name T411
Test name
Test status
Simulation time 382656196 ps
CPU time 2.57 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:09:02 PM PDT 24
Peak memory 200488 kb
Host smart-330344d2-d8b3-4c05-b27a-77ecd7f53b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697094389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1697094389
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.367727508
Short name T318
Test name
Test status
Simulation time 169404281 ps
CPU time 1.16 seconds
Started Jul 19 05:08:54 PM PDT 24
Finished Jul 19 05:08:56 PM PDT 24
Peak memory 200424 kb
Host smart-9606210f-9ce9-4e47-9046-494ae3008f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367727508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.367727508
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1912225511
Short name T456
Test name
Test status
Simulation time 60371187 ps
CPU time 0.75 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:01 PM PDT 24
Peak memory 200272 kb
Host smart-3e14d4ee-0491-4166-97e5-9c6be31e85b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912225511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1912225511
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3205763850
Short name T204
Test name
Test status
Simulation time 1220881926 ps
CPU time 5.71 seconds
Started Jul 19 05:08:58 PM PDT 24
Finished Jul 19 05:09:08 PM PDT 24
Peak memory 217408 kb
Host smart-a57b7aa3-2685-47d9-b13b-39bbefdade8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205763850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3205763850
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4089018431
Short name T347
Test name
Test status
Simulation time 243375984 ps
CPU time 1.16 seconds
Started Jul 19 05:08:57 PM PDT 24
Finished Jul 19 05:09:03 PM PDT 24
Peak memory 217540 kb
Host smart-a29f0e12-8b9a-4a03-a379-2f3f4ee5092f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089018431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4089018431
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3093641950
Short name T163
Test name
Test status
Simulation time 134659480 ps
CPU time 0.88 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:08:59 PM PDT 24
Peak memory 200272 kb
Host smart-59ae2273-66b4-4887-8fb6-4cc58ae20ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093641950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3093641950
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.515496631
Short name T415
Test name
Test status
Simulation time 1428116672 ps
CPU time 5.75 seconds
Started Jul 19 05:08:54 PM PDT 24
Finished Jul 19 05:09:02 PM PDT 24
Peak memory 200808 kb
Host smart-9c30f4ad-9166-4768-bd26-f3c058c758c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515496631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.515496631
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3087825350
Short name T443
Test name
Test status
Simulation time 134242374 ps
CPU time 1.23 seconds
Started Jul 19 05:08:59 PM PDT 24
Finished Jul 19 05:09:03 PM PDT 24
Peak memory 200448 kb
Host smart-713471f4-e345-4316-b8bd-3c1bfbc15993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087825350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3087825350
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.4057544051
Short name T335
Test name
Test status
Simulation time 191116989 ps
CPU time 1.39 seconds
Started Jul 19 05:08:58 PM PDT 24
Finished Jul 19 05:09:03 PM PDT 24
Peak memory 200632 kb
Host smart-facee27c-a965-4fdd-a52a-fa48cd5f7a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057544051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.4057544051
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.4026939260
Short name T372
Test name
Test status
Simulation time 6264739304 ps
CPU time 27.73 seconds
Started Jul 19 05:08:54 PM PDT 24
Finished Jul 19 05:09:24 PM PDT 24
Peak memory 200764 kb
Host smart-2c59ff9e-598b-476d-b583-870b2cb8be0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026939260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.4026939260
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.480517103
Short name T291
Test name
Test status
Simulation time 120483826 ps
CPU time 1.54 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:01 PM PDT 24
Peak memory 200476 kb
Host smart-285b01fb-137e-4a66-967c-0932d9b8500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480517103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.480517103
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.631718576
Short name T351
Test name
Test status
Simulation time 127991238 ps
CPU time 1.05 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:02 PM PDT 24
Peak memory 200468 kb
Host smart-237237f0-e22e-4641-ac9b-ad7297bc43ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631718576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.631718576
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2355031475
Short name T431
Test name
Test status
Simulation time 79355892 ps
CPU time 0.76 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:08:59 PM PDT 24
Peak memory 200268 kb
Host smart-12be223e-72eb-4baf-b361-c311cb628ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355031475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2355031475
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.79134213
Short name T239
Test name
Test status
Simulation time 244246797 ps
CPU time 1.12 seconds
Started Jul 19 05:08:53 PM PDT 24
Finished Jul 19 05:08:56 PM PDT 24
Peak memory 217496 kb
Host smart-6a4e7238-ad06-45ba-8b97-6c791e7709b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79134213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.79134213
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3463126708
Short name T13
Test name
Test status
Simulation time 106610269 ps
CPU time 0.76 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:09:00 PM PDT 24
Peak memory 200248 kb
Host smart-c4367453-9439-480c-8ad8-e63fca045fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463126708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3463126708
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.4280708094
Short name T360
Test name
Test status
Simulation time 858116571 ps
CPU time 4.58 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:09:03 PM PDT 24
Peak memory 200644 kb
Host smart-7b311ede-93e9-4c50-a631-f427f1d70beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280708094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.4280708094
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2121624821
Short name T217
Test name
Test status
Simulation time 170690686 ps
CPU time 1.2 seconds
Started Jul 19 05:08:58 PM PDT 24
Finished Jul 19 05:09:03 PM PDT 24
Peak memory 200428 kb
Host smart-bbabc6b3-7d13-4d1c-b3be-55c6d93de35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121624821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2121624821
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.4119048195
Short name T328
Test name
Test status
Simulation time 126869017 ps
CPU time 1.25 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:08:58 PM PDT 24
Peak memory 200672 kb
Host smart-3c8d2585-4032-4028-9fb2-e420256711a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119048195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4119048195
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3787927765
Short name T261
Test name
Test status
Simulation time 13599546366 ps
CPU time 49.33 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:09:48 PM PDT 24
Peak memory 200828 kb
Host smart-ec10f871-2acb-437e-9608-785eb79fd992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787927765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3787927765
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.63351528
Short name T499
Test name
Test status
Simulation time 269530976 ps
CPU time 1.83 seconds
Started Jul 19 05:08:57 PM PDT 24
Finished Jul 19 05:09:03 PM PDT 24
Peak memory 200480 kb
Host smart-d6a5e671-e102-4141-a41f-756b1f3faf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63351528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.63351528
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.448387989
Short name T222
Test name
Test status
Simulation time 146279889 ps
CPU time 1.29 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:01 PM PDT 24
Peak memory 200452 kb
Host smart-e65f1d8a-1de9-4202-873b-61f2e7b3a558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448387989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.448387989
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2382588803
Short name T59
Test name
Test status
Simulation time 74272589 ps
CPU time 0.84 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:08:58 PM PDT 24
Peak memory 200272 kb
Host smart-808f33c3-9226-4602-b20e-038b4ddb38a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382588803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2382588803
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.754402040
Short name T527
Test name
Test status
Simulation time 1895421137 ps
CPU time 7.51 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:07 PM PDT 24
Peak memory 221528 kb
Host smart-81d7746f-91fd-4953-af53-f6937ee29423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754402040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.754402040
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1944245669
Short name T364
Test name
Test status
Simulation time 244606793 ps
CPU time 1.03 seconds
Started Jul 19 05:08:59 PM PDT 24
Finished Jul 19 05:09:03 PM PDT 24
Peak memory 217568 kb
Host smart-2fa7e487-6f06-4965-9ec3-4181d69cb44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944245669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1944245669
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.372370598
Short name T532
Test name
Test status
Simulation time 212864562 ps
CPU time 0.88 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:01 PM PDT 24
Peak memory 200272 kb
Host smart-7c87cd87-6c6a-4450-b6db-9db86bd695ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372370598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.372370598
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1179428657
Short name T457
Test name
Test status
Simulation time 1058253551 ps
CPU time 5.36 seconds
Started Jul 19 05:08:57 PM PDT 24
Finished Jul 19 05:09:06 PM PDT 24
Peak memory 200736 kb
Host smart-7da4b31b-4044-44d5-827e-6545f584df2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179428657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1179428657
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1726810483
Short name T148
Test name
Test status
Simulation time 101114976 ps
CPU time 1.07 seconds
Started Jul 19 05:08:55 PM PDT 24
Finished Jul 19 05:08:59 PM PDT 24
Peak memory 200388 kb
Host smart-694d0e12-d4ab-4390-825e-bc14a144ec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726810483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1726810483
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2972309283
Short name T462
Test name
Test status
Simulation time 114823855 ps
CPU time 1.25 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:01 PM PDT 24
Peak memory 200648 kb
Host smart-2e749c75-58ee-4348-94c8-d6db90dd8676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972309283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2972309283
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1897667745
Short name T80
Test name
Test status
Simulation time 5949362929 ps
CPU time 25.74 seconds
Started Jul 19 05:09:00 PM PDT 24
Finished Jul 19 05:09:28 PM PDT 24
Peak memory 209024 kb
Host smart-a5d37dd8-c4d2-4f0b-8323-ca3f1e2dd799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897667745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1897667745
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3818550451
Short name T161
Test name
Test status
Simulation time 483330985 ps
CPU time 2.92 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:02 PM PDT 24
Peak memory 200476 kb
Host smart-7fc0bce8-1cee-40fa-9a8a-a2036b486dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818550451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3818550451
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.329110737
Short name T226
Test name
Test status
Simulation time 235027897 ps
CPU time 1.46 seconds
Started Jul 19 05:08:56 PM PDT 24
Finished Jul 19 05:09:01 PM PDT 24
Peak memory 200660 kb
Host smart-bcf84190-e4d2-4127-85ab-1ec7fa3a7abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329110737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.329110737
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3203619493
Short name T175
Test name
Test status
Simulation time 68736131 ps
CPU time 0.75 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:10 PM PDT 24
Peak memory 200232 kb
Host smart-ee818296-a1c8-4720-991d-c3742cf9c554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203619493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3203619493
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4114183785
Short name T28
Test name
Test status
Simulation time 1226796684 ps
CPU time 5.62 seconds
Started Jul 19 05:09:05 PM PDT 24
Finished Jul 19 05:09:13 PM PDT 24
Peak memory 221764 kb
Host smart-5c67678f-2e62-426d-b4c7-57e366927447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114183785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4114183785
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3264408522
Short name T242
Test name
Test status
Simulation time 244541390 ps
CPU time 1.07 seconds
Started Jul 19 05:09:17 PM PDT 24
Finished Jul 19 05:09:22 PM PDT 24
Peak memory 217540 kb
Host smart-bbc1051e-f314-40a3-851b-34e72b5e38b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264408522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3264408522
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4175446120
Short name T219
Test name
Test status
Simulation time 174487413 ps
CPU time 0.89 seconds
Started Jul 19 05:09:09 PM PDT 24
Finished Jul 19 05:09:13 PM PDT 24
Peak memory 200236 kb
Host smart-ba1f02a8-3fdc-4a82-9493-e06a0c9b0e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175446120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4175446120
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.290405293
Short name T514
Test name
Test status
Simulation time 1657755163 ps
CPU time 6.64 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:13 PM PDT 24
Peak memory 200732 kb
Host smart-35f3191f-3e88-4ebf-a664-d075cae14887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290405293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.290405293
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1945675895
Short name T145
Test name
Test status
Simulation time 104665847 ps
CPU time 1.1 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:11 PM PDT 24
Peak memory 200468 kb
Host smart-4b767753-b62d-4d60-abc7-03ee41cf000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945675895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1945675895
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3191992443
Short name T504
Test name
Test status
Simulation time 195581344 ps
CPU time 1.36 seconds
Started Jul 19 05:09:08 PM PDT 24
Finished Jul 19 05:09:13 PM PDT 24
Peak memory 200664 kb
Host smart-01ebf785-83bf-4dcb-a6a0-e53d0577a813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191992443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3191992443
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1644018453
Short name T471
Test name
Test status
Simulation time 547460418 ps
CPU time 2.5 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200708 kb
Host smart-45492f88-c319-4e65-bd3a-5bb536f2e5ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644018453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1644018453
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3283112128
Short name T498
Test name
Test status
Simulation time 279911336 ps
CPU time 1.87 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200436 kb
Host smart-433679e8-fc8e-4e11-b108-f2ac3be31ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283112128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3283112128
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2715943402
Short name T195
Test name
Test status
Simulation time 176029969 ps
CPU time 1.37 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200572 kb
Host smart-c7ebecdd-6c83-41b5-98ac-35973c58ef08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715943402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2715943402
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2617208781
Short name T393
Test name
Test status
Simulation time 63068128 ps
CPU time 0.78 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200280 kb
Host smart-8ff927f1-5cb1-4dd4-8bd5-c886615b7211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617208781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2617208781
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2637680456
Short name T470
Test name
Test status
Simulation time 1897552865 ps
CPU time 6.92 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:17 PM PDT 24
Peak memory 217776 kb
Host smart-11761f2d-7028-4468-a947-c602251d3ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637680456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2637680456
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3473483831
Short name T494
Test name
Test status
Simulation time 244656176 ps
CPU time 1.06 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:10 PM PDT 24
Peak memory 217528 kb
Host smart-e225825a-48bf-4745-bd37-ceae854bfc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473483831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3473483831
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.12744851
Short name T249
Test name
Test status
Simulation time 97492280 ps
CPU time 0.75 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:06 PM PDT 24
Peak memory 200276 kb
Host smart-aa496b5f-ce40-488e-a635-5aef6ddf3514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12744851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.12744851
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2379562723
Short name T358
Test name
Test status
Simulation time 1263119471 ps
CPU time 4.94 seconds
Started Jul 19 05:09:05 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200692 kb
Host smart-81fa6e31-8e8b-4c0a-9e68-aab8e2e24152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379562723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2379562723
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3721498308
Short name T380
Test name
Test status
Simulation time 115858675 ps
CPU time 1.16 seconds
Started Jul 19 05:09:05 PM PDT 24
Finished Jul 19 05:09:10 PM PDT 24
Peak memory 200440 kb
Host smart-882727d5-262d-4090-90a2-92d6f20f81bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721498308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3721498308
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1325667304
Short name T425
Test name
Test status
Simulation time 109405689 ps
CPU time 1.13 seconds
Started Jul 19 05:09:09 PM PDT 24
Finished Jul 19 05:09:14 PM PDT 24
Peak memory 200632 kb
Host smart-b6c2eb99-256b-438e-8932-baed531ea873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325667304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1325667304
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2609194203
Short name T233
Test name
Test status
Simulation time 507321731 ps
CPU time 2.68 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:13 PM PDT 24
Peak memory 200460 kb
Host smart-51134561-2b9f-428d-8f1c-c15d473e6039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609194203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2609194203
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1603187631
Short name T475
Test name
Test status
Simulation time 102120201 ps
CPU time 1.17 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:07 PM PDT 24
Peak memory 200472 kb
Host smart-46c3189f-703c-4bec-b66a-37a80579e3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603187631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1603187631
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1738341289
Short name T399
Test name
Test status
Simulation time 60163713 ps
CPU time 0.73 seconds
Started Jul 19 05:08:02 PM PDT 24
Finished Jul 19 05:08:04 PM PDT 24
Peak memory 200260 kb
Host smart-f6eab008-1255-491c-bd26-0f6a3efca461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738341289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1738341289
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.409243388
Short name T339
Test name
Test status
Simulation time 1890796398 ps
CPU time 8.8 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:19 PM PDT 24
Peak memory 221704 kb
Host smart-fcc6792b-472e-4d95-9719-ffc57b37e35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409243388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.409243388
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2974820433
Short name T479
Test name
Test status
Simulation time 244124261 ps
CPU time 1.13 seconds
Started Jul 19 05:08:03 PM PDT 24
Finished Jul 19 05:08:05 PM PDT 24
Peak memory 217564 kb
Host smart-aa878757-b9b6-47db-a50e-d3764ccb6882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974820433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2974820433
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3753782080
Short name T167
Test name
Test status
Simulation time 153938797 ps
CPU time 0.84 seconds
Started Jul 19 05:08:00 PM PDT 24
Finished Jul 19 05:08:01 PM PDT 24
Peak memory 200232 kb
Host smart-cbed9537-7bdc-47fd-ae17-27ea8a7fee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753782080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3753782080
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.913102817
Short name T290
Test name
Test status
Simulation time 2117342559 ps
CPU time 7.91 seconds
Started Jul 19 05:08:04 PM PDT 24
Finished Jul 19 05:08:13 PM PDT 24
Peak memory 200700 kb
Host smart-3fde1e86-9053-4ff5-85ca-21c2617df9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913102817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.913102817
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1320891303
Short name T62
Test name
Test status
Simulation time 16534747612 ps
CPU time 26.83 seconds
Started Jul 19 05:08:03 PM PDT 24
Finished Jul 19 05:08:32 PM PDT 24
Peak memory 217732 kb
Host smart-10c75851-6dda-4df6-8bcc-de9aee2f3aa9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320891303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1320891303
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1577634169
Short name T1
Test name
Test status
Simulation time 110037839 ps
CPU time 1.05 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:10 PM PDT 24
Peak memory 200456 kb
Host smart-02fad6bc-76ab-46d4-9266-2e3d59f02815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577634169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1577634169
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2763819841
Short name T246
Test name
Test status
Simulation time 194574279 ps
CPU time 1.45 seconds
Started Jul 19 05:07:50 PM PDT 24
Finished Jul 19 05:07:54 PM PDT 24
Peak memory 200632 kb
Host smart-367af283-1516-45ca-b347-23b86cf23c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763819841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2763819841
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3473994810
Short name T243
Test name
Test status
Simulation time 322868798 ps
CPU time 2 seconds
Started Jul 19 05:08:00 PM PDT 24
Finished Jul 19 05:08:03 PM PDT 24
Peak memory 200616 kb
Host smart-a48556f4-9f0a-4a15-9f9c-84305c58e233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473994810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3473994810
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3328542948
Short name T235
Test name
Test status
Simulation time 147611349 ps
CPU time 1.83 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:13 PM PDT 24
Peak memory 200476 kb
Host smart-884df352-8dc5-4ad3-9ad6-5d175cee4d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328542948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3328542948
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.4262433194
Short name T464
Test name
Test status
Simulation time 218820425 ps
CPU time 1.35 seconds
Started Jul 19 05:08:02 PM PDT 24
Finished Jul 19 05:08:05 PM PDT 24
Peak memory 200464 kb
Host smart-deaf2e4f-e3b9-4703-bf82-804a7bec1488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262433194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4262433194
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1429519898
Short name T225
Test name
Test status
Simulation time 54901351 ps
CPU time 0.72 seconds
Started Jul 19 05:09:05 PM PDT 24
Finished Jul 19 05:09:09 PM PDT 24
Peak memory 200284 kb
Host smart-d1609dc3-c050-4264-bafc-1c7f903b9287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429519898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1429519898
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3698783543
Short name T378
Test name
Test status
Simulation time 1227994191 ps
CPU time 5.77 seconds
Started Jul 19 05:09:10 PM PDT 24
Finished Jul 19 05:09:19 PM PDT 24
Peak memory 221772 kb
Host smart-27139f4c-6ff3-4dd0-8957-7cb4658c7dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698783543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3698783543
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.712449241
Short name T165
Test name
Test status
Simulation time 244201076 ps
CPU time 1.08 seconds
Started Jul 19 05:09:08 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 217440 kb
Host smart-1793c28f-59b3-4b8e-a9eb-22414fef2c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712449241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.712449241
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2312233427
Short name T296
Test name
Test status
Simulation time 214369629 ps
CPU time 0.92 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:11 PM PDT 24
Peak memory 200272 kb
Host smart-c24779fc-7473-40bf-a759-2652fb8dc88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312233427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2312233427
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2599530789
Short name T88
Test name
Test status
Simulation time 1412831363 ps
CPU time 5.55 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:16 PM PDT 24
Peak memory 200688 kb
Host smart-90cf0b01-90b9-428c-bf4f-8a10d0dcfe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599530789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2599530789
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2415487012
Short name T9
Test name
Test status
Simulation time 155814365 ps
CPU time 1.14 seconds
Started Jul 19 05:09:08 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200472 kb
Host smart-187f5fa6-6696-4592-8692-d63e39ebb4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415487012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2415487012
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1148679234
Short name T230
Test name
Test status
Simulation time 250691176 ps
CPU time 1.56 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:11 PM PDT 24
Peak memory 200628 kb
Host smart-3edc6983-ef1d-40f8-90c9-ec171278027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148679234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1148679234
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.826585599
Short name T510
Test name
Test status
Simulation time 3271384007 ps
CPU time 16.06 seconds
Started Jul 19 05:09:15 PM PDT 24
Finished Jul 19 05:09:34 PM PDT 24
Peak memory 200752 kb
Host smart-0b365e97-fb02-47ce-b452-9f5380af3d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826585599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.826585599
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1031479483
Short name T524
Test name
Test status
Simulation time 465040696 ps
CPU time 2.51 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:09 PM PDT 24
Peak memory 200460 kb
Host smart-9961e511-a23e-471f-8db0-3aefbb0b1553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031479483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1031479483
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1977937482
Short name T248
Test name
Test status
Simulation time 112235877 ps
CPU time 1.02 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:11 PM PDT 24
Peak memory 200460 kb
Host smart-14b784d9-a28b-4df1-a84b-3b2e93522ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977937482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1977937482
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2781960343
Short name T409
Test name
Test status
Simulation time 55870194 ps
CPU time 0.74 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:11 PM PDT 24
Peak memory 200268 kb
Host smart-262ad71b-c752-43d8-b720-31571578e482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781960343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2781960343
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1869643844
Short name T181
Test name
Test status
Simulation time 1229281590 ps
CPU time 6.2 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:16 PM PDT 24
Peak memory 229948 kb
Host smart-23230191-332c-4e58-a4b3-a35a7c1fc1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869643844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1869643844
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2766307974
Short name T138
Test name
Test status
Simulation time 244485403 ps
CPU time 1.08 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:07 PM PDT 24
Peak memory 217500 kb
Host smart-d7fd351d-0f07-4db2-9953-cc919aa93e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766307974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2766307974
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.641403215
Short name T278
Test name
Test status
Simulation time 115827859 ps
CPU time 0.78 seconds
Started Jul 19 05:09:05 PM PDT 24
Finished Jul 19 05:09:08 PM PDT 24
Peak memory 200276 kb
Host smart-dfcc4bda-3651-4d5f-b43c-7b346b3817ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641403215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.641403215
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.4110701604
Short name T437
Test name
Test status
Simulation time 1507210898 ps
CPU time 6.25 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:16 PM PDT 24
Peak memory 200708 kb
Host smart-5938e5bb-c82e-474b-af7b-7b3a1cfcaafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110701604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.4110701604
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.804849147
Short name T486
Test name
Test status
Simulation time 156326152 ps
CPU time 1.19 seconds
Started Jul 19 05:09:08 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200452 kb
Host smart-2b7ac68d-7951-444b-99d4-c2b9052d9175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804849147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.804849147
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.632189890
Short name T490
Test name
Test status
Simulation time 199695499 ps
CPU time 1.41 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200588 kb
Host smart-4dc925f5-6c00-49a3-afbc-74869fe41c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632189890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.632189890
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3239216514
Short name T196
Test name
Test status
Simulation time 1417283691 ps
CPU time 6.77 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:17 PM PDT 24
Peak memory 217068 kb
Host smart-af6172e2-6f60-493b-ad79-5b681e7980c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239216514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3239216514
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1817584485
Short name T356
Test name
Test status
Simulation time 359953156 ps
CPU time 2.07 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200484 kb
Host smart-18ece8ce-e76e-463b-b287-c2680426ffb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817584485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1817584485
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1087093495
Short name T434
Test name
Test status
Simulation time 101659985 ps
CPU time 0.97 seconds
Started Jul 19 05:09:08 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200468 kb
Host smart-6b7663f3-fce1-49f9-bf64-12d125916381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087093495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1087093495
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2179208153
Short name T388
Test name
Test status
Simulation time 64956365 ps
CPU time 0.76 seconds
Started Jul 19 05:09:05 PM PDT 24
Finished Jul 19 05:09:08 PM PDT 24
Peak memory 200208 kb
Host smart-d8f8e808-e62b-419f-9785-babc12501087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179208153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2179208153
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3715922302
Short name T229
Test name
Test status
Simulation time 1899422294 ps
CPU time 7.38 seconds
Started Jul 19 05:09:08 PM PDT 24
Finished Jul 19 05:09:19 PM PDT 24
Peak memory 217824 kb
Host smart-19181394-496f-41a8-9c2a-40089fbf831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715922302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3715922302
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1914438783
Short name T183
Test name
Test status
Simulation time 244070659 ps
CPU time 1.17 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:07 PM PDT 24
Peak memory 217488 kb
Host smart-863063f9-81e5-4c3b-8ee1-cc6a06f46e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914438783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1914438783
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1774187699
Short name T3
Test name
Test status
Simulation time 154208310 ps
CPU time 0.84 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:06 PM PDT 24
Peak memory 200240 kb
Host smart-ff461d66-5c4f-4850-a147-f8fa27872968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774187699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1774187699
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2236884590
Short name T274
Test name
Test status
Simulation time 1122329786 ps
CPU time 5.73 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200744 kb
Host smart-578cd242-916d-48fa-9430-c58e2b582211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236884590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2236884590
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1395053333
Short name T153
Test name
Test status
Simulation time 140569680 ps
CPU time 1.09 seconds
Started Jul 19 05:09:05 PM PDT 24
Finished Jul 19 05:09:09 PM PDT 24
Peak memory 200424 kb
Host smart-9f22494b-6a52-46a7-b768-9142e2769ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395053333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1395053333
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2152250095
Short name T389
Test name
Test status
Simulation time 114953422 ps
CPU time 1.21 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:06 PM PDT 24
Peak memory 200708 kb
Host smart-9dbd4f3c-44aa-4e79-8410-3e524d4eb34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152250095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2152250095
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2185172878
Short name T530
Test name
Test status
Simulation time 393448802 ps
CPU time 1.94 seconds
Started Jul 19 05:09:05 PM PDT 24
Finished Jul 19 05:09:11 PM PDT 24
Peak memory 200616 kb
Host smart-951ec05c-989e-45bd-9127-27c45aae3589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185172878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2185172878
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3214190508
Short name T306
Test name
Test status
Simulation time 378359517 ps
CPU time 2.48 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:13 PM PDT 24
Peak memory 200436 kb
Host smart-5411ac00-c150-4ea8-9169-c4e677159dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214190508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3214190508
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3550758202
Short name T295
Test name
Test status
Simulation time 248356119 ps
CPU time 1.43 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:11 PM PDT 24
Peak memory 200696 kb
Host smart-df55db5f-f6b5-4bbb-b16c-a17571ced938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550758202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3550758202
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3967018727
Short name T537
Test name
Test status
Simulation time 63497284 ps
CPU time 0.72 seconds
Started Jul 19 05:09:18 PM PDT 24
Finished Jul 19 05:09:22 PM PDT 24
Peak memory 200268 kb
Host smart-9ca5b385-43a0-413f-9674-f66a58afcf7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967018727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3967018727
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2000157071
Short name T414
Test name
Test status
Simulation time 1882917708 ps
CPU time 7.56 seconds
Started Jul 19 05:09:11 PM PDT 24
Finished Jul 19 05:09:21 PM PDT 24
Peak memory 216920 kb
Host smart-99856af9-7edb-4290-92a7-f64c209fdf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000157071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2000157071
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3981438923
Short name T332
Test name
Test status
Simulation time 244661106 ps
CPU time 1.07 seconds
Started Jul 19 05:09:19 PM PDT 24
Finished Jul 19 05:09:24 PM PDT 24
Peak memory 217552 kb
Host smart-5b386ea0-7ad2-4996-adb5-628c46004161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981438923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3981438923
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1268842746
Short name T18
Test name
Test status
Simulation time 108980849 ps
CPU time 0.79 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:11 PM PDT 24
Peak memory 200272 kb
Host smart-982ae7de-b632-4b01-8b6c-4607b0f09973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268842746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1268842746
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3293697650
Short name T103
Test name
Test status
Simulation time 1568915333 ps
CPU time 6.21 seconds
Started Jul 19 05:09:04 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200720 kb
Host smart-ffd8249b-457b-4525-b754-2a65b63201e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293697650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3293697650
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2097534288
Short name T177
Test name
Test status
Simulation time 102540887 ps
CPU time 0.97 seconds
Started Jul 19 05:09:05 PM PDT 24
Finished Jul 19 05:09:08 PM PDT 24
Peak memory 200400 kb
Host smart-3d4bc223-99af-4c25-b3ce-eb808d6a79e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097534288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2097534288
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3268901161
Short name T467
Test name
Test status
Simulation time 121037691 ps
CPU time 1.16 seconds
Started Jul 19 05:09:06 PM PDT 24
Finished Jul 19 05:09:10 PM PDT 24
Peak memory 200668 kb
Host smart-96eb93e4-0e1b-4bb9-874a-cde3ac457962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268901161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3268901161
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1124807332
Short name T404
Test name
Test status
Simulation time 2724794792 ps
CPU time 13.31 seconds
Started Jul 19 05:09:12 PM PDT 24
Finished Jul 19 05:09:28 PM PDT 24
Peak memory 200792 kb
Host smart-1f5e4df6-27b5-45c0-93f5-a7cb2d47ee79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124807332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1124807332
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4044820457
Short name T361
Test name
Test status
Simulation time 278738844 ps
CPU time 1.94 seconds
Started Jul 19 05:09:12 PM PDT 24
Finished Jul 19 05:09:16 PM PDT 24
Peak memory 200472 kb
Host smart-0b8fa493-95ad-4831-bb76-b1a287326276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044820457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4044820457
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1115070116
Short name T362
Test name
Test status
Simulation time 119063791 ps
CPU time 1.05 seconds
Started Jul 19 05:09:07 PM PDT 24
Finished Jul 19 05:09:12 PM PDT 24
Peak memory 200392 kb
Host smart-f3406723-153e-4226-a31b-1eb40c57075a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115070116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1115070116
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.166491083
Short name T202
Test name
Test status
Simulation time 76484787 ps
CPU time 0.79 seconds
Started Jul 19 05:09:15 PM PDT 24
Finished Jul 19 05:09:19 PM PDT 24
Peak memory 200272 kb
Host smart-aa9fec63-fdc9-4996-b1d3-652f7108dcf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166491083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.166491083
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2674645464
Short name T205
Test name
Test status
Simulation time 1233128901 ps
CPU time 5.78 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:23 PM PDT 24
Peak memory 217536 kb
Host smart-0eb150ae-6dbc-406c-8aa0-454815ecc740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674645464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2674645464
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2229052191
Short name T289
Test name
Test status
Simulation time 244074702 ps
CPU time 1.07 seconds
Started Jul 19 05:09:17 PM PDT 24
Finished Jul 19 05:09:21 PM PDT 24
Peak memory 217492 kb
Host smart-1bdfed99-a401-4aeb-bf84-79a27b553d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229052191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2229052191
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.538229490
Short name T449
Test name
Test status
Simulation time 143234564 ps
CPU time 0.85 seconds
Started Jul 19 05:09:16 PM PDT 24
Finished Jul 19 05:09:20 PM PDT 24
Peak memory 200268 kb
Host smart-3c0aad67-98bf-4549-b5eb-ba4e50c6c3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538229490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.538229490
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3284194953
Short name T97
Test name
Test status
Simulation time 1535825050 ps
CPU time 6.11 seconds
Started Jul 19 05:09:17 PM PDT 24
Finished Jul 19 05:09:26 PM PDT 24
Peak memory 200700 kb
Host smart-2679dc63-59bc-4943-97fa-a854fa61f4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284194953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3284194953
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1525537281
Short name T465
Test name
Test status
Simulation time 143441865 ps
CPU time 1.23 seconds
Started Jul 19 05:09:16 PM PDT 24
Finished Jul 19 05:09:21 PM PDT 24
Peak memory 200456 kb
Host smart-839dce8c-67b1-4ad4-8650-64e4c041a115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525537281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1525537281
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2384117742
Short name T484
Test name
Test status
Simulation time 121068135 ps
CPU time 1.22 seconds
Started Jul 19 05:09:15 PM PDT 24
Finished Jul 19 05:09:19 PM PDT 24
Peak memory 200664 kb
Host smart-6fd8fc7d-4b65-456e-8aa3-3b9af858ee19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384117742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2384117742
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1636478800
Short name T260
Test name
Test status
Simulation time 4569892721 ps
CPU time 17.65 seconds
Started Jul 19 05:09:19 PM PDT 24
Finished Jul 19 05:09:40 PM PDT 24
Peak memory 200808 kb
Host smart-7d4436bd-3eff-4415-b885-be06188e2c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636478800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1636478800
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1336535808
Short name T385
Test name
Test status
Simulation time 143953027 ps
CPU time 2.04 seconds
Started Jul 19 05:09:16 PM PDT 24
Finished Jul 19 05:09:22 PM PDT 24
Peak memory 200532 kb
Host smart-a0caf3ee-6613-4fe0-90c3-71434f20cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336535808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1336535808
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.4042496463
Short name T292
Test name
Test status
Simulation time 102563812 ps
CPU time 0.92 seconds
Started Jul 19 05:09:19 PM PDT 24
Finished Jul 19 05:09:23 PM PDT 24
Peak memory 200460 kb
Host smart-3c83d96c-fc7e-4d1d-8866-1d7753345192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042496463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.4042496463
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3658974997
Short name T158
Test name
Test status
Simulation time 72331971 ps
CPU time 0.76 seconds
Started Jul 19 05:09:18 PM PDT 24
Finished Jul 19 05:09:22 PM PDT 24
Peak memory 200268 kb
Host smart-795f0efd-7c71-4e26-a830-6077ce6e1b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658974997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3658974997
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.13656424
Short name T48
Test name
Test status
Simulation time 1227633015 ps
CPU time 5.69 seconds
Started Jul 19 05:09:31 PM PDT 24
Finished Jul 19 05:09:38 PM PDT 24
Peak memory 217520 kb
Host smart-13b45de0-a765-48fa-b87f-04355f05519c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13656424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.13656424
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4087278592
Short name T430
Test name
Test status
Simulation time 245939586 ps
CPU time 1.06 seconds
Started Jul 19 05:09:20 PM PDT 24
Finished Jul 19 05:09:24 PM PDT 24
Peak memory 217440 kb
Host smart-0e7ba71f-e0b6-452f-81f6-d8b7dc8eb9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087278592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4087278592
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3117320135
Short name T192
Test name
Test status
Simulation time 101818568 ps
CPU time 0.8 seconds
Started Jul 19 05:09:19 PM PDT 24
Finished Jul 19 05:09:23 PM PDT 24
Peak memory 200284 kb
Host smart-c3aebd75-b472-4fb4-b076-bcda58d4d07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117320135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3117320135
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3929524657
Short name T297
Test name
Test status
Simulation time 1601468985 ps
CPU time 7.11 seconds
Started Jul 19 05:09:13 PM PDT 24
Finished Jul 19 05:09:22 PM PDT 24
Peak memory 200728 kb
Host smart-fd6d53f1-e753-4e65-8729-d944dc0694e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929524657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3929524657
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.960237543
Short name T369
Test name
Test status
Simulation time 140532353 ps
CPU time 1.24 seconds
Started Jul 19 05:09:11 PM PDT 24
Finished Jul 19 05:09:15 PM PDT 24
Peak memory 200464 kb
Host smart-6be0a372-b34c-428a-b1e5-7db93928ac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960237543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.960237543
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.439607678
Short name T346
Test name
Test status
Simulation time 201775123 ps
CPU time 1.39 seconds
Started Jul 19 05:09:12 PM PDT 24
Finished Jul 19 05:09:16 PM PDT 24
Peak memory 200676 kb
Host smart-61358cd3-a59b-424f-ac30-61cf9de55943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439607678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.439607678
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3397708721
Short name T503
Test name
Test status
Simulation time 871992649 ps
CPU time 3.88 seconds
Started Jul 19 05:09:10 PM PDT 24
Finished Jul 19 05:09:17 PM PDT 24
Peak memory 200644 kb
Host smart-fe7414e2-ae00-46ae-bfec-2eceeb800dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397708721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3397708721
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.60046869
Short name T326
Test name
Test status
Simulation time 151902622 ps
CPU time 1.93 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:19 PM PDT 24
Peak memory 200476 kb
Host smart-c8d2ab27-94b5-42c6-bd64-eb958c784889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60046869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.60046869
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3761728137
Short name T68
Test name
Test status
Simulation time 70820946 ps
CPU time 0.84 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:18 PM PDT 24
Peak memory 200372 kb
Host smart-7d604640-9c58-4c66-9e03-892e57c8b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761728137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3761728137
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3555884322
Short name T189
Test name
Test status
Simulation time 71441646 ps
CPU time 0.79 seconds
Started Jul 19 05:09:17 PM PDT 24
Finished Jul 19 05:09:21 PM PDT 24
Peak memory 200244 kb
Host smart-480f2d11-bff3-4577-9cd2-a5a3f5e9690f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555884322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3555884322
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1034384616
Short name T197
Test name
Test status
Simulation time 1220960312 ps
CPU time 5.72 seconds
Started Jul 19 05:09:12 PM PDT 24
Finished Jul 19 05:09:20 PM PDT 24
Peak memory 216912 kb
Host smart-75f916b2-0a8d-45bd-8229-b4b378d79423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034384616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1034384616
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1514014159
Short name T314
Test name
Test status
Simulation time 244899212 ps
CPU time 1.05 seconds
Started Jul 19 05:09:13 PM PDT 24
Finished Jul 19 05:09:16 PM PDT 24
Peak memory 217568 kb
Host smart-3a00d482-ed4b-4ffb-ab55-a4567eb3d0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514014159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1514014159
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2955043185
Short name T179
Test name
Test status
Simulation time 98607255 ps
CPU time 0.8 seconds
Started Jul 19 05:09:16 PM PDT 24
Finished Jul 19 05:09:20 PM PDT 24
Peak memory 200244 kb
Host smart-4d70d002-4efc-4d4d-9751-a5e347c05024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955043185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2955043185
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3587080293
Short name T65
Test name
Test status
Simulation time 1006923699 ps
CPU time 4.46 seconds
Started Jul 19 05:09:11 PM PDT 24
Finished Jul 19 05:09:18 PM PDT 24
Peak memory 200724 kb
Host smart-53408240-ddaa-463a-a032-66cbfeb05e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587080293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3587080293
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3869777372
Short name T144
Test name
Test status
Simulation time 150278248 ps
CPU time 1.18 seconds
Started Jul 19 05:09:20 PM PDT 24
Finished Jul 19 05:09:25 PM PDT 24
Peak memory 200456 kb
Host smart-d2f0b56b-78b2-4a81-bc8a-0beddc99d061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869777372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3869777372
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3317753925
Short name T231
Test name
Test status
Simulation time 196197524 ps
CPU time 1.43 seconds
Started Jul 19 05:09:18 PM PDT 24
Finished Jul 19 05:09:23 PM PDT 24
Peak memory 200680 kb
Host smart-dcd993ac-020b-4e6f-9353-857c0645daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317753925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3317753925
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1859611278
Short name T334
Test name
Test status
Simulation time 2899889531 ps
CPU time 14.2 seconds
Started Jul 19 05:09:18 PM PDT 24
Finished Jul 19 05:09:36 PM PDT 24
Peak memory 200800 kb
Host smart-bfa5b723-090d-4be7-b7e6-6a5ed853fa39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859611278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1859611278
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.566650515
Short name T266
Test name
Test status
Simulation time 420286232 ps
CPU time 2.47 seconds
Started Jul 19 05:09:13 PM PDT 24
Finished Jul 19 05:09:18 PM PDT 24
Peak memory 208668 kb
Host smart-5e238e20-c0e0-470d-bbf8-23b6322700b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566650515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.566650515
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2096855049
Short name T21
Test name
Test status
Simulation time 68361722 ps
CPU time 0.83 seconds
Started Jul 19 05:09:17 PM PDT 24
Finished Jul 19 05:09:21 PM PDT 24
Peak memory 200436 kb
Host smart-d46880ed-762b-4102-8ee4-9a08c22fac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096855049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2096855049
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1261440716
Short name T482
Test name
Test status
Simulation time 71147553 ps
CPU time 0.77 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:18 PM PDT 24
Peak memory 200272 kb
Host smart-a535ea5f-88d7-4a05-8692-4841ebe27b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261440716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1261440716
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2595750616
Short name T391
Test name
Test status
Simulation time 2368340193 ps
CPU time 10 seconds
Started Jul 19 05:09:13 PM PDT 24
Finished Jul 19 05:09:25 PM PDT 24
Peak memory 217864 kb
Host smart-0f87e5c5-7c42-41f6-8bd5-2a62b8a0e5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595750616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2595750616
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.413572825
Short name T276
Test name
Test status
Simulation time 245028324 ps
CPU time 1.07 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:18 PM PDT 24
Peak memory 217504 kb
Host smart-97bd0fbd-c571-4f7f-b883-081700b64979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413572825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.413572825
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.278083042
Short name T16
Test name
Test status
Simulation time 105832533 ps
CPU time 0.79 seconds
Started Jul 19 05:09:19 PM PDT 24
Finished Jul 19 05:09:23 PM PDT 24
Peak memory 200268 kb
Host smart-7803e7f3-ad2c-4112-ac62-505162a033cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278083042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.278083042
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1204537685
Short name T101
Test name
Test status
Simulation time 2187140804 ps
CPU time 9.42 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:26 PM PDT 24
Peak memory 200724 kb
Host smart-e3f122ca-0b8c-4d70-97ae-2fe66a520493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204537685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1204537685
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.471059106
Short name T508
Test name
Test status
Simulation time 100119230 ps
CPU time 1.04 seconds
Started Jul 19 05:09:17 PM PDT 24
Finished Jul 19 05:09:21 PM PDT 24
Peak memory 200440 kb
Host smart-9b456d54-21dd-4f1e-9840-62a750ac7a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471059106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.471059106
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2373941701
Short name T287
Test name
Test status
Simulation time 230325386 ps
CPU time 1.56 seconds
Started Jul 19 05:09:12 PM PDT 24
Finished Jul 19 05:09:16 PM PDT 24
Peak memory 200660 kb
Host smart-9940d61b-67b0-483c-bfe0-2f23ad339377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373941701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2373941701
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2038747878
Short name T127
Test name
Test status
Simulation time 6401199399 ps
CPU time 22.03 seconds
Started Jul 19 05:09:12 PM PDT 24
Finished Jul 19 05:09:37 PM PDT 24
Peak memory 200788 kb
Host smart-4036c1c7-614e-4dc1-862b-32248b2d53d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038747878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2038747878
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3667173913
Short name T20
Test name
Test status
Simulation time 221539925 ps
CPU time 1.42 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:19 PM PDT 24
Peak memory 200460 kb
Host smart-08b466b6-4052-4a4c-8d78-aea5084e8521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667173913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3667173913
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4090116721
Short name T137
Test name
Test status
Simulation time 52082024 ps
CPU time 0.7 seconds
Started Jul 19 05:09:15 PM PDT 24
Finished Jul 19 05:09:19 PM PDT 24
Peak memory 200268 kb
Host smart-d715a8e0-1d89-4cbb-90e9-bd75435e91ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090116721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4090116721
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3953203882
Short name T350
Test name
Test status
Simulation time 244149132 ps
CPU time 1.07 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:18 PM PDT 24
Peak memory 217476 kb
Host smart-eb380d11-153b-420e-b887-78359c34b1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953203882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3953203882
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2322372845
Short name T444
Test name
Test status
Simulation time 146702344 ps
CPU time 0.85 seconds
Started Jul 19 05:09:18 PM PDT 24
Finished Jul 19 05:09:22 PM PDT 24
Peak memory 200272 kb
Host smart-48f9a34c-fc80-429a-bc30-f6a5a8d21f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322372845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2322372845
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3673045815
Short name T342
Test name
Test status
Simulation time 1816463176 ps
CPU time 7.74 seconds
Started Jul 19 05:09:13 PM PDT 24
Finished Jul 19 05:09:23 PM PDT 24
Peak memory 200664 kb
Host smart-0d7b6c7e-8b69-45b2-977e-76832aea26b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673045815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3673045815
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.114580144
Short name T516
Test name
Test status
Simulation time 105404787 ps
CPU time 1.03 seconds
Started Jul 19 05:09:18 PM PDT 24
Finished Jul 19 05:09:23 PM PDT 24
Peak memory 200636 kb
Host smart-39e754ab-cb2e-460f-a9f7-c036b19d5619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114580144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.114580144
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1299769724
Short name T403
Test name
Test status
Simulation time 247374484 ps
CPU time 1.44 seconds
Started Jul 19 05:09:19 PM PDT 24
Finished Jul 19 05:09:24 PM PDT 24
Peak memory 200664 kb
Host smart-ea226e00-c071-47d7-b2e0-7e838afa8c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299769724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1299769724
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3116182856
Short name T511
Test name
Test status
Simulation time 4640439299 ps
CPU time 16.67 seconds
Started Jul 19 05:09:19 PM PDT 24
Finished Jul 19 05:09:39 PM PDT 24
Peak memory 200948 kb
Host smart-c6ac8a7f-ce8c-410f-8aed-ed03e5cd63d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116182856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3116182856
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.373058129
Short name T367
Test name
Test status
Simulation time 546030078 ps
CPU time 2.76 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:19 PM PDT 24
Peak memory 200464 kb
Host smart-96fed0df-5ae7-47e6-a939-bd5a9c8dafdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373058129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.373058129
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3082190812
Short name T412
Test name
Test status
Simulation time 266363532 ps
CPU time 1.61 seconds
Started Jul 19 05:09:17 PM PDT 24
Finished Jul 19 05:09:22 PM PDT 24
Peak memory 200432 kb
Host smart-d84462ef-f8cf-41b5-aa45-c98c7b26b0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082190812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3082190812
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1997534259
Short name T376
Test name
Test status
Simulation time 76031563 ps
CPU time 0.81 seconds
Started Jul 19 05:09:20 PM PDT 24
Finished Jul 19 05:09:24 PM PDT 24
Peak memory 200268 kb
Host smart-af12604a-3a3b-4f47-b573-f17a60ac9392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997534259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1997534259
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1597122730
Short name T232
Test name
Test status
Simulation time 1230295710 ps
CPU time 5.83 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:22 PM PDT 24
Peak memory 217828 kb
Host smart-303c8725-66df-44e7-8d03-d1615a7dd7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597122730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1597122730
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3027795402
Short name T250
Test name
Test status
Simulation time 244405257 ps
CPU time 1.07 seconds
Started Jul 19 05:09:15 PM PDT 24
Finished Jul 19 05:09:19 PM PDT 24
Peak memory 217564 kb
Host smart-7ff3ad6f-5ca6-4f65-8ae1-629a7348aa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027795402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3027795402
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.230370982
Short name T14
Test name
Test status
Simulation time 106779575 ps
CPU time 0.85 seconds
Started Jul 19 05:09:15 PM PDT 24
Finished Jul 19 05:09:19 PM PDT 24
Peak memory 200236 kb
Host smart-54d25f80-c92c-41a5-8f0b-d26330004a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230370982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.230370982
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2361447833
Short name T485
Test name
Test status
Simulation time 755169404 ps
CPU time 3.97 seconds
Started Jul 19 05:09:19 PM PDT 24
Finished Jul 19 05:09:26 PM PDT 24
Peak memory 200944 kb
Host smart-d3df9dac-4028-4c3b-b223-dbdf36a42c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361447833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2361447833
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.4210384921
Short name T311
Test name
Test status
Simulation time 94531341 ps
CPU time 1.02 seconds
Started Jul 19 05:09:14 PM PDT 24
Finished Jul 19 05:09:18 PM PDT 24
Peak memory 200428 kb
Host smart-42ae47e4-aef9-4ddf-a3b2-8606572ba15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210384921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.4210384921
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.4040000277
Short name T4
Test name
Test status
Simulation time 121372879 ps
CPU time 1.17 seconds
Started Jul 19 05:09:24 PM PDT 24
Finished Jul 19 05:09:26 PM PDT 24
Peak memory 200712 kb
Host smart-4d3e93da-43c1-42f1-9058-363621e3cefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040000277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.4040000277
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.4180647096
Short name T438
Test name
Test status
Simulation time 1647428116 ps
CPU time 6.3 seconds
Started Jul 19 05:09:21 PM PDT 24
Finished Jul 19 05:09:30 PM PDT 24
Peak memory 200780 kb
Host smart-55e424b6-de77-4125-b72c-1a0f376edda9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180647096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.4180647096
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3124057919
Short name T234
Test name
Test status
Simulation time 386955541 ps
CPU time 2.34 seconds
Started Jul 19 05:09:15 PM PDT 24
Finished Jul 19 05:09:20 PM PDT 24
Peak memory 208684 kb
Host smart-6ebc7fb4-4e91-44b4-96c2-21696c8b4585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124057919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3124057919
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.586021937
Short name T272
Test name
Test status
Simulation time 92610456 ps
CPU time 0.86 seconds
Started Jul 19 05:09:24 PM PDT 24
Finished Jul 19 05:09:26 PM PDT 24
Peak memory 200460 kb
Host smart-733cb1e9-4275-4cbb-a7b3-b55eb4073edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586021937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.586021937
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.77833924
Short name T439
Test name
Test status
Simulation time 64785419 ps
CPU time 0.8 seconds
Started Jul 19 05:08:06 PM PDT 24
Finished Jul 19 05:08:07 PM PDT 24
Peak memory 200268 kb
Host smart-80ed6de4-1a71-43cd-aa75-9d381453a50a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77833924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.77833924
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1979997755
Short name T357
Test name
Test status
Simulation time 2361048572 ps
CPU time 9.61 seconds
Started Jul 19 05:08:06 PM PDT 24
Finished Jul 19 05:08:17 PM PDT 24
Peak memory 217240 kb
Host smart-6e46db24-8022-4eb7-af9f-e35a9d502321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979997755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1979997755
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.843100536
Short name T190
Test name
Test status
Simulation time 244657126 ps
CPU time 1.08 seconds
Started Jul 19 05:08:02 PM PDT 24
Finished Jul 19 05:08:05 PM PDT 24
Peak memory 217468 kb
Host smart-aa489e6b-5c3d-4a95-b948-37400d3c5932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843100536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.843100536
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2864128235
Short name T329
Test name
Test status
Simulation time 139983291 ps
CPU time 0.86 seconds
Started Jul 19 05:08:00 PM PDT 24
Finished Jul 19 05:08:01 PM PDT 24
Peak memory 200256 kb
Host smart-45f0c9c1-6172-439e-9f4e-7dcaeb9cac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864128235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2864128235
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.4050411828
Short name T312
Test name
Test status
Simulation time 768043912 ps
CPU time 3.85 seconds
Started Jul 19 05:08:01 PM PDT 24
Finished Jul 19 05:08:06 PM PDT 24
Peak memory 200620 kb
Host smart-b1f52533-545c-4746-9bc7-51d896eeaa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050411828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4050411828
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3455439553
Short name T159
Test name
Test status
Simulation time 100406548 ps
CPU time 1.03 seconds
Started Jul 19 05:08:01 PM PDT 24
Finished Jul 19 05:08:03 PM PDT 24
Peak memory 200428 kb
Host smart-ae2dfca1-e873-41ad-9fea-2c4c03e10277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455439553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3455439553
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3905285282
Short name T251
Test name
Test status
Simulation time 194948906 ps
CPU time 1.51 seconds
Started Jul 19 05:08:06 PM PDT 24
Finished Jul 19 05:08:09 PM PDT 24
Peak memory 200664 kb
Host smart-5716eb93-72fa-4c60-aeeb-a6afdb300f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905285282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3905285282
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1489304356
Short name T363
Test name
Test status
Simulation time 7038670728 ps
CPU time 29.4 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:42 PM PDT 24
Peak memory 200760 kb
Host smart-19420fb0-333b-44b8-8a8d-341db9b6ed38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489304356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1489304356
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3052644051
Short name T521
Test name
Test status
Simulation time 295023655 ps
CPU time 2.05 seconds
Started Jul 19 05:08:02 PM PDT 24
Finished Jul 19 05:08:05 PM PDT 24
Peak memory 208668 kb
Host smart-39c45e29-2176-4eeb-8a40-b9ed82812320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052644051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3052644051
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.122557008
Short name T69
Test name
Test status
Simulation time 159148914 ps
CPU time 1.29 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:13 PM PDT 24
Peak memory 200728 kb
Host smart-b0a04b73-2434-471c-be27-e97ac3cc567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122557008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.122557008
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.4207311642
Short name T284
Test name
Test status
Simulation time 74237292 ps
CPU time 0.77 seconds
Started Jul 19 05:08:02 PM PDT 24
Finished Jul 19 05:08:05 PM PDT 24
Peak memory 200268 kb
Host smart-9dd311e9-da4b-497b-8fae-f00778b7ee0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207311642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4207311642
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.4020773997
Short name T267
Test name
Test status
Simulation time 244241386 ps
CPU time 1.15 seconds
Started Jul 19 05:08:01 PM PDT 24
Finished Jul 19 05:08:04 PM PDT 24
Peak memory 217508 kb
Host smart-d9e1377b-f8fd-4d06-b3e2-1af3d2fb06e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020773997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.4020773997
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2447029880
Short name T517
Test name
Test status
Simulation time 153485002 ps
CPU time 0.88 seconds
Started Jul 19 05:08:02 PM PDT 24
Finished Jul 19 05:08:04 PM PDT 24
Peak memory 200268 kb
Host smart-7df3deff-08ec-438f-bf66-92ac75ab3fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447029880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2447029880
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1094235081
Short name T341
Test name
Test status
Simulation time 1383951201 ps
CPU time 5.92 seconds
Started Jul 19 05:08:03 PM PDT 24
Finished Jul 19 05:08:10 PM PDT 24
Peak memory 200664 kb
Host smart-d42995c7-6086-4e66-93c9-bd14c82a09fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094235081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1094235081
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.741900110
Short name T422
Test name
Test status
Simulation time 172991613 ps
CPU time 1.23 seconds
Started Jul 19 05:08:03 PM PDT 24
Finished Jul 19 05:08:06 PM PDT 24
Peak memory 200460 kb
Host smart-c758739d-f444-4627-a1e9-62b54e5c8e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741900110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.741900110
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3530875679
Short name T512
Test name
Test status
Simulation time 189196488 ps
CPU time 1.45 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:10 PM PDT 24
Peak memory 200552 kb
Host smart-3f4e3dd8-cdfa-460e-9a7f-73c19c809d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530875679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3530875679
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1556785227
Short name T279
Test name
Test status
Simulation time 1259490934 ps
CPU time 6.81 seconds
Started Jul 19 05:08:01 PM PDT 24
Finished Jul 19 05:08:09 PM PDT 24
Peak memory 208932 kb
Host smart-1d6a8846-6346-4bf5-9b61-268044fd539e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556785227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1556785227
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.997393743
Short name T348
Test name
Test status
Simulation time 341025307 ps
CPU time 2.11 seconds
Started Jul 19 05:08:02 PM PDT 24
Finished Jul 19 05:08:05 PM PDT 24
Peak memory 200476 kb
Host smart-8d2104c2-0239-43ed-9a90-8dd55b6cb3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997393743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.997393743
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2119925405
Short name T286
Test name
Test status
Simulation time 126703926 ps
CPU time 1.15 seconds
Started Jul 19 05:08:04 PM PDT 24
Finished Jul 19 05:08:06 PM PDT 24
Peak memory 200448 kb
Host smart-af819f85-a33e-49a1-b290-ed25a20e1935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119925405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2119925405
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3208549278
Short name T256
Test name
Test status
Simulation time 135781056 ps
CPU time 0.95 seconds
Started Jul 19 05:08:02 PM PDT 24
Finished Jul 19 05:08:05 PM PDT 24
Peak memory 200276 kb
Host smart-20c2f8a1-bbe2-4d2e-b031-d67a61768984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208549278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3208549278
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.120438247
Short name T365
Test name
Test status
Simulation time 1879584881 ps
CPU time 7.54 seconds
Started Jul 19 05:08:02 PM PDT 24
Finished Jul 19 05:08:11 PM PDT 24
Peak memory 217696 kb
Host smart-b6514ed7-49c2-4b0f-a22e-829524f3fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120438247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.120438247
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4124345349
Short name T442
Test name
Test status
Simulation time 243782416 ps
CPU time 1.07 seconds
Started Jul 19 05:08:01 PM PDT 24
Finished Jul 19 05:08:04 PM PDT 24
Peak memory 217472 kb
Host smart-7c57ccef-bb3a-44bb-88e3-108653545d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124345349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4124345349
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1879629019
Short name T200
Test name
Test status
Simulation time 142111712 ps
CPU time 0.82 seconds
Started Jul 19 05:08:01 PM PDT 24
Finished Jul 19 05:08:03 PM PDT 24
Peak memory 200208 kb
Host smart-7c928ed4-0c1f-4cd1-b80d-ac5223a6ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879629019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1879629019
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.894270352
Short name T407
Test name
Test status
Simulation time 916328535 ps
CPU time 4.51 seconds
Started Jul 19 05:08:00 PM PDT 24
Finished Jul 19 05:08:06 PM PDT 24
Peak memory 200680 kb
Host smart-cd040a49-d74b-4ca4-9765-b47abd786ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894270352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.894270352
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2373958356
Short name T474
Test name
Test status
Simulation time 188446256 ps
CPU time 1.23 seconds
Started Jul 19 05:08:01 PM PDT 24
Finished Jul 19 05:08:03 PM PDT 24
Peak memory 200372 kb
Host smart-eb9e66dc-7a62-4f05-8a69-f572ed17acbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373958356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2373958356
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3488709111
Short name T66
Test name
Test status
Simulation time 199033954 ps
CPU time 1.33 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:10 PM PDT 24
Peak memory 200632 kb
Host smart-784ceaae-1349-407c-a498-bc6aa1f00b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488709111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3488709111
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2850895310
Short name T446
Test name
Test status
Simulation time 10825991316 ps
CPU time 45.48 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:54 PM PDT 24
Peak memory 200704 kb
Host smart-37b6a101-e9ad-4018-9773-b9fba725aea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850895310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2850895310
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.174757733
Short name T39
Test name
Test status
Simulation time 505317849 ps
CPU time 2.7 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:13 PM PDT 24
Peak memory 200484 kb
Host smart-5758ac56-7b57-42b4-8126-9f7141d86a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174757733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.174757733
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.614434454
Short name T281
Test name
Test status
Simulation time 137035051 ps
CPU time 1.18 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:13 PM PDT 24
Peak memory 200408 kb
Host smart-50007443-131e-4f5f-a300-cb1cb04dae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614434454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.614434454
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.904064393
Short name T371
Test name
Test status
Simulation time 69497597 ps
CPU time 0.79 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:09 PM PDT 24
Peak memory 200264 kb
Host smart-2c5dd3df-e8cb-41f0-a586-abbd428885b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904064393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.904064393
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3332746374
Short name T317
Test name
Test status
Simulation time 1223498395 ps
CPU time 5.59 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:15 PM PDT 24
Peak memory 216852 kb
Host smart-0137b4b6-8c69-4c1e-837b-3f3b747cc9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332746374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3332746374
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.641307258
Short name T416
Test name
Test status
Simulation time 244249776 ps
CPU time 1.1 seconds
Started Jul 19 05:08:10 PM PDT 24
Finished Jul 19 05:08:15 PM PDT 24
Peak memory 217460 kb
Host smart-6ea3b89b-3cdd-4213-84a2-ee2828b3e49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641307258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.641307258
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1731553151
Short name T93
Test name
Test status
Simulation time 245117206 ps
CPU time 1.01 seconds
Started Jul 19 05:08:04 PM PDT 24
Finished Jul 19 05:08:06 PM PDT 24
Peak memory 200260 kb
Host smart-d5096323-2f54-4058-8a1f-2cde2c6eedc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731553151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1731553151
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2826060717
Short name T500
Test name
Test status
Simulation time 1339292670 ps
CPU time 5.5 seconds
Started Jul 19 05:07:59 PM PDT 24
Finished Jul 19 05:08:05 PM PDT 24
Peak memory 200720 kb
Host smart-66deb05e-9e42-47e8-a654-8ed98ae7485c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826060717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2826060717
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3809351579
Short name T359
Test name
Test status
Simulation time 160575430 ps
CPU time 1.25 seconds
Started Jul 19 05:08:11 PM PDT 24
Finished Jul 19 05:08:16 PM PDT 24
Peak memory 200236 kb
Host smart-66a6f32d-90f0-4abe-b81d-e13435adf2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809351579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3809351579
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.576976843
Short name T247
Test name
Test status
Simulation time 117488049 ps
CPU time 1.14 seconds
Started Jul 19 05:08:01 PM PDT 24
Finished Jul 19 05:08:03 PM PDT 24
Peak memory 200608 kb
Host smart-e1ffe329-086e-4102-95b7-51362366c2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576976843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.576976843
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.669832705
Short name T447
Test name
Test status
Simulation time 4387227316 ps
CPU time 20.38 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:31 PM PDT 24
Peak memory 209092 kb
Host smart-a8dc2adb-895e-4b0a-8b52-58bfaf50463c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669832705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.669832705
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3294634930
Short name T212
Test name
Test status
Simulation time 129445920 ps
CPU time 1.54 seconds
Started Jul 19 05:08:06 PM PDT 24
Finished Jul 19 05:08:09 PM PDT 24
Peak memory 200424 kb
Host smart-5556eedb-2de7-4dbd-8647-e7b22fb1eec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294634930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3294634930
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.611050781
Short name T199
Test name
Test status
Simulation time 157443171 ps
CPU time 1.2 seconds
Started Jul 19 05:08:04 PM PDT 24
Finished Jul 19 05:08:06 PM PDT 24
Peak memory 200448 kb
Host smart-67730834-a72d-4142-b104-740aaf57ceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611050781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.611050781
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2959024863
Short name T211
Test name
Test status
Simulation time 72948693 ps
CPU time 0.83 seconds
Started Jul 19 05:08:10 PM PDT 24
Finished Jul 19 05:08:14 PM PDT 24
Peak memory 200272 kb
Host smart-9cb521b1-a7df-4afc-8b71-aea370528bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959024863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2959024863
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2434640785
Short name T316
Test name
Test status
Simulation time 2384589285 ps
CPU time 8.29 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:21 PM PDT 24
Peak memory 221848 kb
Host smart-d13ff40b-464a-442e-b09c-9b3a7b829efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434640785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2434640785
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.925732860
Short name T497
Test name
Test status
Simulation time 244736436 ps
CPU time 1.08 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:21 PM PDT 24
Peak memory 217500 kb
Host smart-5830a71c-881d-40b2-ae64-ef24ce47a0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925732860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.925732860
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2179357398
Short name T8
Test name
Test status
Simulation time 97661070 ps
CPU time 0.83 seconds
Started Jul 19 05:08:08 PM PDT 24
Finished Jul 19 05:08:11 PM PDT 24
Peak memory 200268 kb
Host smart-68fc4f5d-575e-49b6-92ca-d84474fbbdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179357398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2179357398
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.735535225
Short name T125
Test name
Test status
Simulation time 1621295854 ps
CPU time 6.11 seconds
Started Jul 19 05:08:17 PM PDT 24
Finished Jul 19 05:08:26 PM PDT 24
Peak memory 200728 kb
Host smart-23c531c7-facc-40d6-b3d6-00aac037acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735535225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.735535225
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2525126944
Short name T408
Test name
Test status
Simulation time 107452410 ps
CPU time 1.09 seconds
Started Jul 19 05:08:11 PM PDT 24
Finished Jul 19 05:08:16 PM PDT 24
Peak memory 200164 kb
Host smart-f969921e-327e-4c5c-a671-d5260f1943ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525126944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2525126944
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3609764345
Short name T38
Test name
Test status
Simulation time 246116306 ps
CPU time 1.53 seconds
Started Jul 19 05:08:10 PM PDT 24
Finished Jul 19 05:08:15 PM PDT 24
Peak memory 200660 kb
Host smart-cffbc2e8-4f56-47fe-a3dd-ec7179f6856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609764345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3609764345
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.541402603
Short name T477
Test name
Test status
Simulation time 3275509417 ps
CPU time 13.91 seconds
Started Jul 19 05:08:06 PM PDT 24
Finished Jul 19 05:08:21 PM PDT 24
Peak memory 217064 kb
Host smart-fe15b3c6-1cec-4434-9a25-d6c2474fbe0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541402603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.541402603
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3230797445
Short name T168
Test name
Test status
Simulation time 366195331 ps
CPU time 1.98 seconds
Started Jul 19 05:08:09 PM PDT 24
Finished Jul 19 05:08:14 PM PDT 24
Peak memory 200424 kb
Host smart-11cfd170-fb53-4d9a-ac34-12bcae610a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230797445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3230797445
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3626826375
Short name T34
Test name
Test status
Simulation time 101831053 ps
CPU time 0.89 seconds
Started Jul 19 05:08:07 PM PDT 24
Finished Jul 19 05:08:10 PM PDT 24
Peak memory 200360 kb
Host smart-03497acc-53d3-46e8-86db-f9cb3baac5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626826375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3626826375
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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