Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8708

1

T4

250

T5

8

T10

22

auto[1]

11592

1

T4

218

T5

1

T8

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6242	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6753	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3173	1			T4	75		T8	1		T10	7
reset_info_cp[4]	4161	1			T4	111		T8	1		T10	12
reset_info_cp[8]	95	1			T4	2		T13	1		T33	1
reset_info_cp[16]	124	1			T4	3		T10	1		T12	1
reset_info_cp[32]	120	1			T4	2		T5	1		T11	1
reset_info_cp[64]	116	1			T4	1		T11	2		T13	2
reset_info_cp[128]	136	1			T4	3		T11	1		T92	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3236	1			T4	85		T10	4		T12	8
reset_info_cp[1]	auto[1]	2897	1			T4	62		T8	1		T10	10
reset_info_cp[2]	auto[0]	1013	1			T4	32		T10	2		T12	5
reset_info_cp[2]	auto[1]	2160	1			T4	43		T8	1		T10	5
reset_info_cp[4]	auto[0]	1540	1			T4	54		T10	6		T12	7
reset_info_cp[4]	auto[1]	2621	1			T4	57		T8	1		T10	6
reset_info_cp[8]	auto[0]	36	1			T4	1		T33	1		T140	1
reset_info_cp[8]	auto[1]	59	1			T4	1		T13	1		T92	1
reset_info_cp[16]	auto[0]	49	1			T4	2		T12	1		T33	1
reset_info_cp[16]	auto[1]	75	1			T4	1		T10	1		T93	1
reset_info_cp[32]	auto[0]	50	1			T5	1		T11	1		T33	1
reset_info_cp[32]	auto[1]	70	1			T4	2		T12	1		T95	1
reset_info_cp[64]	auto[0]	46	1			T4	1		T11	2		T92	1
reset_info_cp[64]	auto[1]	70	1			T13	2		T51	1		T34	2
reset_info_cp[128]	auto[0]	53	1			T4	2		T11	1		T93	1
reset_info_cp[128]	auto[1]	83	1			T4	1		T92	1		T94	1