Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/27.rstmgr_por_stretcher.1512287007 Jul 20 06:11:15 PM PDT 24 Jul 20 06:11:16 PM PDT 24 119073429 ps
T537 /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.833613856 Jul 20 06:10:52 PM PDT 24 Jul 20 06:11:00 PM PDT 24 1237338453 ps
T538 /workspace/coverage/default/19.rstmgr_smoke.4188474334 Jul 20 06:10:57 PM PDT 24 Jul 20 06:11:00 PM PDT 24 197873992 ps
T539 /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3437328430 Jul 20 06:10:48 PM PDT 24 Jul 20 06:10:51 PM PDT 24 105650199 ps
T540 /workspace/coverage/default/17.rstmgr_alert_test.617772898 Jul 20 06:10:46 PM PDT 24 Jul 20 06:10:48 PM PDT 24 75563767 ps
T69 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1967947002 Jul 20 05:47:12 PM PDT 24 Jul 20 05:47:15 PM PDT 24 102616280 ps
T74 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.379366629 Jul 20 05:46:54 PM PDT 24 Jul 20 05:46:58 PM PDT 24 192787906 ps
T70 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1803132598 Jul 20 05:47:12 PM PDT 24 Jul 20 05:47:15 PM PDT 24 63488295 ps
T71 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3150352672 Jul 20 05:47:11 PM PDT 24 Jul 20 05:47:14 PM PDT 24 63661847 ps
T72 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2543218146 Jul 20 05:47:15 PM PDT 24 Jul 20 05:47:17 PM PDT 24 85524331 ps
T73 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1875581125 Jul 20 05:47:17 PM PDT 24 Jul 20 05:47:21 PM PDT 24 910572931 ps
T75 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1124727317 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:11 PM PDT 24 123733617 ps
T76 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2499332651 Jul 20 05:46:57 PM PDT 24 Jul 20 05:47:02 PM PDT 24 101695723 ps
T121 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3546981864 Jul 20 05:47:08 PM PDT 24 Jul 20 05:47:17 PM PDT 24 483691579 ps
T139 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1870769792 Jul 20 05:46:56 PM PDT 24 Jul 20 05:47:06 PM PDT 24 479665876 ps
T81 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3622031064 Jul 20 05:47:02 PM PDT 24 Jul 20 05:47:06 PM PDT 24 122578649 ps
T541 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1773553629 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:12 PM PDT 24 226369362 ps
T77 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2639514749 Jul 20 05:47:05 PM PDT 24 Jul 20 05:47:10 PM PDT 24 829241075 ps
T98 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2809551554 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:12 PM PDT 24 178498317 ps
T99 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2019547710 Jul 20 05:47:03 PM PDT 24 Jul 20 05:47:08 PM PDT 24 486668121 ps
T100 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1877099206 Jul 20 05:47:11 PM PDT 24 Jul 20 05:47:16 PM PDT 24 398741698 ps
T101 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.785518446 Jul 20 05:47:09 PM PDT 24 Jul 20 05:47:13 PM PDT 24 112191688 ps
T114 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1514786924 Jul 20 05:47:19 PM PDT 24 Jul 20 05:47:20 PM PDT 24 127907472 ps
T102 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2647119266 Jul 20 05:47:40 PM PDT 24 Jul 20 05:47:42 PM PDT 24 166874174 ps
T115 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4234014658 Jul 20 05:47:05 PM PDT 24 Jul 20 05:47:08 PM PDT 24 65816572 ps
T103 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.864019684 Jul 20 05:47:10 PM PDT 24 Jul 20 05:47:16 PM PDT 24 430698607 ps
T104 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.374337504 Jul 20 05:47:02 PM PDT 24 Jul 20 05:47:07 PM PDT 24 233694367 ps
T542 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2204020186 Jul 20 05:47:06 PM PDT 24 Jul 20 05:47:09 PM PDT 24 117775559 ps
T543 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2555472146 Jul 20 05:47:30 PM PDT 24 Jul 20 05:47:32 PM PDT 24 118495691 ps
T116 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1497868890 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:11 PM PDT 24 185871644 ps
T117 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2743858470 Jul 20 05:47:01 PM PDT 24 Jul 20 05:47:05 PM PDT 24 64955473 ps
T544 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3841206547 Jul 20 05:47:14 PM PDT 24 Jul 20 05:47:16 PM PDT 24 175830427 ps
T545 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1059843816 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:10 PM PDT 24 63862223 ps
T126 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.495494964 Jul 20 05:47:02 PM PDT 24 Jul 20 05:47:07 PM PDT 24 492158633 ps
T118 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3973788913 Jul 20 05:47:04 PM PDT 24 Jul 20 05:47:07 PM PDT 24 104238453 ps
T122 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.745541683 Jul 20 05:47:11 PM PDT 24 Jul 20 05:47:16 PM PDT 24 890654786 ps
T546 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2217437679 Jul 20 05:47:08 PM PDT 24 Jul 20 05:47:11 PM PDT 24 88441748 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2745958850 Jul 20 05:47:00 PM PDT 24 Jul 20 05:47:05 PM PDT 24 90703248 ps
T548 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2998682361 Jul 20 05:47:08 PM PDT 24 Jul 20 05:47:12 PM PDT 24 182444690 ps
T549 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3249291950 Jul 20 05:46:57 PM PDT 24 Jul 20 05:47:03 PM PDT 24 462492033 ps
T550 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3749293689 Jul 20 05:47:08 PM PDT 24 Jul 20 05:47:11 PM PDT 24 78613039 ps
T551 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2462325928 Jul 20 05:46:57 PM PDT 24 Jul 20 05:47:09 PM PDT 24 1551006510 ps
T552 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3502933019 Jul 20 05:47:04 PM PDT 24 Jul 20 05:47:07 PM PDT 24 134372263 ps
T119 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3998801722 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:11 PM PDT 24 111943323 ps
T127 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2528804213 Jul 20 05:47:21 PM PDT 24 Jul 20 05:47:25 PM PDT 24 890584618 ps
T553 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3308678201 Jul 20 05:47:20 PM PDT 24 Jul 20 05:47:22 PM PDT 24 355663846 ps
T120 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3197988641 Jul 20 05:47:03 PM PDT 24 Jul 20 05:47:07 PM PDT 24 68942519 ps
T554 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3190695007 Jul 20 05:47:09 PM PDT 24 Jul 20 05:47:14 PM PDT 24 372112230 ps
T555 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2351629785 Jul 20 05:47:03 PM PDT 24 Jul 20 05:47:07 PM PDT 24 233282729 ps
T556 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3834579390 Jul 20 05:47:10 PM PDT 24 Jul 20 05:47:13 PM PDT 24 74533540 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4278342648 Jul 20 05:47:05 PM PDT 24 Jul 20 05:47:09 PM PDT 24 157411945 ps
T558 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1283681501 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:11 PM PDT 24 108782899 ps
T559 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3715143369 Jul 20 05:47:09 PM PDT 24 Jul 20 05:47:13 PM PDT 24 191456729 ps
T560 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3616610109 Jul 20 05:47:00 PM PDT 24 Jul 20 05:47:07 PM PDT 24 948695454 ps
T561 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1433925228 Jul 20 05:47:09 PM PDT 24 Jul 20 05:47:13 PM PDT 24 131694609 ps
T562 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2788484471 Jul 20 05:46:55 PM PDT 24 Jul 20 05:46:59 PM PDT 24 117909830 ps
T563 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3446543233 Jul 20 05:47:09 PM PDT 24 Jul 20 05:47:12 PM PDT 24 66247691 ps
T564 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2482428952 Jul 20 05:47:02 PM PDT 24 Jul 20 05:47:06 PM PDT 24 214568320 ps
T565 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3348535235 Jul 20 05:47:10 PM PDT 24 Jul 20 05:47:13 PM PDT 24 76027942 ps
T566 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1603684963 Jul 20 05:47:37 PM PDT 24 Jul 20 05:47:38 PM PDT 24 72494322 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.663663731 Jul 20 05:47:08 PM PDT 24 Jul 20 05:47:11 PM PDT 24 93656008 ps
T568 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3443143961 Jul 20 05:47:12 PM PDT 24 Jul 20 05:47:15 PM PDT 24 89537860 ps
T569 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1877534140 Jul 20 05:47:06 PM PDT 24 Jul 20 05:47:11 PM PDT 24 268414241 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.68641731 Jul 20 05:46:58 PM PDT 24 Jul 20 05:47:03 PM PDT 24 153538885 ps
T571 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3006891449 Jul 20 05:47:08 PM PDT 24 Jul 20 05:47:13 PM PDT 24 773700559 ps
T572 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2669348978 Jul 20 05:47:11 PM PDT 24 Jul 20 05:47:15 PM PDT 24 127947637 ps
T573 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.235450594 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:10 PM PDT 24 162665017 ps
T574 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1005990006 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:11 PM PDT 24 86775194 ps
T575 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2640915267 Jul 20 05:47:12 PM PDT 24 Jul 20 05:47:15 PM PDT 24 186915272 ps
T576 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1573074992 Jul 20 05:47:06 PM PDT 24 Jul 20 05:47:09 PM PDT 24 77163352 ps
T577 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1124781473 Jul 20 05:47:05 PM PDT 24 Jul 20 05:47:08 PM PDT 24 144578959 ps
T578 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1878863109 Jul 20 05:46:57 PM PDT 24 Jul 20 05:47:03 PM PDT 24 223577398 ps
T579 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2121842966 Jul 20 05:47:41 PM PDT 24 Jul 20 05:47:42 PM PDT 24 128827367 ps
T580 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1358350361 Jul 20 05:47:09 PM PDT 24 Jul 20 05:47:13 PM PDT 24 129457941 ps
T124 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1521375177 Jul 20 05:46:58 PM PDT 24 Jul 20 05:47:05 PM PDT 24 925870808 ps
T581 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1765239897 Jul 20 05:47:04 PM PDT 24 Jul 20 05:47:09 PM PDT 24 266701569 ps
T582 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3793712132 Jul 20 05:47:20 PM PDT 24 Jul 20 05:47:24 PM PDT 24 490198488 ps
T583 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1580394283 Jul 20 05:47:29 PM PDT 24 Jul 20 05:47:33 PM PDT 24 1101836262 ps
T584 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4272669148 Jul 20 05:47:12 PM PDT 24 Jul 20 05:47:15 PM PDT 24 123861035 ps
T585 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2909444946 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:12 PM PDT 24 286027462 ps
T586 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1189553915 Jul 20 05:47:12 PM PDT 24 Jul 20 05:47:15 PM PDT 24 81906501 ps
T587 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1132345813 Jul 20 05:46:56 PM PDT 24 Jul 20 05:47:00 PM PDT 24 136576424 ps
T588 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1082291039 Jul 20 05:47:04 PM PDT 24 Jul 20 05:47:07 PM PDT 24 60276626 ps
T125 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.211532542 Jul 20 05:47:11 PM PDT 24 Jul 20 05:47:17 PM PDT 24 914671761 ps
T589 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1749346416 Jul 20 05:47:03 PM PDT 24 Jul 20 05:47:11 PM PDT 24 1164548284 ps
T590 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.435271601 Jul 20 05:47:10 PM PDT 24 Jul 20 05:47:15 PM PDT 24 147412956 ps
T591 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3801624401 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:11 PM PDT 24 105454491 ps
T129 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.860849061 Jul 20 05:47:10 PM PDT 24 Jul 20 05:47:15 PM PDT 24 789869030 ps
T138 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.49996729 Jul 20 05:47:38 PM PDT 24 Jul 20 05:47:40 PM PDT 24 507239942 ps
T592 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1998092221 Jul 20 05:47:08 PM PDT 24 Jul 20 05:47:12 PM PDT 24 84868880 ps
T593 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.535386118 Jul 20 05:47:08 PM PDT 24 Jul 20 05:47:12 PM PDT 24 155541553 ps
T594 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3121959652 Jul 20 05:47:01 PM PDT 24 Jul 20 05:47:06 PM PDT 24 95327875 ps
T595 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3557261205 Jul 20 05:47:11 PM PDT 24 Jul 20 05:47:14 PM PDT 24 62871013 ps
T596 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3812736756 Jul 20 05:47:02 PM PDT 24 Jul 20 05:47:06 PM PDT 24 72111112 ps
T597 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.801372887 Jul 20 05:47:28 PM PDT 24 Jul 20 05:47:29 PM PDT 24 123158702 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2010672034 Jul 20 05:47:01 PM PDT 24 Jul 20 05:47:05 PM PDT 24 68860637 ps
T599 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3439112763 Jul 20 05:47:37 PM PDT 24 Jul 20 05:47:40 PM PDT 24 226201395 ps
T600 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.692671253 Jul 20 05:47:18 PM PDT 24 Jul 20 05:47:20 PM PDT 24 438294138 ps
T601 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3015439365 Jul 20 05:47:12 PM PDT 24 Jul 20 05:47:15 PM PDT 24 102620361 ps
T602 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.826334588 Jul 20 05:47:03 PM PDT 24 Jul 20 05:47:07 PM PDT 24 87659315 ps
T603 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.888117466 Jul 20 05:47:10 PM PDT 24 Jul 20 05:47:14 PM PDT 24 218484998 ps
T604 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.4200166615 Jul 20 05:47:26 PM PDT 24 Jul 20 05:47:27 PM PDT 24 83614756 ps
T605 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.945808433 Jul 20 05:47:10 PM PDT 24 Jul 20 05:47:14 PM PDT 24 104361946 ps
T606 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2840082294 Jul 20 05:47:04 PM PDT 24 Jul 20 05:47:09 PM PDT 24 828486819 ps
T607 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3842598584 Jul 20 05:47:07 PM PDT 24 Jul 20 05:47:22 PM PDT 24 510452318 ps
T608 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1052313942 Jul 20 05:47:14 PM PDT 24 Jul 20 05:47:18 PM PDT 24 529532346 ps
T128 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2879185618 Jul 20 05:47:05 PM PDT 24 Jul 20 05:47:09 PM PDT 24 473451857 ps
T609 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3751885441 Jul 20 05:47:25 PM PDT 24 Jul 20 05:47:28 PM PDT 24 182816579 ps
T610 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.952675543 Jul 20 05:47:05 PM PDT 24 Jul 20 05:47:08 PM PDT 24 146149912 ps
T611 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3915882271 Jul 20 05:47:08 PM PDT 24 Jul 20 05:47:13 PM PDT 24 519871467 ps
T612 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.417825010 Jul 20 05:47:02 PM PDT 24 Jul 20 05:47:07 PM PDT 24 171372853 ps
T613 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3523199090 Jul 20 05:47:04 PM PDT 24 Jul 20 05:47:08 PM PDT 24 195664840 ps
T614 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1873902954 Jul 20 05:47:10 PM PDT 24 Jul 20 05:47:13 PM PDT 24 55899900 ps
T615 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2923299644 Jul 20 05:47:12 PM PDT 24 Jul 20 05:47:16 PM PDT 24 494710420 ps
T616 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3555995739 Jul 20 05:47:04 PM PDT 24 Jul 20 05:47:07 PM PDT 24 173610706 ps
T617 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1380977015 Jul 20 05:47:00 PM PDT 24 Jul 20 05:47:05 PM PDT 24 159038754 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2679803871 Jul 20 05:46:54 PM PDT 24 Jul 20 05:46:58 PM PDT 24 195028677 ps
T619 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.314137045 Jul 20 05:47:09 PM PDT 24 Jul 20 05:47:13 PM PDT 24 442080027 ps
T620 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3951997832 Jul 20 05:47:11 PM PDT 24 Jul 20 05:47:14 PM PDT 24 148657742 ps
T123 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3088986581 Jul 20 05:47:02 PM PDT 24 Jul 20 05:47:09 PM PDT 24 939742227 ps

Test location /workspace/coverage/default/20.rstmgr_stress_all.1002331457
Short name T4
Test name
Test status
Simulation time 16397002677 ps
CPU time 53.4 seconds
Started Jul 20 06:10:59 PM PDT 24
Finished Jul 20 06:11:54 PM PDT 24
Peak memory 208976 kb
Host smart-aa38d859-4c00-4714-a5c8-1a6a0477f6b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002331457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1002331457
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4141105849
Short name T96
Test name
Test status
Simulation time 353571627 ps
CPU time 2.49 seconds
Started Jul 20 06:11:33 PM PDT 24
Finished Jul 20 06:11:37 PM PDT 24
Peak memory 200492 kb
Host smart-1bb725d0-5ffb-4df2-9841-955c824b9787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141105849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4141105849
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1124727317
Short name T75
Test name
Test status
Simulation time 123733617 ps
CPU time 0.96 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 200332 kb
Host smart-08b01836-337b-4cdf-b26f-4cfce5de58b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124727317 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1124727317
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.535598035
Short name T82
Test name
Test status
Simulation time 16554338841 ps
CPU time 26.7 seconds
Started Jul 20 06:09:58 PM PDT 24
Finished Jul 20 06:10:25 PM PDT 24
Peak memory 218440 kb
Host smart-ba981e7d-64b1-4600-9061-4dbbabaab0f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535598035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.535598035
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.796404811
Short name T13
Test name
Test status
Simulation time 1895040644 ps
CPU time 7.21 seconds
Started Jul 20 06:11:00 PM PDT 24
Finished Jul 20 06:11:09 PM PDT 24
Peak memory 217512 kb
Host smart-91cb500e-14ab-404c-8bb7-863247d6f867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796404811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.796404811
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2639514749
Short name T77
Test name
Test status
Simulation time 829241075 ps
CPU time 2.79 seconds
Started Jul 20 05:47:05 PM PDT 24
Finished Jul 20 05:47:10 PM PDT 24
Peak memory 200532 kb
Host smart-8c550758-58c3-4d05-a561-4f5e7b7b199c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639514749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2639514749
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2663321494
Short name T28
Test name
Test status
Simulation time 72483672 ps
CPU time 0.76 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:51 PM PDT 24
Peak memory 200264 kb
Host smart-c2ca36e6-363f-4fd7-abce-78c8381497bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663321494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2663321494
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.864019684
Short name T103
Test name
Test status
Simulation time 430698607 ps
CPU time 3.31 seconds
Started Jul 20 05:47:10 PM PDT 24
Finished Jul 20 05:47:16 PM PDT 24
Peak memory 212472 kb
Host smart-9efd6961-bf24-47f9-acd1-ff06112f0cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864019684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.864019684
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.869950331
Short name T94
Test name
Test status
Simulation time 146826815 ps
CPU time 1.1 seconds
Started Jul 20 06:10:46 PM PDT 24
Finished Jul 20 06:10:47 PM PDT 24
Peak memory 200448 kb
Host smart-1a74ef85-4529-4b9e-b738-8eb90afe40ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869950331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.869950331
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.387503470
Short name T42
Test name
Test status
Simulation time 2360210370 ps
CPU time 8.28 seconds
Started Jul 20 06:10:37 PM PDT 24
Finished Jul 20 06:10:46 PM PDT 24
Peak memory 217916 kb
Host smart-e6edbb1f-0ec9-4b14-bd02-1360313a4f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387503470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.387503470
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1556147705
Short name T185
Test name
Test status
Simulation time 219068942 ps
CPU time 1.28 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:10:51 PM PDT 24
Peak memory 200460 kb
Host smart-b724325f-5330-4273-bdbd-f6f5c888d13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556147705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1556147705
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.698986320
Short name T34
Test name
Test status
Simulation time 1228785309 ps
CPU time 5.62 seconds
Started Jul 20 06:11:49 PM PDT 24
Finished Jul 20 06:11:57 PM PDT 24
Peak memory 217820 kb
Host smart-215227a3-a23f-45e4-8ce5-574386e9b863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698986320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.698986320
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.860849061
Short name T129
Test name
Test status
Simulation time 789869030 ps
CPU time 3.06 seconds
Started Jul 20 05:47:10 PM PDT 24
Finished Jul 20 05:47:15 PM PDT 24
Peak memory 200460 kb
Host smart-2bb6452a-36be-4dcf-9d5c-c2c25ae546c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860849061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
860849061
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2909444946
Short name T585
Test name
Test status
Simulation time 286027462 ps
CPU time 1.98 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:12 PM PDT 24
Peak memory 208592 kb
Host smart-3054f46f-7516-4650-80b1-4bcc3507d454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909444946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2909444946
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2543218146
Short name T72
Test name
Test status
Simulation time 85524331 ps
CPU time 0.98 seconds
Started Jul 20 05:47:15 PM PDT 24
Finished Jul 20 05:47:17 PM PDT 24
Peak memory 200352 kb
Host smart-9bae5465-fbe9-4dc1-aefc-6a33bd67f470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543218146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2543218146
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3114346660
Short name T21
Test name
Test status
Simulation time 214739733 ps
CPU time 0.87 seconds
Started Jul 20 06:09:58 PM PDT 24
Finished Jul 20 06:10:00 PM PDT 24
Peak memory 200408 kb
Host smart-71776700-7a20-4d61-913d-0973be433841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114346660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3114346660
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.868820207
Short name T30
Test name
Test status
Simulation time 244950198 ps
CPU time 1.05 seconds
Started Jul 20 06:09:58 PM PDT 24
Finished Jul 20 06:09:59 PM PDT 24
Peak memory 217476 kb
Host smart-ddcb5965-0265-499e-b2ed-14639f615049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868820207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.868820207
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3088986581
Short name T123
Test name
Test status
Simulation time 939742227 ps
CPU time 3.63 seconds
Started Jul 20 05:47:02 PM PDT 24
Finished Jul 20 05:47:09 PM PDT 24
Peak memory 200396 kb
Host smart-9dce9961-1ce7-492e-86d8-48947c73525a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088986581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3088986581
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2528804213
Short name T127
Test name
Test status
Simulation time 890584618 ps
CPU time 3.11 seconds
Started Jul 20 05:47:21 PM PDT 24
Finished Jul 20 05:47:25 PM PDT 24
Peak memory 200392 kb
Host smart-1cba3c8f-a596-44af-8fba-9dbf50e955e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528804213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2528804213
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1662586210
Short name T108
Test name
Test status
Simulation time 7245580161 ps
CPU time 30.68 seconds
Started Jul 20 06:10:01 PM PDT 24
Finished Jul 20 06:10:32 PM PDT 24
Peak memory 208968 kb
Host smart-9028cf23-4673-48fd-8f8b-f9ead4dc4e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662586210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1662586210
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2482428952
Short name T564
Test name
Test status
Simulation time 214568320 ps
CPU time 1.59 seconds
Started Jul 20 05:47:02 PM PDT 24
Finished Jul 20 05:47:06 PM PDT 24
Peak memory 200436 kb
Host smart-8ef6b779-4053-4534-9747-8af622d375d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482428952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
482428952
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1877534140
Short name T569
Test name
Test status
Simulation time 268414241 ps
CPU time 3.23 seconds
Started Jul 20 05:47:06 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 200236 kb
Host smart-7698d22e-ab9c-4677-9417-e10d65b565c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877534140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
877534140
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2204020186
Short name T542
Test name
Test status
Simulation time 117775559 ps
CPU time 0.91 seconds
Started Jul 20 05:47:06 PM PDT 24
Finished Jul 20 05:47:09 PM PDT 24
Peak memory 200072 kb
Host smart-7604bd94-0e5e-420f-8712-cde007d6c2ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204020186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
204020186
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2679803871
Short name T618
Test name
Test status
Simulation time 195028677 ps
CPU time 1.84 seconds
Started Jul 20 05:46:54 PM PDT 24
Finished Jul 20 05:46:58 PM PDT 24
Peak memory 208876 kb
Host smart-f822ec31-b0dd-40ee-b1cc-b2fab121bef5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679803871 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2679803871
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2010672034
Short name T598
Test name
Test status
Simulation time 68860637 ps
CPU time 0.75 seconds
Started Jul 20 05:47:01 PM PDT 24
Finished Jul 20 05:47:05 PM PDT 24
Peak memory 200284 kb
Host smart-850138fc-2b4b-4f88-85a5-9944cd9c6d9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010672034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2010672034
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1005990006
Short name T574
Test name
Test status
Simulation time 86775194 ps
CPU time 1.15 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 200472 kb
Host smart-c8e49945-cba2-4f38-9fb2-e0d89f611fe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005990006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1005990006
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2745958850
Short name T547
Test name
Test status
Simulation time 90703248 ps
CPU time 1.29 seconds
Started Jul 20 05:47:00 PM PDT 24
Finished Jul 20 05:47:05 PM PDT 24
Peak memory 211796 kb
Host smart-463a587a-2a47-44a1-8a63-905f25196c22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745958850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2745958850
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3616610109
Short name T560
Test name
Test status
Simulation time 948695454 ps
CPU time 3.47 seconds
Started Jul 20 05:47:00 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 200488 kb
Host smart-f3824335-9503-4578-9615-519c5c9835f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616610109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3616610109
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1773553629
Short name T541
Test name
Test status
Simulation time 226369362 ps
CPU time 1.54 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:12 PM PDT 24
Peak memory 200292 kb
Host smart-64397ceb-38c3-4981-88e1-e4a623f98939
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773553629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
773553629
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1870769792
Short name T139
Test name
Test status
Simulation time 479665876 ps
CPU time 5.89 seconds
Started Jul 20 05:46:56 PM PDT 24
Finished Jul 20 05:47:06 PM PDT 24
Peak memory 200288 kb
Host smart-83725955-2e00-447a-a557-963c3c0b5543
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870769792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
870769792
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1132345813
Short name T587
Test name
Test status
Simulation time 136576424 ps
CPU time 0.96 seconds
Started Jul 20 05:46:56 PM PDT 24
Finished Jul 20 05:47:00 PM PDT 24
Peak memory 200240 kb
Host smart-4bb02fa1-2d2f-497f-9a1b-7d3cbfda4831
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132345813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
132345813
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.235450594
Short name T573
Test name
Test status
Simulation time 162665017 ps
CPU time 1.14 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:10 PM PDT 24
Peak memory 200404 kb
Host smart-cc2edd2a-b679-4747-b45d-54d2dbb2123d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235450594 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.235450594
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3812736756
Short name T596
Test name
Test status
Simulation time 72111112 ps
CPU time 0.87 seconds
Started Jul 20 05:47:02 PM PDT 24
Finished Jul 20 05:47:06 PM PDT 24
Peak memory 200256 kb
Host smart-67192474-4859-471b-b43a-794f3e742534
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812736756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3812736756
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1380977015
Short name T617
Test name
Test status
Simulation time 159038754 ps
CPU time 1.23 seconds
Started Jul 20 05:47:00 PM PDT 24
Finished Jul 20 05:47:05 PM PDT 24
Peak memory 200260 kb
Host smart-68a96100-bb92-4bec-8e7e-0cf4491537ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380977015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1380977015
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2499332651
Short name T76
Test name
Test status
Simulation time 101695723 ps
CPU time 1.54 seconds
Started Jul 20 05:46:57 PM PDT 24
Finished Jul 20 05:47:02 PM PDT 24
Peak memory 208592 kb
Host smart-5f103f2b-335e-4a7e-bfd7-9aa81a0fddef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499332651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2499332651
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1521375177
Short name T124
Test name
Test status
Simulation time 925870808 ps
CPU time 3.34 seconds
Started Jul 20 05:46:58 PM PDT 24
Finished Jul 20 05:47:05 PM PDT 24
Peak memory 200476 kb
Host smart-acd02cad-c9f8-421b-b44c-6da401253c60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521375177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1521375177
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3622031064
Short name T81
Test name
Test status
Simulation time 122578649 ps
CPU time 1.05 seconds
Started Jul 20 05:47:02 PM PDT 24
Finished Jul 20 05:47:06 PM PDT 24
Peak memory 200408 kb
Host smart-a56840af-3382-47c3-97d9-c04b0916b507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622031064 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3622031064
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1082291039
Short name T588
Test name
Test status
Simulation time 60276626 ps
CPU time 0.78 seconds
Started Jul 20 05:47:04 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 200204 kb
Host smart-5d325d9a-af6f-487f-aaad-d694c9f453ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082291039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1082291039
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1433925228
Short name T561
Test name
Test status
Simulation time 131694609 ps
CPU time 1.24 seconds
Started Jul 20 05:47:09 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 200416 kb
Host smart-e9164f34-0520-4d3a-8bc2-d7d8f08e387c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433925228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1433925228
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2121842966
Short name T579
Test name
Test status
Simulation time 128827367 ps
CPU time 1.04 seconds
Started Jul 20 05:47:41 PM PDT 24
Finished Jul 20 05:47:42 PM PDT 24
Peak memory 200440 kb
Host smart-c7500d89-ecc2-4f3c-8967-047903c33d5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121842966 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2121842966
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3834579390
Short name T556
Test name
Test status
Simulation time 74533540 ps
CPU time 0.78 seconds
Started Jul 20 05:47:10 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 200220 kb
Host smart-940fe272-aea6-47b1-a2db-673ca6cfa2d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834579390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3834579390
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1765239897
Short name T581
Test name
Test status
Simulation time 266701569 ps
CPU time 2.09 seconds
Started Jul 20 05:47:04 PM PDT 24
Finished Jul 20 05:47:09 PM PDT 24
Peak memory 212072 kb
Host smart-2044ab47-0e00-4ef2-bd37-4061c737f6f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765239897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1765239897
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2019547710
Short name T99
Test name
Test status
Simulation time 486668121 ps
CPU time 2.02 seconds
Started Jul 20 05:47:03 PM PDT 24
Finished Jul 20 05:47:08 PM PDT 24
Peak memory 200352 kb
Host smart-aec81d27-4bd2-4bb8-9a70-817bbfa600dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019547710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2019547710
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2640915267
Short name T575
Test name
Test status
Simulation time 186915272 ps
CPU time 1.3 seconds
Started Jul 20 05:47:12 PM PDT 24
Finished Jul 20 05:47:15 PM PDT 24
Peak memory 208532 kb
Host smart-84a2dbd1-d117-4101-91ba-8624c1703ac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640915267 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2640915267
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3150352672
Short name T71
Test name
Test status
Simulation time 63661847 ps
CPU time 0.77 seconds
Started Jul 20 05:47:11 PM PDT 24
Finished Jul 20 05:47:14 PM PDT 24
Peak memory 200268 kb
Host smart-1d7029fd-038f-4e1a-90a1-b9fa231ae958
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150352672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3150352672
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3715143369
Short name T559
Test name
Test status
Simulation time 191456729 ps
CPU time 1.47 seconds
Started Jul 20 05:47:09 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 200400 kb
Host smart-a983796d-35e1-4cd8-a67d-7865e036bd38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715143369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3715143369
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1052313942
Short name T608
Test name
Test status
Simulation time 529532346 ps
CPU time 3.62 seconds
Started Jul 20 05:47:14 PM PDT 24
Finished Jul 20 05:47:18 PM PDT 24
Peak memory 208804 kb
Host smart-36d715fc-0a9c-471a-8a6a-e0af2f6b5663
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052313942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1052313942
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1875581125
Short name T73
Test name
Test status
Simulation time 910572931 ps
CPU time 2.87 seconds
Started Jul 20 05:47:17 PM PDT 24
Finished Jul 20 05:47:21 PM PDT 24
Peak memory 200488 kb
Host smart-8781960f-2ff1-4b65-92b8-617052c78f88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875581125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1875581125
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2998682361
Short name T548
Test name
Test status
Simulation time 182444690 ps
CPU time 1.69 seconds
Started Jul 20 05:47:08 PM PDT 24
Finished Jul 20 05:47:12 PM PDT 24
Peak memory 208924 kb
Host smart-a430bdf3-d1b8-488b-bdb4-a02eead5c9bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998682361 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2998682361
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.4200166615
Short name T604
Test name
Test status
Simulation time 83614756 ps
CPU time 0.91 seconds
Started Jul 20 05:47:26 PM PDT 24
Finished Jul 20 05:47:27 PM PDT 24
Peak memory 200192 kb
Host smart-69aeb8be-a829-411c-92c0-40f2a67c763e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200166615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.4200166615
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.888117466
Short name T603
Test name
Test status
Simulation time 218484998 ps
CPU time 1.61 seconds
Started Jul 20 05:47:10 PM PDT 24
Finished Jul 20 05:47:14 PM PDT 24
Peak memory 200472 kb
Host smart-9c5e965c-1751-44fe-9b9a-dc2a32e17a39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888117466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.888117466
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3308678201
Short name T553
Test name
Test status
Simulation time 355663846 ps
CPU time 2.56 seconds
Started Jul 20 05:47:20 PM PDT 24
Finished Jul 20 05:47:22 PM PDT 24
Peak memory 200408 kb
Host smart-3bd8f13d-f613-4d67-a13b-5de75e4ba327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308678201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3308678201
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.745541683
Short name T122
Test name
Test status
Simulation time 890654786 ps
CPU time 2.99 seconds
Started Jul 20 05:47:11 PM PDT 24
Finished Jul 20 05:47:16 PM PDT 24
Peak memory 200620 kb
Host smart-75cb269d-09f8-4d5c-b7bb-748972eda614
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745541683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.745541683
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2555472146
Short name T543
Test name
Test status
Simulation time 118495691 ps
CPU time 0.96 seconds
Started Jul 20 05:47:30 PM PDT 24
Finished Jul 20 05:47:32 PM PDT 24
Peak memory 200388 kb
Host smart-b29d1b31-3b58-4d3f-a989-26dca32b8159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555472146 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2555472146
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3557261205
Short name T595
Test name
Test status
Simulation time 62871013 ps
CPU time 0.77 seconds
Started Jul 20 05:47:11 PM PDT 24
Finished Jul 20 05:47:14 PM PDT 24
Peak memory 200256 kb
Host smart-4f4e7e88-5416-4cd0-8755-4ef42f1c25bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557261205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3557261205
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3951997832
Short name T620
Test name
Test status
Simulation time 148657742 ps
CPU time 1.28 seconds
Started Jul 20 05:47:11 PM PDT 24
Finished Jul 20 05:47:14 PM PDT 24
Peak memory 200356 kb
Host smart-c3daf211-e5b2-4251-a453-ac341a59bdaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951997832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3951997832
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.435271601
Short name T590
Test name
Test status
Simulation time 147412956 ps
CPU time 2.32 seconds
Started Jul 20 05:47:10 PM PDT 24
Finished Jul 20 05:47:15 PM PDT 24
Peak memory 208636 kb
Host smart-81fd5405-f7ac-4a01-aecf-371056efe0bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435271601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.435271601
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2923299644
Short name T615
Test name
Test status
Simulation time 494710420 ps
CPU time 2 seconds
Started Jul 20 05:47:12 PM PDT 24
Finished Jul 20 05:47:16 PM PDT 24
Peak memory 200468 kb
Host smart-9c6bf92c-8db1-467f-950d-2eca4b5bc097
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923299644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2923299644
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3841206547
Short name T544
Test name
Test status
Simulation time 175830427 ps
CPU time 1.17 seconds
Started Jul 20 05:47:14 PM PDT 24
Finished Jul 20 05:47:16 PM PDT 24
Peak memory 200404 kb
Host smart-df4ceb36-913c-4b75-b073-d5b11ee9d146
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841206547 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3841206547
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3443143961
Short name T568
Test name
Test status
Simulation time 89537860 ps
CPU time 0.84 seconds
Started Jul 20 05:47:12 PM PDT 24
Finished Jul 20 05:47:15 PM PDT 24
Peak memory 200152 kb
Host smart-bdc84b8f-a020-4b36-9760-001fea68f914
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443143961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3443143961
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3439112763
Short name T599
Test name
Test status
Simulation time 226201395 ps
CPU time 1.54 seconds
Started Jul 20 05:47:37 PM PDT 24
Finished Jul 20 05:47:40 PM PDT 24
Peak memory 200456 kb
Host smart-97b709e3-7c30-4cb7-9cac-2355d0c7abb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439112763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3439112763
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.692671253
Short name T600
Test name
Test status
Simulation time 438294138 ps
CPU time 1.87 seconds
Started Jul 20 05:47:18 PM PDT 24
Finished Jul 20 05:47:20 PM PDT 24
Peak memory 200404 kb
Host smart-8a5f6fb3-f3a7-42a9-a3e6-295e30c433ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692671253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.692671253
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4272669148
Short name T584
Test name
Test status
Simulation time 123861035 ps
CPU time 1.37 seconds
Started Jul 20 05:47:12 PM PDT 24
Finished Jul 20 05:47:15 PM PDT 24
Peak memory 208636 kb
Host smart-d88b0fd4-b614-4dbd-8a35-c415f2cecd3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272669148 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.4272669148
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1873902954
Short name T614
Test name
Test status
Simulation time 55899900 ps
CPU time 0.77 seconds
Started Jul 20 05:47:10 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 200204 kb
Host smart-6d3e8abc-8dde-4aa0-b03e-8cc8f3eb04e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873902954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1873902954
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1514786924
Short name T114
Test name
Test status
Simulation time 127907472 ps
CPU time 1.26 seconds
Started Jul 20 05:47:19 PM PDT 24
Finished Jul 20 05:47:20 PM PDT 24
Peak memory 200488 kb
Host smart-292cda2e-6b50-4216-aec5-db2358a6351d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514786924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1514786924
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3190695007
Short name T554
Test name
Test status
Simulation time 372112230 ps
CPU time 2.69 seconds
Started Jul 20 05:47:09 PM PDT 24
Finished Jul 20 05:47:14 PM PDT 24
Peak memory 208604 kb
Host smart-830933e1-3646-446f-b4e4-8b1b79f5c414
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190695007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3190695007
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.49996729
Short name T138
Test name
Test status
Simulation time 507239942 ps
CPU time 1.91 seconds
Started Jul 20 05:47:38 PM PDT 24
Finished Jul 20 05:47:40 PM PDT 24
Peak memory 200508 kb
Host smart-c827d464-c8ee-4468-92e1-d77f4b0e2c86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49996729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.49996729
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2647119266
Short name T102
Test name
Test status
Simulation time 166874174 ps
CPU time 1.66 seconds
Started Jul 20 05:47:40 PM PDT 24
Finished Jul 20 05:47:42 PM PDT 24
Peak memory 208776 kb
Host smart-7bc31de5-55b3-4f22-aba8-f5135f0c0230
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647119266 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2647119266
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1803132598
Short name T70
Test name
Test status
Simulation time 63488295 ps
CPU time 0.76 seconds
Started Jul 20 05:47:12 PM PDT 24
Finished Jul 20 05:47:15 PM PDT 24
Peak memory 200256 kb
Host smart-0fd02149-663f-4fbc-9911-5998c42fda92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803132598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1803132598
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1967947002
Short name T69
Test name
Test status
Simulation time 102616280 ps
CPU time 1.27 seconds
Started Jul 20 05:47:12 PM PDT 24
Finished Jul 20 05:47:15 PM PDT 24
Peak memory 200500 kb
Host smart-3759333a-25d5-4b92-9ac7-384f77f61284
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967947002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1967947002
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3793712132
Short name T582
Test name
Test status
Simulation time 490198488 ps
CPU time 3.29 seconds
Started Jul 20 05:47:20 PM PDT 24
Finished Jul 20 05:47:24 PM PDT 24
Peak memory 216448 kb
Host smart-d77405eb-f63f-4098-bfd7-eeeb38dad193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793712132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3793712132
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.211532542
Short name T125
Test name
Test status
Simulation time 914671761 ps
CPU time 3.48 seconds
Started Jul 20 05:47:11 PM PDT 24
Finished Jul 20 05:47:17 PM PDT 24
Peak memory 200468 kb
Host smart-04ea5178-8be5-4c81-898d-9afc524e2994
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211532542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.211532542
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3015439365
Short name T601
Test name
Test status
Simulation time 102620361 ps
CPU time 1.03 seconds
Started Jul 20 05:47:12 PM PDT 24
Finished Jul 20 05:47:15 PM PDT 24
Peak memory 208592 kb
Host smart-97c27962-1dbb-4ec6-acba-09fa76eb0c99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015439365 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3015439365
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3348535235
Short name T565
Test name
Test status
Simulation time 76027942 ps
CPU time 0.8 seconds
Started Jul 20 05:47:10 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 200184 kb
Host smart-91c23a15-7b91-49d0-9976-18926ed2bf7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348535235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3348535235
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2669348978
Short name T572
Test name
Test status
Simulation time 127947637 ps
CPU time 1.11 seconds
Started Jul 20 05:47:11 PM PDT 24
Finished Jul 20 05:47:15 PM PDT 24
Peak memory 200348 kb
Host smart-6d153b4f-bd1a-473c-ada5-b7e81a08e802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669348978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2669348978
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3751885441
Short name T609
Test name
Test status
Simulation time 182816579 ps
CPU time 2.7 seconds
Started Jul 20 05:47:25 PM PDT 24
Finished Jul 20 05:47:28 PM PDT 24
Peak memory 200392 kb
Host smart-a2eb6bc4-189e-4b8b-a380-c4d92095c2f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751885441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3751885441
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.801372887
Short name T597
Test name
Test status
Simulation time 123158702 ps
CPU time 0.92 seconds
Started Jul 20 05:47:28 PM PDT 24
Finished Jul 20 05:47:29 PM PDT 24
Peak memory 200388 kb
Host smart-df3ddebc-0a89-4566-b423-cd7976baae67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801372887 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.801372887
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1603684963
Short name T566
Test name
Test status
Simulation time 72494322 ps
CPU time 0.78 seconds
Started Jul 20 05:47:37 PM PDT 24
Finished Jul 20 05:47:38 PM PDT 24
Peak memory 200184 kb
Host smart-141a33d3-35cb-407d-97ce-2a1c276c4bfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603684963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1603684963
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1189553915
Short name T586
Test name
Test status
Simulation time 81906501 ps
CPU time 1.06 seconds
Started Jul 20 05:47:12 PM PDT 24
Finished Jul 20 05:47:15 PM PDT 24
Peak memory 200252 kb
Host smart-e37df6c1-fd17-4ed8-a982-6c8a8d41ac4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189553915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1189553915
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1877099206
Short name T100
Test name
Test status
Simulation time 398741698 ps
CPU time 2.84 seconds
Started Jul 20 05:47:11 PM PDT 24
Finished Jul 20 05:47:16 PM PDT 24
Peak memory 212116 kb
Host smart-6231a4a6-ae5d-4c8d-bcf1-82c38715587b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877099206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1877099206
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1580394283
Short name T583
Test name
Test status
Simulation time 1101836262 ps
CPU time 3.04 seconds
Started Jul 20 05:47:29 PM PDT 24
Finished Jul 20 05:47:33 PM PDT 24
Peak memory 200432 kb
Host smart-b8e45169-1cbc-4e67-8fa3-82137e5ac531
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580394283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1580394283
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3249291950
Short name T549
Test name
Test status
Simulation time 462492033 ps
CPU time 2.75 seconds
Started Jul 20 05:46:57 PM PDT 24
Finished Jul 20 05:47:03 PM PDT 24
Peak memory 200540 kb
Host smart-8f99a792-dcf0-4f27-b434-a3f7aa402be2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249291950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
249291950
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2462325928
Short name T551
Test name
Test status
Simulation time 1551006510 ps
CPU time 8.14 seconds
Started Jul 20 05:46:57 PM PDT 24
Finished Jul 20 05:47:09 PM PDT 24
Peak memory 200432 kb
Host smart-cd6c95ea-1d66-4123-978b-ece6545dcae2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462325928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
462325928
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2788484471
Short name T562
Test name
Test status
Simulation time 117909830 ps
CPU time 0.89 seconds
Started Jul 20 05:46:55 PM PDT 24
Finished Jul 20 05:46:59 PM PDT 24
Peak memory 200264 kb
Host smart-9b18a1aa-7f08-4a18-b0b4-93ca0cd77a91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788484471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
788484471
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.68641731
Short name T570
Test name
Test status
Simulation time 153538885 ps
CPU time 1.49 seconds
Started Jul 20 05:46:58 PM PDT 24
Finished Jul 20 05:47:03 PM PDT 24
Peak memory 208788 kb
Host smart-8eab49e9-bc98-47a3-afea-2e77c8c3a462
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68641731 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.68641731
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1573074992
Short name T576
Test name
Test status
Simulation time 77163352 ps
CPU time 0.85 seconds
Started Jul 20 05:47:06 PM PDT 24
Finished Jul 20 05:47:09 PM PDT 24
Peak memory 200220 kb
Host smart-d1a159a0-35a4-4e72-930e-13d0ab5bd6f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573074992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1573074992
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1878863109
Short name T578
Test name
Test status
Simulation time 223577398 ps
CPU time 1.58 seconds
Started Jul 20 05:46:57 PM PDT 24
Finished Jul 20 05:47:03 PM PDT 24
Peak memory 200444 kb
Host smart-e24f17b8-c573-4c85-865c-0b24e9167761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878863109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1878863109
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.379366629
Short name T74
Test name
Test status
Simulation time 192787906 ps
CPU time 1.37 seconds
Started Jul 20 05:46:54 PM PDT 24
Finished Jul 20 05:46:58 PM PDT 24
Peak memory 208612 kb
Host smart-1712fe74-ed35-4acb-9a26-61752a0f291b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379366629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.379366629
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.495494964
Short name T126
Test name
Test status
Simulation time 492158633 ps
CPU time 1.94 seconds
Started Jul 20 05:47:02 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 200432 kb
Host smart-67288972-d9c4-4632-9737-00ee7f7e3a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495494964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
495494964
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4278342648
Short name T557
Test name
Test status
Simulation time 157411945 ps
CPU time 1.87 seconds
Started Jul 20 05:47:05 PM PDT 24
Finished Jul 20 05:47:09 PM PDT 24
Peak memory 216776 kb
Host smart-f849e603-680b-43db-8224-33aa7b63546b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278342648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
278342648
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3546981864
Short name T121
Test name
Test status
Simulation time 483691579 ps
CPU time 5.79 seconds
Started Jul 20 05:47:08 PM PDT 24
Finished Jul 20 05:47:17 PM PDT 24
Peak memory 200380 kb
Host smart-831fdb89-40cf-46ee-809c-0c535798d211
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546981864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
546981864
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1124781473
Short name T577
Test name
Test status
Simulation time 144578959 ps
CPU time 0.94 seconds
Started Jul 20 05:47:05 PM PDT 24
Finished Jul 20 05:47:08 PM PDT 24
Peak memory 200264 kb
Host smart-45371caa-3b9d-4d0a-910f-1d8e9fecbfa6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124781473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
124781473
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2351629785
Short name T555
Test name
Test status
Simulation time 233282729 ps
CPU time 1.38 seconds
Started Jul 20 05:47:03 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 208600 kb
Host smart-50970217-c421-4065-83e8-9925ae79f7ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351629785 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2351629785
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3197988641
Short name T120
Test name
Test status
Simulation time 68942519 ps
CPU time 0.81 seconds
Started Jul 20 05:47:03 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 200256 kb
Host smart-40850cec-e5c6-4859-b03f-cc122177ae86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197988641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3197988641
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3121959652
Short name T594
Test name
Test status
Simulation time 95327875 ps
CPU time 1.23 seconds
Started Jul 20 05:47:01 PM PDT 24
Finished Jul 20 05:47:06 PM PDT 24
Peak memory 200456 kb
Host smart-a39cde62-adc6-41d1-b374-792000036d43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121959652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3121959652
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2809551554
Short name T98
Test name
Test status
Simulation time 178498317 ps
CPU time 2.34 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:12 PM PDT 24
Peak memory 208536 kb
Host smart-4f46555d-2876-4e6d-9971-52cf47426211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809551554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2809551554
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.535386118
Short name T593
Test name
Test status
Simulation time 155541553 ps
CPU time 1.91 seconds
Started Jul 20 05:47:08 PM PDT 24
Finished Jul 20 05:47:12 PM PDT 24
Peak memory 208676 kb
Host smart-6c239b73-6d0f-4f72-bedd-39f096d9c10d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535386118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.535386118
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1749346416
Short name T589
Test name
Test status
Simulation time 1164548284 ps
CPU time 5.4 seconds
Started Jul 20 05:47:03 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 216724 kb
Host smart-acb7ca1f-a010-4084-afa1-45dfc0592efa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749346416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
749346416
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.663663731
Short name T567
Test name
Test status
Simulation time 93656008 ps
CPU time 0.78 seconds
Started Jul 20 05:47:08 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 200152 kb
Host smart-1e0a498e-8150-47cb-a2ba-9ced0c9e6eab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663663731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.663663731
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.785518446
Short name T101
Test name
Test status
Simulation time 112191688 ps
CPU time 1.18 seconds
Started Jul 20 05:47:09 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 208560 kb
Host smart-341f691a-8c38-40a1-8167-82fbad8658f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785518446 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.785518446
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1998092221
Short name T592
Test name
Test status
Simulation time 84868880 ps
CPU time 0.87 seconds
Started Jul 20 05:47:08 PM PDT 24
Finished Jul 20 05:47:12 PM PDT 24
Peak memory 200164 kb
Host smart-10cd6f2b-dd15-4235-b6a2-097fc036e8c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998092221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1998092221
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.952675543
Short name T610
Test name
Test status
Simulation time 146149912 ps
CPU time 1.1 seconds
Started Jul 20 05:47:05 PM PDT 24
Finished Jul 20 05:47:08 PM PDT 24
Peak memory 200280 kb
Host smart-1f28d25b-974f-4666-9620-b10b86dc1b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952675543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.952675543
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.374337504
Short name T104
Test name
Test status
Simulation time 233694367 ps
CPU time 1.74 seconds
Started Jul 20 05:47:02 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 208560 kb
Host smart-b02fcbf0-5112-4139-a101-4d96ef0d82a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374337504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.374337504
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2840082294
Short name T606
Test name
Test status
Simulation time 828486819 ps
CPU time 2.88 seconds
Started Jul 20 05:47:04 PM PDT 24
Finished Jul 20 05:47:09 PM PDT 24
Peak memory 200524 kb
Host smart-f798909f-d0e4-41a2-9d80-4802d61dfe7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840082294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2840082294
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2217437679
Short name T546
Test name
Test status
Simulation time 88441748 ps
CPU time 0.9 seconds
Started Jul 20 05:47:08 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 200396 kb
Host smart-0062f25a-6792-4435-8779-6e3bb64d0d22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217437679 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2217437679
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4234014658
Short name T115
Test name
Test status
Simulation time 65816572 ps
CPU time 0.81 seconds
Started Jul 20 05:47:05 PM PDT 24
Finished Jul 20 05:47:08 PM PDT 24
Peak memory 200272 kb
Host smart-e89ae349-fa91-4001-9bdf-08301c44b5c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234014658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.4234014658
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1358350361
Short name T580
Test name
Test status
Simulation time 129457941 ps
CPU time 1.13 seconds
Started Jul 20 05:47:09 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 200332 kb
Host smart-5460e509-25f4-4911-bb60-c356d6b5a300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358350361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1358350361
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3842598584
Short name T607
Test name
Test status
Simulation time 510452318 ps
CPU time 3.26 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:22 PM PDT 24
Peak memory 208592 kb
Host smart-d233fb99-6621-4d85-b530-5f6bbb794ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842598584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3842598584
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2879185618
Short name T128
Test name
Test status
Simulation time 473451857 ps
CPU time 1.86 seconds
Started Jul 20 05:47:05 PM PDT 24
Finished Jul 20 05:47:09 PM PDT 24
Peak memory 200456 kb
Host smart-b115d929-320b-44d4-9667-42bff7b54300
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879185618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2879185618
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3446543233
Short name T563
Test name
Test status
Simulation time 66247691 ps
CPU time 0.78 seconds
Started Jul 20 05:47:09 PM PDT 24
Finished Jul 20 05:47:12 PM PDT 24
Peak memory 200268 kb
Host smart-4fe5c496-a254-4404-a577-5dcde7d79a8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446543233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3446543233
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3998801722
Short name T119
Test name
Test status
Simulation time 111943323 ps
CPU time 1.22 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 200352 kb
Host smart-5f61f442-bb55-416b-99d5-68dc36843361
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998801722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3998801722
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.826334588
Short name T602
Test name
Test status
Simulation time 87659315 ps
CPU time 1.22 seconds
Started Jul 20 05:47:03 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 200244 kb
Host smart-d8c1e0a2-9a20-435c-90c3-585a9030d16d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826334588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.826334588
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3006891449
Short name T571
Test name
Test status
Simulation time 773700559 ps
CPU time 2.6 seconds
Started Jul 20 05:47:08 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 200480 kb
Host smart-3568f925-4850-4f0b-aedd-e05b6cf44a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006891449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3006891449
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3555995739
Short name T616
Test name
Test status
Simulation time 173610706 ps
CPU time 1.32 seconds
Started Jul 20 05:47:04 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 208576 kb
Host smart-8d6fc16d-9cbd-419d-8bd0-b62c8b055292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555995739 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3555995739
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3749293689
Short name T550
Test name
Test status
Simulation time 78613039 ps
CPU time 0.78 seconds
Started Jul 20 05:47:08 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 200084 kb
Host smart-9c80dec0-ffd6-4b5a-a9dd-9fad052eb327
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749293689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3749293689
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.945808433
Short name T605
Test name
Test status
Simulation time 104361946 ps
CPU time 1.29 seconds
Started Jul 20 05:47:10 PM PDT 24
Finished Jul 20 05:47:14 PM PDT 24
Peak memory 200472 kb
Host smart-7177fee0-b6b8-4d52-a856-0c4b7ac6544b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945808433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.945808433
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1283681501
Short name T558
Test name
Test status
Simulation time 108782899 ps
CPU time 1.71 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 200404 kb
Host smart-4dc503d0-dfbd-4805-a01a-f449cc9b6f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283681501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1283681501
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.314137045
Short name T619
Test name
Test status
Simulation time 442080027 ps
CPU time 1.7 seconds
Started Jul 20 05:47:09 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 200492 kb
Host smart-dd1d5d88-798c-427e-881a-b7d1848e7f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314137045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
314137045
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.417825010
Short name T612
Test name
Test status
Simulation time 171372853 ps
CPU time 1.44 seconds
Started Jul 20 05:47:02 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 208740 kb
Host smart-81a3e195-2c26-4b3e-ac3a-06ff0ea8e57d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417825010 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.417825010
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2743858470
Short name T117
Test name
Test status
Simulation time 64955473 ps
CPU time 0.76 seconds
Started Jul 20 05:47:01 PM PDT 24
Finished Jul 20 05:47:05 PM PDT 24
Peak memory 200272 kb
Host smart-3e55eb4e-e907-462f-a874-82a64d3868b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743858470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2743858470
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3973788913
Short name T118
Test name
Test status
Simulation time 104238453 ps
CPU time 0.99 seconds
Started Jul 20 05:47:04 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 200276 kb
Host smart-2496e67a-b185-4f3f-b2b3-fc1222fcfd38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973788913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3973788913
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3801624401
Short name T591
Test name
Test status
Simulation time 105454491 ps
CPU time 1.49 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 200408 kb
Host smart-2f57f13b-8ddb-4cbc-90a6-bb2e5c7e7af2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801624401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3801624401
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3502933019
Short name T552
Test name
Test status
Simulation time 134372263 ps
CPU time 1.01 seconds
Started Jul 20 05:47:04 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 200356 kb
Host smart-939d672f-632c-4258-9b3d-f22cd1e4949c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502933019 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3502933019
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1059843816
Short name T545
Test name
Test status
Simulation time 63862223 ps
CPU time 0.79 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:10 PM PDT 24
Peak memory 200268 kb
Host smart-baef84a6-d9cd-454b-9795-338d871e1b3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059843816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1059843816
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1497868890
Short name T116
Test name
Test status
Simulation time 185871644 ps
CPU time 1.43 seconds
Started Jul 20 05:47:07 PM PDT 24
Finished Jul 20 05:47:11 PM PDT 24
Peak memory 200556 kb
Host smart-295e5f92-1064-46e9-b63e-b73927363932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497868890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1497868890
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3523199090
Short name T613
Test name
Test status
Simulation time 195664840 ps
CPU time 1.62 seconds
Started Jul 20 05:47:04 PM PDT 24
Finished Jul 20 05:47:08 PM PDT 24
Peak memory 208676 kb
Host smart-0469e5ba-aedc-42de-8de1-642772447ef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523199090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3523199090
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3915882271
Short name T611
Test name
Test status
Simulation time 519871467 ps
CPU time 1.97 seconds
Started Jul 20 05:47:08 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 200476 kb
Host smart-811ea595-906f-426f-8a2c-35a76513336c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915882271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3915882271
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2307177119
Short name T217
Test name
Test status
Simulation time 78498353 ps
CPU time 0.78 seconds
Started Jul 20 06:09:57 PM PDT 24
Finished Jul 20 06:09:58 PM PDT 24
Peak memory 200280 kb
Host smart-41f5378e-e4a9-4ac3-875c-d84aceee8008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307177119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2307177119
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1662348646
Short name T41
Test name
Test status
Simulation time 1228007757 ps
CPU time 5.47 seconds
Started Jul 20 06:10:01 PM PDT 24
Finished Jul 20 06:10:07 PM PDT 24
Peak memory 229968 kb
Host smart-7a0ec45f-718b-4a3f-b12a-aa1a7ba91705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662348646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1662348646
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1439450964
Short name T133
Test name
Test status
Simulation time 1784168529 ps
CPU time 6.66 seconds
Started Jul 20 06:09:55 PM PDT 24
Finished Jul 20 06:10:02 PM PDT 24
Peak memory 200724 kb
Host smart-ec882733-2151-48b7-9589-43530a69e80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439450964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1439450964
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1305127080
Short name T416
Test name
Test status
Simulation time 100954857 ps
CPU time 1.06 seconds
Started Jul 20 06:10:00 PM PDT 24
Finished Jul 20 06:10:02 PM PDT 24
Peak memory 200448 kb
Host smart-95f7e102-e9b3-4e8b-b06f-1b42842b057b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305127080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1305127080
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.4205612985
Short name T409
Test name
Test status
Simulation time 197193923 ps
CPU time 1.46 seconds
Started Jul 20 06:09:59 PM PDT 24
Finished Jul 20 06:10:02 PM PDT 24
Peak memory 200656 kb
Host smart-1b250e2a-6603-4b7d-8a36-b7ad80db9c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205612985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.4205612985
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3854398273
Short name T335
Test name
Test status
Simulation time 157407472 ps
CPU time 1.82 seconds
Started Jul 20 06:09:59 PM PDT 24
Finished Jul 20 06:10:02 PM PDT 24
Peak memory 200472 kb
Host smart-f5c6326f-2f23-4dcd-8d98-84fa59efdb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854398273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3854398273
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.4093706937
Short name T261
Test name
Test status
Simulation time 155622298 ps
CPU time 1.22 seconds
Started Jul 20 06:09:58 PM PDT 24
Finished Jul 20 06:10:00 PM PDT 24
Peak memory 200448 kb
Host smart-44faccba-6dc0-4df5-9614-0e598b2e0e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093706937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.4093706937
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1735619974
Short name T89
Test name
Test status
Simulation time 66733330 ps
CPU time 0.74 seconds
Started Jul 20 06:10:05 PM PDT 24
Finished Jul 20 06:10:06 PM PDT 24
Peak memory 200276 kb
Host smart-040847e1-8392-4147-8dda-52fcd793a824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735619974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1735619974
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2597007745
Short name T369
Test name
Test status
Simulation time 1226295517 ps
CPU time 5.3 seconds
Started Jul 20 06:10:04 PM PDT 24
Finished Jul 20 06:10:09 PM PDT 24
Peak memory 221796 kb
Host smart-5eb92f5f-c8b3-4498-b4a6-667a70855de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597007745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2597007745
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1389357546
Short name T173
Test name
Test status
Simulation time 243750586 ps
CPU time 1.01 seconds
Started Jul 20 06:10:02 PM PDT 24
Finished Jul 20 06:10:04 PM PDT 24
Peak memory 217492 kb
Host smart-2ea51ebb-8e2e-441b-a4b7-5ba47e3f3638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389357546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1389357546
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.80670089
Short name T23
Test name
Test status
Simulation time 102076139 ps
CPU time 0.77 seconds
Started Jul 20 06:09:57 PM PDT 24
Finished Jul 20 06:09:58 PM PDT 24
Peak memory 200256 kb
Host smart-21f62329-2a2a-45ad-81e0-3c7eaa43cbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80670089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.80670089
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.738915553
Short name T435
Test name
Test status
Simulation time 1815622908 ps
CPU time 6.55 seconds
Started Jul 20 06:09:59 PM PDT 24
Finished Jul 20 06:10:06 PM PDT 24
Peak memory 200728 kb
Host smart-b4937c53-5311-4f5a-9c1f-e17c32cd2f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738915553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.738915553
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1810313239
Short name T83
Test name
Test status
Simulation time 8294229261 ps
CPU time 15.05 seconds
Started Jul 20 06:10:05 PM PDT 24
Finished Jul 20 06:10:21 PM PDT 24
Peak memory 217308 kb
Host smart-a1ca46ab-70ee-47ff-b275-fc1a492766f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810313239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1810313239
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1360180073
Short name T176
Test name
Test status
Simulation time 146275738 ps
CPU time 1.21 seconds
Started Jul 20 06:10:02 PM PDT 24
Finished Jul 20 06:10:04 PM PDT 24
Peak memory 200440 kb
Host smart-801c61a4-f59d-402b-bfcd-68494e81c662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360180073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1360180073
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.990468614
Short name T382
Test name
Test status
Simulation time 195619922 ps
CPU time 1.4 seconds
Started Jul 20 06:10:00 PM PDT 24
Finished Jul 20 06:10:02 PM PDT 24
Peak memory 200652 kb
Host smart-10b88c67-b992-468d-913a-1e839ac680b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990468614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.990468614
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.376787883
Short name T451
Test name
Test status
Simulation time 3454479693 ps
CPU time 15.2 seconds
Started Jul 20 06:10:04 PM PDT 24
Finished Jul 20 06:10:19 PM PDT 24
Peak memory 208988 kb
Host smart-9e05dd54-a879-45a6-b646-0f192aa492ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376787883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.376787883
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.114008965
Short name T487
Test name
Test status
Simulation time 499488474 ps
CPU time 2.68 seconds
Started Jul 20 06:10:06 PM PDT 24
Finished Jul 20 06:10:10 PM PDT 24
Peak memory 200508 kb
Host smart-f148d914-0c8c-4f8f-99cc-f459a5814f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114008965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.114008965
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.46311668
Short name T256
Test name
Test status
Simulation time 276405961 ps
CPU time 1.62 seconds
Started Jul 20 06:10:02 PM PDT 24
Finished Jul 20 06:10:04 PM PDT 24
Peak memory 200364 kb
Host smart-a57f8477-6e81-40cf-993b-7896737ffb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46311668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.46311668
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1810110265
Short name T441
Test name
Test status
Simulation time 245484993 ps
CPU time 1.01 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:10:50 PM PDT 24
Peak memory 217468 kb
Host smart-09c2529f-693e-4679-b0a0-434b3267ba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810110265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1810110265
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.364193396
Short name T341
Test name
Test status
Simulation time 122114151 ps
CPU time 0.8 seconds
Started Jul 20 06:10:46 PM PDT 24
Finished Jul 20 06:10:47 PM PDT 24
Peak memory 200188 kb
Host smart-70414d42-287c-4f49-8fcb-cc4f121a7ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364193396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.364193396
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.964504317
Short name T403
Test name
Test status
Simulation time 1743290677 ps
CPU time 7.26 seconds
Started Jul 20 06:10:50 PM PDT 24
Finished Jul 20 06:11:00 PM PDT 24
Peak memory 200780 kb
Host smart-54227a5f-1e93-47b2-a495-4a18b77b67f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964504317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.964504317
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2064215524
Short name T170
Test name
Test status
Simulation time 98649000 ps
CPU time 1.05 seconds
Started Jul 20 06:10:46 PM PDT 24
Finished Jul 20 06:10:48 PM PDT 24
Peak memory 200456 kb
Host smart-4b9c405c-b9e9-4c68-97a5-4169e5ef163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064215524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2064215524
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3972136370
Short name T398
Test name
Test status
Simulation time 127362483 ps
CPU time 1.2 seconds
Started Jul 20 06:10:46 PM PDT 24
Finished Jul 20 06:10:48 PM PDT 24
Peak memory 200592 kb
Host smart-87a218a2-8f2d-483b-a519-1d93a92d297e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972136370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3972136370
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.618324126
Short name T347
Test name
Test status
Simulation time 5878163203 ps
CPU time 29.24 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:11:18 PM PDT 24
Peak memory 200792 kb
Host smart-8436423d-8906-4452-9dec-9b92a96fda35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618324126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.618324126
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.691219292
Short name T258
Test name
Test status
Simulation time 144121699 ps
CPU time 1.94 seconds
Started Jul 20 06:10:55 PM PDT 24
Finished Jul 20 06:11:00 PM PDT 24
Peak memory 200468 kb
Host smart-01c7ecea-fcc3-488c-8361-cdca3535dc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691219292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.691219292
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1073660602
Short name T153
Test name
Test status
Simulation time 67163345 ps
CPU time 0.77 seconds
Started Jul 20 06:10:41 PM PDT 24
Finished Jul 20 06:10:42 PM PDT 24
Peak memory 200276 kb
Host smart-9c090084-86f5-4fd3-82ea-eea5eb428414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073660602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1073660602
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3204643949
Short name T39
Test name
Test status
Simulation time 2347765617 ps
CPU time 8.27 seconds
Started Jul 20 06:10:44 PM PDT 24
Finished Jul 20 06:10:53 PM PDT 24
Peak memory 217932 kb
Host smart-b180acc5-4b14-4644-b9f3-11cffabc1dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204643949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3204643949
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2651635395
Short name T143
Test name
Test status
Simulation time 243489257 ps
CPU time 1.08 seconds
Started Jul 20 06:10:36 PM PDT 24
Finished Jul 20 06:10:38 PM PDT 24
Peak memory 217428 kb
Host smart-b0231bed-5601-4901-825d-d44010930d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651635395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2651635395
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.941873864
Short name T443
Test name
Test status
Simulation time 98991371 ps
CPU time 0.77 seconds
Started Jul 20 06:10:39 PM PDT 24
Finished Jul 20 06:10:40 PM PDT 24
Peak memory 200264 kb
Host smart-721029d7-fda8-4d0b-97f6-54b356190f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941873864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.941873864
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1982056236
Short name T385
Test name
Test status
Simulation time 1468372731 ps
CPU time 5.49 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:56 PM PDT 24
Peak memory 200772 kb
Host smart-76c5e0e7-b329-49ac-8cf7-21df113aec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982056236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1982056236
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3437328430
Short name T539
Test name
Test status
Simulation time 105650199 ps
CPU time 1.05 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:10:51 PM PDT 24
Peak memory 200356 kb
Host smart-cc3c2042-2d1f-4230-a316-f5c1002b6592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437328430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3437328430
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.964528619
Short name T517
Test name
Test status
Simulation time 118449579 ps
CPU time 1.25 seconds
Started Jul 20 06:10:52 PM PDT 24
Finished Jul 20 06:10:56 PM PDT 24
Peak memory 200672 kb
Host smart-c97c95ff-76ea-4ef2-bd9e-59da674fef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964528619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.964528619
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3241968535
Short name T502
Test name
Test status
Simulation time 7686013041 ps
CPU time 26.6 seconds
Started Jul 20 06:10:53 PM PDT 24
Finished Jul 20 06:11:22 PM PDT 24
Peak memory 200800 kb
Host smart-d8b59342-508e-47c4-b91e-0781051e0943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241968535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3241968535
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1708551342
Short name T192
Test name
Test status
Simulation time 132453105 ps
CPU time 1.54 seconds
Started Jul 20 06:10:46 PM PDT 24
Finished Jul 20 06:10:48 PM PDT 24
Peak memory 208644 kb
Host smart-123b43d2-9261-4339-bc07-91d1adf5a4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708551342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1708551342
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1462876087
Short name T463
Test name
Test status
Simulation time 141368356 ps
CPU time 1.09 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:51 PM PDT 24
Peak memory 200448 kb
Host smart-04b8c7e6-4c82-43b5-b1a1-ec2160a6dc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462876087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1462876087
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3425899076
Short name T291
Test name
Test status
Simulation time 126858035 ps
CPU time 0.9 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:10:54 PM PDT 24
Peak memory 200244 kb
Host smart-7b8b9ab7-8d7e-484a-b6b8-4e6a99d8b042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425899076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3425899076
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.4153107267
Short name T55
Test name
Test status
Simulation time 1223697874 ps
CPU time 5.21 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:10:59 PM PDT 24
Peak memory 217848 kb
Host smart-598a1fc9-f066-4a30-992a-3c02e0da3140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153107267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.4153107267
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3516393212
Short name T360
Test name
Test status
Simulation time 243651237 ps
CPU time 1.18 seconds
Started Jul 20 06:10:52 PM PDT 24
Finished Jul 20 06:10:55 PM PDT 24
Peak memory 217552 kb
Host smart-fad48054-bea9-44ca-a9c5-119aa2a20217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516393212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3516393212
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1990887825
Short name T290
Test name
Test status
Simulation time 159320589 ps
CPU time 0.84 seconds
Started Jul 20 06:10:40 PM PDT 24
Finished Jul 20 06:10:41 PM PDT 24
Peak memory 200272 kb
Host smart-f9219fb3-ae48-4034-9536-358f7d115648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990887825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1990887825
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1375304531
Short name T481
Test name
Test status
Simulation time 909831404 ps
CPU time 5.02 seconds
Started Jul 20 06:10:46 PM PDT 24
Finished Jul 20 06:10:52 PM PDT 24
Peak memory 200776 kb
Host smart-dd60572c-0520-45bb-a335-6f93d141b12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375304531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1375304531
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.833888887
Short name T254
Test name
Test status
Simulation time 151328699 ps
CPU time 1.14 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:10:55 PM PDT 24
Peak memory 200464 kb
Host smart-530cc015-27cb-4f49-b720-dd5fb0c41071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833888887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.833888887
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3559189647
Short name T190
Test name
Test status
Simulation time 210611484 ps
CPU time 1.49 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:52 PM PDT 24
Peak memory 200604 kb
Host smart-c7c7918d-8607-467e-9fcf-066ee554e185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559189647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3559189647
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.299968060
Short name T230
Test name
Test status
Simulation time 229416594 ps
CPU time 1.28 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:53 PM PDT 24
Peak memory 200380 kb
Host smart-92cb5bc3-6e34-439b-b1b0-8de66883b5d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299968060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.299968060
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3373154594
Short name T226
Test name
Test status
Simulation time 274831936 ps
CPU time 1.82 seconds
Started Jul 20 06:10:44 PM PDT 24
Finished Jul 20 06:10:47 PM PDT 24
Peak memory 200496 kb
Host smart-f7e61aa9-2c10-420d-8648-3173b1340334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373154594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3373154594
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.611260563
Short name T210
Test name
Test status
Simulation time 141615479 ps
CPU time 1.19 seconds
Started Jul 20 06:10:55 PM PDT 24
Finished Jul 20 06:10:58 PM PDT 24
Peak memory 200456 kb
Host smart-73abc1d2-1cf3-496a-804d-df198ac3a945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611260563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.611260563
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2479369274
Short name T266
Test name
Test status
Simulation time 81321185 ps
CPU time 0.78 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:10:50 PM PDT 24
Peak memory 200288 kb
Host smart-dbefcda7-b0a3-4687-8189-7a8bedf1ffba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479369274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2479369274
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3306764242
Short name T383
Test name
Test status
Simulation time 1236037586 ps
CPU time 5.65 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:10:54 PM PDT 24
Peak memory 217776 kb
Host smart-34fef43b-4129-40f0-bed8-3d4b1bb6fdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306764242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3306764242
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2718852316
Short name T233
Test name
Test status
Simulation time 244245007 ps
CPU time 1.07 seconds
Started Jul 20 06:10:50 PM PDT 24
Finished Jul 20 06:10:53 PM PDT 24
Peak memory 217376 kb
Host smart-6bcce171-aeb6-4582-a8a3-ecd44abd238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718852316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2718852316
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3045455600
Short name T298
Test name
Test status
Simulation time 141153985 ps
CPU time 0.8 seconds
Started Jul 20 06:10:53 PM PDT 24
Finished Jul 20 06:10:57 PM PDT 24
Peak memory 200256 kb
Host smart-bd90ca77-2703-481a-88e9-9ab34c74bca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045455600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3045455600
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2148416382
Short name T105
Test name
Test status
Simulation time 1365630247 ps
CPU time 5.35 seconds
Started Jul 20 06:10:54 PM PDT 24
Finished Jul 20 06:11:02 PM PDT 24
Peak memory 200716 kb
Host smart-162cd538-f2ff-4279-9afc-166dca49f128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148416382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2148416382
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2023427058
Short name T437
Test name
Test status
Simulation time 180914823 ps
CPU time 1.14 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:10:55 PM PDT 24
Peak memory 200448 kb
Host smart-88392b21-3941-4553-91f6-d52f607a3673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023427058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2023427058
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2731542929
Short name T135
Test name
Test status
Simulation time 248414005 ps
CPU time 1.5 seconds
Started Jul 20 06:10:50 PM PDT 24
Finished Jul 20 06:10:54 PM PDT 24
Peak memory 200672 kb
Host smart-86b2769c-23a4-4269-8618-095457d00902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731542929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2731542929
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2750173820
Short name T469
Test name
Test status
Simulation time 5423747572 ps
CPU time 19.34 seconds
Started Jul 20 06:10:56 PM PDT 24
Finished Jul 20 06:11:18 PM PDT 24
Peak memory 208992 kb
Host smart-88e39c06-2502-4f54-9264-fcb039a880de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750173820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2750173820
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1339587654
Short name T2
Test name
Test status
Simulation time 459541105 ps
CPU time 2.44 seconds
Started Jul 20 06:10:56 PM PDT 24
Finished Jul 20 06:11:01 PM PDT 24
Peak memory 200512 kb
Host smart-d5f23400-c06a-4322-ac2e-ac1f79a1d4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339587654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1339587654
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2761135349
Short name T330
Test name
Test status
Simulation time 179319375 ps
CPU time 1.28 seconds
Started Jul 20 06:10:55 PM PDT 24
Finished Jul 20 06:10:59 PM PDT 24
Peak memory 200452 kb
Host smart-ddd33e66-d1d3-417d-adc4-a89f9fdd596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761135349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2761135349
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2328558663
Short name T260
Test name
Test status
Simulation time 81706697 ps
CPU time 0.82 seconds
Started Jul 20 06:10:50 PM PDT 24
Finished Jul 20 06:10:54 PM PDT 24
Peak memory 200276 kb
Host smart-4985d3ce-c3e3-435a-ba1f-04744a65ade9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328558663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2328558663
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1771971563
Short name T498
Test name
Test status
Simulation time 1913714260 ps
CPU time 7.22 seconds
Started Jul 20 06:10:53 PM PDT 24
Finished Jul 20 06:11:03 PM PDT 24
Peak memory 221712 kb
Host smart-6b97459e-23b8-446c-b4e8-e5996833c47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771971563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1771971563
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2414031760
Short name T158
Test name
Test status
Simulation time 243526395 ps
CPU time 1.18 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:10:51 PM PDT 24
Peak memory 217548 kb
Host smart-1b3f1fac-70b2-4145-bd0c-572ae6ecd873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414031760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2414031760
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4077829206
Short name T456
Test name
Test status
Simulation time 219777136 ps
CPU time 0.95 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:10:51 PM PDT 24
Peak memory 200276 kb
Host smart-df2db8a1-fc1e-491b-9858-5b738cf2bf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077829206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4077829206
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3013972053
Short name T464
Test name
Test status
Simulation time 1571874568 ps
CPU time 5.61 seconds
Started Jul 20 06:10:52 PM PDT 24
Finished Jul 20 06:11:00 PM PDT 24
Peak memory 200720 kb
Host smart-f676b317-8a61-486d-9306-07d7c0c56e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013972053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3013972053
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2949286715
Short name T231
Test name
Test status
Simulation time 108700651 ps
CPU time 1.05 seconds
Started Jul 20 06:10:53 PM PDT 24
Finished Jul 20 06:10:57 PM PDT 24
Peak memory 200456 kb
Host smart-0916608b-ae78-451f-adee-b8b3a578584a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949286715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2949286715
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2906094826
Short name T459
Test name
Test status
Simulation time 247619632 ps
CPU time 1.47 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:10:55 PM PDT 24
Peak memory 200568 kb
Host smart-3248af56-abba-4896-b241-0693788737e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906094826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2906094826
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3854849538
Short name T323
Test name
Test status
Simulation time 9197814775 ps
CPU time 31.56 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:11:21 PM PDT 24
Peak memory 209032 kb
Host smart-e409f609-e675-4aae-a888-bfe20dcfce85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854849538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3854849538
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1659213267
Short name T1
Test name
Test status
Simulation time 311662575 ps
CPU time 2.05 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:52 PM PDT 24
Peak memory 208668 kb
Host smart-5ff45f06-ea95-4dce-b1a1-c614a5b1e66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659213267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1659213267
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.753555615
Short name T362
Test name
Test status
Simulation time 131528451 ps
CPU time 1.12 seconds
Started Jul 20 06:10:52 PM PDT 24
Finished Jul 20 06:10:56 PM PDT 24
Peak memory 200448 kb
Host smart-6d6e7ee6-3875-4275-bc35-0f2b73ff450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753555615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.753555615
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.107228353
Short name T259
Test name
Test status
Simulation time 71024471 ps
CPU time 0.77 seconds
Started Jul 20 06:10:56 PM PDT 24
Finished Jul 20 06:10:59 PM PDT 24
Peak memory 200276 kb
Host smart-e41e54e6-0d9b-4c66-b245-2b9e5597c6bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107228353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.107228353
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3822028168
Short name T280
Test name
Test status
Simulation time 1871085041 ps
CPU time 7.42 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:10:58 PM PDT 24
Peak memory 217824 kb
Host smart-2acccbfc-04ab-42b8-b05e-0ec1d9dbfc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822028168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3822028168
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.745264137
Short name T363
Test name
Test status
Simulation time 244949456 ps
CPU time 1.12 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:52 PM PDT 24
Peak memory 217488 kb
Host smart-6b07f407-fa61-4eb4-ac93-99f34c4e8a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745264137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.745264137
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2114082307
Short name T244
Test name
Test status
Simulation time 163329894 ps
CPU time 0.84 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:10:51 PM PDT 24
Peak memory 200272 kb
Host smart-3a38af38-bc2b-48b2-93b8-29890cf72757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114082307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2114082307
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3388460935
Short name T113
Test name
Test status
Simulation time 1321796687 ps
CPU time 4.92 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:10:59 PM PDT 24
Peak memory 200716 kb
Host smart-24a8210b-1ba6-44a2-b425-9af625702706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388460935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3388460935
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2446693728
Short name T450
Test name
Test status
Simulation time 174289358 ps
CPU time 1.15 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:10:55 PM PDT 24
Peak memory 200452 kb
Host smart-f9449ba4-cafc-4011-83d2-c5ed24b9757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446693728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2446693728
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3233295395
Short name T236
Test name
Test status
Simulation time 114535683 ps
CPU time 1.18 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:52 PM PDT 24
Peak memory 200708 kb
Host smart-99173c2a-4cc8-4346-a7cf-5c7734d00ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233295395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3233295395
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2283112549
Short name T483
Test name
Test status
Simulation time 12858671289 ps
CPU time 45.53 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:11:39 PM PDT 24
Peak memory 208864 kb
Host smart-016faf4d-e573-41dd-b7c1-be6b8a183d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283112549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2283112549
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2884213257
Short name T474
Test name
Test status
Simulation time 330168277 ps
CPU time 2.16 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:10:51 PM PDT 24
Peak memory 208680 kb
Host smart-aabbae79-d2c2-4116-a826-e4d231599818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884213257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2884213257
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3842417929
Short name T482
Test name
Test status
Simulation time 75695955 ps
CPU time 0.81 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:10:54 PM PDT 24
Peak memory 200464 kb
Host smart-fd2554c0-41a6-4064-8060-fb19a634e121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842417929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3842417929
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2842085602
Short name T262
Test name
Test status
Simulation time 66611125 ps
CPU time 0.78 seconds
Started Jul 20 06:10:55 PM PDT 24
Finished Jul 20 06:10:58 PM PDT 24
Peak memory 200268 kb
Host smart-bd4a4e0e-14e9-4de3-b6a6-c7bd80ce375c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842085602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2842085602
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.185026942
Short name T205
Test name
Test status
Simulation time 1231004240 ps
CPU time 5.48 seconds
Started Jul 20 06:10:45 PM PDT 24
Finished Jul 20 06:10:51 PM PDT 24
Peak memory 221772 kb
Host smart-a79cda5e-bd7b-4455-805e-1f538f34dd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185026942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.185026942
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4117525804
Short name T321
Test name
Test status
Simulation time 244703968 ps
CPU time 1.1 seconds
Started Jul 20 06:10:50 PM PDT 24
Finished Jul 20 06:10:54 PM PDT 24
Peak memory 217480 kb
Host smart-2ecbb3c7-7bf0-41b4-ae96-0ecbc4ae6dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117525804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.4117525804
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3036656940
Short name T16
Test name
Test status
Simulation time 197983364 ps
CPU time 0.96 seconds
Started Jul 20 06:10:53 PM PDT 24
Finished Jul 20 06:10:57 PM PDT 24
Peak memory 200272 kb
Host smart-810fb62d-59df-468f-9b31-31225681277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036656940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3036656940
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1578933368
Short name T304
Test name
Test status
Simulation time 1387955476 ps
CPU time 5.51 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:57 PM PDT 24
Peak memory 200772 kb
Host smart-dd8600b8-036c-4aaa-8a51-f387bea009ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578933368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1578933368
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1027719907
Short name T367
Test name
Test status
Simulation time 142743979 ps
CPU time 1.1 seconds
Started Jul 20 06:10:46 PM PDT 24
Finished Jul 20 06:10:47 PM PDT 24
Peak memory 200376 kb
Host smart-1493ca85-5075-4d84-8393-edc1837045dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027719907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1027719907
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3542235650
Short name T204
Test name
Test status
Simulation time 255860000 ps
CPU time 1.59 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:10:55 PM PDT 24
Peak memory 200660 kb
Host smart-58608987-3a9f-4bcb-915a-a6e8e2d16721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542235650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3542235650
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.686872370
Short name T44
Test name
Test status
Simulation time 6263279492 ps
CPU time 28.05 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:11:18 PM PDT 24
Peak memory 200804 kb
Host smart-6d0359bb-278a-4938-adb9-35eac473c999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686872370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.686872370
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3774404025
Short name T529
Test name
Test status
Simulation time 561040245 ps
CPU time 3.08 seconds
Started Jul 20 06:10:47 PM PDT 24
Finished Jul 20 06:10:50 PM PDT 24
Peak memory 200464 kb
Host smart-996e1772-dd10-4294-80ca-6894fb49275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774404025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3774404025
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.835007484
Short name T240
Test name
Test status
Simulation time 141623289 ps
CPU time 1.09 seconds
Started Jul 20 06:10:50 PM PDT 24
Finished Jul 20 06:10:54 PM PDT 24
Peak memory 200460 kb
Host smart-492ab53a-2ce9-4341-a516-07484072b284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835007484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.835007484
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.617772898
Short name T540
Test name
Test status
Simulation time 75563767 ps
CPU time 0.8 seconds
Started Jul 20 06:10:46 PM PDT 24
Finished Jul 20 06:10:48 PM PDT 24
Peak memory 200252 kb
Host smart-ccbb3eaf-1520-42fb-9d38-91b6561cba8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617772898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.617772898
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2857383007
Short name T297
Test name
Test status
Simulation time 1904000709 ps
CPU time 6.67 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:11:00 PM PDT 24
Peak memory 217512 kb
Host smart-ebbb6742-9a18-4e6b-a22d-3bedfcf9ca6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857383007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2857383007
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.584812645
Short name T249
Test name
Test status
Simulation time 243865713 ps
CPU time 1.11 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:53 PM PDT 24
Peak memory 217532 kb
Host smart-582e0981-10aa-4084-b6cb-2097d1a95a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584812645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.584812645
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1373125313
Short name T184
Test name
Test status
Simulation time 122950190 ps
CPU time 0.83 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:51 PM PDT 24
Peak memory 200260 kb
Host smart-e6253a43-9a34-476e-b2ff-1d30264d6aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373125313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1373125313
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1004472647
Short name T380
Test name
Test status
Simulation time 1525548444 ps
CPU time 5.91 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:57 PM PDT 24
Peak memory 200768 kb
Host smart-d0b47bd8-880b-4e08-862f-a02c09d52312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004472647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1004472647
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1828528127
Short name T216
Test name
Test status
Simulation time 200823698 ps
CPU time 1.34 seconds
Started Jul 20 06:10:54 PM PDT 24
Finished Jul 20 06:10:58 PM PDT 24
Peak memory 200664 kb
Host smart-001deec1-83cb-4a79-8118-ed0a20b212e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828528127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1828528127
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.225339484
Short name T373
Test name
Test status
Simulation time 9652821263 ps
CPU time 32.16 seconds
Started Jul 20 06:10:48 PM PDT 24
Finished Jul 20 06:11:21 PM PDT 24
Peak memory 210832 kb
Host smart-866c48c2-0dcc-4ea6-b895-87e762dbb56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225339484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.225339484
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3759726247
Short name T346
Test name
Test status
Simulation time 254652411 ps
CPU time 1.74 seconds
Started Jul 20 06:10:45 PM PDT 24
Finished Jul 20 06:10:47 PM PDT 24
Peak memory 200460 kb
Host smart-a5cb6e9a-c9d4-4e9b-856e-28bc737b37e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759726247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3759726247
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3161395480
Short name T345
Test name
Test status
Simulation time 63314699 ps
CPU time 0.76 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:52 PM PDT 24
Peak memory 200436 kb
Host smart-67810393-70a1-48e3-8243-7d3da4fa5182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161395480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3161395480
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2097915535
Short name T356
Test name
Test status
Simulation time 80573838 ps
CPU time 0.83 seconds
Started Jul 20 06:10:54 PM PDT 24
Finished Jul 20 06:10:57 PM PDT 24
Peak memory 200252 kb
Host smart-6fe46135-dd0f-47e1-98b1-7f41641d15bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097915535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2097915535
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2705477920
Short name T56
Test name
Test status
Simulation time 1896380940 ps
CPU time 6.73 seconds
Started Jul 20 06:10:53 PM PDT 24
Finished Jul 20 06:11:02 PM PDT 24
Peak memory 221652 kb
Host smart-a0150766-8f92-4147-abdf-08d90b570f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705477920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2705477920
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4238824662
Short name T161
Test name
Test status
Simulation time 245447353 ps
CPU time 1.08 seconds
Started Jul 20 06:10:55 PM PDT 24
Finished Jul 20 06:10:59 PM PDT 24
Peak memory 217460 kb
Host smart-82cbf0dc-e379-48e7-9729-8e03a2f5941e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238824662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4238824662
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.164407548
Short name T475
Test name
Test status
Simulation time 117568241 ps
CPU time 0.8 seconds
Started Jul 20 06:10:56 PM PDT 24
Finished Jul 20 06:10:59 PM PDT 24
Peak memory 200184 kb
Host smart-799cf68d-95bf-4b99-836e-6f1f937340a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164407548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.164407548
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.626833994
Short name T410
Test name
Test status
Simulation time 1365824242 ps
CPU time 5.07 seconds
Started Jul 20 06:10:54 PM PDT 24
Finished Jul 20 06:11:01 PM PDT 24
Peak memory 200716 kb
Host smart-f2040172-b33c-4f0c-a305-c7b10f00c31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626833994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.626833994
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2642174765
Short name T84
Test name
Test status
Simulation time 175786086 ps
CPU time 1.16 seconds
Started Jul 20 06:10:57 PM PDT 24
Finished Jul 20 06:11:01 PM PDT 24
Peak memory 200460 kb
Host smart-fa0b5382-942d-40fa-90b7-2b8f8c10144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642174765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2642174765
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.778789254
Short name T530
Test name
Test status
Simulation time 259698687 ps
CPU time 1.46 seconds
Started Jul 20 06:10:57 PM PDT 24
Finished Jul 20 06:11:01 PM PDT 24
Peak memory 200664 kb
Host smart-d2bc9eae-7ec5-4d05-963c-c854662d5ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778789254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.778789254
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3570346089
Short name T253
Test name
Test status
Simulation time 988448239 ps
CPU time 4.88 seconds
Started Jul 20 06:10:58 PM PDT 24
Finished Jul 20 06:11:05 PM PDT 24
Peak memory 200732 kb
Host smart-636935d8-0044-42e5-bdc6-ef5228df12d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570346089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3570346089
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3749016408
Short name T172
Test name
Test status
Simulation time 274816195 ps
CPU time 1.91 seconds
Started Jul 20 06:10:57 PM PDT 24
Finished Jul 20 06:11:01 PM PDT 24
Peak memory 200476 kb
Host smart-d49c5b65-39e6-42f1-9beb-c6e140aa2252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749016408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3749016408
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.904411568
Short name T404
Test name
Test status
Simulation time 243201344 ps
CPU time 1.43 seconds
Started Jul 20 06:10:54 PM PDT 24
Finished Jul 20 06:10:58 PM PDT 24
Peak memory 200472 kb
Host smart-93771048-8974-4ea1-9d3b-c697be4e1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904411568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.904411568
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1839834446
Short name T144
Test name
Test status
Simulation time 68863416 ps
CPU time 0.78 seconds
Started Jul 20 06:11:00 PM PDT 24
Finished Jul 20 06:11:03 PM PDT 24
Peak memory 200272 kb
Host smart-d0b6e123-d6b4-48c4-9d53-211d3cd93884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839834446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1839834446
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.833613856
Short name T537
Test name
Test status
Simulation time 1237338453 ps
CPU time 5.29 seconds
Started Jul 20 06:10:52 PM PDT 24
Finished Jul 20 06:11:00 PM PDT 24
Peak memory 217828 kb
Host smart-e4812846-843b-41e0-81dd-d3fad295cc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833613856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.833613856
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2691267224
Short name T296
Test name
Test status
Simulation time 244692050 ps
CPU time 1.07 seconds
Started Jul 20 06:10:58 PM PDT 24
Finished Jul 20 06:11:01 PM PDT 24
Peak memory 217468 kb
Host smart-5fe861ab-69e2-4b65-aacf-b99c05517b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691267224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2691267224
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1527863471
Short name T252
Test name
Test status
Simulation time 144534312 ps
CPU time 0.83 seconds
Started Jul 20 06:10:53 PM PDT 24
Finished Jul 20 06:10:57 PM PDT 24
Peak memory 200416 kb
Host smart-f36f66be-6793-4d7d-bd99-10d90a37cf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527863471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1527863471
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.4051806610
Short name T388
Test name
Test status
Simulation time 704618311 ps
CPU time 3.67 seconds
Started Jul 20 06:10:56 PM PDT 24
Finished Jul 20 06:11:02 PM PDT 24
Peak memory 200736 kb
Host smart-e073b5e4-2b9c-449a-a5d9-4606eaeec92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051806610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.4051806610
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.622412065
Short name T271
Test name
Test status
Simulation time 179568879 ps
CPU time 1.19 seconds
Started Jul 20 06:10:58 PM PDT 24
Finished Jul 20 06:11:01 PM PDT 24
Peak memory 200408 kb
Host smart-519a7e1f-6006-481f-aaf7-bd9d51694cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622412065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.622412065
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.4188474334
Short name T538
Test name
Test status
Simulation time 197873992 ps
CPU time 1.35 seconds
Started Jul 20 06:10:57 PM PDT 24
Finished Jul 20 06:11:00 PM PDT 24
Peak memory 200664 kb
Host smart-3b66ad77-7ef4-4664-880d-d078402cc0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188474334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.4188474334
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3278457752
Short name T515
Test name
Test status
Simulation time 6187002440 ps
CPU time 21.76 seconds
Started Jul 20 06:10:58 PM PDT 24
Finished Jul 20 06:11:22 PM PDT 24
Peak memory 200760 kb
Host smart-fe6a1f9c-8763-4df6-ae3b-731aaf704514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278457752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3278457752
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.426886724
Short name T227
Test name
Test status
Simulation time 315281883 ps
CPU time 2.45 seconds
Started Jul 20 06:10:57 PM PDT 24
Finished Jul 20 06:11:02 PM PDT 24
Peak memory 200416 kb
Host smart-8131d744-9232-4962-a37b-85baf6cc17a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426886724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.426886724
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.698041811
Short name T395
Test name
Test status
Simulation time 113537341 ps
CPU time 0.96 seconds
Started Jul 20 06:10:58 PM PDT 24
Finished Jul 20 06:11:01 PM PDT 24
Peak memory 200448 kb
Host smart-98447a96-fa1e-4412-8734-0cdf244daba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698041811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.698041811
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2350330095
Short name T473
Test name
Test status
Simulation time 72358342 ps
CPU time 0.76 seconds
Started Jul 20 06:10:06 PM PDT 24
Finished Jul 20 06:10:08 PM PDT 24
Peak memory 200276 kb
Host smart-b2541111-20f5-4ac1-82a6-85af2ca94b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350330095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2350330095
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3848008538
Short name T65
Test name
Test status
Simulation time 1883040629 ps
CPU time 7.13 seconds
Started Jul 20 06:10:05 PM PDT 24
Finished Jul 20 06:10:13 PM PDT 24
Peak memory 217788 kb
Host smart-fa07847d-d63f-43c4-b319-7b0cf9727b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848008538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3848008538
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.131126190
Short name T371
Test name
Test status
Simulation time 244289768 ps
CPU time 1.07 seconds
Started Jul 20 06:10:02 PM PDT 24
Finished Jul 20 06:10:04 PM PDT 24
Peak memory 217532 kb
Host smart-7e3a2263-c188-430c-8efc-5fc824ddf0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131126190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.131126190
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1150746390
Short name T22
Test name
Test status
Simulation time 145815913 ps
CPU time 0.83 seconds
Started Jul 20 06:10:05 PM PDT 24
Finished Jul 20 06:10:06 PM PDT 24
Peak memory 200260 kb
Host smart-b74db4be-270e-46e6-9256-67bb48663fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150746390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1150746390
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.959628417
Short name T477
Test name
Test status
Simulation time 989616023 ps
CPU time 4.76 seconds
Started Jul 20 06:10:06 PM PDT 24
Finished Jul 20 06:10:12 PM PDT 24
Peak memory 200684 kb
Host smart-6497dc17-fff5-42ef-adc3-8ccee75e4c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959628417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.959628417
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3954897987
Short name T78
Test name
Test status
Simulation time 8541310174 ps
CPU time 13.35 seconds
Started Jul 20 06:10:06 PM PDT 24
Finished Jul 20 06:10:20 PM PDT 24
Peak memory 221188 kb
Host smart-bb6ad558-ebbd-45df-8a81-5b902469d674
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954897987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3954897987
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4053863864
Short name T159
Test name
Test status
Simulation time 103576448 ps
CPU time 1.07 seconds
Started Jul 20 06:10:02 PM PDT 24
Finished Jul 20 06:10:04 PM PDT 24
Peak memory 200408 kb
Host smart-db928186-a489-4264-8706-4a23ee550289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053863864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4053863864
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3904634088
Short name T507
Test name
Test status
Simulation time 119623789 ps
CPU time 1.14 seconds
Started Jul 20 06:10:05 PM PDT 24
Finished Jul 20 06:10:07 PM PDT 24
Peak memory 200704 kb
Host smart-8ae0008b-4c85-42f4-91cc-adbb27d526c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904634088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3904634088
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1158973327
Short name T396
Test name
Test status
Simulation time 9405514625 ps
CPU time 34.12 seconds
Started Jul 20 06:10:02 PM PDT 24
Finished Jul 20 06:10:37 PM PDT 24
Peak memory 209004 kb
Host smart-8d2f70a5-79f5-4d96-b521-bb0790e11c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158973327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1158973327
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.469782423
Short name T368
Test name
Test status
Simulation time 118492823 ps
CPU time 1.46 seconds
Started Jul 20 06:10:03 PM PDT 24
Finished Jul 20 06:10:05 PM PDT 24
Peak memory 200488 kb
Host smart-1213e2ff-0817-4d93-a4ad-c7aed9876d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469782423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.469782423
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1177440499
Short name T283
Test name
Test status
Simulation time 98659904 ps
CPU time 0.89 seconds
Started Jul 20 06:10:06 PM PDT 24
Finished Jul 20 06:10:07 PM PDT 24
Peak memory 200464 kb
Host smart-f73cefce-0527-40c8-a7e8-3a93c3db34f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177440499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1177440499
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1266479401
Short name T212
Test name
Test status
Simulation time 62568647 ps
CPU time 0.74 seconds
Started Jul 20 06:10:58 PM PDT 24
Finished Jul 20 06:11:01 PM PDT 24
Peak memory 200260 kb
Host smart-b4b80a53-0910-4c46-a134-4ba5beab9d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266479401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1266479401
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.4168968350
Short name T307
Test name
Test status
Simulation time 1220497830 ps
CPU time 5.83 seconds
Started Jul 20 06:10:58 PM PDT 24
Finished Jul 20 06:11:06 PM PDT 24
Peak memory 217548 kb
Host smart-81d09949-739f-468e-a525-aba8579ba867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168968350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.4168968350
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3183339594
Short name T155
Test name
Test status
Simulation time 243998455 ps
CPU time 1.08 seconds
Started Jul 20 06:11:00 PM PDT 24
Finished Jul 20 06:11:03 PM PDT 24
Peak memory 217532 kb
Host smart-009624af-adb0-47c8-820f-944333e2ea53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183339594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3183339594
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3551699173
Short name T19
Test name
Test status
Simulation time 118411013 ps
CPU time 0.81 seconds
Started Jul 20 06:10:52 PM PDT 24
Finished Jul 20 06:10:56 PM PDT 24
Peak memory 200264 kb
Host smart-22b2a366-1a6c-4b04-a73e-5520800b445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551699173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3551699173
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3014202478
Short name T112
Test name
Test status
Simulation time 880824517 ps
CPU time 4.23 seconds
Started Jul 20 06:10:57 PM PDT 24
Finished Jul 20 06:11:04 PM PDT 24
Peak memory 200724 kb
Host smart-74524ee4-1681-4bd7-bab9-014511a44722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014202478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3014202478
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1848361684
Short name T412
Test name
Test status
Simulation time 147120882 ps
CPU time 1.11 seconds
Started Jul 20 06:10:53 PM PDT 24
Finished Jul 20 06:10:57 PM PDT 24
Peak memory 200444 kb
Host smart-f2824bc9-149d-464d-8679-bc0692fb0bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848361684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1848361684
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1472237537
Short name T343
Test name
Test status
Simulation time 256325952 ps
CPU time 1.46 seconds
Started Jul 20 06:10:56 PM PDT 24
Finished Jul 20 06:11:00 PM PDT 24
Peak memory 200668 kb
Host smart-e709e1df-3008-4c00-900c-48193c99b0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472237537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1472237537
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3446502606
Short name T246
Test name
Test status
Simulation time 548658022 ps
CPU time 2.82 seconds
Started Jul 20 06:10:56 PM PDT 24
Finished Jul 20 06:11:02 PM PDT 24
Peak memory 200364 kb
Host smart-5897bbb3-73eb-4714-88e8-9ec0010066c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446502606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3446502606
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3065484577
Short name T309
Test name
Test status
Simulation time 181230628 ps
CPU time 1.26 seconds
Started Jul 20 06:11:00 PM PDT 24
Finished Jul 20 06:11:03 PM PDT 24
Peak memory 200456 kb
Host smart-50fd67d5-6234-4554-a2f5-9191c95be6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065484577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3065484577
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3792135534
Short name T458
Test name
Test status
Simulation time 83732378 ps
CPU time 0.85 seconds
Started Jul 20 06:11:00 PM PDT 24
Finished Jul 20 06:11:02 PM PDT 24
Peak memory 200272 kb
Host smart-555991ad-0ec6-4254-861d-ebec4bd7d5f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792135534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3792135534
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.525999982
Short name T6
Test name
Test status
Simulation time 244364760 ps
CPU time 1.16 seconds
Started Jul 20 06:11:09 PM PDT 24
Finished Jul 20 06:11:11 PM PDT 24
Peak memory 217532 kb
Host smart-dd85b0f5-4541-4e26-bd72-5a46028f6d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525999982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.525999982
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1782506690
Short name T486
Test name
Test status
Simulation time 193573672 ps
CPU time 0.97 seconds
Started Jul 20 06:10:54 PM PDT 24
Finished Jul 20 06:10:58 PM PDT 24
Peak memory 200252 kb
Host smart-50b79be6-2eb6-4b72-9af7-b284bead998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782506690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1782506690
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3675403663
Short name T136
Test name
Test status
Simulation time 1674451580 ps
CPU time 6.43 seconds
Started Jul 20 06:10:54 PM PDT 24
Finished Jul 20 06:11:04 PM PDT 24
Peak memory 200748 kb
Host smart-162418f5-9343-41e5-9671-86a952ecd248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675403663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3675403663
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3178242520
Short name T408
Test name
Test status
Simulation time 139992135 ps
CPU time 1.1 seconds
Started Jul 20 06:10:57 PM PDT 24
Finished Jul 20 06:11:00 PM PDT 24
Peak memory 200464 kb
Host smart-18cf60ea-ad0b-4610-9a76-df348d1aa104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178242520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3178242520
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.126849201
Short name T195
Test name
Test status
Simulation time 118817650 ps
CPU time 1.15 seconds
Started Jul 20 06:11:00 PM PDT 24
Finished Jul 20 06:11:02 PM PDT 24
Peak memory 200648 kb
Host smart-551dc3ba-c399-4e79-8288-7c8f3c55e2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126849201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.126849201
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.666988121
Short name T93
Test name
Test status
Simulation time 2393457297 ps
CPU time 10.91 seconds
Started Jul 20 06:10:58 PM PDT 24
Finished Jul 20 06:11:11 PM PDT 24
Peak memory 210624 kb
Host smart-d517ec49-c486-4109-a59a-0f596ba59c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666988121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.666988121
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2681546817
Short name T250
Test name
Test status
Simulation time 340333607 ps
CPU time 2.24 seconds
Started Jul 20 06:10:59 PM PDT 24
Finished Jul 20 06:11:03 PM PDT 24
Peak memory 200508 kb
Host smart-f929d93c-7026-4bab-8244-2ddfbb2246b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681546817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2681546817
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2983508885
Short name T189
Test name
Test status
Simulation time 209407294 ps
CPU time 1.34 seconds
Started Jul 20 06:10:54 PM PDT 24
Finished Jul 20 06:10:58 PM PDT 24
Peak memory 200436 kb
Host smart-17900883-64bc-463d-8ff2-285288acf9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983508885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2983508885
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3381556192
Short name T406
Test name
Test status
Simulation time 65819736 ps
CPU time 0.73 seconds
Started Jul 20 06:11:06 PM PDT 24
Finished Jul 20 06:11:08 PM PDT 24
Peak memory 200248 kb
Host smart-886c0629-fd43-4664-bddf-388f5230c9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381556192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3381556192
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1276835028
Short name T339
Test name
Test status
Simulation time 2364375336 ps
CPU time 7.91 seconds
Started Jul 20 06:11:06 PM PDT 24
Finished Jul 20 06:11:16 PM PDT 24
Peak memory 217764 kb
Host smart-2bf926e0-f203-454a-bb35-8fb385546682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276835028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1276835028
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.895561094
Short name T188
Test name
Test status
Simulation time 244290455 ps
CPU time 1.13 seconds
Started Jul 20 06:11:05 PM PDT 24
Finished Jul 20 06:11:08 PM PDT 24
Peak memory 217500 kb
Host smart-9f8ce36a-f56d-4c85-8a97-6e034a23049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895561094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.895561094
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1735936980
Short name T201
Test name
Test status
Simulation time 189206399 ps
CPU time 0.85 seconds
Started Jul 20 06:11:04 PM PDT 24
Finished Jul 20 06:11:07 PM PDT 24
Peak memory 200276 kb
Host smart-22778652-765f-41ff-a228-f8281719737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735936980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1735936980
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2057984749
Short name T336
Test name
Test status
Simulation time 2001762825 ps
CPU time 7.46 seconds
Started Jul 20 06:11:04 PM PDT 24
Finished Jul 20 06:11:13 PM PDT 24
Peak memory 200692 kb
Host smart-aa87b8eb-0b60-43bb-8e8d-bb6f471f4788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057984749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2057984749
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1726246924
Short name T263
Test name
Test status
Simulation time 107900088 ps
CPU time 1.09 seconds
Started Jul 20 06:11:01 PM PDT 24
Finished Jul 20 06:11:04 PM PDT 24
Peak memory 200592 kb
Host smart-078b1e5b-71c0-42d5-8d87-7368624445fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726246924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1726246924
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3427226484
Short name T46
Test name
Test status
Simulation time 115320409 ps
CPU time 1.17 seconds
Started Jul 20 06:11:04 PM PDT 24
Finished Jul 20 06:11:07 PM PDT 24
Peak memory 200704 kb
Host smart-bb14d30a-b6ca-47dd-8b9b-bc84a7f18cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427226484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3427226484
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3637060965
Short name T237
Test name
Test status
Simulation time 722238322 ps
CPU time 3.18 seconds
Started Jul 20 06:11:03 PM PDT 24
Finished Jul 20 06:11:08 PM PDT 24
Peak memory 208812 kb
Host smart-3d5e22a5-8dab-4d9d-afff-5c5e48d49ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637060965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3637060965
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.389733394
Short name T313
Test name
Test status
Simulation time 291872450 ps
CPU time 1.97 seconds
Started Jul 20 06:11:03 PM PDT 24
Finished Jul 20 06:11:06 PM PDT 24
Peak memory 200364 kb
Host smart-cc669051-8c17-43ef-a3be-0797b56db54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389733394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.389733394
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1338598081
Short name T265
Test name
Test status
Simulation time 118698824 ps
CPU time 1.05 seconds
Started Jul 20 06:11:06 PM PDT 24
Finished Jul 20 06:11:09 PM PDT 24
Peak memory 200460 kb
Host smart-09069ee1-4971-41fd-b35e-59d824fdf33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338598081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1338598081
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3018274044
Short name T440
Test name
Test status
Simulation time 73565757 ps
CPU time 0.75 seconds
Started Jul 20 06:11:02 PM PDT 24
Finished Jul 20 06:11:04 PM PDT 24
Peak memory 200276 kb
Host smart-a5d0cfea-ccff-44e8-b97c-ced6135c975b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018274044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3018274044
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1826431405
Short name T53
Test name
Test status
Simulation time 2352392593 ps
CPU time 8.1 seconds
Started Jul 20 06:11:00 PM PDT 24
Finished Jul 20 06:11:09 PM PDT 24
Peak memory 217928 kb
Host smart-fb51b5b5-25a9-491d-875a-7568d0f498bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826431405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1826431405
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3901721248
Short name T342
Test name
Test status
Simulation time 245569387 ps
CPU time 1.06 seconds
Started Jul 20 06:11:04 PM PDT 24
Finished Jul 20 06:11:07 PM PDT 24
Peak memory 217436 kb
Host smart-fd64c1b3-a6e6-475e-9a6d-cd4707c5ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901721248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3901721248
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2199871671
Short name T491
Test name
Test status
Simulation time 209574026 ps
CPU time 0.87 seconds
Started Jul 20 06:11:03 PM PDT 24
Finished Jul 20 06:11:05 PM PDT 24
Peak memory 200276 kb
Host smart-2e5ae88b-39c6-4164-8745-6f271cafc1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199871671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2199871671
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3863640626
Short name T92
Test name
Test status
Simulation time 951574795 ps
CPU time 4.88 seconds
Started Jul 20 06:11:06 PM PDT 24
Finished Jul 20 06:11:13 PM PDT 24
Peak memory 200716 kb
Host smart-10df6d85-9ca4-4de0-b6ad-de3398dde926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863640626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3863640626
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1850323968
Short name T479
Test name
Test status
Simulation time 155737507 ps
CPU time 1.29 seconds
Started Jul 20 06:11:02 PM PDT 24
Finished Jul 20 06:11:05 PM PDT 24
Peak memory 200460 kb
Host smart-6916fab9-319c-4611-b8d1-e4a30e0f3db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850323968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1850323968
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3190414542
Short name T532
Test name
Test status
Simulation time 257442031 ps
CPU time 1.49 seconds
Started Jul 20 06:11:02 PM PDT 24
Finished Jul 20 06:11:05 PM PDT 24
Peak memory 200668 kb
Host smart-761a455c-2c7f-4464-b1a4-c25603823113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190414542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3190414542
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.194740786
Short name T461
Test name
Test status
Simulation time 529734983 ps
CPU time 3.35 seconds
Started Jul 20 06:11:04 PM PDT 24
Finished Jul 20 06:11:09 PM PDT 24
Peak memory 200680 kb
Host smart-1cb976dc-5ec7-440d-8962-5b2f96eb553b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194740786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.194740786
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.443063882
Short name T384
Test name
Test status
Simulation time 151029332 ps
CPU time 1.85 seconds
Started Jul 20 06:11:01 PM PDT 24
Finished Jul 20 06:11:04 PM PDT 24
Peak memory 200460 kb
Host smart-703eb1f6-7483-497f-a77c-79a742f733b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443063882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.443063882
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3662590252
Short name T220
Test name
Test status
Simulation time 111656927 ps
CPU time 0.94 seconds
Started Jul 20 06:11:02 PM PDT 24
Finished Jul 20 06:11:04 PM PDT 24
Peak memory 200468 kb
Host smart-2883e1bd-0c4e-4cf3-9b29-e1b2c7f97a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662590252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3662590252
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1800899509
Short name T444
Test name
Test status
Simulation time 61105443 ps
CPU time 0.75 seconds
Started Jul 20 06:11:06 PM PDT 24
Finished Jul 20 06:11:09 PM PDT 24
Peak memory 200276 kb
Host smart-34c47c6a-5449-4e7a-834f-20948ca18950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800899509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1800899509
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3732369649
Short name T54
Test name
Test status
Simulation time 1235119330 ps
CPU time 5.52 seconds
Started Jul 20 06:11:07 PM PDT 24
Finished Jul 20 06:11:14 PM PDT 24
Peak memory 217436 kb
Host smart-531ee4fa-373c-4db9-864d-74efee6cb827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732369649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3732369649
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1897433150
Short name T164
Test name
Test status
Simulation time 244567532 ps
CPU time 1.1 seconds
Started Jul 20 06:11:00 PM PDT 24
Finished Jul 20 06:11:03 PM PDT 24
Peak memory 217472 kb
Host smart-c68a21e7-d0a8-4749-a33c-9f37adbb5b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897433150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1897433150
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2928855719
Short name T489
Test name
Test status
Simulation time 214993770 ps
CPU time 0.91 seconds
Started Jul 20 06:11:06 PM PDT 24
Finished Jul 20 06:11:08 PM PDT 24
Peak memory 200188 kb
Host smart-bde636b4-6a51-4471-9013-8ae14d16a81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928855719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2928855719
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3889237118
Short name T90
Test name
Test status
Simulation time 1514209220 ps
CPU time 5.88 seconds
Started Jul 20 06:11:03 PM PDT 24
Finished Jul 20 06:11:10 PM PDT 24
Peak memory 200768 kb
Host smart-8a1fecd0-ea0f-4647-be59-81e948ecce3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889237118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3889237118
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3184901019
Short name T366
Test name
Test status
Simulation time 152481756 ps
CPU time 1.14 seconds
Started Jul 20 06:11:03 PM PDT 24
Finished Jul 20 06:11:05 PM PDT 24
Peak memory 200452 kb
Host smart-1ee7c178-a4aa-4dfa-bbff-76d89fdead59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184901019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3184901019
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1752981900
Short name T337
Test name
Test status
Simulation time 109943007 ps
CPU time 1.15 seconds
Started Jul 20 06:11:02 PM PDT 24
Finished Jul 20 06:11:05 PM PDT 24
Peak memory 200664 kb
Host smart-792b0eb5-00b2-4ab4-8b79-966a756f340d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752981900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1752981900
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2263221389
Short name T405
Test name
Test status
Simulation time 9149761645 ps
CPU time 30.58 seconds
Started Jul 20 06:11:03 PM PDT 24
Finished Jul 20 06:11:36 PM PDT 24
Peak memory 200756 kb
Host smart-178dce08-ad0c-4ab5-abf7-48929946fda5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263221389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2263221389
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2155180286
Short name T171
Test name
Test status
Simulation time 480246121 ps
CPU time 3 seconds
Started Jul 20 06:11:01 PM PDT 24
Finished Jul 20 06:11:05 PM PDT 24
Peak memory 200468 kb
Host smart-aa81988c-cbe3-45da-a9f5-b263edf91a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155180286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2155180286
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.4126273646
Short name T292
Test name
Test status
Simulation time 166407961 ps
CPU time 1.28 seconds
Started Jul 20 06:11:05 PM PDT 24
Finished Jul 20 06:11:08 PM PDT 24
Peak memory 200652 kb
Host smart-9a5cb3d7-2322-4bd5-ab28-7b35d6c1193c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126273646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.4126273646
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3228539249
Short name T57
Test name
Test status
Simulation time 64948498 ps
CPU time 0.78 seconds
Started Jul 20 06:11:06 PM PDT 24
Finished Jul 20 06:11:08 PM PDT 24
Peak memory 200248 kb
Host smart-db8612e2-0ff5-4a55-815d-1c6bf505b145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228539249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3228539249
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1349664554
Short name T35
Test name
Test status
Simulation time 1223008602 ps
CPU time 5.69 seconds
Started Jul 20 06:11:05 PM PDT 24
Finished Jul 20 06:11:12 PM PDT 24
Peak memory 221820 kb
Host smart-451e4bea-7aab-426c-946b-8752b97e9119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349664554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1349664554
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2404800308
Short name T146
Test name
Test status
Simulation time 243857369 ps
CPU time 1.08 seconds
Started Jul 20 06:11:00 PM PDT 24
Finished Jul 20 06:11:03 PM PDT 24
Peak memory 217408 kb
Host smart-3653314e-0e24-4fa9-aa06-4cab7cab0c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404800308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2404800308
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3943470021
Short name T528
Test name
Test status
Simulation time 173242287 ps
CPU time 0.85 seconds
Started Jul 20 06:11:03 PM PDT 24
Finished Jul 20 06:11:06 PM PDT 24
Peak memory 200276 kb
Host smart-38dde573-c5d7-4cf2-9c94-1d144b564a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943470021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3943470021
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2579567379
Short name T287
Test name
Test status
Simulation time 1496871388 ps
CPU time 5.5 seconds
Started Jul 20 06:11:04 PM PDT 24
Finished Jul 20 06:11:11 PM PDT 24
Peak memory 200736 kb
Host smart-aa4480cd-eb5c-40b8-bb4b-fdda8b22c09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579567379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2579567379
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1294340553
Short name T399
Test name
Test status
Simulation time 101398747 ps
CPU time 0.98 seconds
Started Jul 20 06:11:03 PM PDT 24
Finished Jul 20 06:11:05 PM PDT 24
Peak memory 200464 kb
Host smart-5c72f5b1-1444-4851-b263-4318a076a96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294340553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1294340553
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.15720705
Short name T393
Test name
Test status
Simulation time 256691181 ps
CPU time 1.6 seconds
Started Jul 20 06:11:06 PM PDT 24
Finished Jul 20 06:11:09 PM PDT 24
Peak memory 200656 kb
Host smart-fdf05d59-9ddb-4bcd-a5b9-166814772962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15720705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.15720705
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.790218476
Short name T429
Test name
Test status
Simulation time 5760329719 ps
CPU time 25.66 seconds
Started Jul 20 06:11:02 PM PDT 24
Finished Jul 20 06:11:29 PM PDT 24
Peak memory 208996 kb
Host smart-9c169d2d-e06e-4e07-8645-424535828076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790218476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.790218476
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.4194000018
Short name T58
Test name
Test status
Simulation time 561652809 ps
CPU time 2.99 seconds
Started Jul 20 06:11:04 PM PDT 24
Finished Jul 20 06:11:08 PM PDT 24
Peak memory 200468 kb
Host smart-8561d202-ecd7-455d-a1d9-d670eb32c4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194000018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.4194000018
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3955028925
Short name T355
Test name
Test status
Simulation time 106813325 ps
CPU time 0.96 seconds
Started Jul 20 06:11:02 PM PDT 24
Finished Jul 20 06:11:04 PM PDT 24
Peak memory 200456 kb
Host smart-07bca448-5960-4bd6-9516-5f91b80c591f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955028925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3955028925
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3934753299
Short name T445
Test name
Test status
Simulation time 64367083 ps
CPU time 0.72 seconds
Started Jul 20 06:11:11 PM PDT 24
Finished Jul 20 06:11:13 PM PDT 24
Peak memory 200280 kb
Host smart-c460bd74-9b49-412a-b183-48ec34979f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934753299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3934753299
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.177056352
Short name T496
Test name
Test status
Simulation time 2365258994 ps
CPU time 7.78 seconds
Started Jul 20 06:11:10 PM PDT 24
Finished Jul 20 06:11:18 PM PDT 24
Peak memory 217876 kb
Host smart-4e1d747f-661a-415b-9eb4-9b656c24de48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177056352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.177056352
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2077464348
Short name T470
Test name
Test status
Simulation time 244026803 ps
CPU time 1.16 seconds
Started Jul 20 06:11:15 PM PDT 24
Finished Jul 20 06:11:18 PM PDT 24
Peak memory 217468 kb
Host smart-71a02b1e-ac7b-499f-8b60-625bba8ca03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077464348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2077464348
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1471777712
Short name T20
Test name
Test status
Simulation time 225992086 ps
CPU time 0.89 seconds
Started Jul 20 06:11:07 PM PDT 24
Finished Jul 20 06:11:09 PM PDT 24
Peak memory 200272 kb
Host smart-ad76acf5-d797-4d14-8b00-9c5b09a89db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471777712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1471777712
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2056370895
Short name T533
Test name
Test status
Simulation time 1252456360 ps
CPU time 4.91 seconds
Started Jul 20 06:11:05 PM PDT 24
Finished Jul 20 06:11:11 PM PDT 24
Peak memory 200724 kb
Host smart-e2c7c7f3-e7a8-4eb9-a25c-424802bcf997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056370895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2056370895
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.198394251
Short name T48
Test name
Test status
Simulation time 109995460 ps
CPU time 1.12 seconds
Started Jul 20 06:11:13 PM PDT 24
Finished Jul 20 06:11:16 PM PDT 24
Peak memory 200448 kb
Host smart-63978590-f542-4323-92d7-6c99d3a55aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198394251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.198394251
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3211058032
Short name T387
Test name
Test status
Simulation time 124355992 ps
CPU time 1.14 seconds
Started Jul 20 06:11:06 PM PDT 24
Finished Jul 20 06:11:08 PM PDT 24
Peak memory 200596 kb
Host smart-0cb8ecb0-89c2-49ff-b835-f9263909f4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211058032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3211058032
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.870055210
Short name T401
Test name
Test status
Simulation time 1787593700 ps
CPU time 7.02 seconds
Started Jul 20 06:11:11 PM PDT 24
Finished Jul 20 06:11:19 PM PDT 24
Peak memory 208932 kb
Host smart-977d83ae-e063-4352-8530-a0cacb644f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870055210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.870055210
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1951725048
Short name T300
Test name
Test status
Simulation time 120486533 ps
CPU time 1.47 seconds
Started Jul 20 06:11:08 PM PDT 24
Finished Jul 20 06:11:11 PM PDT 24
Peak memory 200616 kb
Host smart-d0d88cd0-80c5-4c15-8be4-97523dd03676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951725048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1951725048
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.442532778
Short name T33
Test name
Test status
Simulation time 173113480 ps
CPU time 1.24 seconds
Started Jul 20 06:11:20 PM PDT 24
Finished Jul 20 06:11:23 PM PDT 24
Peak memory 200464 kb
Host smart-a82b078b-549e-43f9-9d3d-806b68b0b09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442532778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.442532778
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3488021265
Short name T324
Test name
Test status
Simulation time 67866868 ps
CPU time 0.84 seconds
Started Jul 20 06:11:14 PM PDT 24
Finished Jul 20 06:11:16 PM PDT 24
Peak memory 200232 kb
Host smart-bdc6d85e-c6fa-4130-a63f-3dfdac616ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488021265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3488021265
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1617687583
Short name T472
Test name
Test status
Simulation time 2356377757 ps
CPU time 8.32 seconds
Started Jul 20 06:11:10 PM PDT 24
Finished Jul 20 06:11:19 PM PDT 24
Peak memory 221808 kb
Host smart-f8ba62c6-c93e-457d-9ff9-4c3185718664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617687583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1617687583
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3454477964
Short name T3
Test name
Test status
Simulation time 244449383 ps
CPU time 1.11 seconds
Started Jul 20 06:11:21 PM PDT 24
Finished Jul 20 06:11:23 PM PDT 24
Peak memory 217516 kb
Host smart-a5fe8603-284c-45c7-af7d-6b8c97b0ec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454477964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3454477964
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1512287007
Short name T536
Test name
Test status
Simulation time 119073429 ps
CPU time 0.84 seconds
Started Jul 20 06:11:15 PM PDT 24
Finished Jul 20 06:11:16 PM PDT 24
Peak memory 200272 kb
Host smart-95600cb0-ed47-4d71-81a8-1cce25cd9137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512287007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1512287007
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.4283465836
Short name T526
Test name
Test status
Simulation time 1964543215 ps
CPU time 7.2 seconds
Started Jul 20 06:11:21 PM PDT 24
Finished Jul 20 06:11:29 PM PDT 24
Peak memory 200740 kb
Host smart-6bb1aa3f-ed67-4ac0-8d2f-bacdc72a0ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283465836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4283465836
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.795186725
Short name T394
Test name
Test status
Simulation time 141026839 ps
CPU time 1.08 seconds
Started Jul 20 06:11:11 PM PDT 24
Finished Jul 20 06:11:14 PM PDT 24
Peak memory 200464 kb
Host smart-9765594e-fd0a-4996-bf2a-61ab296bf2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795186725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.795186725
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.537078277
Short name T182
Test name
Test status
Simulation time 181240054 ps
CPU time 1.39 seconds
Started Jul 20 06:11:14 PM PDT 24
Finished Jul 20 06:11:17 PM PDT 24
Peak memory 200664 kb
Host smart-294e4753-7754-41e7-b20e-9b6fed2f367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537078277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.537078277
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.751689020
Short name T534
Test name
Test status
Simulation time 12309245752 ps
CPU time 40.41 seconds
Started Jul 20 06:11:09 PM PDT 24
Finished Jul 20 06:11:50 PM PDT 24
Peak memory 208908 kb
Host smart-47b06e6b-4578-4778-a5ef-aa46f776ee83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751689020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.751689020
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1568033793
Short name T167
Test name
Test status
Simulation time 120374689 ps
CPU time 1.52 seconds
Started Jul 20 06:11:11 PM PDT 24
Finished Jul 20 06:11:13 PM PDT 24
Peak memory 200516 kb
Host smart-65319651-7b5b-46d3-9b8e-fcc583d1a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568033793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1568033793
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1023363179
Short name T365
Test name
Test status
Simulation time 66864091 ps
CPU time 0.77 seconds
Started Jul 20 06:11:15 PM PDT 24
Finished Jul 20 06:11:16 PM PDT 24
Peak memory 200416 kb
Host smart-516a3c8a-cbe8-4ea8-bd8a-81879dc8b2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023363179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1023363179
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3867559595
Short name T208
Test name
Test status
Simulation time 77480939 ps
CPU time 0.77 seconds
Started Jul 20 06:11:11 PM PDT 24
Finished Jul 20 06:11:13 PM PDT 24
Peak memory 200264 kb
Host smart-ba0b45f8-8aa4-42b8-92eb-17482e45f442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867559595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3867559595
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1634951506
Short name T372
Test name
Test status
Simulation time 2340498633 ps
CPU time 8.04 seconds
Started Jul 20 06:11:11 PM PDT 24
Finished Jul 20 06:11:21 PM PDT 24
Peak memory 217840 kb
Host smart-6b35b5ad-f1a6-47da-be54-74bc9b750bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634951506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1634951506
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.113835798
Short name T420
Test name
Test status
Simulation time 246448289 ps
CPU time 1.1 seconds
Started Jul 20 06:11:11 PM PDT 24
Finished Jul 20 06:11:14 PM PDT 24
Peak memory 217584 kb
Host smart-3b9d558d-6e51-4261-96c0-6df0c768ef50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113835798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.113835798
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1366002605
Short name T267
Test name
Test status
Simulation time 117609999 ps
CPU time 0.83 seconds
Started Jul 20 06:11:12 PM PDT 24
Finished Jul 20 06:11:14 PM PDT 24
Peak memory 200172 kb
Host smart-8a3ec8c0-d1d6-4259-b189-18b8dca98b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366002605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1366002605
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1845904602
Short name T110
Test name
Test status
Simulation time 1047161926 ps
CPU time 5.1 seconds
Started Jul 20 06:11:12 PM PDT 24
Finished Jul 20 06:11:18 PM PDT 24
Peak memory 200660 kb
Host smart-f80dc2c5-a6cd-43d5-867e-50482c1e2eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845904602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1845904602
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3465201774
Short name T60
Test name
Test status
Simulation time 155832957 ps
CPU time 1.16 seconds
Started Jul 20 06:11:20 PM PDT 24
Finished Jul 20 06:11:23 PM PDT 24
Peak memory 200448 kb
Host smart-59d3755a-b1e9-4fd7-bad2-528e1bfe1b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465201774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3465201774
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1066497098
Short name T294
Test name
Test status
Simulation time 192623923 ps
CPU time 1.34 seconds
Started Jul 20 06:11:11 PM PDT 24
Finished Jul 20 06:11:13 PM PDT 24
Peak memory 200620 kb
Host smart-35cbea4f-fd80-4068-8913-83bf403ddb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066497098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1066497098
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2710329495
Short name T332
Test name
Test status
Simulation time 3751483208 ps
CPU time 13.49 seconds
Started Jul 20 06:11:13 PM PDT 24
Finished Jul 20 06:11:28 PM PDT 24
Peak memory 200836 kb
Host smart-12541c98-d935-4be0-b0f1-71ac28939351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710329495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2710329495
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3064908378
Short name T134
Test name
Test status
Simulation time 415569139 ps
CPU time 2.5 seconds
Started Jul 20 06:11:14 PM PDT 24
Finished Jul 20 06:11:17 PM PDT 24
Peak memory 200468 kb
Host smart-ed14050f-9d8b-4521-a89e-38deaca5156c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064908378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3064908378
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1800186791
Short name T452
Test name
Test status
Simulation time 145035194 ps
CPU time 1.11 seconds
Started Jul 20 06:11:20 PM PDT 24
Finished Jul 20 06:11:22 PM PDT 24
Peak memory 200456 kb
Host smart-4fdca343-c404-46e3-b751-969359ee2688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800186791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1800186791
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1947831592
Short name T319
Test name
Test status
Simulation time 72481955 ps
CPU time 0.79 seconds
Started Jul 20 06:11:19 PM PDT 24
Finished Jul 20 06:11:20 PM PDT 24
Peak memory 200272 kb
Host smart-50d89738-2ebc-4315-b49a-648eff107e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947831592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1947831592
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2030788097
Short name T484
Test name
Test status
Simulation time 2360340696 ps
CPU time 7.88 seconds
Started Jul 20 06:11:10 PM PDT 24
Finished Jul 20 06:11:19 PM PDT 24
Peak memory 221288 kb
Host smart-15943494-9db6-45b8-95e2-7eaa2909acdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030788097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2030788097
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3247941437
Short name T525
Test name
Test status
Simulation time 244366559 ps
CPU time 1.02 seconds
Started Jul 20 06:11:08 PM PDT 24
Finished Jul 20 06:11:10 PM PDT 24
Peak memory 217508 kb
Host smart-38af0356-5484-4cab-8b4f-c570002874c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247941437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3247941437
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2056348913
Short name T466
Test name
Test status
Simulation time 183314385 ps
CPU time 0.86 seconds
Started Jul 20 06:11:10 PM PDT 24
Finished Jul 20 06:11:12 PM PDT 24
Peak memory 200180 kb
Host smart-dc2e8e90-f0ab-496e-9a07-1212f29f1526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056348913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2056348913
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3085481111
Short name T137
Test name
Test status
Simulation time 1168661386 ps
CPU time 5.28 seconds
Started Jul 20 06:11:10 PM PDT 24
Finished Jul 20 06:11:16 PM PDT 24
Peak memory 200656 kb
Host smart-c4a4fdca-9c69-4578-a370-fbc73b02cb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085481111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3085481111
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1014265483
Short name T490
Test name
Test status
Simulation time 175656058 ps
CPU time 1.14 seconds
Started Jul 20 06:11:11 PM PDT 24
Finished Jul 20 06:11:13 PM PDT 24
Peak memory 200456 kb
Host smart-3ca1a045-a3ef-408b-bb7c-de25b435fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014265483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1014265483
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.248693845
Short name T168
Test name
Test status
Simulation time 239667322 ps
CPU time 1.42 seconds
Started Jul 20 06:11:12 PM PDT 24
Finished Jul 20 06:11:15 PM PDT 24
Peak memory 200676 kb
Host smart-7da77538-50a0-4783-bcbf-73ab8bfc1aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248693845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.248693845
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3232645725
Short name T425
Test name
Test status
Simulation time 2209596002 ps
CPU time 9.22 seconds
Started Jul 20 06:11:21 PM PDT 24
Finished Jul 20 06:11:31 PM PDT 24
Peak memory 200840 kb
Host smart-cea805a6-072b-4239-b119-0836cb1576d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232645725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3232645725
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2629939745
Short name T152
Test name
Test status
Simulation time 243995067 ps
CPU time 1.69 seconds
Started Jul 20 06:11:11 PM PDT 24
Finished Jul 20 06:11:15 PM PDT 24
Peak memory 200472 kb
Host smart-d3470b80-ccc3-4bea-b78a-7d1e6ce843ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629939745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2629939745
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.395057247
Short name T285
Test name
Test status
Simulation time 69739682 ps
CPU time 0.78 seconds
Started Jul 20 06:11:12 PM PDT 24
Finished Jul 20 06:11:14 PM PDT 24
Peak memory 200460 kb
Host smart-849ec21d-06ce-461a-a9f4-aa68f53f85a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395057247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.395057247
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.619901328
Short name T142
Test name
Test status
Simulation time 84149734 ps
CPU time 0.8 seconds
Started Jul 20 06:10:15 PM PDT 24
Finished Jul 20 06:10:17 PM PDT 24
Peak memory 200268 kb
Host smart-7e58dbc7-20fb-4b32-aca6-15054f352ef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619901328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.619901328
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1693282929
Short name T50
Test name
Test status
Simulation time 1886302500 ps
CPU time 8.52 seconds
Started Jul 20 06:10:12 PM PDT 24
Finished Jul 20 06:10:21 PM PDT 24
Peak memory 217040 kb
Host smart-27018982-012c-4c91-a770-371448d67c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693282929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1693282929
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1702381973
Short name T415
Test name
Test status
Simulation time 244569658 ps
CPU time 1.11 seconds
Started Jul 20 06:10:14 PM PDT 24
Finished Jul 20 06:10:15 PM PDT 24
Peak memory 217524 kb
Host smart-c8fe5bb0-7bf3-482c-84de-aa6a83573818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702381973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1702381973
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.4222342108
Short name T434
Test name
Test status
Simulation time 89695819 ps
CPU time 0.75 seconds
Started Jul 20 06:10:04 PM PDT 24
Finished Jul 20 06:10:05 PM PDT 24
Peak memory 200260 kb
Host smart-29eab60e-bdc9-414e-90c7-79ac9779269b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222342108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.4222342108
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.939427143
Short name T340
Test name
Test status
Simulation time 1189173456 ps
CPU time 5.29 seconds
Started Jul 20 06:10:06 PM PDT 24
Finished Jul 20 06:10:12 PM PDT 24
Peak memory 200732 kb
Host smart-70eabd9f-73bb-4d09-9ed3-945c443b24c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939427143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.939427143
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1658109157
Short name T79
Test name
Test status
Simulation time 8298763262 ps
CPU time 16.45 seconds
Started Jul 20 06:10:10 PM PDT 24
Finished Jul 20 06:10:27 PM PDT 24
Peak memory 217592 kb
Host smart-85770d20-5347-4e05-affc-f474ac7e30c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658109157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1658109157
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3380033626
Short name T269
Test name
Test status
Simulation time 153993276 ps
CPU time 1.24 seconds
Started Jul 20 06:10:12 PM PDT 24
Finished Jul 20 06:10:14 PM PDT 24
Peak memory 200444 kb
Host smart-471bdf5e-50cb-45cf-9feb-f89793eac974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380033626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3380033626
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.647850598
Short name T251
Test name
Test status
Simulation time 201858973 ps
CPU time 1.45 seconds
Started Jul 20 06:10:07 PM PDT 24
Finished Jul 20 06:10:09 PM PDT 24
Peak memory 200620 kb
Host smart-fbbbadc2-6fc2-4a96-af01-2d6e974401fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647850598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.647850598
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2671999842
Short name T174
Test name
Test status
Simulation time 201243815 ps
CPU time 1.24 seconds
Started Jul 20 06:10:14 PM PDT 24
Finished Jul 20 06:10:16 PM PDT 24
Peak memory 200428 kb
Host smart-39956e20-1618-4aa7-abd5-e1789554e953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671999842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2671999842
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.297015111
Short name T61
Test name
Test status
Simulation time 144985177 ps
CPU time 1.81 seconds
Started Jul 20 06:10:14 PM PDT 24
Finished Jul 20 06:10:17 PM PDT 24
Peak memory 200356 kb
Host smart-4600a10f-a07a-46f5-81f8-4bf8d8037751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297015111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.297015111
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2849165123
Short name T432
Test name
Test status
Simulation time 170869378 ps
CPU time 1.24 seconds
Started Jul 20 06:10:04 PM PDT 24
Finished Jul 20 06:10:06 PM PDT 24
Peak memory 200644 kb
Host smart-842fd529-5a92-4b3d-bfa0-b43fb1db88b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849165123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2849165123
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2473049016
Short name T359
Test name
Test status
Simulation time 71403377 ps
CPU time 0.8 seconds
Started Jul 20 06:11:20 PM PDT 24
Finished Jul 20 06:11:22 PM PDT 24
Peak memory 200280 kb
Host smart-b8116620-6bd4-4957-b177-ed69aa596cc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473049016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2473049016
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3218375740
Short name T357
Test name
Test status
Simulation time 1903121644 ps
CPU time 7.14 seconds
Started Jul 20 06:11:21 PM PDT 24
Finished Jul 20 06:11:29 PM PDT 24
Peak memory 221720 kb
Host smart-eec30b45-7d82-4ea8-b8ad-85ac8b18fbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218375740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3218375740
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2737739158
Short name T442
Test name
Test status
Simulation time 244291549 ps
CPU time 1.04 seconds
Started Jul 20 06:11:18 PM PDT 24
Finished Jul 20 06:11:20 PM PDT 24
Peak memory 217652 kb
Host smart-6ad0c7df-1b9e-4da1-b9aa-84f45ea330d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737739158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2737739158
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3344629640
Short name T527
Test name
Test status
Simulation time 98329918 ps
CPU time 0.76 seconds
Started Jul 20 06:11:20 PM PDT 24
Finished Jul 20 06:11:22 PM PDT 24
Peak memory 200216 kb
Host smart-abfb2f55-0ab7-4037-a68f-dd9daedc5087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344629640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3344629640
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1456521531
Short name T375
Test name
Test status
Simulation time 1313796431 ps
CPU time 5.19 seconds
Started Jul 20 06:11:24 PM PDT 24
Finished Jul 20 06:11:29 PM PDT 24
Peak memory 200716 kb
Host smart-34f73b64-5465-4b53-8813-d96a3639ae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456521531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1456521531
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.477838946
Short name T243
Test name
Test status
Simulation time 151989603 ps
CPU time 1.13 seconds
Started Jul 20 06:11:22 PM PDT 24
Finished Jul 20 06:11:24 PM PDT 24
Peak memory 200452 kb
Host smart-a0f5a895-3a7f-4617-b9a6-1ae29427ae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477838946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.477838946
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3917006327
Short name T215
Test name
Test status
Simulation time 200749760 ps
CPU time 1.47 seconds
Started Jul 20 06:11:22 PM PDT 24
Finished Jul 20 06:11:25 PM PDT 24
Peak memory 200660 kb
Host smart-554adeb2-1fcf-4965-8d5b-9becaf1f1ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917006327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3917006327
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2437502308
Short name T59
Test name
Test status
Simulation time 115746454 ps
CPU time 0.87 seconds
Started Jul 20 06:11:20 PM PDT 24
Finished Jul 20 06:11:23 PM PDT 24
Peak memory 200264 kb
Host smart-2b2f25aa-ebde-44d1-8407-9de1da46f895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437502308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2437502308
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3597830922
Short name T501
Test name
Test status
Simulation time 445958821 ps
CPU time 2.49 seconds
Started Jul 20 06:11:22 PM PDT 24
Finished Jul 20 06:11:25 PM PDT 24
Peak memory 200392 kb
Host smart-9bd15c53-8ef6-4a6c-a4ee-152bc6fef7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597830922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3597830922
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3298936304
Short name T305
Test name
Test status
Simulation time 158277728 ps
CPU time 1.24 seconds
Started Jul 20 06:11:20 PM PDT 24
Finished Jul 20 06:11:22 PM PDT 24
Peak memory 200664 kb
Host smart-e26170d1-02d3-447e-8eed-4d79ec6fad91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298936304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3298936304
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.118098847
Short name T361
Test name
Test status
Simulation time 66784996 ps
CPU time 0.76 seconds
Started Jul 20 06:11:20 PM PDT 24
Finished Jul 20 06:11:22 PM PDT 24
Peak memory 200276 kb
Host smart-c968ae65-ece7-4cd9-9ba3-8607e0e1d721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118098847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.118098847
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.463986886
Short name T288
Test name
Test status
Simulation time 1228322539 ps
CPU time 5.98 seconds
Started Jul 20 06:11:20 PM PDT 24
Finished Jul 20 06:11:27 PM PDT 24
Peak memory 217596 kb
Host smart-92f422d2-f674-4995-afd3-a76668589e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463986886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.463986886
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2733105856
Short name T277
Test name
Test status
Simulation time 243747518 ps
CPU time 1.04 seconds
Started Jul 20 06:11:19 PM PDT 24
Finished Jul 20 06:11:20 PM PDT 24
Peak memory 217496 kb
Host smart-4d5d1e63-ba72-4f6f-9d36-a415727e3fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733105856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2733105856
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3856260552
Short name T439
Test name
Test status
Simulation time 102326988 ps
CPU time 0.79 seconds
Started Jul 20 06:11:22 PM PDT 24
Finished Jul 20 06:11:24 PM PDT 24
Peak memory 200272 kb
Host smart-1b772c97-a958-4bec-9261-9b1466c6d298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856260552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3856260552
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.936923512
Short name T317
Test name
Test status
Simulation time 1061373930 ps
CPU time 5.71 seconds
Started Jul 20 06:11:19 PM PDT 24
Finished Jul 20 06:11:25 PM PDT 24
Peak memory 200720 kb
Host smart-33f6122e-af66-433c-854c-81331ca8e9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936923512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.936923512
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3850861815
Short name T494
Test name
Test status
Simulation time 114748568 ps
CPU time 1.01 seconds
Started Jul 20 06:11:22 PM PDT 24
Finished Jul 20 06:11:24 PM PDT 24
Peak memory 200472 kb
Host smart-530abef2-0c22-4550-870a-59f91615182c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850861815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3850861815
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1578473242
Short name T225
Test name
Test status
Simulation time 254441320 ps
CPU time 1.53 seconds
Started Jul 20 06:11:21 PM PDT 24
Finished Jul 20 06:11:23 PM PDT 24
Peak memory 200668 kb
Host smart-6e70171f-5220-47aa-86c8-e94fb3b2d02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578473242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1578473242
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2764767188
Short name T312
Test name
Test status
Simulation time 1726710115 ps
CPU time 6.74 seconds
Started Jul 20 06:11:20 PM PDT 24
Finished Jul 20 06:11:28 PM PDT 24
Peak memory 200788 kb
Host smart-0fdc4fd7-5d2e-4b55-ab28-15ef784df4a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764767188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2764767188
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2574233131
Short name T180
Test name
Test status
Simulation time 288584691 ps
CPU time 1.96 seconds
Started Jul 20 06:11:25 PM PDT 24
Finished Jul 20 06:11:27 PM PDT 24
Peak memory 208680 kb
Host smart-f497d689-7477-40ce-aead-a259359810a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574233131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2574233131
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.4077105289
Short name T218
Test name
Test status
Simulation time 72278156 ps
CPU time 0.83 seconds
Started Jul 20 06:11:21 PM PDT 24
Finished Jul 20 06:11:23 PM PDT 24
Peak memory 200468 kb
Host smart-9507c12a-c611-457c-b0ea-e82717852f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077105289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.4077105289
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.136967736
Short name T519
Test name
Test status
Simulation time 64527370 ps
CPU time 0.77 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:31 PM PDT 24
Peak memory 200260 kb
Host smart-d9a3cbfa-988d-4f98-ab8b-c954d063624b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136967736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.136967736
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2817737956
Short name T38
Test name
Test status
Simulation time 1875079604 ps
CPU time 7.75 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:38 PM PDT 24
Peak memory 217760 kb
Host smart-109d7bba-f9fa-448a-86ae-54a3f04f2414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817737956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2817737956
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1911834313
Short name T390
Test name
Test status
Simulation time 243789439 ps
CPU time 1.1 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:32 PM PDT 24
Peak memory 217472 kb
Host smart-aa9d1fd3-bc3f-4831-8c03-d767f5d305e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911834313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1911834313
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2950538244
Short name T24
Test name
Test status
Simulation time 219285405 ps
CPU time 0.89 seconds
Started Jul 20 06:11:21 PM PDT 24
Finished Jul 20 06:11:23 PM PDT 24
Peak memory 200264 kb
Host smart-92268438-d000-4ce2-b6d0-ed2c418c5aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950538244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2950538244
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1321196527
Short name T358
Test name
Test status
Simulation time 1839293687 ps
CPU time 6.45 seconds
Started Jul 20 06:11:30 PM PDT 24
Finished Jul 20 06:11:38 PM PDT 24
Peak memory 200764 kb
Host smart-034dcff0-c67a-4e88-a79a-14fcecef2b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321196527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1321196527
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1413484696
Short name T202
Test name
Test status
Simulation time 112856577 ps
CPU time 0.98 seconds
Started Jul 20 06:11:31 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 200456 kb
Host smart-520f6c5b-2d30-40d0-b50b-2733c2128bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413484696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1413484696
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3137972996
Short name T150
Test name
Test status
Simulation time 204067928 ps
CPU time 1.41 seconds
Started Jul 20 06:11:21 PM PDT 24
Finished Jul 20 06:11:24 PM PDT 24
Peak memory 200680 kb
Host smart-b5b77164-d033-4500-ac80-94bff225f942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137972996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3137972996
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2137537286
Short name T91
Test name
Test status
Simulation time 9611437462 ps
CPU time 41.82 seconds
Started Jul 20 06:11:32 PM PDT 24
Finished Jul 20 06:12:15 PM PDT 24
Peak memory 208972 kb
Host smart-d9d2c5d1-a574-4c4b-9b25-fb54a66ffbdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137537286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2137537286
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3745375684
Short name T446
Test name
Test status
Simulation time 153988828 ps
CPU time 1.87 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:32 PM PDT 24
Peak memory 200484 kb
Host smart-baca0000-a3b2-445a-9eaa-6ff20d80d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745375684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3745375684
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3572688516
Short name T270
Test name
Test status
Simulation time 211414068 ps
CPU time 1.34 seconds
Started Jul 20 06:11:32 PM PDT 24
Finished Jul 20 06:11:35 PM PDT 24
Peak memory 200472 kb
Host smart-a7b2114f-2401-43e2-9133-f9fd63a57b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572688516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3572688516
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1343769846
Short name T485
Test name
Test status
Simulation time 64785928 ps
CPU time 0.75 seconds
Started Jul 20 06:11:31 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 200280 kb
Host smart-59c03484-232e-4a75-b98d-c408e0fe6fc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343769846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1343769846
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2677144675
Short name T333
Test name
Test status
Simulation time 1874629073 ps
CPU time 6.68 seconds
Started Jul 20 06:11:38 PM PDT 24
Finished Jul 20 06:11:45 PM PDT 24
Peak memory 221756 kb
Host smart-e00601e9-e79c-4fb9-8d5e-7f722096ae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677144675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2677144675
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2674656018
Short name T431
Test name
Test status
Simulation time 244412691 ps
CPU time 1.09 seconds
Started Jul 20 06:11:30 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 217504 kb
Host smart-b0218ec6-402a-4466-92c7-fe64c51b76a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674656018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2674656018
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1784068462
Short name T331
Test name
Test status
Simulation time 193529990 ps
CPU time 0.97 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:32 PM PDT 24
Peak memory 200224 kb
Host smart-dd49e952-1cda-455d-95a3-d09404f8ab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784068462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1784068462
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1750760724
Short name T329
Test name
Test status
Simulation time 1404251740 ps
CPU time 5.96 seconds
Started Jul 20 06:11:28 PM PDT 24
Finished Jul 20 06:11:36 PM PDT 24
Peak memory 200772 kb
Host smart-eb465694-1636-4dca-937c-bbc9ddd0be49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750760724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1750760724
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.473859022
Short name T471
Test name
Test status
Simulation time 154447257 ps
CPU time 1.1 seconds
Started Jul 20 06:11:30 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 200472 kb
Host smart-b6d5db9f-dc94-40e7-8710-02859e02d582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473859022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.473859022
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.559481203
Short name T272
Test name
Test status
Simulation time 108647184 ps
CPU time 1.18 seconds
Started Jul 20 06:11:34 PM PDT 24
Finished Jul 20 06:11:35 PM PDT 24
Peak memory 200680 kb
Host smart-f853c642-65ed-4953-b198-387dac213509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559481203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.559481203
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.4207060273
Short name T354
Test name
Test status
Simulation time 9811775996 ps
CPU time 33.36 seconds
Started Jul 20 06:11:27 PM PDT 24
Finished Jul 20 06:12:01 PM PDT 24
Peak memory 209044 kb
Host smart-7c21657e-d281-4d4d-942c-ed100ad28b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207060273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.4207060273
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.70137677
Short name T211
Test name
Test status
Simulation time 110372831 ps
CPU time 1.41 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:33 PM PDT 24
Peak memory 200476 kb
Host smart-ba49389b-9062-446b-b001-ce512c72b8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70137677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.70137677
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3626982861
Short name T315
Test name
Test status
Simulation time 150279695 ps
CPU time 1.09 seconds
Started Jul 20 06:11:31 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 200460 kb
Host smart-76ee8097-6f21-41e9-8962-55b01de82774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626982861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3626982861
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.207736173
Short name T275
Test name
Test status
Simulation time 91605805 ps
CPU time 0.84 seconds
Started Jul 20 06:11:28 PM PDT 24
Finished Jul 20 06:11:30 PM PDT 24
Peak memory 200292 kb
Host smart-001cfc30-166d-48b7-a3e7-8e79f10b70a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207736173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.207736173
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.398074260
Short name T68
Test name
Test status
Simulation time 2345919140 ps
CPU time 9.2 seconds
Started Jul 20 06:11:30 PM PDT 24
Finished Jul 20 06:11:41 PM PDT 24
Peak memory 217964 kb
Host smart-d5b8bfad-d20b-46b4-a7e5-536b05be4d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398074260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.398074260
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1577726296
Short name T424
Test name
Test status
Simulation time 243500900 ps
CPU time 1.13 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:33 PM PDT 24
Peak memory 217492 kb
Host smart-41fcc140-23c8-4f91-bb30-49f61e09ba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577726296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1577726296
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1257884673
Short name T511
Test name
Test status
Simulation time 138194400 ps
CPU time 0.83 seconds
Started Jul 20 06:11:30 PM PDT 24
Finished Jul 20 06:11:32 PM PDT 24
Peak memory 200172 kb
Host smart-f4513dab-60b8-4db9-b04a-690bf4e231b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257884673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1257884673
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3154294694
Short name T106
Test name
Test status
Simulation time 1475460714 ps
CPU time 6.86 seconds
Started Jul 20 06:11:31 PM PDT 24
Finished Jul 20 06:11:40 PM PDT 24
Peak memory 200732 kb
Host smart-e612077e-ed05-4950-82b1-907cbed41ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154294694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3154294694
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1343051915
Short name T447
Test name
Test status
Simulation time 95374226 ps
CPU time 1.01 seconds
Started Jul 20 06:11:26 PM PDT 24
Finished Jul 20 06:11:27 PM PDT 24
Peak memory 200452 kb
Host smart-97f5d470-50c7-4e4f-b85f-01bc6dbbef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343051915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1343051915
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.290598969
Short name T328
Test name
Test status
Simulation time 125902266 ps
CPU time 1.18 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:32 PM PDT 24
Peak memory 200704 kb
Host smart-c90f2fed-1af6-4e49-b3e4-5989031e884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290598969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.290598969
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.973087525
Short name T535
Test name
Test status
Simulation time 8356103859 ps
CPU time 26.06 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:57 PM PDT 24
Peak memory 200788 kb
Host smart-56e6b913-a305-479f-945b-4bdc6e705375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973087525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.973087525
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1804255959
Short name T7
Test name
Test status
Simulation time 121816278 ps
CPU time 1.62 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:33 PM PDT 24
Peak memory 208664 kb
Host smart-e1c1df58-5bbb-4695-99e2-ac3d71909889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804255959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1804255959
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2575142787
Short name T513
Test name
Test status
Simulation time 99408394 ps
CPU time 0.93 seconds
Started Jul 20 06:11:33 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 200468 kb
Host smart-340c2b80-0ea3-47b5-bf28-83356206a899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575142787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2575142787
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2825528108
Short name T378
Test name
Test status
Simulation time 93623803 ps
CPU time 0.81 seconds
Started Jul 20 06:11:27 PM PDT 24
Finished Jul 20 06:11:29 PM PDT 24
Peak memory 200252 kb
Host smart-49898969-8a98-4c79-8f8f-ccaebaa2096c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825528108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2825528108
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3165972571
Short name T392
Test name
Test status
Simulation time 1894428854 ps
CPU time 7.26 seconds
Started Jul 20 06:11:29 PM PDT 24
Finished Jul 20 06:11:39 PM PDT 24
Peak memory 216856 kb
Host smart-a1b8eeea-99b7-4ac8-8da5-0901431b5a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165972571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3165972571
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4221134434
Short name T162
Test name
Test status
Simulation time 244458387 ps
CPU time 1.14 seconds
Started Jul 20 06:11:30 PM PDT 24
Finished Jul 20 06:11:33 PM PDT 24
Peak memory 217504 kb
Host smart-b89225b5-c41b-4f55-af8b-ece52203b827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221134434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4221134434
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.4125297752
Short name T495
Test name
Test status
Simulation time 216155500 ps
CPU time 0.94 seconds
Started Jul 20 06:11:27 PM PDT 24
Finished Jul 20 06:11:29 PM PDT 24
Peak memory 200204 kb
Host smart-8166da73-7502-4343-9bc8-cdff38a3b738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125297752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.4125297752
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2523288401
Short name T107
Test name
Test status
Simulation time 968252096 ps
CPU time 5.02 seconds
Started Jul 20 06:11:28 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 200716 kb
Host smart-125a0608-09c1-4f1f-b53e-952fd5c415c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523288401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2523288401
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2937116607
Short name T207
Test name
Test status
Simulation time 98870682 ps
CPU time 0.96 seconds
Started Jul 20 06:11:28 PM PDT 24
Finished Jul 20 06:11:30 PM PDT 24
Peak memory 200460 kb
Host smart-c5c632c0-03fe-4059-aa7e-c77c4300b2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937116607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2937116607
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.4091380219
Short name T427
Test name
Test status
Simulation time 126569338 ps
CPU time 1.25 seconds
Started Jul 20 06:11:31 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 200724 kb
Host smart-bda5c961-3b55-4fea-bb32-2afbcb6a3d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091380219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.4091380219
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2549644460
Short name T349
Test name
Test status
Simulation time 6453631419 ps
CPU time 21.02 seconds
Started Jul 20 06:11:37 PM PDT 24
Finished Jul 20 06:11:59 PM PDT 24
Peak memory 209040 kb
Host smart-6b9a66d9-bf87-48b7-ac40-c1808e7dedd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549644460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2549644460
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2410287890
Short name T140
Test name
Test status
Simulation time 126487683 ps
CPU time 1.03 seconds
Started Jul 20 06:11:28 PM PDT 24
Finished Jul 20 06:11:31 PM PDT 24
Peak memory 200440 kb
Host smart-da31a7ff-1c35-43e4-8264-4db24daa09d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410287890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2410287890
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1972549336
Short name T149
Test name
Test status
Simulation time 62189089 ps
CPU time 0.76 seconds
Started Jul 20 06:11:46 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 200024 kb
Host smart-e878d3a3-d029-4088-bde9-3eb790ef4c3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972549336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1972549336
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3016632527
Short name T455
Test name
Test status
Simulation time 1902047606 ps
CPU time 6.93 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:11:51 PM PDT 24
Peak memory 216952 kb
Host smart-dfa72ebf-72f5-4c65-9e34-5d7f7fe38263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016632527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3016632527
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1672469629
Short name T419
Test name
Test status
Simulation time 244528946 ps
CPU time 1.04 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:41 PM PDT 24
Peak memory 217444 kb
Host smart-ced32f7b-70f8-40dc-8765-6b0d23d962d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672469629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1672469629
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1899483846
Short name T318
Test name
Test status
Simulation time 96372370 ps
CPU time 0.81 seconds
Started Jul 20 06:11:30 PM PDT 24
Finished Jul 20 06:11:33 PM PDT 24
Peak memory 200276 kb
Host smart-d3bb621b-8559-43f6-a9dc-70dedbe1392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899483846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1899483846
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3449651676
Short name T10
Test name
Test status
Simulation time 1461160104 ps
CPU time 5.57 seconds
Started Jul 20 06:11:35 PM PDT 24
Finished Jul 20 06:11:41 PM PDT 24
Peak memory 200744 kb
Host smart-9aaea39a-0e76-4fbf-9099-412f50c68142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449651676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3449651676
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3706414404
Short name T154
Test name
Test status
Simulation time 170289846 ps
CPU time 1.12 seconds
Started Jul 20 06:11:44 PM PDT 24
Finished Jul 20 06:11:48 PM PDT 24
Peak memory 200464 kb
Host smart-49ce3f76-5f54-4d81-a789-58968cb9b336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706414404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3706414404
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1499193502
Short name T148
Test name
Test status
Simulation time 112070352 ps
CPU time 1.17 seconds
Started Jul 20 06:11:30 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 200620 kb
Host smart-9cca059c-9538-4a95-8dce-b6a9e795dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499193502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1499193502
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2325070534
Short name T449
Test name
Test status
Simulation time 9604226495 ps
CPU time 43.09 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:12:26 PM PDT 24
Peak memory 209036 kb
Host smart-d82cd7ca-11b6-4ce8-a58e-e25388f5b1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325070534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2325070534
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.4081282619
Short name T32
Test name
Test status
Simulation time 131950327 ps
CPU time 1.55 seconds
Started Jul 20 06:11:28 PM PDT 24
Finished Jul 20 06:11:32 PM PDT 24
Peak memory 208800 kb
Host smart-6037c3b7-21c0-457c-855f-51dee7994433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081282619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.4081282619
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2971743967
Short name T47
Test name
Test status
Simulation time 95355080 ps
CPU time 0.85 seconds
Started Jul 20 06:11:31 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 200476 kb
Host smart-9b08078d-67f2-43da-9a98-bd41b7f63944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971743967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2971743967
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.687576177
Short name T423
Test name
Test status
Simulation time 88150360 ps
CPU time 0.79 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:11:47 PM PDT 24
Peak memory 200280 kb
Host smart-52c6971b-137f-4aa3-8552-a0b96d8ba878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687576177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.687576177
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.4197608037
Short name T397
Test name
Test status
Simulation time 1895888150 ps
CPU time 8.04 seconds
Started Jul 20 06:11:44 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 221792 kb
Host smart-f73f8532-61ac-477f-8e04-5e21ab4c2dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197608037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.4197608037
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1734744512
Short name T407
Test name
Test status
Simulation time 243776615 ps
CPU time 1.19 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:11:44 PM PDT 24
Peak memory 217532 kb
Host smart-8ef54414-86b0-483f-a946-0bd89b958fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734744512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1734744512
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2487203838
Short name T228
Test name
Test status
Simulation time 123707826 ps
CPU time 0.83 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:11:47 PM PDT 24
Peak memory 200280 kb
Host smart-c1b01765-97ce-4ab4-909f-51daaecd6626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487203838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2487203838
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1463195310
Short name T512
Test name
Test status
Simulation time 1192907722 ps
CPU time 4.78 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 200732 kb
Host smart-53e2f7fc-7ae8-4317-b2a1-7b726eff6b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463195310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1463195310
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3024265496
Short name T326
Test name
Test status
Simulation time 97526681 ps
CPU time 0.97 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:46 PM PDT 24
Peak memory 200472 kb
Host smart-57a45a03-741c-45c4-bf9a-2b57f0deff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024265496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3024265496
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2441378886
Short name T422
Test name
Test status
Simulation time 197695486 ps
CPU time 1.35 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:47 PM PDT 24
Peak memory 200668 kb
Host smart-34565d3b-c827-493c-844d-18ec336552c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441378886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2441378886
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3850049592
Short name T197
Test name
Test status
Simulation time 5447491519 ps
CPU time 21.92 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:12:03 PM PDT 24
Peak memory 208912 kb
Host smart-3592aae8-314e-4d21-a41a-9048a8ecd25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850049592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3850049592
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2312977853
Short name T531
Test name
Test status
Simulation time 137913344 ps
CPU time 1.72 seconds
Started Jul 20 06:11:39 PM PDT 24
Finished Jul 20 06:11:41 PM PDT 24
Peak memory 200480 kb
Host smart-e28d5714-10c8-4336-9c23-a9be0d89a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312977853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2312977853
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.907963867
Short name T499
Test name
Test status
Simulation time 174028367 ps
CPU time 1.23 seconds
Started Jul 20 06:11:38 PM PDT 24
Finished Jul 20 06:11:40 PM PDT 24
Peak memory 200616 kb
Host smart-1f36cbc1-bc14-401e-94ca-d5be32e6d5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907963867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.907963867
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1811110498
Short name T85
Test name
Test status
Simulation time 79533098 ps
CPU time 0.8 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:11:45 PM PDT 24
Peak memory 200248 kb
Host smart-a138b5eb-7035-40bd-8131-b3032fc85ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811110498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1811110498
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.487284454
Short name T67
Test name
Test status
Simulation time 1225710824 ps
CPU time 5.39 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 217772 kb
Host smart-ea105f1f-99ab-4763-bcbe-91f4321c255f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487284454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.487284454
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1517550189
Short name T160
Test name
Test status
Simulation time 244735901 ps
CPU time 1.11 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:11:47 PM PDT 24
Peak memory 217544 kb
Host smart-23d90779-0a16-47f0-a9b3-60707021a2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517550189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1517550189
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.997944347
Short name T524
Test name
Test status
Simulation time 131990632 ps
CPU time 0.85 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:42 PM PDT 24
Peak memory 200188 kb
Host smart-8d52d2fc-4f03-4ef2-ad7b-7fd74848c7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997944347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.997944347
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3778623476
Short name T320
Test name
Test status
Simulation time 834989311 ps
CPU time 4.05 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:11:50 PM PDT 24
Peak memory 200768 kb
Host smart-59e97b29-dd36-43b3-a785-98e98f9baad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778623476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3778623476
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3777378344
Short name T295
Test name
Test status
Simulation time 140952954 ps
CPU time 1.12 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:43 PM PDT 24
Peak memory 200356 kb
Host smart-9039bab4-c626-447c-9eb0-ab9f9db12576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777378344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3777378344
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2621393835
Short name T522
Test name
Test status
Simulation time 114288431 ps
CPU time 1.19 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:11:48 PM PDT 24
Peak memory 200672 kb
Host smart-a90ab0c8-fed9-408f-8528-e4f7dc9b619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621393835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2621393835
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1182698978
Short name T234
Test name
Test status
Simulation time 5169201757 ps
CPU time 21.35 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:12:02 PM PDT 24
Peak memory 200816 kb
Host smart-a31679be-cd19-40ae-8948-cfb167e7676f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182698978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1182698978
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3422162751
Short name T516
Test name
Test status
Simulation time 452622830 ps
CPU time 2.41 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:44 PM PDT 24
Peak memory 200520 kb
Host smart-316f6239-c476-4c82-9638-55d694829ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422162751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3422162751
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2037297587
Short name T453
Test name
Test status
Simulation time 119992992 ps
CPU time 1.03 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:46 PM PDT 24
Peak memory 200456 kb
Host smart-717e0559-4e24-4f61-9578-928bb0d7dd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037297587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2037297587
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2258966822
Short name T178
Test name
Test status
Simulation time 91999516 ps
CPU time 0.81 seconds
Started Jul 20 06:11:39 PM PDT 24
Finished Jul 20 06:11:41 PM PDT 24
Peak memory 200276 kb
Host smart-31a3425a-7ab1-4028-b2fc-12d687382d85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258966822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2258966822
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3944612872
Short name T379
Test name
Test status
Simulation time 1224658236 ps
CPU time 5.79 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 217676 kb
Host smart-76d32304-a0fb-48a8-b496-32c8be04bd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944612872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3944612872
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3408883140
Short name T151
Test name
Test status
Simulation time 245076577 ps
CPU time 1.03 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:11:47 PM PDT 24
Peak memory 217456 kb
Host smart-27adcc67-110f-4f9f-b8b1-f0645f69211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408883140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3408883140
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2251208689
Short name T196
Test name
Test status
Simulation time 235539706 ps
CPU time 0.97 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:11:44 PM PDT 24
Peak memory 200328 kb
Host smart-dd58edfe-e02b-4ee9-b1c2-c8e574836bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251208689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2251208689
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3119332218
Short name T350
Test name
Test status
Simulation time 864212892 ps
CPU time 4 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:45 PM PDT 24
Peak memory 200744 kb
Host smart-33129313-633c-4def-b75a-32fab6b896da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119332218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3119332218
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3684692013
Short name T49
Test name
Test status
Simulation time 157705720 ps
CPU time 1.22 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:47 PM PDT 24
Peak memory 200444 kb
Host smart-3167636e-d9f1-4095-9d74-3b262b70ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684692013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3684692013
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1604874870
Short name T14
Test name
Test status
Simulation time 258699669 ps
CPU time 1.45 seconds
Started Jul 20 06:11:46 PM PDT 24
Finished Jul 20 06:11:50 PM PDT 24
Peak memory 200664 kb
Host smart-86d88c2b-ef2c-4c34-82b4-bb387d2ef14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604874870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1604874870
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2995945815
Short name T273
Test name
Test status
Simulation time 8827094566 ps
CPU time 34.38 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:12:18 PM PDT 24
Peak memory 208992 kb
Host smart-35a8775c-6f6d-435e-aed6-0bf310c36975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995945815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2995945815
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.243529256
Short name T289
Test name
Test status
Simulation time 384832177 ps
CPU time 2.24 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:44 PM PDT 24
Peak memory 200364 kb
Host smart-0b0a6eff-d381-4f33-b602-5f1917e799af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243529256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.243529256
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1336610579
Short name T11
Test name
Test status
Simulation time 166402137 ps
CPU time 1.3 seconds
Started Jul 20 06:11:38 PM PDT 24
Finished Jul 20 06:11:40 PM PDT 24
Peak memory 200640 kb
Host smart-fe3e5aef-5afc-4bcc-8b80-03cfa7254554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336610579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1336610579
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3935960423
Short name T17
Test name
Test status
Simulation time 68873466 ps
CPU time 0.82 seconds
Started Jul 20 06:10:14 PM PDT 24
Finished Jul 20 06:10:15 PM PDT 24
Peak memory 200220 kb
Host smart-8634d091-10b0-40b4-acfc-10445ce79bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935960423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3935960423
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.969904720
Short name T36
Test name
Test status
Simulation time 1899999314 ps
CPU time 7.4 seconds
Started Jul 20 06:10:14 PM PDT 24
Finished Jul 20 06:10:22 PM PDT 24
Peak memory 217824 kb
Host smart-d4502ba4-5cac-4782-a8cd-7145157656b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969904720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.969904720
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.134397046
Short name T232
Test name
Test status
Simulation time 244578703 ps
CPU time 1.09 seconds
Started Jul 20 06:10:11 PM PDT 24
Finished Jul 20 06:10:13 PM PDT 24
Peak memory 217460 kb
Host smart-1390f16f-d494-40fa-808c-8f9980da270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134397046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.134397046
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2309239918
Short name T413
Test name
Test status
Simulation time 205956825 ps
CPU time 0.83 seconds
Started Jul 20 06:10:12 PM PDT 24
Finished Jul 20 06:10:14 PM PDT 24
Peak memory 200272 kb
Host smart-68b3bcf9-222c-4bfa-8a63-7e4cf3f1e5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309239918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2309239918
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2742922501
Short name T518
Test name
Test status
Simulation time 1807207089 ps
CPU time 6.39 seconds
Started Jul 20 06:10:15 PM PDT 24
Finished Jul 20 06:10:22 PM PDT 24
Peak memory 200708 kb
Host smart-624ab9b2-2854-4b65-838e-c78c78f87297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742922501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2742922501
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2088267825
Short name T80
Test name
Test status
Simulation time 8629011251 ps
CPU time 12.96 seconds
Started Jul 20 06:10:12 PM PDT 24
Finished Jul 20 06:10:25 PM PDT 24
Peak memory 217744 kb
Host smart-ad17d901-8a0e-4d43-b13a-582bf010aa3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088267825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2088267825
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.95075568
Short name T63
Test name
Test status
Simulation time 148537000 ps
CPU time 1.13 seconds
Started Jul 20 06:10:14 PM PDT 24
Finished Jul 20 06:10:16 PM PDT 24
Peak memory 200452 kb
Host smart-65fbb8d5-a407-4b8b-8760-9a9be57e34cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95075568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.95075568
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2348861435
Short name T418
Test name
Test status
Simulation time 117944065 ps
CPU time 1.26 seconds
Started Jul 20 06:10:15 PM PDT 24
Finished Jul 20 06:10:17 PM PDT 24
Peak memory 200604 kb
Host smart-3b9d668c-1cce-4b32-927a-8b9f8f460104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348861435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2348861435
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.696593298
Short name T194
Test name
Test status
Simulation time 1366249704 ps
CPU time 5.69 seconds
Started Jul 20 06:10:13 PM PDT 24
Finished Jul 20 06:10:20 PM PDT 24
Peak memory 209160 kb
Host smart-98c4b72d-d9e0-44a3-9a57-0f6e3a799d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696593298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.696593298
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.909334290
Short name T31
Test name
Test status
Simulation time 150357140 ps
CPU time 1.84 seconds
Started Jul 20 06:10:14 PM PDT 24
Finished Jul 20 06:10:17 PM PDT 24
Peak memory 200424 kb
Host smart-a5971046-b1dd-434d-95ad-320c3ff3ea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909334290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.909334290
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.355988633
Short name T348
Test name
Test status
Simulation time 83702787 ps
CPU time 0.86 seconds
Started Jul 20 06:10:11 PM PDT 24
Finished Jul 20 06:10:12 PM PDT 24
Peak memory 200516 kb
Host smart-02b19e89-d6d8-46bb-b201-f625c7a4dc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355988633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.355988633
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3657626502
Short name T279
Test name
Test status
Simulation time 69570354 ps
CPU time 0.83 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:46 PM PDT 24
Peak memory 200264 kb
Host smart-8b3a5efa-c28e-45ad-a454-b4914f2cc17c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657626502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3657626502
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1839541235
Short name T402
Test name
Test status
Simulation time 1220455299 ps
CPU time 5.57 seconds
Started Jul 20 06:11:44 PM PDT 24
Finished Jul 20 06:11:53 PM PDT 24
Peak memory 221772 kb
Host smart-71ab507f-1407-4a72-9c99-6067162b101d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839541235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1839541235
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.886968630
Short name T245
Test name
Test status
Simulation time 245113526 ps
CPU time 1.03 seconds
Started Jul 20 06:11:45 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 217560 kb
Host smart-68b63755-3688-4aee-bbb4-10fd3a43d877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886968630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.886968630
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.356888161
Short name T224
Test name
Test status
Simulation time 132730580 ps
CPU time 0.81 seconds
Started Jul 20 06:11:39 PM PDT 24
Finished Jul 20 06:11:40 PM PDT 24
Peak memory 200252 kb
Host smart-2c7a20d6-3cd7-4dc7-8bf0-5845e989b0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356888161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.356888161
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2496984506
Short name T286
Test name
Test status
Simulation time 1353880368 ps
CPU time 5.55 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:11:52 PM PDT 24
Peak memory 200780 kb
Host smart-05dfd98a-c6a1-451c-84cf-f94cc69e88f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496984506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2496984506
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1567792266
Short name T87
Test name
Test status
Simulation time 152734988 ps
CPU time 1.2 seconds
Started Jul 20 06:11:44 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 200452 kb
Host smart-6b5c5fbc-26f2-4911-954e-ea32cb96825d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567792266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1567792266
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3475125750
Short name T200
Test name
Test status
Simulation time 122623237 ps
CPU time 1.19 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:43 PM PDT 24
Peak memory 200672 kb
Host smart-e5234a2d-404b-4606-a7ca-2cf98c23d25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475125750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3475125750
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2988420591
Short name T433
Test name
Test status
Simulation time 5316364500 ps
CPU time 22.15 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:12:08 PM PDT 24
Peak memory 208940 kb
Host smart-93f8113e-8965-42db-a32b-c33942903744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988420591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2988420591
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2089165309
Short name T428
Test name
Test status
Simulation time 356367352 ps
CPU time 2.07 seconds
Started Jul 20 06:11:44 PM PDT 24
Finished Jul 20 06:11:50 PM PDT 24
Peak memory 200468 kb
Host smart-1175a975-3d25-4104-96fc-7ef0ab3cb7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089165309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2089165309
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.830372741
Short name T198
Test name
Test status
Simulation time 222569493 ps
CPU time 1.32 seconds
Started Jul 20 06:11:44 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 200448 kb
Host smart-5d3d1372-a794-4032-97ac-4613ba216534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830372741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.830372741
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1120936387
Short name T257
Test name
Test status
Simulation time 64447293 ps
CPU time 0.7 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:11:43 PM PDT 24
Peak memory 200248 kb
Host smart-c9c721d1-0c45-4a35-a2ef-16789747697f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120936387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1120936387
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1248419926
Short name T37
Test name
Test status
Simulation time 1876796375 ps
CPU time 6.94 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:11:53 PM PDT 24
Peak memory 221740 kb
Host smart-b8b1d8e2-8acf-4699-ac48-320209b54901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248419926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1248419926
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2529588263
Short name T18
Test name
Test status
Simulation time 243738944 ps
CPU time 1.09 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:46 PM PDT 24
Peak memory 217544 kb
Host smart-1b225e5f-d41b-400d-8510-2c263cb4f9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529588263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2529588263
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1570913036
Short name T460
Test name
Test status
Simulation time 125819541 ps
CPU time 0.82 seconds
Started Jul 20 06:11:46 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 200244 kb
Host smart-855b702c-79b3-4688-92be-ea27f3671b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570913036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1570913036
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3974674393
Short name T281
Test name
Test status
Simulation time 1065663728 ps
CPU time 5 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:47 PM PDT 24
Peak memory 200688 kb
Host smart-7f6ec4c3-a2cb-4713-91a6-5aa8c18d8a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974674393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3974674393
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.58959893
Short name T386
Test name
Test status
Simulation time 102318015 ps
CPU time 1.05 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:11:45 PM PDT 24
Peak memory 200468 kb
Host smart-9d1f0256-7476-4ee9-9f90-35f664ec53fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58959893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.58959893
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2015922388
Short name T282
Test name
Test status
Simulation time 196653009 ps
CPU time 1.46 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:11:48 PM PDT 24
Peak memory 200660 kb
Host smart-f9e5abd6-3125-4a39-a056-be6ed1ae2a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015922388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2015922388
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.796468978
Short name T500
Test name
Test status
Simulation time 6056667676 ps
CPU time 25.65 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:12:06 PM PDT 24
Peak memory 209012 kb
Host smart-a8ce33df-c976-46ac-b8cd-38e795148df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796468978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.796468978
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.942376311
Short name T311
Test name
Test status
Simulation time 109900134 ps
CPU time 1.38 seconds
Started Jul 20 06:11:38 PM PDT 24
Finished Jul 20 06:11:40 PM PDT 24
Peak memory 200404 kb
Host smart-adc02a8a-473b-4c97-a437-c23600b8207c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942376311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.942376311
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1400911304
Short name T391
Test name
Test status
Simulation time 149619390 ps
CPU time 1.13 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:46 PM PDT 24
Peak memory 200452 kb
Host smart-99b821ca-7e41-447b-b232-86ee9947a29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400911304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1400911304
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2466949498
Short name T27
Test name
Test status
Simulation time 78662638 ps
CPU time 0.87 seconds
Started Jul 20 06:11:41 PM PDT 24
Finished Jul 20 06:11:44 PM PDT 24
Peak memory 200272 kb
Host smart-e349f37f-31ab-4c89-aca6-21e20bc33fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466949498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2466949498
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3655982447
Short name T334
Test name
Test status
Simulation time 2162080051 ps
CPU time 8.2 seconds
Started Jul 20 06:11:44 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 217860 kb
Host smart-0a337983-b881-4210-b8f3-ec3f635ca74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655982447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3655982447
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1436309042
Short name T308
Test name
Test status
Simulation time 244610416 ps
CPU time 1.05 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:44 PM PDT 24
Peak memory 217544 kb
Host smart-6d17ac5a-1e32-45c7-8e11-bad2238d0049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436309042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1436309042
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3983383159
Short name T186
Test name
Test status
Simulation time 131317083 ps
CPU time 0.77 seconds
Started Jul 20 06:11:44 PM PDT 24
Finished Jul 20 06:11:48 PM PDT 24
Peak memory 200260 kb
Host smart-38a979ac-3884-41a0-971b-e7e2c22d7e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983383159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3983383159
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1097393097
Short name T505
Test name
Test status
Simulation time 927369836 ps
CPU time 4.36 seconds
Started Jul 20 06:11:38 PM PDT 24
Finished Jul 20 06:11:43 PM PDT 24
Peak memory 200912 kb
Host smart-1c5342e9-9b69-44f0-9323-ffee36a11804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097393097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1097393097
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1688007348
Short name T364
Test name
Test status
Simulation time 98861026 ps
CPU time 1.04 seconds
Started Jul 20 06:11:38 PM PDT 24
Finished Jul 20 06:11:40 PM PDT 24
Peak memory 200592 kb
Host smart-e18790fa-d248-4229-ad63-c5632c87a53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688007348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1688007348
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2583841193
Short name T203
Test name
Test status
Simulation time 200696269 ps
CPU time 1.42 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:44 PM PDT 24
Peak memory 200668 kb
Host smart-052808d4-0b23-4077-9d20-31302fa1b66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583841193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2583841193
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1945224731
Short name T417
Test name
Test status
Simulation time 127609778 ps
CPU time 1 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:46 PM PDT 24
Peak memory 200460 kb
Host smart-faa99026-d51e-4bb7-863c-426949d0ba06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945224731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1945224731
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2430425377
Short name T488
Test name
Test status
Simulation time 343403705 ps
CPU time 2.22 seconds
Started Jul 20 06:11:46 PM PDT 24
Finished Jul 20 06:11:51 PM PDT 24
Peak memory 208668 kb
Host smart-61051a0c-73cc-48e4-8318-7dba05eabf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430425377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2430425377
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.203317709
Short name T248
Test name
Test status
Simulation time 113739506 ps
CPU time 1.01 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:47 PM PDT 24
Peak memory 200408 kb
Host smart-c9034493-2019-482f-84f7-423b6192b28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203317709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.203317709
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1926709924
Short name T476
Test name
Test status
Simulation time 61662270 ps
CPU time 0.79 seconds
Started Jul 20 06:11:48 PM PDT 24
Finished Jul 20 06:11:50 PM PDT 24
Peak memory 200264 kb
Host smart-bbe9e477-ba20-4ca5-9eb2-5104c8e76b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926709924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1926709924
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.4250116804
Short name T66
Test name
Test status
Simulation time 1892466666 ps
CPU time 7.53 seconds
Started Jul 20 06:11:44 PM PDT 24
Finished Jul 20 06:11:54 PM PDT 24
Peak memory 221756 kb
Host smart-dbf0f803-c53c-4fda-a60e-49861f1fdd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250116804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4250116804
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3483797384
Short name T370
Test name
Test status
Simulation time 244916409 ps
CPU time 1.02 seconds
Started Jul 20 06:11:40 PM PDT 24
Finished Jul 20 06:11:42 PM PDT 24
Peak memory 217576 kb
Host smart-49d439b2-dd98-4ffa-a187-35bde0f7e820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483797384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3483797384
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2248422733
Short name T25
Test name
Test status
Simulation time 232149436 ps
CPU time 0.94 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:47 PM PDT 24
Peak memory 200268 kb
Host smart-347f6814-7d33-4258-9a13-9098c0852c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248422733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2248422733
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1997587185
Short name T64
Test name
Test status
Simulation time 2007299336 ps
CPU time 7.27 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:52 PM PDT 24
Peak memory 200728 kb
Host smart-8a918b60-ddbd-45ef-96ad-62e82ac57106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997587185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1997587185
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2095129737
Short name T509
Test name
Test status
Simulation time 105656607 ps
CPU time 0.97 seconds
Started Jul 20 06:11:43 PM PDT 24
Finished Jul 20 06:11:47 PM PDT 24
Peak memory 200444 kb
Host smart-73c6a1ac-3432-4606-9389-95a0dbc5b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095129737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2095129737
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.697658979
Short name T327
Test name
Test status
Simulation time 221734403 ps
CPU time 1.47 seconds
Started Jul 20 06:11:39 PM PDT 24
Finished Jul 20 06:11:41 PM PDT 24
Peak memory 200664 kb
Host smart-d988f150-b714-4d09-a916-7dea5bdb6f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697658979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.697658979
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3220429467
Short name T95
Test name
Test status
Simulation time 5464824985 ps
CPU time 25.35 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:12:10 PM PDT 24
Peak memory 200792 kb
Host smart-09a86cbc-1911-4247-808d-dd65f49b4344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220429467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3220429467
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3685412755
Short name T506
Test name
Test status
Simulation time 290454248 ps
CPU time 2.16 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:48 PM PDT 24
Peak memory 208656 kb
Host smart-c48fdae5-e49f-4e32-8454-dfb02fb84d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685412755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3685412755
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2595268135
Short name T156
Test name
Test status
Simulation time 138206050 ps
CPU time 1.04 seconds
Started Jul 20 06:11:42 PM PDT 24
Finished Jul 20 06:11:46 PM PDT 24
Peak memory 200456 kb
Host smart-655e491a-7d72-4502-b7fd-004eaf0870cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595268135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2595268135
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3704852178
Short name T301
Test name
Test status
Simulation time 77324267 ps
CPU time 0.81 seconds
Started Jul 20 06:11:52 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 200260 kb
Host smart-45b078fc-fbf6-494a-80ee-6777378ccee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704852178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3704852178
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1308040484
Short name T411
Test name
Test status
Simulation time 1228120096 ps
CPU time 5.58 seconds
Started Jul 20 06:11:52 PM PDT 24
Finished Jul 20 06:12:00 PM PDT 24
Peak memory 216752 kb
Host smart-88073400-3217-4145-a7a4-23d39dc4929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308040484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1308040484
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1509100301
Short name T157
Test name
Test status
Simulation time 244864452 ps
CPU time 1.04 seconds
Started Jul 20 06:11:52 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 217356 kb
Host smart-800dd084-f202-4020-b19d-dd4a3e64fa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509100301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1509100301
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2584695682
Short name T193
Test name
Test status
Simulation time 236533098 ps
CPU time 0.9 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:11:54 PM PDT 24
Peak memory 200272 kb
Host smart-74e33fff-7602-48fb-ae0a-bf5ae23c3c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584695682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2584695682
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.4263548766
Short name T325
Test name
Test status
Simulation time 1190002929 ps
CPU time 5.08 seconds
Started Jul 20 06:11:46 PM PDT 24
Finished Jul 20 06:11:53 PM PDT 24
Peak memory 200724 kb
Host smart-68359562-9cb0-4cd1-95ff-54287201875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263548766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4263548766
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3405926422
Short name T457
Test name
Test status
Simulation time 151522151 ps
CPU time 1.07 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:54 PM PDT 24
Peak memory 200456 kb
Host smart-c99cdd12-b54c-4cec-aefb-b1f12f99322e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405926422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3405926422
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.113310792
Short name T239
Test name
Test status
Simulation time 125112285 ps
CPU time 1.14 seconds
Started Jul 20 06:11:45 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 200656 kb
Host smart-c603b91d-2568-4dfa-923c-8e2b03993ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113310792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.113310792
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.144715209
Short name T514
Test name
Test status
Simulation time 2264583059 ps
CPU time 10.2 seconds
Started Jul 20 06:11:46 PM PDT 24
Finished Jul 20 06:11:59 PM PDT 24
Peak memory 200940 kb
Host smart-3c7c234b-b4dc-4f24-998b-662e49af6afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144715209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.144715209
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4214423071
Short name T351
Test name
Test status
Simulation time 265193893 ps
CPU time 1.81 seconds
Started Jul 20 06:11:48 PM PDT 24
Finished Jul 20 06:11:52 PM PDT 24
Peak memory 200480 kb
Host smart-b02b69e8-b5f6-41b8-acdb-5799c01f819c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214423071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4214423071
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2470559778
Short name T465
Test name
Test status
Simulation time 172449567 ps
CPU time 1.18 seconds
Started Jul 20 06:11:54 PM PDT 24
Finished Jul 20 06:11:58 PM PDT 24
Peak memory 200460 kb
Host smart-ee0cf4d7-600a-47db-bb0b-80a586a47634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470559778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2470559778
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.927284457
Short name T468
Test name
Test status
Simulation time 92987305 ps
CPU time 0.89 seconds
Started Jul 20 06:11:49 PM PDT 24
Finished Jul 20 06:11:52 PM PDT 24
Peak memory 200244 kb
Host smart-b3c81c74-2687-49c5-abf0-7c0969881222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927284457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.927284457
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1759952592
Short name T40
Test name
Test status
Simulation time 1230000052 ps
CPU time 5.35 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:58 PM PDT 24
Peak memory 217780 kb
Host smart-e09c3095-a922-4d26-bb3e-a900b6e0ffe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759952592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1759952592
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3295415520
Short name T448
Test name
Test status
Simulation time 249072064 ps
CPU time 1.1 seconds
Started Jul 20 06:11:53 PM PDT 24
Finished Jul 20 06:11:57 PM PDT 24
Peak memory 217524 kb
Host smart-e1849002-8ddd-4203-87d9-f09473049f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295415520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3295415520
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.4199966900
Short name T268
Test name
Test status
Simulation time 141699126 ps
CPU time 0.8 seconds
Started Jul 20 06:11:49 PM PDT 24
Finished Jul 20 06:11:52 PM PDT 24
Peak memory 200260 kb
Host smart-b07589f8-54fb-4c2e-b3f1-64be452ba344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199966900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.4199966900
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2000625533
Short name T12
Test name
Test status
Simulation time 1338826833 ps
CPU time 5.34 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:57 PM PDT 24
Peak memory 200776 kb
Host smart-aa3a6ecf-81e3-4834-896a-011164739171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000625533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2000625533
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1473681258
Short name T219
Test name
Test status
Simulation time 183364363 ps
CPU time 1.21 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:53 PM PDT 24
Peak memory 200468 kb
Host smart-7d684204-dd3f-4820-93e3-91ca6680584b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473681258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1473681258
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.504507767
Short name T8
Test name
Test status
Simulation time 225607881 ps
CPU time 1.4 seconds
Started Jul 20 06:11:54 PM PDT 24
Finished Jul 20 06:11:58 PM PDT 24
Peak memory 200652 kb
Host smart-082aeb21-d472-44b3-a711-da57db88d45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504507767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.504507767
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3934464373
Short name T338
Test name
Test status
Simulation time 1330417167 ps
CPU time 6.75 seconds
Started Jul 20 06:11:52 PM PDT 24
Finished Jul 20 06:12:02 PM PDT 24
Peak memory 200760 kb
Host smart-b1081dd1-cb71-4e11-946a-78a53778e7bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934464373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3934464373
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1029259565
Short name T235
Test name
Test status
Simulation time 326446263 ps
CPU time 2.16 seconds
Started Jul 20 06:11:52 PM PDT 24
Finished Jul 20 06:11:57 PM PDT 24
Peak memory 200176 kb
Host smart-8ccfc251-20dc-427d-a7a6-98fdf8ef5085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029259565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1029259565
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.129269535
Short name T400
Test name
Test status
Simulation time 201318030 ps
CPU time 1.3 seconds
Started Jul 20 06:11:48 PM PDT 24
Finished Jul 20 06:11:51 PM PDT 24
Peak memory 200460 kb
Host smart-96698a34-d336-4c8a-8619-a03824d5dbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129269535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.129269535
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.45745335
Short name T175
Test name
Test status
Simulation time 77072543 ps
CPU time 0.82 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:52 PM PDT 24
Peak memory 200264 kb
Host smart-c25b8a82-4da0-4a16-a90b-30eb9c5430be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45745335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.45745335
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1782171919
Short name T43
Test name
Test status
Simulation time 1237960906 ps
CPU time 5.46 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:12:00 PM PDT 24
Peak memory 216848 kb
Host smart-f20eb240-60b8-438d-b966-f0c8205498aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782171919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1782171919
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.836334296
Short name T322
Test name
Test status
Simulation time 244289160 ps
CPU time 1.15 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:11:55 PM PDT 24
Peak memory 217516 kb
Host smart-61910396-7eda-4460-bb76-806e45038eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836334296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.836334296
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2597748238
Short name T15
Test name
Test status
Simulation time 199033210 ps
CPU time 1.01 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:53 PM PDT 24
Peak memory 200216 kb
Host smart-25d41b3d-01e1-4549-b667-53c2ff2ccd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597748238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2597748238
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2511554319
Short name T242
Test name
Test status
Simulation time 1470672975 ps
CPU time 6.36 seconds
Started Jul 20 06:11:53 PM PDT 24
Finished Jul 20 06:12:03 PM PDT 24
Peak memory 200764 kb
Host smart-5e9d1235-f5e6-4f50-8cbf-2efd5cca496c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511554319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2511554319
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.4268035923
Short name T206
Test name
Test status
Simulation time 178485616 ps
CPU time 1.25 seconds
Started Jul 20 06:11:45 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 200456 kb
Host smart-5a9644e9-0e5e-45b7-adef-b06b68d5a1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268035923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.4268035923
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.762836786
Short name T214
Test name
Test status
Simulation time 122205939 ps
CPU time 1.3 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:11:55 PM PDT 24
Peak memory 200712 kb
Host smart-2046e1d3-5740-4b8c-ac1a-dee3a35b40b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762836786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.762836786
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1690404033
Short name T131
Test name
Test status
Simulation time 10530316440 ps
CPU time 33.29 seconds
Started Jul 20 06:11:47 PM PDT 24
Finished Jul 20 06:12:22 PM PDT 24
Peak memory 200796 kb
Host smart-d38b3d3c-1388-4608-b984-d4183d342f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690404033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1690404033
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2765155411
Short name T467
Test name
Test status
Simulation time 361579170 ps
CPU time 2.38 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:54 PM PDT 24
Peak memory 200464 kb
Host smart-13d7bb17-4260-462b-8a28-ed15f6097b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765155411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2765155411
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2346462191
Short name T5
Test name
Test status
Simulation time 112244739 ps
CPU time 0.96 seconds
Started Jul 20 06:11:47 PM PDT 24
Finished Jul 20 06:11:50 PM PDT 24
Peak memory 200344 kb
Host smart-30f7f62e-7dbc-4070-ad9b-afd73fe40052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346462191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2346462191
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.802658399
Short name T9
Test name
Test status
Simulation time 83364717 ps
CPU time 0.84 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:11:55 PM PDT 24
Peak memory 200280 kb
Host smart-943fad91-c36d-4c7a-8d5a-e66c43ba5279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802658399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.802658399
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2198367388
Short name T454
Test name
Test status
Simulation time 1235001609 ps
CPU time 5.35 seconds
Started Jul 20 06:11:48 PM PDT 24
Finished Jul 20 06:11:55 PM PDT 24
Peak memory 221740 kb
Host smart-c250924b-aac8-46bf-9bb2-51682a715a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198367388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2198367388
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1383881838
Short name T264
Test name
Test status
Simulation time 244569979 ps
CPU time 1.12 seconds
Started Jul 20 06:11:54 PM PDT 24
Finished Jul 20 06:11:59 PM PDT 24
Peak memory 217472 kb
Host smart-f86bdf08-f80d-458f-a9e7-3c4f04f107ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383881838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1383881838
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2612906385
Short name T247
Test name
Test status
Simulation time 185481076 ps
CPU time 0.85 seconds
Started Jul 20 06:11:54 PM PDT 24
Finished Jul 20 06:11:58 PM PDT 24
Peak memory 200264 kb
Host smart-aba325d6-1456-4cc0-91f4-c6373ba9c9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612906385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2612906385
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1045554200
Short name T130
Test name
Test status
Simulation time 1692550408 ps
CPU time 6.47 seconds
Started Jul 20 06:11:48 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 200732 kb
Host smart-2421d104-5669-4238-861e-35c9187a8124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045554200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1045554200
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1748131324
Short name T421
Test name
Test status
Simulation time 153240127 ps
CPU time 1.12 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:11:55 PM PDT 24
Peak memory 200464 kb
Host smart-81c9598f-e376-42f8-b474-091eeb752164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748131324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1748131324
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2025324855
Short name T430
Test name
Test status
Simulation time 126288534 ps
CPU time 1.22 seconds
Started Jul 20 06:11:49 PM PDT 24
Finished Jul 20 06:11:52 PM PDT 24
Peak memory 200716 kb
Host smart-f6f05011-cef6-4f88-9915-a470a965c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025324855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2025324855
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2004256349
Short name T241
Test name
Test status
Simulation time 2819892991 ps
CPU time 10.07 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:12:02 PM PDT 24
Peak memory 217164 kb
Host smart-e4befaca-a4ea-40c7-bd0f-6fd55950072e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004256349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2004256349
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2492719030
Short name T478
Test name
Test status
Simulation time 148541446 ps
CPU time 1.79 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 200456 kb
Host smart-df1f5327-5298-4096-b7f7-7bec7771b3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492719030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2492719030
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3224498802
Short name T213
Test name
Test status
Simulation time 236787074 ps
CPU time 1.36 seconds
Started Jul 20 06:11:53 PM PDT 24
Finished Jul 20 06:11:57 PM PDT 24
Peak memory 200676 kb
Host smart-f06ec9cf-7d91-4b9a-baa3-524a808e9714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224498802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3224498802
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3450651808
Short name T414
Test name
Test status
Simulation time 83660277 ps
CPU time 0.77 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:53 PM PDT 24
Peak memory 200260 kb
Host smart-fa9870bf-2a89-497b-b938-f52f9bf93003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450651808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3450651808
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.313692835
Short name T374
Test name
Test status
Simulation time 245203932 ps
CPU time 1.09 seconds
Started Jul 20 06:11:54 PM PDT 24
Finished Jul 20 06:11:58 PM PDT 24
Peak memory 217472 kb
Host smart-f3b01a14-eb53-4768-bcc9-0e77ba6d58f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313692835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.313692835
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.137530701
Short name T26
Test name
Test status
Simulation time 156241664 ps
CPU time 0.88 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:54 PM PDT 24
Peak memory 200260 kb
Host smart-32ca5d00-0e42-4f05-a616-15ca64346280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137530701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.137530701
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1366428498
Short name T426
Test name
Test status
Simulation time 845448454 ps
CPU time 4.07 seconds
Started Jul 20 06:11:46 PM PDT 24
Finished Jul 20 06:11:53 PM PDT 24
Peak memory 200656 kb
Host smart-8030645c-2b1d-4d72-adb8-115d31dde479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366428498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1366428498
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1096167285
Short name T255
Test name
Test status
Simulation time 144202172 ps
CPU time 1.15 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:53 PM PDT 24
Peak memory 200448 kb
Host smart-ca674209-8102-425e-b489-930122d813dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096167285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1096167285
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2227189427
Short name T166
Test name
Test status
Simulation time 118033179 ps
CPU time 1.13 seconds
Started Jul 20 06:11:52 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 200668 kb
Host smart-e759cbcd-932c-4910-baca-0e827c831988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227189427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2227189427
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2083691970
Short name T111
Test name
Test status
Simulation time 10597540178 ps
CPU time 33.76 seconds
Started Jul 20 06:11:54 PM PDT 24
Finished Jul 20 06:12:31 PM PDT 24
Peak memory 209780 kb
Host smart-edb3730b-b264-4dcf-ac2f-d6ea9ab7be66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083691970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2083691970
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2540592393
Short name T314
Test name
Test status
Simulation time 135861478 ps
CPU time 1.65 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 208716 kb
Host smart-9d68fd27-99bb-422a-ad4d-d4fa3693a17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540592393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2540592393
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.675436282
Short name T62
Test name
Test status
Simulation time 231192209 ps
CPU time 1.37 seconds
Started Jul 20 06:11:45 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 200616 kb
Host smart-3a031a7f-ad8f-453c-8015-4e364e3d159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675436282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.675436282
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2409537805
Short name T222
Test name
Test status
Simulation time 96158734 ps
CPU time 0.84 seconds
Started Jul 20 06:11:52 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 199852 kb
Host smart-633864ff-e0f5-4e29-a320-08ac8191b6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409537805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2409537805
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.18497319
Short name T278
Test name
Test status
Simulation time 1228908280 ps
CPU time 5.11 seconds
Started Jul 20 06:11:52 PM PDT 24
Finished Jul 20 06:12:00 PM PDT 24
Peak memory 221704 kb
Host smart-11c720bd-5e5a-4f18-aff8-b17b7e38109d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18497319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.18497319
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3478055775
Short name T223
Test name
Test status
Simulation time 243866941 ps
CPU time 1.1 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 217488 kb
Host smart-54f547c9-b834-4cc3-b7f4-ef3720b539ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478055775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3478055775
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1867886327
Short name T276
Test name
Test status
Simulation time 135567410 ps
CPU time 0.79 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:11:54 PM PDT 24
Peak memory 200268 kb
Host smart-950b5e5d-03e1-4485-82cb-f0b8c14a4e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867886327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1867886327
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2336836209
Short name T436
Test name
Test status
Simulation time 923246147 ps
CPU time 4.98 seconds
Started Jul 20 06:11:50 PM PDT 24
Finished Jul 20 06:11:58 PM PDT 24
Peak memory 200784 kb
Host smart-f6811a0b-199c-4a28-a426-fe23526d0abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336836209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2336836209
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3845043780
Short name T238
Test name
Test status
Simulation time 102415544 ps
CPU time 0.99 seconds
Started Jul 20 06:11:54 PM PDT 24
Finished Jul 20 06:11:58 PM PDT 24
Peak memory 200448 kb
Host smart-c898c183-1156-462f-a4c9-7a4cd3dfab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845043780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3845043780
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.935306275
Short name T177
Test name
Test status
Simulation time 126900539 ps
CPU time 1.15 seconds
Started Jul 20 06:11:49 PM PDT 24
Finished Jul 20 06:11:52 PM PDT 24
Peak memory 200680 kb
Host smart-ee9db3c1-9f2f-4f0c-9557-8f3fab24a16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935306275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.935306275
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.257935857
Short name T109
Test name
Test status
Simulation time 5645068386 ps
CPU time 19.87 seconds
Started Jul 20 06:11:51 PM PDT 24
Finished Jul 20 06:12:14 PM PDT 24
Peak memory 208988 kb
Host smart-f16d5c8f-8b9c-47ce-9d8b-f6514d5eb932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257935857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.257935857
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.200382427
Short name T199
Test name
Test status
Simulation time 141814716 ps
CPU time 1.82 seconds
Started Jul 20 06:11:46 PM PDT 24
Finished Jul 20 06:11:50 PM PDT 24
Peak memory 200392 kb
Host smart-e9ca7d03-82e7-48e5-8eca-6a0843ea22f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200382427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.200382427
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2825021204
Short name T191
Test name
Test status
Simulation time 77498238 ps
CPU time 0.8 seconds
Started Jul 20 06:11:52 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 200444 kb
Host smart-7863371d-007e-4861-ae0e-9a1ad045efb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825021204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2825021204
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.291814118
Short name T145
Test name
Test status
Simulation time 82152217 ps
CPU time 0.82 seconds
Started Jul 20 06:10:24 PM PDT 24
Finished Jul 20 06:10:26 PM PDT 24
Peak memory 200264 kb
Host smart-6c2f66d4-6c1d-4592-86b0-fe3618602be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291814118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.291814118
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2188078405
Short name T51
Test name
Test status
Simulation time 1231745129 ps
CPU time 5.8 seconds
Started Jul 20 06:10:24 PM PDT 24
Finished Jul 20 06:10:30 PM PDT 24
Peak memory 221780 kb
Host smart-f074d76f-893e-4792-8a52-c9b2c7a8cef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188078405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2188078405
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3543741670
Short name T88
Test name
Test status
Simulation time 244287324 ps
CPU time 1.13 seconds
Started Jul 20 06:10:22 PM PDT 24
Finished Jul 20 06:10:23 PM PDT 24
Peak memory 217468 kb
Host smart-c59e8053-e3ea-46e9-867d-14efdbc9ccd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543741670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3543741670
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3017432256
Short name T316
Test name
Test status
Simulation time 119405921 ps
CPU time 0.76 seconds
Started Jul 20 06:10:14 PM PDT 24
Finished Jul 20 06:10:15 PM PDT 24
Peak memory 200252 kb
Host smart-c94078ec-d68d-407e-9440-36a38150653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017432256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3017432256
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1026766823
Short name T344
Test name
Test status
Simulation time 986118522 ps
CPU time 4.55 seconds
Started Jul 20 06:10:14 PM PDT 24
Finished Jul 20 06:10:19 PM PDT 24
Peak memory 200716 kb
Host smart-c5c7a4b4-9d6b-4f7e-82f1-b1cb703e4f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026766823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1026766823
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2203916178
Short name T284
Test name
Test status
Simulation time 184356887 ps
CPU time 1.17 seconds
Started Jul 20 06:10:11 PM PDT 24
Finished Jul 20 06:10:13 PM PDT 24
Peak memory 200440 kb
Host smart-0c884fb8-c8ad-4758-8e8e-5dc8cb356e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203916178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2203916178
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.786943355
Short name T306
Test name
Test status
Simulation time 197414977 ps
CPU time 1.31 seconds
Started Jul 20 06:10:15 PM PDT 24
Finished Jul 20 06:10:17 PM PDT 24
Peak memory 200660 kb
Host smart-7af3cb32-1a2c-4911-8936-6d7f04ee31e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786943355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.786943355
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2801718193
Short name T352
Test name
Test status
Simulation time 8282016991 ps
CPU time 26.58 seconds
Started Jul 20 06:10:23 PM PDT 24
Finished Jul 20 06:10:50 PM PDT 24
Peak memory 210688 kb
Host smart-e5804fb5-1d58-41a2-8123-566780c51695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801718193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2801718193
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3759984172
Short name T163
Test name
Test status
Simulation time 113402143 ps
CPU time 1.48 seconds
Started Jul 20 06:10:14 PM PDT 24
Finished Jul 20 06:10:16 PM PDT 24
Peak memory 200456 kb
Host smart-76c4029f-425e-4175-bbcd-51b1a5a58ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759984172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3759984172
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.127429147
Short name T183
Test name
Test status
Simulation time 91498314 ps
CPU time 0.88 seconds
Started Jul 20 06:10:13 PM PDT 24
Finished Jul 20 06:10:15 PM PDT 24
Peak memory 200452 kb
Host smart-99cda681-002a-4308-8583-5b90e9e60645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127429147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.127429147
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2565894536
Short name T353
Test name
Test status
Simulation time 73896810 ps
CPU time 0.75 seconds
Started Jul 20 06:10:19 PM PDT 24
Finished Jul 20 06:10:21 PM PDT 24
Peak memory 200180 kb
Host smart-ad0a1629-7016-4bbb-a110-a9053a42524c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565894536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2565894536
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1403655917
Short name T381
Test name
Test status
Simulation time 1245530935 ps
CPU time 5.52 seconds
Started Jul 20 06:10:25 PM PDT 24
Finished Jul 20 06:10:31 PM PDT 24
Peak memory 217564 kb
Host smart-f1bd9a62-f2ab-4eec-ba04-9c4825dbbd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403655917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1403655917
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2598142432
Short name T310
Test name
Test status
Simulation time 244862769 ps
CPU time 1.04 seconds
Started Jul 20 06:10:23 PM PDT 24
Finished Jul 20 06:10:24 PM PDT 24
Peak memory 217452 kb
Host smart-421214b9-b536-46b3-85f0-aae3eb86be97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598142432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2598142432
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.192331955
Short name T520
Test name
Test status
Simulation time 145454524 ps
CPU time 0.85 seconds
Started Jul 20 06:10:23 PM PDT 24
Finished Jul 20 06:10:24 PM PDT 24
Peak memory 200256 kb
Host smart-29da13ae-f265-4b28-8338-cf903583892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192331955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.192331955
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.4215190109
Short name T376
Test name
Test status
Simulation time 1365748968 ps
CPU time 5.65 seconds
Started Jul 20 06:10:22 PM PDT 24
Finished Jul 20 06:10:29 PM PDT 24
Peak memory 200776 kb
Host smart-adb6a997-9f9a-4c18-8a38-ca92a818eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215190109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4215190109
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.809647017
Short name T438
Test name
Test status
Simulation time 152659607 ps
CPU time 1.16 seconds
Started Jul 20 06:10:22 PM PDT 24
Finished Jul 20 06:10:23 PM PDT 24
Peak memory 200468 kb
Host smart-a938aa0e-cf8c-4756-a832-929e91d2bcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809647017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.809647017
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3026818496
Short name T45
Test name
Test status
Simulation time 198329064 ps
CPU time 1.34 seconds
Started Jul 20 06:10:23 PM PDT 24
Finished Jul 20 06:10:25 PM PDT 24
Peak memory 200672 kb
Host smart-23171e75-8498-4519-94ae-a3e9930c95a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026818496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3026818496
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3976311736
Short name T299
Test name
Test status
Simulation time 7798434453 ps
CPU time 31.53 seconds
Started Jul 20 06:10:24 PM PDT 24
Finished Jul 20 06:10:56 PM PDT 24
Peak memory 208992 kb
Host smart-7928b638-0c15-4610-bf47-520c44ce670b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976311736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3976311736
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1796193810
Short name T503
Test name
Test status
Simulation time 314657017 ps
CPU time 2.13 seconds
Started Jul 20 06:10:25 PM PDT 24
Finished Jul 20 06:10:28 PM PDT 24
Peak memory 200468 kb
Host smart-4e8d92d7-601f-4762-b729-4e42fed92f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796193810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1796193810
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3323566756
Short name T523
Test name
Test status
Simulation time 103573918 ps
CPU time 0.84 seconds
Started Jul 20 06:10:22 PM PDT 24
Finished Jul 20 06:10:24 PM PDT 24
Peak memory 200464 kb
Host smart-44b8cc33-af15-4c84-a345-8851be3e5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323566756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3323566756
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3657006323
Short name T493
Test name
Test status
Simulation time 88872181 ps
CPU time 0.82 seconds
Started Jul 20 06:10:32 PM PDT 24
Finished Jul 20 06:10:33 PM PDT 24
Peak memory 200260 kb
Host smart-da6b420e-82f1-4eb5-8c1d-1a952a8d29b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657006323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3657006323
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2511574726
Short name T521
Test name
Test status
Simulation time 1222120083 ps
CPU time 5.23 seconds
Started Jul 20 06:10:29 PM PDT 24
Finished Jul 20 06:10:35 PM PDT 24
Peak memory 220808 kb
Host smart-ca25775f-a14d-4d94-a033-9b2ae6026b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511574726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2511574726
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1712964107
Short name T510
Test name
Test status
Simulation time 243868629 ps
CPU time 1.13 seconds
Started Jul 20 06:10:30 PM PDT 24
Finished Jul 20 06:10:32 PM PDT 24
Peak memory 217476 kb
Host smart-5c08c9a4-3c3d-4139-aef8-65246d1f716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712964107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1712964107
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2175909269
Short name T181
Test name
Test status
Simulation time 218076753 ps
CPU time 0.84 seconds
Started Jul 20 06:10:22 PM PDT 24
Finished Jul 20 06:10:24 PM PDT 24
Peak memory 200280 kb
Host smart-3577a002-b576-4b54-b37a-7d0119b99b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175909269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2175909269
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.14294466
Short name T274
Test name
Test status
Simulation time 1894870351 ps
CPU time 7.37 seconds
Started Jul 20 06:10:19 PM PDT 24
Finished Jul 20 06:10:27 PM PDT 24
Peak memory 200764 kb
Host smart-b7afe9d0-1212-4dbc-b552-d98ba785137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14294466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.14294466
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2748908804
Short name T29
Test name
Test status
Simulation time 183862734 ps
CPU time 1.2 seconds
Started Jul 20 06:10:24 PM PDT 24
Finished Jul 20 06:10:26 PM PDT 24
Peak memory 200452 kb
Host smart-2f22d4f9-dbc3-4eaa-a110-13c7b3d24503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748908804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2748908804
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2216636854
Short name T86
Test name
Test status
Simulation time 117940674 ps
CPU time 1.17 seconds
Started Jul 20 06:10:23 PM PDT 24
Finished Jul 20 06:10:25 PM PDT 24
Peak memory 200664 kb
Host smart-7d6fac0b-bd8a-4c47-8642-0c672cdda719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216636854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2216636854
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.624889017
Short name T492
Test name
Test status
Simulation time 6904416946 ps
CPU time 23.68 seconds
Started Jul 20 06:10:32 PM PDT 24
Finished Jul 20 06:10:56 PM PDT 24
Peak memory 216564 kb
Host smart-6b53317d-96f2-4dc4-9949-72579e0a0b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624889017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.624889017
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2476268329
Short name T97
Test name
Test status
Simulation time 507733408 ps
CPU time 2.63 seconds
Started Jul 20 06:10:21 PM PDT 24
Finished Jul 20 06:10:24 PM PDT 24
Peak memory 200476 kb
Host smart-c9e00d4c-b7c9-4c2b-924d-cd1249d97471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476268329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2476268329
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.473878774
Short name T303
Test name
Test status
Simulation time 65439084 ps
CPU time 0.73 seconds
Started Jul 20 06:10:22 PM PDT 24
Finished Jul 20 06:10:23 PM PDT 24
Peak memory 200468 kb
Host smart-42e90420-c604-4eee-965f-7cca8b6d4619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473878774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.473878774
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1469705213
Short name T462
Test name
Test status
Simulation time 66229767 ps
CPU time 0.8 seconds
Started Jul 20 06:10:31 PM PDT 24
Finished Jul 20 06:10:33 PM PDT 24
Peak memory 200280 kb
Host smart-48deb0e9-f284-4125-ba46-875b4728ce87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469705213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1469705213
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1647699853
Short name T52
Test name
Test status
Simulation time 2166678870 ps
CPU time 9.09 seconds
Started Jul 20 06:10:32 PM PDT 24
Finished Jul 20 06:10:42 PM PDT 24
Peak memory 217412 kb
Host smart-a5321981-9807-4ac8-a58e-83d4f0d809ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647699853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1647699853
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.869070341
Short name T221
Test name
Test status
Simulation time 244578749 ps
CPU time 1.02 seconds
Started Jul 20 06:10:31 PM PDT 24
Finished Jul 20 06:10:33 PM PDT 24
Peak memory 217472 kb
Host smart-fdc4b12f-f111-4985-8f93-b9bed3ce1806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869070341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.869070341
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1095026769
Short name T293
Test name
Test status
Simulation time 101896811 ps
CPU time 0.77 seconds
Started Jul 20 06:10:31 PM PDT 24
Finished Jul 20 06:10:33 PM PDT 24
Peak memory 200280 kb
Host smart-6d2443f0-34cb-488b-a817-d65b33c913d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095026769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1095026769
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.60847028
Short name T209
Test name
Test status
Simulation time 1499407847 ps
CPU time 6.6 seconds
Started Jul 20 06:10:31 PM PDT 24
Finished Jul 20 06:10:39 PM PDT 24
Peak memory 200644 kb
Host smart-9040e44a-29f4-4b5e-b733-82e8ce4b2120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60847028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.60847028
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.610446042
Short name T165
Test name
Test status
Simulation time 104950627 ps
CPU time 1.03 seconds
Started Jul 20 06:10:30 PM PDT 24
Finished Jul 20 06:10:32 PM PDT 24
Peak memory 200428 kb
Host smart-b7025fc8-1e46-4d61-b20c-e239aff70de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610446042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.610446042
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2417519712
Short name T179
Test name
Test status
Simulation time 119034904 ps
CPU time 1.15 seconds
Started Jul 20 06:10:31 PM PDT 24
Finished Jul 20 06:10:33 PM PDT 24
Peak memory 200552 kb
Host smart-7e183002-75ad-4feb-a8c9-7cafaeb129db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417519712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2417519712
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2932479352
Short name T504
Test name
Test status
Simulation time 4451403549 ps
CPU time 19.63 seconds
Started Jul 20 06:10:33 PM PDT 24
Finished Jul 20 06:10:53 PM PDT 24
Peak memory 200792 kb
Host smart-061015de-3cea-4cc1-832b-0c4d5fcda723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932479352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2932479352
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.569976077
Short name T389
Test name
Test status
Simulation time 531449372 ps
CPU time 2.73 seconds
Started Jul 20 06:10:31 PM PDT 24
Finished Jul 20 06:10:35 PM PDT 24
Peak memory 200480 kb
Host smart-78915fbf-5cb9-433e-bd30-ba77ceac3311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569976077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.569976077
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2002583086
Short name T169
Test name
Test status
Simulation time 198281580 ps
CPU time 1.29 seconds
Started Jul 20 06:10:32 PM PDT 24
Finished Jul 20 06:10:34 PM PDT 24
Peak memory 200464 kb
Host smart-ee847034-f185-464a-8082-c82cffc8a1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002583086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2002583086
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3127240910
Short name T302
Test name
Test status
Simulation time 58658600 ps
CPU time 0.73 seconds
Started Jul 20 06:10:54 PM PDT 24
Finished Jul 20 06:10:57 PM PDT 24
Peak memory 200260 kb
Host smart-ba013cca-c8b5-4566-97c7-23e78daed639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127240910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3127240910
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4280897209
Short name T497
Test name
Test status
Simulation time 1219035183 ps
CPU time 5.79 seconds
Started Jul 20 06:10:39 PM PDT 24
Finished Jul 20 06:10:45 PM PDT 24
Peak memory 221772 kb
Host smart-e08099c2-33bd-4b96-ab07-2569adf8fe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280897209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4280897209
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2422402862
Short name T141
Test name
Test status
Simulation time 244065161 ps
CPU time 1.05 seconds
Started Jul 20 06:10:49 PM PDT 24
Finished Jul 20 06:10:53 PM PDT 24
Peak memory 217540 kb
Host smart-5ebbb6d0-99ff-4adb-b989-bc3a81b1f2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422402862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2422402862
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2985203865
Short name T229
Test name
Test status
Simulation time 196865793 ps
CPU time 0.89 seconds
Started Jul 20 06:10:29 PM PDT 24
Finished Jul 20 06:10:30 PM PDT 24
Peak memory 200228 kb
Host smart-4641e5bf-784a-4bc9-a01c-002a25d61d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985203865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2985203865
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1961478512
Short name T508
Test name
Test status
Simulation time 1281838156 ps
CPU time 5.47 seconds
Started Jul 20 06:10:31 PM PDT 24
Finished Jul 20 06:10:37 PM PDT 24
Peak memory 200768 kb
Host smart-abd14b62-6c19-40f9-8705-058e00e77d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961478512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1961478512
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.514202652
Short name T147
Test name
Test status
Simulation time 169365935 ps
CPU time 1.14 seconds
Started Jul 20 06:10:51 PM PDT 24
Finished Jul 20 06:10:55 PM PDT 24
Peak memory 200360 kb
Host smart-8199d0aa-444f-4179-817b-e3b8b90b4457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514202652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.514202652
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1704323591
Short name T377
Test name
Test status
Simulation time 115361167 ps
CPU time 1.11 seconds
Started Jul 20 06:10:28 PM PDT 24
Finished Jul 20 06:10:30 PM PDT 24
Peak memory 200696 kb
Host smart-5e47ba27-c597-466b-aca0-b155470c1ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704323591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1704323591
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.181979379
Short name T132
Test name
Test status
Simulation time 6083038340 ps
CPU time 19.95 seconds
Started Jul 20 06:10:40 PM PDT 24
Finished Jul 20 06:11:00 PM PDT 24
Peak memory 208980 kb
Host smart-1f727de1-d4ce-4099-96d1-3330c708e7b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181979379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.181979379
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1188416675
Short name T187
Test name
Test status
Simulation time 383278004 ps
CPU time 2.31 seconds
Started Jul 20 06:10:32 PM PDT 24
Finished Jul 20 06:10:35 PM PDT 24
Peak memory 200484 kb
Host smart-27b75d9a-9d81-4d9b-8d59-4f177ef82393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188416675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1188416675
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1911440839
Short name T480
Test name
Test status
Simulation time 143907541 ps
CPU time 1.1 seconds
Started Jul 20 06:10:33 PM PDT 24
Finished Jul 20 06:10:34 PM PDT 24
Peak memory 200460 kb
Host smart-a8279978-8bd6-406d-9f4a-7059067a130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911440839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1911440839
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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