Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8027

1

T2

13

T6

116

T7

15

auto[1]

10936

1

T2

1

T3

4

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5880	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6349	1			T1	1		T2	1		T3	2
reset_info_cp[2]	3010	1			T3	1		T4	1		T6	41
reset_info_cp[4]	3793	1			T3	1		T4	1		T6	61
reset_info_cp[8]	106	1			T8	1		T41	1		T32	1
reset_info_cp[16]	93	1			T9	1		T43	1		T33	1
reset_info_cp[32]	117	1			T2	1		T6	1		T9	1
reset_info_cp[64]	118	1			T6	2		T7	1		T11	1
reset_info_cp[128]	117	1			T2	1		T6	1		T9	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3046	1			T6	36		T7	15		T8	14
reset_info_cp[1]	auto[1]	2683	1			T3	1		T4	1		T6	38
reset_info_cp[2]	auto[0]	956	1			T6	18		T11	2		T48	8
reset_info_cp[2]	auto[1]	2054	1			T3	1		T4	1		T6	23
reset_info_cp[4]	auto[0]	1354	1			T6	25		T11	6		T48	10
reset_info_cp[4]	auto[1]	2439	1			T3	1		T4	1		T6	36
reset_info_cp[8]	auto[0]	42	1			T23	1		T136	1		T134	1
reset_info_cp[8]	auto[1]	64	1			T8	1		T41	1		T32	1
reset_info_cp[16]	auto[0]	40	1			T43	1		T23	2		T127	1
reset_info_cp[16]	auto[1]	53	1			T9	1		T33	1		T23	1
reset_info_cp[32]	auto[0]	51	1			T2	1		T12	2		T41	1
reset_info_cp[32]	auto[1]	66	1			T6	1		T9	1		T25	1
reset_info_cp[64]	auto[0]	49	1			T6	2		T23	3		T85	1
reset_info_cp[64]	auto[1]	69	1			T7	1		T11	1		T32	1
reset_info_cp[128]	auto[0]	47	1			T2	1		T11	1		T43	1
reset_info_cp[128]	auto[1]	70	1			T6	1		T9	1		T32	1