Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T534 /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1806017899 Jul 21 05:47:42 PM PDT 24 Jul 21 05:47:51 PM PDT 24 2349960022 ps
T535 /workspace/coverage/default/33.rstmgr_stress_all.362074921 Jul 21 05:48:23 PM PDT 24 Jul 21 05:48:29 PM PDT 24 1117325067 ps
T536 /workspace/coverage/default/46.rstmgr_smoke.3007652288 Jul 21 05:48:55 PM PDT 24 Jul 21 05:48:56 PM PDT 24 202825751 ps
T537 /workspace/coverage/default/14.rstmgr_reset.448585964 Jul 21 05:47:25 PM PDT 24 Jul 21 05:47:29 PM PDT 24 836041440 ps
T538 /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3726344807 Jul 21 05:47:53 PM PDT 24 Jul 21 05:48:01 PM PDT 24 1890672213 ps
T66 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1983352648 Jul 21 05:39:51 PM PDT 24 Jul 21 05:39:53 PM PDT 24 98322540 ps
T61 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3510542101 Jul 21 05:39:56 PM PDT 24 Jul 21 05:39:58 PM PDT 24 153484032 ps
T62 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.295704144 Jul 21 05:39:49 PM PDT 24 Jul 21 05:39:50 PM PDT 24 124998044 ps
T63 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3779573646 Jul 21 05:39:51 PM PDT 24 Jul 21 05:39:56 PM PDT 24 939113395 ps
T64 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3644766523 Jul 21 05:39:49 PM PDT 24 Jul 21 05:39:51 PM PDT 24 195529188 ps
T67 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2759788705 Jul 21 05:39:57 PM PDT 24 Jul 21 05:40:01 PM PDT 24 140036784 ps
T68 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.946521389 Jul 21 05:40:04 PM PDT 24 Jul 21 05:40:07 PM PDT 24 280034980 ps
T107 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1266047430 Jul 21 05:39:45 PM PDT 24 Jul 21 05:39:48 PM PDT 24 234701165 ps
T108 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4274897266 Jul 21 05:39:51 PM PDT 24 Jul 21 05:39:52 PM PDT 24 53943601 ps
T72 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4052298396 Jul 21 05:39:55 PM PDT 24 Jul 21 05:39:57 PM PDT 24 117943151 ps
T109 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3301785696 Jul 21 05:39:49 PM PDT 24 Jul 21 05:39:50 PM PDT 24 81903262 ps
T90 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2588141273 Jul 21 05:39:44 PM PDT 24 Jul 21 05:39:48 PM PDT 24 918741860 ps
T110 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.490939408 Jul 21 05:40:03 PM PDT 24 Jul 21 05:40:05 PM PDT 24 261833177 ps
T91 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3579752056 Jul 21 05:39:52 PM PDT 24 Jul 21 05:39:54 PM PDT 24 135570830 ps
T92 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.724053265 Jul 21 05:39:58 PM PDT 24 Jul 21 05:40:01 PM PDT 24 171689716 ps
T93 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1089451040 Jul 21 05:39:48 PM PDT 24 Jul 21 05:39:51 PM PDT 24 126283846 ps
T94 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2106979104 Jul 21 05:39:54 PM PDT 24 Jul 21 05:39:57 PM PDT 24 295457607 ps
T95 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1628277970 Jul 21 05:39:54 PM PDT 24 Jul 21 05:39:56 PM PDT 24 480332910 ps
T539 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1502498843 Jul 21 05:39:55 PM PDT 24 Jul 21 05:39:57 PM PDT 24 209283683 ps
T116 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4148677918 Jul 21 05:39:41 PM PDT 24 Jul 21 05:39:43 PM PDT 24 91400525 ps
T111 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.85456330 Jul 21 05:39:45 PM PDT 24 Jul 21 05:39:47 PM PDT 24 141998594 ps
T540 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1171416741 Jul 21 05:39:45 PM PDT 24 Jul 21 05:39:47 PM PDT 24 94734995 ps
T117 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2434521743 Jul 21 05:40:02 PM PDT 24 Jul 21 05:40:06 PM PDT 24 776494211 ps
T541 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2532134021 Jul 21 05:40:04 PM PDT 24 Jul 21 05:40:06 PM PDT 24 192954556 ps
T542 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.123545830 Jul 21 05:39:49 PM PDT 24 Jul 21 05:39:51 PM PDT 24 235240305 ps
T115 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2113107637 Jul 21 05:39:53 PM PDT 24 Jul 21 05:39:55 PM PDT 24 103858772 ps
T543 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2208478713 Jul 21 05:39:53 PM PDT 24 Jul 21 05:39:54 PM PDT 24 56940340 ps
T112 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.178799703 Jul 21 05:39:55 PM PDT 24 Jul 21 05:39:57 PM PDT 24 64286669 ps
T131 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1091068187 Jul 21 05:40:01 PM PDT 24 Jul 21 05:40:04 PM PDT 24 430076263 ps
T121 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2008984063 Jul 21 05:39:55 PM PDT 24 Jul 21 05:39:59 PM PDT 24 775661901 ps
T544 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1819909095 Jul 21 05:39:43 PM PDT 24 Jul 21 05:39:45 PM PDT 24 131415710 ps
T113 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.442767882 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:38 PM PDT 24 77734405 ps
T545 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2700360426 Jul 21 05:40:06 PM PDT 24 Jul 21 05:40:07 PM PDT 24 82078651 ps
T114 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.422742701 Jul 21 05:39:41 PM PDT 24 Jul 21 05:39:43 PM PDT 24 67074689 ps
T546 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.442412249 Jul 21 05:39:40 PM PDT 24 Jul 21 05:39:43 PM PDT 24 353957905 ps
T118 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.61249529 Jul 21 05:40:02 PM PDT 24 Jul 21 05:40:05 PM PDT 24 893712767 ps
T547 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1642954341 Jul 21 05:40:06 PM PDT 24 Jul 21 05:40:07 PM PDT 24 141949949 ps
T98 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3893296765 Jul 21 05:39:44 PM PDT 24 Jul 21 05:39:46 PM PDT 24 60610591 ps
T548 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.660566798 Jul 21 05:39:54 PM PDT 24 Jul 21 05:39:57 PM PDT 24 957042732 ps
T549 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3728214393 Jul 21 05:40:11 PM PDT 24 Jul 21 05:40:13 PM PDT 24 242859347 ps
T550 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2378287189 Jul 21 05:39:59 PM PDT 24 Jul 21 05:40:00 PM PDT 24 121897751 ps
T551 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2736398514 Jul 21 05:40:05 PM PDT 24 Jul 21 05:40:07 PM PDT 24 238946099 ps
T552 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.124513371 Jul 21 05:39:37 PM PDT 24 Jul 21 05:39:42 PM PDT 24 464278870 ps
T553 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3967391408 Jul 21 05:39:38 PM PDT 24 Jul 21 05:39:41 PM PDT 24 87038720 ps
T554 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1663809285 Jul 21 05:39:57 PM PDT 24 Jul 21 05:39:59 PM PDT 24 165582859 ps
T555 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3874976084 Jul 21 05:39:50 PM PDT 24 Jul 21 05:39:52 PM PDT 24 120540626 ps
T556 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2938345082 Jul 21 05:39:57 PM PDT 24 Jul 21 05:40:01 PM PDT 24 186533494 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4173865934 Jul 21 05:39:43 PM PDT 24 Jul 21 05:39:45 PM PDT 24 65707816 ps
T558 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1369144307 Jul 21 05:39:41 PM PDT 24 Jul 21 05:39:44 PM PDT 24 180243825 ps
T559 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.605673104 Jul 21 05:39:39 PM PDT 24 Jul 21 05:39:43 PM PDT 24 771321299 ps
T560 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2180912314 Jul 21 05:39:50 PM PDT 24 Jul 21 05:39:52 PM PDT 24 82248035 ps
T561 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.632185922 Jul 21 05:39:55 PM PDT 24 Jul 21 05:39:57 PM PDT 24 217076047 ps
T562 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3300874027 Jul 21 05:39:39 PM PDT 24 Jul 21 05:39:43 PM PDT 24 390696620 ps
T563 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.669064382 Jul 21 05:39:55 PM PDT 24 Jul 21 05:39:59 PM PDT 24 215991862 ps
T564 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2142541895 Jul 21 05:39:48 PM PDT 24 Jul 21 05:39:51 PM PDT 24 484872619 ps
T132 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.418659978 Jul 21 05:39:46 PM PDT 24 Jul 21 05:39:50 PM PDT 24 1032626558 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3810488711 Jul 21 05:39:43 PM PDT 24 Jul 21 05:39:47 PM PDT 24 340957593 ps
T566 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2427515679 Jul 21 05:39:50 PM PDT 24 Jul 21 05:39:52 PM PDT 24 131866267 ps
T567 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2352361121 Jul 21 05:39:56 PM PDT 24 Jul 21 05:39:59 PM PDT 24 57198725 ps
T568 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.466643347 Jul 21 05:39:51 PM PDT 24 Jul 21 05:39:52 PM PDT 24 66742498 ps
T569 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2481688284 Jul 21 05:40:04 PM PDT 24 Jul 21 05:40:06 PM PDT 24 66105924 ps
T570 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3256594242 Jul 21 05:39:57 PM PDT 24 Jul 21 05:39:59 PM PDT 24 79247595 ps
T571 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2603724766 Jul 21 05:39:45 PM PDT 24 Jul 21 05:39:47 PM PDT 24 102994085 ps
T572 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2649843037 Jul 21 05:40:02 PM PDT 24 Jul 21 05:40:04 PM PDT 24 163949261 ps
T573 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2115292736 Jul 21 05:39:46 PM PDT 24 Jul 21 05:39:50 PM PDT 24 428872550 ps
T574 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3072392470 Jul 21 05:39:54 PM PDT 24 Jul 21 05:39:56 PM PDT 24 301816947 ps
T575 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2879887426 Jul 21 05:39:42 PM PDT 24 Jul 21 05:39:50 PM PDT 24 483496069 ps
T576 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4129718279 Jul 21 05:40:03 PM PDT 24 Jul 21 05:40:06 PM PDT 24 188032908 ps
T577 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3577467125 Jul 21 05:39:48 PM PDT 24 Jul 21 05:39:50 PM PDT 24 136240075 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1003047408 Jul 21 05:39:41 PM PDT 24 Jul 21 05:39:42 PM PDT 24 107249230 ps
T579 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1616726138 Jul 21 05:39:51 PM PDT 24 Jul 21 05:39:53 PM PDT 24 124652314 ps
T580 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2717811203 Jul 21 05:39:43 PM PDT 24 Jul 21 05:39:46 PM PDT 24 215439788 ps
T581 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3647332155 Jul 21 05:39:41 PM PDT 24 Jul 21 05:39:43 PM PDT 24 77156070 ps
T582 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2958453067 Jul 21 05:40:01 PM PDT 24 Jul 21 05:40:03 PM PDT 24 129120686 ps
T583 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3689148033 Jul 21 05:39:56 PM PDT 24 Jul 21 05:40:00 PM PDT 24 478374059 ps
T584 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3707596887 Jul 21 05:39:37 PM PDT 24 Jul 21 05:39:40 PM PDT 24 68286074 ps
T585 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1429385185 Jul 21 05:39:38 PM PDT 24 Jul 21 05:39:42 PM PDT 24 504320201 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1254703754 Jul 21 05:39:39 PM PDT 24 Jul 21 05:39:45 PM PDT 24 803788474 ps
T587 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2513593362 Jul 21 05:39:47 PM PDT 24 Jul 21 05:39:50 PM PDT 24 360779540 ps
T588 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.537791612 Jul 21 05:40:24 PM PDT 24 Jul 21 05:40:27 PM PDT 24 178665762 ps
T589 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.852953983 Jul 21 05:39:56 PM PDT 24 Jul 21 05:40:00 PM PDT 24 245530298 ps
T122 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1447943616 Jul 21 05:39:42 PM PDT 24 Jul 21 05:39:45 PM PDT 24 872487343 ps
T590 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2124601567 Jul 21 05:39:55 PM PDT 24 Jul 21 05:39:57 PM PDT 24 84949741 ps
T591 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2383045971 Jul 21 05:39:52 PM PDT 24 Jul 21 05:39:56 PM PDT 24 833403967 ps
T592 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3788579998 Jul 21 05:39:46 PM PDT 24 Jul 21 05:39:49 PM PDT 24 249701287 ps
T593 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3485765669 Jul 21 05:39:55 PM PDT 24 Jul 21 05:39:56 PM PDT 24 55151178 ps
T594 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2003561845 Jul 21 05:39:51 PM PDT 24 Jul 21 05:39:54 PM PDT 24 185284421 ps
T595 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3925515975 Jul 21 05:39:42 PM PDT 24 Jul 21 05:39:45 PM PDT 24 106077396 ps
T596 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.257034186 Jul 21 05:39:56 PM PDT 24 Jul 21 05:39:59 PM PDT 24 459085723 ps
T597 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1995116425 Jul 21 05:39:54 PM PDT 24 Jul 21 05:39:57 PM PDT 24 189035779 ps
T119 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1777728600 Jul 21 05:39:55 PM PDT 24 Jul 21 05:39:59 PM PDT 24 774462413 ps
T598 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2940189003 Jul 21 05:39:42 PM PDT 24 Jul 21 05:39:48 PM PDT 24 806738730 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1571413536 Jul 21 05:39:37 PM PDT 24 Jul 21 05:39:39 PM PDT 24 90443443 ps
T600 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2811599710 Jul 21 05:39:38 PM PDT 24 Jul 21 05:39:41 PM PDT 24 161407974 ps
T601 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2085082106 Jul 21 05:39:56 PM PDT 24 Jul 21 05:40:01 PM PDT 24 537406728 ps
T602 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2972271027 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:40 PM PDT 24 417490416 ps
T603 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.35104128 Jul 21 05:40:02 PM PDT 24 Jul 21 05:40:04 PM PDT 24 130451228 ps
T604 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1617555219 Jul 21 05:39:42 PM PDT 24 Jul 21 05:39:49 PM PDT 24 478786747 ps
T605 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3209400474 Jul 21 05:39:57 PM PDT 24 Jul 21 05:40:00 PM PDT 24 492402128 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4020337304 Jul 21 05:40:01 PM PDT 24 Jul 21 05:40:02 PM PDT 24 56582736 ps
T607 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.605151689 Jul 21 05:39:57 PM PDT 24 Jul 21 05:39:59 PM PDT 24 83274911 ps
T608 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3195834855 Jul 21 05:39:45 PM PDT 24 Jul 21 05:39:49 PM PDT 24 362778282 ps
T609 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1797097371 Jul 21 05:39:50 PM PDT 24 Jul 21 05:39:52 PM PDT 24 161154636 ps
T610 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.589321464 Jul 21 05:39:47 PM PDT 24 Jul 21 05:39:48 PM PDT 24 64663436 ps
T611 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1481130985 Jul 21 05:39:56 PM PDT 24 Jul 21 05:39:58 PM PDT 24 73147627 ps
T612 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.889418127 Jul 21 05:39:42 PM PDT 24 Jul 21 05:39:44 PM PDT 24 94907999 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3860222209 Jul 21 05:39:41 PM PDT 24 Jul 21 05:39:44 PM PDT 24 201540881 ps
T614 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1614639749 Jul 21 05:39:37 PM PDT 24 Jul 21 05:39:40 PM PDT 24 141364852 ps
T615 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3057869483 Jul 21 05:40:11 PM PDT 24 Jul 21 05:40:13 PM PDT 24 126283678 ps
T616 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1019015702 Jul 21 05:39:40 PM PDT 24 Jul 21 05:39:46 PM PDT 24 808250130 ps
T617 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2512876313 Jul 21 05:39:50 PM PDT 24 Jul 21 05:39:52 PM PDT 24 76486157 ps
T618 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3813703691 Jul 21 05:39:52 PM PDT 24 Jul 21 05:39:54 PM PDT 24 473534538 ps
T619 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4197292087 Jul 21 05:39:50 PM PDT 24 Jul 21 05:39:51 PM PDT 24 61981217 ps
T620 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.745030459 Jul 21 05:39:57 PM PDT 24 Jul 21 05:40:02 PM PDT 24 481656977 ps
T120 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2157374306 Jul 21 05:39:41 PM PDT 24 Jul 21 05:39:44 PM PDT 24 504694944 ps

Test location /workspace/coverage/default/47.rstmgr_stress_all.1838459096
Short name T6
Test name
Test status
Simulation time 4308018074 ps
CPU time 19.93 seconds
Started Jul 21 05:49:00 PM PDT 24
Finished Jul 21 05:49:20 PM PDT 24
Peak memory 208992 kb
Host smart-ea67a242-5f0b-4e22-91cc-861cd439f1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838459096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1838459096
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2018495111
Short name T59
Test name
Test status
Simulation time 456445820 ps
CPU time 2.45 seconds
Started Jul 21 05:48:21 PM PDT 24
Finished Jul 21 05:48:24 PM PDT 24
Peak memory 200496 kb
Host smart-f03770fa-fe36-4f13-8d38-eeb72f1d25c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018495111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2018495111
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2588141273
Short name T90
Test name
Test status
Simulation time 918741860 ps
CPU time 3.28 seconds
Started Jul 21 05:39:44 PM PDT 24
Finished Jul 21 05:39:48 PM PDT 24
Peak memory 200296 kb
Host smart-7bf134d8-25ad-47e7-8fff-5a9106bdf789
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588141273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2588141273
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1564353840
Short name T74
Test name
Test status
Simulation time 16725119296 ps
CPU time 25.22 seconds
Started Jul 21 05:46:17 PM PDT 24
Finished Jul 21 05:46:42 PM PDT 24
Peak memory 217332 kb
Host smart-7f26fc7f-c1fe-4487-aae6-8f68da11c5d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564353840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1564353840
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2793999505
Short name T8
Test name
Test status
Simulation time 2365956503 ps
CPU time 8.37 seconds
Started Jul 21 05:47:32 PM PDT 24
Finished Jul 21 05:47:40 PM PDT 24
Peak memory 217952 kb
Host smart-10f4c0a8-e7f2-4881-ab16-6024be562f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793999505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2793999505
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1983352648
Short name T66
Test name
Test status
Simulation time 98322540 ps
CPU time 1.31 seconds
Started Jul 21 05:39:51 PM PDT 24
Finished Jul 21 05:39:53 PM PDT 24
Peak memory 208472 kb
Host smart-d1c477d9-b888-46b4-8a6e-44d825ac9523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983352648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1983352648
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3276514256
Short name T44
Test name
Test status
Simulation time 82734895 ps
CPU time 0.82 seconds
Started Jul 21 05:48:15 PM PDT 24
Finished Jul 21 05:48:17 PM PDT 24
Peak memory 200156 kb
Host smart-868bea67-c33a-4556-85c1-90e5cd9686be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276514256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3276514256
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3624674752
Short name T23
Test name
Test status
Simulation time 8966985700 ps
CPU time 33.15 seconds
Started Jul 21 05:46:50 PM PDT 24
Finished Jul 21 05:47:24 PM PDT 24
Peak memory 200792 kb
Host smart-12cd7972-6a16-4ba4-b746-a2a9508ad8c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624674752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3624674752
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.445075853
Short name T133
Test name
Test status
Simulation time 109579561 ps
CPU time 0.99 seconds
Started Jul 21 05:48:10 PM PDT 24
Finished Jul 21 05:48:11 PM PDT 24
Peak memory 200452 kb
Host smart-e9f162f9-b812-4859-a684-b2572cb23514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445075853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.445075853
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3779573646
Short name T63
Test name
Test status
Simulation time 939113395 ps
CPU time 3.77 seconds
Started Jul 21 05:39:51 PM PDT 24
Finished Jul 21 05:39:56 PM PDT 24
Peak memory 200416 kb
Host smart-43a7212c-e8e1-45d8-a6bb-c0c6e4acc632
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779573646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3779573646
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2335980580
Short name T38
Test name
Test status
Simulation time 1220376946 ps
CPU time 5.91 seconds
Started Jul 21 05:46:39 PM PDT 24
Finished Jul 21 05:46:45 PM PDT 24
Peak memory 221656 kb
Host smart-c98a83d0-9bac-4008-a810-916c0156fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335980580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2335980580
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2657542648
Short name T2
Test name
Test status
Simulation time 218536580 ps
CPU time 1.41 seconds
Started Jul 21 05:49:02 PM PDT 24
Finished Jul 21 05:49:04 PM PDT 24
Peak memory 200436 kb
Host smart-cbae7850-3b83-43b8-aa9e-f5c187a615e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657542648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2657542648
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3300874027
Short name T562
Test name
Test status
Simulation time 390696620 ps
CPU time 2.82 seconds
Started Jul 21 05:39:39 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 210916 kb
Host smart-7923c718-7967-46e3-aae6-f3a3a0604a43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300874027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3300874027
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2661825309
Short name T36
Test name
Test status
Simulation time 1221997837 ps
CPU time 5.46 seconds
Started Jul 21 05:47:37 PM PDT 24
Finished Jul 21 05:47:43 PM PDT 24
Peak memory 216884 kb
Host smart-e9da6314-c5f0-4e7a-91d3-3bdc91f792bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661825309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2661825309
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.61249529
Short name T118
Test name
Test status
Simulation time 893712767 ps
CPU time 2.77 seconds
Started Jul 21 05:40:02 PM PDT 24
Finished Jul 21 05:40:05 PM PDT 24
Peak memory 200528 kb
Host smart-bcc598d7-299e-40d4-93d7-5465eacebf6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61249529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.61249529
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.442767882
Short name T113
Test name
Test status
Simulation time 77734405 ps
CPU time 1.02 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 200308 kb
Host smart-2a354259-abe5-4692-bc03-67d9aa870e3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442767882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.442767882
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.800144412
Short name T22
Test name
Test status
Simulation time 106374350 ps
CPU time 0.84 seconds
Started Jul 21 05:46:05 PM PDT 24
Finished Jul 21 05:46:06 PM PDT 24
Peak memory 200256 kb
Host smart-d3051f90-4841-43d3-a600-e4b2dcde8a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800144412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.800144412
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1807437283
Short name T82
Test name
Test status
Simulation time 244030034 ps
CPU time 1.05 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:35 PM PDT 24
Peak memory 217464 kb
Host smart-a3bbfd14-839d-4627-9951-e8f025b1055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807437283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1807437283
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.124513371
Short name T552
Test name
Test status
Simulation time 464278870 ps
CPU time 3.19 seconds
Started Jul 21 05:39:37 PM PDT 24
Finished Jul 21 05:39:42 PM PDT 24
Peak memory 208612 kb
Host smart-afef9307-7529-4a75-9a41-260194921114
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124513371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.124513371
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2008984063
Short name T121
Test name
Test status
Simulation time 775661901 ps
CPU time 2.96 seconds
Started Jul 21 05:39:55 PM PDT 24
Finished Jul 21 05:39:59 PM PDT 24
Peak memory 200516 kb
Host smart-f82be31f-34a2-4efa-b1af-cc982d67a8de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008984063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2008984063
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2972271027
Short name T602
Test name
Test status
Simulation time 417490416 ps
CPU time 2.56 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:40 PM PDT 24
Peak memory 200288 kb
Host smart-5deada90-5f1a-4eb5-9639-0127dc701d13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972271027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
972271027
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1254703754
Short name T586
Test name
Test status
Simulation time 803788474 ps
CPU time 4.31 seconds
Started Jul 21 05:39:39 PM PDT 24
Finished Jul 21 05:39:45 PM PDT 24
Peak memory 200328 kb
Host smart-033e1f71-8c05-4223-ad93-b0238e637175
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254703754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
254703754
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1614639749
Short name T614
Test name
Test status
Simulation time 141364852 ps
CPU time 1.06 seconds
Started Jul 21 05:39:37 PM PDT 24
Finished Jul 21 05:39:40 PM PDT 24
Peak memory 200076 kb
Host smart-2bda0bb6-c9c8-4121-8d1b-be6fcf61d5d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614639749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
614639749
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2811599710
Short name T600
Test name
Test status
Simulation time 161407974 ps
CPU time 1.62 seconds
Started Jul 21 05:39:38 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 214036 kb
Host smart-a1b12f4a-eddc-470a-aa1b-09ed4d56e481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811599710 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2811599710
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3707596887
Short name T584
Test name
Test status
Simulation time 68286074 ps
CPU time 0.84 seconds
Started Jul 21 05:39:37 PM PDT 24
Finished Jul 21 05:39:40 PM PDT 24
Peak memory 200316 kb
Host smart-7becb469-c837-420e-997b-53183ef8b49c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707596887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3707596887
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1571413536
Short name T599
Test name
Test status
Simulation time 90443443 ps
CPU time 1.01 seconds
Started Jul 21 05:39:37 PM PDT 24
Finished Jul 21 05:39:39 PM PDT 24
Peak memory 200284 kb
Host smart-29886bd7-b08b-43aa-a128-e0c6d3fb66dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571413536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1571413536
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1429385185
Short name T585
Test name
Test status
Simulation time 504320201 ps
CPU time 1.91 seconds
Started Jul 21 05:39:38 PM PDT 24
Finished Jul 21 05:39:42 PM PDT 24
Peak memory 200384 kb
Host smart-2118a010-90bc-4eaf-a6e3-a308db292f66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429385185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1429385185
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2115292736
Short name T573
Test name
Test status
Simulation time 428872550 ps
CPU time 2.75 seconds
Started Jul 21 05:39:46 PM PDT 24
Finished Jul 21 05:39:50 PM PDT 24
Peak memory 200568 kb
Host smart-afa005e4-f166-46f6-8fb3-fc164712e1d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115292736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
115292736
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1019015702
Short name T616
Test name
Test status
Simulation time 808250130 ps
CPU time 4.41 seconds
Started Jul 21 05:39:40 PM PDT 24
Finished Jul 21 05:39:46 PM PDT 24
Peak memory 200296 kb
Host smart-dfea59b7-0f05-4e88-b2da-aa53c5fd11f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019015702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
019015702
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2603724766
Short name T571
Test name
Test status
Simulation time 102994085 ps
CPU time 0.84 seconds
Started Jul 21 05:39:45 PM PDT 24
Finished Jul 21 05:39:47 PM PDT 24
Peak memory 200360 kb
Host smart-3bd6042a-6e0e-42ee-9b7e-f8298d4a9a8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603724766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
603724766
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1819909095
Short name T544
Test name
Test status
Simulation time 131415710 ps
CPU time 1.28 seconds
Started Jul 21 05:39:43 PM PDT 24
Finished Jul 21 05:39:45 PM PDT 24
Peak memory 208496 kb
Host smart-421f90f5-b160-493d-91ba-ed3dceb10fe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819909095 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1819909095
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3967391408
Short name T553
Test name
Test status
Simulation time 87038720 ps
CPU time 0.89 seconds
Started Jul 21 05:39:38 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 200280 kb
Host smart-ad08b3d7-2dfa-4b82-8fc3-80d73cba74eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967391408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3967391408
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.605673104
Short name T559
Test name
Test status
Simulation time 771321299 ps
CPU time 2.78 seconds
Started Jul 21 05:39:39 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 200428 kb
Host smart-73ca4170-7915-4330-861d-8b79081ef520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605673104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
605673104
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3577467125
Short name T577
Test name
Test status
Simulation time 136240075 ps
CPU time 1.43 seconds
Started Jul 21 05:39:48 PM PDT 24
Finished Jul 21 05:39:50 PM PDT 24
Peak memory 208700 kb
Host smart-810de51f-0948-4712-b851-f3c48b97d13f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577467125 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3577467125
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2124601567
Short name T590
Test name
Test status
Simulation time 84949741 ps
CPU time 0.91 seconds
Started Jul 21 05:39:55 PM PDT 24
Finished Jul 21 05:39:57 PM PDT 24
Peak memory 200180 kb
Host smart-e78223a7-e7dc-469c-8ba9-27c9060b9a91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124601567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2124601567
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3644766523
Short name T64
Test name
Test status
Simulation time 195529188 ps
CPU time 1.5 seconds
Started Jul 21 05:39:49 PM PDT 24
Finished Jul 21 05:39:51 PM PDT 24
Peak memory 200384 kb
Host smart-ffc035fb-dc16-4b48-afab-5582c3a212c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644766523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3644766523
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4052298396
Short name T72
Test name
Test status
Simulation time 117943151 ps
CPU time 0.98 seconds
Started Jul 21 05:39:55 PM PDT 24
Finished Jul 21 05:39:57 PM PDT 24
Peak memory 199984 kb
Host smart-ff3d0b4e-d425-477f-b09a-4b05ea5c296b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052298396 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.4052298396
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.466643347
Short name T568
Test name
Test status
Simulation time 66742498 ps
CPU time 0.84 seconds
Started Jul 21 05:39:51 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 200248 kb
Host smart-d6868d48-9bb5-4b6b-87de-13946cebec4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466643347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.466643347
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2427515679
Short name T566
Test name
Test status
Simulation time 131866267 ps
CPU time 1.09 seconds
Started Jul 21 05:39:50 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 200360 kb
Host smart-b0e51a77-1df7-43e0-a4a6-fb37091fbc60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427515679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2427515679
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.669064382
Short name T563
Test name
Test status
Simulation time 215991862 ps
CPU time 3.09 seconds
Started Jul 21 05:39:55 PM PDT 24
Finished Jul 21 05:39:59 PM PDT 24
Peak memory 208284 kb
Host smart-d86a14d8-0ab6-44d3-8f94-6ab6a014c54a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669064382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.669064382
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3813703691
Short name T618
Test name
Test status
Simulation time 473534538 ps
CPU time 1.99 seconds
Started Jul 21 05:39:52 PM PDT 24
Finished Jul 21 05:39:54 PM PDT 24
Peak memory 200428 kb
Host smart-1797bcd2-75c4-4ae2-b418-624acbe92911
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813703691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3813703691
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1995116425
Short name T597
Test name
Test status
Simulation time 189035779 ps
CPU time 2 seconds
Started Jul 21 05:39:54 PM PDT 24
Finished Jul 21 05:39:57 PM PDT 24
Peak memory 208744 kb
Host smart-dc0b0bbd-65d0-4236-8a8e-a5d4587c4d53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995116425 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1995116425
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.178799703
Short name T112
Test name
Test status
Simulation time 64286669 ps
CPU time 0.78 seconds
Started Jul 21 05:39:55 PM PDT 24
Finished Jul 21 05:39:57 PM PDT 24
Peak memory 200264 kb
Host smart-5b22b3a4-7d22-41ee-8682-ee99aab15354
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178799703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.178799703
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.852953983
Short name T589
Test name
Test status
Simulation time 245530298 ps
CPU time 1.7 seconds
Started Jul 21 05:39:56 PM PDT 24
Finished Jul 21 05:40:00 PM PDT 24
Peak memory 200464 kb
Host smart-7661dbe6-d44b-44c7-9eaa-04e9eca8c582
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852953983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.852953983
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2759788705
Short name T67
Test name
Test status
Simulation time 140036784 ps
CPU time 2.31 seconds
Started Jul 21 05:39:57 PM PDT 24
Finished Jul 21 05:40:01 PM PDT 24
Peak memory 212204 kb
Host smart-8b2bb9fa-995e-4eda-92e4-3ad771d9d56a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759788705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2759788705
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.257034186
Short name T596
Test name
Test status
Simulation time 459085723 ps
CPU time 2.02 seconds
Started Jul 21 05:39:56 PM PDT 24
Finished Jul 21 05:39:59 PM PDT 24
Peak memory 200520 kb
Host smart-dd22e974-a7db-4fbe-a66a-e04c50f9e198
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257034186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.257034186
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2938345082
Short name T556
Test name
Test status
Simulation time 186533494 ps
CPU time 1.93 seconds
Started Jul 21 05:39:57 PM PDT 24
Finished Jul 21 05:40:01 PM PDT 24
Peak memory 208724 kb
Host smart-a127b442-60de-4bd5-967f-173ef0758891
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938345082 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2938345082
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.605151689
Short name T607
Test name
Test status
Simulation time 83274911 ps
CPU time 0.98 seconds
Started Jul 21 05:39:57 PM PDT 24
Finished Jul 21 05:39:59 PM PDT 24
Peak memory 200260 kb
Host smart-c88a3ca4-9568-477f-ae0c-330261722867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605151689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.605151689
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2378287189
Short name T550
Test name
Test status
Simulation time 121897751 ps
CPU time 1.2 seconds
Started Jul 21 05:39:59 PM PDT 24
Finished Jul 21 05:40:00 PM PDT 24
Peak memory 200412 kb
Host smart-a55dc900-8ad8-4b9d-96f3-05b9fc07d249
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378287189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2378287189
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2106979104
Short name T94
Test name
Test status
Simulation time 295457607 ps
CPU time 2.19 seconds
Started Jul 21 05:39:54 PM PDT 24
Finished Jul 21 05:39:57 PM PDT 24
Peak memory 211068 kb
Host smart-3eafd12e-b2a2-4866-9ce7-2bfda402ddb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106979104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2106979104
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.724053265
Short name T92
Test name
Test status
Simulation time 171689716 ps
CPU time 1.33 seconds
Started Jul 21 05:39:58 PM PDT 24
Finished Jul 21 05:40:01 PM PDT 24
Peak memory 208520 kb
Host smart-4add5129-0c7f-4dd5-bcba-4f7a9836a984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724053265 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.724053265
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3256594242
Short name T570
Test name
Test status
Simulation time 79247595 ps
CPU time 0.9 seconds
Started Jul 21 05:39:57 PM PDT 24
Finished Jul 21 05:39:59 PM PDT 24
Peak memory 200148 kb
Host smart-6187d61e-2ca3-47c8-9ab6-d81772da7c4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256594242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3256594242
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1481130985
Short name T611
Test name
Test status
Simulation time 73147627 ps
CPU time 0.92 seconds
Started Jul 21 05:39:56 PM PDT 24
Finished Jul 21 05:39:58 PM PDT 24
Peak memory 200348 kb
Host smart-b5cf2188-8bc6-4107-ac51-3325938f94dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481130985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1481130985
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2113107637
Short name T115
Test name
Test status
Simulation time 103858772 ps
CPU time 1.4 seconds
Started Jul 21 05:39:53 PM PDT 24
Finished Jul 21 05:39:55 PM PDT 24
Peak memory 200376 kb
Host smart-c8fcba28-8b3b-42fb-a32a-e68465166d27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113107637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2113107637
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1628277970
Short name T95
Test name
Test status
Simulation time 480332910 ps
CPU time 2.11 seconds
Started Jul 21 05:39:54 PM PDT 24
Finished Jul 21 05:39:56 PM PDT 24
Peak memory 200496 kb
Host smart-5b4e8ce2-7475-41f7-982a-7ac0bfcd7335
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628277970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1628277970
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.632185922
Short name T561
Test name
Test status
Simulation time 217076047 ps
CPU time 1.34 seconds
Started Jul 21 05:39:55 PM PDT 24
Finished Jul 21 05:39:57 PM PDT 24
Peak memory 208396 kb
Host smart-e9145843-fc84-4c0b-9b87-fd6535ea50b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632185922 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.632185922
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3485765669
Short name T593
Test name
Test status
Simulation time 55151178 ps
CPU time 0.77 seconds
Started Jul 21 05:39:55 PM PDT 24
Finished Jul 21 05:39:56 PM PDT 24
Peak memory 199980 kb
Host smart-5f6904fe-428e-4165-af07-499053777c85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485765669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3485765669
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1663809285
Short name T554
Test name
Test status
Simulation time 165582859 ps
CPU time 1.21 seconds
Started Jul 21 05:39:57 PM PDT 24
Finished Jul 21 05:39:59 PM PDT 24
Peak memory 200324 kb
Host smart-2daef4f2-b703-49ae-b3c9-18553705b7e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663809285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1663809285
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3072392470
Short name T574
Test name
Test status
Simulation time 301816947 ps
CPU time 2.36 seconds
Started Jul 21 05:39:54 PM PDT 24
Finished Jul 21 05:39:56 PM PDT 24
Peak memory 208544 kb
Host smart-bc81e229-8822-4386-867d-28ad1be7ea33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072392470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3072392470
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3209400474
Short name T605
Test name
Test status
Simulation time 492402128 ps
CPU time 2.04 seconds
Started Jul 21 05:39:57 PM PDT 24
Finished Jul 21 05:40:00 PM PDT 24
Peak memory 200528 kb
Host smart-5add1b0c-aa37-42a5-8893-1f5b4cf407ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209400474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3209400474
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2532134021
Short name T541
Test name
Test status
Simulation time 192954556 ps
CPU time 1.27 seconds
Started Jul 21 05:40:04 PM PDT 24
Finished Jul 21 05:40:06 PM PDT 24
Peak memory 208572 kb
Host smart-22d000b6-6834-4c4e-8c9d-63a738071140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532134021 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2532134021
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2352361121
Short name T567
Test name
Test status
Simulation time 57198725 ps
CPU time 0.73 seconds
Started Jul 21 05:39:56 PM PDT 24
Finished Jul 21 05:39:59 PM PDT 24
Peak memory 200160 kb
Host smart-9dede623-2927-4e6b-906f-6f188967bb69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352361121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2352361121
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2736398514
Short name T551
Test name
Test status
Simulation time 238946099 ps
CPU time 1.53 seconds
Started Jul 21 05:40:05 PM PDT 24
Finished Jul 21 05:40:07 PM PDT 24
Peak memory 200496 kb
Host smart-8c94bc76-02a7-4ab4-b6cf-6deb1d8cebb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736398514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2736398514
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.745030459
Short name T620
Test name
Test status
Simulation time 481656977 ps
CPU time 3.35 seconds
Started Jul 21 05:39:57 PM PDT 24
Finished Jul 21 05:40:02 PM PDT 24
Peak memory 211716 kb
Host smart-06d56181-9332-4198-ad31-6dddb446d36b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745030459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.745030459
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.660566798
Short name T548
Test name
Test status
Simulation time 957042732 ps
CPU time 3 seconds
Started Jul 21 05:39:54 PM PDT 24
Finished Jul 21 05:39:57 PM PDT 24
Peak memory 200512 kb
Host smart-175dbb31-2b83-4cda-9f5a-56119c7dcbd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660566798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.660566798
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3057869483
Short name T615
Test name
Test status
Simulation time 126283678 ps
CPU time 1.1 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:40:13 PM PDT 24
Peak memory 200160 kb
Host smart-66826100-6d13-488c-9424-644b23f10e44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057869483 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3057869483
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2700360426
Short name T545
Test name
Test status
Simulation time 82078651 ps
CPU time 0.9 seconds
Started Jul 21 05:40:06 PM PDT 24
Finished Jul 21 05:40:07 PM PDT 24
Peak memory 200248 kb
Host smart-5fc29037-7039-447a-a055-db813d9c4e93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700360426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2700360426
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3728214393
Short name T549
Test name
Test status
Simulation time 242859347 ps
CPU time 1.57 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:40:13 PM PDT 24
Peak memory 200488 kb
Host smart-57eb6398-3ca4-4334-97fc-03e3db58bc91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728214393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3728214393
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.946521389
Short name T68
Test name
Test status
Simulation time 280034980 ps
CPU time 2.02 seconds
Started Jul 21 05:40:04 PM PDT 24
Finished Jul 21 05:40:07 PM PDT 24
Peak memory 208648 kb
Host smart-3e38d5b4-9995-4ba6-bea6-76d14cc054b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946521389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.946521389
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1091068187
Short name T131
Test name
Test status
Simulation time 430076263 ps
CPU time 1.77 seconds
Started Jul 21 05:40:01 PM PDT 24
Finished Jul 21 05:40:04 PM PDT 24
Peak memory 200472 kb
Host smart-bae02412-bf76-40d0-8320-a1c1dc3b7155
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091068187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1091068187
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2649843037
Short name T572
Test name
Test status
Simulation time 163949261 ps
CPU time 1.21 seconds
Started Jul 21 05:40:02 PM PDT 24
Finished Jul 21 05:40:04 PM PDT 24
Peak memory 200344 kb
Host smart-c2e7c5ce-2c1b-4a5d-b455-b030fb08b6f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649843037 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2649843037
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4020337304
Short name T606
Test name
Test status
Simulation time 56582736 ps
CPU time 0.85 seconds
Started Jul 21 05:40:01 PM PDT 24
Finished Jul 21 05:40:02 PM PDT 24
Peak memory 200236 kb
Host smart-ebcbdafd-382f-4012-b9fd-eee3a9f1a5a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020337304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4020337304
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1642954341
Short name T547
Test name
Test status
Simulation time 141949949 ps
CPU time 1.24 seconds
Started Jul 21 05:40:06 PM PDT 24
Finished Jul 21 05:40:07 PM PDT 24
Peak memory 200244 kb
Host smart-fd91815d-bc7b-4843-ac5d-43220e930322
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642954341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1642954341
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4129718279
Short name T576
Test name
Test status
Simulation time 188032908 ps
CPU time 2.61 seconds
Started Jul 21 05:40:03 PM PDT 24
Finished Jul 21 05:40:06 PM PDT 24
Peak memory 212264 kb
Host smart-c808e78b-26f4-42a4-8ebb-ddfa5ce2051b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129718279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.4129718279
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2958453067
Short name T582
Test name
Test status
Simulation time 129120686 ps
CPU time 1.13 seconds
Started Jul 21 05:40:01 PM PDT 24
Finished Jul 21 05:40:03 PM PDT 24
Peak memory 200388 kb
Host smart-0fd3de72-a1fd-44c7-bf24-cabf2e43ae8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958453067 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2958453067
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2481688284
Short name T569
Test name
Test status
Simulation time 66105924 ps
CPU time 0.81 seconds
Started Jul 21 05:40:04 PM PDT 24
Finished Jul 21 05:40:06 PM PDT 24
Peak memory 200244 kb
Host smart-3860f4f3-5773-4990-ad6f-4dcd66bde585
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481688284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2481688284
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.490939408
Short name T110
Test name
Test status
Simulation time 261833177 ps
CPU time 1.65 seconds
Started Jul 21 05:40:03 PM PDT 24
Finished Jul 21 05:40:05 PM PDT 24
Peak memory 200516 kb
Host smart-4f37bc34-580f-456a-a47e-a6c84908a9bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490939408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.490939408
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.35104128
Short name T603
Test name
Test status
Simulation time 130451228 ps
CPU time 1.8 seconds
Started Jul 21 05:40:02 PM PDT 24
Finished Jul 21 05:40:04 PM PDT 24
Peak memory 210940 kb
Host smart-d503d2a0-f174-4c61-b7d3-e23a613b007c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35104128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.35104128
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2434521743
Short name T117
Test name
Test status
Simulation time 776494211 ps
CPU time 2.98 seconds
Started Jul 21 05:40:02 PM PDT 24
Finished Jul 21 05:40:06 PM PDT 24
Peak memory 200320 kb
Host smart-c418a2c5-4890-4869-902b-48a82b2ca66d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434521743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2434521743
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3810488711
Short name T565
Test name
Test status
Simulation time 340957593 ps
CPU time 2.39 seconds
Started Jul 21 05:39:43 PM PDT 24
Finished Jul 21 05:39:47 PM PDT 24
Peak memory 200460 kb
Host smart-3a0f87ac-b9e8-474d-8e18-8a85b1efe71a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810488711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
810488711
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2879887426
Short name T575
Test name
Test status
Simulation time 483496069 ps
CPU time 5.74 seconds
Started Jul 21 05:39:42 PM PDT 24
Finished Jul 21 05:39:50 PM PDT 24
Peak memory 200388 kb
Host smart-81f7a595-c3df-465f-bb7e-390a3ead0643
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879887426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
879887426
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.889418127
Short name T612
Test name
Test status
Simulation time 94907999 ps
CPU time 0.83 seconds
Started Jul 21 05:39:42 PM PDT 24
Finished Jul 21 05:39:44 PM PDT 24
Peak memory 200044 kb
Host smart-e780d0d4-fb5d-4301-b771-b2fa772df457
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889418127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.889418127
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1089451040
Short name T93
Test name
Test status
Simulation time 126283846 ps
CPU time 1.48 seconds
Started Jul 21 05:39:48 PM PDT 24
Finished Jul 21 05:39:51 PM PDT 24
Peak memory 208992 kb
Host smart-f2b25b69-6b9e-4541-8a7f-ce84b55c28de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089451040 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1089451040
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3893296765
Short name T98
Test name
Test status
Simulation time 60610591 ps
CPU time 0.75 seconds
Started Jul 21 05:39:44 PM PDT 24
Finished Jul 21 05:39:46 PM PDT 24
Peak memory 200080 kb
Host smart-49f4b72c-3fe2-4627-85ea-f94d43d71847
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893296765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3893296765
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1266047430
Short name T107
Test name
Test status
Simulation time 234701165 ps
CPU time 1.44 seconds
Started Jul 21 05:39:45 PM PDT 24
Finished Jul 21 05:39:48 PM PDT 24
Peak memory 208628 kb
Host smart-ca0f8fd1-27fc-47e5-a86a-9706c408bf93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266047430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1266047430
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.442412249
Short name T546
Test name
Test status
Simulation time 353957905 ps
CPU time 2.67 seconds
Started Jul 21 05:39:40 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 208588 kb
Host smart-3460ab8e-3de1-464c-adce-5a07a90aeefe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442412249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.442412249
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1447943616
Short name T122
Test name
Test status
Simulation time 872487343 ps
CPU time 3.02 seconds
Started Jul 21 05:39:42 PM PDT 24
Finished Jul 21 05:39:45 PM PDT 24
Peak memory 200404 kb
Host smart-7477a318-0aa8-4a6c-9957-6802558751a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447943616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1447943616
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3925515975
Short name T595
Test name
Test status
Simulation time 106077396 ps
CPU time 1.34 seconds
Started Jul 21 05:39:42 PM PDT 24
Finished Jul 21 05:39:45 PM PDT 24
Peak memory 200344 kb
Host smart-1a658f18-2343-426f-94d4-85782453905d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925515975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
925515975
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1617555219
Short name T604
Test name
Test status
Simulation time 478786747 ps
CPU time 5.65 seconds
Started Jul 21 05:39:42 PM PDT 24
Finished Jul 21 05:39:49 PM PDT 24
Peak memory 200264 kb
Host smart-eb183c1d-c8da-4ddb-85c3-e2ff05536399
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617555219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
617555219
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1171416741
Short name T540
Test name
Test status
Simulation time 94734995 ps
CPU time 0.87 seconds
Started Jul 21 05:39:45 PM PDT 24
Finished Jul 21 05:39:47 PM PDT 24
Peak memory 200256 kb
Host smart-09206f72-b443-4e26-8823-f35d09f9fa13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171416741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
171416741
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1369144307
Short name T558
Test name
Test status
Simulation time 180243825 ps
CPU time 1.19 seconds
Started Jul 21 05:39:41 PM PDT 24
Finished Jul 21 05:39:44 PM PDT 24
Peak memory 208604 kb
Host smart-4e59832f-7e04-4ac3-a24f-8e9c43c6f339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369144307 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1369144307
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4173865934
Short name T557
Test name
Test status
Simulation time 65707816 ps
CPU time 0.82 seconds
Started Jul 21 05:39:43 PM PDT 24
Finished Jul 21 05:39:45 PM PDT 24
Peak memory 200192 kb
Host smart-aa0784cc-58c0-4a60-aa62-777aa9afaa97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173865934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4173865934
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3647332155
Short name T581
Test name
Test status
Simulation time 77156070 ps
CPU time 0.96 seconds
Started Jul 21 05:39:41 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 200344 kb
Host smart-04884800-3a10-422d-87d4-b584aff6ef9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647332155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3647332155
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4148677918
Short name T116
Test name
Test status
Simulation time 91400525 ps
CPU time 1.43 seconds
Started Jul 21 05:39:41 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 211360 kb
Host smart-2c020375-daaa-4735-91a1-716254140e68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148677918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.4148677918
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3195834855
Short name T608
Test name
Test status
Simulation time 362778282 ps
CPU time 2.44 seconds
Started Jul 21 05:39:45 PM PDT 24
Finished Jul 21 05:39:49 PM PDT 24
Peak memory 200424 kb
Host smart-b6b6d3a2-fe38-41b7-9612-0d215852fe2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195834855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
195834855
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2940189003
Short name T598
Test name
Test status
Simulation time 806738730 ps
CPU time 4.46 seconds
Started Jul 21 05:39:42 PM PDT 24
Finished Jul 21 05:39:48 PM PDT 24
Peak memory 200384 kb
Host smart-fac42ab2-7d7f-47a0-92d1-3fce72f387bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940189003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
940189003
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1003047408
Short name T578
Test name
Test status
Simulation time 107249230 ps
CPU time 0.85 seconds
Started Jul 21 05:39:41 PM PDT 24
Finished Jul 21 05:39:42 PM PDT 24
Peak memory 200184 kb
Host smart-2ecd07db-13bf-4252-aea8-8587226f7388
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003047408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
003047408
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3860222209
Short name T613
Test name
Test status
Simulation time 201540881 ps
CPU time 1.45 seconds
Started Jul 21 05:39:41 PM PDT 24
Finished Jul 21 05:39:44 PM PDT 24
Peak memory 208480 kb
Host smart-3b69fc76-37fe-43aa-9acb-11b95bb2b2eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860222209 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3860222209
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2208478713
Short name T543
Test name
Test status
Simulation time 56940340 ps
CPU time 0.8 seconds
Started Jul 21 05:39:53 PM PDT 24
Finished Jul 21 05:39:54 PM PDT 24
Peak memory 200028 kb
Host smart-705483c8-2c74-4e86-8cef-1f06fb9a92f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208478713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2208478713
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3788579998
Short name T592
Test name
Test status
Simulation time 249701287 ps
CPU time 1.59 seconds
Started Jul 21 05:39:46 PM PDT 24
Finished Jul 21 05:39:49 PM PDT 24
Peak memory 200496 kb
Host smart-3eb5d099-c256-4cb4-a92e-89b0a1701eff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788579998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3788579998
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2513593362
Short name T587
Test name
Test status
Simulation time 360779540 ps
CPU time 2.41 seconds
Started Jul 21 05:39:47 PM PDT 24
Finished Jul 21 05:39:50 PM PDT 24
Peak memory 216612 kb
Host smart-3195f056-1bd1-4719-a038-04b104ea8fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513593362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2513593362
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.418659978
Short name T132
Test name
Test status
Simulation time 1032626558 ps
CPU time 3.29 seconds
Started Jul 21 05:39:46 PM PDT 24
Finished Jul 21 05:39:50 PM PDT 24
Peak memory 200548 kb
Host smart-41dad888-8d68-45e7-b2c8-90a9ba35fc11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418659978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
418659978
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.295704144
Short name T62
Test name
Test status
Simulation time 124998044 ps
CPU time 0.97 seconds
Started Jul 21 05:39:49 PM PDT 24
Finished Jul 21 05:39:50 PM PDT 24
Peak memory 200356 kb
Host smart-124dd24c-654d-4ff8-bb1e-3f9ae04d2af3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295704144 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.295704144
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.422742701
Short name T114
Test name
Test status
Simulation time 67074689 ps
CPU time 0.81 seconds
Started Jul 21 05:39:41 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 200276 kb
Host smart-391d3506-0382-4941-a5bc-edf87a38b42c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422742701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.422742701
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.85456330
Short name T111
Test name
Test status
Simulation time 141998594 ps
CPU time 1.17 seconds
Started Jul 21 05:39:45 PM PDT 24
Finished Jul 21 05:39:47 PM PDT 24
Peak memory 200260 kb
Host smart-f5434d6a-79ca-4456-81ba-daca4856cda9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85456330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same
_csr_outstanding.85456330
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2717811203
Short name T580
Test name
Test status
Simulation time 215439788 ps
CPU time 1.75 seconds
Started Jul 21 05:39:43 PM PDT 24
Finished Jul 21 05:39:46 PM PDT 24
Peak memory 208564 kb
Host smart-590f8949-e978-4b55-8467-66cc8366d173
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717811203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2717811203
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2157374306
Short name T120
Test name
Test status
Simulation time 504694944 ps
CPU time 2.21 seconds
Started Jul 21 05:39:41 PM PDT 24
Finished Jul 21 05:39:44 PM PDT 24
Peak memory 200488 kb
Host smart-89b7c436-0ba7-4366-b030-58f531161ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157374306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2157374306
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1502498843
Short name T539
Test name
Test status
Simulation time 209283683 ps
CPU time 1.41 seconds
Started Jul 21 05:39:55 PM PDT 24
Finished Jul 21 05:39:57 PM PDT 24
Peak memory 200300 kb
Host smart-0bcbd195-68cb-4520-ac87-01e9ffa0cbd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502498843 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1502498843
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3301785696
Short name T109
Test name
Test status
Simulation time 81903262 ps
CPU time 0.87 seconds
Started Jul 21 05:39:49 PM PDT 24
Finished Jul 21 05:39:50 PM PDT 24
Peak memory 200176 kb
Host smart-3f20b27e-e9da-4289-9d77-6d18ce014734
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301785696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3301785696
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3510542101
Short name T61
Test name
Test status
Simulation time 153484032 ps
CPU time 1.26 seconds
Started Jul 21 05:39:56 PM PDT 24
Finished Jul 21 05:39:58 PM PDT 24
Peak memory 200244 kb
Host smart-50bb16e5-ed09-42d6-aa95-3a16ac381b7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510542101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3510542101
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2003561845
Short name T594
Test name
Test status
Simulation time 185284421 ps
CPU time 2.53 seconds
Started Jul 21 05:39:51 PM PDT 24
Finished Jul 21 05:39:54 PM PDT 24
Peak memory 208576 kb
Host smart-3d61f932-a6e8-4db0-ad3f-16b5d787353d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003561845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2003561845
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1777728600
Short name T119
Test name
Test status
Simulation time 774462413 ps
CPU time 2.89 seconds
Started Jul 21 05:39:55 PM PDT 24
Finished Jul 21 05:39:59 PM PDT 24
Peak memory 200428 kb
Host smart-f9f1b154-f590-4e21-8e69-e9efdc1d6d11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777728600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1777728600
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1616726138
Short name T579
Test name
Test status
Simulation time 124652314 ps
CPU time 1.06 seconds
Started Jul 21 05:39:51 PM PDT 24
Finished Jul 21 05:39:53 PM PDT 24
Peak memory 208660 kb
Host smart-e8240bed-d21a-47e8-a3a0-234a628222ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616726138 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1616726138
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.589321464
Short name T610
Test name
Test status
Simulation time 64663436 ps
CPU time 0.78 seconds
Started Jul 21 05:39:47 PM PDT 24
Finished Jul 21 05:39:48 PM PDT 24
Peak memory 200276 kb
Host smart-7452102f-de85-49d7-a53c-10f2b05af329
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589321464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.589321464
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2512876313
Short name T617
Test name
Test status
Simulation time 76486157 ps
CPU time 1.01 seconds
Started Jul 21 05:39:50 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 200228 kb
Host smart-273b4e28-73d6-4c32-9ea7-7eea77f2c92b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512876313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2512876313
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2085082106
Short name T601
Test name
Test status
Simulation time 537406728 ps
CPU time 3.25 seconds
Started Jul 21 05:39:56 PM PDT 24
Finished Jul 21 05:40:01 PM PDT 24
Peak memory 208504 kb
Host smart-401f7833-4cdb-4cf8-b1aa-b48e01cfe675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085082106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2085082106
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2142541895
Short name T564
Test name
Test status
Simulation time 484872619 ps
CPU time 2.08 seconds
Started Jul 21 05:39:48 PM PDT 24
Finished Jul 21 05:39:51 PM PDT 24
Peak memory 200376 kb
Host smart-79920e30-4d45-4be3-b00c-b11a4294fe59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142541895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2142541895
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3579752056
Short name T91
Test name
Test status
Simulation time 135570830 ps
CPU time 1.09 seconds
Started Jul 21 05:39:52 PM PDT 24
Finished Jul 21 05:39:54 PM PDT 24
Peak memory 200320 kb
Host smart-21977988-cbd2-44c7-bea5-af149590de36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579752056 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3579752056
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4197292087
Short name T619
Test name
Test status
Simulation time 61981217 ps
CPU time 0.75 seconds
Started Jul 21 05:39:50 PM PDT 24
Finished Jul 21 05:39:51 PM PDT 24
Peak memory 200204 kb
Host smart-5a6e2f9d-2258-40b2-9012-b9338ef2631c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197292087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4197292087
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3874976084
Short name T555
Test name
Test status
Simulation time 120540626 ps
CPU time 1.09 seconds
Started Jul 21 05:39:50 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 200356 kb
Host smart-1d0480a0-6fb3-4bf5-aba6-32d624854865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874976084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3874976084
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.537791612
Short name T588
Test name
Test status
Simulation time 178665762 ps
CPU time 2.44 seconds
Started Jul 21 05:40:24 PM PDT 24
Finished Jul 21 05:40:27 PM PDT 24
Peak memory 208556 kb
Host smart-1442a74d-2087-4229-b9fb-96353c2c86c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537791612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.537791612
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3689148033
Short name T583
Test name
Test status
Simulation time 478374059 ps
CPU time 1.84 seconds
Started Jul 21 05:39:56 PM PDT 24
Finished Jul 21 05:40:00 PM PDT 24
Peak memory 200392 kb
Host smart-5e359f94-990b-4c12-b46e-65b472ab7fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689148033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3689148033
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1797097371
Short name T609
Test name
Test status
Simulation time 161154636 ps
CPU time 1.61 seconds
Started Jul 21 05:39:50 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 208764 kb
Host smart-c4a77732-bea9-44ce-9241-8cb43e97390e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797097371 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1797097371
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4274897266
Short name T108
Test name
Test status
Simulation time 53943601 ps
CPU time 0.77 seconds
Started Jul 21 05:39:51 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 200260 kb
Host smart-783ed3e7-98cd-4504-a9fd-ee6db08685ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274897266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4274897266
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2180912314
Short name T560
Test name
Test status
Simulation time 82248035 ps
CPU time 1.04 seconds
Started Jul 21 05:39:50 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 200324 kb
Host smart-e19742e5-2572-42a2-aca2-09282cd91d03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180912314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2180912314
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.123545830
Short name T542
Test name
Test status
Simulation time 235240305 ps
CPU time 1.9 seconds
Started Jul 21 05:39:49 PM PDT 24
Finished Jul 21 05:39:51 PM PDT 24
Peak memory 208596 kb
Host smart-82c9537e-11a8-4928-8655-0e1140e47bab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123545830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.123545830
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2383045971
Short name T591
Test name
Test status
Simulation time 833403967 ps
CPU time 3.02 seconds
Started Jul 21 05:39:52 PM PDT 24
Finished Jul 21 05:39:56 PM PDT 24
Peak memory 200448 kb
Host smart-2f0ebbfd-ee4a-4e96-8395-51f5150d1e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383045971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2383045971
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.294944031
Short name T173
Test name
Test status
Simulation time 82107042 ps
CPU time 0.85 seconds
Started Jul 21 05:46:15 PM PDT 24
Finished Jul 21 05:46:16 PM PDT 24
Peak memory 200156 kb
Host smart-b64caefd-29e4-48f5-b52b-78587171f773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294944031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.294944031
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1053398954
Short name T471
Test name
Test status
Simulation time 1217906307 ps
CPU time 5.66 seconds
Started Jul 21 05:46:16 PM PDT 24
Finished Jul 21 05:46:22 PM PDT 24
Peak memory 217616 kb
Host smart-cf5c9906-915d-4bd4-baff-7701dc1d7a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053398954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1053398954
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.590369525
Short name T497
Test name
Test status
Simulation time 243624934 ps
CPU time 1.05 seconds
Started Jul 21 05:46:14 PM PDT 24
Finished Jul 21 05:46:16 PM PDT 24
Peak memory 217452 kb
Host smart-850bb6ea-def1-4f02-a115-67e622b69f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590369525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.590369525
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1861183677
Short name T301
Test name
Test status
Simulation time 800325438 ps
CPU time 4.5 seconds
Started Jul 21 05:46:10 PM PDT 24
Finished Jul 21 05:46:15 PM PDT 24
Peak memory 200708 kb
Host smart-bb2c4464-4fa2-4003-828e-e95ebc14478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861183677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1861183677
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3580504904
Short name T298
Test name
Test status
Simulation time 142907898 ps
CPU time 1.04 seconds
Started Jul 21 05:46:10 PM PDT 24
Finished Jul 21 05:46:11 PM PDT 24
Peak memory 200340 kb
Host smart-5703ed78-fe72-4fa8-a27c-1349a01673b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580504904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3580504904
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1702028086
Short name T196
Test name
Test status
Simulation time 249575432 ps
CPU time 1.48 seconds
Started Jul 21 05:46:09 PM PDT 24
Finished Jul 21 05:46:11 PM PDT 24
Peak memory 200568 kb
Host smart-bd1b7bec-5d80-44a5-9293-97fc860aa928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702028086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1702028086
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1329214696
Short name T413
Test name
Test status
Simulation time 2313919878 ps
CPU time 9.64 seconds
Started Jul 21 05:46:15 PM PDT 24
Finished Jul 21 05:46:25 PM PDT 24
Peak memory 200728 kb
Host smart-a0411343-886a-4562-94a5-57adfdbf527b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329214696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1329214696
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1921959581
Short name T247
Test name
Test status
Simulation time 153154833 ps
CPU time 1.88 seconds
Started Jul 21 05:46:10 PM PDT 24
Finished Jul 21 05:46:12 PM PDT 24
Peak memory 200376 kb
Host smart-6feb6a6b-177b-4703-8280-c3c19c26882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921959581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1921959581
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.4097511355
Short name T475
Test name
Test status
Simulation time 118609518 ps
CPU time 0.93 seconds
Started Jul 21 05:46:10 PM PDT 24
Finished Jul 21 05:46:11 PM PDT 24
Peak memory 200440 kb
Host smart-e412be05-5945-4426-a5c9-5b06a5a6e04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097511355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.4097511355
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3932333009
Short name T163
Test name
Test status
Simulation time 60274920 ps
CPU time 0.73 seconds
Started Jul 21 05:46:30 PM PDT 24
Finished Jul 21 05:46:31 PM PDT 24
Peak memory 200260 kb
Host smart-3a68fc86-7b26-4afb-b0b7-0195acbbc487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932333009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3932333009
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1150906154
Short name T506
Test name
Test status
Simulation time 1235171600 ps
CPU time 5.8 seconds
Started Jul 21 05:46:25 PM PDT 24
Finished Jul 21 05:46:31 PM PDT 24
Peak memory 217704 kb
Host smart-d3c5eda0-4dd3-4fa2-a12b-0aa7166768a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150906154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1150906154
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2103494897
Short name T232
Test name
Test status
Simulation time 245231437 ps
CPU time 1.06 seconds
Started Jul 21 05:46:23 PM PDT 24
Finished Jul 21 05:46:24 PM PDT 24
Peak memory 217452 kb
Host smart-71703961-24f0-4cda-b13d-cadb75488b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103494897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2103494897
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3381657676
Short name T456
Test name
Test status
Simulation time 235441036 ps
CPU time 0.9 seconds
Started Jul 21 05:46:24 PM PDT 24
Finished Jul 21 05:46:25 PM PDT 24
Peak memory 200200 kb
Host smart-e6444c35-7deb-49dc-acf2-ccf263308cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381657676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3381657676
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.81089053
Short name T49
Test name
Test status
Simulation time 1450784897 ps
CPU time 5.83 seconds
Started Jul 21 05:46:23 PM PDT 24
Finished Jul 21 05:46:29 PM PDT 24
Peak memory 200672 kb
Host smart-4e3dbcbb-fe1c-4ad5-8ec4-09d79f6d7e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81089053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.81089053
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2753834551
Short name T70
Test name
Test status
Simulation time 17720342691 ps
CPU time 26.08 seconds
Started Jul 21 05:46:33 PM PDT 24
Finished Jul 21 05:46:59 PM PDT 24
Peak memory 217628 kb
Host smart-768c6694-9382-412a-9a84-ce43af37d5b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753834551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2753834551
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3788449695
Short name T450
Test name
Test status
Simulation time 94955512 ps
CPU time 0.99 seconds
Started Jul 21 05:46:23 PM PDT 24
Finished Jul 21 05:46:24 PM PDT 24
Peak memory 200356 kb
Host smart-7fa1b1a3-a390-4bad-916a-2252d626ad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788449695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3788449695
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.4224442643
Short name T431
Test name
Test status
Simulation time 231814991 ps
CPU time 1.43 seconds
Started Jul 21 05:46:17 PM PDT 24
Finished Jul 21 05:46:19 PM PDT 24
Peak memory 200648 kb
Host smart-b85061cb-9a5d-492c-b362-086fa78eb052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224442643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4224442643
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3205158111
Short name T255
Test name
Test status
Simulation time 9682315247 ps
CPU time 33.05 seconds
Started Jul 21 05:46:25 PM PDT 24
Finished Jul 21 05:46:58 PM PDT 24
Peak memory 200776 kb
Host smart-76bd7b43-38cf-4c03-8f3e-fe7e7adffac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205158111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3205158111
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3249754076
Short name T502
Test name
Test status
Simulation time 325367399 ps
CPU time 2.14 seconds
Started Jul 21 05:46:23 PM PDT 24
Finished Jul 21 05:46:25 PM PDT 24
Peak memory 200512 kb
Host smart-3f0c769b-0d9b-43f7-a363-b569dfeac1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249754076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3249754076
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2573986011
Short name T418
Test name
Test status
Simulation time 92124778 ps
CPU time 0.92 seconds
Started Jul 21 05:46:22 PM PDT 24
Finished Jul 21 05:46:23 PM PDT 24
Peak memory 200460 kb
Host smart-75c200fd-19fe-46bd-8f21-e6ae3db8a9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573986011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2573986011
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1643101645
Short name T145
Test name
Test status
Simulation time 82605180 ps
CPU time 0.89 seconds
Started Jul 21 05:47:20 PM PDT 24
Finished Jul 21 05:47:22 PM PDT 24
Peak memory 200268 kb
Host smart-bbf8436b-2e62-42e1-89be-d8ca70383cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643101645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1643101645
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2047084665
Short name T337
Test name
Test status
Simulation time 1880134738 ps
CPU time 7.47 seconds
Started Jul 21 05:47:15 PM PDT 24
Finished Jul 21 05:47:23 PM PDT 24
Peak memory 217564 kb
Host smart-810d2de3-c57b-4203-a76f-5f9dd9631cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047084665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2047084665
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.59527152
Short name T299
Test name
Test status
Simulation time 243615359 ps
CPU time 1.04 seconds
Started Jul 21 05:47:13 PM PDT 24
Finished Jul 21 05:47:15 PM PDT 24
Peak memory 217468 kb
Host smart-b20dd6a2-d782-4152-8c8c-7553535a8c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59527152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.59527152
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4029069262
Short name T216
Test name
Test status
Simulation time 155458172 ps
CPU time 0.84 seconds
Started Jul 21 05:47:14 PM PDT 24
Finished Jul 21 05:47:15 PM PDT 24
Peak memory 200104 kb
Host smart-bacabaf9-9935-4346-be69-9b96bfd94e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029069262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4029069262
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2673792181
Short name T123
Test name
Test status
Simulation time 1516123369 ps
CPU time 5.73 seconds
Started Jul 21 05:47:13 PM PDT 24
Finished Jul 21 05:47:19 PM PDT 24
Peak memory 200732 kb
Host smart-4259e92c-c1d9-4394-9cd4-19682bc69307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673792181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2673792181
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4174921796
Short name T371
Test name
Test status
Simulation time 184582085 ps
CPU time 1.19 seconds
Started Jul 21 05:47:14 PM PDT 24
Finished Jul 21 05:47:15 PM PDT 24
Peak memory 200404 kb
Host smart-28495835-7909-4384-b3d3-a6fd35642d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174921796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4174921796
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3754662089
Short name T256
Test name
Test status
Simulation time 191821183 ps
CPU time 1.36 seconds
Started Jul 21 05:47:16 PM PDT 24
Finished Jul 21 05:47:18 PM PDT 24
Peak memory 200544 kb
Host smart-18d36514-3bfe-405f-901e-4008d2e19ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754662089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3754662089
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.578764639
Short name T360
Test name
Test status
Simulation time 6353874620 ps
CPU time 21.83 seconds
Started Jul 21 05:47:14 PM PDT 24
Finished Jul 21 05:47:36 PM PDT 24
Peak memory 208924 kb
Host smart-d074d2b0-e9cf-433f-853d-d0bfe7035ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578764639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.578764639
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3427944687
Short name T243
Test name
Test status
Simulation time 385543636 ps
CPU time 1.97 seconds
Started Jul 21 05:47:15 PM PDT 24
Finished Jul 21 05:47:17 PM PDT 24
Peak memory 200636 kb
Host smart-a3b1871f-606a-46fb-be68-ea8c98f7136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427944687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3427944687
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2867795370
Short name T358
Test name
Test status
Simulation time 252279082 ps
CPU time 1.51 seconds
Started Jul 21 05:47:14 PM PDT 24
Finished Jul 21 05:47:16 PM PDT 24
Peak memory 200452 kb
Host smart-a984af07-a11d-4b6c-81ba-75a08e04320a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867795370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2867795370
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2390750077
Short name T144
Test name
Test status
Simulation time 58994792 ps
CPU time 0.75 seconds
Started Jul 21 05:47:21 PM PDT 24
Finished Jul 21 05:47:22 PM PDT 24
Peak memory 200244 kb
Host smart-70e0804d-36ff-4db9-bc79-e89dbea3dd15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390750077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2390750077
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.275815620
Short name T393
Test name
Test status
Simulation time 1883205241 ps
CPU time 6.75 seconds
Started Jul 21 05:47:23 PM PDT 24
Finished Jul 21 05:47:30 PM PDT 24
Peak memory 221772 kb
Host smart-f9cf7f1d-b922-407a-bfb0-eeda54fedbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275815620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.275815620
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.546688515
Short name T435
Test name
Test status
Simulation time 244079323 ps
CPU time 1.2 seconds
Started Jul 21 05:47:20 PM PDT 24
Finished Jul 21 05:47:21 PM PDT 24
Peak memory 217568 kb
Host smart-e14ea36b-4e21-46fe-bcfa-3a213f8b88b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546688515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.546688515
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1871536942
Short name T503
Test name
Test status
Simulation time 120737011 ps
CPU time 0.79 seconds
Started Jul 21 05:47:13 PM PDT 24
Finished Jul 21 05:47:14 PM PDT 24
Peak memory 200228 kb
Host smart-3f9b9156-724f-4e40-af68-ac8e29c56c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871536942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1871536942
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2747236806
Short name T148
Test name
Test status
Simulation time 863697731 ps
CPU time 4.13 seconds
Started Jul 21 05:47:20 PM PDT 24
Finished Jul 21 05:47:24 PM PDT 24
Peak memory 200752 kb
Host smart-54fb0b32-e79b-4653-baf2-34a43fd6cc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747236806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2747236806
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1996675424
Short name T339
Test name
Test status
Simulation time 143194807 ps
CPU time 1.12 seconds
Started Jul 21 05:47:30 PM PDT 24
Finished Jul 21 05:47:31 PM PDT 24
Peak memory 200420 kb
Host smart-3150d8f9-e864-4811-8889-5bd7ef3fe88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996675424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1996675424
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3691856263
Short name T308
Test name
Test status
Simulation time 122540512 ps
CPU time 1.28 seconds
Started Jul 21 05:47:15 PM PDT 24
Finished Jul 21 05:47:17 PM PDT 24
Peak memory 200616 kb
Host smart-dd2b5e4d-b01f-490b-a1f9-6eac477bccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691856263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3691856263
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1864550643
Short name T390
Test name
Test status
Simulation time 5208897787 ps
CPU time 22.89 seconds
Started Jul 21 05:47:21 PM PDT 24
Finished Jul 21 05:47:44 PM PDT 24
Peak memory 200796 kb
Host smart-411324a4-4c7f-45d4-a8c3-887bc20cc934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864550643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1864550643
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2202774763
Short name T433
Test name
Test status
Simulation time 323117300 ps
CPU time 1.91 seconds
Started Jul 21 05:47:29 PM PDT 24
Finished Jul 21 05:47:31 PM PDT 24
Peak memory 200436 kb
Host smart-f37b39cc-820a-41e4-bae3-e8bdc01472ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202774763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2202774763
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3856193925
Short name T233
Test name
Test status
Simulation time 273542376 ps
CPU time 1.53 seconds
Started Jul 21 05:47:21 PM PDT 24
Finished Jul 21 05:47:23 PM PDT 24
Peak memory 200448 kb
Host smart-a8eac6ff-4367-4e26-9ccd-74f607bb0c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856193925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3856193925
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2360643808
Short name T211
Test name
Test status
Simulation time 66153337 ps
CPU time 0.71 seconds
Started Jul 21 05:47:25 PM PDT 24
Finished Jul 21 05:47:26 PM PDT 24
Peak memory 200272 kb
Host smart-d1e6cbed-58ca-4071-996c-e01b11438e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360643808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2360643808
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1991797418
Short name T53
Test name
Test status
Simulation time 1880912581 ps
CPU time 7.84 seconds
Started Jul 21 05:47:19 PM PDT 24
Finished Jul 21 05:47:28 PM PDT 24
Peak memory 217816 kb
Host smart-6418ed1d-9036-4bf7-a38e-0f4984a189a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991797418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1991797418
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3956032255
Short name T349
Test name
Test status
Simulation time 245780228 ps
CPU time 1.09 seconds
Started Jul 21 05:47:38 PM PDT 24
Finished Jul 21 05:47:40 PM PDT 24
Peak memory 218360 kb
Host smart-e51d6092-0d80-448e-add7-bfbf17627196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956032255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3956032255
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.95466650
Short name T21
Test name
Test status
Simulation time 73160968 ps
CPU time 0.73 seconds
Started Jul 21 05:47:24 PM PDT 24
Finished Jul 21 05:47:25 PM PDT 24
Peak memory 200296 kb
Host smart-030e1199-edd5-4481-956e-8f8ab1c1fff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95466650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.95466650
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.23062554
Short name T157
Test name
Test status
Simulation time 677626994 ps
CPU time 3.73 seconds
Started Jul 21 05:47:18 PM PDT 24
Finished Jul 21 05:47:22 PM PDT 24
Peak memory 200764 kb
Host smart-beca1d3e-6e9a-4acd-bda2-ee1c41abc298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23062554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.23062554
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2832206573
Short name T215
Test name
Test status
Simulation time 149833325 ps
CPU time 1.09 seconds
Started Jul 21 05:47:23 PM PDT 24
Finished Jul 21 05:47:24 PM PDT 24
Peak memory 200476 kb
Host smart-304a9520-c4a8-4624-9684-d6b363907a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832206573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2832206573
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.4231492703
Short name T438
Test name
Test status
Simulation time 198240193 ps
CPU time 1.35 seconds
Started Jul 21 05:47:19 PM PDT 24
Finished Jul 21 05:47:20 PM PDT 24
Peak memory 200648 kb
Host smart-f7bc0a68-a168-4123-8c70-4f26c482d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231492703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.4231492703
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2434474908
Short name T191
Test name
Test status
Simulation time 1788671382 ps
CPU time 8.83 seconds
Started Jul 21 05:47:26 PM PDT 24
Finished Jul 21 05:47:35 PM PDT 24
Peak memory 217124 kb
Host smart-0df19df9-0bac-4a33-80f6-a088cb17bcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434474908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2434474908
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.134464
Short name T203
Test name
Test status
Simulation time 381820901 ps
CPU time 2.31 seconds
Started Jul 21 05:47:20 PM PDT 24
Finished Jul 21 05:47:23 PM PDT 24
Peak memory 200312 kb
Host smart-65f87498-a49e-4171-a354-8636399568b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.134464
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.650822778
Short name T238
Test name
Test status
Simulation time 130283511 ps
CPU time 0.97 seconds
Started Jul 21 05:47:21 PM PDT 24
Finished Jul 21 05:47:22 PM PDT 24
Peak memory 200436 kb
Host smart-34e4c24f-fe44-4017-adb8-30e25a26e492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650822778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.650822778
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.355301225
Short name T498
Test name
Test status
Simulation time 65616209 ps
CPU time 0.79 seconds
Started Jul 21 05:47:26 PM PDT 24
Finished Jul 21 05:47:27 PM PDT 24
Peak memory 200316 kb
Host smart-f52a9673-11fa-4b93-8e07-ad34ff9663d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355301225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.355301225
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1608974194
Short name T55
Test name
Test status
Simulation time 2364640825 ps
CPU time 8.22 seconds
Started Jul 21 05:47:26 PM PDT 24
Finished Jul 21 05:47:34 PM PDT 24
Peak memory 217872 kb
Host smart-69a79477-7668-4577-8fe2-02410184f344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608974194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1608974194
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.620067171
Short name T467
Test name
Test status
Simulation time 244247516 ps
CPU time 1.08 seconds
Started Jul 21 05:47:25 PM PDT 24
Finished Jul 21 05:47:26 PM PDT 24
Peak memory 217500 kb
Host smart-9a1bf117-7a72-47b7-86da-801d874ce3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620067171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.620067171
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.234898810
Short name T227
Test name
Test status
Simulation time 149658574 ps
CPU time 0.88 seconds
Started Jul 21 05:47:25 PM PDT 24
Finished Jul 21 05:47:26 PM PDT 24
Peak memory 200268 kb
Host smart-70f0e3f9-9c66-4763-9dcd-08de00d5ba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234898810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.234898810
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2487038853
Short name T423
Test name
Test status
Simulation time 1165209839 ps
CPU time 5.38 seconds
Started Jul 21 05:47:38 PM PDT 24
Finished Jul 21 05:47:45 PM PDT 24
Peak memory 200708 kb
Host smart-f38f26fb-3949-4fdf-9671-57499d9a45f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487038853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2487038853
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3562827243
Short name T168
Test name
Test status
Simulation time 141277578 ps
CPU time 1.08 seconds
Started Jul 21 05:47:39 PM PDT 24
Finished Jul 21 05:47:40 PM PDT 24
Peak memory 200428 kb
Host smart-70e6d54e-7d48-46cc-a182-fc23e7e200e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562827243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3562827243
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.343851013
Short name T65
Test name
Test status
Simulation time 126117725 ps
CPU time 1.16 seconds
Started Jul 21 05:47:24 PM PDT 24
Finished Jul 21 05:47:25 PM PDT 24
Peak memory 200668 kb
Host smart-b71debef-2f5d-4855-8602-f61981116923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343851013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.343851013
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2974677759
Short name T401
Test name
Test status
Simulation time 6359116662 ps
CPU time 22.77 seconds
Started Jul 21 05:47:26 PM PDT 24
Finished Jul 21 05:47:50 PM PDT 24
Peak memory 200696 kb
Host smart-53a48bd5-92d0-4edf-af69-d0772893c45b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974677759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2974677759
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2182013201
Short name T355
Test name
Test status
Simulation time 111821938 ps
CPU time 1.33 seconds
Started Jul 21 05:47:24 PM PDT 24
Finished Jul 21 05:47:25 PM PDT 24
Peak memory 200468 kb
Host smart-42f3ed49-97fe-4336-8f78-1a309dcd06d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182013201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2182013201
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.449673617
Short name T428
Test name
Test status
Simulation time 130570289 ps
CPU time 1.03 seconds
Started Jul 21 05:47:38 PM PDT 24
Finished Jul 21 05:47:40 PM PDT 24
Peak memory 200428 kb
Host smart-a136eba1-0f83-4937-875b-319c4a5038a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449673617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.449673617
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.4139949521
Short name T345
Test name
Test status
Simulation time 80738388 ps
CPU time 0.8 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:34 PM PDT 24
Peak memory 200288 kb
Host smart-bba8a785-1c2a-4726-bd32-dc744ac0ad14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139949521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.4139949521
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3178680862
Short name T447
Test name
Test status
Simulation time 92787106 ps
CPU time 0.77 seconds
Started Jul 21 05:47:25 PM PDT 24
Finished Jul 21 05:47:26 PM PDT 24
Peak memory 200220 kb
Host smart-654c50ec-ce19-4c9e-9c45-04d2d2b40011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178680862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3178680862
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.448585964
Short name T537
Test name
Test status
Simulation time 836041440 ps
CPU time 4.04 seconds
Started Jul 21 05:47:25 PM PDT 24
Finished Jul 21 05:47:29 PM PDT 24
Peak memory 200780 kb
Host smart-c972452c-93d7-4f6d-a25d-1f427cdbfd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448585964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.448585964
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1492892576
Short name T209
Test name
Test status
Simulation time 144197260 ps
CPU time 1.13 seconds
Started Jul 21 05:47:38 PM PDT 24
Finished Jul 21 05:47:40 PM PDT 24
Peak memory 200424 kb
Host smart-46c7e841-448c-4c38-a250-782a498e806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492892576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1492892576
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1821583689
Short name T27
Test name
Test status
Simulation time 246442046 ps
CPU time 1.43 seconds
Started Jul 21 05:47:38 PM PDT 24
Finished Jul 21 05:47:40 PM PDT 24
Peak memory 200636 kb
Host smart-054d940d-a669-4dce-a6c9-ff3398fc7940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821583689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1821583689
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2822474336
Short name T321
Test name
Test status
Simulation time 2294555461 ps
CPU time 10.98 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:45 PM PDT 24
Peak memory 208992 kb
Host smart-0dcc403c-58dc-4222-b7fb-d4190923138d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822474336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2822474336
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.94583842
Short name T407
Test name
Test status
Simulation time 319456552 ps
CPU time 2.01 seconds
Started Jul 21 05:47:26 PM PDT 24
Finished Jul 21 05:47:28 PM PDT 24
Peak memory 200472 kb
Host smart-81245b11-d7d6-4a4d-b674-856b400a75e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94583842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.94583842
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.328965201
Short name T426
Test name
Test status
Simulation time 63695219 ps
CPU time 0.76 seconds
Started Jul 21 05:47:26 PM PDT 24
Finished Jul 21 05:47:27 PM PDT 24
Peak memory 200432 kb
Host smart-8f6eac29-e703-49ca-9904-dffceff47d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328965201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.328965201
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2279257035
Short name T452
Test name
Test status
Simulation time 72735421 ps
CPU time 0.84 seconds
Started Jul 21 05:47:35 PM PDT 24
Finished Jul 21 05:47:36 PM PDT 24
Peak memory 200220 kb
Host smart-23c71385-f53e-41b8-b104-31dc5751e5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279257035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2279257035
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.290059811
Short name T372
Test name
Test status
Simulation time 2339799797 ps
CPU time 7.89 seconds
Started Jul 21 05:47:32 PM PDT 24
Finished Jul 21 05:47:41 PM PDT 24
Peak memory 217856 kb
Host smart-a3c103b2-e31f-46e3-8799-c643ec72d27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290059811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.290059811
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2958124445
Short name T139
Test name
Test status
Simulation time 243363845 ps
CPU time 1.12 seconds
Started Jul 21 05:47:32 PM PDT 24
Finished Jul 21 05:47:34 PM PDT 24
Peak memory 217476 kb
Host smart-b27cffcc-0d2c-4d2e-918c-5e515025a283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958124445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2958124445
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1251888946
Short name T304
Test name
Test status
Simulation time 142983952 ps
CPU time 0.86 seconds
Started Jul 21 05:47:32 PM PDT 24
Finished Jul 21 05:47:33 PM PDT 24
Peak memory 200216 kb
Host smart-617c436d-d7aa-4ab7-a6e2-cc4ba2739a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251888946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1251888946
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2956858886
Short name T283
Test name
Test status
Simulation time 1792911906 ps
CPU time 6.26 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:39 PM PDT 24
Peak memory 200652 kb
Host smart-24aa1af9-45b0-4855-a631-6b5f260e5524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956858886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2956858886
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1860752627
Short name T179
Test name
Test status
Simulation time 113911926 ps
CPU time 1.01 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:35 PM PDT 24
Peak memory 200356 kb
Host smart-cbbc0f57-3ad2-4fe4-970a-cc8d095ca6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860752627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1860752627
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1745836823
Short name T510
Test name
Test status
Simulation time 224571788 ps
CPU time 1.54 seconds
Started Jul 21 05:47:34 PM PDT 24
Finished Jul 21 05:47:36 PM PDT 24
Peak memory 200604 kb
Host smart-40aa16e6-ba95-47e6-aae3-57385c0bc896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745836823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1745836823
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.4216224642
Short name T89
Test name
Test status
Simulation time 2129339045 ps
CPU time 7.27 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:41 PM PDT 24
Peak memory 200712 kb
Host smart-b8281edd-431b-44f3-9494-9e753c27ad9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216224642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.4216224642
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.565739078
Short name T449
Test name
Test status
Simulation time 375039035 ps
CPU time 2.29 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:36 PM PDT 24
Peak memory 200480 kb
Host smart-6c89b6f7-ace0-42fd-9d3a-c73976507a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565739078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.565739078
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2425496529
Short name T412
Test name
Test status
Simulation time 113818350 ps
CPU time 0.95 seconds
Started Jul 21 05:47:32 PM PDT 24
Finished Jul 21 05:47:33 PM PDT 24
Peak memory 200380 kb
Host smart-3b9ccc3f-bb18-406d-b706-ac2497c8dafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425496529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2425496529
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.616951312
Short name T384
Test name
Test status
Simulation time 58072057 ps
CPU time 0.73 seconds
Started Jul 21 05:47:35 PM PDT 24
Finished Jul 21 05:47:36 PM PDT 24
Peak memory 200216 kb
Host smart-1aa9d4c0-b2b9-4cc0-8034-83e5da46af5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616951312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.616951312
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3488924544
Short name T239
Test name
Test status
Simulation time 244908549 ps
CPU time 1.15 seconds
Started Jul 21 05:47:35 PM PDT 24
Finished Jul 21 05:47:36 PM PDT 24
Peak memory 217488 kb
Host smart-a76b57fe-da75-4d34-af27-2821977ef33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488924544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3488924544
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2824321201
Short name T16
Test name
Test status
Simulation time 107871619 ps
CPU time 0.79 seconds
Started Jul 21 05:47:34 PM PDT 24
Finished Jul 21 05:47:35 PM PDT 24
Peak memory 200276 kb
Host smart-023c6c3f-9a13-42e3-b449-ef844c616de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824321201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2824321201
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2630516942
Short name T289
Test name
Test status
Simulation time 1084506495 ps
CPU time 4.52 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:38 PM PDT 24
Peak memory 200712 kb
Host smart-f5d8e472-e863-4cd6-a9c8-6070f0c6afbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630516942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2630516942
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2687523562
Short name T402
Test name
Test status
Simulation time 181403251 ps
CPU time 1.21 seconds
Started Jul 21 05:47:34 PM PDT 24
Finished Jul 21 05:47:36 PM PDT 24
Peak memory 200456 kb
Host smart-27345ecb-3d4b-407c-8571-9a45bae681f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687523562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2687523562
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.985096023
Short name T353
Test name
Test status
Simulation time 202983652 ps
CPU time 1.31 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:35 PM PDT 24
Peak memory 200700 kb
Host smart-2792fc2c-7bd2-4317-813e-6f3dd0c82a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985096023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.985096023
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1287719882
Short name T48
Test name
Test status
Simulation time 1456047089 ps
CPU time 6.27 seconds
Started Jul 21 05:47:35 PM PDT 24
Finished Jul 21 05:47:41 PM PDT 24
Peak memory 200676 kb
Host smart-b5a76ed8-bd65-4674-a86f-87b19f532e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287719882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1287719882
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4293378106
Short name T186
Test name
Test status
Simulation time 341452851 ps
CPU time 2.19 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:35 PM PDT 24
Peak memory 208652 kb
Host smart-c384ca32-f440-42b8-a297-ed8241759f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293378106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4293378106
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.800582624
Short name T41
Test name
Test status
Simulation time 116578852 ps
CPU time 1.05 seconds
Started Jul 21 05:47:35 PM PDT 24
Finished Jul 21 05:47:36 PM PDT 24
Peak memory 200460 kb
Host smart-8a58462c-7724-4331-8bdc-439c1bb6f377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800582624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.800582624
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1606292222
Short name T194
Test name
Test status
Simulation time 55325689 ps
CPU time 0.71 seconds
Started Jul 21 05:47:36 PM PDT 24
Finished Jul 21 05:47:37 PM PDT 24
Peak memory 200272 kb
Host smart-50887455-c921-4035-b7c7-20d7b67899e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606292222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1606292222
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2260025578
Short name T32
Test name
Test status
Simulation time 2358184301 ps
CPU time 8.34 seconds
Started Jul 21 05:47:40 PM PDT 24
Finished Jul 21 05:47:49 PM PDT 24
Peak memory 217724 kb
Host smart-b64c3fa0-31ec-40ba-a47d-89917cccd8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260025578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2260025578
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3988306324
Short name T333
Test name
Test status
Simulation time 244241856 ps
CPU time 1.13 seconds
Started Jul 21 05:47:39 PM PDT 24
Finished Jul 21 05:47:41 PM PDT 24
Peak memory 217564 kb
Host smart-905db6ad-c86d-4ad1-9a7d-104c74d06a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988306324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3988306324
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3743432416
Short name T323
Test name
Test status
Simulation time 184160015 ps
CPU time 0.9 seconds
Started Jul 21 05:47:36 PM PDT 24
Finished Jul 21 05:47:37 PM PDT 24
Peak memory 200260 kb
Host smart-cfbdc766-e613-48a1-82b7-a142167bc140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743432416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3743432416
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1945880563
Short name T28
Test name
Test status
Simulation time 854533379 ps
CPU time 4.58 seconds
Started Jul 21 05:47:33 PM PDT 24
Finished Jul 21 05:47:38 PM PDT 24
Peak memory 200608 kb
Host smart-4739fb35-77aa-41df-a374-2575c336a6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945880563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1945880563
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.231089317
Short name T296
Test name
Test status
Simulation time 147690088 ps
CPU time 1.15 seconds
Started Jul 21 05:47:38 PM PDT 24
Finished Jul 21 05:47:39 PM PDT 24
Peak memory 200344 kb
Host smart-094415e7-0388-493c-88f8-8cae1937be17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231089317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.231089317
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1045628465
Short name T525
Test name
Test status
Simulation time 110197853 ps
CPU time 1.18 seconds
Started Jul 21 05:47:35 PM PDT 24
Finished Jul 21 05:47:37 PM PDT 24
Peak memory 200656 kb
Host smart-c726da6c-9fdc-4e27-98bb-a40027dfd4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045628465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1045628465
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.4255001875
Short name T350
Test name
Test status
Simulation time 12726635098 ps
CPU time 45.28 seconds
Started Jul 21 05:47:38 PM PDT 24
Finished Jul 21 05:48:25 PM PDT 24
Peak memory 209028 kb
Host smart-52295601-4a88-4289-a631-4b211c8ffcb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255001875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.4255001875
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1969122709
Short name T386
Test name
Test status
Simulation time 142316229 ps
CPU time 1.67 seconds
Started Jul 21 05:47:37 PM PDT 24
Finished Jul 21 05:47:39 PM PDT 24
Peak memory 200472 kb
Host smart-b77dbab6-1d09-4d5d-91e9-475815bdb423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969122709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1969122709
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.149321437
Short name T253
Test name
Test status
Simulation time 207042250 ps
CPU time 1.23 seconds
Started Jul 21 05:47:40 PM PDT 24
Finished Jul 21 05:47:42 PM PDT 24
Peak memory 200348 kb
Host smart-a7524493-bc13-46f2-9221-0690f92a07e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149321437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.149321437
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1290641835
Short name T143
Test name
Test status
Simulation time 78913557 ps
CPU time 0.76 seconds
Started Jul 21 05:47:40 PM PDT 24
Finished Jul 21 05:47:41 PM PDT 24
Peak memory 200280 kb
Host smart-d96e07da-9bcd-4f71-9723-4d987b0615ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290641835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1290641835
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2970388218
Short name T385
Test name
Test status
Simulation time 1906830651 ps
CPU time 6.7 seconds
Started Jul 21 05:47:39 PM PDT 24
Finished Jul 21 05:47:47 PM PDT 24
Peak memory 217580 kb
Host smart-2c2f6bad-7faa-4dd1-9b95-18c650368770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970388218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2970388218
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3069575498
Short name T183
Test name
Test status
Simulation time 244207868 ps
CPU time 1.01 seconds
Started Jul 21 05:47:38 PM PDT 24
Finished Jul 21 05:47:39 PM PDT 24
Peak memory 217536 kb
Host smart-6e968f23-ccb7-4196-8550-64d7a6bde498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069575498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3069575498
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3538496582
Short name T13
Test name
Test status
Simulation time 98495850 ps
CPU time 0.74 seconds
Started Jul 21 05:47:40 PM PDT 24
Finished Jul 21 05:47:41 PM PDT 24
Peak memory 200212 kb
Host smart-a11886cc-4a96-4ad5-801e-c94c77764814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538496582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3538496582
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2716990941
Short name T511
Test name
Test status
Simulation time 836874423 ps
CPU time 3.85 seconds
Started Jul 21 05:47:38 PM PDT 24
Finished Jul 21 05:47:43 PM PDT 24
Peak memory 200792 kb
Host smart-16d10c7c-2db2-4c9a-8ddb-9c66d4935843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716990941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2716990941
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3758923321
Short name T140
Test name
Test status
Simulation time 147701182 ps
CPU time 1.11 seconds
Started Jul 21 05:47:40 PM PDT 24
Finished Jul 21 05:47:41 PM PDT 24
Peak memory 200480 kb
Host smart-e04adcc4-fa6e-4047-9b3b-f883befc19a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758923321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3758923321
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.546227414
Short name T363
Test name
Test status
Simulation time 120609411 ps
CPU time 1.12 seconds
Started Jul 21 05:47:40 PM PDT 24
Finished Jul 21 05:47:42 PM PDT 24
Peak memory 200560 kb
Host smart-f8743af0-d35b-481b-9a14-0b583f15abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546227414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.546227414
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2598212353
Short name T273
Test name
Test status
Simulation time 4654028321 ps
CPU time 21.8 seconds
Started Jul 21 05:47:39 PM PDT 24
Finished Jul 21 05:48:01 PM PDT 24
Peak memory 200732 kb
Host smart-8c38f445-d0da-4b87-a340-a9304f678bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598212353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2598212353
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1271299902
Short name T405
Test name
Test status
Simulation time 247123949 ps
CPU time 1.67 seconds
Started Jul 21 05:47:41 PM PDT 24
Finished Jul 21 05:47:43 PM PDT 24
Peak memory 200372 kb
Host smart-67b1fdca-6be8-40db-90ec-c5de53212c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271299902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1271299902
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.4047434550
Short name T451
Test name
Test status
Simulation time 141328701 ps
CPU time 1.14 seconds
Started Jul 21 05:47:38 PM PDT 24
Finished Jul 21 05:47:40 PM PDT 24
Peak memory 200460 kb
Host smart-61249cb0-eb74-474d-9070-846c2cf272b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047434550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4047434550
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3527895651
Short name T338
Test name
Test status
Simulation time 67647891 ps
CPU time 0.77 seconds
Started Jul 21 05:47:45 PM PDT 24
Finished Jul 21 05:47:46 PM PDT 24
Peak memory 200280 kb
Host smart-6745fa90-6818-468a-ac30-561eda0bc2bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527895651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3527895651
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.32716831
Short name T221
Test name
Test status
Simulation time 1902543545 ps
CPU time 6.81 seconds
Started Jul 21 05:47:43 PM PDT 24
Finished Jul 21 05:47:50 PM PDT 24
Peak memory 217792 kb
Host smart-995dbc1a-a097-4b87-8b8f-db98f22f143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32716831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.32716831
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3687254684
Short name T217
Test name
Test status
Simulation time 244124797 ps
CPU time 1.01 seconds
Started Jul 21 05:47:46 PM PDT 24
Finished Jul 21 05:47:48 PM PDT 24
Peak memory 217508 kb
Host smart-7e9da054-5aaa-4c81-b586-707fe9f485a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687254684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3687254684
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.222093986
Short name T334
Test name
Test status
Simulation time 92828351 ps
CPU time 0.75 seconds
Started Jul 21 05:47:39 PM PDT 24
Finished Jul 21 05:47:40 PM PDT 24
Peak memory 200304 kb
Host smart-a18072d4-a2e1-4dea-a87e-7df2c5ca06b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222093986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.222093986
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2021669113
Short name T519
Test name
Test status
Simulation time 1506174058 ps
CPU time 5.41 seconds
Started Jul 21 05:47:44 PM PDT 24
Finished Jul 21 05:47:50 PM PDT 24
Peak memory 200656 kb
Host smart-ed67d9ef-f31c-4de7-8b34-eb021ab6e8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021669113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2021669113
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2379572795
Short name T151
Test name
Test status
Simulation time 107788618 ps
CPU time 1 seconds
Started Jul 21 05:47:45 PM PDT 24
Finished Jul 21 05:47:47 PM PDT 24
Peak memory 200472 kb
Host smart-aa73aed7-5730-402a-bfd9-722dadb97329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379572795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2379572795
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3193368235
Short name T189
Test name
Test status
Simulation time 116862351 ps
CPU time 1.22 seconds
Started Jul 21 05:47:40 PM PDT 24
Finished Jul 21 05:47:42 PM PDT 24
Peak memory 200672 kb
Host smart-451fea1c-8f15-4cfb-9fee-ab44842ee5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193368235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3193368235
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3716772864
Short name T101
Test name
Test status
Simulation time 8373978911 ps
CPU time 28.06 seconds
Started Jul 21 05:47:45 PM PDT 24
Finished Jul 21 05:48:13 PM PDT 24
Peak memory 209040 kb
Host smart-cd119068-94a4-4882-97fa-477ffc2805e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716772864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3716772864
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1341019911
Short name T156
Test name
Test status
Simulation time 133451713 ps
CPU time 1.71 seconds
Started Jul 21 05:47:45 PM PDT 24
Finished Jul 21 05:47:47 PM PDT 24
Peak memory 200472 kb
Host smart-8efc8656-83a5-4a83-91dd-82258bd564de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341019911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1341019911
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3267021524
Short name T77
Test name
Test status
Simulation time 160189774 ps
CPU time 1.19 seconds
Started Jul 21 05:47:46 PM PDT 24
Finished Jul 21 05:47:47 PM PDT 24
Peak memory 200432 kb
Host smart-c18fdbeb-215d-4f73-a601-8ea9a7e237dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267021524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3267021524
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.4038575603
Short name T389
Test name
Test status
Simulation time 69573263 ps
CPU time 0.77 seconds
Started Jul 21 05:46:34 PM PDT 24
Finished Jul 21 05:46:36 PM PDT 24
Peak memory 200256 kb
Host smart-0b37a27b-e56c-465e-b9e4-c726abc36360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038575603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4038575603
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3637654337
Short name T269
Test name
Test status
Simulation time 1237544069 ps
CPU time 5.61 seconds
Started Jul 21 05:46:31 PM PDT 24
Finished Jul 21 05:46:37 PM PDT 24
Peak memory 216840 kb
Host smart-a4aaf305-1ff7-4258-9e3f-79047089d7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637654337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3637654337
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.4010250154
Short name T241
Test name
Test status
Simulation time 243700102 ps
CPU time 1.05 seconds
Started Jul 21 05:46:30 PM PDT 24
Finished Jul 21 05:46:32 PM PDT 24
Peak memory 217472 kb
Host smart-4c34e209-7546-4433-91fe-4676191ceef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010250154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.4010250154
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3786822859
Short name T276
Test name
Test status
Simulation time 93624112 ps
CPU time 0.75 seconds
Started Jul 21 05:46:31 PM PDT 24
Finished Jul 21 05:46:32 PM PDT 24
Peak memory 200148 kb
Host smart-8d2d4b9c-fdf5-4034-abd6-cfc958a3d148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786822859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3786822859
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1125174710
Short name T509
Test name
Test status
Simulation time 1017659018 ps
CPU time 4.79 seconds
Started Jul 21 05:46:30 PM PDT 24
Finished Jul 21 05:46:35 PM PDT 24
Peak memory 200748 kb
Host smart-15b994e4-8293-4aa7-a712-89d2fe7cf5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125174710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1125174710
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.750204580
Short name T73
Test name
Test status
Simulation time 8326427751 ps
CPU time 12.78 seconds
Started Jul 21 05:46:31 PM PDT 24
Finished Jul 21 05:46:44 PM PDT 24
Peak memory 217240 kb
Host smart-b1dbb872-03b6-4748-8fe2-579116219654
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750204580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.750204580
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2113903703
Short name T268
Test name
Test status
Simulation time 136494117 ps
CPU time 1.11 seconds
Started Jul 21 05:46:31 PM PDT 24
Finished Jul 21 05:46:32 PM PDT 24
Peak memory 200444 kb
Host smart-4908cb13-fee9-49f9-85f6-1f09673b36ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113903703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2113903703
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.845072200
Short name T440
Test name
Test status
Simulation time 124202475 ps
CPU time 1.18 seconds
Started Jul 21 05:46:32 PM PDT 24
Finished Jul 21 05:46:33 PM PDT 24
Peak memory 200608 kb
Host smart-534ddf7d-b06f-4d75-9002-cb66d27016bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845072200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.845072200
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1713708487
Short name T408
Test name
Test status
Simulation time 10488944300 ps
CPU time 34.61 seconds
Started Jul 21 05:46:31 PM PDT 24
Finished Jul 21 05:47:06 PM PDT 24
Peak memory 208972 kb
Host smart-74338654-301b-4d62-8659-181f31fa8944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713708487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1713708487
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3068696564
Short name T181
Test name
Test status
Simulation time 128402801 ps
CPU time 1.55 seconds
Started Jul 21 05:46:30 PM PDT 24
Finished Jul 21 05:46:32 PM PDT 24
Peak memory 200536 kb
Host smart-597bc5c7-dbda-4dc8-a6fb-dd1738809ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068696564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3068696564
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2625727693
Short name T137
Test name
Test status
Simulation time 115860174 ps
CPU time 0.92 seconds
Started Jul 21 05:46:31 PM PDT 24
Finished Jul 21 05:46:33 PM PDT 24
Peak memory 200336 kb
Host smart-e7acd49b-179a-4b1e-a705-29b5d3c622ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625727693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2625727693
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2323557968
Short name T346
Test name
Test status
Simulation time 63582455 ps
CPU time 0.77 seconds
Started Jul 21 05:47:50 PM PDT 24
Finished Jul 21 05:47:51 PM PDT 24
Peak memory 200280 kb
Host smart-8798d058-775c-4206-a544-b8851c5298bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323557968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2323557968
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1806017899
Short name T534
Test name
Test status
Simulation time 2349960022 ps
CPU time 8.27 seconds
Started Jul 21 05:47:42 PM PDT 24
Finished Jul 21 05:47:51 PM PDT 24
Peak memory 217956 kb
Host smart-7f33feaa-0289-4deb-bc37-226497ab8135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806017899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1806017899
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2129415920
Short name T430
Test name
Test status
Simulation time 244533588 ps
CPU time 1.05 seconds
Started Jul 21 05:47:49 PM PDT 24
Finished Jul 21 05:47:50 PM PDT 24
Peak memory 217508 kb
Host smart-64a573bd-5137-4d19-8545-55f130cd3bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129415920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2129415920
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3704513736
Short name T495
Test name
Test status
Simulation time 124647879 ps
CPU time 0.78 seconds
Started Jul 21 05:47:42 PM PDT 24
Finished Jul 21 05:47:43 PM PDT 24
Peak memory 200204 kb
Host smart-54924482-a60c-4809-b419-2ad877bd4b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704513736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3704513736
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3275361421
Short name T420
Test name
Test status
Simulation time 1302707934 ps
CPU time 4.93 seconds
Started Jul 21 05:47:44 PM PDT 24
Finished Jul 21 05:47:49 PM PDT 24
Peak memory 200728 kb
Host smart-08361a51-861d-48bf-b79d-8e7e153810dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275361421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3275361421
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.414641365
Short name T10
Test name
Test status
Simulation time 105984777 ps
CPU time 1 seconds
Started Jul 21 05:47:45 PM PDT 24
Finished Jul 21 05:47:46 PM PDT 24
Peak memory 200452 kb
Host smart-9124de08-844f-4789-aaf9-ec0ddfebbc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414641365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.414641365
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.223576277
Short name T316
Test name
Test status
Simulation time 249942303 ps
CPU time 1.52 seconds
Started Jul 21 05:47:46 PM PDT 24
Finished Jul 21 05:47:48 PM PDT 24
Peak memory 200676 kb
Host smart-bb17c5e2-d9cc-4497-bbf5-80533622e738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223576277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.223576277
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1811093182
Short name T453
Test name
Test status
Simulation time 7100747063 ps
CPU time 25.01 seconds
Started Jul 21 05:47:43 PM PDT 24
Finished Jul 21 05:48:08 PM PDT 24
Peak memory 208968 kb
Host smart-16f20513-d04b-47a7-9ce7-ec30dce238de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811093182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1811093182
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.4228781248
Short name T335
Test name
Test status
Simulation time 138574552 ps
CPU time 1.72 seconds
Started Jul 21 05:47:45 PM PDT 24
Finished Jul 21 05:47:47 PM PDT 24
Peak memory 200404 kb
Host smart-232faa3b-53ba-4625-8d7a-0e68640aeaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228781248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.4228781248
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.32029390
Short name T462
Test name
Test status
Simulation time 168566572 ps
CPU time 1.16 seconds
Started Jul 21 05:47:45 PM PDT 24
Finished Jul 21 05:47:46 PM PDT 24
Peak memory 200428 kb
Host smart-7179d21d-142a-4fac-9233-cf8cf02c8169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32029390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.32029390
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.343113527
Short name T212
Test name
Test status
Simulation time 58081007 ps
CPU time 0.73 seconds
Started Jul 21 05:47:47 PM PDT 24
Finished Jul 21 05:47:48 PM PDT 24
Peak memory 200280 kb
Host smart-7f82fd16-2013-4f86-b83e-c049c327572b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343113527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.343113527
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3726344807
Short name T538
Test name
Test status
Simulation time 1890672213 ps
CPU time 7.71 seconds
Started Jul 21 05:47:53 PM PDT 24
Finished Jul 21 05:48:01 PM PDT 24
Peak memory 217120 kb
Host smart-6e487cc8-9c0c-4622-be3a-ec6a3fe5fcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726344807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3726344807
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.4286618362
Short name T246
Test name
Test status
Simulation time 244861789 ps
CPU time 1.02 seconds
Started Jul 21 05:47:48 PM PDT 24
Finished Jul 21 05:47:50 PM PDT 24
Peak memory 217548 kb
Host smart-6aa62ac8-60a6-421a-9bf6-34afc86833f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286618362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.4286618362
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.536230504
Short name T18
Test name
Test status
Simulation time 119488959 ps
CPU time 0.82 seconds
Started Jul 21 05:47:49 PM PDT 24
Finished Jul 21 05:47:50 PM PDT 24
Peak memory 200224 kb
Host smart-41e2d2cb-291b-4571-9f8a-fb5ef159068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536230504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.536230504
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3914705190
Short name T136
Test name
Test status
Simulation time 1323839392 ps
CPU time 5.42 seconds
Started Jul 21 05:47:50 PM PDT 24
Finished Jul 21 05:47:56 PM PDT 24
Peak memory 200684 kb
Host smart-bd88e9d7-0bb6-494b-8aca-d8fc0a301c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914705190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3914705190
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1886196164
Short name T180
Test name
Test status
Simulation time 99028898 ps
CPU time 1 seconds
Started Jul 21 05:47:50 PM PDT 24
Finished Jul 21 05:47:52 PM PDT 24
Peak memory 200472 kb
Host smart-df38d720-b021-4a33-90e7-c03c6778b1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886196164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1886196164
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2786663491
Short name T494
Test name
Test status
Simulation time 250321932 ps
CPU time 1.44 seconds
Started Jul 21 05:47:51 PM PDT 24
Finished Jul 21 05:47:53 PM PDT 24
Peak memory 200608 kb
Host smart-6e5fa1a7-2167-4e28-aa6e-860ac1da9f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786663491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2786663491
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.500179072
Short name T88
Test name
Test status
Simulation time 3174981727 ps
CPU time 14.92 seconds
Started Jul 21 05:47:49 PM PDT 24
Finished Jul 21 05:48:04 PM PDT 24
Peak memory 200784 kb
Host smart-6fcf6dab-52da-4e24-aca4-9d0d63afcaa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500179072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.500179072
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.4205943008
Short name T220
Test name
Test status
Simulation time 510327925 ps
CPU time 2.62 seconds
Started Jul 21 05:47:51 PM PDT 24
Finished Jul 21 05:47:54 PM PDT 24
Peak memory 200448 kb
Host smart-8564eb54-251c-48bf-9ef0-3bf9ad676ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205943008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4205943008
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.652475274
Short name T270
Test name
Test status
Simulation time 148952669 ps
CPU time 1.21 seconds
Started Jul 21 05:47:49 PM PDT 24
Finished Jul 21 05:47:51 PM PDT 24
Peak memory 200296 kb
Host smart-e0642588-ff44-46e5-9d94-d3c2e0758ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652475274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.652475274
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1940576577
Short name T200
Test name
Test status
Simulation time 70528540 ps
CPU time 0.84 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:02 PM PDT 24
Peak memory 200272 kb
Host smart-626371db-fa0b-4782-abe6-bf3f05b5d37d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940576577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1940576577
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.382267542
Short name T9
Test name
Test status
Simulation time 2350931903 ps
CPU time 7.87 seconds
Started Jul 21 05:47:53 PM PDT 24
Finished Jul 21 05:48:01 PM PDT 24
Peak memory 217944 kb
Host smart-3521df32-bdbb-49ba-9286-8d87b8cbb768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382267542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.382267542
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1759984656
Short name T359
Test name
Test status
Simulation time 244909780 ps
CPU time 1.06 seconds
Started Jul 21 05:47:48 PM PDT 24
Finished Jul 21 05:47:49 PM PDT 24
Peak memory 217504 kb
Host smart-4d7dd2e8-9237-4112-a1c8-c6414dcf3901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759984656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1759984656
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2705511625
Short name T492
Test name
Test status
Simulation time 214692042 ps
CPU time 0.95 seconds
Started Jul 21 05:47:52 PM PDT 24
Finished Jul 21 05:47:53 PM PDT 24
Peak memory 200248 kb
Host smart-ee30835f-54b0-430e-abdd-cfd074ee36b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705511625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2705511625
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3382403254
Short name T96
Test name
Test status
Simulation time 763037183 ps
CPU time 4.2 seconds
Started Jul 21 05:47:49 PM PDT 24
Finished Jul 21 05:47:54 PM PDT 24
Peak memory 200728 kb
Host smart-c9ef7618-e792-4465-84e1-06fe4c748a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382403254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3382403254
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1272316215
Short name T499
Test name
Test status
Simulation time 153493827 ps
CPU time 1.29 seconds
Started Jul 21 05:47:52 PM PDT 24
Finished Jul 21 05:47:53 PM PDT 24
Peak memory 200444 kb
Host smart-2d2a1591-48c1-4ce1-a7da-82eafb0d2d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272316215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1272316215
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2673578637
Short name T470
Test name
Test status
Simulation time 239334303 ps
CPU time 1.55 seconds
Started Jul 21 05:47:51 PM PDT 24
Finished Jul 21 05:47:53 PM PDT 24
Peak memory 200672 kb
Host smart-8c645a19-8f45-4e65-95f3-3441aef18de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673578637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2673578637
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3356458398
Short name T397
Test name
Test status
Simulation time 2140834892 ps
CPU time 7.45 seconds
Started Jul 21 05:47:49 PM PDT 24
Finished Jul 21 05:47:57 PM PDT 24
Peak memory 200716 kb
Host smart-d1d6017d-21ab-4ac1-81d0-57ddf1253bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356458398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3356458398
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.964529983
Short name T409
Test name
Test status
Simulation time 474776805 ps
CPU time 2.41 seconds
Started Jul 21 05:47:51 PM PDT 24
Finished Jul 21 05:47:54 PM PDT 24
Peak memory 208644 kb
Host smart-b34f033b-7412-414c-84ca-4bd6fd106206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964529983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.964529983
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3235362273
Short name T261
Test name
Test status
Simulation time 93526074 ps
CPU time 0.97 seconds
Started Jul 21 05:47:49 PM PDT 24
Finished Jul 21 05:47:50 PM PDT 24
Peak memory 200460 kb
Host smart-fb9c2007-0e96-499f-92a0-c30ed123810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235362273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3235362273
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2049603268
Short name T318
Test name
Test status
Simulation time 86237621 ps
CPU time 0.85 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:03 PM PDT 24
Peak memory 200264 kb
Host smart-d6d8d22f-9fc7-4889-8833-9793f36a48e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049603268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2049603268
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2368388068
Short name T508
Test name
Test status
Simulation time 1893549256 ps
CPU time 7.91 seconds
Started Jul 21 05:47:58 PM PDT 24
Finished Jul 21 05:48:06 PM PDT 24
Peak memory 217568 kb
Host smart-3c1ad8b8-221f-4d63-9b9f-40f52d4694b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368388068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2368388068
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.292950927
Short name T357
Test name
Test status
Simulation time 244370823 ps
CPU time 1.09 seconds
Started Jul 21 05:47:59 PM PDT 24
Finished Jul 21 05:48:00 PM PDT 24
Peak memory 217492 kb
Host smart-8937b911-dfc3-4c8f-96d7-a4f09a2513c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292950927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.292950927
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.435596527
Short name T454
Test name
Test status
Simulation time 117499784 ps
CPU time 0.81 seconds
Started Jul 21 05:47:59 PM PDT 24
Finished Jul 21 05:48:00 PM PDT 24
Peak memory 200268 kb
Host smart-f052a09c-0010-4af8-a1c4-e7b177ac0a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435596527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.435596527
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3213815974
Short name T399
Test name
Test status
Simulation time 1489124394 ps
CPU time 5.85 seconds
Started Jul 21 05:48:00 PM PDT 24
Finished Jul 21 05:48:06 PM PDT 24
Peak memory 200776 kb
Host smart-b3e46fd3-44b3-4d44-88fd-ab5237750b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213815974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3213815974
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.755827138
Short name T415
Test name
Test status
Simulation time 98614679 ps
CPU time 1 seconds
Started Jul 21 05:47:57 PM PDT 24
Finished Jul 21 05:47:59 PM PDT 24
Peak memory 200368 kb
Host smart-ab6b9180-f7c8-4ff8-ad5e-d1ca5c6aff78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755827138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.755827138
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1406587475
Short name T285
Test name
Test status
Simulation time 211357397 ps
CPU time 1.42 seconds
Started Jul 21 05:47:59 PM PDT 24
Finished Jul 21 05:48:01 PM PDT 24
Peak memory 200692 kb
Host smart-5d0aeab4-099f-41fb-b3b3-475e62698da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406587475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1406587475
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1723487695
Short name T478
Test name
Test status
Simulation time 7023578356 ps
CPU time 25.52 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:28 PM PDT 24
Peak memory 200676 kb
Host smart-d7fe260d-b279-4cb5-99b5-d80f8a9f8714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723487695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1723487695
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1569349640
Short name T530
Test name
Test status
Simulation time 384996393 ps
CPU time 2.37 seconds
Started Jul 21 05:47:58 PM PDT 24
Finished Jul 21 05:48:01 PM PDT 24
Peak memory 200368 kb
Host smart-e6cb1f4f-d4c5-47a6-870b-79fe34f77648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569349640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1569349640
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4063957541
Short name T12
Test name
Test status
Simulation time 215486798 ps
CPU time 1.26 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:03 PM PDT 24
Peak memory 200632 kb
Host smart-d38533df-57ef-4d36-ba60-51546e736f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063957541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4063957541
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2826148552
Short name T166
Test name
Test status
Simulation time 80938482 ps
CPU time 0.79 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:02 PM PDT 24
Peak memory 200268 kb
Host smart-f7af4829-78a3-4fb5-ae03-4fc8dbc72554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826148552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2826148552
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1408393766
Short name T222
Test name
Test status
Simulation time 1222406998 ps
CPU time 5.79 seconds
Started Jul 21 05:48:02 PM PDT 24
Finished Jul 21 05:48:08 PM PDT 24
Peak memory 217832 kb
Host smart-25ae6cec-0fe4-4fd8-9619-14abe99d667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408393766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1408393766
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1719261216
Short name T224
Test name
Test status
Simulation time 244158262 ps
CPU time 1.23 seconds
Started Jul 21 05:48:04 PM PDT 24
Finished Jul 21 05:48:06 PM PDT 24
Peak memory 217408 kb
Host smart-81d8aa46-90be-4e93-80c9-84d62056f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719261216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1719261216
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2490547297
Short name T17
Test name
Test status
Simulation time 121779038 ps
CPU time 0.79 seconds
Started Jul 21 05:48:00 PM PDT 24
Finished Jul 21 05:48:02 PM PDT 24
Peak memory 200312 kb
Host smart-1530d957-a4ee-4f25-b4fb-5612b18c714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490547297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2490547297
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.674936091
Short name T480
Test name
Test status
Simulation time 983838328 ps
CPU time 4.81 seconds
Started Jul 21 05:47:59 PM PDT 24
Finished Jul 21 05:48:04 PM PDT 24
Peak memory 200572 kb
Host smart-5d6c0c45-a074-439b-b1bc-a242ae843986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674936091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.674936091
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1845574239
Short name T184
Test name
Test status
Simulation time 95607026 ps
CPU time 1 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:03 PM PDT 24
Peak memory 200452 kb
Host smart-cf5871b9-d32c-4b37-a3c3-dc67c121c38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845574239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1845574239
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3239098038
Short name T159
Test name
Test status
Simulation time 202198091 ps
CPU time 1.48 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:03 PM PDT 24
Peak memory 200644 kb
Host smart-f2f1767b-0c92-4532-bec2-c3ebbfb69dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239098038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3239098038
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1675917777
Short name T394
Test name
Test status
Simulation time 11779199822 ps
CPU time 42.55 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:44 PM PDT 24
Peak memory 200792 kb
Host smart-8778dfe8-4461-4800-9013-540d6bb973bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675917777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1675917777
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1371128226
Short name T434
Test name
Test status
Simulation time 126456616 ps
CPU time 1.76 seconds
Started Jul 21 05:47:59 PM PDT 24
Finished Jul 21 05:48:01 PM PDT 24
Peak memory 200476 kb
Host smart-88feb4d7-bbc0-4afc-b6fb-924e59085134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371128226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1371128226
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1265147632
Short name T469
Test name
Test status
Simulation time 89732551 ps
CPU time 0.86 seconds
Started Jul 21 05:47:58 PM PDT 24
Finished Jul 21 05:47:59 PM PDT 24
Peak memory 200416 kb
Host smart-d676a036-686d-441e-b438-b443b4398aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265147632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1265147632
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3593554046
Short name T366
Test name
Test status
Simulation time 78690731 ps
CPU time 0.87 seconds
Started Jul 21 05:48:02 PM PDT 24
Finished Jul 21 05:48:03 PM PDT 24
Peak memory 200248 kb
Host smart-a3bda876-5b28-4da9-aed1-cb5136a3acb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593554046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3593554046
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2860483937
Short name T35
Test name
Test status
Simulation time 1228757465 ps
CPU time 5.62 seconds
Started Jul 21 05:48:03 PM PDT 24
Finished Jul 21 05:48:09 PM PDT 24
Peak memory 221492 kb
Host smart-94f0cb93-9ea2-4613-99eb-a2073d27bc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860483937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2860483937
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.516795341
Short name T198
Test name
Test status
Simulation time 244159767 ps
CPU time 1.1 seconds
Started Jul 21 05:48:03 PM PDT 24
Finished Jul 21 05:48:05 PM PDT 24
Peak memory 217564 kb
Host smart-a85cd2e7-401c-4b7c-82f1-b386ce7eecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516795341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.516795341
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3873737483
Short name T14
Test name
Test status
Simulation time 216451530 ps
CPU time 1 seconds
Started Jul 21 05:48:00 PM PDT 24
Finished Jul 21 05:48:02 PM PDT 24
Peak memory 200308 kb
Host smart-d2817355-f85f-4242-a947-1a6a6a037f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873737483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3873737483
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.150068579
Short name T50
Test name
Test status
Simulation time 836197946 ps
CPU time 3.99 seconds
Started Jul 21 05:48:04 PM PDT 24
Finished Jul 21 05:48:08 PM PDT 24
Peak memory 200608 kb
Host smart-aaff9eae-d1df-420d-9e74-52a8d09f5091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150068579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.150068579
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2351471199
Short name T231
Test name
Test status
Simulation time 171409213 ps
CPU time 1.28 seconds
Started Jul 21 05:48:03 PM PDT 24
Finished Jul 21 05:48:05 PM PDT 24
Peak memory 200392 kb
Host smart-b9c6a790-5de6-4859-97ca-e07d0ffd5330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351471199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2351471199
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1482564905
Short name T352
Test name
Test status
Simulation time 122902298 ps
CPU time 1.14 seconds
Started Jul 21 05:48:02 PM PDT 24
Finished Jul 21 05:48:04 PM PDT 24
Peak memory 200636 kb
Host smart-275b29b1-8654-43d7-a40a-c38f89e5b414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482564905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1482564905
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3905555986
Short name T307
Test name
Test status
Simulation time 4211108237 ps
CPU time 13.64 seconds
Started Jul 21 05:48:07 PM PDT 24
Finished Jul 21 05:48:21 PM PDT 24
Peak memory 200816 kb
Host smart-72bc6306-2641-4441-90ea-23b4e238969f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905555986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3905555986
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3200438818
Short name T381
Test name
Test status
Simulation time 114333179 ps
CPU time 1.55 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:03 PM PDT 24
Peak memory 200520 kb
Host smart-8ca19ed6-420f-4260-bc97-67b3f0204251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200438818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3200438818
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2078895383
Short name T164
Test name
Test status
Simulation time 66536041 ps
CPU time 0.74 seconds
Started Jul 21 05:48:04 PM PDT 24
Finished Jul 21 05:48:05 PM PDT 24
Peak memory 200444 kb
Host smart-f88e5493-b060-4f25-acee-4afc6a3fdd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078895383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2078895383
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.888853487
Short name T463
Test name
Test status
Simulation time 66527566 ps
CPU time 0.76 seconds
Started Jul 21 05:48:06 PM PDT 24
Finished Jul 21 05:48:07 PM PDT 24
Peak memory 200260 kb
Host smart-3e212e16-66f8-44b6-877d-842dfcbf1736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888853487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.888853487
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2103121630
Short name T400
Test name
Test status
Simulation time 1226370177 ps
CPU time 5.55 seconds
Started Jul 21 05:48:03 PM PDT 24
Finished Jul 21 05:48:09 PM PDT 24
Peak memory 217776 kb
Host smart-205e3cca-af97-4e0f-ad6b-9bfc11d972dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103121630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2103121630
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.103833006
Short name T199
Test name
Test status
Simulation time 244617264 ps
CPU time 1.05 seconds
Started Jul 21 05:48:07 PM PDT 24
Finished Jul 21 05:48:08 PM PDT 24
Peak memory 217492 kb
Host smart-acf63678-192c-4cf6-8870-4756f63e94ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103833006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.103833006
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.36516173
Short name T259
Test name
Test status
Simulation time 212912092 ps
CPU time 0.94 seconds
Started Jul 21 05:48:03 PM PDT 24
Finished Jul 21 05:48:04 PM PDT 24
Peak memory 200260 kb
Host smart-11eb5b37-bdda-4402-be58-cd59b52b44c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36516173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.36516173
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.704446610
Short name T370
Test name
Test status
Simulation time 897572036 ps
CPU time 4.22 seconds
Started Jul 21 05:48:04 PM PDT 24
Finished Jul 21 05:48:09 PM PDT 24
Peak memory 200656 kb
Host smart-b56d416c-b86e-482a-b6c5-cf692c5e0dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704446610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.704446610
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.520665769
Short name T249
Test name
Test status
Simulation time 106189777 ps
CPU time 0.97 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:03 PM PDT 24
Peak memory 200460 kb
Host smart-c8451ee0-d73c-4a16-b967-20f431ee08c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520665769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.520665769
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1809569522
Short name T387
Test name
Test status
Simulation time 116901014 ps
CPU time 1.16 seconds
Started Jul 21 05:48:01 PM PDT 24
Finished Jul 21 05:48:03 PM PDT 24
Peak memory 200700 kb
Host smart-7bd875c7-797c-44a3-a23b-014b536c3498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809569522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1809569522
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2959984949
Short name T85
Test name
Test status
Simulation time 3204344041 ps
CPU time 11.59 seconds
Started Jul 21 05:48:10 PM PDT 24
Finished Jul 21 05:48:22 PM PDT 24
Peak memory 208940 kb
Host smart-b13e43ff-e133-4f1d-a37f-4beb95a1273d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959984949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2959984949
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.260801783
Short name T60
Test name
Test status
Simulation time 145369199 ps
CPU time 1.87 seconds
Started Jul 21 05:48:02 PM PDT 24
Finished Jul 21 05:48:04 PM PDT 24
Peak memory 200648 kb
Host smart-81e7cf82-d3ae-4b8b-b142-032715e73ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260801783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.260801783
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2363705689
Short name T83
Test name
Test status
Simulation time 80698994 ps
CPU time 0.81 seconds
Started Jul 21 05:48:07 PM PDT 24
Finished Jul 21 05:48:08 PM PDT 24
Peak memory 200484 kb
Host smart-25c3f571-dc8d-4f11-9cd5-a1d155d6d7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363705689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2363705689
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.4006764578
Short name T315
Test name
Test status
Simulation time 73449987 ps
CPU time 0.8 seconds
Started Jul 21 05:48:13 PM PDT 24
Finished Jul 21 05:48:15 PM PDT 24
Peak memory 200248 kb
Host smart-7c22d8db-ab21-43eb-9e9d-df08eadee8e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006764578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.4006764578
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2215789821
Short name T513
Test name
Test status
Simulation time 1886878301 ps
CPU time 6.9 seconds
Started Jul 21 05:48:09 PM PDT 24
Finished Jul 21 05:48:16 PM PDT 24
Peak memory 216896 kb
Host smart-be273682-7062-45fc-9e1e-3a83e38e65bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215789821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2215789821
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1244488236
Short name T267
Test name
Test status
Simulation time 244531996 ps
CPU time 1.05 seconds
Started Jul 21 05:48:05 PM PDT 24
Finished Jul 21 05:48:07 PM PDT 24
Peak memory 217496 kb
Host smart-d7be76a5-968c-456b-9b99-0ba61c7f09e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244488236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1244488236
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.896843827
Short name T484
Test name
Test status
Simulation time 177208333 ps
CPU time 0.86 seconds
Started Jul 21 05:48:09 PM PDT 24
Finished Jul 21 05:48:10 PM PDT 24
Peak memory 200288 kb
Host smart-1fb2cd6b-0171-4b33-b237-9c5f5fe64252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896843827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.896843827
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1825385639
Short name T172
Test name
Test status
Simulation time 886040291 ps
CPU time 4.26 seconds
Started Jul 21 05:48:08 PM PDT 24
Finished Jul 21 05:48:13 PM PDT 24
Peak memory 200732 kb
Host smart-adb3fa63-cc92-4bb8-9de2-c9bedd72c1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825385639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1825385639
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2187062705
Short name T314
Test name
Test status
Simulation time 121864483 ps
CPU time 1.18 seconds
Started Jul 21 05:48:08 PM PDT 24
Finished Jul 21 05:48:09 PM PDT 24
Peak memory 200564 kb
Host smart-39e54b58-7fe1-4bfd-be8c-582aa7f4467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187062705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2187062705
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.477968955
Short name T501
Test name
Test status
Simulation time 12952762346 ps
CPU time 42.07 seconds
Started Jul 21 05:48:06 PM PDT 24
Finished Jul 21 05:48:49 PM PDT 24
Peak memory 208932 kb
Host smart-1c3f69d5-f5eb-48cb-b109-d5240fb1e103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477968955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.477968955
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2725465254
Short name T254
Test name
Test status
Simulation time 146540928 ps
CPU time 1.8 seconds
Started Jul 21 05:48:06 PM PDT 24
Finished Jul 21 05:48:08 PM PDT 24
Peak memory 200472 kb
Host smart-150d8d61-b9d3-47fc-96a9-a343558a57e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725465254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2725465254
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3115630487
Short name T84
Test name
Test status
Simulation time 100699659 ps
CPU time 0.98 seconds
Started Jul 21 05:48:13 PM PDT 24
Finished Jul 21 05:48:15 PM PDT 24
Peak memory 200432 kb
Host smart-1b428711-3b53-4982-b822-a89cf59c66ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115630487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3115630487
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2558318461
Short name T57
Test name
Test status
Simulation time 1220213941 ps
CPU time 5.4 seconds
Started Jul 21 05:48:09 PM PDT 24
Finished Jul 21 05:48:15 PM PDT 24
Peak memory 217812 kb
Host smart-7b97ae5c-0dc4-4363-8cc8-233fcc61e335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558318461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2558318461
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1091706434
Short name T45
Test name
Test status
Simulation time 244484331 ps
CPU time 1.1 seconds
Started Jul 21 05:48:10 PM PDT 24
Finished Jul 21 05:48:11 PM PDT 24
Peak memory 217468 kb
Host smart-b90b30b1-379f-475f-a1cf-0ffd94a6c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091706434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1091706434
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2077825348
Short name T250
Test name
Test status
Simulation time 198786608 ps
CPU time 0.88 seconds
Started Jul 21 05:48:08 PM PDT 24
Finished Jul 21 05:48:10 PM PDT 24
Peak memory 200260 kb
Host smart-2351b65c-f015-4c4f-8093-b6e4ae18e227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077825348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2077825348
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.194943198
Short name T446
Test name
Test status
Simulation time 869572920 ps
CPU time 4.18 seconds
Started Jul 21 05:48:08 PM PDT 24
Finished Jul 21 05:48:13 PM PDT 24
Peak memory 200776 kb
Host smart-2b2ddbd1-990b-49f8-a7fa-7c8db52fa8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194943198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.194943198
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.414822750
Short name T190
Test name
Test status
Simulation time 103244219 ps
CPU time 0.98 seconds
Started Jul 21 05:48:06 PM PDT 24
Finished Jul 21 05:48:07 PM PDT 24
Peak memory 200384 kb
Host smart-f2135662-1be3-43d3-8792-0fbe54c05e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414822750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.414822750
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1504090124
Short name T487
Test name
Test status
Simulation time 115868291 ps
CPU time 1.22 seconds
Started Jul 21 05:48:09 PM PDT 24
Finished Jul 21 05:48:11 PM PDT 24
Peak memory 200688 kb
Host smart-f3e518e2-3f48-4a9a-8e43-5cdf8fc08fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504090124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1504090124
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1956460909
Short name T512
Test name
Test status
Simulation time 9713772774 ps
CPU time 33.55 seconds
Started Jul 21 05:48:12 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 200740 kb
Host smart-65e87ca5-613f-4d43-8e1d-d3357925819a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956460909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1956460909
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3998635119
Short name T367
Test name
Test status
Simulation time 316700871 ps
CPU time 2.29 seconds
Started Jul 21 05:48:07 PM PDT 24
Finished Jul 21 05:48:10 PM PDT 24
Peak memory 200476 kb
Host smart-a630d88e-d597-475a-a4b1-79a3bbe7335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998635119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3998635119
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.103875573
Short name T235
Test name
Test status
Simulation time 238901508 ps
CPU time 1.41 seconds
Started Jul 21 05:48:09 PM PDT 24
Finished Jul 21 05:48:11 PM PDT 24
Peak memory 200676 kb
Host smart-c0991da4-6648-469e-973a-6dd4bd117068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103875573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.103875573
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1239080786
Short name T311
Test name
Test status
Simulation time 57288830 ps
CPU time 0.72 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:17 PM PDT 24
Peak memory 200264 kb
Host smart-9e35f32d-6abc-44c4-a361-8122e75134db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239080786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1239080786
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2704477041
Short name T277
Test name
Test status
Simulation time 2168879285 ps
CPU time 7.8 seconds
Started Jul 21 05:48:15 PM PDT 24
Finished Jul 21 05:48:24 PM PDT 24
Peak memory 217840 kb
Host smart-0541c898-7258-47a7-b0b0-1078128b6a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704477041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2704477041
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3231692015
Short name T422
Test name
Test status
Simulation time 247028236 ps
CPU time 1.08 seconds
Started Jul 21 05:48:13 PM PDT 24
Finished Jul 21 05:48:15 PM PDT 24
Peak memory 217500 kb
Host smart-671d68a3-d432-4d4b-bbd0-48d8db7fd846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231692015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3231692015
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1264714075
Short name T457
Test name
Test status
Simulation time 156576176 ps
CPU time 0.87 seconds
Started Jul 21 05:48:12 PM PDT 24
Finished Jul 21 05:48:13 PM PDT 24
Peak memory 200220 kb
Host smart-3592877f-62f6-4b2f-b5ef-00e9b164b745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264714075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1264714075
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.367645381
Short name T106
Test name
Test status
Simulation time 860114967 ps
CPU time 4.58 seconds
Started Jul 21 05:48:16 PM PDT 24
Finished Jul 21 05:48:22 PM PDT 24
Peak memory 200720 kb
Host smart-2e768edf-b100-4e11-9c4f-08f0bec6dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367645381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.367645381
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3198417198
Short name T280
Test name
Test status
Simulation time 105527790 ps
CPU time 0.99 seconds
Started Jul 21 05:48:13 PM PDT 24
Finished Jul 21 05:48:15 PM PDT 24
Peak memory 200460 kb
Host smart-e95f28d6-d806-4a82-a9c7-807efe530a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198417198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3198417198
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2048031417
Short name T516
Test name
Test status
Simulation time 110245164 ps
CPU time 1.16 seconds
Started Jul 21 05:48:13 PM PDT 24
Finished Jul 21 05:48:15 PM PDT 24
Peak memory 200708 kb
Host smart-796b5abe-eeeb-4d11-b32e-3bfecb1da42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048031417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2048031417
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2835080827
Short name T297
Test name
Test status
Simulation time 6453701404 ps
CPU time 30.86 seconds
Started Jul 21 05:48:17 PM PDT 24
Finished Jul 21 05:48:49 PM PDT 24
Peak memory 200816 kb
Host smart-50a16408-460c-4ac5-bb3b-06b49b33c475
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835080827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2835080827
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3176350441
Short name T362
Test name
Test status
Simulation time 142952101 ps
CPU time 1.76 seconds
Started Jul 21 05:48:23 PM PDT 24
Finished Jul 21 05:48:25 PM PDT 24
Peak memory 200444 kb
Host smart-2c964e36-9430-4b2c-9247-ebb14f19107b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176350441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3176350441
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3900747803
Short name T165
Test name
Test status
Simulation time 111357030 ps
CPU time 0.96 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:17 PM PDT 24
Peak memory 200360 kb
Host smart-f2f71a6d-8f53-4a13-bbb1-e7b1781d443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900747803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3900747803
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2184524469
Short name T161
Test name
Test status
Simulation time 58160758 ps
CPU time 0.73 seconds
Started Jul 21 05:46:44 PM PDT 24
Finished Jul 21 05:46:45 PM PDT 24
Peak memory 200248 kb
Host smart-ee9e7dc9-68d8-4185-95c3-fc6142a3cd1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184524469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2184524469
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.4069174664
Short name T317
Test name
Test status
Simulation time 244027207 ps
CPU time 1.07 seconds
Started Jul 21 05:46:34 PM PDT 24
Finished Jul 21 05:46:36 PM PDT 24
Peak memory 217400 kb
Host smart-6f8e1a56-479d-438b-903d-7896a86264aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069174664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.4069174664
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3724224877
Short name T380
Test name
Test status
Simulation time 103747229 ps
CPU time 0.81 seconds
Started Jul 21 05:46:36 PM PDT 24
Finished Jul 21 05:46:37 PM PDT 24
Peak memory 200168 kb
Host smart-2fbfd167-9da8-4ba0-a8f1-e190c46d21a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724224877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3724224877
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2718454520
Short name T97
Test name
Test status
Simulation time 1248296390 ps
CPU time 4.78 seconds
Started Jul 21 05:46:36 PM PDT 24
Finished Jul 21 05:46:41 PM PDT 24
Peak memory 200716 kb
Host smart-2ef73233-e014-4ec5-9e5f-3c3d9f92eb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718454520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2718454520
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2906760007
Short name T71
Test name
Test status
Simulation time 8492315028 ps
CPU time 13.27 seconds
Started Jul 21 05:46:36 PM PDT 24
Finished Jul 21 05:46:50 PM PDT 24
Peak memory 217276 kb
Host smart-4a1ce7be-6378-4cc0-8c35-344098247919
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906760007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2906760007
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2133334495
Short name T305
Test name
Test status
Simulation time 148148686 ps
CPU time 1.16 seconds
Started Jul 21 05:46:35 PM PDT 24
Finished Jul 21 05:46:36 PM PDT 24
Peak memory 200476 kb
Host smart-d582fe27-f465-4f85-aa76-94e820047b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133334495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2133334495
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1553541182
Short name T312
Test name
Test status
Simulation time 117578964 ps
CPU time 1.21 seconds
Started Jul 21 05:46:34 PM PDT 24
Finished Jul 21 05:46:36 PM PDT 24
Peak memory 200556 kb
Host smart-b171e222-4737-4825-a329-aeb54f699160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553541182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1553541182
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.932920063
Short name T468
Test name
Test status
Simulation time 3998643999 ps
CPU time 18.16 seconds
Started Jul 21 05:46:37 PM PDT 24
Finished Jul 21 05:46:55 PM PDT 24
Peak memory 200772 kb
Host smart-55c42b22-75e8-464d-b6db-dc63c3cfbb6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932920063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.932920063
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.900805391
Short name T425
Test name
Test status
Simulation time 136775486 ps
CPU time 1.67 seconds
Started Jul 21 05:46:35 PM PDT 24
Finished Jul 21 05:46:37 PM PDT 24
Peak memory 208680 kb
Host smart-779bc58d-6b48-4538-89e7-5343c6cbabc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900805391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.900805391
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.388778375
Short name T523
Test name
Test status
Simulation time 171285476 ps
CPU time 1.1 seconds
Started Jul 21 05:46:34 PM PDT 24
Finished Jul 21 05:46:36 PM PDT 24
Peak memory 200340 kb
Host smart-b6380bac-30c1-4b32-b3e3-28ad467ff538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388778375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.388778375
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1989278378
Short name T141
Test name
Test status
Simulation time 76525296 ps
CPU time 0.8 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:16 PM PDT 24
Peak memory 200292 kb
Host smart-737419a8-e598-4f59-9786-71753fc9234d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989278378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1989278378
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3574589554
Short name T522
Test name
Test status
Simulation time 2174213657 ps
CPU time 7.7 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:23 PM PDT 24
Peak memory 217796 kb
Host smart-e96a52f5-85b1-4a66-ba81-f2ad16c20d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574589554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3574589554
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2621515221
Short name T517
Test name
Test status
Simulation time 247403332 ps
CPU time 1.04 seconds
Started Jul 21 05:48:15 PM PDT 24
Finished Jul 21 05:48:17 PM PDT 24
Peak memory 217572 kb
Host smart-8318deca-4630-49e8-a03b-3fbc27db8d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621515221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2621515221
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2417310479
Short name T437
Test name
Test status
Simulation time 160566331 ps
CPU time 0.89 seconds
Started Jul 21 05:48:23 PM PDT 24
Finished Jul 21 05:48:24 PM PDT 24
Peak memory 200244 kb
Host smart-604ac02a-f921-4eef-abc4-d5bc7d6a8252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417310479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2417310479
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2625029178
Short name T177
Test name
Test status
Simulation time 714504235 ps
CPU time 3.75 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:20 PM PDT 24
Peak memory 200732 kb
Host smart-84f8d384-2499-4740-994a-c3dba81fea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625029178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2625029178
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3417585909
Short name T329
Test name
Test status
Simulation time 111066982 ps
CPU time 0.99 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:16 PM PDT 24
Peak memory 200464 kb
Host smart-4eaee285-70c5-43b5-9d78-35f4dc0e2f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417585909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3417585909
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4095151023
Short name T130
Test name
Test status
Simulation time 247041670 ps
CPU time 1.5 seconds
Started Jul 21 05:48:13 PM PDT 24
Finished Jul 21 05:48:16 PM PDT 24
Peak memory 200612 kb
Host smart-4f2448a2-89bd-4147-a7a6-02a73aef74a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095151023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4095151023
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3623377685
Short name T87
Test name
Test status
Simulation time 3696853579 ps
CPU time 12.89 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:28 PM PDT 24
Peak memory 208996 kb
Host smart-91c9d87f-a77b-44d5-8e14-df217b72d1fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623377685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3623377685
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3020126112
Short name T158
Test name
Test status
Simulation time 106118816 ps
CPU time 1.39 seconds
Started Jul 21 05:48:15 PM PDT 24
Finished Jul 21 05:48:18 PM PDT 24
Peak memory 200460 kb
Host smart-744b96c9-4852-440f-a28b-dccbeaaffbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020126112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3020126112
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1168017519
Short name T476
Test name
Test status
Simulation time 122565815 ps
CPU time 0.96 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:16 PM PDT 24
Peak memory 200296 kb
Host smart-42879841-d0da-4ff0-b54e-f167ebeaadbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168017519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1168017519
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3811629073
Short name T288
Test name
Test status
Simulation time 91780945 ps
CPU time 0.83 seconds
Started Jul 21 05:48:16 PM PDT 24
Finished Jul 21 05:48:18 PM PDT 24
Peak memory 200264 kb
Host smart-3633fcbf-c7ff-4092-ab9f-b15243cee5e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811629073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3811629073
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1001448088
Short name T47
Test name
Test status
Simulation time 1876917257 ps
CPU time 6.94 seconds
Started Jul 21 05:48:13 PM PDT 24
Finished Jul 21 05:48:21 PM PDT 24
Peak memory 221732 kb
Host smart-53ee8324-e9d4-4e5c-9591-7d64864c518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001448088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1001448088
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1353829993
Short name T429
Test name
Test status
Simulation time 246366661 ps
CPU time 1.01 seconds
Started Jul 21 05:48:16 PM PDT 24
Finished Jul 21 05:48:18 PM PDT 24
Peak memory 217352 kb
Host smart-2d6e8574-d090-4ccd-8345-5553a7f7d19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353829993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1353829993
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1334887594
Short name T213
Test name
Test status
Simulation time 180274104 ps
CPU time 0.86 seconds
Started Jul 21 05:48:12 PM PDT 24
Finished Jul 21 05:48:14 PM PDT 24
Peak memory 200276 kb
Host smart-68f5f303-7e4f-4a6b-8f63-93f490b098a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334887594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1334887594
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3531859064
Short name T531
Test name
Test status
Simulation time 1542331878 ps
CPU time 6.38 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:21 PM PDT 24
Peak memory 200776 kb
Host smart-008f53ef-2f24-4e2d-b6f7-9c10d9746772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531859064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3531859064
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3787261423
Short name T521
Test name
Test status
Simulation time 107664762 ps
CPU time 1.04 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:16 PM PDT 24
Peak memory 200440 kb
Host smart-50e65a80-747e-43a3-8a02-44ca5818694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787261423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3787261423
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1279487235
Short name T4
Test name
Test status
Simulation time 188239447 ps
CPU time 1.31 seconds
Started Jul 21 05:48:16 PM PDT 24
Finished Jul 21 05:48:18 PM PDT 24
Peak memory 200692 kb
Host smart-5028260c-cdda-4492-b967-94c169d1318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279487235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1279487235
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.830252178
Short name T263
Test name
Test status
Simulation time 2051121186 ps
CPU time 9.2 seconds
Started Jul 21 05:48:21 PM PDT 24
Finished Jul 21 05:48:31 PM PDT 24
Peak memory 200680 kb
Host smart-fe59163b-c468-4b46-90e1-be9c88b6aba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830252178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.830252178
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3849560607
Short name T175
Test name
Test status
Simulation time 125232658 ps
CPU time 1.48 seconds
Started Jul 21 05:48:13 PM PDT 24
Finished Jul 21 05:48:16 PM PDT 24
Peak memory 200456 kb
Host smart-86b28bae-378b-46e1-8956-4b2d9b63928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849560607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3849560607
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2577184740
Short name T135
Test name
Test status
Simulation time 137489979 ps
CPU time 1.11 seconds
Started Jul 21 05:48:12 PM PDT 24
Finished Jul 21 05:48:13 PM PDT 24
Peak memory 200348 kb
Host smart-c129f634-15b0-43f0-ad87-41b4b314b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577184740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2577184740
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2400408605
Short name T483
Test name
Test status
Simulation time 94825220 ps
CPU time 0.87 seconds
Started Jul 21 05:48:19 PM PDT 24
Finished Jul 21 05:48:20 PM PDT 24
Peak memory 200284 kb
Host smart-a4644ed4-0c52-4691-babd-cc86066bb81f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400408605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2400408605
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.4235524929
Short name T33
Test name
Test status
Simulation time 2364515887 ps
CPU time 7.87 seconds
Started Jul 21 05:48:20 PM PDT 24
Finished Jul 21 05:48:28 PM PDT 24
Peak memory 217772 kb
Host smart-ffe0ff6e-fd6e-4d45-b271-5ee30bdacc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235524929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.4235524929
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.359225175
Short name T532
Test name
Test status
Simulation time 244492515 ps
CPU time 1.04 seconds
Started Jul 21 05:48:22 PM PDT 24
Finished Jul 21 05:48:23 PM PDT 24
Peak memory 217568 kb
Host smart-6144c79d-c09f-4236-bc6b-936e20a54578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359225175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.359225175
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3810379813
Short name T391
Test name
Test status
Simulation time 184490257 ps
CPU time 0.89 seconds
Started Jul 21 05:48:13 PM PDT 24
Finished Jul 21 05:48:15 PM PDT 24
Peak memory 200252 kb
Host smart-4d2d092b-8e80-4b58-a2ee-1e3a0980cc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810379813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3810379813
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3401178198
Short name T76
Test name
Test status
Simulation time 682998861 ps
CPU time 3.57 seconds
Started Jul 21 05:48:14 PM PDT 24
Finished Jul 21 05:48:18 PM PDT 24
Peak memory 200676 kb
Host smart-173f07c0-461f-46b2-bca9-ca42fd6fbcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401178198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3401178198
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2235898339
Short name T292
Test name
Test status
Simulation time 104824895 ps
CPU time 0.97 seconds
Started Jul 21 05:48:20 PM PDT 24
Finished Jul 21 05:48:21 PM PDT 24
Peak memory 200460 kb
Host smart-3b79a598-898d-4a9d-8e46-c4e8b582e0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235898339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2235898339
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2238748963
Short name T223
Test name
Test status
Simulation time 121956877 ps
CPU time 1.17 seconds
Started Jul 21 05:48:15 PM PDT 24
Finished Jul 21 05:48:17 PM PDT 24
Peak memory 200692 kb
Host smart-69a4bc66-60fc-4c76-a50e-e662ac914311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238748963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2238748963
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1753279414
Short name T479
Test name
Test status
Simulation time 1028493267 ps
CPU time 4.72 seconds
Started Jul 21 05:48:26 PM PDT 24
Finished Jul 21 05:48:31 PM PDT 24
Peak memory 200708 kb
Host smart-bac98b97-1e94-4f95-a157-04e0465f34fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753279414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1753279414
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1624219867
Short name T432
Test name
Test status
Simulation time 288327008 ps
CPU time 1.97 seconds
Started Jul 21 05:48:20 PM PDT 24
Finished Jul 21 05:48:23 PM PDT 24
Peak memory 200448 kb
Host smart-c4205876-b732-43f2-878c-2db2de80d91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624219867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1624219867
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2184967031
Short name T43
Test name
Test status
Simulation time 246416031 ps
CPU time 1.42 seconds
Started Jul 21 05:48:23 PM PDT 24
Finished Jul 21 05:48:25 PM PDT 24
Peak memory 200700 kb
Host smart-5c0551e0-59bd-43da-85f5-18dff8dbe2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184967031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2184967031
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3146376922
Short name T472
Test name
Test status
Simulation time 72359162 ps
CPU time 0.83 seconds
Started Jul 21 05:48:21 PM PDT 24
Finished Jul 21 05:48:23 PM PDT 24
Peak memory 200220 kb
Host smart-b3038896-e604-4fa8-ab4e-7843d1298eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146376922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3146376922
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3447562691
Short name T56
Test name
Test status
Simulation time 1894080721 ps
CPU time 6.79 seconds
Started Jul 21 05:48:23 PM PDT 24
Finished Jul 21 05:48:30 PM PDT 24
Peak memory 221772 kb
Host smart-0f6e6abf-a71d-4721-97eb-32bc1b3b59b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447562691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3447562691
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3020619254
Short name T228
Test name
Test status
Simulation time 244526488 ps
CPU time 1.08 seconds
Started Jul 21 05:48:20 PM PDT 24
Finished Jul 21 05:48:21 PM PDT 24
Peak memory 217480 kb
Host smart-cb63b798-d523-419c-b731-f6af727d60a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020619254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3020619254
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2628074844
Short name T442
Test name
Test status
Simulation time 117815860 ps
CPU time 0.78 seconds
Started Jul 21 05:48:21 PM PDT 24
Finished Jul 21 05:48:22 PM PDT 24
Peak memory 200272 kb
Host smart-581489d7-e574-4132-9f68-2b61466d05e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628074844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2628074844
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1728151145
Short name T414
Test name
Test status
Simulation time 1805678891 ps
CPU time 7.64 seconds
Started Jul 21 05:48:21 PM PDT 24
Finished Jul 21 05:48:29 PM PDT 24
Peak memory 200708 kb
Host smart-db9c0180-464b-468f-b33f-b71a5813a753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728151145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1728151145
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3858522672
Short name T171
Test name
Test status
Simulation time 141528432 ps
CPU time 1.12 seconds
Started Jul 21 05:48:27 PM PDT 24
Finished Jul 21 05:48:29 PM PDT 24
Peak memory 200428 kb
Host smart-efd2d15b-ee31-4002-9d41-11a622f8a811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858522672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3858522672
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2452557782
Short name T229
Test name
Test status
Simulation time 114414056 ps
CPU time 1.17 seconds
Started Jul 21 05:48:21 PM PDT 24
Finished Jul 21 05:48:23 PM PDT 24
Peak memory 200712 kb
Host smart-801eae1b-5179-4e62-94d8-6409232098f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452557782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2452557782
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.362074921
Short name T535
Test name
Test status
Simulation time 1117325067 ps
CPU time 5.37 seconds
Started Jul 21 05:48:23 PM PDT 24
Finished Jul 21 05:48:29 PM PDT 24
Peak memory 200772 kb
Host smart-07b5ff50-f9d0-4c5e-9f69-2d1d6e44a496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362074921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.362074921
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.420969882
Short name T193
Test name
Test status
Simulation time 100074862 ps
CPU time 1.02 seconds
Started Jul 21 05:48:20 PM PDT 24
Finished Jul 21 05:48:22 PM PDT 24
Peak memory 200436 kb
Host smart-8e8f4889-3976-4191-9782-4ec358da8a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420969882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.420969882
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2088624501
Short name T162
Test name
Test status
Simulation time 69319588 ps
CPU time 0.73 seconds
Started Jul 21 05:48:24 PM PDT 24
Finished Jul 21 05:48:25 PM PDT 24
Peak memory 200272 kb
Host smart-f14ae95e-00d4-4e7d-b81d-04a5c3388921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088624501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2088624501
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1216358550
Short name T382
Test name
Test status
Simulation time 1223204152 ps
CPU time 6.23 seconds
Started Jul 21 05:48:25 PM PDT 24
Finished Jul 21 05:48:31 PM PDT 24
Peak memory 221772 kb
Host smart-7b9510b1-41d6-4166-934d-b7f5b12534a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216358550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1216358550
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1552466817
Short name T75
Test name
Test status
Simulation time 245364311 ps
CPU time 1.05 seconds
Started Jul 21 05:48:26 PM PDT 24
Finished Jul 21 05:48:28 PM PDT 24
Peak memory 217436 kb
Host smart-69614d7d-2d6f-46db-b843-dc1bb62d7fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552466817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1552466817
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1545268451
Short name T230
Test name
Test status
Simulation time 174999606 ps
CPU time 0.83 seconds
Started Jul 21 05:48:21 PM PDT 24
Finished Jul 21 05:48:22 PM PDT 24
Peak memory 200276 kb
Host smart-f03b5a30-d1d8-4c1c-98f4-951d8d26f289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545268451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1545268451
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3081716046
Short name T491
Test name
Test status
Simulation time 1445333469 ps
CPU time 5.98 seconds
Started Jul 21 05:48:27 PM PDT 24
Finished Jul 21 05:48:33 PM PDT 24
Peak memory 200744 kb
Host smart-4a0ab03e-a20f-47b3-a858-034a0d16cde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081716046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3081716046
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.4031630466
Short name T149
Test name
Test status
Simulation time 144657648 ps
CPU time 1.15 seconds
Started Jul 21 05:48:21 PM PDT 24
Finished Jul 21 05:48:23 PM PDT 24
Peak memory 200456 kb
Host smart-95239f93-4786-482a-bb7e-9c7fd6d65253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031630466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.4031630466
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2592619422
Short name T218
Test name
Test status
Simulation time 193946116 ps
CPU time 1.31 seconds
Started Jul 21 05:48:18 PM PDT 24
Finished Jul 21 05:48:20 PM PDT 24
Peak memory 200684 kb
Host smart-fae33ed7-8dc5-464e-8b5d-5191807a1670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592619422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2592619422
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.350344992
Short name T104
Test name
Test status
Simulation time 14549685615 ps
CPU time 55.12 seconds
Started Jul 21 05:48:26 PM PDT 24
Finished Jul 21 05:49:21 PM PDT 24
Peak memory 209016 kb
Host smart-4221ec24-79d2-4fbf-af77-fc7fdba8ee52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350344992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.350344992
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.842289864
Short name T266
Test name
Test status
Simulation time 524783650 ps
CPU time 2.76 seconds
Started Jul 21 05:48:19 PM PDT 24
Finished Jul 21 05:48:22 PM PDT 24
Peak memory 200476 kb
Host smart-34f2a359-c996-4a89-a1cd-0a8cf2d77368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842289864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.842289864
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1395853989
Short name T465
Test name
Test status
Simulation time 70397942 ps
CPU time 0.83 seconds
Started Jul 21 05:48:20 PM PDT 24
Finished Jul 21 05:48:21 PM PDT 24
Peak memory 200460 kb
Host smart-742b1f28-22d5-4474-ae7f-c627dab0027a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395853989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1395853989
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1638349526
Short name T436
Test name
Test status
Simulation time 81114632 ps
CPU time 0.8 seconds
Started Jul 21 05:48:27 PM PDT 24
Finished Jul 21 05:48:28 PM PDT 24
Peak memory 200232 kb
Host smart-11898fa4-42d3-46c4-afd7-ddb6243c012d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638349526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1638349526
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1491012444
Short name T52
Test name
Test status
Simulation time 1222323391 ps
CPU time 5.12 seconds
Started Jul 21 05:48:25 PM PDT 24
Finished Jul 21 05:48:31 PM PDT 24
Peak memory 217788 kb
Host smart-e24bcd72-d4c6-4bd2-b48a-73fe78beaea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491012444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1491012444
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4200773783
Short name T306
Test name
Test status
Simulation time 244191199 ps
CPU time 1.12 seconds
Started Jul 21 05:48:27 PM PDT 24
Finished Jul 21 05:48:28 PM PDT 24
Peak memory 217492 kb
Host smart-84c2d3a4-f839-491d-84fe-9f2a5e1cb1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200773783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4200773783
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3399610449
Short name T524
Test name
Test status
Simulation time 82456341 ps
CPU time 0.72 seconds
Started Jul 21 05:48:26 PM PDT 24
Finished Jul 21 05:48:27 PM PDT 24
Peak memory 200276 kb
Host smart-fb03d89a-1351-4a63-9b6f-619aea8924c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399610449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3399610449
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2697508173
Short name T327
Test name
Test status
Simulation time 2146886273 ps
CPU time 7.75 seconds
Started Jul 21 05:48:28 PM PDT 24
Finished Jul 21 05:48:37 PM PDT 24
Peak memory 200744 kb
Host smart-959643ea-1844-4ec4-89b4-994504dc3210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697508173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2697508173
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2393910224
Short name T507
Test name
Test status
Simulation time 100856180 ps
CPU time 1.01 seconds
Started Jul 21 05:48:28 PM PDT 24
Finished Jul 21 05:48:30 PM PDT 24
Peak memory 200444 kb
Host smart-d1aa8a6b-4ce6-46b1-aaf0-13525a7af73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393910224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2393910224
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1375209236
Short name T226
Test name
Test status
Simulation time 225416578 ps
CPU time 1.41 seconds
Started Jul 21 05:48:28 PM PDT 24
Finished Jul 21 05:48:30 PM PDT 24
Peak memory 200660 kb
Host smart-54958beb-eb36-4c19-b816-21f4b7f3a8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375209236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1375209236
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1371700801
Short name T459
Test name
Test status
Simulation time 2009889849 ps
CPU time 9.21 seconds
Started Jul 21 05:48:27 PM PDT 24
Finished Jul 21 05:48:37 PM PDT 24
Peak memory 200784 kb
Host smart-6b96320b-cb94-495d-b9ae-6efe82e2c244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371700801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1371700801
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3296911373
Short name T86
Test name
Test status
Simulation time 270738220 ps
CPU time 1.96 seconds
Started Jul 21 05:48:28 PM PDT 24
Finished Jul 21 05:48:30 PM PDT 24
Peak memory 200472 kb
Host smart-03534432-9cce-4b67-90c3-930cdfb90809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296911373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3296911373
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.155407736
Short name T343
Test name
Test status
Simulation time 213118201 ps
CPU time 1.34 seconds
Started Jul 21 05:48:28 PM PDT 24
Finished Jul 21 05:48:30 PM PDT 24
Peak memory 200456 kb
Host smart-c6d006f0-480f-4a53-92dc-637c3a830542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155407736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.155407736
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1888690405
Short name T146
Test name
Test status
Simulation time 68072572 ps
CPU time 0.76 seconds
Started Jul 21 05:48:28 PM PDT 24
Finished Jul 21 05:48:30 PM PDT 24
Peak memory 200248 kb
Host smart-07efc9ae-86ea-4d5a-9c6f-016e1fd7c3b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888690405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1888690405
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.548007094
Short name T441
Test name
Test status
Simulation time 1909286731 ps
CPU time 6.9 seconds
Started Jul 21 05:48:25 PM PDT 24
Finished Jul 21 05:48:32 PM PDT 24
Peak memory 217324 kb
Host smart-8c6958f6-6c8b-4414-b0ec-6ddf58e42471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548007094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.548007094
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2794495895
Short name T493
Test name
Test status
Simulation time 244198073 ps
CPU time 1.27 seconds
Started Jul 21 05:48:26 PM PDT 24
Finished Jul 21 05:48:27 PM PDT 24
Peak memory 217600 kb
Host smart-4457f129-7c81-4440-b555-39b173bcfc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794495895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2794495895
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3701286736
Short name T504
Test name
Test status
Simulation time 140659181 ps
CPU time 0.82 seconds
Started Jul 21 05:48:26 PM PDT 24
Finished Jul 21 05:48:28 PM PDT 24
Peak memory 200216 kb
Host smart-fc3f18c4-d2a8-4902-aecb-e6ccecc8abbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701286736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3701286736
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1023191866
Short name T373
Test name
Test status
Simulation time 883448775 ps
CPU time 4.54 seconds
Started Jul 21 05:48:26 PM PDT 24
Finished Jul 21 05:48:31 PM PDT 24
Peak memory 200772 kb
Host smart-02df2a52-fb6e-4a7d-a64e-e77029df8aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023191866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1023191866
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1434714627
Short name T466
Test name
Test status
Simulation time 114526255 ps
CPU time 0.99 seconds
Started Jul 21 05:48:27 PM PDT 24
Finished Jul 21 05:48:29 PM PDT 24
Peak memory 200460 kb
Host smart-6e6bf002-6577-4704-aff2-83ed9d1749ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434714627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1434714627
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1724660032
Short name T361
Test name
Test status
Simulation time 193117758 ps
CPU time 1.33 seconds
Started Jul 21 05:48:25 PM PDT 24
Finished Jul 21 05:48:27 PM PDT 24
Peak memory 200684 kb
Host smart-c55768c2-01a5-4cc0-9bed-9502d46d5798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724660032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1724660032
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3486737884
Short name T258
Test name
Test status
Simulation time 6759750885 ps
CPU time 21.86 seconds
Started Jul 21 05:48:26 PM PDT 24
Finished Jul 21 05:48:48 PM PDT 24
Peak memory 200796 kb
Host smart-fd36d491-a409-480f-8863-8eefdac6101c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486737884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3486737884
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1766485842
Short name T406
Test name
Test status
Simulation time 158498738 ps
CPU time 1.9 seconds
Started Jul 21 05:48:26 PM PDT 24
Finished Jul 21 05:48:28 PM PDT 24
Peak memory 200476 kb
Host smart-ddcbcd19-62b7-47c5-a801-79012cc4280e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766485842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1766485842
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.4272256418
Short name T210
Test name
Test status
Simulation time 104695549 ps
CPU time 0.89 seconds
Started Jul 21 05:48:25 PM PDT 24
Finished Jul 21 05:48:26 PM PDT 24
Peak memory 200496 kb
Host smart-0a04ea49-3f2e-4379-9a41-dcc2c6b989d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272256418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.4272256418
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3025786642
Short name T225
Test name
Test status
Simulation time 65201533 ps
CPU time 0.76 seconds
Started Jul 21 05:48:31 PM PDT 24
Finished Jul 21 05:48:33 PM PDT 24
Peak memory 200216 kb
Host smart-1dc9edda-4a19-446b-b527-888ce29b2997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025786642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3025786642
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1519124844
Short name T336
Test name
Test status
Simulation time 1226535516 ps
CPU time 6 seconds
Started Jul 21 05:48:32 PM PDT 24
Finished Jul 21 05:48:38 PM PDT 24
Peak memory 216888 kb
Host smart-5e942385-8e2b-40c3-88e1-fc980035f9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519124844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1519124844
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.318907790
Short name T396
Test name
Test status
Simulation time 244625543 ps
CPU time 1.07 seconds
Started Jul 21 05:48:31 PM PDT 24
Finished Jul 21 05:48:33 PM PDT 24
Peak memory 217516 kb
Host smart-e9fd4e15-7b25-4cd2-82a2-f3d70cc419b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318907790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.318907790
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2725845133
Short name T19
Test name
Test status
Simulation time 157698764 ps
CPU time 0.96 seconds
Started Jul 21 05:48:34 PM PDT 24
Finished Jul 21 05:48:35 PM PDT 24
Peak memory 200252 kb
Host smart-f3955546-e514-47c0-8255-678e4c76796c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725845133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2725845133
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1419880980
Short name T187
Test name
Test status
Simulation time 1102582378 ps
CPU time 5.21 seconds
Started Jul 21 05:48:32 PM PDT 24
Finished Jul 21 05:48:37 PM PDT 24
Peak memory 200728 kb
Host smart-3e2e2102-5aad-4369-a38b-360a78d49338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419880980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1419880980
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3458579693
Short name T421
Test name
Test status
Simulation time 101607713 ps
CPU time 0.96 seconds
Started Jul 21 05:48:31 PM PDT 24
Finished Jul 21 05:48:32 PM PDT 24
Peak memory 200464 kb
Host smart-3282fad5-3fe2-43f1-bd05-cc1017238332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458579693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3458579693
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3504745468
Short name T24
Test name
Test status
Simulation time 114824247 ps
CPU time 1.17 seconds
Started Jul 21 05:48:33 PM PDT 24
Finished Jul 21 05:48:34 PM PDT 24
Peak memory 200656 kb
Host smart-f09c8c3d-0256-4823-9f38-dacc991bb1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504745468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3504745468
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2376036725
Short name T529
Test name
Test status
Simulation time 133282632 ps
CPU time 1.4 seconds
Started Jul 21 05:48:33 PM PDT 24
Finished Jul 21 05:48:35 PM PDT 24
Peak memory 200456 kb
Host smart-d80ae2e6-7eb2-42b8-b9df-f3570a015e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376036725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2376036725
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3434096031
Short name T153
Test name
Test status
Simulation time 344202190 ps
CPU time 2.32 seconds
Started Jul 21 05:48:31 PM PDT 24
Finished Jul 21 05:48:34 PM PDT 24
Peak memory 200428 kb
Host smart-cfe24ea4-02cc-4ea3-bef8-fad5fd3ded1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434096031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3434096031
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.4101747582
Short name T375
Test name
Test status
Simulation time 145576354 ps
CPU time 1.13 seconds
Started Jul 21 05:48:31 PM PDT 24
Finished Jul 21 05:48:33 PM PDT 24
Peak memory 200428 kb
Host smart-bc46b91b-e80f-4546-8827-39d6f91effd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101747582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.4101747582
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.580327713
Short name T142
Test name
Test status
Simulation time 69440236 ps
CPU time 0.78 seconds
Started Jul 21 05:48:38 PM PDT 24
Finished Jul 21 05:48:39 PM PDT 24
Peak memory 200316 kb
Host smart-107a5c99-efd7-40f3-8ebe-fd6c8c717def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580327713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.580327713
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4036874941
Short name T185
Test name
Test status
Simulation time 1883138419 ps
CPU time 7.63 seconds
Started Jul 21 05:48:39 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 217792 kb
Host smart-ae6da76e-77cc-485a-b1da-f8c8a8500ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036874941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4036874941
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2983247264
Short name T160
Test name
Test status
Simulation time 243158057 ps
CPU time 1.05 seconds
Started Jul 21 05:48:37 PM PDT 24
Finished Jul 21 05:48:39 PM PDT 24
Peak memory 217436 kb
Host smart-fd269989-cbda-466a-9bb9-3006a2443dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983247264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2983247264
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3464717389
Short name T322
Test name
Test status
Simulation time 185489024 ps
CPU time 0.9 seconds
Started Jul 21 05:48:38 PM PDT 24
Finished Jul 21 05:48:40 PM PDT 24
Peak memory 200244 kb
Host smart-461097a1-a810-4e16-becf-637280555233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464717389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3464717389
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3595376838
Short name T30
Test name
Test status
Simulation time 1460716048 ps
CPU time 5.47 seconds
Started Jul 21 05:48:38 PM PDT 24
Finished Jul 21 05:48:44 PM PDT 24
Peak memory 200772 kb
Host smart-60f1739c-b184-441d-a91a-924f21a6efcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595376838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3595376838
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3161967172
Short name T234
Test name
Test status
Simulation time 148194663 ps
CPU time 1.16 seconds
Started Jul 21 05:48:39 PM PDT 24
Finished Jul 21 05:48:41 PM PDT 24
Peak memory 200480 kb
Host smart-2b59fa2b-1db2-4354-a6e9-37d972011fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161967172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3161967172
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.255261321
Short name T287
Test name
Test status
Simulation time 119067775 ps
CPU time 1.13 seconds
Started Jul 21 05:48:32 PM PDT 24
Finished Jul 21 05:48:33 PM PDT 24
Peak memory 200648 kb
Host smart-5512aaf6-95ac-441c-aaaf-1bab616473fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255261321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.255261321
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1424074098
Short name T100
Test name
Test status
Simulation time 937987497 ps
CPU time 4.55 seconds
Started Jul 21 05:48:40 PM PDT 24
Finished Jul 21 05:48:46 PM PDT 24
Peak memory 200904 kb
Host smart-5f1a7042-dfb1-4072-8943-5571ffc364e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424074098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1424074098
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.683679415
Short name T202
Test name
Test status
Simulation time 152866646 ps
CPU time 1.75 seconds
Started Jul 21 05:48:37 PM PDT 24
Finished Jul 21 05:48:40 PM PDT 24
Peak memory 200500 kb
Host smart-3c6ecd34-ef82-4f9f-968e-8d0dda9cad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683679415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.683679415
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1912080005
Short name T500
Test name
Test status
Simulation time 96271675 ps
CPU time 0.9 seconds
Started Jul 21 05:48:38 PM PDT 24
Finished Jul 21 05:48:40 PM PDT 24
Peak memory 200456 kb
Host smart-0cb25788-f12f-412e-a42b-12dcbb59c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912080005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1912080005
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3983066878
Short name T26
Test name
Test status
Simulation time 59197203 ps
CPU time 0.76 seconds
Started Jul 21 05:48:42 PM PDT 24
Finished Jul 21 05:48:43 PM PDT 24
Peak memory 200252 kb
Host smart-7dea0e93-fa43-4e1f-bc7b-07d43799e86e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983066878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3983066878
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2191301002
Short name T58
Test name
Test status
Simulation time 1909673693 ps
CPU time 8.12 seconds
Started Jul 21 05:48:37 PM PDT 24
Finished Jul 21 05:48:46 PM PDT 24
Peak memory 217824 kb
Host smart-b65c633a-19a2-4518-a6ce-a8c750260a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191301002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2191301002
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1841769501
Short name T178
Test name
Test status
Simulation time 243956250 ps
CPU time 1.15 seconds
Started Jul 21 05:48:38 PM PDT 24
Finished Jul 21 05:48:41 PM PDT 24
Peak memory 217520 kb
Host smart-3573920d-deb6-4ffe-bb6b-62cebd5b9e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841769501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1841769501
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.299527095
Short name T245
Test name
Test status
Simulation time 171159522 ps
CPU time 0.87 seconds
Started Jul 21 05:48:41 PM PDT 24
Finished Jul 21 05:48:43 PM PDT 24
Peak memory 200244 kb
Host smart-ab7f99ce-7de3-47f5-a8fd-13090378f6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299527095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.299527095
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2282748637
Short name T515
Test name
Test status
Simulation time 1102377473 ps
CPU time 5.2 seconds
Started Jul 21 05:48:40 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 200812 kb
Host smart-5b206b20-f1e7-4e82-8fa1-15ed18fa1916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282748637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2282748637
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3635081794
Short name T25
Test name
Test status
Simulation time 98204781 ps
CPU time 1.01 seconds
Started Jul 21 05:48:40 PM PDT 24
Finished Jul 21 05:48:42 PM PDT 24
Peak memory 199984 kb
Host smart-0bc0aad5-2f1d-40b1-ae6b-5030c8a89db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635081794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3635081794
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2694697247
Short name T325
Test name
Test status
Simulation time 116107603 ps
CPU time 1.18 seconds
Started Jul 21 05:48:39 PM PDT 24
Finished Jul 21 05:48:41 PM PDT 24
Peak memory 200656 kb
Host smart-7ee9ef06-14f6-42a7-a46d-b583a99f7dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694697247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2694697247
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.4213124184
Short name T154
Test name
Test status
Simulation time 1734716458 ps
CPU time 7.16 seconds
Started Jul 21 05:48:41 PM PDT 24
Finished Jul 21 05:48:49 PM PDT 24
Peak memory 200700 kb
Host smart-6d403ef5-74c0-4ef8-b485-214a2c65bd12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213124184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.4213124184
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4098190190
Short name T455
Test name
Test status
Simulation time 137741249 ps
CPU time 1.55 seconds
Started Jul 21 05:48:39 PM PDT 24
Finished Jul 21 05:48:41 PM PDT 24
Peak memory 208680 kb
Host smart-f444c65c-c192-479f-a060-6de1fabeacbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098190190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4098190190
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.777620036
Short name T427
Test name
Test status
Simulation time 166275046 ps
CPU time 1.25 seconds
Started Jul 21 05:48:37 PM PDT 24
Finished Jul 21 05:48:39 PM PDT 24
Peak memory 200608 kb
Host smart-7d34847e-fc20-445e-b98e-6bddb58d8877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777620036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.777620036
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3519511490
Short name T242
Test name
Test status
Simulation time 71370139 ps
CPU time 0.77 seconds
Started Jul 21 05:46:50 PM PDT 24
Finished Jul 21 05:46:51 PM PDT 24
Peak memory 200292 kb
Host smart-3f988fd3-b75b-4537-8844-82f9c9844b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519511490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3519511490
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4117324849
Short name T37
Test name
Test status
Simulation time 1226162306 ps
CPU time 6.25 seconds
Started Jul 21 05:46:43 PM PDT 24
Finished Jul 21 05:46:50 PM PDT 24
Peak memory 221564 kb
Host smart-03db5601-bfe3-405c-982a-19c23f578b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117324849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4117324849
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4290280531
Short name T485
Test name
Test status
Simulation time 243901533 ps
CPU time 1.12 seconds
Started Jul 21 05:46:50 PM PDT 24
Finished Jul 21 05:46:52 PM PDT 24
Peak memory 217388 kb
Host smart-4a2d67cc-2873-48fd-9ba5-a3b485420b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290280531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4290280531
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1355246000
Short name T374
Test name
Test status
Simulation time 84495706 ps
CPU time 0.74 seconds
Started Jul 21 05:46:43 PM PDT 24
Finished Jul 21 05:46:44 PM PDT 24
Peak memory 200244 kb
Host smart-5dce8876-1ff2-46f5-aa6f-73a65f3a621b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355246000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1355246000
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1816339862
Short name T379
Test name
Test status
Simulation time 836005781 ps
CPU time 4.16 seconds
Started Jul 21 05:46:40 PM PDT 24
Finished Jul 21 05:46:45 PM PDT 24
Peak memory 200708 kb
Host smart-209583e3-99a8-4c73-93bd-d26c8bc2b697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816339862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1816339862
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3040760430
Short name T69
Test name
Test status
Simulation time 16534329950 ps
CPU time 30.95 seconds
Started Jul 21 05:46:51 PM PDT 24
Finished Jul 21 05:47:22 PM PDT 24
Peak memory 218336 kb
Host smart-06b2e6ec-de7a-4064-860b-df6138b0856a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040760430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3040760430
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.564613181
Short name T284
Test name
Test status
Simulation time 181037734 ps
CPU time 1.18 seconds
Started Jul 21 05:46:43 PM PDT 24
Finished Jul 21 05:46:45 PM PDT 24
Peak memory 200464 kb
Host smart-e1ed0370-956c-40ba-a644-f767309a0960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564613181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.564613181
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2292312394
Short name T443
Test name
Test status
Simulation time 122284288 ps
CPU time 1.2 seconds
Started Jul 21 05:46:43 PM PDT 24
Finished Jul 21 05:46:45 PM PDT 24
Peak memory 200696 kb
Host smart-47da5bc5-ff18-42e1-97c2-3de33f416b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292312394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2292312394
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.554411993
Short name T81
Test name
Test status
Simulation time 1549957054 ps
CPU time 5.75 seconds
Started Jul 21 05:46:49 PM PDT 24
Finished Jul 21 05:46:55 PM PDT 24
Peak memory 200752 kb
Host smart-2d19c511-7bf6-4fb0-811c-38e6ee17fa8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554411993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.554411993
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1500475390
Short name T474
Test name
Test status
Simulation time 345413531 ps
CPU time 2.18 seconds
Started Jul 21 05:46:43 PM PDT 24
Finished Jul 21 05:46:46 PM PDT 24
Peak memory 200472 kb
Host smart-1a8d997c-e329-4332-89ee-def20034cfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500475390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1500475390
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3354613770
Short name T127
Test name
Test status
Simulation time 220317299 ps
CPU time 1.35 seconds
Started Jul 21 05:46:44 PM PDT 24
Finished Jul 21 05:46:45 PM PDT 24
Peak memory 200448 kb
Host smart-ec5fbe58-cc61-4524-8b90-5ccf9437a077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354613770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3354613770
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3134874969
Short name T395
Test name
Test status
Simulation time 77938392 ps
CPU time 0.75 seconds
Started Jul 21 05:48:37 PM PDT 24
Finished Jul 21 05:48:39 PM PDT 24
Peak memory 200300 kb
Host smart-5d03a1ab-8c73-4763-8d38-62a9f76b7ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134874969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3134874969
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2766713769
Short name T378
Test name
Test status
Simulation time 2382135103 ps
CPU time 8.96 seconds
Started Jul 21 05:48:40 PM PDT 24
Finished Jul 21 05:48:50 PM PDT 24
Peak memory 217904 kb
Host smart-1741d375-8149-484b-9fec-b4314b027da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766713769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2766713769
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.897040253
Short name T274
Test name
Test status
Simulation time 244161364 ps
CPU time 1.09 seconds
Started Jul 21 05:48:38 PM PDT 24
Finished Jul 21 05:48:40 PM PDT 24
Peak memory 217432 kb
Host smart-af237fcc-3336-4fe7-988b-a05b6fdc122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897040253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.897040253
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3698562014
Short name T275
Test name
Test status
Simulation time 111827137 ps
CPU time 0.81 seconds
Started Jul 21 05:48:39 PM PDT 24
Finished Jul 21 05:48:41 PM PDT 24
Peak memory 200316 kb
Host smart-f3e69d4c-a275-4d2d-bde3-039221ec5de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698562014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3698562014
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3329754004
Short name T79
Test name
Test status
Simulation time 705116176 ps
CPU time 4.15 seconds
Started Jul 21 05:48:40 PM PDT 24
Finished Jul 21 05:48:45 PM PDT 24
Peak memory 200268 kb
Host smart-4a7a424b-29fd-4de1-a514-bb99b52eb82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329754004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3329754004
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2582812197
Short name T197
Test name
Test status
Simulation time 107566660 ps
CPU time 0.98 seconds
Started Jul 21 05:48:37 PM PDT 24
Finished Jul 21 05:48:38 PM PDT 24
Peak memory 200448 kb
Host smart-e73acfd9-3d5d-4e78-9121-79f3075ff986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582812197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2582812197
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3020469885
Short name T237
Test name
Test status
Simulation time 114574414 ps
CPU time 1.23 seconds
Started Jul 21 05:48:39 PM PDT 24
Finished Jul 21 05:48:41 PM PDT 24
Peak memory 200664 kb
Host smart-988af3ed-ff4c-43f1-9f35-e5c6d13121e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020469885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3020469885
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.41404806
Short name T103
Test name
Test status
Simulation time 1904546289 ps
CPU time 9.23 seconds
Started Jul 21 05:48:37 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 200768 kb
Host smart-d0e9c5a4-7ca7-4c7f-841d-d1512d322b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41404806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.41404806
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.882532407
Short name T319
Test name
Test status
Simulation time 154327349 ps
CPU time 1.95 seconds
Started Jul 21 05:48:38 PM PDT 24
Finished Jul 21 05:48:41 PM PDT 24
Peak memory 200476 kb
Host smart-660b43a0-df4c-429e-9c2c-fa32a470903c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882532407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.882532407
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.4059823364
Short name T439
Test name
Test status
Simulation time 112703887 ps
CPU time 1.01 seconds
Started Jul 21 05:48:41 PM PDT 24
Finished Jul 21 05:48:43 PM PDT 24
Peak memory 200440 kb
Host smart-000ad937-d5ff-41fb-b425-4a5082382e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059823364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4059823364
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.146627011
Short name T150
Test name
Test status
Simulation time 76027762 ps
CPU time 0.85 seconds
Started Jul 21 05:48:47 PM PDT 24
Finished Jul 21 05:48:49 PM PDT 24
Peak memory 200260 kb
Host smart-4b75b3d8-d50c-4201-a636-23adeab73387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146627011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.146627011
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1060969421
Short name T39
Test name
Test status
Simulation time 1235822563 ps
CPU time 5.57 seconds
Started Jul 21 05:48:48 PM PDT 24
Finished Jul 21 05:48:54 PM PDT 24
Peak memory 217468 kb
Host smart-8c668dd8-63ac-463b-8a22-d61a0de9bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060969421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1060969421
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2001199749
Short name T262
Test name
Test status
Simulation time 244273079 ps
CPU time 1.08 seconds
Started Jul 21 05:48:45 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 217568 kb
Host smart-47703465-0884-48f4-a03f-4210790d4f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001199749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2001199749
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2575372038
Short name T15
Test name
Test status
Simulation time 163122762 ps
CPU time 0.92 seconds
Started Jul 21 05:48:40 PM PDT 24
Finished Jul 21 05:48:42 PM PDT 24
Peak memory 200260 kb
Host smart-02e5e2c8-13b2-4c8b-a992-cbdc0e802b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575372038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2575372038
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3492894730
Short name T445
Test name
Test status
Simulation time 1045370824 ps
CPU time 5.05 seconds
Started Jul 21 05:48:40 PM PDT 24
Finished Jul 21 05:48:46 PM PDT 24
Peak memory 200740 kb
Host smart-4f460099-88da-44f3-be80-24dcd1b10fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492894730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3492894730
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2492728752
Short name T174
Test name
Test status
Simulation time 164111228 ps
CPU time 1.14 seconds
Started Jul 21 05:48:49 PM PDT 24
Finished Jul 21 05:48:51 PM PDT 24
Peak memory 200336 kb
Host smart-16795a14-d75b-4d78-9d1f-042e42535e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492728752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2492728752
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1408829813
Short name T331
Test name
Test status
Simulation time 111365077 ps
CPU time 1.18 seconds
Started Jul 21 05:48:39 PM PDT 24
Finished Jul 21 05:48:42 PM PDT 24
Peak memory 200668 kb
Host smart-1bb9e1bd-f383-4416-b4e0-dfa7c1b8d0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408829813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1408829813
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2616480497
Short name T348
Test name
Test status
Simulation time 8469262345 ps
CPU time 28.6 seconds
Started Jul 21 05:48:51 PM PDT 24
Finished Jul 21 05:49:20 PM PDT 24
Peak memory 200684 kb
Host smart-87212d9f-0b43-44a4-af51-13a977c8f1db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616480497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2616480497
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2782611654
Short name T129
Test name
Test status
Simulation time 451157723 ps
CPU time 2.38 seconds
Started Jul 21 05:48:48 PM PDT 24
Finished Jul 21 05:48:51 PM PDT 24
Peak memory 200372 kb
Host smart-3b56f1ac-6706-4376-929a-327e54248473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782611654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2782611654
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3921431367
Short name T326
Test name
Test status
Simulation time 89773707 ps
CPU time 0.87 seconds
Started Jul 21 05:48:38 PM PDT 24
Finished Jul 21 05:48:40 PM PDT 24
Peak memory 200360 kb
Host smart-75ce32f6-b3e9-49ad-ab13-b31113ed0de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921431367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3921431367
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.566668014
Short name T291
Test name
Test status
Simulation time 96951627 ps
CPU time 0.83 seconds
Started Jul 21 05:48:48 PM PDT 24
Finished Jul 21 05:48:50 PM PDT 24
Peak memory 200320 kb
Host smart-cd3f4a77-6bd8-4050-85f5-8216cf5a0c9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566668014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.566668014
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1465044983
Short name T490
Test name
Test status
Simulation time 2356973596 ps
CPU time 7.75 seconds
Started Jul 21 05:48:48 PM PDT 24
Finished Jul 21 05:48:56 PM PDT 24
Peak memory 217868 kb
Host smart-8ac6374c-30d1-4e46-a427-804006d6672e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465044983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1465044983
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2573753911
Short name T488
Test name
Test status
Simulation time 245457342 ps
CPU time 1.08 seconds
Started Jul 21 05:48:46 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 217484 kb
Host smart-84d44dae-7342-49d3-b11a-a573b97f5443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573753911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2573753911
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2704862609
Short name T392
Test name
Test status
Simulation time 231731787 ps
CPU time 0.9 seconds
Started Jul 21 05:48:47 PM PDT 24
Finished Jul 21 05:48:48 PM PDT 24
Peak memory 200288 kb
Host smart-f134300f-279e-45f1-b91d-43d8f5263db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704862609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2704862609
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.4204520495
Short name T105
Test name
Test status
Simulation time 931037807 ps
CPU time 4.73 seconds
Started Jul 21 05:48:50 PM PDT 24
Finished Jul 21 05:48:55 PM PDT 24
Peak memory 200620 kb
Host smart-1851d38f-4fd9-4abb-a765-902fe92c8a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204520495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.4204520495
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.831953967
Short name T518
Test name
Test status
Simulation time 105451050 ps
CPU time 0.98 seconds
Started Jul 21 05:48:50 PM PDT 24
Finished Jul 21 05:48:51 PM PDT 24
Peak memory 200632 kb
Host smart-b1c579d1-f741-4d91-8dc6-b771068149c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831953967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.831953967
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3157481420
Short name T207
Test name
Test status
Simulation time 199539520 ps
CPU time 1.43 seconds
Started Jul 21 05:48:48 PM PDT 24
Finished Jul 21 05:48:49 PM PDT 24
Peak memory 200664 kb
Host smart-a481d5ec-daee-47ba-92d7-a18bac2b5730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157481420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3157481420
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1300683369
Short name T383
Test name
Test status
Simulation time 7130252808 ps
CPU time 27.29 seconds
Started Jul 21 05:48:49 PM PDT 24
Finished Jul 21 05:49:17 PM PDT 24
Peak memory 209156 kb
Host smart-419c8a03-43cf-4e9b-a3cd-bf3e8fed2351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300683369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1300683369
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.668358395
Short name T128
Test name
Test status
Simulation time 478500538 ps
CPU time 2.46 seconds
Started Jul 21 05:48:49 PM PDT 24
Finished Jul 21 05:48:52 PM PDT 24
Peak memory 208552 kb
Host smart-d8037df0-b7af-4ba3-849d-c7e7e1f0575e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668358395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.668358395
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4036317863
Short name T167
Test name
Test status
Simulation time 64771981 ps
CPU time 0.78 seconds
Started Jul 21 05:48:48 PM PDT 24
Finished Jul 21 05:48:49 PM PDT 24
Peak memory 200432 kb
Host smart-7e917d9d-8742-4f28-8787-af1f67f8df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036317863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4036317863
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1543564029
Short name T214
Test name
Test status
Simulation time 61540355 ps
CPU time 0.71 seconds
Started Jul 21 05:48:46 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 200280 kb
Host smart-f8a1d48e-cdeb-46fb-af33-90f82c328b13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543564029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1543564029
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.164587901
Short name T279
Test name
Test status
Simulation time 2353766424 ps
CPU time 8.14 seconds
Started Jul 21 05:48:47 PM PDT 24
Finished Jul 21 05:48:56 PM PDT 24
Peak memory 221800 kb
Host smart-57f8586c-8ba4-4552-ade3-bd9201c4fa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164587901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.164587901
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.764328158
Short name T251
Test name
Test status
Simulation time 244830897 ps
CPU time 1.03 seconds
Started Jul 21 05:48:50 PM PDT 24
Finished Jul 21 05:48:51 PM PDT 24
Peak memory 217400 kb
Host smart-5a6a5e13-9c3f-4a31-8976-511840fb63c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764328158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.764328158
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1628921507
Short name T282
Test name
Test status
Simulation time 77942441 ps
CPU time 0.78 seconds
Started Jul 21 05:48:47 PM PDT 24
Finished Jul 21 05:48:48 PM PDT 24
Peak memory 200260 kb
Host smart-7d911cf2-aec0-4267-9ff2-5626d51b1fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628921507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1628921507
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3096731303
Short name T496
Test name
Test status
Simulation time 922922752 ps
CPU time 4.62 seconds
Started Jul 21 05:48:45 PM PDT 24
Finished Jul 21 05:48:50 PM PDT 24
Peak memory 200832 kb
Host smart-20a3206d-ef9e-4704-a88a-ba5c002416d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096731303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3096731303
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3494910836
Short name T332
Test name
Test status
Simulation time 183457504 ps
CPU time 1.14 seconds
Started Jul 21 05:48:45 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 200500 kb
Host smart-6a61654c-d3d0-4832-995a-8d6e681fb025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494910836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3494910836
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3447560336
Short name T264
Test name
Test status
Simulation time 112820592 ps
CPU time 1.22 seconds
Started Jul 21 05:48:46 PM PDT 24
Finished Jul 21 05:48:48 PM PDT 24
Peak memory 200620 kb
Host smart-7c979fef-c97f-4c70-98ab-81c44d1303c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447560336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3447560336
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3923324563
Short name T533
Test name
Test status
Simulation time 643279331 ps
CPU time 2.6 seconds
Started Jul 21 05:48:44 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 200656 kb
Host smart-f8c13f0e-ec1d-44ba-9620-9731665f7c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923324563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3923324563
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2453880313
Short name T271
Test name
Test status
Simulation time 442000432 ps
CPU time 2.38 seconds
Started Jul 21 05:48:45 PM PDT 24
Finished Jul 21 05:48:48 PM PDT 24
Peak memory 200512 kb
Host smart-a9bd4afc-79a2-4ce2-9b4c-52795ee428cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453880313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2453880313
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.639203152
Short name T347
Test name
Test status
Simulation time 198913596 ps
CPU time 1.13 seconds
Started Jul 21 05:48:51 PM PDT 24
Finished Jul 21 05:48:53 PM PDT 24
Peak memory 200348 kb
Host smart-d0053671-767a-42b7-b19c-a413b8e23ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639203152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.639203152
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1982795160
Short name T330
Test name
Test status
Simulation time 63867059 ps
CPU time 0.75 seconds
Started Jul 21 05:48:51 PM PDT 24
Finished Jul 21 05:48:52 PM PDT 24
Peak memory 200248 kb
Host smart-3e049579-67e9-4bd0-9d12-31d27da56588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982795160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1982795160
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1756164298
Short name T46
Test name
Test status
Simulation time 1225331859 ps
CPU time 5.25 seconds
Started Jul 21 05:48:51 PM PDT 24
Finished Jul 21 05:48:57 PM PDT 24
Peak memory 217768 kb
Host smart-35e45e2e-2bfc-4169-a0cf-6a6d9e26aa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756164298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1756164298
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1168815700
Short name T244
Test name
Test status
Simulation time 244572485 ps
CPU time 1.1 seconds
Started Jul 21 05:48:52 PM PDT 24
Finished Jul 21 05:48:54 PM PDT 24
Peak memory 217508 kb
Host smart-3283f8ff-1fc5-4ec5-9ea2-a5207a3f12e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168815700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1168815700
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.870309396
Short name T313
Test name
Test status
Simulation time 74152737 ps
CPU time 0.74 seconds
Started Jul 21 05:48:55 PM PDT 24
Finished Jul 21 05:48:56 PM PDT 24
Peak memory 200256 kb
Host smart-0df646bc-04c1-45d6-aecf-3cc5a1444d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870309396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.870309396
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2219946446
Short name T236
Test name
Test status
Simulation time 1255047827 ps
CPU time 5.07 seconds
Started Jul 21 05:48:54 PM PDT 24
Finished Jul 21 05:48:59 PM PDT 24
Peak memory 200768 kb
Host smart-74758910-f606-446c-98bf-c3dc7186eb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219946446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2219946446
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3675153614
Short name T377
Test name
Test status
Simulation time 107116084 ps
CPU time 0.98 seconds
Started Jul 21 05:48:53 PM PDT 24
Finished Jul 21 05:48:55 PM PDT 24
Peak memory 200124 kb
Host smart-ba534baa-a911-4258-b132-762d80446ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675153614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3675153614
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2988261272
Short name T192
Test name
Test status
Simulation time 252361334 ps
CPU time 1.56 seconds
Started Jul 21 05:48:52 PM PDT 24
Finished Jul 21 05:48:54 PM PDT 24
Peak memory 200680 kb
Host smart-fac20d5f-1300-43e9-9e13-7b9dd9f0f3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988261272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2988261272
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2525124945
Short name T126
Test name
Test status
Simulation time 7192300148 ps
CPU time 23.83 seconds
Started Jul 21 05:48:54 PM PDT 24
Finished Jul 21 05:49:18 PM PDT 24
Peak memory 200680 kb
Host smart-51aaa3c0-ea0e-43b3-92dc-7c9c7a9bb415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525124945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2525124945
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3730764616
Short name T147
Test name
Test status
Simulation time 149945634 ps
CPU time 1.79 seconds
Started Jul 21 05:48:53 PM PDT 24
Finished Jul 21 05:48:55 PM PDT 24
Peak memory 200488 kb
Host smart-a27045f9-eaa4-4424-997c-e02dc0873951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730764616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3730764616
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2853370523
Short name T526
Test name
Test status
Simulation time 115373426 ps
CPU time 0.93 seconds
Started Jul 21 05:48:51 PM PDT 24
Finished Jul 21 05:48:52 PM PDT 24
Peak memory 200456 kb
Host smart-0f9d2e7e-98dc-4150-bf75-9d3cf067ca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853370523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2853370523
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1850609422
Short name T78
Test name
Test status
Simulation time 71358969 ps
CPU time 0.76 seconds
Started Jul 21 05:48:53 PM PDT 24
Finished Jul 21 05:48:54 PM PDT 24
Peak memory 200280 kb
Host smart-1eaf07f0-473e-4814-99c5-cca395318657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850609422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1850609422
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.396716179
Short name T376
Test name
Test status
Simulation time 1223827784 ps
CPU time 5.39 seconds
Started Jul 21 05:48:52 PM PDT 24
Finished Jul 21 05:48:58 PM PDT 24
Peak memory 220800 kb
Host smart-82e1497b-d1be-4dfd-9441-b370c1b8e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396716179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.396716179
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1209564126
Short name T51
Test name
Test status
Simulation time 243996978 ps
CPU time 1.05 seconds
Started Jul 21 05:48:52 PM PDT 24
Finished Jul 21 05:48:54 PM PDT 24
Peak memory 217524 kb
Host smart-03a3a4ce-a66a-4193-b51f-5330d0bab6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209564126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1209564126
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2299368205
Short name T403
Test name
Test status
Simulation time 197911843 ps
CPU time 0.87 seconds
Started Jul 21 05:48:52 PM PDT 24
Finished Jul 21 05:48:54 PM PDT 24
Peak memory 200244 kb
Host smart-d8ea07be-bbb3-477c-8372-efa78b683fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299368205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2299368205
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2740680617
Short name T99
Test name
Test status
Simulation time 1058995375 ps
CPU time 4.59 seconds
Started Jul 21 05:48:51 PM PDT 24
Finished Jul 21 05:48:56 PM PDT 24
Peak memory 200704 kb
Host smart-452c0f69-92dc-43f3-ba1c-992841b7e8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740680617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2740680617
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1223015156
Short name T205
Test name
Test status
Simulation time 114401553 ps
CPU time 1.12 seconds
Started Jul 21 05:48:54 PM PDT 24
Finished Jul 21 05:48:55 PM PDT 24
Peak memory 200440 kb
Host smart-4bcea4fd-4205-403e-a5a5-d78c70fb7aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223015156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1223015156
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2194690326
Short name T473
Test name
Test status
Simulation time 125735582 ps
CPU time 1.19 seconds
Started Jul 21 05:48:55 PM PDT 24
Finished Jul 21 05:48:57 PM PDT 24
Peak memory 200676 kb
Host smart-1d7f0ed5-cba5-410d-829d-3f75d2dfe463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194690326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2194690326
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.327118199
Short name T265
Test name
Test status
Simulation time 18339557303 ps
CPU time 61.92 seconds
Started Jul 21 05:48:52 PM PDT 24
Finished Jul 21 05:49:54 PM PDT 24
Peak memory 208992 kb
Host smart-7a029c2b-8135-48cb-931a-7abbfcaa74d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327118199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.327118199
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.4130491042
Short name T514
Test name
Test status
Simulation time 362245576 ps
CPU time 2.04 seconds
Started Jul 21 05:48:52 PM PDT 24
Finished Jul 21 05:48:54 PM PDT 24
Peak memory 200480 kb
Host smart-4479de39-7882-4f85-8f76-c5b3d833a1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130491042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.4130491042
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3977352791
Short name T134
Test name
Test status
Simulation time 93403346 ps
CPU time 0.91 seconds
Started Jul 21 05:48:53 PM PDT 24
Finished Jul 21 05:48:55 PM PDT 24
Peak memory 200380 kb
Host smart-6bd3897b-9f47-4a31-b167-3db9b11421b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977352791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3977352791
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.62804893
Short name T248
Test name
Test status
Simulation time 82986580 ps
CPU time 0.88 seconds
Started Jul 21 05:48:51 PM PDT 24
Finished Jul 21 05:48:53 PM PDT 24
Peak memory 200168 kb
Host smart-c331fd18-1115-4afb-a57d-fb4bc5a41261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62804893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.62804893
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4133899326
Short name T328
Test name
Test status
Simulation time 1891011167 ps
CPU time 7.13 seconds
Started Jul 21 05:48:53 PM PDT 24
Finished Jul 21 05:49:01 PM PDT 24
Peak memory 221376 kb
Host smart-d74b2a50-76c0-46a7-9729-36ef5d691644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133899326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4133899326
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3942695962
Short name T42
Test name
Test status
Simulation time 244158281 ps
CPU time 1.07 seconds
Started Jul 21 05:48:53 PM PDT 24
Finished Jul 21 05:48:54 PM PDT 24
Peak memory 217540 kb
Host smart-7c3625cd-2b6a-4152-9513-be079ebd6fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942695962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3942695962
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4228468833
Short name T309
Test name
Test status
Simulation time 93867519 ps
CPU time 0.76 seconds
Started Jul 21 05:48:52 PM PDT 24
Finished Jul 21 05:48:54 PM PDT 24
Peak memory 200252 kb
Host smart-db33416a-1f13-42b5-9d5f-d312019b7161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228468833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4228468833
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1855766888
Short name T281
Test name
Test status
Simulation time 593076445 ps
CPU time 3.29 seconds
Started Jul 21 05:48:55 PM PDT 24
Finished Jul 21 05:48:59 PM PDT 24
Peak memory 200784 kb
Host smart-4159bbb8-7ba7-48e5-ab17-1070f03a3db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855766888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1855766888
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1300054959
Short name T486
Test name
Test status
Simulation time 155538798 ps
CPU time 1.16 seconds
Started Jul 21 05:48:51 PM PDT 24
Finished Jul 21 05:48:53 PM PDT 24
Peak memory 200464 kb
Host smart-0bcaeead-d901-4f5b-8b8d-6c71109cad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300054959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1300054959
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3007652288
Short name T536
Test name
Test status
Simulation time 202825751 ps
CPU time 1.42 seconds
Started Jul 21 05:48:55 PM PDT 24
Finished Jul 21 05:48:56 PM PDT 24
Peak memory 200652 kb
Host smart-71aedef0-2edc-45cb-99d3-504fd7370cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007652288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3007652288
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.4060614243
Short name T417
Test name
Test status
Simulation time 5657613566 ps
CPU time 20.66 seconds
Started Jul 21 05:48:52 PM PDT 24
Finished Jul 21 05:49:13 PM PDT 24
Peak memory 208920 kb
Host smart-be1b5169-9e4b-4234-ad47-b3454e4fc033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060614243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4060614243
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3664704062
Short name T208
Test name
Test status
Simulation time 496908817 ps
CPU time 2.5 seconds
Started Jul 21 05:48:53 PM PDT 24
Finished Jul 21 05:48:56 PM PDT 24
Peak memory 200556 kb
Host smart-e66f5524-ec7c-40d9-83b2-30096725ec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664704062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3664704062
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1254608096
Short name T206
Test name
Test status
Simulation time 122788291 ps
CPU time 1.07 seconds
Started Jul 21 05:48:55 PM PDT 24
Finished Jul 21 05:48:56 PM PDT 24
Peak memory 200520 kb
Host smart-3dd90ed9-7cdc-48bc-ac1c-125586065fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254608096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1254608096
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.4293379415
Short name T1
Test name
Test status
Simulation time 75741011 ps
CPU time 0.85 seconds
Started Jul 21 05:48:58 PM PDT 24
Finished Jul 21 05:48:59 PM PDT 24
Peak memory 200276 kb
Host smart-d947d6cd-9507-4854-8fc2-54b6b59b072c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293379415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.4293379415
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.302659285
Short name T40
Test name
Test status
Simulation time 1894831054 ps
CPU time 7.47 seconds
Started Jul 21 05:49:04 PM PDT 24
Finished Jul 21 05:49:12 PM PDT 24
Peak memory 229952 kb
Host smart-e482693a-33bb-4ec6-8eab-81fdb3fc99b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302659285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.302659285
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.40524832
Short name T138
Test name
Test status
Simulation time 244565577 ps
CPU time 1.05 seconds
Started Jul 21 05:48:59 PM PDT 24
Finished Jul 21 05:49:01 PM PDT 24
Peak memory 217496 kb
Host smart-27dde348-9c82-4066-9e45-ae7a2155b668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40524832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.40524832
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3372683789
Short name T528
Test name
Test status
Simulation time 98732537 ps
CPU time 0.73 seconds
Started Jul 21 05:48:53 PM PDT 24
Finished Jul 21 05:48:54 PM PDT 24
Peak memory 199856 kb
Host smart-45e6c5c2-3694-4cb0-b6f4-630e64844b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372683789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3372683789
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3757184022
Short name T170
Test name
Test status
Simulation time 942824425 ps
CPU time 5.06 seconds
Started Jul 21 05:48:52 PM PDT 24
Finished Jul 21 05:48:58 PM PDT 24
Peak memory 200736 kb
Host smart-f16941ad-a8a2-49f4-83a9-ee8eca6c4758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757184022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3757184022
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1658310964
Short name T342
Test name
Test status
Simulation time 147623564 ps
CPU time 1.16 seconds
Started Jul 21 05:48:58 PM PDT 24
Finished Jul 21 05:48:59 PM PDT 24
Peak memory 200436 kb
Host smart-1faa52f5-55da-4589-ad63-07150cde41dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658310964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1658310964
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.548957354
Short name T204
Test name
Test status
Simulation time 121234916 ps
CPU time 1.19 seconds
Started Jul 21 05:48:55 PM PDT 24
Finished Jul 21 05:48:57 PM PDT 24
Peak memory 200564 kb
Host smart-3bdcd31c-b5fd-430e-929d-0802cc10880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548957354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.548957354
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.436102264
Short name T300
Test name
Test status
Simulation time 142990262 ps
CPU time 1.74 seconds
Started Jul 21 05:48:54 PM PDT 24
Finished Jul 21 05:48:56 PM PDT 24
Peak memory 200356 kb
Host smart-677249d5-729d-4475-ada7-fd41a4b0a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436102264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.436102264
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3699271269
Short name T424
Test name
Test status
Simulation time 104238046 ps
CPU time 0.91 seconds
Started Jul 21 05:48:53 PM PDT 24
Finished Jul 21 05:48:55 PM PDT 24
Peak memory 200404 kb
Host smart-a7910ad1-1020-41e4-a9bf-23829f9e0848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699271269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3699271269
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4024746592
Short name T201
Test name
Test status
Simulation time 63492523 ps
CPU time 0.78 seconds
Started Jul 21 05:49:04 PM PDT 24
Finished Jul 21 05:49:05 PM PDT 24
Peak memory 200236 kb
Host smart-44920f7c-b303-4c51-b25b-c7d13e1dd792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024746592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4024746592
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.317605067
Short name T7
Test name
Test status
Simulation time 1232706809 ps
CPU time 5.92 seconds
Started Jul 21 05:48:57 PM PDT 24
Finished Jul 21 05:49:04 PM PDT 24
Peak memory 216832 kb
Host smart-0a8b0368-aa95-4417-8fac-37085caea6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317605067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.317605067
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.425089534
Short name T293
Test name
Test status
Simulation time 244356688 ps
CPU time 1.09 seconds
Started Jul 21 05:48:58 PM PDT 24
Finished Jul 21 05:49:00 PM PDT 24
Peak memory 217512 kb
Host smart-40953e39-0a87-4207-812d-2353a8e1fff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425089534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.425089534
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1457953566
Short name T458
Test name
Test status
Simulation time 144956731 ps
CPU time 0.81 seconds
Started Jul 21 05:49:08 PM PDT 24
Finished Jul 21 05:49:09 PM PDT 24
Peak memory 200276 kb
Host smart-1d6d35fe-aef1-4849-8891-e9264cb192ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457953566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1457953566
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3220941405
Short name T398
Test name
Test status
Simulation time 1324871180 ps
CPU time 5.87 seconds
Started Jul 21 05:48:58 PM PDT 24
Finished Jul 21 05:49:05 PM PDT 24
Peak memory 200732 kb
Host smart-8876ff9a-5bae-4dda-b4c1-b4989dcc1f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220941405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3220941405
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.918168213
Short name T169
Test name
Test status
Simulation time 105330549 ps
CPU time 0.95 seconds
Started Jul 21 05:48:59 PM PDT 24
Finished Jul 21 05:49:00 PM PDT 24
Peak memory 200520 kb
Host smart-761f3aa4-02a2-4b12-9729-07c5effb5d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918168213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.918168213
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2298584379
Short name T489
Test name
Test status
Simulation time 193198555 ps
CPU time 1.26 seconds
Started Jul 21 05:48:57 PM PDT 24
Finished Jul 21 05:48:59 PM PDT 24
Peak memory 200668 kb
Host smart-461b8a27-3964-4906-8b7f-6a532d392a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298584379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2298584379
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.54069484
Short name T464
Test name
Test status
Simulation time 1167418798 ps
CPU time 5.57 seconds
Started Jul 21 05:48:59 PM PDT 24
Finished Jul 21 05:49:05 PM PDT 24
Peak memory 200056 kb
Host smart-e87d5d21-a4e3-4ed6-a34f-378806f958e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54069484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.54069484
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3677733249
Short name T344
Test name
Test status
Simulation time 266694800 ps
CPU time 1.85 seconds
Started Jul 21 05:49:05 PM PDT 24
Finished Jul 21 05:49:08 PM PDT 24
Peak memory 200468 kb
Host smart-9f50f4a9-56f5-44dd-b3b4-fa6a4fd3afb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677733249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3677733249
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2952018994
Short name T80
Test name
Test status
Simulation time 208153830 ps
CPU time 1.28 seconds
Started Jul 21 05:48:57 PM PDT 24
Finished Jul 21 05:48:58 PM PDT 24
Peak memory 200456 kb
Host smart-5ecb4636-8125-403a-b20a-d91dcdf765df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952018994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2952018994
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.943814875
Short name T155
Test name
Test status
Simulation time 86832671 ps
CPU time 0.81 seconds
Started Jul 21 05:49:00 PM PDT 24
Finished Jul 21 05:49:02 PM PDT 24
Peak memory 200252 kb
Host smart-5332b374-88cd-46a5-bcff-e55d8005a5c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943814875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.943814875
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3390139009
Short name T477
Test name
Test status
Simulation time 1900286709 ps
CPU time 7.43 seconds
Started Jul 21 05:48:59 PM PDT 24
Finished Jul 21 05:49:07 PM PDT 24
Peak memory 217648 kb
Host smart-c4a149f7-34e9-4c0c-af58-0f57a17b65a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390139009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3390139009
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.4220888821
Short name T195
Test name
Test status
Simulation time 244363956 ps
CPU time 1.1 seconds
Started Jul 21 05:48:59 PM PDT 24
Finished Jul 21 05:49:01 PM PDT 24
Peak memory 216880 kb
Host smart-3348659a-31ca-46af-8166-adbea0288128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220888821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.4220888821
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1065987339
Short name T295
Test name
Test status
Simulation time 130778521 ps
CPU time 0.86 seconds
Started Jul 21 05:49:03 PM PDT 24
Finished Jul 21 05:49:04 PM PDT 24
Peak memory 200244 kb
Host smart-9f52b52f-abce-48e5-aab6-c0fed21690db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065987339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1065987339
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.465196029
Short name T302
Test name
Test status
Simulation time 1121920927 ps
CPU time 5.58 seconds
Started Jul 21 05:48:58 PM PDT 24
Finished Jul 21 05:49:05 PM PDT 24
Peak memory 200740 kb
Host smart-2e289659-fac2-4466-9550-8599290124cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465196029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.465196029
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1539867133
Short name T368
Test name
Test status
Simulation time 171780186 ps
CPU time 1.15 seconds
Started Jul 21 05:48:58 PM PDT 24
Finished Jul 21 05:49:00 PM PDT 24
Peak memory 200460 kb
Host smart-a7e79049-4079-4679-b8bb-87f41bc3b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539867133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1539867133
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1945673960
Short name T410
Test name
Test status
Simulation time 125734238 ps
CPU time 1.23 seconds
Started Jul 21 05:48:58 PM PDT 24
Finished Jul 21 05:49:00 PM PDT 24
Peak memory 200656 kb
Host smart-57a419ca-8589-4857-a8d2-41cfd4c538d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945673960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1945673960
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2580049770
Short name T482
Test name
Test status
Simulation time 8231148050 ps
CPU time 29.43 seconds
Started Jul 21 05:48:58 PM PDT 24
Finished Jul 21 05:49:28 PM PDT 24
Peak memory 200852 kb
Host smart-f4fe2cde-955e-4f14-bcef-6a846b8cb8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580049770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2580049770
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.542258564
Short name T416
Test name
Test status
Simulation time 330859487 ps
CPU time 2.21 seconds
Started Jul 21 05:49:05 PM PDT 24
Finished Jul 21 05:49:08 PM PDT 24
Peak memory 200484 kb
Host smart-f4c4947e-7b65-4423-a72c-1578632b8dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542258564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.542258564
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3018206528
Short name T419
Test name
Test status
Simulation time 68362753 ps
CPU time 0.75 seconds
Started Jul 21 05:46:49 PM PDT 24
Finished Jul 21 05:46:51 PM PDT 24
Peak memory 200264 kb
Host smart-f8851413-b8fd-4bcf-9ac0-bc0a8a078b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018206528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3018206528
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1120486914
Short name T34
Test name
Test status
Simulation time 2361547290 ps
CPU time 7.9 seconds
Started Jul 21 05:46:50 PM PDT 24
Finished Jul 21 05:46:58 PM PDT 24
Peak memory 217812 kb
Host smart-db706330-05f9-48b4-84e4-153cf6b25bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120486914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1120486914
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.290749490
Short name T356
Test name
Test status
Simulation time 249826247 ps
CPU time 1.01 seconds
Started Jul 21 05:46:49 PM PDT 24
Finished Jul 21 05:46:50 PM PDT 24
Peak memory 217380 kb
Host smart-830e4b0d-6435-4bcf-a422-a74b59458bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290749490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.290749490
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.260464921
Short name T369
Test name
Test status
Simulation time 104451915 ps
CPU time 0.75 seconds
Started Jul 21 05:46:53 PM PDT 24
Finished Jul 21 05:46:54 PM PDT 24
Peak memory 200192 kb
Host smart-e79e2efc-3f6f-404e-bbb3-5827fb63cbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260464921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.260464921
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1030950454
Short name T125
Test name
Test status
Simulation time 1761673423 ps
CPU time 6.72 seconds
Started Jul 21 05:46:52 PM PDT 24
Finished Jul 21 05:46:59 PM PDT 24
Peak memory 200736 kb
Host smart-c6008430-565a-4c3f-8ae5-2bb414c51004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030950454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1030950454
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4205404581
Short name T272
Test name
Test status
Simulation time 143159741 ps
CPU time 1.07 seconds
Started Jul 21 05:46:48 PM PDT 24
Finished Jul 21 05:46:50 PM PDT 24
Peak memory 200356 kb
Host smart-3e9090ce-7904-4645-be53-28a72bf9cf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205404581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4205404581
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2889830218
Short name T341
Test name
Test status
Simulation time 240575964 ps
CPU time 1.43 seconds
Started Jul 21 05:46:49 PM PDT 24
Finished Jul 21 05:46:50 PM PDT 24
Peak memory 200700 kb
Host smart-4e59d832-32de-47c5-b2bc-285fc6854233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889830218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2889830218
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3138567342
Short name T152
Test name
Test status
Simulation time 369113927 ps
CPU time 2.47 seconds
Started Jul 21 05:46:49 PM PDT 24
Finished Jul 21 05:46:52 PM PDT 24
Peak memory 200476 kb
Host smart-6deb0f90-e7ec-40d1-a0d9-bc9e04465c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138567342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3138567342
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.998479572
Short name T290
Test name
Test status
Simulation time 128955448 ps
CPU time 0.95 seconds
Started Jul 21 05:46:52 PM PDT 24
Finished Jul 21 05:46:53 PM PDT 24
Peak memory 200388 kb
Host smart-b5a2bee1-82aa-4e72-8b17-099ba6ecd751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998479572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.998479572
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.480106048
Short name T340
Test name
Test status
Simulation time 78773612 ps
CPU time 0.79 seconds
Started Jul 21 05:46:56 PM PDT 24
Finished Jul 21 05:46:58 PM PDT 24
Peak memory 200216 kb
Host smart-202047ed-5561-4476-a382-6cca690af807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480106048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.480106048
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.723734141
Short name T54
Test name
Test status
Simulation time 2165085783 ps
CPU time 7.36 seconds
Started Jul 21 05:46:56 PM PDT 24
Finished Jul 21 05:47:04 PM PDT 24
Peak memory 217012 kb
Host smart-8c044fe8-c9ed-46fe-b0b7-16c515e5e6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723734141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.723734141
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3572544058
Short name T176
Test name
Test status
Simulation time 244817536 ps
CPU time 1.18 seconds
Started Jul 21 05:46:56 PM PDT 24
Finished Jul 21 05:46:58 PM PDT 24
Peak memory 217548 kb
Host smart-2f8279dd-8895-457f-be0d-194092788882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572544058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3572544058
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1270064839
Short name T460
Test name
Test status
Simulation time 204696762 ps
CPU time 0.89 seconds
Started Jul 21 05:46:50 PM PDT 24
Finished Jul 21 05:46:51 PM PDT 24
Peak memory 200172 kb
Host smart-3b5d13fe-f0d9-49e2-886f-1d5bbb3ebcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270064839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1270064839
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.38365232
Short name T294
Test name
Test status
Simulation time 1342531631 ps
CPU time 4.92 seconds
Started Jul 21 05:46:57 PM PDT 24
Finished Jul 21 05:47:03 PM PDT 24
Peak memory 200672 kb
Host smart-1dd6edb2-e50b-44a3-8610-92a3f39ecb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38365232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.38365232
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2757085018
Short name T505
Test name
Test status
Simulation time 178692280 ps
CPU time 1.17 seconds
Started Jul 21 05:46:57 PM PDT 24
Finished Jul 21 05:46:59 PM PDT 24
Peak memory 200348 kb
Host smart-b075236b-5905-40fc-935b-ead65a8b6a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757085018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2757085018
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.269608945
Short name T520
Test name
Test status
Simulation time 112031923 ps
CPU time 1.17 seconds
Started Jul 21 05:46:50 PM PDT 24
Finished Jul 21 05:46:52 PM PDT 24
Peak memory 200688 kb
Host smart-974e816a-4259-4827-8ef5-aa7f1ea214f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269608945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.269608945
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1075933960
Short name T102
Test name
Test status
Simulation time 8297346630 ps
CPU time 26.68 seconds
Started Jul 21 05:46:56 PM PDT 24
Finished Jul 21 05:47:23 PM PDT 24
Peak memory 200836 kb
Host smart-cf255545-4410-47ee-8725-918b40103e4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075933960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1075933960
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3411805838
Short name T310
Test name
Test status
Simulation time 141735645 ps
CPU time 1.86 seconds
Started Jul 21 05:46:57 PM PDT 24
Finished Jul 21 05:46:59 PM PDT 24
Peak memory 200460 kb
Host smart-ccbf1a62-8c8a-4b0c-b56e-863853bb8f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411805838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3411805838
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1775823728
Short name T286
Test name
Test status
Simulation time 227859453 ps
CPU time 1.41 seconds
Started Jul 21 05:46:55 PM PDT 24
Finished Jul 21 05:46:57 PM PDT 24
Peak memory 200344 kb
Host smart-73712580-8d4c-482c-bf45-747269bb25e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775823728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1775823728
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3097365334
Short name T320
Test name
Test status
Simulation time 87816168 ps
CPU time 0.87 seconds
Started Jul 21 05:47:04 PM PDT 24
Finished Jul 21 05:47:06 PM PDT 24
Peak memory 200280 kb
Host smart-358a4a79-9db4-4f35-a088-3dc066ed39e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097365334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3097365334
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3932835995
Short name T31
Test name
Test status
Simulation time 1222664952 ps
CPU time 5.49 seconds
Started Jul 21 05:47:01 PM PDT 24
Finished Jul 21 05:47:07 PM PDT 24
Peak memory 216832 kb
Host smart-6c5bf726-c692-40a5-9629-48a78951696b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932835995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3932835995
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.467950625
Short name T29
Test name
Test status
Simulation time 243903940 ps
CPU time 1 seconds
Started Jul 21 05:46:59 PM PDT 24
Finished Jul 21 05:47:01 PM PDT 24
Peak memory 217468 kb
Host smart-004fa6e0-d98d-438c-8b8b-df2d72958609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467950625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.467950625
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.429941261
Short name T20
Test name
Test status
Simulation time 187457084 ps
CPU time 0.92 seconds
Started Jul 21 05:46:56 PM PDT 24
Finished Jul 21 05:46:58 PM PDT 24
Peak memory 200240 kb
Host smart-335c3da9-0d63-4f1c-8281-9aca6f80f76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429941261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.429941261
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.4097548852
Short name T448
Test name
Test status
Simulation time 976162718 ps
CPU time 4.76 seconds
Started Jul 21 05:46:56 PM PDT 24
Finished Jul 21 05:47:01 PM PDT 24
Peak memory 200628 kb
Host smart-c1889fc6-d2a6-46cc-84f0-08d3fef3d311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097548852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.4097548852
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2165130830
Short name T411
Test name
Test status
Simulation time 143662308 ps
CPU time 1.07 seconds
Started Jul 21 05:47:02 PM PDT 24
Finished Jul 21 05:47:03 PM PDT 24
Peak memory 200344 kb
Host smart-151cd970-e5b6-4b93-b06c-913770a4a0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165130830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2165130830
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.833663789
Short name T3
Test name
Test status
Simulation time 118245515 ps
CPU time 1.1 seconds
Started Jul 21 05:46:55 PM PDT 24
Finished Jul 21 05:46:56 PM PDT 24
Peak memory 200664 kb
Host smart-143ba069-c06a-4828-bfed-e10863959740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833663789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.833663789
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1813264217
Short name T354
Test name
Test status
Simulation time 12681379956 ps
CPU time 40.84 seconds
Started Jul 21 05:47:01 PM PDT 24
Finished Jul 21 05:47:42 PM PDT 24
Peak memory 200836 kb
Host smart-891aada2-8a6b-4930-abcf-4190c0d2b6d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813264217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1813264217
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.187297127
Short name T404
Test name
Test status
Simulation time 298248425 ps
CPU time 1.96 seconds
Started Jul 21 05:46:56 PM PDT 24
Finished Jul 21 05:46:58 PM PDT 24
Peak memory 208708 kb
Host smart-2eba3cba-da7b-4472-b2ab-14f56dae644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187297127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.187297127
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3622393839
Short name T365
Test name
Test status
Simulation time 63608176 ps
CPU time 0.78 seconds
Started Jul 21 05:46:56 PM PDT 24
Finished Jul 21 05:46:57 PM PDT 24
Peak memory 200436 kb
Host smart-35aad549-7b2e-4444-8a9e-0044ba30bc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622393839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3622393839
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3705175799
Short name T260
Test name
Test status
Simulation time 75368608 ps
CPU time 0.75 seconds
Started Jul 21 05:47:10 PM PDT 24
Finished Jul 21 05:47:11 PM PDT 24
Peak memory 200220 kb
Host smart-9aba41a1-5d5f-44e0-87ee-614fa6ae2197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705175799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3705175799
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2873443312
Short name T252
Test name
Test status
Simulation time 2336462184 ps
CPU time 7.54 seconds
Started Jul 21 05:47:07 PM PDT 24
Finished Jul 21 05:47:15 PM PDT 24
Peak memory 217856 kb
Host smart-627cf159-cb7e-435a-83c7-db602f290240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873443312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2873443312
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1555811053
Short name T527
Test name
Test status
Simulation time 244038920 ps
CPU time 1.04 seconds
Started Jul 21 05:47:09 PM PDT 24
Finished Jul 21 05:47:11 PM PDT 24
Peak memory 217476 kb
Host smart-5d6b3bff-f36e-4717-b6cd-eeda9dd94d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555811053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1555811053
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.638969366
Short name T461
Test name
Test status
Simulation time 110162432 ps
CPU time 0.81 seconds
Started Jul 21 05:47:02 PM PDT 24
Finished Jul 21 05:47:03 PM PDT 24
Peak memory 200252 kb
Host smart-ef0c3178-c5b7-413c-81d6-711c020ba865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638969366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.638969366
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2331025962
Short name T124
Test name
Test status
Simulation time 1811221831 ps
CPU time 6.17 seconds
Started Jul 21 05:47:01 PM PDT 24
Finished Jul 21 05:47:07 PM PDT 24
Peak memory 200676 kb
Host smart-889ad63a-bf63-4712-b6b7-72dec5f46141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331025962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2331025962
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.486869574
Short name T303
Test name
Test status
Simulation time 100331810 ps
CPU time 0.96 seconds
Started Jul 21 05:47:07 PM PDT 24
Finished Jul 21 05:47:08 PM PDT 24
Peak memory 200456 kb
Host smart-9cc1953f-98e3-4876-8e17-6c688ab12925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486869574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.486869574
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.563403653
Short name T188
Test name
Test status
Simulation time 111539225 ps
CPU time 1.21 seconds
Started Jul 21 05:47:00 PM PDT 24
Finished Jul 21 05:47:02 PM PDT 24
Peak memory 200708 kb
Host smart-c1f10caf-6812-4381-8756-2c04d68b1e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563403653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.563403653
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.515866258
Short name T324
Test name
Test status
Simulation time 6190089498 ps
CPU time 22.77 seconds
Started Jul 21 05:47:08 PM PDT 24
Finished Jul 21 05:47:31 PM PDT 24
Peak memory 209008 kb
Host smart-49e63020-39ac-48d2-bff9-ad86f69e1594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515866258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.515866258
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.526109552
Short name T5
Test name
Test status
Simulation time 359239653 ps
CPU time 2.4 seconds
Started Jul 21 05:47:08 PM PDT 24
Finished Jul 21 05:47:11 PM PDT 24
Peak memory 200424 kb
Host smart-0ad51324-3ed7-447d-b2be-8499863dfc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526109552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.526109552
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3171395694
Short name T240
Test name
Test status
Simulation time 228455929 ps
CPU time 1.42 seconds
Started Jul 21 05:47:05 PM PDT 24
Finished Jul 21 05:47:07 PM PDT 24
Peak memory 200704 kb
Host smart-df7fc682-5589-44b7-b4e8-9072bf45968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171395694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3171395694
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.311921544
Short name T278
Test name
Test status
Simulation time 85865348 ps
CPU time 0.85 seconds
Started Jul 21 05:47:15 PM PDT 24
Finished Jul 21 05:47:16 PM PDT 24
Peak memory 200260 kb
Host smart-01b30961-0d71-4e35-82d4-02d2474f8d6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311921544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.311921544
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2454459416
Short name T444
Test name
Test status
Simulation time 1231500444 ps
CPU time 5.3 seconds
Started Jul 21 05:47:15 PM PDT 24
Finished Jul 21 05:47:20 PM PDT 24
Peak memory 221668 kb
Host smart-1f8da62d-347c-4de0-899a-9e4def55bda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454459416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2454459416
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.866505028
Short name T388
Test name
Test status
Simulation time 244488876 ps
CPU time 1.07 seconds
Started Jul 21 05:47:16 PM PDT 24
Finished Jul 21 05:47:18 PM PDT 24
Peak memory 217352 kb
Host smart-51b16dd0-8126-4a6a-9ba5-8fbe8b5db4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866505028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.866505028
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.751048358
Short name T257
Test name
Test status
Simulation time 175326024 ps
CPU time 0.95 seconds
Started Jul 21 05:47:07 PM PDT 24
Finished Jul 21 05:47:08 PM PDT 24
Peak memory 200204 kb
Host smart-26e7e585-cd71-4540-85fe-bfe3d976eaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751048358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.751048358
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2110458349
Short name T11
Test name
Test status
Simulation time 1036365967 ps
CPU time 5.29 seconds
Started Jul 21 05:47:07 PM PDT 24
Finished Jul 21 05:47:13 PM PDT 24
Peak memory 200752 kb
Host smart-7d01fa75-e169-4ff6-9c27-7e599e5d8766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110458349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2110458349
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.358312712
Short name T481
Test name
Test status
Simulation time 154314473 ps
CPU time 1.12 seconds
Started Jul 21 05:47:16 PM PDT 24
Finished Jul 21 05:47:17 PM PDT 24
Peak memory 200356 kb
Host smart-88a08133-20af-49d6-9d91-fa93cb67272c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358312712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.358312712
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2677413385
Short name T364
Test name
Test status
Simulation time 116410943 ps
CPU time 1.15 seconds
Started Jul 21 05:47:08 PM PDT 24
Finished Jul 21 05:47:09 PM PDT 24
Peak memory 200648 kb
Host smart-efacbfc3-62ee-4e8c-ab64-c3571bce62c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677413385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2677413385
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3170319370
Short name T351
Test name
Test status
Simulation time 3476847188 ps
CPU time 12.39 seconds
Started Jul 21 05:47:14 PM PDT 24
Finished Jul 21 05:47:27 PM PDT 24
Peak memory 200800 kb
Host smart-5dd07da5-50f0-4aba-8f6f-a977964f2db1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170319370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3170319370
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2031961990
Short name T182
Test name
Test status
Simulation time 450325677 ps
CPU time 2.46 seconds
Started Jul 21 05:47:09 PM PDT 24
Finished Jul 21 05:47:11 PM PDT 24
Peak memory 200496 kb
Host smart-356ebd9a-3879-41e7-8263-610d60ee2997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031961990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2031961990
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1398682653
Short name T219
Test name
Test status
Simulation time 74605797 ps
CPU time 0.79 seconds
Started Jul 21 05:47:10 PM PDT 24
Finished Jul 21 05:47:11 PM PDT 24
Peak memory 200360 kb
Host smart-8f8160a1-df4b-43e7-acf4-3f153da44011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398682653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1398682653
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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