Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7529

1

T5

28

T7

18

T20

3

auto[1]

10459

1

T1

4

T2

4

T3

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5665	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6117	1			T1	2		T2	2		T3	1
reset_info_cp[2]	2737	1			T1	1		T2	1		T5	7
reset_info_cp[4]	3596	1			T1	1		T2	1		T5	10
reset_info_cp[8]	109	1			T7	1		T22	3		T75	1
reset_info_cp[16]	82	1			T7	1		T22	3		T75	1
reset_info_cp[32]	112	1			T5	1		T22	4		T25	1
reset_info_cp[64]	101	1			T5	1		T7	1		T25	1
reset_info_cp[128]	89	1			T21	1		T22	1		T36	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2944	1			T5	8		T7	18		T21	9
reset_info_cp[1]	auto[1]	2553	1			T1	1		T2	1		T5	8
reset_info_cp[2]	auto[0]	816	1			T5	3		T21	5		T22	18
reset_info_cp[2]	auto[1]	1921	1			T1	1		T2	1		T5	4
reset_info_cp[4]	auto[0]	1266	1			T5	6		T21	11		T22	37
reset_info_cp[4]	auto[1]	2330	1			T1	1		T2	1		T5	4
reset_info_cp[8]	auto[0]	37	1			T22	1		T80	1		T72	1
reset_info_cp[8]	auto[1]	72	1			T7	1		T22	2		T75	1
reset_info_cp[16]	auto[0]	37	1			T22	1		T75	1		T71	2
reset_info_cp[16]	auto[1]	45	1			T7	1		T22	2		T26	1
reset_info_cp[32]	auto[0]	38	1			T22	2		T73	1		T97	1
reset_info_cp[32]	auto[1]	74	1			T5	1		T22	2		T25	1
reset_info_cp[64]	auto[0]	40	1			T5	1		T80	1		T92	1
reset_info_cp[64]	auto[1]	61	1			T7	1		T25	1		T80	1
reset_info_cp[128]	auto[0]	36	1			T80	1		T73	1		T95	1
reset_info_cp[128]	auto[1]	53	1			T21	1		T22	1		T36	2