Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T541 /workspace/coverage/default/22.rstmgr_smoke.3534710305 Jul 22 06:57:44 PM PDT 24 Jul 22 06:57:56 PM PDT 24 220316325 ps
T542 /workspace/coverage/default/49.rstmgr_reset.114517673 Jul 22 06:58:59 PM PDT 24 Jul 22 06:59:13 PM PDT 24 2076763370 ps
T543 /workspace/coverage/default/47.rstmgr_stress_all.4252875220 Jul 22 06:59:20 PM PDT 24 Jul 22 06:59:59 PM PDT 24 6067622022 ps
T544 /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3317088200 Jul 22 06:58:29 PM PDT 24 Jul 22 06:58:36 PM PDT 24 168571649 ps
T545 /workspace/coverage/default/6.rstmgr_sw_rst.3916638451 Jul 22 06:56:53 PM PDT 24 Jul 22 06:57:08 PM PDT 24 151449186 ps
T52 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.919135858 Jul 22 06:16:32 PM PDT 24 Jul 22 06:16:33 PM PDT 24 87575635 ps
T57 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4270824753 Jul 22 06:17:00 PM PDT 24 Jul 22 06:17:03 PM PDT 24 293706747 ps
T53 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3763233754 Jul 22 06:16:26 PM PDT 24 Jul 22 06:16:28 PM PDT 24 105033817 ps
T54 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3385154711 Jul 22 06:17:04 PM PDT 24 Jul 22 06:17:07 PM PDT 24 474155710 ps
T55 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3241756616 Jul 22 06:16:34 PM PDT 24 Jul 22 06:16:36 PM PDT 24 148608765 ps
T56 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1509694018 Jul 22 06:16:58 PM PDT 24 Jul 22 06:17:01 PM PDT 24 506542809 ps
T110 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1720900254 Jul 22 06:16:46 PM PDT 24 Jul 22 06:16:48 PM PDT 24 89818224 ps
T101 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4149239293 Jul 22 06:16:56 PM PDT 24 Jul 22 06:16:57 PM PDT 24 59485072 ps
T58 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1178868927 Jul 22 06:16:29 PM PDT 24 Jul 22 06:16:30 PM PDT 24 135452713 ps
T133 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1390951907 Jul 22 06:16:26 PM PDT 24 Jul 22 06:16:32 PM PDT 24 491746591 ps
T59 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1615078702 Jul 22 06:16:35 PM PDT 24 Jul 22 06:16:36 PM PDT 24 119120521 ps
T60 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2925709278 Jul 22 06:16:48 PM PDT 24 Jul 22 06:16:51 PM PDT 24 492203521 ps
T102 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.319056717 Jul 22 06:16:47 PM PDT 24 Jul 22 06:16:50 PM PDT 24 251661549 ps
T61 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.54965023 Jul 22 06:16:54 PM PDT 24 Jul 22 06:16:56 PM PDT 24 511874031 ps
T103 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3398770079 Jul 22 06:16:50 PM PDT 24 Jul 22 06:16:51 PM PDT 24 82278025 ps
T86 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2526348288 Jul 22 06:16:37 PM PDT 24 Jul 22 06:16:41 PM PDT 24 443750213 ps
T104 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.20815260 Jul 22 06:16:29 PM PDT 24 Jul 22 06:16:31 PM PDT 24 89866534 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3628147631 Jul 22 06:16:27 PM PDT 24 Jul 22 06:16:28 PM PDT 24 66410354 ps
T105 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.393027613 Jul 22 06:16:55 PM PDT 24 Jul 22 06:16:57 PM PDT 24 152327108 ps
T547 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.227051752 Jul 22 06:16:26 PM PDT 24 Jul 22 06:16:28 PM PDT 24 119289933 ps
T87 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3452218661 Jul 22 06:16:36 PM PDT 24 Jul 22 06:16:38 PM PDT 24 100907669 ps
T114 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1197976679 Jul 22 06:16:55 PM PDT 24 Jul 22 06:16:58 PM PDT 24 493862570 ps
T88 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.614556837 Jul 22 06:16:55 PM PDT 24 Jul 22 06:16:57 PM PDT 24 173200741 ps
T89 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1757381724 Jul 22 06:17:01 PM PDT 24 Jul 22 06:17:05 PM PDT 24 220991547 ps
T548 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.90741055 Jul 22 06:16:35 PM PDT 24 Jul 22 06:16:37 PM PDT 24 106901392 ps
T90 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3141077252 Jul 22 06:17:23 PM PDT 24 Jul 22 06:17:25 PM PDT 24 113064258 ps
T549 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3628784177 Jul 22 06:16:48 PM PDT 24 Jul 22 06:16:49 PM PDT 24 69692861 ps
T550 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1390666384 Jul 22 06:16:47 PM PDT 24 Jul 22 06:16:48 PM PDT 24 97861664 ps
T106 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3818696750 Jul 22 06:16:37 PM PDT 24 Jul 22 06:16:39 PM PDT 24 128944840 ps
T107 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2247369267 Jul 22 06:16:36 PM PDT 24 Jul 22 06:16:38 PM PDT 24 79291099 ps
T108 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2630838755 Jul 22 06:16:56 PM PDT 24 Jul 22 06:16:57 PM PDT 24 118066371 ps
T91 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2719073022 Jul 22 06:16:56 PM PDT 24 Jul 22 06:16:59 PM PDT 24 293376215 ps
T109 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1895340452 Jul 22 06:16:56 PM PDT 24 Jul 22 06:16:58 PM PDT 24 59490191 ps
T134 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1350322786 Jul 22 06:17:52 PM PDT 24 Jul 22 06:17:53 PM PDT 24 90164737 ps
T551 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2436435061 Jul 22 06:16:57 PM PDT 24 Jul 22 06:16:58 PM PDT 24 69405534 ps
T552 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2811208458 Jul 22 06:16:55 PM PDT 24 Jul 22 06:16:56 PM PDT 24 175238712 ps
T111 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3268964783 Jul 22 06:16:36 PM PDT 24 Jul 22 06:16:40 PM PDT 24 169574710 ps
T130 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2802966904 Jul 22 06:16:48 PM PDT 24 Jul 22 06:16:51 PM PDT 24 497028664 ps
T553 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3755726501 Jul 22 06:16:36 PM PDT 24 Jul 22 06:16:38 PM PDT 24 74362355 ps
T554 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1924082815 Jul 22 06:16:37 PM PDT 24 Jul 22 06:16:44 PM PDT 24 1168081130 ps
T555 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.906119778 Jul 22 06:16:55 PM PDT 24 Jul 22 06:16:57 PM PDT 24 137147609 ps
T556 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3747475147 Jul 22 06:16:26 PM PDT 24 Jul 22 06:16:28 PM PDT 24 103363843 ps
T115 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2519833780 Jul 22 06:16:46 PM PDT 24 Jul 22 06:16:48 PM PDT 24 490125468 ps
T557 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2640917202 Jul 22 06:16:26 PM PDT 24 Jul 22 06:16:30 PM PDT 24 271356940 ps
T132 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4288068116 Jul 22 06:16:25 PM PDT 24 Jul 22 06:16:28 PM PDT 24 812835311 ps
T558 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3981073751 Jul 22 06:16:58 PM PDT 24 Jul 22 06:16:59 PM PDT 24 111271755 ps
T559 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1474795267 Jul 22 06:16:28 PM PDT 24 Jul 22 06:16:30 PM PDT 24 122737808 ps
T560 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4010032479 Jul 22 06:16:48 PM PDT 24 Jul 22 06:16:50 PM PDT 24 130355269 ps
T561 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1254131081 Jul 22 06:17:07 PM PDT 24 Jul 22 06:17:09 PM PDT 24 83945689 ps
T117 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3007540290 Jul 22 06:17:22 PM PDT 24 Jul 22 06:17:24 PM PDT 24 126070369 ps
T118 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2700396658 Jul 22 06:17:30 PM PDT 24 Jul 22 06:17:33 PM PDT 24 436281782 ps
T119 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3613256580 Jul 22 06:16:48 PM PDT 24 Jul 22 06:16:51 PM PDT 24 220568778 ps
T562 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1722718860 Jul 22 06:16:47 PM PDT 24 Jul 22 06:16:49 PM PDT 24 123653512 ps
T563 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.834487586 Jul 22 06:17:01 PM PDT 24 Jul 22 06:17:02 PM PDT 24 75481332 ps
T564 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3296856744 Jul 22 06:16:47 PM PDT 24 Jul 22 06:16:48 PM PDT 24 87319418 ps
T565 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2273725623 Jul 22 06:17:04 PM PDT 24 Jul 22 06:17:06 PM PDT 24 187108311 ps
T131 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.529805867 Jul 22 06:16:26 PM PDT 24 Jul 22 06:16:29 PM PDT 24 481541871 ps
T566 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2791396492 Jul 22 06:16:34 PM PDT 24 Jul 22 06:16:36 PM PDT 24 90536033 ps
T567 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.136138247 Jul 22 06:16:47 PM PDT 24 Jul 22 06:16:50 PM PDT 24 489067096 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.392750226 Jul 22 06:16:37 PM PDT 24 Jul 22 06:16:39 PM PDT 24 124409316 ps
T112 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2262063508 Jul 22 06:16:47 PM PDT 24 Jul 22 06:16:50 PM PDT 24 547742126 ps
T569 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1408052944 Jul 22 06:17:06 PM PDT 24 Jul 22 06:17:09 PM PDT 24 499616024 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1510747014 Jul 22 06:16:25 PM PDT 24 Jul 22 06:16:26 PM PDT 24 91360153 ps
T571 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2373233349 Jul 22 06:17:04 PM PDT 24 Jul 22 06:17:07 PM PDT 24 83789978 ps
T572 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.945101493 Jul 22 06:17:07 PM PDT 24 Jul 22 06:17:09 PM PDT 24 87817659 ps
T573 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3944408063 Jul 22 06:16:28 PM PDT 24 Jul 22 06:16:31 PM PDT 24 465080796 ps
T574 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1474695174 Jul 22 06:16:34 PM PDT 24 Jul 22 06:16:36 PM PDT 24 418946030 ps
T575 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.734657461 Jul 22 06:16:48 PM PDT 24 Jul 22 06:16:50 PM PDT 24 176873345 ps
T576 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2588695695 Jul 22 06:17:29 PM PDT 24 Jul 22 06:17:32 PM PDT 24 157534218 ps
T577 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.144272348 Jul 22 06:18:43 PM PDT 24 Jul 22 06:18:44 PM PDT 24 139286962 ps
T578 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3035206499 Jul 22 06:16:47 PM PDT 24 Jul 22 06:16:49 PM PDT 24 115608999 ps
T116 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3946081018 Jul 22 06:17:15 PM PDT 24 Jul 22 06:17:20 PM PDT 24 1053583874 ps
T579 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3381460644 Jul 22 06:16:56 PM PDT 24 Jul 22 06:16:58 PM PDT 24 281815251 ps
T580 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.159044027 Jul 22 06:16:32 PM PDT 24 Jul 22 06:16:36 PM PDT 24 432783859 ps
T581 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2748418168 Jul 22 06:16:35 PM PDT 24 Jul 22 06:16:37 PM PDT 24 465360290 ps
T582 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3276606319 Jul 22 06:16:32 PM PDT 24 Jul 22 06:16:34 PM PDT 24 73529212 ps
T583 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4036036745 Jul 22 06:17:04 PM PDT 24 Jul 22 06:17:06 PM PDT 24 73688114 ps
T584 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2154770673 Jul 22 06:16:29 PM PDT 24 Jul 22 06:16:32 PM PDT 24 762582777 ps
T585 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.32204204 Jul 22 06:16:26 PM PDT 24 Jul 22 06:16:27 PM PDT 24 140494553 ps
T586 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3697143230 Jul 22 06:17:05 PM PDT 24 Jul 22 06:17:09 PM PDT 24 575585748 ps
T587 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.546194538 Jul 22 06:16:36 PM PDT 24 Jul 22 06:16:38 PM PDT 24 64986845 ps
T588 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1263344025 Jul 22 06:16:37 PM PDT 24 Jul 22 06:16:41 PM PDT 24 929159345 ps
T589 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2331362524 Jul 22 06:16:38 PM PDT 24 Jul 22 06:16:39 PM PDT 24 54563221 ps
T590 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1617855148 Jul 22 06:16:47 PM PDT 24 Jul 22 06:16:49 PM PDT 24 291539141 ps
T591 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1836371099 Jul 22 06:16:28 PM PDT 24 Jul 22 06:16:30 PM PDT 24 214865323 ps
T592 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.310305785 Jul 22 06:16:28 PM PDT 24 Jul 22 06:16:31 PM PDT 24 158790544 ps
T593 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2487697550 Jul 22 06:16:47 PM PDT 24 Jul 22 06:16:49 PM PDT 24 131274884 ps
T594 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3570024799 Jul 22 06:16:24 PM PDT 24 Jul 22 06:16:26 PM PDT 24 112537451 ps
T595 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3394878948 Jul 22 06:16:47 PM PDT 24 Jul 22 06:16:50 PM PDT 24 446401464 ps
T596 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1540353350 Jul 22 06:17:07 PM PDT 24 Jul 22 06:17:10 PM PDT 24 127359402 ps
T597 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2190209822 Jul 22 06:16:55 PM PDT 24 Jul 22 06:16:59 PM PDT 24 894820053 ps
T598 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1074147984 Jul 22 06:16:48 PM PDT 24 Jul 22 06:16:50 PM PDT 24 252650793 ps
T599 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3864069185 Jul 22 06:16:58 PM PDT 24 Jul 22 06:16:59 PM PDT 24 66196781 ps
T600 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3422667779 Jul 22 06:17:07 PM PDT 24 Jul 22 06:17:09 PM PDT 24 122124977 ps
T601 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1422171733 Jul 22 06:16:27 PM PDT 24 Jul 22 06:16:34 PM PDT 24 492862079 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3966768671 Jul 22 06:16:34 PM PDT 24 Jul 22 06:16:37 PM PDT 24 356651281 ps
T603 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2636478789 Jul 22 06:16:37 PM PDT 24 Jul 22 06:16:39 PM PDT 24 116324749 ps
T604 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.681872485 Jul 22 06:16:26 PM PDT 24 Jul 22 06:16:35 PM PDT 24 1538666824 ps
T605 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2542226237 Jul 22 06:16:28 PM PDT 24 Jul 22 06:16:31 PM PDT 24 381368404 ps
T606 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2643269557 Jul 22 06:16:33 PM PDT 24 Jul 22 06:16:36 PM PDT 24 258037984 ps
T607 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.230011376 Jul 22 06:16:56 PM PDT 24 Jul 22 06:16:59 PM PDT 24 304742421 ps
T608 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2805881711 Jul 22 06:16:50 PM PDT 24 Jul 22 06:16:51 PM PDT 24 157040050 ps
T609 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2398364824 Jul 22 06:17:05 PM PDT 24 Jul 22 06:17:07 PM PDT 24 111149486 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3050809754 Jul 22 06:16:28 PM PDT 24 Jul 22 06:16:29 PM PDT 24 108195775 ps
T611 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1950840280 Jul 22 06:16:45 PM PDT 24 Jul 22 06:16:47 PM PDT 24 194732103 ps
T612 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2488103632 Jul 22 06:16:27 PM PDT 24 Jul 22 06:16:29 PM PDT 24 179785701 ps
T613 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2549779148 Jul 22 06:16:46 PM PDT 24 Jul 22 06:16:48 PM PDT 24 105499393 ps
T614 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3301457467 Jul 22 06:16:25 PM PDT 24 Jul 22 06:16:26 PM PDT 24 77617817 ps
T615 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.298409789 Jul 22 06:16:55 PM PDT 24 Jul 22 06:16:57 PM PDT 24 131021907 ps
T616 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2825641099 Jul 22 06:17:04 PM PDT 24 Jul 22 06:17:07 PM PDT 24 222858184 ps
T617 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2010988189 Jul 22 06:16:25 PM PDT 24 Jul 22 06:16:28 PM PDT 24 292691918 ps
T618 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1357889285 Jul 22 06:17:04 PM PDT 24 Jul 22 06:17:06 PM PDT 24 115190597 ps
T619 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.9362312 Jul 22 06:17:01 PM PDT 24 Jul 22 06:17:04 PM PDT 24 175532786 ps
T620 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3919540087 Jul 22 06:18:43 PM PDT 24 Jul 22 06:18:46 PM PDT 24 184743325 ps
T113 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.248751611 Jul 22 06:17:00 PM PDT 24 Jul 22 06:17:04 PM PDT 24 801376695 ps

Test location /workspace/coverage/default/26.rstmgr_smoke.129537772
Short name T9
Test name
Test status
Simulation time 199700064 ps
CPU time 1.42 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:06 PM PDT 24
Peak memory 200344 kb
Host smart-75d9c24a-3f28-4d8d-924a-7150f71d7a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129537772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.129537772
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2591585143
Short name T22
Test name
Test status
Simulation time 6644171658 ps
CPU time 30.02 seconds
Started Jul 22 06:58:03 PM PDT 24
Finished Jul 22 06:58:43 PM PDT 24
Peak memory 208680 kb
Host smart-d28137fb-6e96-4ed9-9419-5047665b17be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591585143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2591585143
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4270824753
Short name T57
Test name
Test status
Simulation time 293706747 ps
CPU time 2.32 seconds
Started Jul 22 06:17:00 PM PDT 24
Finished Jul 22 06:17:03 PM PDT 24
Peak memory 208208 kb
Host smart-4280fa25-2234-4e6f-af91-f77be4780625
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270824753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4270824753
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1137905712
Short name T24
Test name
Test status
Simulation time 362530407 ps
CPU time 2.14 seconds
Started Jul 22 06:58:18 PM PDT 24
Finished Jul 22 06:58:26 PM PDT 24
Peak memory 200232 kb
Host smart-f66fc675-6135-46c5-9074-ba81d8a4949a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137905712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1137905712
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3069837158
Short name T64
Test name
Test status
Simulation time 8338845137 ps
CPU time 15.13 seconds
Started Jul 22 06:56:41 PM PDT 24
Finished Jul 22 06:57:17 PM PDT 24
Peak memory 217188 kb
Host smart-9019c00c-6ef8-4027-bbaf-89ff5468e268
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069837158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3069837158
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3151162096
Short name T7
Test name
Test status
Simulation time 1890051872 ps
CPU time 8.42 seconds
Started Jul 22 06:57:17 PM PDT 24
Finished Jul 22 06:57:30 PM PDT 24
Peak memory 217004 kb
Host smart-f7dcc3ca-6be1-406f-b693-abdd3bd2b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151162096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3151162096
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3385154711
Short name T54
Test name
Test status
Simulation time 474155710 ps
CPU time 1.89 seconds
Started Jul 22 06:17:04 PM PDT 24
Finished Jul 22 06:17:07 PM PDT 24
Peak memory 199496 kb
Host smart-540c00ba-21c3-434d-bc04-f084988dc53e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385154711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3385154711
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3471535082
Short name T66
Test name
Test status
Simulation time 76490265 ps
CPU time 0.76 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:05 PM PDT 24
Peak memory 199928 kb
Host smart-e606a02d-f146-4181-abde-9e610d7ec712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471535082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3471535082
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2802966904
Short name T130
Test name
Test status
Simulation time 497028664 ps
CPU time 1.92 seconds
Started Jul 22 06:16:48 PM PDT 24
Finished Jul 22 06:16:51 PM PDT 24
Peak memory 200088 kb
Host smart-a7eed138-6272-4bd6-ad89-430345cd1ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802966904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2802966904
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.720824763
Short name T80
Test name
Test status
Simulation time 6062952867 ps
CPU time 21.47 seconds
Started Jul 22 06:57:20 PM PDT 24
Finished Jul 22 06:57:46 PM PDT 24
Peak memory 208668 kb
Host smart-b2359e78-7bd5-42ea-bc4c-d79fd97abfce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720824763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.720824763
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.44918627
Short name T149
Test name
Test status
Simulation time 175857008 ps
CPU time 1.22 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:55 PM PDT 24
Peak memory 200152 kb
Host smart-6a573965-eb44-4873-b904-17acf107335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44918627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.44918627
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.4281852719
Short name T28
Test name
Test status
Simulation time 1236997754 ps
CPU time 5.48 seconds
Started Jul 22 06:56:28 PM PDT 24
Finished Jul 22 06:57:02 PM PDT 24
Peak memory 217868 kb
Host smart-f087a4df-4828-40bc-9156-98e7a6f9f4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281852719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.4281852719
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2526348288
Short name T86
Test name
Test status
Simulation time 443750213 ps
CPU time 2.81 seconds
Started Jul 22 06:16:37 PM PDT 24
Finished Jul 22 06:16:41 PM PDT 24
Peak memory 208268 kb
Host smart-85a8644c-3cd4-4450-82b2-3487e3bd946a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526348288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2526348288
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1025706824
Short name T121
Test name
Test status
Simulation time 9909818141 ps
CPU time 32.06 seconds
Started Jul 22 06:57:24 PM PDT 24
Finished Jul 22 06:58:02 PM PDT 24
Peak memory 208636 kb
Host smart-f534d0bd-d4e2-4015-8232-50a5dd7baa72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025706824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1025706824
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.659597288
Short name T20
Test name
Test status
Simulation time 76037396 ps
CPU time 0.84 seconds
Started Jul 22 06:56:31 PM PDT 24
Finished Jul 22 06:56:59 PM PDT 24
Peak memory 200164 kb
Host smart-d175a2cc-940a-4544-af63-dfa7160235f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659597288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.659597288
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.499328162
Short name T44
Test name
Test status
Simulation time 1885329908 ps
CPU time 7.08 seconds
Started Jul 22 06:58:02 PM PDT 24
Finished Jul 22 06:58:19 PM PDT 24
Peak memory 217760 kb
Host smart-3c285bdd-9ebe-4883-b963-4168d3a16141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499328162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.499328162
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.20815260
Short name T104
Test name
Test status
Simulation time 89866534 ps
CPU time 1.05 seconds
Started Jul 22 06:16:29 PM PDT 24
Finished Jul 22 06:16:31 PM PDT 24
Peak memory 199932 kb
Host smart-df43cd87-e89f-4f73-8d00-b25bad659d99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20815260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same
_csr_outstanding.20815260
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.628611954
Short name T12
Test name
Test status
Simulation time 216286876 ps
CPU time 0.96 seconds
Started Jul 22 06:56:28 PM PDT 24
Finished Jul 22 06:56:58 PM PDT 24
Peak memory 199960 kb
Host smart-67834d77-ec44-49e0-b915-c0f41b70f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628611954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.628611954
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2519833780
Short name T115
Test name
Test status
Simulation time 490125468 ps
CPU time 1.89 seconds
Started Jul 22 06:16:46 PM PDT 24
Finished Jul 22 06:16:48 PM PDT 24
Peak memory 200112 kb
Host smart-2131e42b-df3f-4cf2-a348-2c1bdaf3670e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519833780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2519833780
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2262063508
Short name T112
Test name
Test status
Simulation time 547742126 ps
CPU time 1.92 seconds
Started Jul 22 06:16:47 PM PDT 24
Finished Jul 22 06:16:50 PM PDT 24
Peak memory 200044 kb
Host smart-d88d676e-965e-4ef0-a5b2-fb10afa67b86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262063508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2262063508
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.248751611
Short name T113
Test name
Test status
Simulation time 801376695 ps
CPU time 2.89 seconds
Started Jul 22 06:17:00 PM PDT 24
Finished Jul 22 06:17:04 PM PDT 24
Peak memory 200048 kb
Host smart-cfbf4c45-661c-49a7-865a-5f1432eb4b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248751611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.248751611
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2588695695
Short name T576
Test name
Test status
Simulation time 157534218 ps
CPU time 1.94 seconds
Started Jul 22 06:17:29 PM PDT 24
Finished Jul 22 06:17:32 PM PDT 24
Peak memory 200052 kb
Host smart-24cf2bf6-ec10-405d-be22-9091c6b49359
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588695695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
588695695
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.681872485
Short name T604
Test name
Test status
Simulation time 1538666824 ps
CPU time 8.42 seconds
Started Jul 22 06:16:26 PM PDT 24
Finished Jul 22 06:16:35 PM PDT 24
Peak memory 199900 kb
Host smart-8d733cc8-c309-4dca-ae6f-04ba40676308
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681872485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.681872485
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3763233754
Short name T53
Test name
Test status
Simulation time 105033817 ps
CPU time 0.81 seconds
Started Jul 22 06:16:26 PM PDT 24
Finished Jul 22 06:16:28 PM PDT 24
Peak memory 199812 kb
Host smart-2a041f69-e656-4b00-93dc-b618389b6843
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763233754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
763233754
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1474795267
Short name T559
Test name
Test status
Simulation time 122737808 ps
CPU time 1.44 seconds
Started Jul 22 06:16:28 PM PDT 24
Finished Jul 22 06:16:30 PM PDT 24
Peak memory 208308 kb
Host smart-716891e7-6746-423b-8aec-341a812e1bb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474795267 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1474795267
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.919135858
Short name T52
Test name
Test status
Simulation time 87575635 ps
CPU time 0.87 seconds
Started Jul 22 06:16:32 PM PDT 24
Finished Jul 22 06:16:33 PM PDT 24
Peak memory 199880 kb
Host smart-b947adec-666d-4d55-abda-5f392a865c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919135858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.919135858
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2010988189
Short name T617
Test name
Test status
Simulation time 292691918 ps
CPU time 2.19 seconds
Started Jul 22 06:16:25 PM PDT 24
Finished Jul 22 06:16:28 PM PDT 24
Peak memory 216268 kb
Host smart-bf1f7449-8b99-43a4-a6eb-ee99fef9ca19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010988189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2010988189
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2154770673
Short name T584
Test name
Test status
Simulation time 762582777 ps
CPU time 2.95 seconds
Started Jul 22 06:16:29 PM PDT 24
Finished Jul 22 06:16:32 PM PDT 24
Peak memory 200028 kb
Host smart-595dd80e-3574-452e-a8b0-36c9c27ed19c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154770673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2154770673
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.310305785
Short name T592
Test name
Test status
Simulation time 158790544 ps
CPU time 1.97 seconds
Started Jul 22 06:16:28 PM PDT 24
Finished Jul 22 06:16:31 PM PDT 24
Peak memory 200004 kb
Host smart-8e198921-b899-4fa3-8957-d5d41d9ebf44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310305785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.310305785
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2640917202
Short name T557
Test name
Test status
Simulation time 271356940 ps
CPU time 3.11 seconds
Started Jul 22 06:16:26 PM PDT 24
Finished Jul 22 06:16:30 PM PDT 24
Peak memory 199952 kb
Host smart-715c62ae-7dba-4352-baf2-316bad750076
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640917202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
640917202
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.227051752
Short name T547
Test name
Test status
Simulation time 119289933 ps
CPU time 0.92 seconds
Started Jul 22 06:16:26 PM PDT 24
Finished Jul 22 06:16:28 PM PDT 24
Peak memory 199868 kb
Host smart-ca35c656-757e-42f4-be74-d40d49af2657
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227051752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.227051752
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2488103632
Short name T612
Test name
Test status
Simulation time 179785701 ps
CPU time 1.19 seconds
Started Jul 22 06:16:27 PM PDT 24
Finished Jul 22 06:16:29 PM PDT 24
Peak memory 208172 kb
Host smart-95de3218-55dd-46ea-98c4-68169c37e5e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488103632 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2488103632
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3276606319
Short name T582
Test name
Test status
Simulation time 73529212 ps
CPU time 0.87 seconds
Started Jul 22 06:16:32 PM PDT 24
Finished Jul 22 06:16:34 PM PDT 24
Peak memory 199880 kb
Host smart-f71381af-a7bd-4129-894d-bbf34f361de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276606319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3276606319
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1836371099
Short name T591
Test name
Test status
Simulation time 214865323 ps
CPU time 1.42 seconds
Started Jul 22 06:16:28 PM PDT 24
Finished Jul 22 06:16:30 PM PDT 24
Peak memory 200076 kb
Host smart-65a4c320-8036-472c-839b-11a5fe31d438
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836371099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1836371099
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.159044027
Short name T580
Test name
Test status
Simulation time 432783859 ps
CPU time 2.85 seconds
Started Jul 22 06:16:32 PM PDT 24
Finished Jul 22 06:16:36 PM PDT 24
Peak memory 216232 kb
Host smart-c44cc5e9-fa8e-4c2f-9010-8db6f5ed4f85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159044027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.159044027
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4288068116
Short name T132
Test name
Test status
Simulation time 812835311 ps
CPU time 2.83 seconds
Started Jul 22 06:16:25 PM PDT 24
Finished Jul 22 06:16:28 PM PDT 24
Peak memory 200120 kb
Host smart-d82c8ac4-d797-41fc-87de-58d07f2617ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288068116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.4288068116
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2549779148
Short name T613
Test name
Test status
Simulation time 105499393 ps
CPU time 1.13 seconds
Started Jul 22 06:16:46 PM PDT 24
Finished Jul 22 06:16:48 PM PDT 24
Peak memory 208172 kb
Host smart-16e02180-7cb0-4c88-a6a6-e7b83cc1ec20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549779148 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2549779148
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3296856744
Short name T564
Test name
Test status
Simulation time 87319418 ps
CPU time 0.87 seconds
Started Jul 22 06:16:47 PM PDT 24
Finished Jul 22 06:16:48 PM PDT 24
Peak memory 199836 kb
Host smart-747e6725-327a-4d02-9795-71d0199f4d10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296856744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3296856744
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1074147984
Short name T598
Test name
Test status
Simulation time 252650793 ps
CPU time 1.65 seconds
Started Jul 22 06:16:48 PM PDT 24
Finished Jul 22 06:16:50 PM PDT 24
Peak memory 200032 kb
Host smart-3bcab667-9de7-4864-8bf1-b02072726213
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074147984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1074147984
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1617855148
Short name T590
Test name
Test status
Simulation time 291539141 ps
CPU time 2.1 seconds
Started Jul 22 06:16:47 PM PDT 24
Finished Jul 22 06:16:49 PM PDT 24
Peak memory 208200 kb
Host smart-a0ffd2e5-7ba3-4877-b2db-d8529382041d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617855148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1617855148
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2487697550
Short name T593
Test name
Test status
Simulation time 131274884 ps
CPU time 1.01 seconds
Started Jul 22 06:16:47 PM PDT 24
Finished Jul 22 06:16:49 PM PDT 24
Peak memory 200052 kb
Host smart-4850518f-f28b-4af3-9237-efa66565bc76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487697550 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2487697550
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3628784177
Short name T549
Test name
Test status
Simulation time 69692861 ps
CPU time 0.79 seconds
Started Jul 22 06:16:48 PM PDT 24
Finished Jul 22 06:16:49 PM PDT 24
Peak memory 199788 kb
Host smart-67e29b0a-52b8-44c3-9d7e-910486242282
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628784177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3628784177
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.319056717
Short name T102
Test name
Test status
Simulation time 251661549 ps
CPU time 1.68 seconds
Started Jul 22 06:16:47 PM PDT 24
Finished Jul 22 06:16:50 PM PDT 24
Peak memory 199952 kb
Host smart-9c5dae65-b59f-4190-9740-4c30b0f64d46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319056717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.319056717
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3394878948
Short name T595
Test name
Test status
Simulation time 446401464 ps
CPU time 2.78 seconds
Started Jul 22 06:16:47 PM PDT 24
Finished Jul 22 06:16:50 PM PDT 24
Peak memory 211836 kb
Host smart-69f561d9-2c6d-4e26-828c-af83ab016155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394878948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3394878948
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2811208458
Short name T552
Test name
Test status
Simulation time 175238712 ps
CPU time 1.15 seconds
Started Jul 22 06:16:55 PM PDT 24
Finished Jul 22 06:16:56 PM PDT 24
Peak memory 208144 kb
Host smart-a3c03aee-0672-4121-b59c-99e8f27aa9ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811208458 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2811208458
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3864069185
Short name T599
Test name
Test status
Simulation time 66196781 ps
CPU time 0.74 seconds
Started Jul 22 06:16:58 PM PDT 24
Finished Jul 22 06:16:59 PM PDT 24
Peak memory 199864 kb
Host smart-58a9a444-156f-4f4c-ac86-2e08cfb49e8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864069185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3864069185
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3381460644
Short name T579
Test name
Test status
Simulation time 281815251 ps
CPU time 1.66 seconds
Started Jul 22 06:16:56 PM PDT 24
Finished Jul 22 06:16:58 PM PDT 24
Peak memory 200044 kb
Host smart-2a2beacb-8fe0-493f-a11f-7550c19534ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381460644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3381460644
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1722718860
Short name T562
Test name
Test status
Simulation time 123653512 ps
CPU time 1.59 seconds
Started Jul 22 06:16:47 PM PDT 24
Finished Jul 22 06:16:49 PM PDT 24
Peak memory 208176 kb
Host smart-a3cb32e2-3d66-4cf6-b2f3-f99c16582ef6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722718860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1722718860
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1357889285
Short name T618
Test name
Test status
Simulation time 115190597 ps
CPU time 1.17 seconds
Started Jul 22 06:17:04 PM PDT 24
Finished Jul 22 06:17:06 PM PDT 24
Peak memory 208084 kb
Host smart-5f126fb0-a9a7-4727-b0ca-b6895c5334f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357889285 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1357889285
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1895340452
Short name T109
Test name
Test status
Simulation time 59490191 ps
CPU time 0.75 seconds
Started Jul 22 06:16:56 PM PDT 24
Finished Jul 22 06:16:58 PM PDT 24
Peak memory 199852 kb
Host smart-d18dd2e4-70a7-4a51-981f-edc4d66d9071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895340452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1895340452
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2630838755
Short name T108
Test name
Test status
Simulation time 118066371 ps
CPU time 1.03 seconds
Started Jul 22 06:16:56 PM PDT 24
Finished Jul 22 06:16:57 PM PDT 24
Peak memory 199952 kb
Host smart-596b2cad-d37a-4601-a895-9bbad51c7894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630838755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2630838755
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1540353350
Short name T596
Test name
Test status
Simulation time 127359402 ps
CPU time 1.63 seconds
Started Jul 22 06:17:07 PM PDT 24
Finished Jul 22 06:17:10 PM PDT 24
Peak memory 208248 kb
Host smart-8ded2fad-4517-4c86-876c-cbfa785317fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540353350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1540353350
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.614556837
Short name T88
Test name
Test status
Simulation time 173200741 ps
CPU time 1.46 seconds
Started Jul 22 06:16:55 PM PDT 24
Finished Jul 22 06:16:57 PM PDT 24
Peak memory 208316 kb
Host smart-af438cdf-f5eb-4a53-900f-7152ca049654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614556837 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.614556837
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1254131081
Short name T561
Test name
Test status
Simulation time 83945689 ps
CPU time 0.83 seconds
Started Jul 22 06:17:07 PM PDT 24
Finished Jul 22 06:17:09 PM PDT 24
Peak memory 199836 kb
Host smart-7d89453c-c80c-46eb-8841-007786565d6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254131081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1254131081
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2825641099
Short name T616
Test name
Test status
Simulation time 222858184 ps
CPU time 1.53 seconds
Started Jul 22 06:17:04 PM PDT 24
Finished Jul 22 06:17:07 PM PDT 24
Peak memory 200048 kb
Host smart-82848889-f844-4cb6-9d8f-af513925f3f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825641099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2825641099
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.9362312
Short name T619
Test name
Test status
Simulation time 175532786 ps
CPU time 2.65 seconds
Started Jul 22 06:17:01 PM PDT 24
Finished Jul 22 06:17:04 PM PDT 24
Peak memory 208196 kb
Host smart-e764beb9-cfd5-4db2-922d-aa1d76a6e04f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9362312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.9362312
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2190209822
Short name T597
Test name
Test status
Simulation time 894820053 ps
CPU time 3.3 seconds
Started Jul 22 06:16:55 PM PDT 24
Finished Jul 22 06:16:59 PM PDT 24
Peak memory 200028 kb
Host smart-46cb7cdd-afcf-486a-878c-d1831945fca1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190209822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2190209822
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.298409789
Short name T615
Test name
Test status
Simulation time 131021907 ps
CPU time 1.48 seconds
Started Jul 22 06:16:55 PM PDT 24
Finished Jul 22 06:16:57 PM PDT 24
Peak memory 208328 kb
Host smart-a939c960-db47-4c22-a73a-3ad348e7137c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298409789 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.298409789
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4149239293
Short name T101
Test name
Test status
Simulation time 59485072 ps
CPU time 0.73 seconds
Started Jul 22 06:16:56 PM PDT 24
Finished Jul 22 06:16:57 PM PDT 24
Peak memory 199872 kb
Host smart-ef82584e-cf73-4cf3-a504-6feeec819770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149239293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.4149239293
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.834487586
Short name T563
Test name
Test status
Simulation time 75481332 ps
CPU time 1.04 seconds
Started Jul 22 06:17:01 PM PDT 24
Finished Jul 22 06:17:02 PM PDT 24
Peak memory 199944 kb
Host smart-9a6cfd83-1caa-4d5f-aeeb-e2545ab4d465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834487586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.834487586
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3919540087
Short name T620
Test name
Test status
Simulation time 184743325 ps
CPU time 2.64 seconds
Started Jul 22 06:18:43 PM PDT 24
Finished Jul 22 06:18:46 PM PDT 24
Peak memory 208220 kb
Host smart-1d858aa2-2028-4bc6-9968-d092bf343638
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919540087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3919540087
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.54965023
Short name T61
Test name
Test status
Simulation time 511874031 ps
CPU time 1.89 seconds
Started Jul 22 06:16:54 PM PDT 24
Finished Jul 22 06:16:56 PM PDT 24
Peak memory 200108 kb
Host smart-c94efadc-529a-4e26-be09-1dc1a6b98ced
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54965023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.54965023
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.144272348
Short name T577
Test name
Test status
Simulation time 139286962 ps
CPU time 1.09 seconds
Started Jul 22 06:18:43 PM PDT 24
Finished Jul 22 06:18:44 PM PDT 24
Peak memory 200152 kb
Host smart-0d5d614c-44eb-4221-895d-2257031e007f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144272348 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.144272348
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4036036745
Short name T583
Test name
Test status
Simulation time 73688114 ps
CPU time 0.83 seconds
Started Jul 22 06:17:04 PM PDT 24
Finished Jul 22 06:17:06 PM PDT 24
Peak memory 199368 kb
Host smart-60609484-c183-48fc-8fe0-15885d8ac7be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036036745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.4036036745
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.945101493
Short name T572
Test name
Test status
Simulation time 87817659 ps
CPU time 0.98 seconds
Started Jul 22 06:17:07 PM PDT 24
Finished Jul 22 06:17:09 PM PDT 24
Peak memory 199924 kb
Host smart-53d14fa7-a008-421c-9200-47dc09194a82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945101493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.945101493
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2719073022
Short name T91
Test name
Test status
Simulation time 293376215 ps
CPU time 2.29 seconds
Started Jul 22 06:16:56 PM PDT 24
Finished Jul 22 06:16:59 PM PDT 24
Peak memory 208228 kb
Host smart-810cc1b4-bd1f-4f84-98b9-f40a992528d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719073022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2719073022
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3697143230
Short name T586
Test name
Test status
Simulation time 575585748 ps
CPU time 2.05 seconds
Started Jul 22 06:17:05 PM PDT 24
Finished Jul 22 06:17:09 PM PDT 24
Peak memory 200000 kb
Host smart-e8f3e0e8-cfb3-4002-b737-d50ea8ca78a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697143230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3697143230
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3981073751
Short name T558
Test name
Test status
Simulation time 111271755 ps
CPU time 0.95 seconds
Started Jul 22 06:16:58 PM PDT 24
Finished Jul 22 06:16:59 PM PDT 24
Peak memory 199988 kb
Host smart-5b795880-3d86-4e7f-be54-9deaf7bc1419
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981073751 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3981073751
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2436435061
Short name T551
Test name
Test status
Simulation time 69405534 ps
CPU time 0.83 seconds
Started Jul 22 06:16:57 PM PDT 24
Finished Jul 22 06:16:58 PM PDT 24
Peak memory 199836 kb
Host smart-9acd720c-8da0-4198-950d-a423c9e51610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436435061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2436435061
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.393027613
Short name T105
Test name
Test status
Simulation time 152327108 ps
CPU time 1.16 seconds
Started Jul 22 06:16:55 PM PDT 24
Finished Jul 22 06:16:57 PM PDT 24
Peak memory 199964 kb
Host smart-c1f0afa5-f684-4de0-8437-fb3576c92e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393027613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.393027613
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1757381724
Short name T89
Test name
Test status
Simulation time 220991547 ps
CPU time 3.29 seconds
Started Jul 22 06:17:01 PM PDT 24
Finished Jul 22 06:17:05 PM PDT 24
Peak memory 208196 kb
Host smart-baa418f2-4007-4451-b099-a2407bbc2ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757381724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1757381724
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3422667779
Short name T600
Test name
Test status
Simulation time 122124977 ps
CPU time 1.27 seconds
Started Jul 22 06:17:07 PM PDT 24
Finished Jul 22 06:17:09 PM PDT 24
Peak memory 208168 kb
Host smart-d2870b78-424c-4d9d-bb5c-b0299f42b108
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422667779 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3422667779
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1350322786
Short name T134
Test name
Test status
Simulation time 90164737 ps
CPU time 0.86 seconds
Started Jul 22 06:17:52 PM PDT 24
Finished Jul 22 06:17:53 PM PDT 24
Peak memory 199876 kb
Host smart-d5b51e6d-d394-4ce9-9daf-b7461f651e96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350322786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1350322786
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.906119778
Short name T555
Test name
Test status
Simulation time 137147609 ps
CPU time 1.38 seconds
Started Jul 22 06:16:55 PM PDT 24
Finished Jul 22 06:16:57 PM PDT 24
Peak memory 200064 kb
Host smart-c445ca87-fba8-47a0-94be-d14bd3ee555d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906119778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.906119778
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.230011376
Short name T607
Test name
Test status
Simulation time 304742421 ps
CPU time 2.14 seconds
Started Jul 22 06:16:56 PM PDT 24
Finished Jul 22 06:16:59 PM PDT 24
Peak memory 216228 kb
Host smart-8548a0bd-909f-4d68-977c-4deb98debe86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230011376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.230011376
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1509694018
Short name T56
Test name
Test status
Simulation time 506542809 ps
CPU time 2.11 seconds
Started Jul 22 06:16:58 PM PDT 24
Finished Jul 22 06:17:01 PM PDT 24
Peak memory 200048 kb
Host smart-cec796cd-5d25-41e6-a1a5-0115fc5b14ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509694018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1509694018
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2273725623
Short name T565
Test name
Test status
Simulation time 187108311 ps
CPU time 1.14 seconds
Started Jul 22 06:17:04 PM PDT 24
Finished Jul 22 06:17:06 PM PDT 24
Peak memory 210292 kb
Host smart-d03df514-afec-4536-b6a0-cdde52092dd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273725623 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2273725623
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2373233349
Short name T571
Test name
Test status
Simulation time 83789978 ps
CPU time 0.84 seconds
Started Jul 22 06:17:04 PM PDT 24
Finished Jul 22 06:17:07 PM PDT 24
Peak memory 199820 kb
Host smart-069b8db3-6682-42bb-8e65-724f7b4cb864
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373233349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2373233349
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2398364824
Short name T609
Test name
Test status
Simulation time 111149486 ps
CPU time 1.22 seconds
Started Jul 22 06:17:05 PM PDT 24
Finished Jul 22 06:17:07 PM PDT 24
Peak memory 200072 kb
Host smart-6600f439-a99e-4261-bf60-0af350fc8d15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398364824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2398364824
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1197976679
Short name T114
Test name
Test status
Simulation time 493862570 ps
CPU time 2.02 seconds
Started Jul 22 06:16:55 PM PDT 24
Finished Jul 22 06:16:58 PM PDT 24
Peak memory 200244 kb
Host smart-08aec85a-bd81-4b51-8d8a-8b0a6f2af316
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197976679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1197976679
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3747475147
Short name T556
Test name
Test status
Simulation time 103363843 ps
CPU time 1.31 seconds
Started Jul 22 06:16:26 PM PDT 24
Finished Jul 22 06:16:28 PM PDT 24
Peak memory 200024 kb
Host smart-c770cc30-c2bd-4634-892b-623b72de1b51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747475147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
747475147
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1390951907
Short name T133
Test name
Test status
Simulation time 491746591 ps
CPU time 6.04 seconds
Started Jul 22 06:16:26 PM PDT 24
Finished Jul 22 06:16:32 PM PDT 24
Peak memory 200036 kb
Host smart-fbbd571b-2c8d-4c1a-a00f-6f119dc78772
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390951907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
390951907
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1510747014
Short name T570
Test name
Test status
Simulation time 91360153 ps
CPU time 0.79 seconds
Started Jul 22 06:16:25 PM PDT 24
Finished Jul 22 06:16:26 PM PDT 24
Peak memory 199808 kb
Host smart-2b28d0ec-1379-43f6-bb5d-03e1d29d58de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510747014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
510747014
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1178868927
Short name T58
Test name
Test status
Simulation time 135452713 ps
CPU time 1.11 seconds
Started Jul 22 06:16:29 PM PDT 24
Finished Jul 22 06:16:30 PM PDT 24
Peak memory 199972 kb
Host smart-3942a8ea-e66b-4043-9876-e7e2b8557519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178868927 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1178868927
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3301457467
Short name T614
Test name
Test status
Simulation time 77617817 ps
CPU time 0.82 seconds
Started Jul 22 06:16:25 PM PDT 24
Finished Jul 22 06:16:26 PM PDT 24
Peak memory 199856 kb
Host smart-f7896247-fc0c-41b9-8b2c-cea0683358bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301457467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3301457467
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.32204204
Short name T585
Test name
Test status
Simulation time 140494553 ps
CPU time 1.02 seconds
Started Jul 22 06:16:26 PM PDT 24
Finished Jul 22 06:16:27 PM PDT 24
Peak memory 199968 kb
Host smart-530cfc65-ee86-4a64-8cab-31665c2a08a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32204204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same
_csr_outstanding.32204204
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2542226237
Short name T605
Test name
Test status
Simulation time 381368404 ps
CPU time 2.97 seconds
Started Jul 22 06:16:28 PM PDT 24
Finished Jul 22 06:16:31 PM PDT 24
Peak memory 208264 kb
Host smart-26d170b4-e5eb-4894-af63-d058b6e867a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542226237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2542226237
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.529805867
Short name T131
Test name
Test status
Simulation time 481541871 ps
CPU time 1.87 seconds
Started Jul 22 06:16:26 PM PDT 24
Finished Jul 22 06:16:29 PM PDT 24
Peak memory 200072 kb
Host smart-7862be74-a1b6-4180-b4ac-34e4df1eb1d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529805867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
529805867
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3944408063
Short name T573
Test name
Test status
Simulation time 465080796 ps
CPU time 2.49 seconds
Started Jul 22 06:16:28 PM PDT 24
Finished Jul 22 06:16:31 PM PDT 24
Peak memory 199932 kb
Host smart-af5155dd-25f8-49b8-aa40-509c5e7cdc32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944408063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
944408063
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1422171733
Short name T601
Test name
Test status
Simulation time 492862079 ps
CPU time 6.06 seconds
Started Jul 22 06:16:27 PM PDT 24
Finished Jul 22 06:16:34 PM PDT 24
Peak memory 199988 kb
Host smart-12af0abf-2943-4997-8b42-478ce7f64a86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422171733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
422171733
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3050809754
Short name T610
Test name
Test status
Simulation time 108195775 ps
CPU time 0.88 seconds
Started Jul 22 06:16:28 PM PDT 24
Finished Jul 22 06:16:29 PM PDT 24
Peak memory 199852 kb
Host smart-c0dc1c75-cc24-4c51-9261-a3487d81e784
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050809754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
050809754
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3141077252
Short name T90
Test name
Test status
Simulation time 113064258 ps
CPU time 0.95 seconds
Started Jul 22 06:17:23 PM PDT 24
Finished Jul 22 06:17:25 PM PDT 24
Peak memory 199980 kb
Host smart-9355617b-71cb-40e1-829a-2304d6b6ffbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141077252 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3141077252
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3628147631
Short name T546
Test name
Test status
Simulation time 66410354 ps
CPU time 0.76 seconds
Started Jul 22 06:16:27 PM PDT 24
Finished Jul 22 06:16:28 PM PDT 24
Peak memory 199848 kb
Host smart-c11c6d5c-db39-4779-a5f9-7584c03ebcf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628147631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3628147631
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3570024799
Short name T594
Test name
Test status
Simulation time 112537451 ps
CPU time 1.24 seconds
Started Jul 22 06:16:24 PM PDT 24
Finished Jul 22 06:16:26 PM PDT 24
Peak memory 200040 kb
Host smart-b2220c54-bea4-478e-bba7-ff927642cec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570024799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3570024799
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2700396658
Short name T118
Test name
Test status
Simulation time 436281782 ps
CPU time 2.83 seconds
Started Jul 22 06:17:30 PM PDT 24
Finished Jul 22 06:17:33 PM PDT 24
Peak memory 208188 kb
Host smart-1faa19c1-2bba-42b4-9607-e81b84d1fb25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700396658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2700396658
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1408052944
Short name T569
Test name
Test status
Simulation time 499616024 ps
CPU time 2.06 seconds
Started Jul 22 06:17:06 PM PDT 24
Finished Jul 22 06:17:09 PM PDT 24
Peak memory 200028 kb
Host smart-20f2295a-5bf9-414b-8cec-8fb2a4280133
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408052944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1408052944
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3966768671
Short name T602
Test name
Test status
Simulation time 356651281 ps
CPU time 2.4 seconds
Started Jul 22 06:16:34 PM PDT 24
Finished Jul 22 06:16:37 PM PDT 24
Peak memory 200268 kb
Host smart-b2eb0191-fe7e-47dc-afdc-4d4d79b36a57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966768671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
966768671
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1924082815
Short name T554
Test name
Test status
Simulation time 1168081130 ps
CPU time 5.42 seconds
Started Jul 22 06:16:37 PM PDT 24
Finished Jul 22 06:16:44 PM PDT 24
Peak memory 199996 kb
Host smart-c55dff80-d3cf-41ab-90eb-d43df30a2aa0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924082815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
924082815
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.90741055
Short name T548
Test name
Test status
Simulation time 106901392 ps
CPU time 0.8 seconds
Started Jul 22 06:16:35 PM PDT 24
Finished Jul 22 06:16:37 PM PDT 24
Peak memory 199784 kb
Host smart-0a2d9583-84c9-4114-b4fe-48f0e8d5c491
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90741055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.90741055
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.392750226
Short name T568
Test name
Test status
Simulation time 124409316 ps
CPU time 0.94 seconds
Started Jul 22 06:16:37 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 199948 kb
Host smart-efc18ffc-a0a8-4b71-a41f-f105dda69c5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392750226 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.392750226
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3755726501
Short name T553
Test name
Test status
Simulation time 74362355 ps
CPU time 0.86 seconds
Started Jul 22 06:16:36 PM PDT 24
Finished Jul 22 06:16:38 PM PDT 24
Peak memory 199872 kb
Host smart-9e773927-4041-4941-a614-cc4af020b157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755726501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3755726501
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3818696750
Short name T106
Test name
Test status
Simulation time 128944840 ps
CPU time 1.05 seconds
Started Jul 22 06:16:37 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 199880 kb
Host smart-642c47a2-2736-45ba-93f7-4c846f07bc85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818696750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3818696750
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3452218661
Short name T87
Test name
Test status
Simulation time 100907669 ps
CPU time 1.39 seconds
Started Jul 22 06:16:36 PM PDT 24
Finished Jul 22 06:16:38 PM PDT 24
Peak memory 199980 kb
Host smart-560a2621-00b4-467e-94ea-250819145021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452218661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3452218661
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2748418168
Short name T581
Test name
Test status
Simulation time 465360290 ps
CPU time 2.01 seconds
Started Jul 22 06:16:35 PM PDT 24
Finished Jul 22 06:16:37 PM PDT 24
Peak memory 200120 kb
Host smart-d5e5c448-6e51-44ed-b197-5f4652d6dcd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748418168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2748418168
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2636478789
Short name T603
Test name
Test status
Simulation time 116324749 ps
CPU time 0.95 seconds
Started Jul 22 06:16:37 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 199948 kb
Host smart-023f6040-2694-49fc-a411-e86143af1c48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636478789 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2636478789
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.546194538
Short name T587
Test name
Test status
Simulation time 64986845 ps
CPU time 0.81 seconds
Started Jul 22 06:16:36 PM PDT 24
Finished Jul 22 06:16:38 PM PDT 24
Peak memory 199852 kb
Host smart-fab75a0a-6c0c-4129-aa3e-74789363cea6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546194538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.546194538
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3241756616
Short name T55
Test name
Test status
Simulation time 148608765 ps
CPU time 1.18 seconds
Started Jul 22 06:16:34 PM PDT 24
Finished Jul 22 06:16:36 PM PDT 24
Peak memory 199924 kb
Host smart-7a98d626-5093-4576-b664-7414b8e9cccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241756616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3241756616
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1474695174
Short name T574
Test name
Test status
Simulation time 418946030 ps
CPU time 1.77 seconds
Started Jul 22 06:16:34 PM PDT 24
Finished Jul 22 06:16:36 PM PDT 24
Peak memory 199828 kb
Host smart-20749332-c218-4fb6-b398-732eef41c3a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474695174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1474695174
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1615078702
Short name T59
Test name
Test status
Simulation time 119120521 ps
CPU time 0.9 seconds
Started Jul 22 06:16:35 PM PDT 24
Finished Jul 22 06:16:36 PM PDT 24
Peak memory 199928 kb
Host smart-0e115c6a-e3bf-4d36-8370-8f7e087d4f3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615078702 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1615078702
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2331362524
Short name T589
Test name
Test status
Simulation time 54563221 ps
CPU time 0.74 seconds
Started Jul 22 06:16:38 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 199860 kb
Host smart-58b31092-301f-42f0-be83-ad3f43eede70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331362524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2331362524
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2247369267
Short name T107
Test name
Test status
Simulation time 79291099 ps
CPU time 1.07 seconds
Started Jul 22 06:16:36 PM PDT 24
Finished Jul 22 06:16:38 PM PDT 24
Peak memory 199940 kb
Host smart-a0afef9e-4e45-4bbb-af73-553005a3b0d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247369267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2247369267
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3268964783
Short name T111
Test name
Test status
Simulation time 169574710 ps
CPU time 2.3 seconds
Started Jul 22 06:16:36 PM PDT 24
Finished Jul 22 06:16:40 PM PDT 24
Peak memory 211364 kb
Host smart-7c1ac577-41b5-411a-94cc-8c7d61226b40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268964783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3268964783
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1263344025
Short name T588
Test name
Test status
Simulation time 929159345 ps
CPU time 2.85 seconds
Started Jul 22 06:16:37 PM PDT 24
Finished Jul 22 06:16:41 PM PDT 24
Peak memory 200084 kb
Host smart-5913ad67-79a5-4bd8-b235-5d13f67885cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263344025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1263344025
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1950840280
Short name T611
Test name
Test status
Simulation time 194732103 ps
CPU time 1.33 seconds
Started Jul 22 06:16:45 PM PDT 24
Finished Jul 22 06:16:47 PM PDT 24
Peak memory 199888 kb
Host smart-cd4c3fdf-2d6d-476c-9e96-f40d28ca6920
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950840280 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1950840280
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2791396492
Short name T566
Test name
Test status
Simulation time 90536033 ps
CPU time 0.82 seconds
Started Jul 22 06:16:34 PM PDT 24
Finished Jul 22 06:16:36 PM PDT 24
Peak memory 199884 kb
Host smart-a4edaa06-6466-40f7-9d0e-0076d235c83d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791396492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2791396492
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3398770079
Short name T103
Test name
Test status
Simulation time 82278025 ps
CPU time 1 seconds
Started Jul 22 06:16:50 PM PDT 24
Finished Jul 22 06:16:51 PM PDT 24
Peak memory 199792 kb
Host smart-1f004170-822e-45d0-a4fb-9eb234106f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398770079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3398770079
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2643269557
Short name T606
Test name
Test status
Simulation time 258037984 ps
CPU time 1.83 seconds
Started Jul 22 06:16:33 PM PDT 24
Finished Jul 22 06:16:36 PM PDT 24
Peak memory 208180 kb
Host smart-d4e21a55-ec11-4391-9dbe-32c50ddf0f12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643269557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2643269557
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3946081018
Short name T116
Test name
Test status
Simulation time 1053583874 ps
CPU time 3.17 seconds
Started Jul 22 06:17:15 PM PDT 24
Finished Jul 22 06:17:20 PM PDT 24
Peak memory 200076 kb
Host smart-a2d84aef-1d07-406a-ad68-4485c474ebad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946081018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3946081018
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3035206499
Short name T578
Test name
Test status
Simulation time 115608999 ps
CPU time 0.92 seconds
Started Jul 22 06:16:47 PM PDT 24
Finished Jul 22 06:16:49 PM PDT 24
Peak memory 199868 kb
Host smart-fb6cebcc-2dc0-43c2-8885-7514542685b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035206499 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3035206499
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1390666384
Short name T550
Test name
Test status
Simulation time 97861664 ps
CPU time 0.85 seconds
Started Jul 22 06:16:47 PM PDT 24
Finished Jul 22 06:16:48 PM PDT 24
Peak memory 199832 kb
Host smart-bb213909-44ae-4fe4-99a8-d75679174c1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390666384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1390666384
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.734657461
Short name T575
Test name
Test status
Simulation time 176873345 ps
CPU time 1.3 seconds
Started Jul 22 06:16:48 PM PDT 24
Finished Jul 22 06:16:50 PM PDT 24
Peak memory 199936 kb
Host smart-737e0272-d79b-439e-86e7-b8f73a113914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734657461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.734657461
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3007540290
Short name T117
Test name
Test status
Simulation time 126070369 ps
CPU time 1.75 seconds
Started Jul 22 06:17:22 PM PDT 24
Finished Jul 22 06:17:24 PM PDT 24
Peak memory 208256 kb
Host smart-926750a2-46be-4219-9133-4bee0ad48c31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007540290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3007540290
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2925709278
Short name T60
Test name
Test status
Simulation time 492203521 ps
CPU time 1.91 seconds
Started Jul 22 06:16:48 PM PDT 24
Finished Jul 22 06:16:51 PM PDT 24
Peak memory 200072 kb
Host smart-1909dc44-a1a6-4152-85d3-ca7ed27ce3db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925709278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2925709278
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4010032479
Short name T560
Test name
Test status
Simulation time 130355269 ps
CPU time 1.11 seconds
Started Jul 22 06:16:48 PM PDT 24
Finished Jul 22 06:16:50 PM PDT 24
Peak memory 208132 kb
Host smart-8fa30ddf-92fb-4727-b383-46d07dcddbc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010032479 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.4010032479
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1720900254
Short name T110
Test name
Test status
Simulation time 89818224 ps
CPU time 0.89 seconds
Started Jul 22 06:16:46 PM PDT 24
Finished Jul 22 06:16:48 PM PDT 24
Peak memory 199864 kb
Host smart-5b851ee7-5c96-400e-a21b-4aad9b76f5c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720900254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1720900254
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2805881711
Short name T608
Test name
Test status
Simulation time 157040050 ps
CPU time 1.18 seconds
Started Jul 22 06:16:50 PM PDT 24
Finished Jul 22 06:16:51 PM PDT 24
Peak memory 199836 kb
Host smart-8971056f-1475-4d59-accc-9fb0b7e21643
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805881711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2805881711
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3613256580
Short name T119
Test name
Test status
Simulation time 220568778 ps
CPU time 1.77 seconds
Started Jul 22 06:16:48 PM PDT 24
Finished Jul 22 06:16:51 PM PDT 24
Peak memory 208192 kb
Host smart-86e472af-9026-4d6b-a8dc-cb987352720e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613256580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3613256580
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.136138247
Short name T567
Test name
Test status
Simulation time 489067096 ps
CPU time 1.87 seconds
Started Jul 22 06:16:47 PM PDT 24
Finished Jul 22 06:16:50 PM PDT 24
Peak memory 200076 kb
Host smart-0d71809d-0ed2-48a2-8851-15eb9dd4a7f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136138247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
136138247
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.4105253422
Short name T465
Test name
Test status
Simulation time 93444071 ps
CPU time 0.83 seconds
Started Jul 22 06:56:30 PM PDT 24
Finished Jul 22 06:56:58 PM PDT 24
Peak memory 199932 kb
Host smart-20621140-f9ba-411f-9e51-d0b1321d6c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105253422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4105253422
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1936942277
Short name T430
Test name
Test status
Simulation time 1228201617 ps
CPU time 5.72 seconds
Started Jul 22 06:56:32 PM PDT 24
Finished Jul 22 06:57:04 PM PDT 24
Peak memory 217848 kb
Host smart-cf5415bd-bd5b-4c7a-9cc7-c3b61d7dc613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936942277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1936942277
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.731693972
Short name T198
Test name
Test status
Simulation time 244074242 ps
CPU time 1.18 seconds
Started Jul 22 06:56:30 PM PDT 24
Finished Jul 22 06:56:59 PM PDT 24
Peak memory 217444 kb
Host smart-ac97dc4d-b595-4fd9-8a1a-8944b5fe86d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731693972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.731693972
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2249386771
Short name T293
Test name
Test status
Simulation time 693794312 ps
CPU time 3.68 seconds
Started Jul 22 06:56:30 PM PDT 24
Finished Jul 22 06:57:01 PM PDT 24
Peak memory 200480 kb
Host smart-55dac2cb-cb22-41aa-8224-1f2e22f4771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249386771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2249386771
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2759824031
Short name T65
Test name
Test status
Simulation time 10934987236 ps
CPU time 17.45 seconds
Started Jul 22 06:56:29 PM PDT 24
Finished Jul 22 06:57:15 PM PDT 24
Peak memory 217180 kb
Host smart-313de183-f1be-4e05-9a4d-d0ba2aa21768
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759824031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2759824031
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1221088523
Short name T513
Test name
Test status
Simulation time 105399266 ps
CPU time 1.05 seconds
Started Jul 22 06:56:30 PM PDT 24
Finished Jul 22 06:56:59 PM PDT 24
Peak memory 200140 kb
Host smart-1a9f523d-59f0-4e32-8730-8b0f48e99f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221088523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1221088523
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3947789403
Short name T41
Test name
Test status
Simulation time 112776299 ps
CPU time 1.16 seconds
Started Jul 22 06:56:30 PM PDT 24
Finished Jul 22 06:56:59 PM PDT 24
Peak memory 200356 kb
Host smart-a9b79878-6c98-4a0a-a3f1-497615d3b089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947789403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3947789403
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.4160562809
Short name T236
Test name
Test status
Simulation time 1160424955 ps
CPU time 4.76 seconds
Started Jul 22 06:56:28 PM PDT 24
Finished Jul 22 06:57:01 PM PDT 24
Peak memory 208508 kb
Host smart-2509345b-28cf-4093-bf75-64c0a5855f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160562809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.4160562809
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3916397393
Short name T491
Test name
Test status
Simulation time 149526931 ps
CPU time 1.7 seconds
Started Jul 22 06:56:29 PM PDT 24
Finished Jul 22 06:56:59 PM PDT 24
Peak memory 200128 kb
Host smart-3c1698a7-dfb9-4d14-b225-23e2a39bfa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916397393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3916397393
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1906732410
Short name T238
Test name
Test status
Simulation time 100069616 ps
CPU time 0.88 seconds
Started Jul 22 06:56:28 PM PDT 24
Finished Jul 22 06:56:58 PM PDT 24
Peak memory 200064 kb
Host smart-1c55ec95-d2c5-4402-8789-2938464217eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906732410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1906732410
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2436684724
Short name T439
Test name
Test status
Simulation time 90021999 ps
CPU time 0.85 seconds
Started Jul 22 06:57:36 PM PDT 24
Finished Jul 22 06:57:48 PM PDT 24
Peak memory 199932 kb
Host smart-6bde2329-6d3c-4401-99b0-f8f22b4c726e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436684724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2436684724
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3470893703
Short name T151
Test name
Test status
Simulation time 244414828 ps
CPU time 1.08 seconds
Started Jul 22 06:56:29 PM PDT 24
Finished Jul 22 06:56:58 PM PDT 24
Peak memory 217472 kb
Host smart-00024902-e320-439f-afb2-9105035df4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470893703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3470893703
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.7425575
Short name T15
Test name
Test status
Simulation time 176983589 ps
CPU time 0.83 seconds
Started Jul 22 06:56:30 PM PDT 24
Finished Jul 22 06:56:59 PM PDT 24
Peak memory 199940 kb
Host smart-bcd811ce-35b4-4aac-9dd2-4a5164b446ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7425575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.7425575
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2373840769
Short name T261
Test name
Test status
Simulation time 1702541885 ps
CPU time 6.32 seconds
Started Jul 22 06:56:28 PM PDT 24
Finished Jul 22 06:57:03 PM PDT 24
Peak memory 200412 kb
Host smart-96f6ebc9-8227-4dd1-9579-8dbb860c34f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373840769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2373840769
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2722928981
Short name T69
Test name
Test status
Simulation time 10088495345 ps
CPU time 15.68 seconds
Started Jul 22 06:56:32 PM PDT 24
Finished Jul 22 06:57:14 PM PDT 24
Peak memory 217740 kb
Host smart-fafd6c1f-0839-40d4-a8e7-24da144fd1c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722928981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2722928981
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2206736577
Short name T330
Test name
Test status
Simulation time 110406075 ps
CPU time 1.03 seconds
Started Jul 22 06:56:30 PM PDT 24
Finished Jul 22 06:56:58 PM PDT 24
Peak memory 200120 kb
Host smart-d772efd6-8177-42e8-be27-43956999ec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206736577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2206736577
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2083083622
Short name T239
Test name
Test status
Simulation time 224448016 ps
CPU time 1.38 seconds
Started Jul 22 06:56:29 PM PDT 24
Finished Jul 22 06:56:59 PM PDT 24
Peak memory 200316 kb
Host smart-b1d22692-87b4-41a4-8574-31c2dfd23b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083083622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2083083622
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1229943692
Short name T170
Test name
Test status
Simulation time 172278679 ps
CPU time 1.12 seconds
Started Jul 22 06:56:29 PM PDT 24
Finished Jul 22 06:56:58 PM PDT 24
Peak memory 199952 kb
Host smart-a458df19-fe01-4e0e-9fa9-0d97ea5c12fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229943692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1229943692
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3534504487
Short name T472
Test name
Test status
Simulation time 255694078 ps
CPU time 1.8 seconds
Started Jul 22 06:56:29 PM PDT 24
Finished Jul 22 06:56:59 PM PDT 24
Peak memory 200136 kb
Host smart-b0afd8b1-23ab-44ba-ab78-58a031888705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534504487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3534504487
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1271962996
Short name T347
Test name
Test status
Simulation time 68406158 ps
CPU time 0.75 seconds
Started Jul 22 06:57:24 PM PDT 24
Finished Jul 22 06:57:31 PM PDT 24
Peak memory 199924 kb
Host smart-4c1b9159-b3fd-4581-98ad-d2ba9c0436de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271962996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1271962996
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3108752734
Short name T146
Test name
Test status
Simulation time 245292742 ps
CPU time 1.07 seconds
Started Jul 22 06:57:55 PM PDT 24
Finished Jul 22 06:58:07 PM PDT 24
Peak memory 217512 kb
Host smart-f0f12e43-5fbe-40cf-a445-3be2e7159f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108752734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3108752734
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.799812681
Short name T405
Test name
Test status
Simulation time 189569982 ps
CPU time 0.91 seconds
Started Jul 22 06:57:32 PM PDT 24
Finished Jul 22 06:57:43 PM PDT 24
Peak memory 199908 kb
Host smart-a9d49f85-b987-4a41-8356-55e9fd4eb8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799812681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.799812681
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3546696654
Short name T406
Test name
Test status
Simulation time 749706282 ps
CPU time 3.85 seconds
Started Jul 22 06:57:32 PM PDT 24
Finished Jul 22 06:57:45 PM PDT 24
Peak memory 200364 kb
Host smart-7b0806bb-2380-4f5e-82c0-cf966fc62ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546696654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3546696654
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2534729229
Short name T348
Test name
Test status
Simulation time 183329605 ps
CPU time 1.33 seconds
Started Jul 22 06:57:18 PM PDT 24
Finished Jul 22 06:57:23 PM PDT 24
Peak memory 200132 kb
Host smart-f34f7721-71ce-4d66-9477-3593b3d40774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534729229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2534729229
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2516505396
Short name T470
Test name
Test status
Simulation time 252404832 ps
CPU time 1.54 seconds
Started Jul 22 06:57:20 PM PDT 24
Finished Jul 22 06:57:27 PM PDT 24
Peak memory 200424 kb
Host smart-030dec7a-2a67-497c-9d7e-ec74de7416c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516505396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2516505396
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.85231186
Short name T435
Test name
Test status
Simulation time 133064899 ps
CPU time 1.54 seconds
Started Jul 22 06:57:21 PM PDT 24
Finished Jul 22 06:57:27 PM PDT 24
Peak memory 208340 kb
Host smart-838ca171-9324-475b-a8fa-bf7c520d809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85231186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.85231186
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1875298854
Short name T428
Test name
Test status
Simulation time 135034700 ps
CPU time 0.99 seconds
Started Jul 22 06:57:25 PM PDT 24
Finished Jul 22 06:57:32 PM PDT 24
Peak memory 200216 kb
Host smart-39412baa-0c14-46b1-aac2-3729f1879f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875298854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1875298854
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2468607872
Short name T191
Test name
Test status
Simulation time 55330481 ps
CPU time 0.75 seconds
Started Jul 22 06:57:21 PM PDT 24
Finished Jul 22 06:57:26 PM PDT 24
Peak memory 199956 kb
Host smart-b4361ee4-f372-4344-bc13-0119fbea6490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468607872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2468607872
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.400277984
Short name T317
Test name
Test status
Simulation time 2173877862 ps
CPU time 7.27 seconds
Started Jul 22 06:57:33 PM PDT 24
Finished Jul 22 06:57:49 PM PDT 24
Peak memory 217776 kb
Host smart-ca7b16d1-5194-4be3-8135-ddcb96b15b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400277984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.400277984
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3957832270
Short name T352
Test name
Test status
Simulation time 243457106 ps
CPU time 1.06 seconds
Started Jul 22 06:57:18 PM PDT 24
Finished Jul 22 06:57:23 PM PDT 24
Peak memory 217488 kb
Host smart-ff89d246-d23d-4ed1-a497-cd8aefd3c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957832270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3957832270
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.949792585
Short name T16
Test name
Test status
Simulation time 83821479 ps
CPU time 0.76 seconds
Started Jul 22 06:57:25 PM PDT 24
Finished Jul 22 06:57:32 PM PDT 24
Peak memory 200024 kb
Host smart-6d764938-0fde-4445-bb2a-e3caf585a03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949792585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.949792585
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2904122415
Short name T208
Test name
Test status
Simulation time 1434259842 ps
CPU time 5.57 seconds
Started Jul 22 06:57:19 PM PDT 24
Finished Jul 22 06:57:29 PM PDT 24
Peak memory 200452 kb
Host smart-bc6c70eb-8afb-4524-b38c-cbdbaf7a1adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904122415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2904122415
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.429496966
Short name T393
Test name
Test status
Simulation time 145411940 ps
CPU time 1.24 seconds
Started Jul 22 06:57:17 PM PDT 24
Finished Jul 22 06:57:23 PM PDT 24
Peak memory 200208 kb
Host smart-a7123c35-150a-4b7f-a67b-5e798a60a515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429496966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.429496966
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1243242151
Short name T79
Test name
Test status
Simulation time 199369801 ps
CPU time 1.46 seconds
Started Jul 22 06:57:20 PM PDT 24
Finished Jul 22 06:57:26 PM PDT 24
Peak memory 200352 kb
Host smart-915389c0-4373-423a-9d95-9f5502883da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243242151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1243242151
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2110763411
Short name T313
Test name
Test status
Simulation time 1870134958 ps
CPU time 9.46 seconds
Started Jul 22 06:57:19 PM PDT 24
Finished Jul 22 06:57:33 PM PDT 24
Peak memory 200256 kb
Host smart-4b7f37ad-2639-4c27-b024-f88c9a18fb6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110763411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2110763411
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.213684226
Short name T232
Test name
Test status
Simulation time 406748171 ps
CPU time 2.25 seconds
Started Jul 22 06:57:33 PM PDT 24
Finished Jul 22 06:57:44 PM PDT 24
Peak memory 200156 kb
Host smart-c97ec923-079c-462d-9a79-e8b0b0193c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213684226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.213684226
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1948642059
Short name T242
Test name
Test status
Simulation time 98367701 ps
CPU time 0.9 seconds
Started Jul 22 06:57:21 PM PDT 24
Finished Jul 22 06:57:26 PM PDT 24
Peak memory 199984 kb
Host smart-ac1badcb-5e37-454e-8525-1f671b035c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948642059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1948642059
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2088255125
Short name T257
Test name
Test status
Simulation time 108321625 ps
CPU time 0.89 seconds
Started Jul 22 06:57:32 PM PDT 24
Finished Jul 22 06:57:43 PM PDT 24
Peak memory 199832 kb
Host smart-57a8c374-5d6f-4341-823b-af96395d3281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088255125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2088255125
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1308440440
Short name T262
Test name
Test status
Simulation time 2369290561 ps
CPU time 9.22 seconds
Started Jul 22 06:57:20 PM PDT 24
Finished Jul 22 06:57:34 PM PDT 24
Peak memory 217872 kb
Host smart-0e983339-c0b5-4a13-86cd-d07b4f753bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308440440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1308440440
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1954470410
Short name T260
Test name
Test status
Simulation time 245235792 ps
CPU time 1.13 seconds
Started Jul 22 06:57:24 PM PDT 24
Finished Jul 22 06:57:31 PM PDT 24
Peak memory 217452 kb
Host smart-4611d77b-4901-43dc-8511-bc71a7db1e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954470410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1954470410
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.4177223200
Short name T181
Test name
Test status
Simulation time 135120739 ps
CPU time 0.77 seconds
Started Jul 22 06:57:18 PM PDT 24
Finished Jul 22 06:57:23 PM PDT 24
Peak memory 199984 kb
Host smart-6d6ff648-b511-48c7-b28e-9b63f8037515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177223200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.4177223200
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.803499282
Short name T426
Test name
Test status
Simulation time 1603870582 ps
CPU time 6.23 seconds
Started Jul 22 06:57:19 PM PDT 24
Finished Jul 22 06:57:29 PM PDT 24
Peak memory 200368 kb
Host smart-02c677f5-4705-4544-9bf2-c8f115f31fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803499282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.803499282
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3318003586
Short name T390
Test name
Test status
Simulation time 142947914 ps
CPU time 1.16 seconds
Started Jul 22 06:57:24 PM PDT 24
Finished Jul 22 06:57:31 PM PDT 24
Peak memory 200116 kb
Host smart-8b5e7fe4-8e06-48a0-837b-2442eddd375e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318003586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3318003586
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3170335979
Short name T483
Test name
Test status
Simulation time 124234082 ps
CPU time 1.24 seconds
Started Jul 22 06:57:19 PM PDT 24
Finished Jul 22 06:57:25 PM PDT 24
Peak memory 200452 kb
Host smart-51414d28-b632-42e2-866b-d6780d340063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170335979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3170335979
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.624158565
Short name T126
Test name
Test status
Simulation time 9663654352 ps
CPU time 34.74 seconds
Started Jul 22 06:57:19 PM PDT 24
Finished Jul 22 06:57:58 PM PDT 24
Peak memory 200480 kb
Host smart-4df4fa39-4b4e-49da-a38a-dd52ae4a54e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624158565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.624158565
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1694960557
Short name T539
Test name
Test status
Simulation time 128648443 ps
CPU time 1.68 seconds
Started Jul 22 06:57:20 PM PDT 24
Finished Jul 22 06:57:27 PM PDT 24
Peak memory 200112 kb
Host smart-37e29d14-de2f-494e-9456-4d1b0134d181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694960557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1694960557
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2229315997
Short name T73
Test name
Test status
Simulation time 173455113 ps
CPU time 1.35 seconds
Started Jul 22 06:57:21 PM PDT 24
Finished Jul 22 06:57:28 PM PDT 24
Peak memory 200372 kb
Host smart-5e3df090-630a-45ef-8a83-a87161c3a45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229315997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2229315997
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3759668670
Short name T466
Test name
Test status
Simulation time 97866781 ps
CPU time 0.92 seconds
Started Jul 22 06:57:24 PM PDT 24
Finished Jul 22 06:57:31 PM PDT 24
Peak memory 199916 kb
Host smart-78fb2cbe-0e50-44d3-8c18-ded2b2d75f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759668670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3759668670
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.625300567
Short name T45
Test name
Test status
Simulation time 1880289776 ps
CPU time 7.47 seconds
Started Jul 22 06:57:32 PM PDT 24
Finished Jul 22 06:57:49 PM PDT 24
Peak memory 217600 kb
Host smart-e5b1e0f4-58b1-46b9-b26f-08cb1ee2b99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625300567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.625300567
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1248401037
Short name T384
Test name
Test status
Simulation time 244371619 ps
CPU time 1.14 seconds
Started Jul 22 06:57:20 PM PDT 24
Finished Jul 22 06:57:25 PM PDT 24
Peak memory 217484 kb
Host smart-4bb3a3ce-265c-4725-b8f8-db626009e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248401037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1248401037
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.949534990
Short name T332
Test name
Test status
Simulation time 236941858 ps
CPU time 0.94 seconds
Started Jul 22 06:57:19 PM PDT 24
Finished Jul 22 06:57:24 PM PDT 24
Peak memory 199900 kb
Host smart-63a4810d-1213-4e59-8717-2c81d61a64c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949534990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.949534990
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3666784424
Short name T361
Test name
Test status
Simulation time 917623941 ps
CPU time 4.79 seconds
Started Jul 22 06:57:26 PM PDT 24
Finished Jul 22 06:57:37 PM PDT 24
Peak memory 200484 kb
Host smart-699bc43f-4286-44dd-8374-569df126505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666784424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3666784424
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.236918343
Short name T259
Test name
Test status
Simulation time 101823057 ps
CPU time 1.05 seconds
Started Jul 22 06:57:23 PM PDT 24
Finished Jul 22 06:57:31 PM PDT 24
Peak memory 200116 kb
Host smart-862e9ca4-e902-4054-adc3-304544968720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236918343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.236918343
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2049154272
Short name T83
Test name
Test status
Simulation time 201942007 ps
CPU time 1.53 seconds
Started Jul 22 06:57:25 PM PDT 24
Finished Jul 22 06:57:33 PM PDT 24
Peak memory 200420 kb
Host smart-f24bf7dd-6b21-4073-bc4c-8ed2f5df2f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049154272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2049154272
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1349213117
Short name T309
Test name
Test status
Simulation time 383789747 ps
CPU time 2.44 seconds
Started Jul 22 06:57:21 PM PDT 24
Finished Jul 22 06:57:29 PM PDT 24
Peak memory 200136 kb
Host smart-275de46b-e7f4-429d-9d7d-cc5e797c473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349213117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1349213117
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2776501594
Short name T440
Test name
Test status
Simulation time 103232267 ps
CPU time 1.01 seconds
Started Jul 22 06:57:21 PM PDT 24
Finished Jul 22 06:57:28 PM PDT 24
Peak memory 200128 kb
Host smart-62627dd3-990a-4746-bf15-3beff2579cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776501594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2776501594
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2377883706
Short name T452
Test name
Test status
Simulation time 79572124 ps
CPU time 0.82 seconds
Started Jul 22 06:57:54 PM PDT 24
Finished Jul 22 06:58:06 PM PDT 24
Peak memory 199940 kb
Host smart-afe3d883-2343-486d-aa0b-a10842875330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377883706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2377883706
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3419328707
Short name T290
Test name
Test status
Simulation time 1896006455 ps
CPU time 7.23 seconds
Started Jul 22 06:57:31 PM PDT 24
Finished Jul 22 06:57:45 PM PDT 24
Peak memory 217520 kb
Host smart-37e0f628-a6e1-47e6-8f26-af0dd6fc617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419328707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3419328707
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.169498280
Short name T197
Test name
Test status
Simulation time 243530790 ps
CPU time 1.09 seconds
Started Jul 22 06:57:30 PM PDT 24
Finished Jul 22 06:57:37 PM PDT 24
Peak memory 217480 kb
Host smart-d526a2dd-398d-4934-aea5-dba91c8441c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169498280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.169498280
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.341147397
Short name T414
Test name
Test status
Simulation time 157690995 ps
CPU time 0.85 seconds
Started Jul 22 06:57:29 PM PDT 24
Finished Jul 22 06:57:37 PM PDT 24
Peak memory 199872 kb
Host smart-661a34d5-1783-4840-8fab-cc55401a87f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341147397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.341147397
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3727874115
Short name T294
Test name
Test status
Simulation time 1351325096 ps
CPU time 5.14 seconds
Started Jul 22 06:59:02 PM PDT 24
Finished Jul 22 06:59:14 PM PDT 24
Peak memory 199964 kb
Host smart-98da99b1-61f5-4616-8696-c37b225789b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727874115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3727874115
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3778105720
Short name T288
Test name
Test status
Simulation time 112824419 ps
CPU time 0.97 seconds
Started Jul 22 06:57:31 PM PDT 24
Finished Jul 22 06:57:40 PM PDT 24
Peak memory 200140 kb
Host smart-4aeb0e0a-5e29-4317-b864-b2d2aa4e457f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778105720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3778105720
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3435103494
Short name T70
Test name
Test status
Simulation time 188027159 ps
CPU time 1.4 seconds
Started Jul 22 06:57:24 PM PDT 24
Finished Jul 22 06:57:31 PM PDT 24
Peak memory 200328 kb
Host smart-7feb8f22-a0d4-4316-8529-6ac2743b8b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435103494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3435103494
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.4222349480
Short name T377
Test name
Test status
Simulation time 3416230213 ps
CPU time 14.67 seconds
Started Jul 22 06:57:30 PM PDT 24
Finished Jul 22 06:57:51 PM PDT 24
Peak memory 208652 kb
Host smart-22e7d162-69f0-4d68-a6dc-1667fb9d2d0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222349480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.4222349480
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.108285177
Short name T518
Test name
Test status
Simulation time 304733239 ps
CPU time 2.04 seconds
Started Jul 22 06:57:35 PM PDT 24
Finished Jul 22 06:57:47 PM PDT 24
Peak memory 208308 kb
Host smart-3dcca23d-0cf7-4e97-a275-a207c8bd6e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108285177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.108285177
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.4197064441
Short name T403
Test name
Test status
Simulation time 163065344 ps
CPU time 1.26 seconds
Started Jul 22 06:57:31 PM PDT 24
Finished Jul 22 06:57:41 PM PDT 24
Peak memory 200392 kb
Host smart-b8bc644f-44c0-4eea-ba75-77a41dbdbfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197064441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.4197064441
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3210565869
Short name T504
Test name
Test status
Simulation time 52696197 ps
CPU time 0.73 seconds
Started Jul 22 06:57:31 PM PDT 24
Finished Jul 22 06:57:40 PM PDT 24
Peak memory 199780 kb
Host smart-2164ead0-668f-41b6-961f-941c0dc1e5c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210565869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3210565869
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1210923716
Short name T295
Test name
Test status
Simulation time 2354888603 ps
CPU time 8.91 seconds
Started Jul 22 06:57:32 PM PDT 24
Finished Jul 22 06:57:49 PM PDT 24
Peak memory 217976 kb
Host smart-af2c1c1d-fde3-4edb-b6e8-9392851eef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210923716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1210923716
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2771500209
Short name T397
Test name
Test status
Simulation time 244581762 ps
CPU time 1.06 seconds
Started Jul 22 06:57:29 PM PDT 24
Finished Jul 22 06:57:37 PM PDT 24
Peak memory 217488 kb
Host smart-2708e717-ef2b-4ae6-9aa5-536fa34df3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771500209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2771500209
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2417949529
Short name T167
Test name
Test status
Simulation time 91284235 ps
CPU time 0.75 seconds
Started Jul 22 06:57:31 PM PDT 24
Finished Jul 22 06:57:39 PM PDT 24
Peak memory 200028 kb
Host smart-74f79a21-6fa3-4a2a-8598-15dba640402b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417949529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2417949529
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1973124711
Short name T278
Test name
Test status
Simulation time 1364591189 ps
CPU time 5.82 seconds
Started Jul 22 06:58:37 PM PDT 24
Finished Jul 22 06:58:49 PM PDT 24
Peak memory 200404 kb
Host smart-3cc3cd38-2960-411a-90a9-14690db16e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973124711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1973124711
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3899466792
Short name T492
Test name
Test status
Simulation time 109148414 ps
CPU time 1.02 seconds
Started Jul 22 06:58:38 PM PDT 24
Finished Jul 22 06:58:44 PM PDT 24
Peak memory 200132 kb
Host smart-a966548c-bffa-450e-88ac-f2934e51fe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899466792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3899466792
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1779573212
Short name T531
Test name
Test status
Simulation time 249738661 ps
CPU time 1.63 seconds
Started Jul 22 06:58:20 PM PDT 24
Finished Jul 22 06:58:28 PM PDT 24
Peak memory 200288 kb
Host smart-0ad7faee-0912-43b5-a778-1ba4cd8590d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779573212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1779573212
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2225226972
Short name T228
Test name
Test status
Simulation time 6174006820 ps
CPU time 27.6 seconds
Started Jul 22 06:57:32 PM PDT 24
Finished Jul 22 06:58:07 PM PDT 24
Peak memory 209516 kb
Host smart-869b19f0-5b78-417f-a6c1-a4b7b0d55196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225226972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2225226972
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1272880587
Short name T211
Test name
Test status
Simulation time 155484369 ps
CPU time 1.94 seconds
Started Jul 22 06:57:39 PM PDT 24
Finished Jul 22 06:57:51 PM PDT 24
Peak memory 200152 kb
Host smart-e10484b4-57ba-4be3-aba7-d6b5959fe985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272880587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1272880587
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2832960747
Short name T3
Test name
Test status
Simulation time 65989778 ps
CPU time 0.83 seconds
Started Jul 22 06:57:31 PM PDT 24
Finished Jul 22 06:57:40 PM PDT 24
Peak memory 200144 kb
Host smart-01b663f1-962c-4472-a400-5a9f7b3b5d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832960747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2832960747
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2827146093
Short name T300
Test name
Test status
Simulation time 76568101 ps
CPU time 0.81 seconds
Started Jul 22 06:57:30 PM PDT 24
Finished Jul 22 06:57:38 PM PDT 24
Peak memory 199904 kb
Host smart-9c1d68b5-bcd7-46da-8559-d21c46b8bef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827146093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2827146093
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2146680376
Short name T49
Test name
Test status
Simulation time 1229757937 ps
CPU time 5.83 seconds
Started Jul 22 06:57:30 PM PDT 24
Finished Jul 22 06:57:43 PM PDT 24
Peak memory 216904 kb
Host smart-fbe740e4-04a4-4766-8971-03d555160f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146680376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2146680376
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2097998856
Short name T37
Test name
Test status
Simulation time 248200921 ps
CPU time 1.02 seconds
Started Jul 22 06:59:05 PM PDT 24
Finished Jul 22 06:59:14 PM PDT 24
Peak memory 217348 kb
Host smart-53a8e6b2-e1bf-479f-8ed3-530c8e235486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097998856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2097998856
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2959966430
Short name T18
Test name
Test status
Simulation time 189121738 ps
CPU time 0.93 seconds
Started Jul 22 06:57:29 PM PDT 24
Finished Jul 22 06:57:37 PM PDT 24
Peak memory 199980 kb
Host smart-af35d8ce-c7a6-4e05-a58d-74c18008f6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959966430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2959966430
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2705174686
Short name T357
Test name
Test status
Simulation time 891751476 ps
CPU time 5.05 seconds
Started Jul 22 06:57:32 PM PDT 24
Finished Jul 22 06:57:45 PM PDT 24
Peak memory 200488 kb
Host smart-be5249a0-bdbc-454b-bd19-ba7e02a9323f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705174686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2705174686
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3580616494
Short name T233
Test name
Test status
Simulation time 153239345 ps
CPU time 1.17 seconds
Started Jul 22 06:57:29 PM PDT 24
Finished Jul 22 06:57:37 PM PDT 24
Peak memory 200056 kb
Host smart-289f49a9-4941-45f0-a70e-70616ac9438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580616494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3580616494
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4058407649
Short name T340
Test name
Test status
Simulation time 109823677 ps
CPU time 1.1 seconds
Started Jul 22 06:58:29 PM PDT 24
Finished Jul 22 06:58:36 PM PDT 24
Peak memory 200376 kb
Host smart-a816fdf4-a021-4654-a83c-e2f7880b0c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058407649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4058407649
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.84806326
Short name T438
Test name
Test status
Simulation time 248828455 ps
CPU time 1.31 seconds
Started Jul 22 06:57:29 PM PDT 24
Finished Jul 22 06:57:37 PM PDT 24
Peak memory 199856 kb
Host smart-020a8fb0-4d6b-41b2-8c4c-c1281d3a0d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84806326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.84806326
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2545479982
Short name T408
Test name
Test status
Simulation time 394149057 ps
CPU time 2.22 seconds
Started Jul 22 06:57:30 PM PDT 24
Finished Jul 22 06:57:39 PM PDT 24
Peak memory 200144 kb
Host smart-877298b8-873e-4828-8e09-9fe1d548a6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545479982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2545479982
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1396471026
Short name T456
Test name
Test status
Simulation time 80114498 ps
CPU time 0.81 seconds
Started Jul 22 06:57:33 PM PDT 24
Finished Jul 22 06:57:44 PM PDT 24
Peak memory 200140 kb
Host smart-764c6464-fe15-4bbb-a871-3a10f8af400d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396471026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1396471026
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4062204047
Short name T74
Test name
Test status
Simulation time 63163916 ps
CPU time 0.72 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:25 PM PDT 24
Peak memory 199864 kb
Host smart-8dc2162d-3f76-4c6f-8486-976712eeac0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062204047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4062204047
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1275848236
Short name T529
Test name
Test status
Simulation time 1225780635 ps
CPU time 5.85 seconds
Started Jul 22 06:57:32 PM PDT 24
Finished Jul 22 06:57:47 PM PDT 24
Peak memory 216804 kb
Host smart-420d13ea-fd48-455a-9290-8d132095663c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275848236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1275848236
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2608052980
Short name T484
Test name
Test status
Simulation time 244609247 ps
CPU time 1.07 seconds
Started Jul 22 06:57:35 PM PDT 24
Finished Jul 22 06:57:47 PM PDT 24
Peak memory 217564 kb
Host smart-8b3adc81-a59b-4f9c-a352-545baf9cb5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608052980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2608052980
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.4268111483
Short name T431
Test name
Test status
Simulation time 159706083 ps
CPU time 0.88 seconds
Started Jul 22 06:57:31 PM PDT 24
Finished Jul 22 06:57:39 PM PDT 24
Peak memory 199948 kb
Host smart-92c51f1f-6a17-4d95-a036-8d5ea9f4cd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268111483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4268111483
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3379144909
Short name T36
Test name
Test status
Simulation time 1018871573 ps
CPU time 5.47 seconds
Started Jul 22 06:57:32 PM PDT 24
Finished Jul 22 06:57:45 PM PDT 24
Peak memory 200404 kb
Host smart-619eb5e4-db9c-45fb-af62-ff94ff96ba1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379144909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3379144909
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1572716171
Short name T341
Test name
Test status
Simulation time 111205824 ps
CPU time 1.04 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:25 PM PDT 24
Peak memory 200068 kb
Host smart-678e345d-2102-4ffd-821d-17b9958b9385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572716171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1572716171
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.155371072
Short name T266
Test name
Test status
Simulation time 130397983 ps
CPU time 1.18 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:25 PM PDT 24
Peak memory 200284 kb
Host smart-947c2b61-a61a-4b17-a743-c797aa35ba75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155371072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.155371072
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1557982334
Short name T123
Test name
Test status
Simulation time 2234172715 ps
CPU time 7.62 seconds
Started Jul 22 06:57:34 PM PDT 24
Finished Jul 22 06:57:51 PM PDT 24
Peak memory 200516 kb
Host smart-efbb319b-6d14-4ac0-aa23-4f823466ddbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557982334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1557982334
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.764118611
Short name T523
Test name
Test status
Simulation time 138957774 ps
CPU time 1.68 seconds
Started Jul 22 06:57:32 PM PDT 24
Finished Jul 22 06:57:42 PM PDT 24
Peak memory 200232 kb
Host smart-548c7274-094e-4bfd-ad84-36fa5c7ae5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764118611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.764118611
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2726935458
Short name T200
Test name
Test status
Simulation time 111066525 ps
CPU time 1.01 seconds
Started Jul 22 06:57:31 PM PDT 24
Finished Jul 22 06:57:39 PM PDT 24
Peak memory 200156 kb
Host smart-d4ad6a98-5bfb-476a-8f28-d71d2acecbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726935458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2726935458
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3883151564
Short name T474
Test name
Test status
Simulation time 78365469 ps
CPU time 0.8 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:55 PM PDT 24
Peak memory 199996 kb
Host smart-16d2d3e3-b1df-4072-84b6-aa7577ce1f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883151564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3883151564
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2259869824
Short name T320
Test name
Test status
Simulation time 1230574168 ps
CPU time 5.94 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:30 PM PDT 24
Peak memory 217504 kb
Host smart-ee2eb0d1-8e34-4839-992f-1468beb07405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259869824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2259869824
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1098850701
Short name T206
Test name
Test status
Simulation time 243192852 ps
CPU time 1.13 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:56 PM PDT 24
Peak memory 217508 kb
Host smart-f1c7f641-97df-4008-b696-147b193f7353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098850701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1098850701
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2184875194
Short name T368
Test name
Test status
Simulation time 95615660 ps
CPU time 0.77 seconds
Started Jul 22 06:57:34 PM PDT 24
Finished Jul 22 06:57:44 PM PDT 24
Peak memory 199952 kb
Host smart-8c49f8ac-1a95-419d-bcb6-169b72297e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184875194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2184875194
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1126931514
Short name T5
Test name
Test status
Simulation time 1545417934 ps
CPU time 5.81 seconds
Started Jul 22 06:57:35 PM PDT 24
Finished Jul 22 06:57:51 PM PDT 24
Peak memory 200452 kb
Host smart-ad0ec353-83df-4325-b8f9-1e0682854d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126931514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1126931514
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.4105353618
Short name T319
Test name
Test status
Simulation time 96605924 ps
CPU time 1 seconds
Started Jul 22 06:57:30 PM PDT 24
Finished Jul 22 06:57:37 PM PDT 24
Peak memory 200164 kb
Host smart-3b1d7968-061f-4458-94ff-969f291b111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105353618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.4105353618
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.665076304
Short name T354
Test name
Test status
Simulation time 246904666 ps
CPU time 1.44 seconds
Started Jul 22 06:57:35 PM PDT 24
Finished Jul 22 06:57:47 PM PDT 24
Peak memory 200344 kb
Host smart-10e2a883-6f43-4539-b18e-b26407163063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665076304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.665076304
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3862911926
Short name T164
Test name
Test status
Simulation time 3786346066 ps
CPU time 15.04 seconds
Started Jul 22 06:57:42 PM PDT 24
Finished Jul 22 06:58:07 PM PDT 24
Peak memory 216812 kb
Host smart-f9a12667-e121-436b-812f-aa09ff620dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862911926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3862911926
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.166701047
Short name T509
Test name
Test status
Simulation time 457783400 ps
CPU time 2.53 seconds
Started Jul 22 06:57:33 PM PDT 24
Finished Jul 22 06:57:46 PM PDT 24
Peak memory 200152 kb
Host smart-ed718dfa-788c-4963-88c2-e312faabd8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166701047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.166701047
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.582934937
Short name T323
Test name
Test status
Simulation time 199740495 ps
CPU time 1.25 seconds
Started Jul 22 06:57:39 PM PDT 24
Finished Jul 22 06:57:51 PM PDT 24
Peak memory 200176 kb
Host smart-dbcf1c65-086b-4067-baa3-e713e8bf2ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582934937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.582934937
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.4061238299
Short name T487
Test name
Test status
Simulation time 74328639 ps
CPU time 0.77 seconds
Started Jul 22 06:57:45 PM PDT 24
Finished Jul 22 06:57:58 PM PDT 24
Peak memory 199892 kb
Host smart-384f865a-1a8b-4ebe-af1e-ec71f1cc07fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061238299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4061238299
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.4183836849
Short name T51
Test name
Test status
Simulation time 1878250538 ps
CPU time 6.61 seconds
Started Jul 22 06:58:48 PM PDT 24
Finished Jul 22 06:59:01 PM PDT 24
Peak memory 217544 kb
Host smart-34ee58cf-a974-4f5e-83e1-223a28a29f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183836849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.4183836849
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1699798355
Short name T473
Test name
Test status
Simulation time 244245135 ps
CPU time 1.04 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:54 PM PDT 24
Peak memory 217488 kb
Host smart-ae1a7264-6804-417e-b003-52ea491c6f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699798355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1699798355
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.131744183
Short name T446
Test name
Test status
Simulation time 177666712 ps
CPU time 0.93 seconds
Started Jul 22 06:57:42 PM PDT 24
Finished Jul 22 06:57:53 PM PDT 24
Peak memory 199976 kb
Host smart-697babf7-6e94-4348-ab8b-33035aa21c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131744183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.131744183
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.518879542
Short name T249
Test name
Test status
Simulation time 994588321 ps
CPU time 4.67 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:59 PM PDT 24
Peak memory 200384 kb
Host smart-78f9f99a-4451-4027-920f-fa5344ba1f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518879542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.518879542
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3384017726
Short name T322
Test name
Test status
Simulation time 153282228 ps
CPU time 1.09 seconds
Started Jul 22 06:57:47 PM PDT 24
Finished Jul 22 06:58:00 PM PDT 24
Peak memory 200132 kb
Host smart-d8166716-01b5-4359-820f-3f1590cbfc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384017726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3384017726
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.180196762
Short name T443
Test name
Test status
Simulation time 187910790 ps
CPU time 1.36 seconds
Started Jul 22 06:57:47 PM PDT 24
Finished Jul 22 06:58:00 PM PDT 24
Peak memory 200348 kb
Host smart-51a1a3af-94ad-47b9-9646-d1cb74b079d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180196762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.180196762
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3859803740
Short name T122
Test name
Test status
Simulation time 9682020379 ps
CPU time 33.13 seconds
Started Jul 22 06:58:48 PM PDT 24
Finished Jul 22 06:59:28 PM PDT 24
Peak memory 216296 kb
Host smart-77786d60-b121-4269-815a-7769250aa55a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859803740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3859803740
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3982512771
Short name T499
Test name
Test status
Simulation time 361330392 ps
CPU time 2.02 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:56 PM PDT 24
Peak memory 200148 kb
Host smart-58771d09-2f2f-4570-8d98-56f6a2fd4141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982512771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3982512771
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.744118620
Short name T424
Test name
Test status
Simulation time 73705532 ps
CPU time 0.81 seconds
Started Jul 22 06:59:02 PM PDT 24
Finished Jul 22 06:59:09 PM PDT 24
Peak memory 199692 kb
Host smart-a2394a14-b495-47d1-8798-b4790de3ed7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744118620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.744118620
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1682334734
Short name T365
Test name
Test status
Simulation time 77199690 ps
CPU time 0.82 seconds
Started Jul 22 06:56:38 PM PDT 24
Finished Jul 22 06:57:02 PM PDT 24
Peak memory 199936 kb
Host smart-f063845c-dc2e-43a1-acd4-21dd1d545b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682334734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1682334734
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2355755725
Short name T30
Test name
Test status
Simulation time 1896048957 ps
CPU time 7.2 seconds
Started Jul 22 06:56:40 PM PDT 24
Finished Jul 22 06:57:09 PM PDT 24
Peak memory 216852 kb
Host smart-59f26340-756a-4250-a638-c657958de7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355755725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2355755725
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.274304069
Short name T502
Test name
Test status
Simulation time 244165495 ps
CPU time 1.1 seconds
Started Jul 22 06:56:43 PM PDT 24
Finished Jul 22 06:57:03 PM PDT 24
Peak memory 217476 kb
Host smart-a7dc06cc-b90b-4316-a6fd-195ecf680512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274304069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.274304069
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3357277530
Short name T14
Test name
Test status
Simulation time 121623773 ps
CPU time 0.81 seconds
Started Jul 22 06:56:40 PM PDT 24
Finished Jul 22 06:57:02 PM PDT 24
Peak memory 199952 kb
Host smart-1eedf2c7-dfe4-43b7-81a5-064e81f39d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357277530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3357277530
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2587483406
Short name T92
Test name
Test status
Simulation time 1678799103 ps
CPU time 7.12 seconds
Started Jul 22 06:56:40 PM PDT 24
Finished Jul 22 06:57:09 PM PDT 24
Peak memory 200400 kb
Host smart-8b6f7346-62f1-4323-873e-9b7cefabcbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587483406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2587483406
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.658603077
Short name T68
Test name
Test status
Simulation time 8297088043 ps
CPU time 17.05 seconds
Started Jul 22 06:56:41 PM PDT 24
Finished Jul 22 06:57:19 PM PDT 24
Peak memory 217676 kb
Host smart-7a6a4e09-025c-4568-9e17-7b7d2dc47bc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658603077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.658603077
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2749007583
Short name T235
Test name
Test status
Simulation time 148541060 ps
CPU time 1.17 seconds
Started Jul 22 06:56:40 PM PDT 24
Finished Jul 22 06:57:03 PM PDT 24
Peak memory 200168 kb
Host smart-22562383-b90e-48c4-9ec4-f3b5e8074520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749007583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2749007583
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3302562001
Short name T327
Test name
Test status
Simulation time 194206770 ps
CPU time 1.34 seconds
Started Jul 22 06:56:30 PM PDT 24
Finished Jul 22 06:56:59 PM PDT 24
Peak memory 200344 kb
Host smart-c3e5274c-f67a-4842-9db5-f5e277b56efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302562001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3302562001
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1961290225
Short name T217
Test name
Test status
Simulation time 5197358740 ps
CPU time 18.51 seconds
Started Jul 22 06:56:47 PM PDT 24
Finished Jul 22 06:57:22 PM PDT 24
Peak memory 208640 kb
Host smart-190a11ae-aece-4167-bee5-0b303c9cc58f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961290225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1961290225
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3510458613
Short name T179
Test name
Test status
Simulation time 278244277 ps
CPU time 1.9 seconds
Started Jul 22 06:56:42 PM PDT 24
Finished Jul 22 06:57:04 PM PDT 24
Peak memory 200128 kb
Host smart-521e7cd7-09d4-4fe5-827a-fecebe6244bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510458613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3510458613
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3085525906
Short name T171
Test name
Test status
Simulation time 100318355 ps
CPU time 0.96 seconds
Started Jul 22 06:56:38 PM PDT 24
Finished Jul 22 06:57:02 PM PDT 24
Peak memory 200148 kb
Host smart-91c18eef-51d2-42cb-a5f6-c22cc27d5600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085525906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3085525906
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.662132822
Short name T447
Test name
Test status
Simulation time 71942032 ps
CPU time 0.81 seconds
Started Jul 22 06:57:41 PM PDT 24
Finished Jul 22 06:57:53 PM PDT 24
Peak memory 199780 kb
Host smart-42de0cd5-64ab-4ca9-ac56-b33f78088dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662132822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.662132822
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3376313521
Short name T433
Test name
Test status
Simulation time 1216330913 ps
CPU time 5.51 seconds
Started Jul 22 06:57:40 PM PDT 24
Finished Jul 22 06:57:56 PM PDT 24
Peak memory 217524 kb
Host smart-5ba8863e-5354-42ee-aab4-764461d1b829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376313521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3376313521
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1822632963
Short name T276
Test name
Test status
Simulation time 243913433 ps
CPU time 1.08 seconds
Started Jul 22 06:57:41 PM PDT 24
Finished Jul 22 06:57:53 PM PDT 24
Peak memory 217532 kb
Host smart-e5d97890-6879-409e-9de6-787afbb1bda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822632963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1822632963
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2408576838
Short name T308
Test name
Test status
Simulation time 201613494 ps
CPU time 0.91 seconds
Started Jul 22 06:57:42 PM PDT 24
Finished Jul 22 06:57:53 PM PDT 24
Peak memory 199872 kb
Host smart-8ca20996-1336-492d-a9b8-0b820e844bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408576838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2408576838
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3223820050
Short name T21
Test name
Test status
Simulation time 951837605 ps
CPU time 4.58 seconds
Started Jul 22 06:57:41 PM PDT 24
Finished Jul 22 06:57:56 PM PDT 24
Peak memory 200388 kb
Host smart-c84ee9fb-f433-4e17-bea7-f556774c9ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223820050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3223820050
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2213386819
Short name T139
Test name
Test status
Simulation time 195332853 ps
CPU time 1.49 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:55 PM PDT 24
Peak memory 200424 kb
Host smart-08881a29-bf7d-4c0e-9cf7-c9a5081474da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213386819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2213386819
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3991532100
Short name T194
Test name
Test status
Simulation time 10859942809 ps
CPU time 44.65 seconds
Started Jul 22 06:57:47 PM PDT 24
Finished Jul 22 06:58:44 PM PDT 24
Peak memory 200472 kb
Host smart-f11b2382-4a84-4430-80bc-92de54d84ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991532100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3991532100
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.4203662010
Short name T226
Test name
Test status
Simulation time 440995614 ps
CPU time 2.54 seconds
Started Jul 22 06:57:42 PM PDT 24
Finished Jul 22 06:57:56 PM PDT 24
Peak memory 200080 kb
Host smart-e8017762-fe1d-4f9f-9792-514c1656b683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203662010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.4203662010
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2120934569
Short name T220
Test name
Test status
Simulation time 68607271 ps
CPU time 0.78 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:54 PM PDT 24
Peak memory 200140 kb
Host smart-5a4adf86-0963-4980-a74d-9eb309f5e58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120934569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2120934569
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2829528652
Short name T312
Test name
Test status
Simulation time 82031179 ps
CPU time 0.79 seconds
Started Jul 22 06:57:57 PM PDT 24
Finished Jul 22 06:58:09 PM PDT 24
Peak memory 199976 kb
Host smart-02fc30df-37a8-4f1e-b8ca-1d3f4df4b211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829528652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2829528652
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.355651063
Short name T399
Test name
Test status
Simulation time 2359345491 ps
CPU time 7.9 seconds
Started Jul 22 06:57:44 PM PDT 24
Finished Jul 22 06:58:03 PM PDT 24
Peak memory 218080 kb
Host smart-34f10d65-b4d1-4dd1-a7fa-784640436627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355651063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.355651063
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2216711904
Short name T421
Test name
Test status
Simulation time 244862018 ps
CPU time 1.09 seconds
Started Jul 22 06:59:14 PM PDT 24
Finished Jul 22 06:59:25 PM PDT 24
Peak memory 217504 kb
Host smart-b6d4251c-b823-40eb-850b-8561c59d7bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216711904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2216711904
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1681171956
Short name T176
Test name
Test status
Simulation time 100190769 ps
CPU time 0.76 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:55 PM PDT 24
Peak memory 199952 kb
Host smart-73c7a82e-f816-41ac-8793-32c0f1769156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681171956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1681171956
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.690639641
Short name T124
Test name
Test status
Simulation time 1710787357 ps
CPU time 6.61 seconds
Started Jul 22 06:57:41 PM PDT 24
Finished Jul 22 06:57:58 PM PDT 24
Peak memory 200412 kb
Host smart-691cea85-bd0a-432c-81ba-2587851d1102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690639641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.690639641
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1846768094
Short name T148
Test name
Test status
Simulation time 98200900 ps
CPU time 1.06 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:55 PM PDT 24
Peak memory 200196 kb
Host smart-58fad939-a803-4aa0-8f5c-d1ea9d9261e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846768094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1846768094
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3833565495
Short name T379
Test name
Test status
Simulation time 258662632 ps
CPU time 1.41 seconds
Started Jul 22 06:57:47 PM PDT 24
Finished Jul 22 06:58:01 PM PDT 24
Peak memory 200304 kb
Host smart-c63568c6-0798-4fc5-9508-3937893d3c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833565495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3833565495
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3666425838
Short name T94
Test name
Test status
Simulation time 3210509034 ps
CPU time 14.36 seconds
Started Jul 22 06:57:46 PM PDT 24
Finished Jul 22 06:58:13 PM PDT 24
Peak memory 208668 kb
Host smart-d6723990-79d2-4e75-854b-f844e089f812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666425838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3666425838
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2535025791
Short name T296
Test name
Test status
Simulation time 305458693 ps
CPU time 1.94 seconds
Started Jul 22 06:57:41 PM PDT 24
Finished Jul 22 06:57:54 PM PDT 24
Peak memory 208316 kb
Host smart-5d771684-cc5b-42f8-931d-f152d287d5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535025791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2535025791
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.481293344
Short name T161
Test name
Test status
Simulation time 76748052 ps
CPU time 0.86 seconds
Started Jul 22 06:57:41 PM PDT 24
Finished Jul 22 06:57:52 PM PDT 24
Peak memory 200136 kb
Host smart-079fffa5-82c3-49e3-842f-843d7e064a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481293344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.481293344
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1037989985
Short name T286
Test name
Test status
Simulation time 1224577078 ps
CPU time 5.48 seconds
Started Jul 22 06:57:47 PM PDT 24
Finished Jul 22 06:58:04 PM PDT 24
Peak memory 221724 kb
Host smart-733bddc2-baac-479d-84a9-1d77adeee022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037989985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1037989985
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1556575323
Short name T395
Test name
Test status
Simulation time 245661202 ps
CPU time 1.03 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:05 PM PDT 24
Peak memory 218404 kb
Host smart-17b2e3a9-93bc-4f77-8fab-f8931b6e41b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556575323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1556575323
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2979107844
Short name T157
Test name
Test status
Simulation time 120115234 ps
CPU time 0.8 seconds
Started Jul 22 06:57:41 PM PDT 24
Finished Jul 22 06:57:52 PM PDT 24
Peak memory 199948 kb
Host smart-a16ffa75-f221-4833-8982-40b1d6f718e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979107844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2979107844
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3296072340
Short name T373
Test name
Test status
Simulation time 1078501144 ps
CPU time 5.11 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:58 PM PDT 24
Peak memory 200492 kb
Host smart-a210ff64-4013-45e7-a65e-e9fa02626c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296072340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3296072340
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1015706707
Short name T494
Test name
Test status
Simulation time 163736422 ps
CPU time 1.13 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:54 PM PDT 24
Peak memory 200124 kb
Host smart-47282552-054e-46d4-9567-f66c9c9972c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015706707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1015706707
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3534710305
Short name T541
Test name
Test status
Simulation time 220316325 ps
CPU time 1.4 seconds
Started Jul 22 06:57:44 PM PDT 24
Finished Jul 22 06:57:56 PM PDT 24
Peak memory 200316 kb
Host smart-42588966-d072-4116-bf18-c6a07c1ee2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534710305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3534710305
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3841429226
Short name T251
Test name
Test status
Simulation time 1559707347 ps
CPU time 7.14 seconds
Started Jul 22 06:58:00 PM PDT 24
Finished Jul 22 06:58:17 PM PDT 24
Peak memory 200440 kb
Host smart-f237347f-1fdc-40ad-b7f4-57eb81cd51e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841429226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3841429226
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1343293292
Short name T128
Test name
Test status
Simulation time 542487760 ps
CPU time 2.61 seconds
Started Jul 22 06:57:42 PM PDT 24
Finished Jul 22 06:57:55 PM PDT 24
Peak memory 200148 kb
Host smart-5bae9738-6510-4b0b-9e5e-4652dc73f0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343293292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1343293292
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.321063343
Short name T209
Test name
Test status
Simulation time 103067974 ps
CPU time 0.87 seconds
Started Jul 22 06:57:43 PM PDT 24
Finished Jul 22 06:57:54 PM PDT 24
Peak memory 200136 kb
Host smart-35c43cd0-a2f0-4830-85dd-5275540f9897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321063343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.321063343
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3173273272
Short name T394
Test name
Test status
Simulation time 70664388 ps
CPU time 0.84 seconds
Started Jul 22 06:57:51 PM PDT 24
Finished Jul 22 06:58:03 PM PDT 24
Peak memory 199940 kb
Host smart-a4a6d179-5213-4276-adce-4c008ee3bede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173273272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3173273272
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.236517853
Short name T46
Test name
Test status
Simulation time 1221197743 ps
CPU time 5.67 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:09 PM PDT 24
Peak memory 217124 kb
Host smart-8907fd31-4784-422c-abed-d6f29a3c3294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236517853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.236517853
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1856793492
Short name T423
Test name
Test status
Simulation time 244456008 ps
CPU time 1.13 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:05 PM PDT 24
Peak memory 217532 kb
Host smart-893b31c3-9dfa-42ec-9fa9-8a76ff22c235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856793492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1856793492
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2938663223
Short name T402
Test name
Test status
Simulation time 90582442 ps
CPU time 0.74 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:06 PM PDT 24
Peak memory 199924 kb
Host smart-45ac3637-cdc4-4ed8-b2b7-450eefb9c979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938663223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2938663223
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2359988377
Short name T508
Test name
Test status
Simulation time 1032867342 ps
CPU time 5.53 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:10 PM PDT 24
Peak memory 200404 kb
Host smart-2fee31bd-baf6-4a08-b565-f97ea4135385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359988377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2359988377
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3366668186
Short name T141
Test name
Test status
Simulation time 159197725 ps
CPU time 1.19 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:05 PM PDT 24
Peak memory 200132 kb
Host smart-a47ac68d-f276-46f3-87c9-0aa97a058012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366668186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3366668186
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3666967073
Short name T419
Test name
Test status
Simulation time 123814137 ps
CPU time 1.24 seconds
Started Jul 22 06:57:52 PM PDT 24
Finished Jul 22 06:58:04 PM PDT 24
Peak memory 200356 kb
Host smart-66ed2aab-9cd6-41eb-878f-0661d1181737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666967073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3666967073
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.985619109
Short name T244
Test name
Test status
Simulation time 6693868263 ps
CPU time 22.31 seconds
Started Jul 22 06:57:51 PM PDT 24
Finished Jul 22 06:58:25 PM PDT 24
Peak memory 208652 kb
Host smart-22a4066a-609e-4de4-8fee-e3d092c63009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985619109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.985619109
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3102793039
Short name T182
Test name
Test status
Simulation time 474368126 ps
CPU time 2.67 seconds
Started Jul 22 06:57:50 PM PDT 24
Finished Jul 22 06:58:04 PM PDT 24
Peak memory 200092 kb
Host smart-e80e7b9c-3c6b-40f5-a41a-8c7532673d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102793039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3102793039
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3517426116
Short name T303
Test name
Test status
Simulation time 103861501 ps
CPU time 0.86 seconds
Started Jul 22 06:57:51 PM PDT 24
Finished Jul 22 06:58:03 PM PDT 24
Peak memory 200212 kb
Host smart-6d0512df-9c15-4b7e-bb12-2e97152af40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517426116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3517426116
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2347733664
Short name T389
Test name
Test status
Simulation time 67575083 ps
CPU time 0.78 seconds
Started Jul 22 06:57:51 PM PDT 24
Finished Jul 22 06:58:03 PM PDT 24
Peak memory 199920 kb
Host smart-64af5d0f-a1aa-4513-9411-e7bb23f1aed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347733664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2347733664
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.560693145
Short name T31
Test name
Test status
Simulation time 2356806138 ps
CPU time 7.7 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:13 PM PDT 24
Peak memory 217136 kb
Host smart-ae837699-39db-4c3c-8662-d6dc0bb34d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560693145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.560693145
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.461065277
Short name T481
Test name
Test status
Simulation time 244495709 ps
CPU time 1.12 seconds
Started Jul 22 06:57:51 PM PDT 24
Finished Jul 22 06:58:03 PM PDT 24
Peak memory 217476 kb
Host smart-143c172c-12af-42a6-b716-9d82f787852e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461065277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.461065277
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3646823944
Short name T10
Test name
Test status
Simulation time 129410514 ps
CPU time 0.84 seconds
Started Jul 22 06:57:51 PM PDT 24
Finished Jul 22 06:58:03 PM PDT 24
Peak memory 199872 kb
Host smart-af6792c1-90e2-4843-89cd-d8a5008d5b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646823944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3646823944
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2288226484
Short name T245
Test name
Test status
Simulation time 1728794607 ps
CPU time 7.46 seconds
Started Jul 22 06:57:54 PM PDT 24
Finished Jul 22 06:58:13 PM PDT 24
Peak memory 200412 kb
Host smart-a1a15cd9-6d6f-4d4e-8396-f3993adbb33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288226484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2288226484
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.482319607
Short name T359
Test name
Test status
Simulation time 110231705 ps
CPU time 1.06 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:05 PM PDT 24
Peak memory 200220 kb
Host smart-7b2362d0-5951-44e4-beba-b1b638020426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482319607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.482319607
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3444062755
Short name T40
Test name
Test status
Simulation time 202356419 ps
CPU time 1.28 seconds
Started Jul 22 06:58:57 PM PDT 24
Finished Jul 22 06:59:02 PM PDT 24
Peak memory 200336 kb
Host smart-ac56b1de-2a89-47e7-91dd-ba4671409cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444062755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3444062755
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3675639425
Short name T289
Test name
Test status
Simulation time 10686245392 ps
CPU time 34.82 seconds
Started Jul 22 06:57:52 PM PDT 24
Finished Jul 22 06:58:37 PM PDT 24
Peak memory 208704 kb
Host smart-73f476fd-3a9c-49c0-b59a-61147287e06c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675639425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3675639425
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3323103534
Short name T528
Test name
Test status
Simulation time 473533148 ps
CPU time 2.35 seconds
Started Jul 22 06:58:58 PM PDT 24
Finished Jul 22 06:59:04 PM PDT 24
Peak memory 200144 kb
Host smart-6ecdcbad-55b0-4ebe-99be-0a77e5f77249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323103534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3323103534
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2235212506
Short name T524
Test name
Test status
Simulation time 103492452 ps
CPU time 0.96 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:05 PM PDT 24
Peak memory 200136 kb
Host smart-0a93ffa4-4c18-4ad0-b201-8d27b72cccef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235212506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2235212506
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.4168869643
Short name T444
Test name
Test status
Simulation time 68866845 ps
CPU time 0.8 seconds
Started Jul 22 06:57:55 PM PDT 24
Finished Jul 22 06:58:06 PM PDT 24
Peak memory 199892 kb
Host smart-50928f2b-9e2c-4610-911e-0266f92f3f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168869643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.4168869643
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1694399330
Short name T48
Test name
Test status
Simulation time 1223781170 ps
CPU time 5.69 seconds
Started Jul 22 06:57:50 PM PDT 24
Finished Jul 22 06:58:07 PM PDT 24
Peak memory 221764 kb
Host smart-7b525cda-3cd0-4208-b3b8-20d2a404813c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694399330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1694399330
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3816418593
Short name T137
Test name
Test status
Simulation time 243483016 ps
CPU time 1.08 seconds
Started Jul 22 06:57:59 PM PDT 24
Finished Jul 22 06:58:11 PM PDT 24
Peak memory 217484 kb
Host smart-4bd2520a-a5c4-4dbc-850e-601904052941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816418593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3816418593
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.67606234
Short name T486
Test name
Test status
Simulation time 181749579 ps
CPU time 0.88 seconds
Started Jul 22 06:57:54 PM PDT 24
Finished Jul 22 06:58:06 PM PDT 24
Peak memory 199924 kb
Host smart-79830432-f3b7-42a7-a7d9-48d1799bf577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67606234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.67606234
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1384250365
Short name T310
Test name
Test status
Simulation time 1411955944 ps
CPU time 5.87 seconds
Started Jul 22 06:57:52 PM PDT 24
Finished Jul 22 06:58:09 PM PDT 24
Peak memory 200408 kb
Host smart-3f496406-1716-4fa6-b3df-16232371b43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384250365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1384250365
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1097385576
Short name T162
Test name
Test status
Simulation time 180439074 ps
CPU time 1.23 seconds
Started Jul 22 06:57:52 PM PDT 24
Finished Jul 22 06:58:04 PM PDT 24
Peak memory 200140 kb
Host smart-5d967adf-5211-4393-9072-6d3b4a42be82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097385576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1097385576
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3324920558
Short name T174
Test name
Test status
Simulation time 196409675 ps
CPU time 1.46 seconds
Started Jul 22 06:57:51 PM PDT 24
Finished Jul 22 06:58:03 PM PDT 24
Peak memory 200408 kb
Host smart-ddaf7b0f-33f9-4e3d-9c42-ebd2cdeec0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324920558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3324920558
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2144916628
Short name T221
Test name
Test status
Simulation time 2048005404 ps
CPU time 9.55 seconds
Started Jul 22 06:57:54 PM PDT 24
Finished Jul 22 06:58:15 PM PDT 24
Peak memory 200368 kb
Host smart-440d2df2-88d9-40a0-b51b-f8c998c0ddd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144916628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2144916628
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1001482845
Short name T342
Test name
Test status
Simulation time 369069276 ps
CPU time 2.06 seconds
Started Jul 22 06:57:50 PM PDT 24
Finished Jul 22 06:58:03 PM PDT 24
Peak memory 200120 kb
Host smart-3bba24ef-fd5f-408e-b7a1-a4064f100a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001482845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1001482845
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2301972443
Short name T227
Test name
Test status
Simulation time 216943520 ps
CPU time 1.48 seconds
Started Jul 22 06:57:51 PM PDT 24
Finished Jul 22 06:58:03 PM PDT 24
Peak memory 200140 kb
Host smart-65d4779b-bceb-4bde-8151-35ede7abee50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301972443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2301972443
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1257522292
Short name T302
Test name
Test status
Simulation time 73741585 ps
CPU time 0.78 seconds
Started Jul 22 06:57:54 PM PDT 24
Finished Jul 22 06:58:06 PM PDT 24
Peak memory 199904 kb
Host smart-a5854c14-de08-4383-bd01-3e2e55edb56b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257522292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1257522292
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2151962884
Short name T34
Test name
Test status
Simulation time 1226863990 ps
CPU time 5.85 seconds
Started Jul 22 06:57:51 PM PDT 24
Finished Jul 22 06:58:08 PM PDT 24
Peak memory 217788 kb
Host smart-842d86c4-844b-40a5-b1fb-04f9f47cac7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151962884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2151962884
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3473355836
Short name T140
Test name
Test status
Simulation time 243658904 ps
CPU time 1.01 seconds
Started Jul 22 06:58:58 PM PDT 24
Finished Jul 22 06:59:03 PM PDT 24
Peak memory 217472 kb
Host smart-ce479594-b6af-490b-b7bd-c86b25d04328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473355836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3473355836
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3058224771
Short name T353
Test name
Test status
Simulation time 152401260 ps
CPU time 0.89 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:05 PM PDT 24
Peak memory 200036 kb
Host smart-71ac77d0-332b-49e7-8f5a-0cd0e592878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058224771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3058224771
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.350278372
Short name T43
Test name
Test status
Simulation time 1610339241 ps
CPU time 6.87 seconds
Started Jul 22 06:57:51 PM PDT 24
Finished Jul 22 06:58:09 PM PDT 24
Peak memory 200364 kb
Host smart-498b2555-487e-4cb9-9740-71be8f9f8d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350278372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.350278372
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2293435694
Short name T210
Test name
Test status
Simulation time 103902577 ps
CPU time 1.04 seconds
Started Jul 22 06:57:52 PM PDT 24
Finished Jul 22 06:58:04 PM PDT 24
Peak memory 200108 kb
Host smart-8a907f05-4c8a-45ea-ade7-51613f6d9b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293435694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2293435694
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2453288146
Short name T381
Test name
Test status
Simulation time 1729204554 ps
CPU time 7 seconds
Started Jul 22 06:57:54 PM PDT 24
Finished Jul 22 06:58:12 PM PDT 24
Peak memory 200408 kb
Host smart-dabf168e-8215-4afc-99a9-3e9a34004b99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453288146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2453288146
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.39446564
Short name T207
Test name
Test status
Simulation time 482621397 ps
CPU time 2.46 seconds
Started Jul 22 06:58:00 PM PDT 24
Finished Jul 22 06:58:12 PM PDT 24
Peak memory 200124 kb
Host smart-9f980f80-fd23-4188-ada0-b39580175481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39446564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.39446564
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3843137358
Short name T537
Test name
Test status
Simulation time 253659308 ps
CPU time 1.45 seconds
Started Jul 22 06:57:54 PM PDT 24
Finished Jul 22 06:58:07 PM PDT 24
Peak memory 200144 kb
Host smart-a6dd9e38-e59f-44e8-b007-bc924ad2fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843137358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3843137358
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2748937016
Short name T67
Test name
Test status
Simulation time 77403285 ps
CPU time 0.79 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:05 PM PDT 24
Peak memory 199948 kb
Host smart-b8326ccd-2a74-4f48-840b-fa7b34a589f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748937016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2748937016
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1220003784
Short name T50
Test name
Test status
Simulation time 1224591486 ps
CPU time 6.49 seconds
Started Jul 22 06:57:55 PM PDT 24
Finished Jul 22 06:58:12 PM PDT 24
Peak memory 217444 kb
Host smart-0956cc34-e35f-4cc8-b791-73c3b14e9b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220003784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1220003784
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1444850818
Short name T154
Test name
Test status
Simulation time 243615931 ps
CPU time 1.15 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:06 PM PDT 24
Peak memory 217532 kb
Host smart-990f9b8b-c132-4d05-a7e2-0ff75ea84d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444850818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1444850818
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1558454198
Short name T410
Test name
Test status
Simulation time 217708068 ps
CPU time 0.93 seconds
Started Jul 22 06:57:59 PM PDT 24
Finished Jul 22 06:58:10 PM PDT 24
Peak memory 199940 kb
Host smart-e2add95f-0969-44ce-8ef8-4451b3b407fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558454198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1558454198
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3744143801
Short name T285
Test name
Test status
Simulation time 1601331748 ps
CPU time 6.23 seconds
Started Jul 22 06:57:55 PM PDT 24
Finished Jul 22 06:58:12 PM PDT 24
Peak memory 200408 kb
Host smart-9021d9c1-79aa-47a1-9929-44051d4c8543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744143801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3744143801
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2012314771
Short name T475
Test name
Test status
Simulation time 144289909 ps
CPU time 1.12 seconds
Started Jul 22 06:57:54 PM PDT 24
Finished Jul 22 06:58:06 PM PDT 24
Peak memory 200132 kb
Host smart-a29ceaba-51cd-42d6-8064-aa92d3598d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012314771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2012314771
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.541956468
Short name T517
Test name
Test status
Simulation time 230403779 ps
CPU time 1.36 seconds
Started Jul 22 06:58:58 PM PDT 24
Finished Jul 22 06:59:02 PM PDT 24
Peak memory 200336 kb
Host smart-abfb181a-97ed-4075-8fdd-e69187792b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541956468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.541956468
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2800901573
Short name T535
Test name
Test status
Simulation time 4546224567 ps
CPU time 16.27 seconds
Started Jul 22 06:57:55 PM PDT 24
Finished Jul 22 06:58:22 PM PDT 24
Peak memory 208684 kb
Host smart-53d814b3-fc83-407a-afa9-f703b81f113a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800901573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2800901573
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3372693932
Short name T82
Test name
Test status
Simulation time 520987138 ps
CPU time 2.61 seconds
Started Jul 22 06:58:00 PM PDT 24
Finished Jul 22 06:58:12 PM PDT 24
Peak memory 200108 kb
Host smart-79aebad8-6910-4bf1-9472-9da486342c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372693932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3372693932
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.628176301
Short name T156
Test name
Test status
Simulation time 159654137 ps
CPU time 1.28 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:05 PM PDT 24
Peak memory 200340 kb
Host smart-737b5d10-d56c-4ef0-bd26-d23690a54588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628176301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.628176301
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.415151085
Short name T498
Test name
Test status
Simulation time 65532658 ps
CPU time 0.74 seconds
Started Jul 22 06:58:47 PM PDT 24
Finished Jul 22 06:58:55 PM PDT 24
Peak memory 199876 kb
Host smart-9848e4ab-593d-4f12-bbab-c29e4584312e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415151085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.415151085
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1352986880
Short name T478
Test name
Test status
Simulation time 1888680901 ps
CPU time 7.08 seconds
Started Jul 22 06:58:03 PM PDT 24
Finished Jul 22 06:58:20 PM PDT 24
Peak memory 217504 kb
Host smart-d0c5eed3-832f-4422-8823-b0924f77d26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352986880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1352986880
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3372866952
Short name T35
Test name
Test status
Simulation time 243959039 ps
CPU time 1.11 seconds
Started Jul 22 06:58:04 PM PDT 24
Finished Jul 22 06:58:14 PM PDT 24
Peak memory 217560 kb
Host smart-86d82afb-fecc-4909-85a4-1d5e89aa6380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372866952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3372866952
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2780762191
Short name T264
Test name
Test status
Simulation time 222709115 ps
CPU time 0.97 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:05 PM PDT 24
Peak memory 199948 kb
Host smart-fbbd502e-4143-4bec-a091-8aec1e6598a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780762191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2780762191
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3882326071
Short name T281
Test name
Test status
Simulation time 955786630 ps
CPU time 4.4 seconds
Started Jul 22 06:58:03 PM PDT 24
Finished Jul 22 06:58:17 PM PDT 24
Peak memory 200388 kb
Host smart-a0770014-5ef0-419d-87e8-dca045f3e51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882326071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3882326071
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2224296070
Short name T432
Test name
Test status
Simulation time 110537895 ps
CPU time 1.09 seconds
Started Jul 22 06:58:02 PM PDT 24
Finished Jul 22 06:58:13 PM PDT 24
Peak memory 200124 kb
Host smart-4ef400d8-3135-4bfb-8415-69c9828bee92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224296070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2224296070
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1627805377
Short name T338
Test name
Test status
Simulation time 127831424 ps
CPU time 1.13 seconds
Started Jul 22 06:58:58 PM PDT 24
Finished Jul 22 06:59:04 PM PDT 24
Peak memory 200384 kb
Host smart-c048dacc-610d-40ec-9c4f-ba2024fa3b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627805377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1627805377
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1689261970
Short name T413
Test name
Test status
Simulation time 4635653706 ps
CPU time 18.19 seconds
Started Jul 22 06:58:02 PM PDT 24
Finished Jul 22 06:58:30 PM PDT 24
Peak memory 200652 kb
Host smart-5f7eabb9-1de1-4ff7-8b4b-8451c52a0c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689261970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1689261970
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1472706307
Short name T318
Test name
Test status
Simulation time 254240638 ps
CPU time 1.77 seconds
Started Jul 22 06:58:03 PM PDT 24
Finished Jul 22 06:58:14 PM PDT 24
Peak memory 200108 kb
Host smart-6f963ecc-7ec2-4c21-b22f-683a9b0b3585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472706307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1472706307
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.49527246
Short name T202
Test name
Test status
Simulation time 176776523 ps
CPU time 1.25 seconds
Started Jul 22 06:58:00 PM PDT 24
Finished Jul 22 06:58:11 PM PDT 24
Peak memory 200216 kb
Host smart-785df0eb-5b35-4730-b642-706fb87ebdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49527246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.49527246
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.164021709
Short name T351
Test name
Test status
Simulation time 60649722 ps
CPU time 0.73 seconds
Started Jul 22 06:58:04 PM PDT 24
Finished Jul 22 06:58:14 PM PDT 24
Peak memory 200016 kb
Host smart-56fb73d9-18ed-4042-8e1c-13a67490a862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164021709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.164021709
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.853987566
Short name T385
Test name
Test status
Simulation time 1889133650 ps
CPU time 8.09 seconds
Started Jul 22 06:58:04 PM PDT 24
Finished Jul 22 06:58:21 PM PDT 24
Peak memory 221480 kb
Host smart-dacb5421-3c43-4fb4-bdc2-0b8dbd61a439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853987566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.853987566
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3885793607
Short name T135
Test name
Test status
Simulation time 244911856 ps
CPU time 1.12 seconds
Started Jul 22 06:58:05 PM PDT 24
Finished Jul 22 06:58:15 PM PDT 24
Peak memory 217484 kb
Host smart-d11ae7c7-2fce-4792-b6e5-2884354871ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885793607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3885793607
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1744389881
Short name T272
Test name
Test status
Simulation time 203565560 ps
CPU time 0.96 seconds
Started Jul 22 06:58:04 PM PDT 24
Finished Jul 22 06:58:15 PM PDT 24
Peak memory 199956 kb
Host smart-6b92d4a5-8205-4ccc-ac7a-44e120258742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744389881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1744389881
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.4185908129
Short name T252
Test name
Test status
Simulation time 903039870 ps
CPU time 4.88 seconds
Started Jul 22 06:58:03 PM PDT 24
Finished Jul 22 06:58:17 PM PDT 24
Peak memory 200484 kb
Host smart-ac5cff9c-0d6d-4be0-8f9e-7d1889bf8e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185908129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.4185908129
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3491138271
Short name T350
Test name
Test status
Simulation time 108573805 ps
CPU time 1.06 seconds
Started Jul 22 06:58:06 PM PDT 24
Finished Jul 22 06:58:16 PM PDT 24
Peak memory 199888 kb
Host smart-10bf76ab-af8c-43af-bb97-49153629d0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491138271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3491138271
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3436897235
Short name T199
Test name
Test status
Simulation time 266536503 ps
CPU time 1.56 seconds
Started Jul 22 06:59:05 PM PDT 24
Finished Jul 22 06:59:15 PM PDT 24
Peak memory 200224 kb
Host smart-773858e9-23be-46dc-967d-2bfa182db184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436897235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3436897235
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2564883302
Short name T461
Test name
Test status
Simulation time 372494084 ps
CPU time 2.06 seconds
Started Jul 22 06:58:04 PM PDT 24
Finished Jul 22 06:58:15 PM PDT 24
Peak memory 200228 kb
Host smart-cf5404a5-df6c-4b3f-aad9-00113958a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564883302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2564883302
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.327425100
Short name T269
Test name
Test status
Simulation time 102035854 ps
CPU time 0.92 seconds
Started Jul 22 06:58:04 PM PDT 24
Finished Jul 22 06:58:14 PM PDT 24
Peak memory 200064 kb
Host smart-2861eb17-bf3e-4b87-a244-6d9c5e1496e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327425100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.327425100
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3065309889
Short name T370
Test name
Test status
Simulation time 69152169 ps
CPU time 0.78 seconds
Started Jul 22 06:56:39 PM PDT 24
Finished Jul 22 06:57:02 PM PDT 24
Peak memory 199936 kb
Host smart-9bf2af7e-2393-4b99-80bb-c9ed2acbbb4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065309889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3065309889
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3796450111
Short name T337
Test name
Test status
Simulation time 1223169144 ps
CPU time 5.32 seconds
Started Jul 22 06:56:40 PM PDT 24
Finished Jul 22 06:57:07 PM PDT 24
Peak memory 217724 kb
Host smart-88f31047-b23f-4453-9f2a-b6e9e2d52a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796450111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3796450111
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.81443788
Short name T495
Test name
Test status
Simulation time 243949706 ps
CPU time 1.15 seconds
Started Jul 22 06:56:40 PM PDT 24
Finished Jul 22 06:57:03 PM PDT 24
Peak memory 217544 kb
Host smart-04e27dea-15cc-4a32-b232-85d221f3e576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81443788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.81443788
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2494787444
Short name T386
Test name
Test status
Simulation time 106021881 ps
CPU time 0.73 seconds
Started Jul 22 06:56:48 PM PDT 24
Finished Jul 22 06:57:05 PM PDT 24
Peak memory 199648 kb
Host smart-2b0ef6dc-04fd-41ee-af9d-d99f50aa7b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494787444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2494787444
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.872522110
Short name T363
Test name
Test status
Simulation time 1876829933 ps
CPU time 7.76 seconds
Started Jul 22 06:56:39 PM PDT 24
Finished Jul 22 06:57:09 PM PDT 24
Peak memory 200452 kb
Host smart-65e5cfa4-b0f5-4c2b-b2aa-63f600506eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872522110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.872522110
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1233330115
Short name T265
Test name
Test status
Simulation time 167199601 ps
CPU time 1.18 seconds
Started Jul 22 06:56:38 PM PDT 24
Finished Jul 22 06:57:02 PM PDT 24
Peak memory 199980 kb
Host smart-887e220f-402a-49b3-9403-82a1ccdbc8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233330115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1233330115
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1727088567
Short name T412
Test name
Test status
Simulation time 249149564 ps
CPU time 1.54 seconds
Started Jul 22 06:56:40 PM PDT 24
Finished Jul 22 06:57:03 PM PDT 24
Peak memory 200272 kb
Host smart-8297020a-4285-4533-9264-11721b6a1bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727088567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1727088567
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3512253052
Short name T214
Test name
Test status
Simulation time 4510942404 ps
CPU time 22.2 seconds
Started Jul 22 06:56:42 PM PDT 24
Finished Jul 22 06:57:24 PM PDT 24
Peak memory 216892 kb
Host smart-b92d0606-397e-4273-9491-31f55099dc9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512253052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3512253052
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.846523301
Short name T84
Test name
Test status
Simulation time 433608360 ps
CPU time 2.3 seconds
Started Jul 22 06:56:47 PM PDT 24
Finished Jul 22 06:57:06 PM PDT 24
Peak memory 208368 kb
Host smart-a68cc56d-bbf0-4ec2-8b4c-e098693aed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846523301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.846523301
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.311883093
Short name T147
Test name
Test status
Simulation time 152026815 ps
CPU time 1.18 seconds
Started Jul 22 06:58:21 PM PDT 24
Finished Jul 22 06:58:28 PM PDT 24
Peak memory 200128 kb
Host smart-71f4741f-a850-4c39-850f-ae4394cdaae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311883093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.311883093
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2484491674
Short name T142
Test name
Test status
Simulation time 76737426 ps
CPU time 0.82 seconds
Started Jul 22 06:58:04 PM PDT 24
Finished Jul 22 06:58:14 PM PDT 24
Peak memory 199948 kb
Host smart-1d844cd0-9467-437c-a4e1-9304060a38d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484491674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2484491674
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3548841676
Short name T195
Test name
Test status
Simulation time 243824045 ps
CPU time 1.05 seconds
Started Jul 22 06:58:05 PM PDT 24
Finished Jul 22 06:58:15 PM PDT 24
Peak memory 217404 kb
Host smart-e2071b8a-c236-486d-b661-ab85373b5661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548841676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3548841676
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.997035914
Short name T280
Test name
Test status
Simulation time 111955453 ps
CPU time 0.78 seconds
Started Jul 22 06:58:05 PM PDT 24
Finished Jul 22 06:58:14 PM PDT 24
Peak memory 199952 kb
Host smart-fa858d77-e348-46a1-aa17-a3c1bd0054fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997035914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.997035914
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1668500719
Short name T129
Test name
Test status
Simulation time 743663700 ps
CPU time 3.86 seconds
Started Jul 22 06:58:47 PM PDT 24
Finished Jul 22 06:58:58 PM PDT 24
Peak memory 200356 kb
Host smart-a9dcac53-c4e3-4fa3-93e4-963364dd212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668500719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1668500719
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.668355831
Short name T367
Test name
Test status
Simulation time 107485866 ps
CPU time 1.05 seconds
Started Jul 22 06:58:03 PM PDT 24
Finished Jul 22 06:58:13 PM PDT 24
Peak memory 200132 kb
Host smart-50bbe58f-ec4c-48c8-b4fa-5332abbbde0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668355831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.668355831
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.986210034
Short name T192
Test name
Test status
Simulation time 122373424 ps
CPU time 1.28 seconds
Started Jul 22 06:58:02 PM PDT 24
Finished Jul 22 06:58:12 PM PDT 24
Peak memory 200344 kb
Host smart-e1edb37e-0aad-4e12-9539-d76eadbdcd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986210034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.986210034
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.409276573
Short name T255
Test name
Test status
Simulation time 14028481279 ps
CPU time 48.82 seconds
Started Jul 22 06:58:04 PM PDT 24
Finished Jul 22 06:59:02 PM PDT 24
Peak memory 208668 kb
Host smart-b5d0afe4-10bd-4c2d-97c0-2ffa1e43917c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409276573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.409276573
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2148517791
Short name T297
Test name
Test status
Simulation time 365246511 ps
CPU time 2.03 seconds
Started Jul 22 06:58:03 PM PDT 24
Finished Jul 22 06:58:15 PM PDT 24
Peak memory 200148 kb
Host smart-d99841dd-fb6a-450e-8f84-514dd92e08fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148517791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2148517791
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3671397295
Short name T469
Test name
Test status
Simulation time 194986201 ps
CPU time 1.25 seconds
Started Jul 22 06:58:02 PM PDT 24
Finished Jul 22 06:58:13 PM PDT 24
Peak memory 200120 kb
Host smart-cef101f3-8378-487c-b150-f234f622154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671397295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3671397295
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2071393864
Short name T172
Test name
Test status
Simulation time 80358730 ps
CPU time 0.79 seconds
Started Jul 22 06:58:16 PM PDT 24
Finished Jul 22 06:58:22 PM PDT 24
Peak memory 199920 kb
Host smart-2632284d-a39f-469a-8969-62de88732218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071393864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2071393864
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2158135900
Short name T525
Test name
Test status
Simulation time 1225157950 ps
CPU time 5.54 seconds
Started Jul 22 06:58:03 PM PDT 24
Finished Jul 22 06:58:18 PM PDT 24
Peak memory 217772 kb
Host smart-975dfd42-bb10-4201-b31e-b44ef520dbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158135900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2158135900
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3174237123
Short name T196
Test name
Test status
Simulation time 243732115 ps
CPU time 1.07 seconds
Started Jul 22 06:58:06 PM PDT 24
Finished Jul 22 06:58:16 PM PDT 24
Peak memory 217484 kb
Host smart-34277353-a17a-4e76-9185-ca8ed614fc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174237123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3174237123
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2980782516
Short name T301
Test name
Test status
Simulation time 130579533 ps
CPU time 0.84 seconds
Started Jul 22 06:58:02 PM PDT 24
Finished Jul 22 06:58:12 PM PDT 24
Peak memory 199952 kb
Host smart-17e2913c-be17-4821-860d-bd30b11978a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980782516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2980782516
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.474386076
Short name T458
Test name
Test status
Simulation time 904237575 ps
CPU time 4.59 seconds
Started Jul 22 06:58:05 PM PDT 24
Finished Jul 22 06:58:19 PM PDT 24
Peak memory 200420 kb
Host smart-3bbc335a-5bfa-4fbe-8b84-3e8c120c0f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474386076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.474386076
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.898590646
Short name T223
Test name
Test status
Simulation time 108699288 ps
CPU time 1.03 seconds
Started Jul 22 06:59:05 PM PDT 24
Finished Jul 22 06:59:14 PM PDT 24
Peak memory 199936 kb
Host smart-f9704b9c-45a5-421a-8568-5e7e77328313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898590646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.898590646
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.208004536
Short name T451
Test name
Test status
Simulation time 113946576 ps
CPU time 1.18 seconds
Started Jul 22 06:58:03 PM PDT 24
Finished Jul 22 06:58:14 PM PDT 24
Peak memory 200368 kb
Host smart-0036919d-77d1-436d-96d1-6bd6f3c0e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208004536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.208004536
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3287823508
Short name T95
Test name
Test status
Simulation time 4786642857 ps
CPU time 17.09 seconds
Started Jul 22 06:58:04 PM PDT 24
Finished Jul 22 06:58:30 PM PDT 24
Peak memory 200536 kb
Host smart-54efa178-34ad-481a-bb20-d08dc894b7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287823508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3287823508
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2214664283
Short name T532
Test name
Test status
Simulation time 371610051 ps
CPU time 2.54 seconds
Started Jul 22 06:58:06 PM PDT 24
Finished Jul 22 06:58:17 PM PDT 24
Peak memory 199904 kb
Host smart-c9ec89b7-9e7f-4951-af9c-7ef2c9f6452e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214664283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2214664283
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2539552294
Short name T436
Test name
Test status
Simulation time 226996403 ps
CPU time 1.38 seconds
Started Jul 22 06:58:01 PM PDT 24
Finished Jul 22 06:58:12 PM PDT 24
Peak memory 200128 kb
Host smart-ff162eac-745c-455d-aa3c-12e87b569528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539552294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2539552294
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1846467849
Short name T506
Test name
Test status
Simulation time 64193349 ps
CPU time 0.76 seconds
Started Jul 22 06:59:52 PM PDT 24
Finished Jul 22 07:00:04 PM PDT 24
Peak memory 199884 kb
Host smart-2df7988a-9807-4e42-bb6b-27a29ea47e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846467849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1846467849
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3966256519
Short name T26
Test name
Test status
Simulation time 2339890677 ps
CPU time 8.33 seconds
Started Jul 22 06:58:38 PM PDT 24
Finished Jul 22 06:58:51 PM PDT 24
Peak memory 217944 kb
Host smart-9b473773-67e9-45a5-8030-8fed2ae0f8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966256519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3966256519
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1153818430
Short name T388
Test name
Test status
Simulation time 244158241 ps
CPU time 1.06 seconds
Started Jul 22 06:58:16 PM PDT 24
Finished Jul 22 06:58:22 PM PDT 24
Peak memory 217432 kb
Host smart-5f16a9fa-90ad-40d6-826e-c812c2c11720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153818430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1153818430
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.4287940062
Short name T19
Test name
Test status
Simulation time 87021791 ps
CPU time 0.74 seconds
Started Jul 22 06:58:17 PM PDT 24
Finished Jul 22 06:58:22 PM PDT 24
Peak memory 199904 kb
Host smart-6bd7a3fc-beed-4357-ab8f-c5066987c828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287940062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.4287940062
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3049902211
Short name T75
Test name
Test status
Simulation time 809786563 ps
CPU time 4.01 seconds
Started Jul 22 06:58:24 PM PDT 24
Finished Jul 22 06:58:32 PM PDT 24
Peak memory 200424 kb
Host smart-714797fd-8f51-4378-9afd-4359b5d92e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049902211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3049902211
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1681429550
Short name T540
Test name
Test status
Simulation time 179278774 ps
CPU time 1.19 seconds
Started Jul 22 06:58:37 PM PDT 24
Finished Jul 22 06:58:44 PM PDT 24
Peak memory 199736 kb
Host smart-af17bb1c-48e0-498b-b87a-cc98f3369e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681429550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1681429550
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3321946952
Short name T158
Test name
Test status
Simulation time 187618259 ps
CPU time 1.35 seconds
Started Jul 22 06:58:19 PM PDT 24
Finished Jul 22 06:58:27 PM PDT 24
Peak memory 200376 kb
Host smart-c69127e6-2015-4247-b13a-17dce5034330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321946952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3321946952
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2746019577
Short name T215
Test name
Test status
Simulation time 146900743 ps
CPU time 1.04 seconds
Started Jul 22 06:58:22 PM PDT 24
Finished Jul 22 06:58:29 PM PDT 24
Peak memory 200128 kb
Host smart-8065017f-5b29-470b-86be-ef936be78637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746019577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2746019577
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3000953013
Short name T39
Test name
Test status
Simulation time 304412910 ps
CPU time 1.98 seconds
Started Jul 22 06:59:52 PM PDT 24
Finished Jul 22 07:00:05 PM PDT 24
Peak memory 208296 kb
Host smart-83e40089-89ca-4e35-b32c-a96ec8646fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000953013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3000953013
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2317113997
Short name T166
Test name
Test status
Simulation time 91275116 ps
CPU time 0.86 seconds
Started Jul 22 06:58:24 PM PDT 24
Finished Jul 22 06:58:29 PM PDT 24
Peak memory 200216 kb
Host smart-2e2ae59b-2d5e-40f1-8599-0eec678cd84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317113997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2317113997
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.4012897463
Short name T250
Test name
Test status
Simulation time 83534973 ps
CPU time 0.84 seconds
Started Jul 22 06:58:18 PM PDT 24
Finished Jul 22 06:58:25 PM PDT 24
Peak memory 199856 kb
Host smart-fa83b0cc-71f7-44a4-8500-accadbd1a2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012897463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.4012897463
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.204625150
Short name T27
Test name
Test status
Simulation time 1886122237 ps
CPU time 7.7 seconds
Started Jul 22 06:58:18 PM PDT 24
Finished Jul 22 06:58:32 PM PDT 24
Peak memory 217872 kb
Host smart-70f5d25c-8a6e-4e0a-9492-dd27c8020843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204625150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.204625150
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2086503823
Short name T144
Test name
Test status
Simulation time 244445406 ps
CPU time 1.17 seconds
Started Jul 22 06:58:19 PM PDT 24
Finished Jul 22 06:58:26 PM PDT 24
Peak memory 217404 kb
Host smart-2cf87864-1024-431c-8d54-3cb3742781c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086503823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2086503823
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2479007917
Short name T333
Test name
Test status
Simulation time 93333110 ps
CPU time 0.74 seconds
Started Jul 22 06:58:29 PM PDT 24
Finished Jul 22 06:58:35 PM PDT 24
Peak memory 199928 kb
Host smart-449d38ae-8a20-44e1-ba0a-3ec1981591ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479007917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2479007917
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1624368041
Short name T364
Test name
Test status
Simulation time 1102373963 ps
CPU time 5.76 seconds
Started Jul 22 06:58:20 PM PDT 24
Finished Jul 22 06:58:32 PM PDT 24
Peak memory 200388 kb
Host smart-2eefa7f5-b098-411a-a292-65cdc2c5e878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624368041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1624368041
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3713134345
Short name T480
Test name
Test status
Simulation time 174734713 ps
CPU time 1.26 seconds
Started Jul 22 06:58:18 PM PDT 24
Finished Jul 22 06:58:26 PM PDT 24
Peak memory 200116 kb
Host smart-56345351-af3f-4095-bf25-f36f5ff3b436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713134345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3713134345
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1365235653
Short name T204
Test name
Test status
Simulation time 113495376 ps
CPU time 1.19 seconds
Started Jul 22 06:58:16 PM PDT 24
Finished Jul 22 06:58:22 PM PDT 24
Peak memory 200364 kb
Host smart-d44a42f9-5c15-4118-9578-236957c23554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365235653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1365235653
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.647680266
Short name T188
Test name
Test status
Simulation time 3493173883 ps
CPU time 15.95 seconds
Started Jul 22 06:59:38 PM PDT 24
Finished Jul 22 07:00:10 PM PDT 24
Peak memory 208672 kb
Host smart-c7fd3de0-fe91-4eef-8813-dc30265e043f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647680266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.647680266
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1798535565
Short name T127
Test name
Test status
Simulation time 498623739 ps
CPU time 2.54 seconds
Started Jul 22 06:58:37 PM PDT 24
Finished Jul 22 06:58:46 PM PDT 24
Peak memory 199796 kb
Host smart-63113c16-1a0e-4770-a5e3-aa78ab9a5bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798535565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1798535565
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2577540479
Short name T534
Test name
Test status
Simulation time 249944813 ps
CPU time 1.42 seconds
Started Jul 22 06:58:17 PM PDT 24
Finished Jul 22 06:58:25 PM PDT 24
Peak memory 200108 kb
Host smart-5200ec39-7edd-461f-9efe-aee5d335e16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577540479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2577540479
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2809891243
Short name T514
Test name
Test status
Simulation time 71036112 ps
CPU time 0.77 seconds
Started Jul 22 06:58:21 PM PDT 24
Finished Jul 22 06:58:28 PM PDT 24
Peak memory 199912 kb
Host smart-5de4df69-ca41-4239-8ee6-5da12c0f6284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809891243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2809891243
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.750513786
Short name T331
Test name
Test status
Simulation time 1892208374 ps
CPU time 7.74 seconds
Started Jul 22 06:58:19 PM PDT 24
Finished Jul 22 06:58:33 PM PDT 24
Peak memory 217852 kb
Host smart-e4c1376b-443b-413c-b339-5224c6087333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750513786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.750513786
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2025441834
Short name T324
Test name
Test status
Simulation time 244709208 ps
CPU time 1.09 seconds
Started Jul 22 06:58:17 PM PDT 24
Finished Jul 22 06:58:24 PM PDT 24
Peak memory 217484 kb
Host smart-1c3d4f77-2670-4370-8e5e-ec2c05bd5438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025441834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2025441834
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.52192559
Short name T13
Test name
Test status
Simulation time 101567984 ps
CPU time 0.79 seconds
Started Jul 22 06:58:17 PM PDT 24
Finished Jul 22 06:58:22 PM PDT 24
Peak memory 199952 kb
Host smart-645d9840-ccac-405e-8d81-70b84db349ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52192559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.52192559
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.332363974
Short name T420
Test name
Test status
Simulation time 900374702 ps
CPU time 4.89 seconds
Started Jul 22 06:58:19 PM PDT 24
Finished Jul 22 06:58:30 PM PDT 24
Peak memory 200488 kb
Host smart-2f937947-8517-432f-9eec-0296c9bafa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332363974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.332363974
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3047314596
Short name T378
Test name
Test status
Simulation time 104034059 ps
CPU time 1.01 seconds
Started Jul 22 06:58:16 PM PDT 24
Finished Jul 22 06:58:22 PM PDT 24
Peak memory 200020 kb
Host smart-1e0f6ae6-bc68-41b6-81b9-39b569165b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047314596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3047314596
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2106994790
Short name T471
Test name
Test status
Simulation time 192065724 ps
CPU time 1.41 seconds
Started Jul 22 06:58:18 PM PDT 24
Finished Jul 22 06:58:25 PM PDT 24
Peak memory 200268 kb
Host smart-ab11f102-5be5-4387-b2b6-b2371b3133c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106994790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2106994790
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3627766078
Short name T305
Test name
Test status
Simulation time 4461404679 ps
CPU time 19.32 seconds
Started Jul 22 06:58:29 PM PDT 24
Finished Jul 22 06:58:54 PM PDT 24
Peak memory 216780 kb
Host smart-20992c19-b0a4-48a1-ad43-0f62fd083483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627766078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3627766078
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1195823664
Short name T448
Test name
Test status
Simulation time 123493664 ps
CPU time 1.58 seconds
Started Jul 22 06:58:28 PM PDT 24
Finished Jul 22 06:58:35 PM PDT 24
Peak memory 208308 kb
Host smart-6f37d9da-0d7e-4f21-9c42-1fb505d8c185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195823664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1195823664
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1432397303
Short name T387
Test name
Test status
Simulation time 140575936 ps
CPU time 1.19 seconds
Started Jul 22 06:58:32 PM PDT 24
Finished Jul 22 06:58:39 PM PDT 24
Peak memory 200144 kb
Host smart-a01020be-3e5f-456e-b4c7-19a4cbcb77db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432397303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1432397303
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1018237698
Short name T391
Test name
Test status
Simulation time 69904102 ps
CPU time 0.76 seconds
Started Jul 22 06:58:21 PM PDT 24
Finished Jul 22 06:58:28 PM PDT 24
Peak memory 199924 kb
Host smart-d697e73c-fc63-400d-bb83-8c0e7e324fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018237698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1018237698
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.523021345
Short name T422
Test name
Test status
Simulation time 2175422659 ps
CPU time 7.51 seconds
Started Jul 22 06:59:38 PM PDT 24
Finished Jul 22 07:00:02 PM PDT 24
Peak memory 216960 kb
Host smart-d13aad71-f760-4bc8-9be1-58e7ab300fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523021345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.523021345
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.768929281
Short name T335
Test name
Test status
Simulation time 248082155 ps
CPU time 1.05 seconds
Started Jul 22 06:58:17 PM PDT 24
Finished Jul 22 06:58:24 PM PDT 24
Peak memory 217392 kb
Host smart-b9f6f965-0ade-43a2-878d-fb5c4f72c327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768929281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.768929281
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3628486952
Short name T247
Test name
Test status
Simulation time 218327092 ps
CPU time 0.9 seconds
Started Jul 22 06:58:48 PM PDT 24
Finished Jul 22 06:58:55 PM PDT 24
Peak memory 199940 kb
Host smart-6d8dc490-6d63-4af6-9dd1-09985e7fc6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628486952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3628486952
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1643629575
Short name T203
Test name
Test status
Simulation time 884172786 ps
CPU time 4.53 seconds
Started Jul 22 06:58:26 PM PDT 24
Finished Jul 22 06:58:35 PM PDT 24
Peak memory 200404 kb
Host smart-ae9e814f-7b4a-4bf9-9d88-998e331f9550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643629575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1643629575
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2720541477
Short name T485
Test name
Test status
Simulation time 94534022 ps
CPU time 0.97 seconds
Started Jul 22 06:59:38 PM PDT 24
Finished Jul 22 06:59:55 PM PDT 24
Peak memory 200100 kb
Host smart-0f1b9250-bbf0-48b8-bfd9-97efed4006b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720541477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2720541477
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.499941531
Short name T243
Test name
Test status
Simulation time 193450195 ps
CPU time 1.34 seconds
Started Jul 22 06:58:24 PM PDT 24
Finished Jul 22 06:58:30 PM PDT 24
Peak memory 200384 kb
Host smart-c3764d94-782c-48cf-8df6-1375a22f0ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499941531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.499941531
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.205980047
Short name T457
Test name
Test status
Simulation time 2493268051 ps
CPU time 9.04 seconds
Started Jul 22 06:58:16 PM PDT 24
Finished Jul 22 06:58:30 PM PDT 24
Peak memory 200484 kb
Host smart-5ba3fb78-e51f-4974-a8a4-6b7437de7d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205980047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.205980047
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1848181020
Short name T71
Test name
Test status
Simulation time 132582051 ps
CPU time 1.09 seconds
Started Jul 22 06:58:17 PM PDT 24
Finished Jul 22 06:58:23 PM PDT 24
Peak memory 200224 kb
Host smart-a88e72ff-0e46-4081-9039-2a25d39c5901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848181020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1848181020
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.4148495508
Short name T497
Test name
Test status
Simulation time 70158924 ps
CPU time 0.76 seconds
Started Jul 22 06:59:52 PM PDT 24
Finished Jul 22 07:00:04 PM PDT 24
Peak memory 199884 kb
Host smart-0de98247-482c-4119-bc97-820edccd7951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148495508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.4148495508
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3690206573
Short name T33
Test name
Test status
Simulation time 2345388688 ps
CPU time 9.26 seconds
Started Jul 22 06:58:21 PM PDT 24
Finished Jul 22 06:58:36 PM PDT 24
Peak memory 217328 kb
Host smart-cfc25c6c-f0b9-422a-bc92-276669421966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690206573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3690206573
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.276611122
Short name T155
Test name
Test status
Simulation time 244317164 ps
CPU time 1.17 seconds
Started Jul 22 06:58:21 PM PDT 24
Finished Jul 22 06:58:28 PM PDT 24
Peak memory 217520 kb
Host smart-475d2e0f-e359-4db6-817a-1a6e46da6825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276611122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.276611122
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.299682649
Short name T374
Test name
Test status
Simulation time 145574241 ps
CPU time 0.89 seconds
Started Jul 22 06:58:18 PM PDT 24
Finished Jul 22 06:58:25 PM PDT 24
Peak memory 199896 kb
Host smart-b0bdb170-0c3a-4ac6-87a2-891342f7752c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299682649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.299682649
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3674792479
Short name T98
Test name
Test status
Simulation time 961330544 ps
CPU time 4.85 seconds
Started Jul 22 06:58:38 PM PDT 24
Finished Jul 22 06:58:48 PM PDT 24
Peak memory 200440 kb
Host smart-111b35a8-7af5-4150-b92f-dfeaf61fd937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674792479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3674792479
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2674985844
Short name T136
Test name
Test status
Simulation time 188064096 ps
CPU time 1.28 seconds
Started Jul 22 06:58:21 PM PDT 24
Finished Jul 22 06:58:28 PM PDT 24
Peak memory 200132 kb
Host smart-5326a3c6-ec00-4f49-9006-e521a6fe32bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674985844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2674985844
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.354652703
Short name T165
Test name
Test status
Simulation time 194824655 ps
CPU time 1.35 seconds
Started Jul 22 06:58:24 PM PDT 24
Finished Jul 22 06:58:30 PM PDT 24
Peak memory 200420 kb
Host smart-47ccce87-6643-4e48-9f82-9ae31613561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354652703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.354652703
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.410273916
Short name T339
Test name
Test status
Simulation time 722829536 ps
CPU time 3.51 seconds
Started Jul 22 06:58:17 PM PDT 24
Finished Jul 22 06:58:25 PM PDT 24
Peak memory 200344 kb
Host smart-286c6eba-d1d0-43b0-8024-c13389f1d41d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410273916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.410273916
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.513917488
Short name T479
Test name
Test status
Simulation time 277027624 ps
CPU time 1.87 seconds
Started Jul 22 06:58:20 PM PDT 24
Finished Jul 22 06:58:28 PM PDT 24
Peak memory 200128 kb
Host smart-45467786-1632-4fc4-b753-d25ec48d42dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513917488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.513917488
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3317088200
Short name T544
Test name
Test status
Simulation time 168571649 ps
CPU time 1.31 seconds
Started Jul 22 06:58:29 PM PDT 24
Finished Jul 22 06:58:36 PM PDT 24
Peak memory 200296 kb
Host smart-f194603b-bfa7-44b4-ad23-142e2a046b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317088200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3317088200
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3065847281
Short name T237
Test name
Test status
Simulation time 78492881 ps
CPU time 0.81 seconds
Started Jul 22 06:58:33 PM PDT 24
Finished Jul 22 06:58:40 PM PDT 24
Peak memory 199936 kb
Host smart-5d6d421e-0379-4495-b69e-07a9b807a9ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065847281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3065847281
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1782581924
Short name T493
Test name
Test status
Simulation time 2360637379 ps
CPU time 8.54 seconds
Started Jul 22 06:58:29 PM PDT 24
Finished Jul 22 06:58:43 PM PDT 24
Peak memory 221820 kb
Host smart-12344b3b-663c-4c95-b542-5986e9dfc671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782581924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1782581924
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.218724545
Short name T229
Test name
Test status
Simulation time 243984780 ps
CPU time 1.12 seconds
Started Jul 22 06:58:33 PM PDT 24
Finished Jul 22 06:58:41 PM PDT 24
Peak memory 217584 kb
Host smart-2375c2bb-11f3-4a12-9169-1271c9033f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218724545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.218724545
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1825453993
Short name T418
Test name
Test status
Simulation time 109651703 ps
CPU time 0.77 seconds
Started Jul 22 06:59:52 PM PDT 24
Finished Jul 22 07:00:04 PM PDT 24
Peak memory 199900 kb
Host smart-20bb60cb-e391-4cf6-9177-9f2fb5e56c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825453993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1825453993
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.155987442
Short name T125
Test name
Test status
Simulation time 1380341731 ps
CPU time 5.13 seconds
Started Jul 22 06:58:17 PM PDT 24
Finished Jul 22 06:58:27 PM PDT 24
Peak memory 200456 kb
Host smart-26fd5585-78cb-4d94-b82a-5173f917d0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155987442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.155987442
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3553860384
Short name T375
Test name
Test status
Simulation time 183908007 ps
CPU time 1.18 seconds
Started Jul 22 06:58:30 PM PDT 24
Finished Jul 22 06:58:38 PM PDT 24
Peak memory 200116 kb
Host smart-87060ee8-1d38-4702-a762-3437b2f33852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553860384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3553860384
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3510705302
Short name T138
Test name
Test status
Simulation time 110532616 ps
CPU time 1.18 seconds
Started Jul 22 06:59:52 PM PDT 24
Finished Jul 22 07:00:04 PM PDT 24
Peak memory 200292 kb
Host smart-d7a324b6-72e9-430c-a487-d816bb837648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510705302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3510705302
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.871236221
Short name T193
Test name
Test status
Simulation time 4150318221 ps
CPU time 17.66 seconds
Started Jul 22 06:58:32 PM PDT 24
Finished Jul 22 06:58:56 PM PDT 24
Peak memory 200500 kb
Host smart-143c3845-af6d-4c64-9954-aa89d209534e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871236221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.871236221
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.131487524
Short name T270
Test name
Test status
Simulation time 306651330 ps
CPU time 2.01 seconds
Started Jul 22 06:58:29 PM PDT 24
Finished Jul 22 06:58:38 PM PDT 24
Peak memory 208428 kb
Host smart-eff15bc0-fedc-44ab-a9e6-71588188620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131487524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.131487524
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3386732036
Short name T516
Test name
Test status
Simulation time 113704029 ps
CPU time 1.04 seconds
Started Jul 22 06:58:18 PM PDT 24
Finished Jul 22 06:58:26 PM PDT 24
Peak memory 200156 kb
Host smart-8ab4669b-7033-41af-8a9a-610c3d748582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386732036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3386732036
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1026896428
Short name T212
Test name
Test status
Simulation time 77330100 ps
CPU time 0.83 seconds
Started Jul 22 06:58:34 PM PDT 24
Finished Jul 22 06:58:41 PM PDT 24
Peak memory 199920 kb
Host smart-69254488-b42c-4634-91a2-242a66da8cc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026896428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1026896428
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1721295173
Short name T434
Test name
Test status
Simulation time 1227331740 ps
CPU time 5.75 seconds
Started Jul 22 06:58:35 PM PDT 24
Finished Jul 22 06:58:47 PM PDT 24
Peak memory 216876 kb
Host smart-6ded68d3-6a3a-4301-b375-7dace1200d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721295173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1721295173
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2218295825
Short name T175
Test name
Test status
Simulation time 245032585 ps
CPU time 1.05 seconds
Started Jul 22 06:58:36 PM PDT 24
Finished Jul 22 06:58:43 PM PDT 24
Peak memory 217500 kb
Host smart-fe6195bd-bb67-482b-a011-5e5dbb52decd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218295825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2218295825
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.226497000
Short name T263
Test name
Test status
Simulation time 179483843 ps
CPU time 0.85 seconds
Started Jul 22 06:58:31 PM PDT 24
Finished Jul 22 06:58:38 PM PDT 24
Peak memory 199932 kb
Host smart-a58dac4c-4bbd-464b-82e2-76595aa33f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226497000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.226497000
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.4132677718
Short name T334
Test name
Test status
Simulation time 724902225 ps
CPU time 4.17 seconds
Started Jul 22 06:58:32 PM PDT 24
Finished Jul 22 06:58:43 PM PDT 24
Peak memory 200460 kb
Host smart-ca15ffc9-687a-42f5-82c3-0c8cb596ea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132677718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.4132677718
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.459871481
Short name T299
Test name
Test status
Simulation time 155316426 ps
CPU time 1.14 seconds
Started Jul 22 06:58:29 PM PDT 24
Finished Jul 22 06:58:36 PM PDT 24
Peak memory 200220 kb
Host smart-7098d438-6918-4821-8af5-979f50fa5573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459871481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.459871481
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1649525015
Short name T328
Test name
Test status
Simulation time 190022653 ps
CPU time 1.32 seconds
Started Jul 22 06:59:53 PM PDT 24
Finished Jul 22 07:00:05 PM PDT 24
Peak memory 200340 kb
Host smart-1af90ef3-4d2f-4d23-97e4-2300af308d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649525015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1649525015
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.999747991
Short name T169
Test name
Test status
Simulation time 395701687 ps
CPU time 2.54 seconds
Started Jul 22 06:58:29 PM PDT 24
Finished Jul 22 06:58:37 PM PDT 24
Peak memory 200344 kb
Host smart-e501d234-48e9-416d-97eb-fe8696b89b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999747991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.999747991
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.221455876
Short name T510
Test name
Test status
Simulation time 129616204 ps
CPU time 1.63 seconds
Started Jul 22 06:59:53 PM PDT 24
Finished Jul 22 07:00:05 PM PDT 24
Peak memory 208092 kb
Host smart-8961d306-3aa9-47cd-ae07-83674791c601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221455876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.221455876
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2631366433
Short name T349
Test name
Test status
Simulation time 147537911 ps
CPU time 1.08 seconds
Started Jul 22 06:58:53 PM PDT 24
Finished Jul 22 06:58:57 PM PDT 24
Peak memory 200136 kb
Host smart-5275662f-e12f-439b-8004-a208796a26f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631366433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2631366433
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1345473485
Short name T189
Test name
Test status
Simulation time 53613322 ps
CPU time 0.74 seconds
Started Jul 22 06:58:31 PM PDT 24
Finished Jul 22 06:58:37 PM PDT 24
Peak memory 199956 kb
Host smart-2e01d0fd-58aa-4630-8de4-4fb99432f1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345473485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1345473485
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.165697529
Short name T279
Test name
Test status
Simulation time 1228006075 ps
CPU time 5.71 seconds
Started Jul 22 06:58:39 PM PDT 24
Finished Jul 22 06:58:49 PM PDT 24
Peak memory 221792 kb
Host smart-3e818118-0dca-4ae5-a376-18e89613c6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165697529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.165697529
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2138680968
Short name T160
Test name
Test status
Simulation time 243748265 ps
CPU time 1.12 seconds
Started Jul 22 06:58:29 PM PDT 24
Finished Jul 22 06:58:36 PM PDT 24
Peak memory 217456 kb
Host smart-82def509-021e-4e98-89ae-7a2fd8b5e766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138680968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2138680968
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.168967886
Short name T427
Test name
Test status
Simulation time 87323933 ps
CPU time 0.77 seconds
Started Jul 22 06:58:31 PM PDT 24
Finished Jul 22 06:58:38 PM PDT 24
Peak memory 199872 kb
Host smart-f2ff3304-a723-4782-9353-e11ec6fd554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168967886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.168967886
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.939986117
Short name T99
Test name
Test status
Simulation time 935253774 ps
CPU time 4.93 seconds
Started Jul 22 06:59:00 PM PDT 24
Finished Jul 22 06:59:12 PM PDT 24
Peak memory 200364 kb
Host smart-79cd26a9-866b-4ad2-8d36-8cee0230f9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939986117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.939986117
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3527660564
Short name T273
Test name
Test status
Simulation time 185704201 ps
CPU time 1.25 seconds
Started Jul 22 06:58:48 PM PDT 24
Finished Jul 22 06:58:56 PM PDT 24
Peak memory 200132 kb
Host smart-d9cdbe01-b62b-4105-8aa0-cd04e8f7bea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527660564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3527660564
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2675440875
Short name T522
Test name
Test status
Simulation time 109234367 ps
CPU time 1.26 seconds
Started Jul 22 06:58:32 PM PDT 24
Finished Jul 22 06:58:40 PM PDT 24
Peak memory 200384 kb
Host smart-e982506f-2f11-40eb-9887-73afc456facc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675440875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2675440875
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3961614080
Short name T526
Test name
Test status
Simulation time 3913899703 ps
CPU time 14.26 seconds
Started Jul 22 06:58:30 PM PDT 24
Finished Jul 22 06:58:51 PM PDT 24
Peak memory 200480 kb
Host smart-a234a931-c9dd-44fe-b526-cbe2b7193997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961614080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3961614080
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2148710978
Short name T291
Test name
Test status
Simulation time 381040542 ps
CPU time 2.44 seconds
Started Jul 22 06:58:39 PM PDT 24
Finished Jul 22 06:58:46 PM PDT 24
Peak memory 200152 kb
Host smart-5822e844-73ea-4285-9737-f757ba1b3d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148710978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2148710978
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.937029214
Short name T225
Test name
Test status
Simulation time 248450226 ps
CPU time 1.37 seconds
Started Jul 22 06:58:32 PM PDT 24
Finished Jul 22 06:58:40 PM PDT 24
Peak memory 200060 kb
Host smart-47986244-9b67-40d7-896a-87521c496d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937029214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.937029214
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3751500763
Short name T321
Test name
Test status
Simulation time 65199208 ps
CPU time 0.79 seconds
Started Jul 22 06:58:24 PM PDT 24
Finished Jul 22 06:58:30 PM PDT 24
Peak memory 199920 kb
Host smart-42d6ba1b-7f3e-425c-8362-e1e6db3d618f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751500763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3751500763
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.228690682
Short name T32
Test name
Test status
Simulation time 1231408916 ps
CPU time 6.09 seconds
Started Jul 22 06:56:52 PM PDT 24
Finished Jul 22 06:57:12 PM PDT 24
Peak memory 221740 kb
Host smart-af5bbe54-4b86-48f8-945c-317a0497eb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228690682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.228690682
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3153152697
Short name T258
Test name
Test status
Simulation time 244443148 ps
CPU time 1.1 seconds
Started Jul 22 06:56:52 PM PDT 24
Finished Jul 22 06:57:07 PM PDT 24
Peak memory 217556 kb
Host smart-0d4bb5e0-ad60-4cb7-aca6-9faecd67d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153152697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3153152697
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.704225678
Short name T8
Test name
Test status
Simulation time 203400058 ps
CPU time 0.86 seconds
Started Jul 22 06:56:40 PM PDT 24
Finished Jul 22 06:57:02 PM PDT 24
Peak memory 199868 kb
Host smart-74d42dde-78c0-4d91-85db-94e74616294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704225678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.704225678
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2697887028
Short name T248
Test name
Test status
Simulation time 600026820 ps
CPU time 3.3 seconds
Started Jul 22 06:56:48 PM PDT 24
Finished Jul 22 06:57:07 PM PDT 24
Peak memory 200220 kb
Host smart-f1713dcd-582d-4d35-a36b-6fc77e2b4fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697887028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2697887028
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3931355840
Short name T63
Test name
Test status
Simulation time 16723046277 ps
CPU time 29.4 seconds
Started Jul 22 06:57:40 PM PDT 24
Finished Jul 22 06:58:20 PM PDT 24
Peak memory 221240 kb
Host smart-2451557d-cae2-4d1b-9da2-0a7812d2d1cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931355840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3931355840
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2178497925
Short name T183
Test name
Test status
Simulation time 101281899 ps
CPU time 0.99 seconds
Started Jul 22 06:56:52 PM PDT 24
Finished Jul 22 06:57:07 PM PDT 24
Peak memory 200128 kb
Host smart-2317f586-29d7-4860-a105-5226e1df072e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178497925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2178497925
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2431927337
Short name T38
Test name
Test status
Simulation time 232662310 ps
CPU time 1.4 seconds
Started Jul 22 06:56:40 PM PDT 24
Finished Jul 22 06:57:03 PM PDT 24
Peak memory 200340 kb
Host smart-5d5dbb99-7676-4088-b6a4-1118e5c4916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431927337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2431927337
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.4150236624
Short name T267
Test name
Test status
Simulation time 4203139192 ps
CPU time 20.43 seconds
Started Jul 22 06:57:26 PM PDT 24
Finished Jul 22 06:57:52 PM PDT 24
Peak memory 208676 kb
Host smart-f0a7b58a-1c68-4d61-a711-60cc91dce82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150236624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.4150236624
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1085408457
Short name T230
Test name
Test status
Simulation time 492708767 ps
CPU time 2.91 seconds
Started Jul 22 06:56:42 PM PDT 24
Finished Jul 22 06:57:05 PM PDT 24
Peak memory 200260 kb
Host smart-a096cbd2-2b05-4616-927a-a50d508d0657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085408457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1085408457
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.820958194
Short name T400
Test name
Test status
Simulation time 78856345 ps
CPU time 0.81 seconds
Started Jul 22 06:57:23 PM PDT 24
Finished Jul 22 06:57:30 PM PDT 24
Peak memory 200136 kb
Host smart-94a22943-1aa3-474d-806a-affab1503bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820958194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.820958194
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2401054967
Short name T490
Test name
Test status
Simulation time 67772373 ps
CPU time 0.79 seconds
Started Jul 22 06:58:34 PM PDT 24
Finished Jul 22 06:58:42 PM PDT 24
Peak memory 199916 kb
Host smart-4b5abcf7-05f2-4bd6-b3bb-bb672ddb925b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401054967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2401054967
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2933291316
Short name T218
Test name
Test status
Simulation time 1225008695 ps
CPU time 5.99 seconds
Started Jul 22 06:58:34 PM PDT 24
Finished Jul 22 06:58:47 PM PDT 24
Peak memory 216844 kb
Host smart-0b4bbf5b-2dc0-4530-bf96-3c028e988dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933291316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2933291316
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1997730728
Short name T241
Test name
Test status
Simulation time 246414560 ps
CPU time 1.1 seconds
Started Jul 22 06:58:30 PM PDT 24
Finished Jul 22 06:58:37 PM PDT 24
Peak memory 217468 kb
Host smart-d8ac2b13-92e4-480e-ad3a-2c3dd85537a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997730728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1997730728
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3652090421
Short name T17
Test name
Test status
Simulation time 186401805 ps
CPU time 0.89 seconds
Started Jul 22 06:58:31 PM PDT 24
Finished Jul 22 06:58:39 PM PDT 24
Peak memory 199952 kb
Host smart-47c4c687-7f54-431d-ba29-6ea1524f3ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652090421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3652090421
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1324731068
Short name T476
Test name
Test status
Simulation time 1759049476 ps
CPU time 6.3 seconds
Started Jul 22 06:58:33 PM PDT 24
Finished Jul 22 06:58:47 PM PDT 24
Peak memory 200488 kb
Host smart-91f38526-2963-4669-b616-e65bda57103b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324731068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1324731068
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.688297133
Short name T449
Test name
Test status
Simulation time 176288575 ps
CPU time 1.15 seconds
Started Jul 22 06:58:31 PM PDT 24
Finished Jul 22 06:58:39 PM PDT 24
Peak memory 199992 kb
Host smart-460340cb-1591-49fb-9f32-6f324b8cca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688297133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.688297133
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1100532612
Short name T275
Test name
Test status
Simulation time 251829804 ps
CPU time 1.48 seconds
Started Jul 22 06:58:34 PM PDT 24
Finished Jul 22 06:58:42 PM PDT 24
Peak memory 200316 kb
Host smart-2704a3bc-cd15-4c80-b709-0f19b1eed0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100532612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1100532612
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1078290903
Short name T216
Test name
Test status
Simulation time 3891641374 ps
CPU time 13.97 seconds
Started Jul 22 06:58:31 PM PDT 24
Finished Jul 22 06:58:52 PM PDT 24
Peak memory 208720 kb
Host smart-c1700777-9a47-4c8c-ba14-08d2a0729a6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078290903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1078290903
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2194864081
Short name T231
Test name
Test status
Simulation time 137567406 ps
CPU time 1.76 seconds
Started Jul 22 06:59:53 PM PDT 24
Finished Jul 22 07:00:05 PM PDT 24
Peak memory 200148 kb
Host smart-d83a09d9-3756-4ce1-8c74-fd96d1fe8175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194864081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2194864081
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3770783951
Short name T284
Test name
Test status
Simulation time 116692146 ps
CPU time 0.97 seconds
Started Jul 22 06:58:30 PM PDT 24
Finished Jul 22 06:58:38 PM PDT 24
Peak memory 199988 kb
Host smart-a374b58c-5e3a-46e1-aeb4-f7be3aafb098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770783951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3770783951
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1436340196
Short name T527
Test name
Test status
Simulation time 93989218 ps
CPU time 0.89 seconds
Started Jul 22 06:58:50 PM PDT 24
Finished Jul 22 06:58:56 PM PDT 24
Peak memory 199928 kb
Host smart-a1797c3b-466a-466a-8024-d106d7960dd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436340196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1436340196
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1881888297
Short name T445
Test name
Test status
Simulation time 2374716429 ps
CPU time 8.41 seconds
Started Jul 22 06:58:37 PM PDT 24
Finished Jul 22 06:58:51 PM PDT 24
Peak memory 217960 kb
Host smart-85df2db4-0e44-46c7-8417-73abc9a6fe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881888297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1881888297
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3639444926
Short name T76
Test name
Test status
Simulation time 243983356 ps
CPU time 1.19 seconds
Started Jul 22 06:58:32 PM PDT 24
Finished Jul 22 06:58:40 PM PDT 24
Peak memory 217552 kb
Host smart-72f30f90-cf87-4966-98f5-d4b18fad5ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639444926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3639444926
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.591252732
Short name T358
Test name
Test status
Simulation time 196154765 ps
CPU time 0.87 seconds
Started Jul 22 06:58:35 PM PDT 24
Finished Jul 22 06:58:42 PM PDT 24
Peak memory 199928 kb
Host smart-d09bdc41-eb33-4f1a-80a0-ac8829171095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591252732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.591252732
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3413519376
Short name T520
Test name
Test status
Simulation time 1672828269 ps
CPU time 6.34 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:11 PM PDT 24
Peak memory 200492 kb
Host smart-ed6eb444-5a28-4b14-8eea-6fcb074d5918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413519376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3413519376
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2937334315
Short name T477
Test name
Test status
Simulation time 180369337 ps
CPU time 1.21 seconds
Started Jul 22 06:58:33 PM PDT 24
Finished Jul 22 06:58:41 PM PDT 24
Peak memory 200212 kb
Host smart-fa05c9b7-0f1d-4500-b935-5ab1905b0987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937334315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2937334315
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3447313030
Short name T468
Test name
Test status
Simulation time 116525510 ps
CPU time 1.2 seconds
Started Jul 22 06:59:53 PM PDT 24
Finished Jul 22 07:00:05 PM PDT 24
Peak memory 200340 kb
Host smart-a81e68fd-57e1-4d02-8ae8-e1a66954da48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447313030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3447313030
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1709022379
Short name T85
Test name
Test status
Simulation time 4305362280 ps
CPU time 19.23 seconds
Started Jul 22 06:58:31 PM PDT 24
Finished Jul 22 06:58:57 PM PDT 24
Peak memory 208564 kb
Host smart-f049190c-70d6-4eeb-98a9-55ea7747c98d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709022379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1709022379
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2786099808
Short name T271
Test name
Test status
Simulation time 116788508 ps
CPU time 1.54 seconds
Started Jul 22 06:58:34 PM PDT 24
Finished Jul 22 06:58:42 PM PDT 24
Peak memory 200208 kb
Host smart-7b9746e6-b256-4b76-a42e-fcd2380d3b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786099808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2786099808
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.4163885447
Short name T521
Test name
Test status
Simulation time 121189114 ps
CPU time 1.06 seconds
Started Jul 22 06:58:31 PM PDT 24
Finished Jul 22 06:58:39 PM PDT 24
Peak memory 200128 kb
Host smart-d6844fdc-f302-4080-98e4-fed0665eae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163885447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.4163885447
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1716001367
Short name T307
Test name
Test status
Simulation time 68898063 ps
CPU time 0.74 seconds
Started Jul 22 06:58:44 PM PDT 24
Finished Jul 22 06:58:50 PM PDT 24
Peak memory 199928 kb
Host smart-8941176a-e899-4c55-9c10-95ba2df4769d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716001367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1716001367
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1354179330
Short name T287
Test name
Test status
Simulation time 1232508077 ps
CPU time 5.74 seconds
Started Jul 22 06:59:23 PM PDT 24
Finished Jul 22 06:59:44 PM PDT 24
Peak memory 216984 kb
Host smart-252ad324-7ee1-4e4f-9dbd-125fe9d9439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354179330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1354179330
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.458347912
Short name T234
Test name
Test status
Simulation time 243873254 ps
CPU time 1.1 seconds
Started Jul 22 06:58:44 PM PDT 24
Finished Jul 22 06:58:50 PM PDT 24
Peak memory 217448 kb
Host smart-2887de04-ad89-4ad3-9524-5d39b3bbc3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458347912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.458347912
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1352064262
Short name T538
Test name
Test status
Simulation time 212952980 ps
CPU time 0.9 seconds
Started Jul 22 06:58:31 PM PDT 24
Finished Jul 22 06:58:39 PM PDT 24
Peak memory 199952 kb
Host smart-5e33be16-556f-4c01-afc3-e3613a4adb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352064262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1352064262
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3683923471
Short name T401
Test name
Test status
Simulation time 855461848 ps
CPU time 4.19 seconds
Started Jul 22 06:58:39 PM PDT 24
Finished Jul 22 06:58:48 PM PDT 24
Peak memory 200408 kb
Host smart-cea14fbe-0e91-4ed3-be2e-7dad199dd6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683923471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3683923471
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3116867923
Short name T398
Test name
Test status
Simulation time 183031890 ps
CPU time 1.25 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:05 PM PDT 24
Peak memory 200168 kb
Host smart-ad91641e-963f-4c64-a04c-3087277de4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116867923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3116867923
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.399914231
Short name T11
Test name
Test status
Simulation time 260329135 ps
CPU time 1.58 seconds
Started Jul 22 06:58:37 PM PDT 24
Finished Jul 22 06:58:44 PM PDT 24
Peak memory 200340 kb
Host smart-8232f0cb-8280-4f69-be25-740a09530106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399914231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.399914231
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3193477221
Short name T177
Test name
Test status
Simulation time 1969539196 ps
CPU time 8.53 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:59 PM PDT 24
Peak memory 200432 kb
Host smart-7ba30248-4f95-4185-97b4-127d49fc993f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193477221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3193477221
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.515283129
Short name T77
Test name
Test status
Simulation time 462155453 ps
CPU time 2.72 seconds
Started Jul 22 06:58:36 PM PDT 24
Finished Jul 22 06:58:45 PM PDT 24
Peak memory 200188 kb
Host smart-9fe72c2c-c7a2-433b-81bd-14aa9d5cc204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515283129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.515283129
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2792137232
Short name T425
Test name
Test status
Simulation time 90403319 ps
CPU time 0.86 seconds
Started Jul 22 06:58:32 PM PDT 24
Finished Jul 22 06:58:40 PM PDT 24
Peak memory 200140 kb
Host smart-97b104f2-edb0-4fdd-8c52-3ed1156e9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792137232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2792137232
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.194381140
Short name T411
Test name
Test status
Simulation time 63981890 ps
CPU time 0.75 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:51 PM PDT 24
Peak memory 199916 kb
Host smart-971be80c-b319-42b1-a333-deee7b93ebda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194381140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.194381140
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3075064295
Short name T29
Test name
Test status
Simulation time 1214965374 ps
CPU time 5.75 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:57 PM PDT 24
Peak memory 217592 kb
Host smart-075bae8c-2f85-4bc9-a1d3-bc27761985dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075064295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3075064295
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1475451106
Short name T450
Test name
Test status
Simulation time 244900741 ps
CPU time 1.05 seconds
Started Jul 22 06:58:44 PM PDT 24
Finished Jul 22 06:58:50 PM PDT 24
Peak memory 217568 kb
Host smart-0853ace2-4acd-470f-8a32-3443891a5648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475451106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1475451106
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3266602292
Short name T185
Test name
Test status
Simulation time 192657844 ps
CPU time 0.91 seconds
Started Jul 22 06:58:46 PM PDT 24
Finished Jul 22 06:58:54 PM PDT 24
Peak memory 199932 kb
Host smart-006688e5-dd4f-4c61-bec6-4201696d6755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266602292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3266602292
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1838994612
Short name T178
Test name
Test status
Simulation time 970371719 ps
CPU time 4.66 seconds
Started Jul 22 06:58:43 PM PDT 24
Finished Jul 22 06:58:52 PM PDT 24
Peak memory 200408 kb
Host smart-1a036543-182e-4d42-a45a-0e38df405998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838994612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1838994612
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2804918581
Short name T409
Test name
Test status
Simulation time 181745187 ps
CPU time 1.36 seconds
Started Jul 22 06:58:43 PM PDT 24
Finished Jul 22 06:58:49 PM PDT 24
Peak memory 200052 kb
Host smart-7b07eb49-ad19-4c42-82f7-1a35ba16f109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804918581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2804918581
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.519337606
Short name T219
Test name
Test status
Simulation time 190855745 ps
CPU time 1.34 seconds
Started Jul 22 06:59:03 PM PDT 24
Finished Jul 22 06:59:12 PM PDT 24
Peak memory 200348 kb
Host smart-9b66a200-cf1d-478d-ab95-93952e94b9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519337606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.519337606
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1388449393
Short name T96
Test name
Test status
Simulation time 4649690863 ps
CPU time 15.49 seconds
Started Jul 22 06:58:44 PM PDT 24
Finished Jul 22 06:59:05 PM PDT 24
Peak memory 200428 kb
Host smart-3649e178-549c-43a4-bbd3-dc8cf4b7d32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388449393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1388449393
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1649118033
Short name T222
Test name
Test status
Simulation time 256406924 ps
CPU time 1.78 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:54 PM PDT 24
Peak memory 200132 kb
Host smart-f09c7d9c-19c2-4a2f-96c4-43bbebae46a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649118033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1649118033
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2840902829
Short name T372
Test name
Test status
Simulation time 71655310 ps
CPU time 0.8 seconds
Started Jul 22 06:59:53 PM PDT 24
Finished Jul 22 07:00:04 PM PDT 24
Peak memory 199920 kb
Host smart-e7c56979-d702-4b13-9c56-34913a022573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840902829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2840902829
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1581705800
Short name T454
Test name
Test status
Simulation time 65939797 ps
CPU time 0.75 seconds
Started Jul 22 06:58:42 PM PDT 24
Finished Jul 22 06:58:46 PM PDT 24
Peak memory 200012 kb
Host smart-811ca26b-11f4-4b78-9855-f491421348cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581705800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1581705800
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1068217680
Short name T253
Test name
Test status
Simulation time 1898332417 ps
CPU time 7.65 seconds
Started Jul 22 06:59:11 PM PDT 24
Finished Jul 22 06:59:27 PM PDT 24
Peak memory 217760 kb
Host smart-ff74b911-7fb8-4799-b9b7-162dadcc7054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068217680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1068217680
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1125047772
Short name T254
Test name
Test status
Simulation time 245577300 ps
CPU time 1.09 seconds
Started Jul 22 06:58:40 PM PDT 24
Finished Jul 22 06:58:45 PM PDT 24
Peak memory 217544 kb
Host smart-deef873f-93fc-4491-92f2-a6ebb79e341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125047772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1125047772
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.714518410
Short name T316
Test name
Test status
Simulation time 81120477 ps
CPU time 0.76 seconds
Started Jul 22 06:58:44 PM PDT 24
Finished Jul 22 06:58:50 PM PDT 24
Peak memory 199940 kb
Host smart-0bacd243-9bd5-4b7f-bb8b-226f549a5cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714518410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.714518410
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1795271620
Short name T304
Test name
Test status
Simulation time 1725928558 ps
CPU time 6.91 seconds
Started Jul 22 06:58:47 PM PDT 24
Finished Jul 22 06:59:01 PM PDT 24
Peak memory 200260 kb
Host smart-0bc444f9-9eaf-4166-9651-d5970651bf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795271620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1795271620
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.265435193
Short name T246
Test name
Test status
Simulation time 174823289 ps
CPU time 1.25 seconds
Started Jul 22 06:58:46 PM PDT 24
Finished Jul 22 06:58:53 PM PDT 24
Peak memory 200208 kb
Host smart-0266f71a-16f2-4f9d-a791-f8fd219a36a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265435193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.265435193
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.570102277
Short name T173
Test name
Test status
Simulation time 252238014 ps
CPU time 1.49 seconds
Started Jul 22 06:58:44 PM PDT 24
Finished Jul 22 06:58:49 PM PDT 24
Peak memory 200336 kb
Host smart-37d49f7e-4310-4e2f-a9e1-c54df3b07e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570102277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.570102277
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2162996411
Short name T274
Test name
Test status
Simulation time 12057169542 ps
CPU time 40.96 seconds
Started Jul 22 06:58:47 PM PDT 24
Finished Jul 22 06:59:35 PM PDT 24
Peak memory 200472 kb
Host smart-603f1dd4-257e-4b41-8a4b-72972b4f748b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162996411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2162996411
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3369282589
Short name T4
Test name
Test status
Simulation time 157191518 ps
CPU time 2.01 seconds
Started Jul 22 06:58:42 PM PDT 24
Finished Jul 22 06:58:49 PM PDT 24
Peak memory 200152 kb
Host smart-0a72ff21-996a-418f-8f30-26efb0a3cea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369282589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3369282589
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1811135617
Short name T416
Test name
Test status
Simulation time 133827720 ps
CPU time 1.04 seconds
Started Jul 22 06:58:57 PM PDT 24
Finished Jul 22 06:59:00 PM PDT 24
Peak memory 199632 kb
Host smart-dcc2637d-7171-47dc-8ac2-41903662bcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811135617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1811135617
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1026156837
Short name T530
Test name
Test status
Simulation time 70915870 ps
CPU time 0.78 seconds
Started Jul 22 06:58:44 PM PDT 24
Finished Jul 22 06:58:50 PM PDT 24
Peak memory 199992 kb
Host smart-092fb39d-1a7f-476a-b011-0651772389a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026156837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1026156837
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2797746017
Short name T356
Test name
Test status
Simulation time 1229463779 ps
CPU time 5.53 seconds
Started Jul 22 06:58:57 PM PDT 24
Finished Jul 22 06:59:05 PM PDT 24
Peak memory 217380 kb
Host smart-d0dad0d6-1087-4880-97fa-2ec2aa9513ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797746017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2797746017
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2403093792
Short name T536
Test name
Test status
Simulation time 245580778 ps
CPU time 1.02 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:52 PM PDT 24
Peak memory 217508 kb
Host smart-0828903f-80b0-4ac5-aba4-a4b6af2cf1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403093792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2403093792
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.989391035
Short name T292
Test name
Test status
Simulation time 131070213 ps
CPU time 0.82 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:53 PM PDT 24
Peak memory 199920 kb
Host smart-bf21216c-d716-49b9-b15a-6dc637dd81da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989391035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.989391035
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.806337360
Short name T186
Test name
Test status
Simulation time 1490634562 ps
CPU time 6.61 seconds
Started Jul 22 06:58:46 PM PDT 24
Finished Jul 22 06:58:59 PM PDT 24
Peak memory 200492 kb
Host smart-b18cbe37-852b-4f9b-b5e0-98b603c57d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806337360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.806337360
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1051993102
Short name T190
Test name
Test status
Simulation time 106083015 ps
CPU time 1 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:51 PM PDT 24
Peak memory 200108 kb
Host smart-6bae8f5c-e3df-4855-9630-81122fdb5ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051993102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1051993102
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.325119970
Short name T441
Test name
Test status
Simulation time 203273087 ps
CPU time 1.36 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:51 PM PDT 24
Peak memory 200324 kb
Host smart-576af6a6-5187-480b-8a6a-310108c5d102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325119970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.325119970
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.438380197
Short name T366
Test name
Test status
Simulation time 11135581677 ps
CPU time 37.25 seconds
Started Jul 22 06:59:15 PM PDT 24
Finished Jul 22 07:00:03 PM PDT 24
Peak memory 208668 kb
Host smart-a70d0ba8-5408-4fd5-8738-78d1ca8df7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438380197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.438380197
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.446148219
Short name T515
Test name
Test status
Simulation time 128280090 ps
CPU time 1.78 seconds
Started Jul 22 06:58:47 PM PDT 24
Finished Jul 22 06:58:56 PM PDT 24
Peak memory 200152 kb
Host smart-3ff8626c-1336-4f71-9a82-23b3e2393764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446148219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.446148219
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3071212501
Short name T240
Test name
Test status
Simulation time 157817733 ps
CPU time 1.01 seconds
Started Jul 22 06:58:41 PM PDT 24
Finished Jul 22 06:58:46 PM PDT 24
Peak memory 200128 kb
Host smart-49daf8b0-23c1-41a1-97f4-d7a6e9f46c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071212501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3071212501
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2621023625
Short name T325
Test name
Test status
Simulation time 62989421 ps
CPU time 0.77 seconds
Started Jul 22 06:58:43 PM PDT 24
Finished Jul 22 06:58:48 PM PDT 24
Peak memory 200008 kb
Host smart-903b162b-2581-4ef0-9edb-d85212fdb6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621023625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2621023625
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4238888352
Short name T415
Test name
Test status
Simulation time 1230207803 ps
CPU time 5.42 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:56 PM PDT 24
Peak memory 221752 kb
Host smart-a7b29521-1909-4def-be41-b990822b4046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238888352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4238888352
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3804717294
Short name T519
Test name
Test status
Simulation time 243913186 ps
CPU time 1.11 seconds
Started Jul 22 06:58:47 PM PDT 24
Finished Jul 22 06:58:55 PM PDT 24
Peak memory 217472 kb
Host smart-3fdb00ab-4ba9-4393-bbb9-5692f466f67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804717294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3804717294
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3276181441
Short name T153
Test name
Test status
Simulation time 141612512 ps
CPU time 0.85 seconds
Started Jul 22 06:58:42 PM PDT 24
Finished Jul 22 06:58:47 PM PDT 24
Peak memory 199980 kb
Host smart-b6481416-7c41-416d-858d-866d1638d47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276181441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3276181441
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3838141989
Short name T100
Test name
Test status
Simulation time 663491353 ps
CPU time 3.5 seconds
Started Jul 22 06:58:43 PM PDT 24
Finished Jul 22 06:58:51 PM PDT 24
Peak memory 200404 kb
Host smart-5175d8cd-fb5f-4d65-b7a0-1cf9468bf6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838141989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3838141989
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3365763046
Short name T315
Test name
Test status
Simulation time 187360718 ps
CPU time 1.22 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:53 PM PDT 24
Peak memory 200196 kb
Host smart-a3940fd6-46cd-4b83-b1ae-97dd09ceb97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365763046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3365763046
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.87659274
Short name T184
Test name
Test status
Simulation time 110234174 ps
CPU time 1.27 seconds
Started Jul 22 06:58:44 PM PDT 24
Finished Jul 22 06:58:49 PM PDT 24
Peak memory 200320 kb
Host smart-d816c38d-a927-4af7-b5a2-16916c66e007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87659274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.87659274
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1279324975
Short name T511
Test name
Test status
Simulation time 8987652522 ps
CPU time 32.85 seconds
Started Jul 22 06:58:47 PM PDT 24
Finished Jul 22 06:59:27 PM PDT 24
Peak memory 208676 kb
Host smart-523c360e-cdf5-47c5-a50e-f0f544ed36fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279324975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1279324975
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.67728694
Short name T392
Test name
Test status
Simulation time 253068260 ps
CPU time 1.83 seconds
Started Jul 22 06:58:47 PM PDT 24
Finished Jul 22 06:58:56 PM PDT 24
Peak memory 200160 kb
Host smart-3d7bd4c1-98e0-4d5a-85f4-23c0583a7f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67728694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.67728694
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1641106068
Short name T213
Test name
Test status
Simulation time 137701860 ps
CPU time 1.23 seconds
Started Jul 22 06:58:44 PM PDT 24
Finished Jul 22 06:58:49 PM PDT 24
Peak memory 200116 kb
Host smart-32f234e4-4d09-4e6c-92c2-79a163cf9692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641106068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1641106068
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2792946478
Short name T488
Test name
Test status
Simulation time 73949131 ps
CPU time 0.84 seconds
Started Jul 22 06:59:19 PM PDT 24
Finished Jul 22 06:59:34 PM PDT 24
Peak memory 199980 kb
Host smart-ad97d06e-4b67-4f51-836e-81a5a938cd3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792946478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2792946478
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3844570987
Short name T489
Test name
Test status
Simulation time 1896304997 ps
CPU time 7.61 seconds
Started Jul 22 06:59:09 PM PDT 24
Finished Jul 22 06:59:26 PM PDT 24
Peak memory 217804 kb
Host smart-6714cdfa-449c-4733-9488-fbb137547ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844570987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3844570987
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1086207628
Short name T163
Test name
Test status
Simulation time 244528859 ps
CPU time 1.02 seconds
Started Jul 22 06:59:00 PM PDT 24
Finished Jul 22 06:59:07 PM PDT 24
Peak memory 217484 kb
Host smart-58c79ece-8c43-4149-baa1-ade574b028f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086207628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1086207628
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3805370014
Short name T306
Test name
Test status
Simulation time 81034857 ps
CPU time 0.74 seconds
Started Jul 22 06:58:45 PM PDT 24
Finished Jul 22 06:58:52 PM PDT 24
Peak memory 199944 kb
Host smart-e4977ac7-0c4d-4a95-b8a7-b73e6ee7c66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805370014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3805370014
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1164870058
Short name T382
Test name
Test status
Simulation time 776416027 ps
CPU time 4.3 seconds
Started Jul 22 06:58:43 PM PDT 24
Finished Jul 22 06:58:52 PM PDT 24
Peak memory 200420 kb
Host smart-3fe54253-34b4-47df-af5b-1ac7c646d811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164870058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1164870058
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2157173770
Short name T201
Test name
Test status
Simulation time 95533619 ps
CPU time 0.99 seconds
Started Jul 22 06:58:57 PM PDT 24
Finished Jul 22 06:59:00 PM PDT 24
Peak memory 200144 kb
Host smart-833296ce-ad37-4436-9a76-2d417b4fa4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157173770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2157173770
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.798755629
Short name T501
Test name
Test status
Simulation time 206274852 ps
CPU time 1.44 seconds
Started Jul 22 06:58:43 PM PDT 24
Finished Jul 22 06:58:48 PM PDT 24
Peak memory 200416 kb
Host smart-26689ddf-958c-4922-9b26-3903ca429573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798755629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.798755629
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.4252875220
Short name T543
Test name
Test status
Simulation time 6067622022 ps
CPU time 25.51 seconds
Started Jul 22 06:59:20 PM PDT 24
Finished Jul 22 06:59:59 PM PDT 24
Peak memory 208644 kb
Host smart-4ad7d18d-a180-4f0b-8e2d-f14f888750ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252875220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.4252875220
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.139610885
Short name T205
Test name
Test status
Simulation time 426610961 ps
CPU time 2.38 seconds
Started Jul 22 06:58:41 PM PDT 24
Finished Jul 22 06:58:47 PM PDT 24
Peak memory 208288 kb
Host smart-5dfad3f6-13e6-49b7-becf-c165ea244405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139610885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.139610885
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1249352044
Short name T383
Test name
Test status
Simulation time 123997312 ps
CPU time 0.98 seconds
Started Jul 22 06:58:43 PM PDT 24
Finished Jul 22 06:58:48 PM PDT 24
Peak memory 200088 kb
Host smart-e796b1f5-a935-4bf6-9cff-4424e4c79d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249352044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1249352044
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2885315380
Short name T396
Test name
Test status
Simulation time 74075609 ps
CPU time 0.78 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:09 PM PDT 24
Peak memory 199856 kb
Host smart-4ce7d787-48fd-4433-b75d-dd24f8b9e117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885315380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2885315380
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3910594496
Short name T369
Test name
Test status
Simulation time 2369673000 ps
CPU time 8.36 seconds
Started Jul 22 06:59:07 PM PDT 24
Finished Jul 22 06:59:23 PM PDT 24
Peak memory 217956 kb
Host smart-620bee42-00af-4304-bb09-02e6703e50dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910594496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3910594496
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.993504818
Short name T311
Test name
Test status
Simulation time 244613304 ps
CPU time 1.06 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:09 PM PDT 24
Peak memory 217500 kb
Host smart-bbb4c514-9cf9-486c-bc5a-18ce5e4a5342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993504818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.993504818
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3961281863
Short name T437
Test name
Test status
Simulation time 121069485 ps
CPU time 0.86 seconds
Started Jul 22 06:59:03 PM PDT 24
Finished Jul 22 06:59:12 PM PDT 24
Peak memory 199908 kb
Host smart-84434cb0-4676-4c2a-b72e-0ed5c648c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961281863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3961281863
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1314617700
Short name T42
Test name
Test status
Simulation time 1136368834 ps
CPU time 4.53 seconds
Started Jul 22 06:59:45 PM PDT 24
Finished Jul 22 07:00:02 PM PDT 24
Peak memory 200344 kb
Host smart-6a34307c-d4e3-4efb-a396-7f4c30602e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314617700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1314617700
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1725910119
Short name T6
Test name
Test status
Simulation time 106818998 ps
CPU time 0.99 seconds
Started Jul 22 06:59:38 PM PDT 24
Finished Jul 22 06:59:54 PM PDT 24
Peak memory 200144 kb
Host smart-2ebfd7b0-4c1b-4415-99bb-45d97b47780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725910119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1725910119
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1558203248
Short name T404
Test name
Test status
Simulation time 115731048 ps
CPU time 1.23 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:06 PM PDT 24
Peak memory 200344 kb
Host smart-a05e674f-a2cf-49b8-aeb3-8e4d1a762f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558203248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1558203248
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2504843307
Short name T120
Test name
Test status
Simulation time 2129263191 ps
CPU time 7.97 seconds
Started Jul 22 06:59:02 PM PDT 24
Finished Jul 22 06:59:17 PM PDT 24
Peak memory 209924 kb
Host smart-7fbe71bd-e1ee-49c4-9525-45a402992b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504843307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2504843307
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2355032839
Short name T343
Test name
Test status
Simulation time 531526955 ps
CPU time 3.05 seconds
Started Jul 22 06:59:02 PM PDT 24
Finished Jul 22 06:59:12 PM PDT 24
Peak memory 200140 kb
Host smart-ca566a5f-21e5-4935-81e6-3f7285af7a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355032839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2355032839
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2629741029
Short name T78
Test name
Test status
Simulation time 138529818 ps
CPU time 1.19 seconds
Started Jul 22 06:59:16 PM PDT 24
Finished Jul 22 06:59:29 PM PDT 24
Peak memory 200128 kb
Host smart-709780a7-061a-40da-9500-fa0876448693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629741029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2629741029
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1525187019
Short name T145
Test name
Test status
Simulation time 67067449 ps
CPU time 0.76 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:04 PM PDT 24
Peak memory 199936 kb
Host smart-a23a35b4-586d-4038-a80d-652f8230b885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525187019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1525187019
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.793039192
Short name T407
Test name
Test status
Simulation time 1886246154 ps
CPU time 7.06 seconds
Started Jul 22 07:00:04 PM PDT 24
Finished Jul 22 07:00:20 PM PDT 24
Peak memory 217752 kb
Host smart-864baa96-9e28-4a02-9cc4-57c927b12541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793039192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.793039192
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1569936761
Short name T464
Test name
Test status
Simulation time 245317688 ps
CPU time 1.09 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:06 PM PDT 24
Peak memory 217568 kb
Host smart-3b5f1a76-ac08-4ee1-bcb6-e81409838e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569936761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1569936761
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1637167770
Short name T429
Test name
Test status
Simulation time 122398980 ps
CPU time 0.82 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:04 PM PDT 24
Peak memory 199900 kb
Host smart-03aa27d1-be15-42b2-a7ff-ca965ee1e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637167770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1637167770
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.114517673
Short name T542
Test name
Test status
Simulation time 2076763370 ps
CPU time 7.55 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:13 PM PDT 24
Peak memory 200424 kb
Host smart-f6e89611-fc5e-43f4-bf93-a737d2851347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114517673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.114517673
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2136488726
Short name T2
Test name
Test status
Simulation time 178532606 ps
CPU time 1.2 seconds
Started Jul 22 06:59:11 PM PDT 24
Finished Jul 22 06:59:21 PM PDT 24
Peak memory 200116 kb
Host smart-281f0aff-62fd-446f-9286-3e35452b7625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136488726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2136488726
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.218006205
Short name T505
Test name
Test status
Simulation time 199534108 ps
CPU time 1.43 seconds
Started Jul 22 06:59:01 PM PDT 24
Finished Jul 22 06:59:10 PM PDT 24
Peak memory 200420 kb
Host smart-e0ade2c5-4811-4af7-887c-a3c63b707b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218006205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.218006205
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1907404145
Short name T462
Test name
Test status
Simulation time 6945340673 ps
CPU time 24.81 seconds
Started Jul 22 06:58:59 PM PDT 24
Finished Jul 22 06:59:28 PM PDT 24
Peak memory 208564 kb
Host smart-365d19d2-0b00-4148-9914-56779279ba89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907404145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1907404145
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.977249206
Short name T463
Test name
Test status
Simulation time 113705148 ps
CPU time 1.57 seconds
Started Jul 22 06:59:03 PM PDT 24
Finished Jul 22 06:59:12 PM PDT 24
Peak memory 200148 kb
Host smart-7d6ad736-d4ba-4fb0-8db5-b2e26ef2422d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977249206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.977249206
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.50457616
Short name T453
Test name
Test status
Simulation time 134914973 ps
CPU time 1.11 seconds
Started Jul 22 06:59:00 PM PDT 24
Finished Jul 22 06:59:07 PM PDT 24
Peak memory 200144 kb
Host smart-c4d8e6a7-9e03-4928-b649-930d2023d71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50457616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.50457616
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1872454458
Short name T298
Test name
Test status
Simulation time 78147356 ps
CPU time 0.83 seconds
Started Jul 22 06:56:54 PM PDT 24
Finished Jul 22 06:57:07 PM PDT 24
Peak memory 199940 kb
Host smart-bbce0630-f982-4e4f-8e4b-01844e122915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872454458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1872454458
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.420068085
Short name T25
Test name
Test status
Simulation time 1228824349 ps
CPU time 5.55 seconds
Started Jul 22 06:56:52 PM PDT 24
Finished Jul 22 06:57:11 PM PDT 24
Peak memory 221772 kb
Host smart-b586d461-5273-498b-992a-b869de963c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420068085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.420068085
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2756299945
Short name T336
Test name
Test status
Simulation time 245274253 ps
CPU time 1.06 seconds
Started Jul 22 06:56:53 PM PDT 24
Finished Jul 22 06:57:07 PM PDT 24
Peak memory 217476 kb
Host smart-eb40cadf-2320-4723-b9e3-c84d20736190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756299945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2756299945
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1865498734
Short name T533
Test name
Test status
Simulation time 138121814 ps
CPU time 0.82 seconds
Started Jul 22 06:56:53 PM PDT 24
Finished Jul 22 06:57:07 PM PDT 24
Peak memory 199952 kb
Host smart-5c2db1b9-678f-4f7d-8bd2-38e29b9afc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865498734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1865498734
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.4264134335
Short name T187
Test name
Test status
Simulation time 986957983 ps
CPU time 5.07 seconds
Started Jul 22 06:56:53 PM PDT 24
Finished Jul 22 06:57:12 PM PDT 24
Peak memory 200408 kb
Host smart-7d57b809-9c5a-403c-b6fa-13e944f4464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264134335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4264134335
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.703264115
Short name T346
Test name
Test status
Simulation time 161650028 ps
CPU time 1.19 seconds
Started Jul 22 06:56:53 PM PDT 24
Finished Jul 22 06:57:08 PM PDT 24
Peak memory 200136 kb
Host smart-dd54ff40-c18d-4dfb-b704-0f6b5fe50dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703264115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.703264115
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1787011079
Short name T344
Test name
Test status
Simulation time 192399881 ps
CPU time 1.38 seconds
Started Jul 22 06:56:53 PM PDT 24
Finished Jul 22 06:57:08 PM PDT 24
Peak memory 200324 kb
Host smart-b893e51b-564a-45cc-a8ca-ad38b51e0596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787011079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1787011079
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.4008949854
Short name T467
Test name
Test status
Simulation time 7690967912 ps
CPU time 26.9 seconds
Started Jul 22 06:56:51 PM PDT 24
Finished Jul 22 06:57:32 PM PDT 24
Peak memory 200364 kb
Host smart-3981e60b-194d-4e79-bfe5-66f2e1e37a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008949854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.4008949854
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2317602326
Short name T283
Test name
Test status
Simulation time 335121753 ps
CPU time 2.13 seconds
Started Jul 22 06:57:46 PM PDT 24
Finished Jul 22 06:58:01 PM PDT 24
Peak memory 200192 kb
Host smart-06191a8e-0098-4e8d-b600-752719e1d9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317602326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2317602326
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2981049838
Short name T355
Test name
Test status
Simulation time 141740176 ps
CPU time 1.1 seconds
Started Jul 22 06:56:52 PM PDT 24
Finished Jul 22 06:57:07 PM PDT 24
Peak memory 200120 kb
Host smart-b7cb6f6f-f021-4b75-ac49-821ac8870af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981049838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2981049838
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1540795139
Short name T168
Test name
Test status
Simulation time 77906933 ps
CPU time 0.81 seconds
Started Jul 22 06:57:08 PM PDT 24
Finished Jul 22 06:57:16 PM PDT 24
Peak memory 199932 kb
Host smart-1ca83a1d-7159-427c-bd14-8ae41b59984a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540795139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1540795139
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.599880242
Short name T314
Test name
Test status
Simulation time 2344309438 ps
CPU time 8.75 seconds
Started Jul 22 06:56:52 PM PDT 24
Finished Jul 22 06:57:15 PM PDT 24
Peak memory 221812 kb
Host smart-cf6cce58-d8f2-44e9-b140-afaab69a57c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599880242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.599880242
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2478953889
Short name T62
Test name
Test status
Simulation time 243863145 ps
CPU time 1.17 seconds
Started Jul 22 06:57:08 PM PDT 24
Finished Jul 22 06:57:16 PM PDT 24
Peak memory 217472 kb
Host smart-ba2b08f2-5e71-4efd-b115-5bedc5d022a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478953889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2478953889
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1040485303
Short name T180
Test name
Test status
Simulation time 110164962 ps
CPU time 0.81 seconds
Started Jul 22 06:56:53 PM PDT 24
Finished Jul 22 06:57:07 PM PDT 24
Peak memory 200024 kb
Host smart-c83332cc-d893-42ac-9a27-1190497255a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040485303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1040485303
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3301407869
Short name T345
Test name
Test status
Simulation time 989037991 ps
CPU time 5.19 seconds
Started Jul 22 06:56:54 PM PDT 24
Finished Jul 22 06:57:12 PM PDT 24
Peak memory 200464 kb
Host smart-4917602e-b707-44e3-9b46-89714468b0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301407869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3301407869
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2437497535
Short name T256
Test name
Test status
Simulation time 99112202 ps
CPU time 0.99 seconds
Started Jul 22 06:56:54 PM PDT 24
Finished Jul 22 06:57:08 PM PDT 24
Peak memory 200124 kb
Host smart-773d4ab2-1a37-4d39-bda3-9af4833b1ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437497535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2437497535
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1861569843
Short name T455
Test name
Test status
Simulation time 247899259 ps
CPU time 1.42 seconds
Started Jul 22 06:57:09 PM PDT 24
Finished Jul 22 06:57:17 PM PDT 24
Peak memory 200280 kb
Host smart-7bddad5c-b543-4260-996c-1ec161f6b01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861569843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1861569843
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2133655726
Short name T97
Test name
Test status
Simulation time 6371532306 ps
CPU time 28.98 seconds
Started Jul 22 06:57:07 PM PDT 24
Finished Jul 22 06:57:42 PM PDT 24
Peak memory 208752 kb
Host smart-559efff6-d7ba-44c9-9d7c-c66f027e46a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133655726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2133655726
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3916638451
Short name T545
Test name
Test status
Simulation time 151449186 ps
CPU time 1.96 seconds
Started Jul 22 06:56:53 PM PDT 24
Finished Jul 22 06:57:08 PM PDT 24
Peak memory 200168 kb
Host smart-16e60824-659e-4261-9321-dc9fda161317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916638451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3916638451
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1147098808
Short name T496
Test name
Test status
Simulation time 159898644 ps
CPU time 1.07 seconds
Started Jul 22 06:56:53 PM PDT 24
Finished Jul 22 06:57:07 PM PDT 24
Peak memory 200144 kb
Host smart-b3790eef-176b-4f1f-9a6a-dbacae9b1fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147098808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1147098808
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2397240219
Short name T152
Test name
Test status
Simulation time 65939004 ps
CPU time 0.8 seconds
Started Jul 22 06:57:09 PM PDT 24
Finished Jul 22 06:57:17 PM PDT 24
Peak memory 199936 kb
Host smart-3846b9a9-8bce-4347-bd76-b897a505b78b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397240219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2397240219
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.721516228
Short name T500
Test name
Test status
Simulation time 2345720585 ps
CPU time 8.14 seconds
Started Jul 22 06:57:10 PM PDT 24
Finished Jul 22 06:57:24 PM PDT 24
Peak memory 217184 kb
Host smart-5a6e24fa-bac9-4664-ba95-d2a21bfeb537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721516228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.721516228
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1721999330
Short name T503
Test name
Test status
Simulation time 244913353 ps
CPU time 1.09 seconds
Started Jul 22 06:57:53 PM PDT 24
Finished Jul 22 06:58:05 PM PDT 24
Peak memory 217560 kb
Host smart-11b1dfd0-abe1-4322-9d49-97ce17edb701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721999330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1721999330
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2540760948
Short name T282
Test name
Test status
Simulation time 162159570 ps
CPU time 0.98 seconds
Started Jul 22 06:57:08 PM PDT 24
Finished Jul 22 06:57:15 PM PDT 24
Peak memory 199880 kb
Host smart-dbc808f9-9181-4a8e-a3ed-cb1f25b3028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540760948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2540760948
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2922033293
Short name T277
Test name
Test status
Simulation time 1239115265 ps
CPU time 4.89 seconds
Started Jul 22 06:58:36 PM PDT 24
Finished Jul 22 06:58:47 PM PDT 24
Peak memory 200344 kb
Host smart-8b981b32-ae8d-48b9-8f8e-e6d8373654c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922033293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2922033293
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2007838943
Short name T1
Test name
Test status
Simulation time 108442349 ps
CPU time 1.04 seconds
Started Jul 22 06:57:07 PM PDT 24
Finished Jul 22 06:57:15 PM PDT 24
Peak memory 200112 kb
Host smart-6d71397d-cc41-4daa-a7bd-3b8d4ad9ba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007838943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2007838943
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.663630829
Short name T362
Test name
Test status
Simulation time 247743054 ps
CPU time 1.46 seconds
Started Jul 22 06:57:09 PM PDT 24
Finished Jul 22 06:57:18 PM PDT 24
Peak memory 200336 kb
Host smart-b19f22ad-0957-4ed9-9293-8ac56b5c1652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663630829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.663630829
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.691855372
Short name T371
Test name
Test status
Simulation time 1504253689 ps
CPU time 7.41 seconds
Started Jul 22 06:57:09 PM PDT 24
Finished Jul 22 06:57:23 PM PDT 24
Peak memory 200484 kb
Host smart-8e86fd0e-b504-48de-a961-4cf40ab26a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691855372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.691855372
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1598315564
Short name T329
Test name
Test status
Simulation time 137872068 ps
CPU time 1.84 seconds
Started Jul 22 06:57:08 PM PDT 24
Finished Jul 22 06:57:17 PM PDT 24
Peak memory 200160 kb
Host smart-bb8156fe-e1d9-485f-be82-811fdbcb40ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598315564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1598315564
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1495424043
Short name T72
Test name
Test status
Simulation time 102122084 ps
CPU time 0.94 seconds
Started Jul 22 06:57:08 PM PDT 24
Finished Jul 22 06:57:16 PM PDT 24
Peak memory 200068 kb
Host smart-399f9246-6876-44ac-9526-c62de5ffee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495424043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1495424043
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1590885068
Short name T459
Test name
Test status
Simulation time 82538012 ps
CPU time 0.78 seconds
Started Jul 22 06:58:28 PM PDT 24
Finished Jul 22 06:58:34 PM PDT 24
Peak memory 199920 kb
Host smart-d09dc8d4-3a8b-4e7c-81d6-aecf245294c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590885068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1590885068
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1702826560
Short name T417
Test name
Test status
Simulation time 1221913222 ps
CPU time 5.74 seconds
Started Jul 22 06:57:08 PM PDT 24
Finished Jul 22 06:57:20 PM PDT 24
Peak memory 217844 kb
Host smart-c1a78956-1338-409f-bff0-b7418106d10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702826560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1702826560
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2966498504
Short name T150
Test name
Test status
Simulation time 245041848 ps
CPU time 1.04 seconds
Started Jul 22 06:57:09 PM PDT 24
Finished Jul 22 06:57:17 PM PDT 24
Peak memory 217528 kb
Host smart-9855ef3d-ecf0-422f-b2af-06919a0b9fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966498504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2966498504
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3535194681
Short name T507
Test name
Test status
Simulation time 83654493 ps
CPU time 0.81 seconds
Started Jul 22 06:57:08 PM PDT 24
Finished Jul 22 06:57:15 PM PDT 24
Peak memory 200012 kb
Host smart-0de92a7d-4d42-4e9f-9773-ebc24e51a53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535194681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3535194681
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2035279519
Short name T360
Test name
Test status
Simulation time 856335120 ps
CPU time 4.7 seconds
Started Jul 22 06:57:07 PM PDT 24
Finished Jul 22 06:57:18 PM PDT 24
Peak memory 200464 kb
Host smart-81796957-67d4-4b1b-a2d7-f12429b17a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035279519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2035279519
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4103198530
Short name T442
Test name
Test status
Simulation time 156079733 ps
CPU time 1.15 seconds
Started Jul 22 06:57:09 PM PDT 24
Finished Jul 22 06:57:17 PM PDT 24
Peak memory 200128 kb
Host smart-1c7ad4f9-46a7-4ee9-8537-1b62a9a78c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103198530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4103198530
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3078852892
Short name T326
Test name
Test status
Simulation time 236320186 ps
CPU time 1.53 seconds
Started Jul 22 06:57:07 PM PDT 24
Finished Jul 22 06:57:15 PM PDT 24
Peak memory 200344 kb
Host smart-4e9ce8cd-6241-4b23-9aac-a885705342ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078852892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3078852892
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2592093478
Short name T376
Test name
Test status
Simulation time 4357324621 ps
CPU time 15.49 seconds
Started Jul 22 06:57:06 PM PDT 24
Finished Jul 22 06:57:28 PM PDT 24
Peak memory 200464 kb
Host smart-180ab5fe-dd3d-4ee8-8e75-600274888519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592093478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2592093478
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1853501678
Short name T512
Test name
Test status
Simulation time 114816602 ps
CPU time 1.47 seconds
Started Jul 22 06:57:08 PM PDT 24
Finished Jul 22 06:57:16 PM PDT 24
Peak memory 200112 kb
Host smart-9215048d-14fe-409f-9bb0-130afdd85dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853501678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1853501678
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2633559747
Short name T380
Test name
Test status
Simulation time 209624034 ps
CPU time 1.29 seconds
Started Jul 22 06:57:09 PM PDT 24
Finished Jul 22 06:57:17 PM PDT 24
Peak memory 200144 kb
Host smart-177e0cf6-d965-4d5f-b152-df0bed1c5774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633559747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2633559747
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.64155820
Short name T23
Test name
Test status
Simulation time 66321698 ps
CPU time 0.74 seconds
Started Jul 22 06:57:33 PM PDT 24
Finished Jul 22 06:57:43 PM PDT 24
Peak memory 199832 kb
Host smart-b045cf7c-e204-4c2b-a9a2-0d95656073af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64155820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.64155820
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.730192187
Short name T47
Test name
Test status
Simulation time 1218409849 ps
CPU time 5.7 seconds
Started Jul 22 06:57:21 PM PDT 24
Finished Jul 22 06:57:32 PM PDT 24
Peak memory 217788 kb
Host smart-81f70302-fa41-4473-832e-32fdb9d4b181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730192187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.730192187
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2929006015
Short name T460
Test name
Test status
Simulation time 244619085 ps
CPU time 1.11 seconds
Started Jul 22 06:57:24 PM PDT 24
Finished Jul 22 06:57:31 PM PDT 24
Peak memory 217508 kb
Host smart-aa990860-784f-4e65-b334-b25dae156833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929006015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2929006015
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2273159970
Short name T224
Test name
Test status
Simulation time 126579196 ps
CPU time 0.82 seconds
Started Jul 22 06:57:09 PM PDT 24
Finished Jul 22 06:57:17 PM PDT 24
Peak memory 200028 kb
Host smart-85cbdc7e-32d5-4836-9f5e-457e32128d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273159970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2273159970
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3354971244
Short name T93
Test name
Test status
Simulation time 1611410210 ps
CPU time 5.82 seconds
Started Jul 22 06:57:10 PM PDT 24
Finished Jul 22 06:57:23 PM PDT 24
Peak memory 200388 kb
Host smart-203e058b-fa8d-4498-91ba-43eeb8efc922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354971244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3354971244
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2216253592
Short name T482
Test name
Test status
Simulation time 103402660 ps
CPU time 0.98 seconds
Started Jul 22 06:57:20 PM PDT 24
Finished Jul 22 06:57:25 PM PDT 24
Peak memory 200128 kb
Host smart-a6123f6e-bb2a-4cb1-9da0-00c6b12108d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216253592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2216253592
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4114163259
Short name T143
Test name
Test status
Simulation time 119821382 ps
CPU time 1.24 seconds
Started Jul 22 06:57:45 PM PDT 24
Finished Jul 22 06:57:59 PM PDT 24
Peak memory 200288 kb
Host smart-3c22eb8b-7633-4277-9e38-9ce0c761ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114163259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4114163259
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.380681308
Short name T268
Test name
Test status
Simulation time 1900215279 ps
CPU time 8.74 seconds
Started Jul 22 06:57:24 PM PDT 24
Finished Jul 22 06:57:39 PM PDT 24
Peak memory 200388 kb
Host smart-0fcef23a-deea-4d0b-a886-87eba9fb5146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380681308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.380681308
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3979799763
Short name T81
Test name
Test status
Simulation time 265241473 ps
CPU time 1.92 seconds
Started Jul 22 06:57:24 PM PDT 24
Finished Jul 22 06:57:32 PM PDT 24
Peak memory 200136 kb
Host smart-51cd63df-ab03-4845-8a74-1cae3317febf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979799763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3979799763
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3368436125
Short name T159
Test name
Test status
Simulation time 82735609 ps
CPU time 0.95 seconds
Started Jul 22 06:57:10 PM PDT 24
Finished Jul 22 06:57:18 PM PDT 24
Peak memory 200120 kb
Host smart-9cef4b2d-fa55-4182-9d80-3280a010516b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368436125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3368436125
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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