Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8809

1

T1

18

T3

106

T6

62

auto[1]

11717

1

T1

83

T3

91

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6326	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6904	1			T1	27		T2	1		T3	68
reset_info_cp[2]	3173	1			T1	20		T3	32		T4	1
reset_info_cp[4]	4156	1			T1	13		T3	49		T4	1
reset_info_cp[8]	121	1			T6	1		T7	1		T10	1
reset_info_cp[16]	112	1			T3	1		T6	1		T10	2
reset_info_cp[32]	117	1			T1	1		T3	2		T6	1
reset_info_cp[64]	116	1			T3	2		T6	1		T7	1
reset_info_cp[128]	121	1			T1	1		T3	1		T6	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3246	1			T1	18		T3	38		T6	21
reset_info_cp[1]	auto[1]	3038	1			T1	8		T3	29		T4	1
reset_info_cp[2]	auto[0]	1049	1			T3	13		T6	10		T10	8
reset_info_cp[2]	auto[1]	2124	1			T1	20		T3	19		T4	1
reset_info_cp[4]	auto[0]	1533	1			T3	27		T6	10		T10	9
reset_info_cp[4]	auto[1]	2623	1			T1	13		T3	22		T4	1
reset_info_cp[8]	auto[0]	55	1			T31	1		T76	2		T115	1
reset_info_cp[8]	auto[1]	66	1			T6	1		T7	1		T10	1
reset_info_cp[16]	auto[0]	38	1			T10	1		T89	1		T122	1
reset_info_cp[16]	auto[1]	74	1			T3	1		T6	1		T10	1
reset_info_cp[32]	auto[0]	42	1			T3	1		T10	2		T31	2
reset_info_cp[32]	auto[1]	75	1			T1	1		T3	1		T6	1
reset_info_cp[64]	auto[0]	52	1			T6	1		T31	2		T115	1
reset_info_cp[64]	auto[1]	64	1			T3	2		T7	1		T10	1
reset_info_cp[128]	auto[0]	45	1			T6	1		T115	1		T45	1
reset_info_cp[128]	auto[1]	76	1			T1	1		T3	1		T31	1