Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T535 /workspace/coverage/default/25.rstmgr_alert_test.2351362226 Jul 23 05:46:58 PM PDT 24 Jul 23 05:47:00 PM PDT 24 69943345 ps
T536 /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2909788379 Jul 23 05:47:56 PM PDT 24 Jul 23 05:48:05 PM PDT 24 1227588585 ps
T537 /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1275041242 Jul 23 05:47:29 PM PDT 24 Jul 23 05:47:43 PM PDT 24 1892757765 ps
T538 /workspace/coverage/default/28.rstmgr_por_stretcher.2640569488 Jul 23 05:47:00 PM PDT 24 Jul 23 05:47:04 PM PDT 24 158108554 ps
T539 /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3520107440 Jul 23 05:46:10 PM PDT 24 Jul 23 05:46:20 PM PDT 24 1878081607 ps
T52 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1100708960 Jul 23 05:44:08 PM PDT 24 Jul 23 05:44:11 PM PDT 24 799292745 ps
T57 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2201441489 Jul 23 05:43:56 PM PDT 24 Jul 23 05:44:00 PM PDT 24 159039809 ps
T53 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.14690439 Jul 23 05:44:15 PM PDT 24 Jul 23 05:44:16 PM PDT 24 132067473 ps
T54 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.828254981 Jul 23 05:43:55 PM PDT 24 Jul 23 05:43:57 PM PDT 24 62576878 ps
T58 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1651058736 Jul 23 05:44:08 PM PDT 24 Jul 23 05:44:11 PM PDT 24 359293428 ps
T79 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1742918498 Jul 23 05:43:56 PM PDT 24 Jul 23 05:44:02 PM PDT 24 451573491 ps
T80 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1990770186 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:13 PM PDT 24 223830116 ps
T81 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1679218213 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:17 PM PDT 24 549207142 ps
T55 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3147031651 Jul 23 05:44:11 PM PDT 24 Jul 23 05:44:17 PM PDT 24 931204391 ps
T82 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3126193795 Jul 23 05:44:09 PM PDT 24 Jul 23 05:44:12 PM PDT 24 163569949 ps
T83 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3518088647 Jul 23 05:44:12 PM PDT 24 Jul 23 05:44:15 PM PDT 24 171276913 ps
T92 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.460899934 Jul 23 05:44:15 PM PDT 24 Jul 23 05:44:17 PM PDT 24 55358522 ps
T93 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.157314507 Jul 23 05:44:12 PM PDT 24 Jul 23 05:44:15 PM PDT 24 217456609 ps
T540 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3817520838 Jul 23 05:43:55 PM PDT 24 Jul 23 05:43:57 PM PDT 24 90939159 ps
T120 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.197468973 Jul 23 05:43:50 PM PDT 24 Jul 23 05:43:59 PM PDT 24 1545129089 ps
T94 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2551485113 Jul 23 05:44:09 PM PDT 24 Jul 23 05:44:12 PM PDT 24 206246367 ps
T95 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2855748003 Jul 23 05:44:07 PM PDT 24 Jul 23 05:44:09 PM PDT 24 66371806 ps
T96 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3281706053 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:01 PM PDT 24 136956050 ps
T85 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1410698469 Jul 23 05:43:53 PM PDT 24 Jul 23 05:43:56 PM PDT 24 443453655 ps
T541 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3945762788 Jul 23 05:43:50 PM PDT 24 Jul 23 05:43:52 PM PDT 24 104494970 ps
T97 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2504014657 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:01 PM PDT 24 197000206 ps
T98 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.296105312 Jul 23 05:43:55 PM PDT 24 Jul 23 05:43:58 PM PDT 24 75947181 ps
T84 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.943796319 Jul 23 05:44:01 PM PDT 24 Jul 23 05:44:03 PM PDT 24 113950069 ps
T86 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2370038005 Jul 23 05:44:02 PM PDT 24 Jul 23 05:44:06 PM PDT 24 499074622 ps
T542 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1643227081 Jul 23 05:43:55 PM PDT 24 Jul 23 05:43:57 PM PDT 24 99280292 ps
T99 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.227133205 Jul 23 05:44:11 PM PDT 24 Jul 23 05:44:13 PM PDT 24 84401169 ps
T102 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1125312990 Jul 23 05:44:02 PM PDT 24 Jul 23 05:44:05 PM PDT 24 120406234 ps
T100 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2042234897 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:01 PM PDT 24 65650828 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.582500357 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:01 PM PDT 24 183897940 ps
T101 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.778386128 Jul 23 05:44:03 PM PDT 24 Jul 23 05:44:07 PM PDT 24 458459636 ps
T544 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2589948422 Jul 23 05:43:56 PM PDT 24 Jul 23 05:43:59 PM PDT 24 131575188 ps
T545 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3311696180 Jul 23 05:44:09 PM PDT 24 Jul 23 05:44:11 PM PDT 24 71069891 ps
T546 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.626332530 Jul 23 05:44:12 PM PDT 24 Jul 23 05:44:14 PM PDT 24 76646677 ps
T547 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1993965129 Jul 23 05:44:12 PM PDT 24 Jul 23 05:44:14 PM PDT 24 68647429 ps
T548 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.218267494 Jul 23 05:43:48 PM PDT 24 Jul 23 05:43:51 PM PDT 24 499651550 ps
T549 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3207102271 Jul 23 05:44:02 PM PDT 24 Jul 23 05:44:04 PM PDT 24 124166097 ps
T105 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.563750344 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:14 PM PDT 24 928038069 ps
T550 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.123172444 Jul 23 05:44:01 PM PDT 24 Jul 23 05:44:04 PM PDT 24 498317300 ps
T551 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2208069765 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:06 PM PDT 24 1163667542 ps
T109 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2893305949 Jul 23 05:44:16 PM PDT 24 Jul 23 05:44:18 PM PDT 24 138664458 ps
T552 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.46846993 Jul 23 05:44:01 PM PDT 24 Jul 23 05:44:03 PM PDT 24 141278391 ps
T553 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.640994193 Jul 23 05:44:17 PM PDT 24 Jul 23 05:44:19 PM PDT 24 246325608 ps
T110 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3931597994 Jul 23 05:44:13 PM PDT 24 Jul 23 05:44:16 PM PDT 24 221230983 ps
T554 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3894124305 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:13 PM PDT 24 149772422 ps
T555 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1968245979 Jul 23 05:44:17 PM PDT 24 Jul 23 05:44:19 PM PDT 24 133737180 ps
T556 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3304198930 Jul 23 05:44:05 PM PDT 24 Jul 23 05:44:07 PM PDT 24 218734490 ps
T557 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3420178764 Jul 23 05:43:56 PM PDT 24 Jul 23 05:43:59 PM PDT 24 66442711 ps
T558 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3609604380 Jul 23 05:44:02 PM PDT 24 Jul 23 05:44:04 PM PDT 24 115772987 ps
T559 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2557560474 Jul 23 05:44:12 PM PDT 24 Jul 23 05:44:16 PM PDT 24 133455458 ps
T560 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2792551016 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:03 PM PDT 24 302610606 ps
T561 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2621499052 Jul 23 05:43:46 PM PDT 24 Jul 23 05:43:49 PM PDT 24 172411293 ps
T562 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.680247424 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:01 PM PDT 24 124108572 ps
T563 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.848937901 Jul 23 05:44:01 PM PDT 24 Jul 23 05:44:05 PM PDT 24 155911903 ps
T564 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.369581176 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:12 PM PDT 24 70905670 ps
T107 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.575133007 Jul 23 05:44:16 PM PDT 24 Jul 23 05:44:20 PM PDT 24 872280214 ps
T565 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1403545689 Jul 23 05:44:08 PM PDT 24 Jul 23 05:44:11 PM PDT 24 218237948 ps
T566 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1756956054 Jul 23 05:43:47 PM PDT 24 Jul 23 05:43:49 PM PDT 24 123873337 ps
T567 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3645503133 Jul 23 05:44:16 PM PDT 24 Jul 23 05:44:20 PM PDT 24 400525453 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1665181207 Jul 23 05:43:56 PM PDT 24 Jul 23 05:44:00 PM PDT 24 120201056 ps
T569 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2544495573 Jul 23 05:43:55 PM PDT 24 Jul 23 05:43:57 PM PDT 24 60064504 ps
T103 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2607768087 Jul 23 05:44:11 PM PDT 24 Jul 23 05:44:16 PM PDT 24 1008791657 ps
T570 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2523347816 Jul 23 05:44:07 PM PDT 24 Jul 23 05:44:09 PM PDT 24 83571267 ps
T104 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.433723238 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:15 PM PDT 24 946793642 ps
T571 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1507916392 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:01 PM PDT 24 117616619 ps
T572 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.940421417 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:03 PM PDT 24 278993510 ps
T573 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2409770819 Jul 23 05:43:54 PM PDT 24 Jul 23 05:43:57 PM PDT 24 200900004 ps
T574 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4199456120 Jul 23 05:44:18 PM PDT 24 Jul 23 05:44:21 PM PDT 24 478917898 ps
T575 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.112277223 Jul 23 05:44:12 PM PDT 24 Jul 23 05:44:14 PM PDT 24 57992139 ps
T576 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2970311703 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:08 PM PDT 24 1550426354 ps
T577 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2844314203 Jul 23 05:44:08 PM PDT 24 Jul 23 05:44:11 PM PDT 24 140983020 ps
T578 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2354473157 Jul 23 05:44:09 PM PDT 24 Jul 23 05:44:11 PM PDT 24 124245270 ps
T579 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.787807134 Jul 23 05:44:00 PM PDT 24 Jul 23 05:44:06 PM PDT 24 576285609 ps
T580 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3352153588 Jul 23 05:44:21 PM PDT 24 Jul 23 05:44:24 PM PDT 24 79528997 ps
T581 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1171244148 Jul 23 05:44:11 PM PDT 24 Jul 23 05:44:14 PM PDT 24 107106657 ps
T582 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.636506890 Jul 23 05:43:53 PM PDT 24 Jul 23 05:43:55 PM PDT 24 78940306 ps
T583 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2732070253 Jul 23 05:44:00 PM PDT 24 Jul 23 05:44:04 PM PDT 24 549735822 ps
T584 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1301184059 Jul 23 05:43:56 PM PDT 24 Jul 23 05:44:03 PM PDT 24 929037404 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1313577504 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:05 PM PDT 24 478405435 ps
T586 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.986449372 Jul 23 05:44:02 PM PDT 24 Jul 23 05:44:05 PM PDT 24 87569184 ps
T587 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.565187656 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:14 PM PDT 24 196032418 ps
T588 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1848853661 Jul 23 05:43:55 PM PDT 24 Jul 23 05:43:59 PM PDT 24 363662406 ps
T589 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1491151894 Jul 23 05:44:01 PM PDT 24 Jul 23 05:44:05 PM PDT 24 327704229 ps
T590 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.731105592 Jul 23 05:44:09 PM PDT 24 Jul 23 05:44:11 PM PDT 24 90563651 ps
T591 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2361745560 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:01 PM PDT 24 103832730 ps
T592 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2925657856 Jul 23 05:44:02 PM PDT 24 Jul 23 05:44:05 PM PDT 24 147195045 ps
T593 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1419510547 Jul 23 05:43:50 PM PDT 24 Jul 23 05:43:52 PM PDT 24 99535086 ps
T594 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1491967541 Jul 23 05:43:56 PM PDT 24 Jul 23 05:43:59 PM PDT 24 120327931 ps
T595 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1517963225 Jul 23 05:43:47 PM PDT 24 Jul 23 05:43:49 PM PDT 24 87537823 ps
T596 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1951237 Jul 23 05:44:02 PM PDT 24 Jul 23 05:44:06 PM PDT 24 395778981 ps
T108 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3015761170 Jul 23 05:44:07 PM PDT 24 Jul 23 05:44:10 PM PDT 24 618578307 ps
T597 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.463244883 Jul 23 05:44:02 PM PDT 24 Jul 23 05:44:04 PM PDT 24 85111888 ps
T598 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2632470828 Jul 23 05:43:56 PM PDT 24 Jul 23 05:44:03 PM PDT 24 922409594 ps
T599 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.47141737 Jul 23 05:44:12 PM PDT 24 Jul 23 05:44:14 PM PDT 24 57577150 ps
T600 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.102455546 Jul 23 05:44:12 PM PDT 24 Jul 23 05:44:16 PM PDT 24 432783538 ps
T601 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.97660403 Jul 23 05:43:53 PM PDT 24 Jul 23 05:43:56 PM PDT 24 420524386 ps
T106 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.442944670 Jul 23 05:44:07 PM PDT 24 Jul 23 05:44:11 PM PDT 24 987029012 ps
T602 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.492393019 Jul 23 05:43:57 PM PDT 24 Jul 23 05:44:03 PM PDT 24 784954641 ps
T603 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4033124787 Jul 23 05:44:07 PM PDT 24 Jul 23 05:44:09 PM PDT 24 116414683 ps
T604 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3603299501 Jul 23 05:44:02 PM PDT 24 Jul 23 05:44:04 PM PDT 24 59113121 ps
T605 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1712900931 Jul 23 05:44:16 PM PDT 24 Jul 23 05:44:18 PM PDT 24 125611940 ps
T606 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3192540042 Jul 23 05:43:50 PM PDT 24 Jul 23 05:43:53 PM PDT 24 257663915 ps
T607 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4214647788 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:13 PM PDT 24 135236119 ps
T608 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2585007419 Jul 23 05:44:09 PM PDT 24 Jul 23 05:44:10 PM PDT 24 65109440 ps
T609 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.446203343 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:12 PM PDT 24 78330686 ps
T610 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2122726764 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:13 PM PDT 24 78400901 ps
T611 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2468738608 Jul 23 05:44:02 PM PDT 24 Jul 23 05:44:05 PM PDT 24 122531364 ps
T612 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1603919008 Jul 23 05:44:10 PM PDT 24 Jul 23 05:44:15 PM PDT 24 879714286 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1253368038 Jul 23 05:43:54 PM PDT 24 Jul 23 05:43:56 PM PDT 24 125324480 ps
T614 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1095337623 Jul 23 05:44:15 PM PDT 24 Jul 23 05:44:17 PM PDT 24 111482606 ps
T615 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3911636333 Jul 23 05:44:11 PM PDT 24 Jul 23 05:44:14 PM PDT 24 109069505 ps
T616 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3326533684 Jul 23 05:43:56 PM PDT 24 Jul 23 05:43:59 PM PDT 24 180915930 ps
T617 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3630477633 Jul 23 05:43:51 PM PDT 24 Jul 23 05:43:54 PM PDT 24 169790452 ps
T618 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3856048328 Jul 23 05:44:12 PM PDT 24 Jul 23 05:44:15 PM PDT 24 104152687 ps
T619 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.880693197 Jul 23 05:43:55 PM PDT 24 Jul 23 05:43:59 PM PDT 24 361459729 ps
T620 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3177302127 Jul 23 05:44:09 PM PDT 24 Jul 23 05:44:12 PM PDT 24 128161852 ps

Test location /workspace/coverage/default/21.rstmgr_stress_all.4124107247
Short name T3
Test name
Test status
Simulation time 7140833392 ps
CPU time 26.94 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:47:16 PM PDT 24
Peak memory 200484 kb
Host smart-0ff66ae3-8e86-4d63-bda2-3241f2671d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124107247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.4124107247
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3466338570
Short name T33
Test name
Test status
Simulation time 150666112 ps
CPU time 1.92 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:45:59 PM PDT 24
Peak memory 200152 kb
Host smart-68f693d6-519e-4fba-9331-38df4bdbaa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466338570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3466338570
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3126193795
Short name T82
Test name
Test status
Simulation time 163569949 ps
CPU time 1.55 seconds
Started Jul 23 05:44:09 PM PDT 24
Finished Jul 23 05:44:12 PM PDT 24
Peak memory 208376 kb
Host smart-54e74209-b13b-4608-ac8f-2e382b9a7d2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126193795 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3126193795
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2670555665
Short name T61
Test name
Test status
Simulation time 16523870512 ps
CPU time 31.48 seconds
Started Jul 23 05:45:25 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 217320 kb
Host smart-9f691621-3733-480c-aaae-6a298347e09a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670555665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2670555665
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2444022613
Short name T7
Test name
Test status
Simulation time 1227281099 ps
CPU time 5.84 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:31 PM PDT 24
Peak memory 221804 kb
Host smart-b46e58e7-8563-49e5-bd4a-2fb3078208e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444022613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2444022613
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3147031651
Short name T55
Test name
Test status
Simulation time 931204391 ps
CPU time 3.58 seconds
Started Jul 23 05:44:11 PM PDT 24
Finished Jul 23 05:44:17 PM PDT 24
Peak memory 199924 kb
Host smart-7b1009ad-8f73-4cbd-8a63-2266c24d1bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147031651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3147031651
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.611868994
Short name T148
Test name
Test status
Simulation time 81663555 ps
CPU time 0.8 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:12 PM PDT 24
Peak memory 199876 kb
Host smart-b29d86d6-e92b-472a-9fe0-e2c3acbbb1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611868994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.611868994
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3468270693
Short name T115
Test name
Test status
Simulation time 246541006 ps
CPU time 1.36 seconds
Started Jul 23 05:48:04 PM PDT 24
Finished Jul 23 05:48:08 PM PDT 24
Peak memory 200152 kb
Host smart-d081c785-ed42-4813-83b0-9e9b444fc613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468270693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3468270693
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.944426385
Short name T9
Test name
Test status
Simulation time 181651607 ps
CPU time 1.19 seconds
Started Jul 23 05:48:15 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 200128 kb
Host smart-f631c6bd-dbf1-462e-9cb9-7dba65899811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944426385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.944426385
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2621499052
Short name T561
Test name
Test status
Simulation time 172411293 ps
CPU time 2.42 seconds
Started Jul 23 05:43:46 PM PDT 24
Finished Jul 23 05:43:49 PM PDT 24
Peak memory 211880 kb
Host smart-ffa73164-bb4b-40d5-9788-d2f3f2f816b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621499052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2621499052
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2046132034
Short name T25
Test name
Test status
Simulation time 1237074502 ps
CPU time 5.72 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:46:00 PM PDT 24
Peak memory 221720 kb
Host smart-7cff2ff0-215b-4c0f-b264-4a5a25a51b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046132034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2046132034
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1488455936
Short name T112
Test name
Test status
Simulation time 10708786806 ps
CPU time 36.45 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:51 PM PDT 24
Peak memory 200392 kb
Host smart-8958f325-0b60-483f-ad35-1901b89288a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488455936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1488455936
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2607768087
Short name T103
Test name
Test status
Simulation time 1008791657 ps
CPU time 3.09 seconds
Started Jul 23 05:44:11 PM PDT 24
Finished Jul 23 05:44:16 PM PDT 24
Peak memory 200052 kb
Host smart-2e0a5865-99ab-4e45-b7d5-30b43ec601f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607768087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2607768087
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3963389455
Short name T40
Test name
Test status
Simulation time 1887805306 ps
CPU time 7.24 seconds
Started Jul 23 05:46:17 PM PDT 24
Finished Jul 23 05:46:25 PM PDT 24
Peak memory 217648 kb
Host smart-411d35b9-ca83-4bfb-9c8f-9028430f5732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963389455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3963389455
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.442944670
Short name T106
Test name
Test status
Simulation time 987029012 ps
CPU time 3.06 seconds
Started Jul 23 05:44:07 PM PDT 24
Finished Jul 23 05:44:11 PM PDT 24
Peak memory 200028 kb
Host smart-5f0fdffa-a8d8-4402-bf71-6ae040ec67b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442944670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
442944670
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2042234897
Short name T100
Test name
Test status
Simulation time 65650828 ps
CPU time 0.8 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:01 PM PDT 24
Peak memory 199852 kb
Host smart-9026f181-a3d8-4549-9ec4-c9db4de47250
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042234897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2042234897
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.500177768
Short name T15
Test name
Test status
Simulation time 123783360 ps
CPU time 0.78 seconds
Started Jul 23 05:46:22 PM PDT 24
Finished Jul 23 05:46:27 PM PDT 24
Peak memory 199960 kb
Host smart-32a916f2-176a-4271-af49-e79647f2b119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500177768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.500177768
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3945762788
Short name T541
Test name
Test status
Simulation time 104494970 ps
CPU time 1.38 seconds
Started Jul 23 05:43:50 PM PDT 24
Finished Jul 23 05:43:52 PM PDT 24
Peak memory 208056 kb
Host smart-d09c4e97-a8f6-404f-8008-bf1f79ac976e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945762788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
945762788
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.197468973
Short name T120
Test name
Test status
Simulation time 1545129089 ps
CPU time 8.33 seconds
Started Jul 23 05:43:50 PM PDT 24
Finished Jul 23 05:43:59 PM PDT 24
Peak memory 199860 kb
Host smart-e597a7cf-571b-4ad3-9d93-abb7fa7171d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197468973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.197468973
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1419510547
Short name T593
Test name
Test status
Simulation time 99535086 ps
CPU time 0.84 seconds
Started Jul 23 05:43:50 PM PDT 24
Finished Jul 23 05:43:52 PM PDT 24
Peak memory 199840 kb
Host smart-7f3e66c1-9c68-4d43-8c71-0c4a82ec72f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419510547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
419510547
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1756956054
Short name T566
Test name
Test status
Simulation time 123873337 ps
CPU time 0.96 seconds
Started Jul 23 05:43:47 PM PDT 24
Finished Jul 23 05:43:49 PM PDT 24
Peak memory 199956 kb
Host smart-940d2b5d-f52c-4f26-bc5d-f7ec4ba4764a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756956054 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1756956054
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1517963225
Short name T595
Test name
Test status
Simulation time 87537823 ps
CPU time 0.86 seconds
Started Jul 23 05:43:47 PM PDT 24
Finished Jul 23 05:43:49 PM PDT 24
Peak memory 199856 kb
Host smart-1e3a511a-4faa-4628-8b6a-878d99b6a192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517963225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1517963225
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3192540042
Short name T606
Test name
Test status
Simulation time 257663915 ps
CPU time 1.49 seconds
Started Jul 23 05:43:50 PM PDT 24
Finished Jul 23 05:43:53 PM PDT 24
Peak memory 199864 kb
Host smart-df608b67-eafa-48b1-a7fb-294b1705749d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192540042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3192540042
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3630477633
Short name T617
Test name
Test status
Simulation time 169790452 ps
CPU time 2.38 seconds
Started Jul 23 05:43:51 PM PDT 24
Finished Jul 23 05:43:54 PM PDT 24
Peak memory 216260 kb
Host smart-32e26ee8-4066-41f2-8770-eb53c5aa68da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630477633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3630477633
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.218267494
Short name T548
Test name
Test status
Simulation time 499651550 ps
CPU time 1.99 seconds
Started Jul 23 05:43:48 PM PDT 24
Finished Jul 23 05:43:51 PM PDT 24
Peak memory 200116 kb
Host smart-2542384b-0d31-4c9c-9dba-719b8ef4387b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218267494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
218267494
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1848853661
Short name T588
Test name
Test status
Simulation time 363662406 ps
CPU time 2.38 seconds
Started Jul 23 05:43:55 PM PDT 24
Finished Jul 23 05:43:59 PM PDT 24
Peak memory 199948 kb
Host smart-18125e06-cde0-4895-b906-a1fde274a86f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848853661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
848853661
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1313577504
Short name T585
Test name
Test status
Simulation time 478405435 ps
CPU time 6.12 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:05 PM PDT 24
Peak memory 199948 kb
Host smart-c49f2734-3ae0-4420-b6a0-f6daa19b0398
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313577504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
313577504
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1643227081
Short name T542
Test name
Test status
Simulation time 99280292 ps
CPU time 0.87 seconds
Started Jul 23 05:43:55 PM PDT 24
Finished Jul 23 05:43:57 PM PDT 24
Peak memory 199784 kb
Host smart-2e09bfe9-8a1b-4aa8-b609-80358c7e1d55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643227081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
643227081
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.582500357
Short name T543
Test name
Test status
Simulation time 183897940 ps
CPU time 1.23 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:01 PM PDT 24
Peak memory 208104 kb
Host smart-90b72268-5cbd-4f83-9880-4c18e7b634ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582500357 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.582500357
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.296105312
Short name T98
Test name
Test status
Simulation time 75947181 ps
CPU time 1.03 seconds
Started Jul 23 05:43:55 PM PDT 24
Finished Jul 23 05:43:58 PM PDT 24
Peak memory 199824 kb
Host smart-4a5d43f6-944a-4e6e-a762-83d0079ef7b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296105312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.296105312
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.492393019
Short name T602
Test name
Test status
Simulation time 784954641 ps
CPU time 2.89 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:03 PM PDT 24
Peak memory 200056 kb
Host smart-c9d7b3ef-aafa-4c08-94d6-a4d24e67b3a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492393019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
492393019
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3518088647
Short name T83
Test name
Test status
Simulation time 171276913 ps
CPU time 1.51 seconds
Started Jul 23 05:44:12 PM PDT 24
Finished Jul 23 05:44:15 PM PDT 24
Peak memory 208320 kb
Host smart-f898bc1e-f26e-47ee-9568-625648b76b50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518088647 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3518088647
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.626332530
Short name T546
Test name
Test status
Simulation time 76646677 ps
CPU time 0.78 seconds
Started Jul 23 05:44:12 PM PDT 24
Finished Jul 23 05:44:14 PM PDT 24
Peak memory 199876 kb
Host smart-3018cd7f-2cdc-4375-9dae-2d56c971befa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626332530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.626332530
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.731105592
Short name T590
Test name
Test status
Simulation time 90563651 ps
CPU time 1.01 seconds
Started Jul 23 05:44:09 PM PDT 24
Finished Jul 23 05:44:11 PM PDT 24
Peak memory 199912 kb
Host smart-43f2acb7-aca2-4009-ad89-73c11b03af91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731105592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.731105592
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2468738608
Short name T611
Test name
Test status
Simulation time 122531364 ps
CPU time 1.8 seconds
Started Jul 23 05:44:02 PM PDT 24
Finished Jul 23 05:44:05 PM PDT 24
Peak memory 208260 kb
Host smart-effb8c30-298e-4008-941b-24fc76f978ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468738608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2468738608
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2370038005
Short name T86
Test name
Test status
Simulation time 499074622 ps
CPU time 2 seconds
Started Jul 23 05:44:02 PM PDT 24
Finished Jul 23 05:44:06 PM PDT 24
Peak memory 200000 kb
Host smart-d8d6cda7-e301-406b-9ff6-c8f46e76b6a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370038005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2370038005
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2354473157
Short name T578
Test name
Test status
Simulation time 124245270 ps
CPU time 1.48 seconds
Started Jul 23 05:44:09 PM PDT 24
Finished Jul 23 05:44:11 PM PDT 24
Peak memory 208264 kb
Host smart-c25df548-ac14-499c-92c9-eb37473134ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354473157 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2354473157
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1993965129
Short name T547
Test name
Test status
Simulation time 68647429 ps
CPU time 0.86 seconds
Started Jul 23 05:44:12 PM PDT 24
Finished Jul 23 05:44:14 PM PDT 24
Peak memory 199848 kb
Host smart-cac05802-bebb-4854-93bf-2aa0b8084444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993965129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1993965129
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2122726764
Short name T610
Test name
Test status
Simulation time 78400901 ps
CPU time 0.98 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:13 PM PDT 24
Peak memory 199908 kb
Host smart-3110ce55-bfb3-4a7c-9180-8e52060d7a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122726764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2122726764
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1679218213
Short name T81
Test name
Test status
Simulation time 549207142 ps
CPU time 4.06 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:17 PM PDT 24
Peak memory 212200 kb
Host smart-a362cf05-ed8f-427b-8aea-14e9870aaa9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679218213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1679218213
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1171244148
Short name T581
Test name
Test status
Simulation time 107106657 ps
CPU time 1.18 seconds
Started Jul 23 05:44:11 PM PDT 24
Finished Jul 23 05:44:14 PM PDT 24
Peak memory 208172 kb
Host smart-cb58ad11-bb27-4e07-b6ca-1911d3e57182
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171244148 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1171244148
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3311696180
Short name T545
Test name
Test status
Simulation time 71069891 ps
CPU time 0.85 seconds
Started Jul 23 05:44:09 PM PDT 24
Finished Jul 23 05:44:11 PM PDT 24
Peak memory 199832 kb
Host smart-866d51de-d8df-49a4-bf70-50a9f473c933
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311696180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3311696180
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1403545689
Short name T565
Test name
Test status
Simulation time 218237948 ps
CPU time 1.45 seconds
Started Jul 23 05:44:08 PM PDT 24
Finished Jul 23 05:44:11 PM PDT 24
Peak memory 200052 kb
Host smart-ccd5a199-ac53-4731-88fa-774a25807f1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403545689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1403545689
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2844314203
Short name T577
Test name
Test status
Simulation time 140983020 ps
CPU time 1.91 seconds
Started Jul 23 05:44:08 PM PDT 24
Finished Jul 23 05:44:11 PM PDT 24
Peak memory 208100 kb
Host smart-225456e8-2618-44b9-848c-7731c0c01659
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844314203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2844314203
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1603919008
Short name T612
Test name
Test status
Simulation time 879714286 ps
CPU time 3.02 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:15 PM PDT 24
Peak memory 200080 kb
Host smart-3c390258-d05e-48a7-92f8-4843903f4419
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603919008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1603919008
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4214647788
Short name T607
Test name
Test status
Simulation time 135236119 ps
CPU time 1.03 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:13 PM PDT 24
Peak memory 199940 kb
Host smart-308eeaed-7264-4e2a-9f80-065f14234dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214647788 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4214647788
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.227133205
Short name T99
Test name
Test status
Simulation time 84401169 ps
CPU time 0.85 seconds
Started Jul 23 05:44:11 PM PDT 24
Finished Jul 23 05:44:13 PM PDT 24
Peak memory 199740 kb
Host smart-00e681e2-fe6a-4669-a533-37b4f41daa5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227133205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.227133205
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.446203343
Short name T609
Test name
Test status
Simulation time 78330686 ps
CPU time 1.05 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:12 PM PDT 24
Peak memory 199888 kb
Host smart-0e45b744-3432-4403-b00c-c0260dc62bc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446203343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.446203343
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3177302127
Short name T620
Test name
Test status
Simulation time 128161852 ps
CPU time 1.99 seconds
Started Jul 23 05:44:09 PM PDT 24
Finished Jul 23 05:44:12 PM PDT 24
Peak memory 208156 kb
Host smart-a4797d72-c7ad-4325-b241-bfde5322b1a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177302127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3177302127
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.102455546
Short name T600
Test name
Test status
Simulation time 432783538 ps
CPU time 1.86 seconds
Started Jul 23 05:44:12 PM PDT 24
Finished Jul 23 05:44:16 PM PDT 24
Peak memory 200068 kb
Host smart-6f8d8c41-1bbc-429f-9f2f-2f2426401251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102455546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.102455546
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3931597994
Short name T110
Test name
Test status
Simulation time 221230983 ps
CPU time 1.43 seconds
Started Jul 23 05:44:13 PM PDT 24
Finished Jul 23 05:44:16 PM PDT 24
Peak memory 208304 kb
Host smart-e43f0632-48ab-46f8-818c-d94d4e89faae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931597994 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3931597994
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.369581176
Short name T564
Test name
Test status
Simulation time 70905670 ps
CPU time 0.81 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:12 PM PDT 24
Peak memory 199876 kb
Host smart-0388fa2a-1574-46de-b9ad-ac5fa85238ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369581176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.369581176
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.157314507
Short name T93
Test name
Test status
Simulation time 217456609 ps
CPU time 1.37 seconds
Started Jul 23 05:44:12 PM PDT 24
Finished Jul 23 05:44:15 PM PDT 24
Peak memory 200064 kb
Host smart-38699138-ac00-4a12-b9a4-90a88b913245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157314507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.157314507
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3856048328
Short name T618
Test name
Test status
Simulation time 104152687 ps
CPU time 1.44 seconds
Started Jul 23 05:44:12 PM PDT 24
Finished Jul 23 05:44:15 PM PDT 24
Peak memory 208188 kb
Host smart-ce687afc-f6ec-4155-9347-f108c48892f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856048328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3856048328
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.433723238
Short name T104
Test name
Test status
Simulation time 946793642 ps
CPU time 3.05 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:15 PM PDT 24
Peak memory 200052 kb
Host smart-31358177-77e4-4044-88dd-391224dbe566
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433723238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.433723238
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.112277223
Short name T575
Test name
Test status
Simulation time 57992139 ps
CPU time 0.79 seconds
Started Jul 23 05:44:12 PM PDT 24
Finished Jul 23 05:44:14 PM PDT 24
Peak memory 199876 kb
Host smart-afcc4f2f-4dff-48b0-bb4a-47a4cfba00b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112277223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.112277223
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.565187656
Short name T587
Test name
Test status
Simulation time 196032418 ps
CPU time 1.57 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:14 PM PDT 24
Peak memory 200076 kb
Host smart-d93bbcf2-28b2-413e-9c7b-f87f0586e799
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565187656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.565187656
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2557560474
Short name T559
Test name
Test status
Simulation time 133455458 ps
CPU time 1.85 seconds
Started Jul 23 05:44:12 PM PDT 24
Finished Jul 23 05:44:16 PM PDT 24
Peak memory 208152 kb
Host smart-6a5f7ec3-c4c7-4284-8815-d500ac2d9212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557560474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2557560474
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.563750344
Short name T105
Test name
Test status
Simulation time 928038069 ps
CPU time 3.4 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:14 PM PDT 24
Peak memory 200052 kb
Host smart-79c7ffb1-2a6b-4f2b-8883-55ca242072c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563750344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.563750344
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3911636333
Short name T615
Test name
Test status
Simulation time 109069505 ps
CPU time 1.02 seconds
Started Jul 23 05:44:11 PM PDT 24
Finished Jul 23 05:44:14 PM PDT 24
Peak memory 199864 kb
Host smart-3122ca5a-e625-4922-8cd1-8a4a5963b5c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911636333 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3911636333
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2585007419
Short name T608
Test name
Test status
Simulation time 65109440 ps
CPU time 0.82 seconds
Started Jul 23 05:44:09 PM PDT 24
Finished Jul 23 05:44:10 PM PDT 24
Peak memory 199848 kb
Host smart-8fe2d450-b064-4fa8-a2eb-5998a0a57b37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585007419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2585007419
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2551485113
Short name T94
Test name
Test status
Simulation time 206246367 ps
CPU time 1.5 seconds
Started Jul 23 05:44:09 PM PDT 24
Finished Jul 23 05:44:12 PM PDT 24
Peak memory 199984 kb
Host smart-9a76de71-f101-411c-94f7-bd4da1be2ad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551485113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2551485113
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1651058736
Short name T58
Test name
Test status
Simulation time 359293428 ps
CPU time 2.48 seconds
Started Jul 23 05:44:08 PM PDT 24
Finished Jul 23 05:44:11 PM PDT 24
Peak memory 212356 kb
Host smart-a8be05dc-fdc9-4e26-82d5-787dfb245c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651058736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1651058736
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1968245979
Short name T555
Test name
Test status
Simulation time 133737180 ps
CPU time 1.08 seconds
Started Jul 23 05:44:17 PM PDT 24
Finished Jul 23 05:44:19 PM PDT 24
Peak memory 208316 kb
Host smart-6b54ec36-a4d0-404d-b52c-b9af4cb4178c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968245979 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1968245979
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.47141737
Short name T599
Test name
Test status
Simulation time 57577150 ps
CPU time 0.75 seconds
Started Jul 23 05:44:12 PM PDT 24
Finished Jul 23 05:44:14 PM PDT 24
Peak memory 199796 kb
Host smart-e639a400-ff32-427c-b9b6-cac28c2f7c75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47141737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.47141737
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3894124305
Short name T554
Test name
Test status
Simulation time 149772422 ps
CPU time 1.24 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:13 PM PDT 24
Peak memory 199916 kb
Host smart-2fa6ead4-ee19-4648-8dbe-044a8b10c33f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894124305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3894124305
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1990770186
Short name T80
Test name
Test status
Simulation time 223830116 ps
CPU time 1.81 seconds
Started Jul 23 05:44:10 PM PDT 24
Finished Jul 23 05:44:13 PM PDT 24
Peak memory 216272 kb
Host smart-6bdba1c3-af78-4194-8b9f-e380d620c796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990770186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1990770186
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1100708960
Short name T52
Test name
Test status
Simulation time 799292745 ps
CPU time 2.78 seconds
Started Jul 23 05:44:08 PM PDT 24
Finished Jul 23 05:44:11 PM PDT 24
Peak memory 200320 kb
Host smart-a99ee350-6881-4dd8-a0c0-498bb91b8320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100708960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1100708960
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2893305949
Short name T109
Test name
Test status
Simulation time 138664458 ps
CPU time 1.09 seconds
Started Jul 23 05:44:16 PM PDT 24
Finished Jul 23 05:44:18 PM PDT 24
Peak memory 208172 kb
Host smart-110a7b9c-d174-41bc-aa5a-1b59efe39904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893305949 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2893305949
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.460899934
Short name T92
Test name
Test status
Simulation time 55358522 ps
CPU time 0.77 seconds
Started Jul 23 05:44:15 PM PDT 24
Finished Jul 23 05:44:17 PM PDT 24
Peak memory 199844 kb
Host smart-104d041a-436c-4db8-9ac2-3bac264af876
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460899934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.460899934
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.640994193
Short name T553
Test name
Test status
Simulation time 246325608 ps
CPU time 1.58 seconds
Started Jul 23 05:44:17 PM PDT 24
Finished Jul 23 05:44:19 PM PDT 24
Peak memory 200028 kb
Host smart-e4992a17-c169-400c-b3cc-b1302d5abc22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640994193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.640994193
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1095337623
Short name T614
Test name
Test status
Simulation time 111482606 ps
CPU time 1.69 seconds
Started Jul 23 05:44:15 PM PDT 24
Finished Jul 23 05:44:17 PM PDT 24
Peak memory 216280 kb
Host smart-e12ef9bb-f9c9-4426-aa4e-4607c355b318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095337623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1095337623
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.575133007
Short name T107
Test name
Test status
Simulation time 872280214 ps
CPU time 3.23 seconds
Started Jul 23 05:44:16 PM PDT 24
Finished Jul 23 05:44:20 PM PDT 24
Peak memory 200072 kb
Host smart-1fb01b9a-1bf7-4c2f-a23e-248aedb6c091
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575133007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.575133007
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.14690439
Short name T53
Test name
Test status
Simulation time 132067473 ps
CPU time 1.14 seconds
Started Jul 23 05:44:15 PM PDT 24
Finished Jul 23 05:44:16 PM PDT 24
Peak memory 208000 kb
Host smart-c1aede46-94f4-4d47-9e73-fcd5469a7f47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14690439 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.14690439
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3352153588
Short name T580
Test name
Test status
Simulation time 79528997 ps
CPU time 0.81 seconds
Started Jul 23 05:44:21 PM PDT 24
Finished Jul 23 05:44:24 PM PDT 24
Peak memory 199828 kb
Host smart-aab722da-1f9a-45b5-b85f-1a5e6b1c1509
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352153588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3352153588
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1712900931
Short name T605
Test name
Test status
Simulation time 125611940 ps
CPU time 1.33 seconds
Started Jul 23 05:44:16 PM PDT 24
Finished Jul 23 05:44:18 PM PDT 24
Peak memory 200076 kb
Host smart-6c18d8c8-2713-4410-8d03-d7bab1d6206a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712900931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1712900931
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3645503133
Short name T567
Test name
Test status
Simulation time 400525453 ps
CPU time 2.82 seconds
Started Jul 23 05:44:16 PM PDT 24
Finished Jul 23 05:44:20 PM PDT 24
Peak memory 208156 kb
Host smart-c8739c8b-8d2c-41be-ab22-bba1a0c2c4d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645503133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3645503133
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4199456120
Short name T574
Test name
Test status
Simulation time 478917898 ps
CPU time 1.89 seconds
Started Jul 23 05:44:18 PM PDT 24
Finished Jul 23 05:44:21 PM PDT 24
Peak memory 200036 kb
Host smart-1ad5305f-930c-4d62-80a0-f59e59c02ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199456120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.4199456120
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2409770819
Short name T573
Test name
Test status
Simulation time 200900004 ps
CPU time 1.61 seconds
Started Jul 23 05:43:54 PM PDT 24
Finished Jul 23 05:43:57 PM PDT 24
Peak memory 199912 kb
Host smart-dfbd3143-d216-4e12-8a21-81d3b2297eb3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409770819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
409770819
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2970311703
Short name T576
Test name
Test status
Simulation time 1550426354 ps
CPU time 8.14 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:08 PM PDT 24
Peak memory 199984 kb
Host smart-a4db6b48-b3ae-45c1-98d8-08f5dc2af06b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970311703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
970311703
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2589948422
Short name T544
Test name
Test status
Simulation time 131575188 ps
CPU time 0.93 seconds
Started Jul 23 05:43:56 PM PDT 24
Finished Jul 23 05:43:59 PM PDT 24
Peak memory 199784 kb
Host smart-e1c30091-ae9a-4e4a-ab80-19fd1d0dee46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589948422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
589948422
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1491967541
Short name T594
Test name
Test status
Simulation time 120327931 ps
CPU time 1.01 seconds
Started Jul 23 05:43:56 PM PDT 24
Finished Jul 23 05:43:59 PM PDT 24
Peak memory 199940 kb
Host smart-55d80f40-8335-483c-bc4c-b62f65699c23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491967541 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1491967541
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.828254981
Short name T54
Test name
Test status
Simulation time 62576878 ps
CPU time 0.85 seconds
Started Jul 23 05:43:55 PM PDT 24
Finished Jul 23 05:43:57 PM PDT 24
Peak memory 199840 kb
Host smart-bddb6b30-306f-4e9b-9362-886840052ba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828254981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.828254981
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.46846993
Short name T552
Test name
Test status
Simulation time 141278391 ps
CPU time 1.04 seconds
Started Jul 23 05:44:01 PM PDT 24
Finished Jul 23 05:44:03 PM PDT 24
Peak memory 199884 kb
Host smart-fe37d76f-20c8-4732-b7a9-72901fb7c2b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46846993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same
_csr_outstanding.46846993
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1742918498
Short name T79
Test name
Test status
Simulation time 451573491 ps
CPU time 3.39 seconds
Started Jul 23 05:43:56 PM PDT 24
Finished Jul 23 05:44:02 PM PDT 24
Peak memory 216336 kb
Host smart-2df4bda7-86a5-471b-9ced-923726027fa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742918498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1742918498
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1410698469
Short name T85
Test name
Test status
Simulation time 443453655 ps
CPU time 1.72 seconds
Started Jul 23 05:43:53 PM PDT 24
Finished Jul 23 05:43:56 PM PDT 24
Peak memory 200068 kb
Host smart-f76a1ee7-ae9e-497c-a05b-79cf8c54dd87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410698469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1410698469
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.880693197
Short name T619
Test name
Test status
Simulation time 361459729 ps
CPU time 2.43 seconds
Started Jul 23 05:43:55 PM PDT 24
Finished Jul 23 05:43:59 PM PDT 24
Peak memory 199984 kb
Host smart-7da53364-9f9e-45b5-a1b7-dfdc43c21316
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880693197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.880693197
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.940421417
Short name T572
Test name
Test status
Simulation time 278993510 ps
CPU time 3.19 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:03 PM PDT 24
Peak memory 216364 kb
Host smart-f8914cab-e61e-4113-aa5d-9af813270a40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940421417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.940421417
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1507916392
Short name T571
Test name
Test status
Simulation time 117616619 ps
CPU time 0.96 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:01 PM PDT 24
Peak memory 199792 kb
Host smart-77967789-0a11-450a-8ed2-2c06ad27c6cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507916392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
507916392
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3326533684
Short name T616
Test name
Test status
Simulation time 180915930 ps
CPU time 1.24 seconds
Started Jul 23 05:43:56 PM PDT 24
Finished Jul 23 05:43:59 PM PDT 24
Peak memory 208108 kb
Host smart-e90aea3d-1c4b-413e-a7d8-ba73560328d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326533684 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3326533684
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3817520838
Short name T540
Test name
Test status
Simulation time 90939159 ps
CPU time 0.9 seconds
Started Jul 23 05:43:55 PM PDT 24
Finished Jul 23 05:43:57 PM PDT 24
Peak memory 199836 kb
Host smart-8aa03ffb-8a75-4644-ba1b-00a23d9b779c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817520838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3817520838
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3281706053
Short name T96
Test name
Test status
Simulation time 136956050 ps
CPU time 1.31 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:01 PM PDT 24
Peak memory 200072 kb
Host smart-7b622fa3-9b42-417e-8887-b37df770f324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281706053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3281706053
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2792551016
Short name T560
Test name
Test status
Simulation time 302610606 ps
CPU time 2.43 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:03 PM PDT 24
Peak memory 216324 kb
Host smart-c31b94cf-421f-41ce-91b8-17415d8a5f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792551016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2792551016
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2632470828
Short name T598
Test name
Test status
Simulation time 922409594 ps
CPU time 3.38 seconds
Started Jul 23 05:43:56 PM PDT 24
Finished Jul 23 05:44:03 PM PDT 24
Peak memory 200056 kb
Host smart-e573d4b9-ab1d-40bc-af03-67536c2d0c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632470828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2632470828
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.848937901
Short name T563
Test name
Test status
Simulation time 155911903 ps
CPU time 2.08 seconds
Started Jul 23 05:44:01 PM PDT 24
Finished Jul 23 05:44:05 PM PDT 24
Peak memory 199968 kb
Host smart-1235ffe2-c167-4220-a6fe-701e73037ee3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848937901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.848937901
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2208069765
Short name T551
Test name
Test status
Simulation time 1163667542 ps
CPU time 5.19 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:06 PM PDT 24
Peak memory 199956 kb
Host smart-fe432cc3-505b-4243-a408-00a1e3b19c9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208069765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
208069765
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.680247424
Short name T562
Test name
Test status
Simulation time 124108572 ps
CPU time 0.89 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:01 PM PDT 24
Peak memory 199824 kb
Host smart-9fdcc8ca-28da-45a7-8a18-73ac57bb9102
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680247424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.680247424
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1665181207
Short name T568
Test name
Test status
Simulation time 120201056 ps
CPU time 1.26 seconds
Started Jul 23 05:43:56 PM PDT 24
Finished Jul 23 05:44:00 PM PDT 24
Peak memory 208180 kb
Host smart-2c4aee8d-7543-4986-a276-d423781ff11a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665181207 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1665181207
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3420178764
Short name T557
Test name
Test status
Simulation time 66442711 ps
CPU time 0.79 seconds
Started Jul 23 05:43:56 PM PDT 24
Finished Jul 23 05:43:59 PM PDT 24
Peak memory 199844 kb
Host smart-71b824e7-7760-4f3a-8e8c-3c1cd701a0f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420178764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3420178764
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1253368038
Short name T613
Test name
Test status
Simulation time 125324480 ps
CPU time 1.07 seconds
Started Jul 23 05:43:54 PM PDT 24
Finished Jul 23 05:43:56 PM PDT 24
Peak memory 199904 kb
Host smart-6828fb16-e677-40a6-b108-c10499674091
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253368038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1253368038
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2201441489
Short name T57
Test name
Test status
Simulation time 159039809 ps
CPU time 1.36 seconds
Started Jul 23 05:43:56 PM PDT 24
Finished Jul 23 05:44:00 PM PDT 24
Peak memory 208040 kb
Host smart-14fcd74c-78e9-4c2e-bfcb-202350a90170
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201441489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2201441489
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1301184059
Short name T584
Test name
Test status
Simulation time 929037404 ps
CPU time 3.54 seconds
Started Jul 23 05:43:56 PM PDT 24
Finished Jul 23 05:44:03 PM PDT 24
Peak memory 199992 kb
Host smart-fe2862a9-0310-4691-af08-ce4c67b41e85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301184059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1301184059
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.943796319
Short name T84
Test name
Test status
Simulation time 113950069 ps
CPU time 0.99 seconds
Started Jul 23 05:44:01 PM PDT 24
Finished Jul 23 05:44:03 PM PDT 24
Peak memory 199952 kb
Host smart-9424c4c6-c526-43cd-995b-90f5155a4ed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943796319 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.943796319
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2544495573
Short name T569
Test name
Test status
Simulation time 60064504 ps
CPU time 0.76 seconds
Started Jul 23 05:43:55 PM PDT 24
Finished Jul 23 05:43:57 PM PDT 24
Peak memory 199848 kb
Host smart-81f2d485-1d8a-4587-bfc1-105ad2b8260f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544495573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2544495573
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2504014657
Short name T97
Test name
Test status
Simulation time 197000206 ps
CPU time 1.55 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:01 PM PDT 24
Peak memory 200116 kb
Host smart-11b3990d-daa4-4fb3-8eca-6fe74d0e7cca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504014657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2504014657
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2361745560
Short name T591
Test name
Test status
Simulation time 103832730 ps
CPU time 1.44 seconds
Started Jul 23 05:43:57 PM PDT 24
Finished Jul 23 05:44:01 PM PDT 24
Peak memory 199912 kb
Host smart-e9a4d8f5-92fe-4262-ae31-2f1cf0aace64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361745560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2361745560
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.97660403
Short name T601
Test name
Test status
Simulation time 420524386 ps
CPU time 1.97 seconds
Started Jul 23 05:43:53 PM PDT 24
Finished Jul 23 05:43:56 PM PDT 24
Peak memory 200060 kb
Host smart-cbf72011-2b01-4841-8809-9f63c7750c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97660403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.97660403
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1125312990
Short name T102
Test name
Test status
Simulation time 120406234 ps
CPU time 1.32 seconds
Started Jul 23 05:44:02 PM PDT 24
Finished Jul 23 05:44:05 PM PDT 24
Peak memory 208180 kb
Host smart-16aa9dc5-3792-4b76-a2ff-d9bf78f66bc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125312990 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1125312990
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.636506890
Short name T582
Test name
Test status
Simulation time 78940306 ps
CPU time 0.86 seconds
Started Jul 23 05:43:53 PM PDT 24
Finished Jul 23 05:43:55 PM PDT 24
Peak memory 199848 kb
Host smart-eb740c72-2f27-48de-9e25-fba2ec4c0b52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636506890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.636506890
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.463244883
Short name T597
Test name
Test status
Simulation time 85111888 ps
CPU time 0.93 seconds
Started Jul 23 05:44:02 PM PDT 24
Finished Jul 23 05:44:04 PM PDT 24
Peak memory 199892 kb
Host smart-88dbb1f2-8cf9-41c2-914d-578d57807a43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463244883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.463244883
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.787807134
Short name T579
Test name
Test status
Simulation time 576285609 ps
CPU time 3.96 seconds
Started Jul 23 05:44:00 PM PDT 24
Finished Jul 23 05:44:06 PM PDT 24
Peak memory 199960 kb
Host smart-482fb1b6-8db4-4864-8b80-a26d2608e212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787807134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.787807134
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2732070253
Short name T583
Test name
Test status
Simulation time 549735822 ps
CPU time 2.1 seconds
Started Jul 23 05:44:00 PM PDT 24
Finished Jul 23 05:44:04 PM PDT 24
Peak memory 200048 kb
Host smart-64253797-a2f2-4c41-b467-8fed35fcf5b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732070253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2732070253
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2925657856
Short name T592
Test name
Test status
Simulation time 147195045 ps
CPU time 1.17 seconds
Started Jul 23 05:44:02 PM PDT 24
Finished Jul 23 05:44:05 PM PDT 24
Peak memory 208152 kb
Host smart-e48f0a67-693a-47e9-ae09-32003a900203
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925657856 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2925657856
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3603299501
Short name T604
Test name
Test status
Simulation time 59113121 ps
CPU time 0.73 seconds
Started Jul 23 05:44:02 PM PDT 24
Finished Jul 23 05:44:04 PM PDT 24
Peak memory 199804 kb
Host smart-10e24f64-559f-4a58-84f7-55b2b75bdd2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603299501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3603299501
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3304198930
Short name T556
Test name
Test status
Simulation time 218734490 ps
CPU time 1.58 seconds
Started Jul 23 05:44:05 PM PDT 24
Finished Jul 23 05:44:07 PM PDT 24
Peak memory 200108 kb
Host smart-e7e46045-a821-4f65-9369-6880a1e0c076
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304198930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3304198930
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1491151894
Short name T589
Test name
Test status
Simulation time 327704229 ps
CPU time 2.72 seconds
Started Jul 23 05:44:01 PM PDT 24
Finished Jul 23 05:44:05 PM PDT 24
Peak memory 211888 kb
Host smart-3233b9ce-8895-4045-ac16-c40279e60fc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491151894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1491151894
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.123172444
Short name T550
Test name
Test status
Simulation time 498317300 ps
CPU time 2.06 seconds
Started Jul 23 05:44:01 PM PDT 24
Finished Jul 23 05:44:04 PM PDT 24
Peak memory 200008 kb
Host smart-59ab1d0b-b9c5-4da5-8d21-9776689cea28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123172444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
123172444
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3207102271
Short name T549
Test name
Test status
Simulation time 124166097 ps
CPU time 1.37 seconds
Started Jul 23 05:44:02 PM PDT 24
Finished Jul 23 05:44:04 PM PDT 24
Peak memory 208224 kb
Host smart-89aad021-90bc-49f2-a7dd-b6d4a28b4b45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207102271 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3207102271
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2855748003
Short name T95
Test name
Test status
Simulation time 66371806 ps
CPU time 0.76 seconds
Started Jul 23 05:44:07 PM PDT 24
Finished Jul 23 05:44:09 PM PDT 24
Peak memory 199820 kb
Host smart-a1cae025-1c01-4dec-ac02-922ba49d566a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855748003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2855748003
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4033124787
Short name T603
Test name
Test status
Simulation time 116414683 ps
CPU time 1.02 seconds
Started Jul 23 05:44:07 PM PDT 24
Finished Jul 23 05:44:09 PM PDT 24
Peak memory 199880 kb
Host smart-c93b0aa5-f9a7-4a25-8e10-644ee0b76da1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033124787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.4033124787
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1951237
Short name T596
Test name
Test status
Simulation time 395778981 ps
CPU time 2.81 seconds
Started Jul 23 05:44:02 PM PDT 24
Finished Jul 23 05:44:06 PM PDT 24
Peak memory 212060 kb
Host smart-4b22741f-957b-4898-b466-bb5f00bca562
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1951237
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3015761170
Short name T108
Test name
Test status
Simulation time 618578307 ps
CPU time 2.07 seconds
Started Jul 23 05:44:07 PM PDT 24
Finished Jul 23 05:44:10 PM PDT 24
Peak memory 200080 kb
Host smart-07aa1fe0-530b-4e1b-880d-549233c21087
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015761170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3015761170
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3609604380
Short name T558
Test name
Test status
Simulation time 115772987 ps
CPU time 0.93 seconds
Started Jul 23 05:44:02 PM PDT 24
Finished Jul 23 05:44:04 PM PDT 24
Peak memory 199980 kb
Host smart-0b94a3cc-108c-4eb3-8045-77f7583b875e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609604380 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3609604380
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2523347816
Short name T570
Test name
Test status
Simulation time 83571267 ps
CPU time 0.86 seconds
Started Jul 23 05:44:07 PM PDT 24
Finished Jul 23 05:44:09 PM PDT 24
Peak memory 199820 kb
Host smart-7e61b14d-7b71-4dc2-bfb0-a36163f7e3e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523347816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2523347816
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.986449372
Short name T586
Test name
Test status
Simulation time 87569184 ps
CPU time 0.99 seconds
Started Jul 23 05:44:02 PM PDT 24
Finished Jul 23 05:44:05 PM PDT 24
Peak memory 199928 kb
Host smart-6df70a35-de93-4d0c-90e3-b186fc801a65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986449372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.986449372
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.778386128
Short name T101
Test name
Test status
Simulation time 458459636 ps
CPU time 3.17 seconds
Started Jul 23 05:44:03 PM PDT 24
Finished Jul 23 05:44:07 PM PDT 24
Peak memory 208116 kb
Host smart-427aa64a-84dc-47dc-a405-d736f3a98cef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778386128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.778386128
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3809559320
Short name T274
Test name
Test status
Simulation time 76773039 ps
CPU time 0.76 seconds
Started Jul 23 05:45:31 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 199784 kb
Host smart-42459234-2526-4d7c-83bb-ebcc588a4cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809559320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3809559320
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3119327612
Short name T504
Test name
Test status
Simulation time 1229422862 ps
CPU time 5.65 seconds
Started Jul 23 05:45:21 PM PDT 24
Finished Jul 23 05:45:28 PM PDT 24
Peak memory 217760 kb
Host smart-27679712-cccd-43db-979b-64cafd15080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119327612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3119327612
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1732793769
Short name T59
Test name
Test status
Simulation time 245249954 ps
CPU time 1.04 seconds
Started Jul 23 05:45:28 PM PDT 24
Finished Jul 23 05:45:31 PM PDT 24
Peak memory 217400 kb
Host smart-f51f79e1-772b-4dc8-892e-42c340316c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732793769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1732793769
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2017063111
Short name T480
Test name
Test status
Simulation time 101112318 ps
CPU time 0.82 seconds
Started Jul 23 05:45:21 PM PDT 24
Finished Jul 23 05:45:24 PM PDT 24
Peak memory 199908 kb
Host smart-44b2e96c-d32c-4a81-9963-0c2017d3f3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017063111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2017063111
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3646483818
Short name T485
Test name
Test status
Simulation time 1759928105 ps
CPU time 6.59 seconds
Started Jul 23 05:45:24 PM PDT 24
Finished Jul 23 05:45:32 PM PDT 24
Peak memory 200448 kb
Host smart-49abac25-b58a-4e3b-b9fe-4d25fd1bff5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646483818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3646483818
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2226212334
Short name T369
Test name
Test status
Simulation time 154288181 ps
CPU time 1.13 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:45:23 PM PDT 24
Peak memory 200028 kb
Host smart-5dcf51f9-a793-4712-8402-a22e4ece2cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226212334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2226212334
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3526264320
Short name T478
Test name
Test status
Simulation time 186732722 ps
CPU time 1.41 seconds
Started Jul 23 05:45:22 PM PDT 24
Finished Jul 23 05:45:25 PM PDT 24
Peak memory 200324 kb
Host smart-aed9812c-5b46-493e-896b-2014246f3503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526264320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3526264320
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1217550581
Short name T457
Test name
Test status
Simulation time 7360547277 ps
CPU time 31.92 seconds
Started Jul 23 05:45:27 PM PDT 24
Finished Jul 23 05:46:00 PM PDT 24
Peak memory 200512 kb
Host smart-c32c274e-4879-4589-bd64-6e37b64b985b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217550581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1217550581
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.489851484
Short name T443
Test name
Test status
Simulation time 358325724 ps
CPU time 2.27 seconds
Started Jul 23 05:45:22 PM PDT 24
Finished Jul 23 05:45:26 PM PDT 24
Peak memory 200144 kb
Host smart-bac80a06-066f-4bb2-bb3f-3f83eeed55b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489851484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.489851484
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3315611174
Short name T467
Test name
Test status
Simulation time 174497130 ps
CPU time 1.12 seconds
Started Jul 23 05:45:20 PM PDT 24
Finished Jul 23 05:45:23 PM PDT 24
Peak memory 200156 kb
Host smart-603ca37b-4436-454a-b0de-6aa971911066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315611174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3315611174
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.474042986
Short name T454
Test name
Test status
Simulation time 68856326 ps
CPU time 0.79 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:45:33 PM PDT 24
Peak memory 199928 kb
Host smart-e32a5ee6-ef54-4816-8532-1e2792f02b04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474042986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.474042986
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1945217693
Short name T38
Test name
Test status
Simulation time 2354308013 ps
CPU time 7.7 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:45:39 PM PDT 24
Peak memory 221792 kb
Host smart-004cd731-b7d2-4dda-b969-0c6b09df07d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945217693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1945217693
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3764416258
Short name T133
Test name
Test status
Simulation time 243446560 ps
CPU time 1.1 seconds
Started Jul 23 05:45:32 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 217468 kb
Host smart-bd798354-ead6-4d04-80cf-77b294184ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764416258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3764416258
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.280723587
Short name T332
Test name
Test status
Simulation time 135405692 ps
CPU time 0.82 seconds
Started Jul 23 05:45:28 PM PDT 24
Finished Jul 23 05:45:31 PM PDT 24
Peak memory 199864 kb
Host smart-05676a2c-a085-469d-9db6-7dc147d7ae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280723587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.280723587
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2644046311
Short name T326
Test name
Test status
Simulation time 1544090349 ps
CPU time 6.55 seconds
Started Jul 23 05:45:30 PM PDT 24
Finished Jul 23 05:45:40 PM PDT 24
Peak memory 200468 kb
Host smart-be958b02-e373-4316-a3e0-059308bc6aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644046311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2644046311
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2559277002
Short name T66
Test name
Test status
Simulation time 17831749024 ps
CPU time 26.46 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:45:59 PM PDT 24
Peak memory 217248 kb
Host smart-77ccfdb3-4fef-4329-80c7-7f0a064f9e74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559277002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2559277002
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2486417256
Short name T244
Test name
Test status
Simulation time 149327300 ps
CPU time 1.09 seconds
Started Jul 23 05:45:28 PM PDT 24
Finished Jul 23 05:45:32 PM PDT 24
Peak memory 200076 kb
Host smart-6bd818ad-244a-4274-ac76-69f34a47bba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486417256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2486417256
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.4077476420
Short name T34
Test name
Test status
Simulation time 117524843 ps
CPU time 1.17 seconds
Started Jul 23 05:45:32 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 200200 kb
Host smart-4ee884f1-054e-4602-9615-0fd6a1b25a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077476420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4077476420
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2741845636
Short name T111
Test name
Test status
Simulation time 4015184055 ps
CPU time 13.78 seconds
Started Jul 23 05:45:28 PM PDT 24
Finished Jul 23 05:45:45 PM PDT 24
Peak memory 208688 kb
Host smart-1bb050f0-081d-4503-b7f0-54675d7d2bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741845636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2741845636
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3221566823
Short name T229
Test name
Test status
Simulation time 324194219 ps
CPU time 2.14 seconds
Started Jul 23 05:45:27 PM PDT 24
Finished Jul 23 05:45:31 PM PDT 24
Peak memory 200152 kb
Host smart-37944054-b3bb-4701-a73a-fce5b3790800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221566823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3221566823
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3829876878
Short name T49
Test name
Test status
Simulation time 136285949 ps
CPU time 1.14 seconds
Started Jul 23 05:45:27 PM PDT 24
Finished Jul 23 05:45:30 PM PDT 24
Peak memory 200064 kb
Host smart-c5fd31ed-ebf1-43ba-b1b9-726a514e1377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829876878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3829876878
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1292664870
Short name T235
Test name
Test status
Simulation time 70990480 ps
CPU time 0.8 seconds
Started Jul 23 05:46:12 PM PDT 24
Finished Jul 23 05:46:15 PM PDT 24
Peak memory 199788 kb
Host smart-970cc15a-1f86-4564-8a4f-6ca8d4aefe59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292664870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1292664870
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.337901118
Short name T29
Test name
Test status
Simulation time 1219252137 ps
CPU time 5 seconds
Started Jul 23 05:46:11 PM PDT 24
Finished Jul 23 05:46:19 PM PDT 24
Peak memory 221752 kb
Host smart-49f26720-6174-4ac4-90e0-57cb03a72db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337901118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.337901118
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3421316710
Short name T509
Test name
Test status
Simulation time 245160520 ps
CPU time 1.03 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:13 PM PDT 24
Peak memory 217500 kb
Host smart-1e01396b-4e5d-4a7a-8fad-6dc8c7da1006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421316710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3421316710
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.837456155
Short name T185
Test name
Test status
Simulation time 122703305 ps
CPU time 0.79 seconds
Started Jul 23 05:46:12 PM PDT 24
Finished Jul 23 05:46:15 PM PDT 24
Peak memory 199944 kb
Host smart-9478214e-4b91-4aa4-8e0c-6d7e99a9e89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837456155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.837456155
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.254745180
Short name T466
Test name
Test status
Simulation time 1527049163 ps
CPU time 6.1 seconds
Started Jul 23 05:46:12 PM PDT 24
Finished Jul 23 05:46:21 PM PDT 24
Peak memory 200360 kb
Host smart-9fd125fb-7e9e-4379-937f-9e12f287a291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254745180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.254745180
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1309362447
Short name T177
Test name
Test status
Simulation time 95039495 ps
CPU time 1.06 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:14 PM PDT 24
Peak memory 200140 kb
Host smart-d4727a1e-3507-4e1a-93ee-ae8a1b383a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309362447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1309362447
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1785648406
Short name T241
Test name
Test status
Simulation time 249374012 ps
CPU time 1.46 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:13 PM PDT 24
Peak memory 200272 kb
Host smart-34c929c5-9219-4021-b1b3-9fb1c6af8bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785648406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1785648406
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.195574360
Short name T197
Test name
Test status
Simulation time 11399492689 ps
CPU time 38.67 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:49 PM PDT 24
Peak memory 208648 kb
Host smart-2b3deb0e-2677-4d62-8dad-c51ec71893bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195574360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.195574360
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.331545692
Short name T179
Test name
Test status
Simulation time 112109966 ps
CPU time 1.39 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:10 PM PDT 24
Peak memory 200076 kb
Host smart-c82afc05-b3aa-493d-b594-23f86fddbf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331545692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.331545692
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.347216850
Short name T153
Test name
Test status
Simulation time 58702382 ps
CPU time 0.73 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:14 PM PDT 24
Peak memory 200008 kb
Host smart-b0a8efaa-91fb-4ed5-b4aa-09fc5bd636ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347216850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.347216850
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1264822679
Short name T293
Test name
Test status
Simulation time 70116563 ps
CPU time 0.78 seconds
Started Jul 23 05:46:12 PM PDT 24
Finished Jul 23 05:46:15 PM PDT 24
Peak memory 199924 kb
Host smart-b4d2a226-ae09-4ce3-8bca-ea36f31e4779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264822679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1264822679
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2329360161
Short name T335
Test name
Test status
Simulation time 1229879572 ps
CPU time 5.31 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 221768 kb
Host smart-70049cd2-3794-400f-a3f1-90236896070b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329360161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2329360161
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.717517445
Short name T453
Test name
Test status
Simulation time 243996673 ps
CPU time 1.11 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:14 PM PDT 24
Peak memory 217460 kb
Host smart-993400cb-b0e7-4b62-9b6d-e778c84ac329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717517445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.717517445
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2364073195
Short name T217
Test name
Test status
Simulation time 121446216 ps
CPU time 0.82 seconds
Started Jul 23 05:46:12 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 199956 kb
Host smart-fb8c3ba5-2e16-408b-bdda-fe8bec6271cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364073195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2364073195
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1904796969
Short name T113
Test name
Test status
Simulation time 1859885081 ps
CPU time 6.64 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:18 PM PDT 24
Peak memory 200468 kb
Host smart-d210be80-6c7f-415c-b635-76db91b3461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904796969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1904796969
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2885104938
Short name T5
Test name
Test status
Simulation time 147780758 ps
CPU time 1.15 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:11 PM PDT 24
Peak memory 200048 kb
Host smart-5d5e0648-455b-4082-9813-4d8abebca40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885104938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2885104938
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2616171232
Short name T155
Test name
Test status
Simulation time 255862175 ps
CPU time 1.57 seconds
Started Jul 23 05:46:11 PM PDT 24
Finished Jul 23 05:46:15 PM PDT 24
Peak memory 200340 kb
Host smart-e990c6e2-0bf5-4cd4-b40e-390846bfca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616171232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2616171232
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.819191180
Short name T431
Test name
Test status
Simulation time 12365796781 ps
CPU time 39.97 seconds
Started Jul 23 05:46:08 PM PDT 24
Finished Jul 23 05:46:49 PM PDT 24
Peak memory 208580 kb
Host smart-322a17e9-a92f-4983-bd9c-52904542fcc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819191180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.819191180
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1893614563
Short name T257
Test name
Test status
Simulation time 343650849 ps
CPU time 2.19 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:13 PM PDT 24
Peak memory 208588 kb
Host smart-905f7764-32d5-49aa-a41c-d96bf481d0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893614563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1893614563
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3122486572
Short name T178
Test name
Test status
Simulation time 135664634 ps
CPU time 1.15 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:12 PM PDT 24
Peak memory 200372 kb
Host smart-9dd17017-79d3-4781-adab-115ee7894105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122486572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3122486572
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3520107440
Short name T539
Test name
Test status
Simulation time 1878081607 ps
CPU time 6.77 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:20 PM PDT 24
Peak memory 217776 kb
Host smart-916f3bab-c7f5-4f5d-b61b-3d9ef3d9f35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520107440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3520107440
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3663032918
Short name T227
Test name
Test status
Simulation time 244653764 ps
CPU time 1.11 seconds
Started Jul 23 05:46:11 PM PDT 24
Finished Jul 23 05:46:15 PM PDT 24
Peak memory 217568 kb
Host smart-c1a82690-700d-4ee1-9335-d61d21bede26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663032918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3663032918
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.490056523
Short name T462
Test name
Test status
Simulation time 138025200 ps
CPU time 0.85 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:14 PM PDT 24
Peak memory 199880 kb
Host smart-41eebca8-6550-41e1-8cc6-487ace910848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490056523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.490056523
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3149008337
Short name T191
Test name
Test status
Simulation time 2051384543 ps
CPU time 7.85 seconds
Started Jul 23 05:46:14 PM PDT 24
Finished Jul 23 05:46:23 PM PDT 24
Peak memory 200420 kb
Host smart-0cbe7b5c-9859-4cc8-b8ff-5b9044342179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149008337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3149008337
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2616695868
Short name T195
Test name
Test status
Simulation time 102825021 ps
CPU time 1.02 seconds
Started Jul 23 05:46:13 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 200076 kb
Host smart-b224d854-3dc0-432b-9880-2b8dfb461529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616695868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2616695868
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2228571928
Short name T127
Test name
Test status
Simulation time 121149261 ps
CPU time 1.2 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:13 PM PDT 24
Peak memory 200356 kb
Host smart-52fb09be-a56b-471f-b824-ed7a72f83d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228571928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2228571928
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.857985852
Short name T520
Test name
Test status
Simulation time 10646317868 ps
CPU time 40.75 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:54 PM PDT 24
Peak memory 208680 kb
Host smart-e8edb992-d56a-4ccd-adde-97fdf122040d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857985852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.857985852
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2127501609
Short name T435
Test name
Test status
Simulation time 331743032 ps
CPU time 2.38 seconds
Started Jul 23 05:46:10 PM PDT 24
Finished Jul 23 05:46:16 PM PDT 24
Peak memory 200064 kb
Host smart-420544c0-f9c0-43cc-aa57-68c19cf790f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127501609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2127501609
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2901063152
Short name T356
Test name
Test status
Simulation time 76278815 ps
CPU time 0.8 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:13 PM PDT 24
Peak memory 200132 kb
Host smart-7e62aa80-c5b1-4f80-aa8e-518df320cf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901063152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2901063152
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1793932594
Short name T309
Test name
Test status
Simulation time 66123078 ps
CPU time 0.83 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:23 PM PDT 24
Peak memory 199876 kb
Host smart-45f9e6ec-323d-4411-b841-2494d4a36af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793932594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1793932594
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3267267594
Short name T506
Test name
Test status
Simulation time 243917224 ps
CPU time 1.1 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:24 PM PDT 24
Peak memory 217536 kb
Host smart-3d5f3d58-4025-4745-9d5b-a77b63a0b1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267267594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3267267594
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3052848974
Short name T373
Test name
Test status
Simulation time 798825982 ps
CPU time 3.82 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:26 PM PDT 24
Peak memory 200420 kb
Host smart-c553d88a-7175-4969-a0ea-a89cca2413d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052848974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3052848974
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2450608609
Short name T368
Test name
Test status
Simulation time 186822002 ps
CPU time 1.22 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:25 PM PDT 24
Peak memory 200144 kb
Host smart-d6f89c66-6029-4df6-ac94-afc46d72c572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450608609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2450608609
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3286497987
Short name T295
Test name
Test status
Simulation time 113949909 ps
CPU time 1.22 seconds
Started Jul 23 05:46:19 PM PDT 24
Finished Jul 23 05:46:21 PM PDT 24
Peak memory 200332 kb
Host smart-d6450bfa-0499-45a0-99eb-f61ec39ae3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286497987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3286497987
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2092488397
Short name T530
Test name
Test status
Simulation time 4225975132 ps
CPU time 18.83 seconds
Started Jul 23 05:46:22 PM PDT 24
Finished Jul 23 05:46:45 PM PDT 24
Peak memory 200324 kb
Host smart-b40db693-0d4d-4b0d-9d97-1071f47d76fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092488397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2092488397
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3387625356
Short name T176
Test name
Test status
Simulation time 512786473 ps
CPU time 2.47 seconds
Started Jul 23 05:46:19 PM PDT 24
Finished Jul 23 05:46:24 PM PDT 24
Peak memory 200096 kb
Host smart-98272a94-ac7d-49c0-a890-a6131bbb750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387625356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3387625356
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4132567231
Short name T446
Test name
Test status
Simulation time 85448134 ps
CPU time 0.88 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:24 PM PDT 24
Peak memory 200144 kb
Host smart-f2951df1-936a-418e-9114-6fef74109484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132567231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4132567231
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2718905316
Short name T328
Test name
Test status
Simulation time 83322154 ps
CPU time 0.85 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:24 PM PDT 24
Peak memory 199824 kb
Host smart-fc7050de-2b28-4c4d-93c6-9121fcf556e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718905316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2718905316
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3286500003
Short name T258
Test name
Test status
Simulation time 1883886989 ps
CPU time 6.93 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:29 PM PDT 24
Peak memory 221744 kb
Host smart-4807853b-169d-4c32-aadf-0ffa294b292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286500003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3286500003
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2595122075
Short name T143
Test name
Test status
Simulation time 243691458 ps
CPU time 1.13 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:26 PM PDT 24
Peak memory 217432 kb
Host smart-132cab44-f869-4ffd-aca6-c9dac6e2f445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595122075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2595122075
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3408681967
Short name T290
Test name
Test status
Simulation time 172000398 ps
CPU time 0.95 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:24 PM PDT 24
Peak memory 199968 kb
Host smart-9276151e-69a3-48cf-97a3-030ee5a72508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408681967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3408681967
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2135020032
Short name T90
Test name
Test status
Simulation time 1837003203 ps
CPU time 6.8 seconds
Started Jul 23 05:46:19 PM PDT 24
Finished Jul 23 05:46:27 PM PDT 24
Peak memory 200360 kb
Host smart-d180ca4e-aa1f-4912-83e6-5ef8bb2e0f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135020032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2135020032
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2546687643
Short name T377
Test name
Test status
Simulation time 99946982 ps
CPU time 0.99 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:25 PM PDT 24
Peak memory 200152 kb
Host smart-e288cfaa-3633-475d-b87f-af728291b2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546687643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2546687643
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2665644731
Short name T280
Test name
Test status
Simulation time 209833372 ps
CPU time 1.38 seconds
Started Jul 23 05:46:18 PM PDT 24
Finished Jul 23 05:46:21 PM PDT 24
Peak memory 200328 kb
Host smart-98915319-595a-4fcf-b00c-35cd62ebc635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665644731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2665644731
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1962732643
Short name T385
Test name
Test status
Simulation time 11957545304 ps
CPU time 42.49 seconds
Started Jul 23 05:46:24 PM PDT 24
Finished Jul 23 05:47:10 PM PDT 24
Peak memory 200484 kb
Host smart-602e4a9b-a028-44bd-80a9-06ff0d5a47da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962732643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1962732643
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.795306269
Short name T246
Test name
Test status
Simulation time 398901053 ps
CPU time 2.33 seconds
Started Jul 23 05:46:18 PM PDT 24
Finished Jul 23 05:46:21 PM PDT 24
Peak memory 200140 kb
Host smart-72c0dd95-7f01-4350-8dea-6b73abd58bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795306269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.795306269
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2847214747
Short name T275
Test name
Test status
Simulation time 138190745 ps
CPU time 1.13 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:26 PM PDT 24
Peak memory 200060 kb
Host smart-a65ce029-af1a-4931-949f-0a5b966506d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847214747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2847214747
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3877651716
Short name T391
Test name
Test status
Simulation time 82980558 ps
CPU time 0.86 seconds
Started Jul 23 05:46:26 PM PDT 24
Finished Jul 23 05:46:30 PM PDT 24
Peak memory 199924 kb
Host smart-71a8632c-d113-4a21-abfc-9bf7508f0215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877651716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3877651716
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1504610133
Short name T361
Test name
Test status
Simulation time 244537810 ps
CPU time 1.06 seconds
Started Jul 23 05:46:24 PM PDT 24
Finished Jul 23 05:46:29 PM PDT 24
Peak memory 217516 kb
Host smart-bc93225f-cdab-47d8-95e0-e6b2e2a34c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504610133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1504610133
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2089051456
Short name T468
Test name
Test status
Simulation time 79533336 ps
CPU time 0.8 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:23 PM PDT 24
Peak memory 199944 kb
Host smart-eebd2c7d-ce93-49f5-a266-781e756d89c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089051456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2089051456
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2817527466
Short name T88
Test name
Test status
Simulation time 1379251565 ps
CPU time 5.41 seconds
Started Jul 23 05:46:19 PM PDT 24
Finished Jul 23 05:46:25 PM PDT 24
Peak memory 200364 kb
Host smart-762273fb-9056-4050-bdc1-02790d80d8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817527466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2817527466
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2262339469
Short name T351
Test name
Test status
Simulation time 144360391 ps
CPU time 1.08 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:27 PM PDT 24
Peak memory 200028 kb
Host smart-6ed9027a-0426-45f4-8857-5d73a4a9603e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262339469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2262339469
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1707988999
Short name T355
Test name
Test status
Simulation time 255120140 ps
CPU time 1.52 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:24 PM PDT 24
Peak memory 200260 kb
Host smart-3d7fa4ce-4521-4222-b688-ed128ec69b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707988999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1707988999
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.415947610
Short name T398
Test name
Test status
Simulation time 2656425662 ps
CPU time 11.72 seconds
Started Jul 23 05:46:22 PM PDT 24
Finished Jul 23 05:46:38 PM PDT 24
Peak memory 200328 kb
Host smart-bab54e8b-3ff0-4bf8-b8dd-6e1c52e9baf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415947610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.415947610
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2815378906
Short name T406
Test name
Test status
Simulation time 125656810 ps
CPU time 1.43 seconds
Started Jul 23 05:46:21 PM PDT 24
Finished Jul 23 05:46:25 PM PDT 24
Peak memory 200116 kb
Host smart-f52a075d-a24c-4654-b014-130f6e3c615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815378906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2815378906
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.573903870
Short name T472
Test name
Test status
Simulation time 261248690 ps
CPU time 1.39 seconds
Started Jul 23 05:46:20 PM PDT 24
Finished Jul 23 05:46:24 PM PDT 24
Peak memory 200148 kb
Host smart-1f216848-f47f-4026-bd4d-ce83b1e9e312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573903870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.573903870
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.562891582
Short name T492
Test name
Test status
Simulation time 71582675 ps
CPU time 0.74 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:39 PM PDT 24
Peak memory 199892 kb
Host smart-01fd2031-c006-4327-bd0f-4ca0a7e8ae65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562891582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.562891582
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.4279815003
Short name T501
Test name
Test status
Simulation time 1862387898 ps
CPU time 7.77 seconds
Started Jul 23 05:46:30 PM PDT 24
Finished Jul 23 05:46:39 PM PDT 24
Peak memory 217740 kb
Host smart-13e2969e-a885-4339-9c7c-e3d5451885c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279815003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4279815003
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3979257809
Short name T510
Test name
Test status
Simulation time 244332221 ps
CPU time 1.1 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:43 PM PDT 24
Peak memory 217552 kb
Host smart-24ea7cf3-8406-4e52-be4d-8fae3d5a982d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979257809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3979257809
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3163075096
Short name T425
Test name
Test status
Simulation time 143779085 ps
CPU time 0.89 seconds
Started Jul 23 05:46:26 PM PDT 24
Finished Jul 23 05:46:30 PM PDT 24
Peak memory 199940 kb
Host smart-01752c9c-8a84-4d64-8e45-186512d5fb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163075096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3163075096
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2915385624
Short name T247
Test name
Test status
Simulation time 961865409 ps
CPU time 4.9 seconds
Started Jul 23 05:46:19 PM PDT 24
Finished Jul 23 05:46:26 PM PDT 24
Peak memory 200360 kb
Host smart-ebcdd6ef-20ba-4375-b621-1e278ea32c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915385624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2915385624
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2667092502
Short name T173
Test name
Test status
Simulation time 104790044 ps
CPU time 0.99 seconds
Started Jul 23 05:46:27 PM PDT 24
Finished Jul 23 05:46:30 PM PDT 24
Peak memory 200124 kb
Host smart-91f6eb75-204b-47a0-841c-94417cc3a093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667092502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2667092502
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1702733883
Short name T75
Test name
Test status
Simulation time 198701056 ps
CPU time 1.43 seconds
Started Jul 23 05:46:26 PM PDT 24
Finished Jul 23 05:46:30 PM PDT 24
Peak memory 200340 kb
Host smart-af1cd025-da1a-48da-8f79-7404c996543a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702733883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1702733883
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2288063484
Short name T213
Test name
Test status
Simulation time 2813128227 ps
CPU time 10.59 seconds
Started Jul 23 05:46:29 PM PDT 24
Finished Jul 23 05:46:41 PM PDT 24
Peak memory 200500 kb
Host smart-3e1525e2-9ddc-4176-9500-343b2e06cd44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288063484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2288063484
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3551738012
Short name T126
Test name
Test status
Simulation time 138939524 ps
CPU time 1.74 seconds
Started Jul 23 05:46:35 PM PDT 24
Finished Jul 23 05:46:38 PM PDT 24
Peak memory 200136 kb
Host smart-46535f27-8c17-46cb-9a58-f5cd80ca1106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551738012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3551738012
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.4031683714
Short name T349
Test name
Test status
Simulation time 90313379 ps
CPU time 0.92 seconds
Started Jul 23 05:46:32 PM PDT 24
Finished Jul 23 05:46:34 PM PDT 24
Peak memory 200056 kb
Host smart-f32036d7-8544-491d-8397-7900cefc96d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031683714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.4031683714
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4174528520
Short name T64
Test name
Test status
Simulation time 55564776 ps
CPU time 0.76 seconds
Started Jul 23 05:46:27 PM PDT 24
Finished Jul 23 05:46:30 PM PDT 24
Peak memory 199932 kb
Host smart-137cbeec-6f7f-4612-b9de-ca6fdeb0ad0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174528520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4174528520
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1426604199
Short name T37
Test name
Test status
Simulation time 2350878605 ps
CPU time 8.29 seconds
Started Jul 23 05:46:31 PM PDT 24
Finished Jul 23 05:46:40 PM PDT 24
Peak memory 217836 kb
Host smart-c8396e11-e395-4333-a7da-2818688592f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426604199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1426604199
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1217274910
Short name T413
Test name
Test status
Simulation time 244459177 ps
CPU time 1.12 seconds
Started Jul 23 05:46:29 PM PDT 24
Finished Jul 23 05:46:32 PM PDT 24
Peak memory 217436 kb
Host smart-e598e799-9875-4833-b19a-4ff0158cf95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217274910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1217274910
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2540718512
Short name T338
Test name
Test status
Simulation time 104771719 ps
CPU time 0.77 seconds
Started Jul 23 05:46:33 PM PDT 24
Finished Jul 23 05:46:35 PM PDT 24
Peak memory 199868 kb
Host smart-e4265a23-4b91-4b09-b4de-34d1b0b43063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540718512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2540718512
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.666141588
Short name T359
Test name
Test status
Simulation time 1650996814 ps
CPU time 6.65 seconds
Started Jul 23 05:46:35 PM PDT 24
Finished Jul 23 05:46:43 PM PDT 24
Peak memory 200396 kb
Host smart-89245c2d-d228-40ae-8980-e9a32bc299c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666141588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.666141588
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1039643311
Short name T168
Test name
Test status
Simulation time 105123463 ps
CPU time 1.03 seconds
Started Jul 23 05:46:34 PM PDT 24
Finished Jul 23 05:46:36 PM PDT 24
Peak memory 200116 kb
Host smart-d7178f77-2d03-4c66-85f9-4463bd200215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039643311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1039643311
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3503552323
Short name T434
Test name
Test status
Simulation time 244620728 ps
CPU time 1.47 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:41 PM PDT 24
Peak memory 200364 kb
Host smart-91adb4d9-bf59-4834-92a3-93730983108d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503552323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3503552323
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3013122192
Short name T71
Test name
Test status
Simulation time 4375106913 ps
CPU time 18.69 seconds
Started Jul 23 05:46:29 PM PDT 24
Finished Jul 23 05:46:50 PM PDT 24
Peak memory 200436 kb
Host smart-ace20ca1-1148-4fa1-b8ac-0b9058ea24b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013122192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3013122192
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.118972210
Short name T375
Test name
Test status
Simulation time 391866801 ps
CPU time 2.41 seconds
Started Jul 23 05:46:32 PM PDT 24
Finished Jul 23 05:46:36 PM PDT 24
Peak memory 200140 kb
Host smart-d5904e79-07a4-4346-a347-b203e4e3e448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118972210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.118972210
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2486539096
Short name T220
Test name
Test status
Simulation time 117907760 ps
CPU time 1.05 seconds
Started Jul 23 05:46:35 PM PDT 24
Finished Jul 23 05:46:38 PM PDT 24
Peak memory 200128 kb
Host smart-39fd9eb6-b659-4732-a697-c958eafee5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486539096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2486539096
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3012305520
Short name T429
Test name
Test status
Simulation time 83707479 ps
CPU time 0.83 seconds
Started Jul 23 05:46:40 PM PDT 24
Finished Jul 23 05:46:45 PM PDT 24
Peak memory 199928 kb
Host smart-d2a1bf20-1230-4944-8ae3-c5146344c925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012305520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3012305520
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1819352694
Short name T190
Test name
Test status
Simulation time 1228712588 ps
CPU time 5.93 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 217212 kb
Host smart-cd6978b5-31a9-4072-82d9-d1e1b6c9a493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819352694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1819352694
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1066635612
Short name T339
Test name
Test status
Simulation time 245568832 ps
CPU time 1.18 seconds
Started Jul 23 05:46:36 PM PDT 24
Finished Jul 23 05:46:39 PM PDT 24
Peak memory 217488 kb
Host smart-b02cca3f-2012-4f6b-9bde-5454eba84ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066635612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1066635612
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3797834507
Short name T321
Test name
Test status
Simulation time 208995813 ps
CPU time 0.98 seconds
Started Jul 23 05:46:32 PM PDT 24
Finished Jul 23 05:46:35 PM PDT 24
Peak memory 199944 kb
Host smart-87db9f1b-19ff-41ba-abb5-c45705223919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797834507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3797834507
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2310055964
Short name T175
Test name
Test status
Simulation time 1449199797 ps
CPU time 5.62 seconds
Started Jul 23 05:46:26 PM PDT 24
Finished Jul 23 05:46:34 PM PDT 24
Peak memory 200424 kb
Host smart-34dd3bd5-18b7-4c7b-ad4e-d9033c52f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310055964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2310055964
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3578413907
Short name T348
Test name
Test status
Simulation time 172867936 ps
CPU time 1.16 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:41 PM PDT 24
Peak memory 200148 kb
Host smart-eb89ea58-31fc-4b31-ac1b-0f2f9c4fd538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578413907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3578413907
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2484895364
Short name T300
Test name
Test status
Simulation time 192031335 ps
CPU time 1.46 seconds
Started Jul 23 05:46:29 PM PDT 24
Finished Jul 23 05:46:32 PM PDT 24
Peak memory 200340 kb
Host smart-81836e3a-20ec-44a7-a5d8-25bcbd184a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484895364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2484895364
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3055475705
Short name T474
Test name
Test status
Simulation time 7539559120 ps
CPU time 36.07 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:47:16 PM PDT 24
Peak memory 200376 kb
Host smart-b369da40-fe1a-45c0-b366-e438e9107113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055475705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3055475705
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1181690482
Short name T430
Test name
Test status
Simulation time 258916536 ps
CPU time 1.72 seconds
Started Jul 23 05:46:28 PM PDT 24
Finished Jul 23 05:46:32 PM PDT 24
Peak memory 200064 kb
Host smart-dabece9a-e9c4-4c2c-81c4-4dbfaeedf872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181690482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1181690482
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3905811208
Short name T342
Test name
Test status
Simulation time 241159607 ps
CPU time 1.53 seconds
Started Jul 23 05:46:32 PM PDT 24
Finished Jul 23 05:46:36 PM PDT 24
Peak memory 200060 kb
Host smart-2e68e6d9-0073-4d2c-b1f8-ecd3dbd4b660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905811208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3905811208
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.120000170
Short name T69
Test name
Test status
Simulation time 75526077 ps
CPU time 0.73 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:40 PM PDT 24
Peak memory 199952 kb
Host smart-febbcee9-b2dc-45f0-99fb-3d0ea5ae49fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120000170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.120000170
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2911879203
Short name T50
Test name
Test status
Simulation time 1222960692 ps
CPU time 5.9 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:49 PM PDT 24
Peak memory 221732 kb
Host smart-ff197109-10b5-4cf2-b7b7-3e170d609060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911879203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2911879203
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2911392098
Short name T341
Test name
Test status
Simulation time 244373821 ps
CPU time 1.08 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:40 PM PDT 24
Peak memory 217516 kb
Host smart-42144029-96e9-4dbd-a007-79ae0716e1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911392098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2911392098
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3624585097
Short name T456
Test name
Test status
Simulation time 235030804 ps
CPU time 1 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:40 PM PDT 24
Peak memory 199892 kb
Host smart-b9c3d46e-55dd-4a9c-b732-ccba7640d2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624585097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3624585097
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1705264913
Short name T20
Test name
Test status
Simulation time 871422362 ps
CPU time 4.25 seconds
Started Jul 23 05:46:37 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 200384 kb
Host smart-75dcaf96-2d54-494b-9d45-72f5a47f1c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705264913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1705264913
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1633746716
Short name T528
Test name
Test status
Simulation time 137996672 ps
CPU time 1.14 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:42 PM PDT 24
Peak memory 200144 kb
Host smart-06974906-b24e-48da-bb71-9465e160eb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633746716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1633746716
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2583745900
Short name T243
Test name
Test status
Simulation time 196607128 ps
CPU time 1.41 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 200004 kb
Host smart-e4d3d360-eef4-41c1-8c59-fe8c6ea6019e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583745900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2583745900
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3975463104
Short name T91
Test name
Test status
Simulation time 7640541796 ps
CPU time 26.95 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:47:09 PM PDT 24
Peak memory 200464 kb
Host smart-77520a24-caee-4757-8a4c-7b79265e72c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975463104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3975463104
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4262740886
Short name T412
Test name
Test status
Simulation time 330399607 ps
CPU time 2.31 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:46 PM PDT 24
Peak memory 200148 kb
Host smart-b6bd8442-4313-4f7c-836d-68a8986f86f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262740886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4262740886
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3480745307
Short name T409
Test name
Test status
Simulation time 123994390 ps
CPU time 0.96 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:41 PM PDT 24
Peak memory 200144 kb
Host smart-b2f6e543-74b3-4799-b5e3-6fbe90168ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480745307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3480745307
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2897137697
Short name T142
Test name
Test status
Simulation time 67692891 ps
CPU time 0.78 seconds
Started Jul 23 05:45:43 PM PDT 24
Finished Jul 23 05:45:45 PM PDT 24
Peak memory 199932 kb
Host smart-df22a974-1eb8-40d4-bd1f-c435b67ccd8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897137697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2897137697
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2165541100
Short name T201
Test name
Test status
Simulation time 2348917813 ps
CPU time 8.57 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:45:40 PM PDT 24
Peak memory 221664 kb
Host smart-8a401b5d-74e8-42a1-8507-1bdc7e432c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165541100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2165541100
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1694540442
Short name T384
Test name
Test status
Simulation time 245283721 ps
CPU time 1.01 seconds
Started Jul 23 05:45:30 PM PDT 24
Finished Jul 23 05:45:33 PM PDT 24
Peak memory 218408 kb
Host smart-ebeba571-22fa-467a-9db2-a3c8457e33ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694540442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1694540442
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.778158897
Short name T245
Test name
Test status
Simulation time 191232215 ps
CPU time 0.86 seconds
Started Jul 23 05:45:31 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 199896 kb
Host smart-daa78ac3-b5d6-4020-a060-447435d6a2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778158897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.778158897
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2600340542
Short name T252
Test name
Test status
Simulation time 985654997 ps
CPU time 4.76 seconds
Started Jul 23 05:45:34 PM PDT 24
Finished Jul 23 05:45:40 PM PDT 24
Peak memory 200360 kb
Host smart-48ac582c-0752-41e9-bc62-407920aed490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600340542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2600340542
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.48799962
Short name T62
Test name
Test status
Simulation time 16913453905 ps
CPU time 24.66 seconds
Started Jul 23 05:45:30 PM PDT 24
Finished Jul 23 05:45:58 PM PDT 24
Peak memory 218280 kb
Host smart-a18159a0-3177-4a11-a303-2566fdb43f53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48799962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.48799962
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4166346712
Short name T414
Test name
Test status
Simulation time 106243887 ps
CPU time 0.97 seconds
Started Jul 23 05:45:31 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 199984 kb
Host smart-6e528dc5-2631-4751-b824-3729cab3f666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166346712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4166346712
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2541971085
Short name T486
Test name
Test status
Simulation time 200525598 ps
CPU time 1.35 seconds
Started Jul 23 05:45:34 PM PDT 24
Finished Jul 23 05:45:37 PM PDT 24
Peak memory 200296 kb
Host smart-fc670d55-4ca4-4f94-b0a5-5318f2066372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541971085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2541971085
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2395953569
Short name T460
Test name
Test status
Simulation time 3369466549 ps
CPU time 13.67 seconds
Started Jul 23 05:45:28 PM PDT 24
Finished Jul 23 05:45:43 PM PDT 24
Peak memory 200704 kb
Host smart-e5519577-f8a8-40e1-8125-b3ceaa3c5437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395953569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2395953569
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3867221593
Short name T386
Test name
Test status
Simulation time 438460950 ps
CPU time 2.65 seconds
Started Jul 23 05:45:28 PM PDT 24
Finished Jul 23 05:45:32 PM PDT 24
Peak memory 200128 kb
Host smart-6c99f1f1-efd5-4434-821c-416dfd6409da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867221593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3867221593
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2684207960
Short name T418
Test name
Test status
Simulation time 77321167 ps
CPU time 0.87 seconds
Started Jul 23 05:45:29 PM PDT 24
Finished Jul 23 05:45:33 PM PDT 24
Peak memory 200040 kb
Host smart-ba8191af-6fa4-4e25-a010-2d24238ae4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684207960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2684207960
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.4149383212
Short name T387
Test name
Test status
Simulation time 77031440 ps
CPU time 0.8 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:42 PM PDT 24
Peak memory 199932 kb
Host smart-c657cb4c-3951-4903-b393-43be4106a871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149383212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.4149383212
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3736685386
Short name T263
Test name
Test status
Simulation time 1220800061 ps
CPU time 5.94 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:49 PM PDT 24
Peak memory 221644 kb
Host smart-1399a7ae-353c-4b9a-8ded-d8367282e3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736685386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3736685386
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1667886889
Short name T514
Test name
Test status
Simulation time 244493280 ps
CPU time 1.07 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:43 PM PDT 24
Peak memory 217284 kb
Host smart-a2cc7619-a4c0-4109-bdb1-06130421036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667886889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1667886889
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1505583686
Short name T270
Test name
Test status
Simulation time 100650922 ps
CPU time 0.8 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 199932 kb
Host smart-acafa680-4262-42bb-a25b-42d399befceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505583686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1505583686
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2397390167
Short name T516
Test name
Test status
Simulation time 1265919313 ps
CPU time 5.1 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:45 PM PDT 24
Peak memory 200424 kb
Host smart-112b39f0-f4c1-4d27-b2ca-ab62e8fc9495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397390167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2397390167
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1476803479
Short name T324
Test name
Test status
Simulation time 171748256 ps
CPU time 1.24 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:44 PM PDT 24
Peak memory 200132 kb
Host smart-4bbea34f-a9ce-4121-905a-ccffaca3531e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476803479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1476803479
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.4060932453
Short name T180
Test name
Test status
Simulation time 229583059 ps
CPU time 1.39 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:43 PM PDT 24
Peak memory 200336 kb
Host smart-c0cc2088-8aa7-4c27-a612-f6c59ee6a607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060932453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4060932453
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.560182762
Short name T166
Test name
Test status
Simulation time 3219982333 ps
CPU time 12.55 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:55 PM PDT 24
Peak memory 200460 kb
Host smart-15cb408a-d4c9-467f-b181-3a1a3a16c1a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560182762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.560182762
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3298060765
Short name T211
Test name
Test status
Simulation time 139405068 ps
CPU time 1.67 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:43 PM PDT 24
Peak memory 200156 kb
Host smart-bc5370dc-1261-450b-8165-6f8cad4f46f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298060765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3298060765
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1590610843
Short name T147
Test name
Test status
Simulation time 93200834 ps
CPU time 0.88 seconds
Started Jul 23 05:46:41 PM PDT 24
Finished Jul 23 05:46:45 PM PDT 24
Peak memory 200136 kb
Host smart-90d0beaf-fa7b-457a-85dd-c38c8b7faa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590610843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1590610843
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1095998178
Short name T427
Test name
Test status
Simulation time 91398823 ps
CPU time 0.85 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:49 PM PDT 24
Peak memory 199824 kb
Host smart-d7b9ca31-6a59-4f2a-8fd4-e93e85d23d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095998178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1095998178
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2052804159
Short name T36
Test name
Test status
Simulation time 1888545306 ps
CPU time 6.87 seconds
Started Jul 23 05:46:44 PM PDT 24
Finished Jul 23 05:46:53 PM PDT 24
Peak memory 221668 kb
Host smart-37840724-c322-459f-b2b1-d69f290ffed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052804159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2052804159
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1205963800
Short name T74
Test name
Test status
Simulation time 243996810 ps
CPU time 1.21 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:51 PM PDT 24
Peak memory 217304 kb
Host smart-fd2e3e1f-ab39-4f51-a849-fa69baee52af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205963800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1205963800
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3078925915
Short name T12
Test name
Test status
Simulation time 118406579 ps
CPU time 0.81 seconds
Started Jul 23 05:46:42 PM PDT 24
Finished Jul 23 05:46:46 PM PDT 24
Peak memory 199944 kb
Host smart-12f63ad3-db03-49de-9f18-bfcbdf840cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078925915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3078925915
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3599088765
Short name T304
Test name
Test status
Simulation time 1596992576 ps
CPU time 6.33 seconds
Started Jul 23 05:46:40 PM PDT 24
Finished Jul 23 05:46:51 PM PDT 24
Peak memory 200416 kb
Host smart-34fd919a-3abc-4fe9-b6c4-43f00ee120d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599088765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3599088765
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2201403538
Short name T524
Test name
Test status
Simulation time 175065416 ps
CPU time 1.22 seconds
Started Jul 23 05:46:40 PM PDT 24
Finished Jul 23 05:46:45 PM PDT 24
Peak memory 200136 kb
Host smart-3c73bd78-d4c1-46f6-9aab-6f71f5720d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201403538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2201403538
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1163117561
Short name T254
Test name
Test status
Simulation time 124783713 ps
CPU time 1.24 seconds
Started Jul 23 05:46:39 PM PDT 24
Finished Jul 23 05:46:43 PM PDT 24
Peak memory 200336 kb
Host smart-21a466fb-85c1-4b46-a8a2-12761a966f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163117561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1163117561
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3998361613
Short name T447
Test name
Test status
Simulation time 458651196 ps
CPU time 2.54 seconds
Started Jul 23 05:46:40 PM PDT 24
Finished Jul 23 05:46:47 PM PDT 24
Peak memory 200140 kb
Host smart-f0000039-480c-4818-ae44-e68326cf5e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998361613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3998361613
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.4179990218
Short name T279
Test name
Test status
Simulation time 109788677 ps
CPU time 1 seconds
Started Jul 23 05:46:38 PM PDT 24
Finished Jul 23 05:46:43 PM PDT 24
Peak memory 200060 kb
Host smart-6e0fa139-7a5f-445a-854a-9c43350010d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179990218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.4179990218
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.200472805
Short name T327
Test name
Test status
Simulation time 74119351 ps
CPU time 0.84 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:46:51 PM PDT 24
Peak memory 199924 kb
Host smart-2b1f39c0-3446-4e1a-ae2f-844ebc1edb98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200472805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.200472805
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3092931597
Short name T162
Test name
Test status
Simulation time 1218161388 ps
CPU time 5.24 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:47:00 PM PDT 24
Peak memory 217552 kb
Host smart-8cfdc1cf-3de6-43f5-b676-1eef02d03c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092931597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3092931597
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2489232823
Short name T209
Test name
Test status
Simulation time 245457926 ps
CPU time 1.05 seconds
Started Jul 23 05:46:48 PM PDT 24
Finished Jul 23 05:46:53 PM PDT 24
Peak memory 217504 kb
Host smart-b75f2220-4084-4ab4-94b5-8de6c3fad873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489232823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2489232823
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.921716388
Short name T294
Test name
Test status
Simulation time 101536283 ps
CPU time 0.78 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:46:56 PM PDT 24
Peak memory 199932 kb
Host smart-3d73a6aa-1e02-44d3-9e48-ee2d017767f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921716388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.921716388
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1545918520
Short name T260
Test name
Test status
Simulation time 1577759431 ps
CPU time 5.77 seconds
Started Jul 23 05:46:49 PM PDT 24
Finished Jul 23 05:46:58 PM PDT 24
Peak memory 200396 kb
Host smart-1e14483a-7398-41c3-b94a-27ad89ab8d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545918520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1545918520
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3515360727
Short name T128
Test name
Test status
Simulation time 105107223 ps
CPU time 1.02 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:49 PM PDT 24
Peak memory 200124 kb
Host smart-2bb0fd17-dad1-489a-9317-c6bc6a53dfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515360727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3515360727
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2172711437
Short name T500
Test name
Test status
Simulation time 257287374 ps
CPU time 1.46 seconds
Started Jul 23 05:46:45 PM PDT 24
Finished Jul 23 05:46:49 PM PDT 24
Peak memory 200332 kb
Host smart-01684b42-ef46-4be6-a090-ac5fb5c17a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172711437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2172711437
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2126906092
Short name T188
Test name
Test status
Simulation time 1615135572 ps
CPU time 7.92 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:56 PM PDT 24
Peak memory 208572 kb
Host smart-e0a50f66-bc12-4a49-b4bc-bbb377e83954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126906092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2126906092
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.4099082529
Short name T116
Test name
Test status
Simulation time 520830759 ps
CPU time 2.71 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:46:53 PM PDT 24
Peak memory 200104 kb
Host smart-8eb89332-6707-47c0-9694-58f8b0c57b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099082529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.4099082529
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2651010673
Short name T405
Test name
Test status
Simulation time 194412434 ps
CPU time 1.32 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:46:52 PM PDT 24
Peak memory 200288 kb
Host smart-5505a052-0abe-4a3b-a564-99f63b5bbaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651010673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2651010673
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3408816129
Short name T444
Test name
Test status
Simulation time 71327721 ps
CPU time 0.8 seconds
Started Jul 23 05:46:48 PM PDT 24
Finished Jul 23 05:46:52 PM PDT 24
Peak memory 199928 kb
Host smart-54e4ffe6-7f92-43da-af01-9e3f5b793352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408816129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3408816129
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.4043292992
Short name T1
Test name
Test status
Simulation time 2368626355 ps
CPU time 7.69 seconds
Started Jul 23 05:46:45 PM PDT 24
Finished Jul 23 05:46:55 PM PDT 24
Peak memory 217184 kb
Host smart-168c5adf-d3f9-4728-adc1-8477671b062e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043292992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.4043292992
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.324253996
Short name T253
Test name
Test status
Simulation time 244822989 ps
CPU time 1.03 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:46:56 PM PDT 24
Peak memory 217564 kb
Host smart-5a1040d3-f905-4c0f-8fb7-48130c2d3541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324253996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.324253996
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.875811558
Short name T502
Test name
Test status
Simulation time 99991937 ps
CPU time 0.78 seconds
Started Jul 23 05:46:45 PM PDT 24
Finished Jul 23 05:46:48 PM PDT 24
Peak memory 199864 kb
Host smart-07260fa5-58bc-4b8b-af6a-3c83aa0c80fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875811558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.875811558
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1386630303
Short name T199
Test name
Test status
Simulation time 1011822438 ps
CPU time 5.17 seconds
Started Jul 23 05:46:49 PM PDT 24
Finished Jul 23 05:46:58 PM PDT 24
Peak memory 200352 kb
Host smart-ce832640-6759-4a86-9e32-775747178d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386630303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1386630303
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.885657732
Short name T200
Test name
Test status
Simulation time 154204088 ps
CPU time 1.15 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:46:52 PM PDT 24
Peak memory 200296 kb
Host smart-65d3dd1c-56d6-45ea-853a-debf895104f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885657732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.885657732
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.522848957
Short name T8
Test name
Test status
Simulation time 208497216 ps
CPU time 1.39 seconds
Started Jul 23 05:46:49 PM PDT 24
Finished Jul 23 05:46:54 PM PDT 24
Peak memory 200292 kb
Host smart-6557ce2c-4165-43ed-b62c-b0c320d0b990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522848957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.522848957
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3950163037
Short name T499
Test name
Test status
Simulation time 2271259357 ps
CPU time 8.56 seconds
Started Jul 23 05:46:48 PM PDT 24
Finished Jul 23 05:47:00 PM PDT 24
Peak memory 200472 kb
Host smart-cf0916c1-af3f-4bae-9442-021498e202a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950163037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3950163037
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3193852844
Short name T319
Test name
Test status
Simulation time 378118259 ps
CPU time 2.33 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:46:54 PM PDT 24
Peak memory 200100 kb
Host smart-83db4bdd-3966-4f8b-b204-21483bb35a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193852844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3193852844
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.60028743
Short name T251
Test name
Test status
Simulation time 91490471 ps
CPU time 0.9 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:46:52 PM PDT 24
Peak memory 200100 kb
Host smart-a578ef25-f278-4002-b199-7b48ac79a7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60028743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.60028743
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.291401100
Short name T186
Test name
Test status
Simulation time 93654608 ps
CPU time 0.87 seconds
Started Jul 23 05:46:59 PM PDT 24
Finished Jul 23 05:47:02 PM PDT 24
Peak memory 199944 kb
Host smart-a0966c3c-f537-4980-87de-a946792f1f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291401100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.291401100
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3040715374
Short name T285
Test name
Test status
Simulation time 2349384371 ps
CPU time 8.82 seconds
Started Jul 23 05:46:55 PM PDT 24
Finished Jul 23 05:47:06 PM PDT 24
Peak memory 221812 kb
Host smart-d7e88a70-8dd2-42cb-8361-1e709356b491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040715374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3040715374
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.80635682
Short name T230
Test name
Test status
Simulation time 245150258 ps
CPU time 1.11 seconds
Started Jul 23 05:46:51 PM PDT 24
Finished Jul 23 05:46:55 PM PDT 24
Peak memory 217488 kb
Host smart-12d4dc29-ffd3-4467-a44d-1a73da1e53d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80635682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.80635682
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2410080179
Short name T2
Test name
Test status
Simulation time 248626092 ps
CPU time 0.94 seconds
Started Jul 23 05:46:50 PM PDT 24
Finished Jul 23 05:46:55 PM PDT 24
Peak memory 199944 kb
Host smart-ee62e68d-3bc3-469b-913c-638c7aabea21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410080179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2410080179
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3269961313
Short name T497
Test name
Test status
Simulation time 907120229 ps
CPU time 4.51 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:46:54 PM PDT 24
Peak memory 200356 kb
Host smart-cdde6a96-ba9d-420b-8dd5-59af541d2db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269961313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3269961313
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.753851713
Short name T219
Test name
Test status
Simulation time 133981972 ps
CPU time 1.12 seconds
Started Jul 23 05:46:54 PM PDT 24
Finished Jul 23 05:46:58 PM PDT 24
Peak memory 200116 kb
Host smart-f577b6e4-a855-468d-a49d-17c9a0ec6d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753851713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.753851713
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1137500799
Short name T157
Test name
Test status
Simulation time 199565370 ps
CPU time 1.31 seconds
Started Jul 23 05:46:46 PM PDT 24
Finished Jul 23 05:46:50 PM PDT 24
Peak memory 200488 kb
Host smart-88333286-2570-454d-82e0-f2da8ab21a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137500799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1137500799
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.27026129
Short name T363
Test name
Test status
Simulation time 6891663080 ps
CPU time 25.05 seconds
Started Jul 23 05:46:53 PM PDT 24
Finished Jul 23 05:47:21 PM PDT 24
Peak memory 208660 kb
Host smart-c02ce5a0-4e12-4cd9-9136-500bea15a03a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27026129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.27026129
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.469414380
Short name T119
Test name
Test status
Simulation time 393535844 ps
CPU time 2.22 seconds
Started Jul 23 05:46:48 PM PDT 24
Finished Jul 23 05:46:54 PM PDT 24
Peak memory 200152 kb
Host smart-e82ba2e0-d589-4eaa-a0f6-9fa6990cbe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469414380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.469414380
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1698433607
Short name T437
Test name
Test status
Simulation time 156241770 ps
CPU time 1.09 seconds
Started Jul 23 05:46:47 PM PDT 24
Finished Jul 23 05:46:52 PM PDT 24
Peak memory 200136 kb
Host smart-bc0bdead-4e91-46c5-8775-5478fe7a0763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698433607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1698433607
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2351362226
Short name T535
Test name
Test status
Simulation time 69943345 ps
CPU time 0.82 seconds
Started Jul 23 05:46:58 PM PDT 24
Finished Jul 23 05:47:00 PM PDT 24
Peak memory 199928 kb
Host smart-c22a722f-b27b-4be5-88ca-0664db3ad140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351362226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2351362226
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3641003062
Short name T325
Test name
Test status
Simulation time 1230794510 ps
CPU time 5.51 seconds
Started Jul 23 05:46:53 PM PDT 24
Finished Jul 23 05:47:01 PM PDT 24
Peak memory 217844 kb
Host smart-792bf2ce-a495-438c-9462-3722944afb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641003062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3641003062
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3977641469
Short name T239
Test name
Test status
Simulation time 244207297 ps
CPU time 1.14 seconds
Started Jul 23 05:46:58 PM PDT 24
Finished Jul 23 05:47:01 PM PDT 24
Peak memory 217404 kb
Host smart-7612aeed-8371-4082-b2ee-b1c824b5dd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977641469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3977641469
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1573160374
Short name T402
Test name
Test status
Simulation time 141286676 ps
CPU time 0.84 seconds
Started Jul 23 05:46:58 PM PDT 24
Finished Jul 23 05:47:01 PM PDT 24
Peak memory 199956 kb
Host smart-7c1b6038-a7e7-49cd-94d3-911350176b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573160374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1573160374
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.862785569
Short name T517
Test name
Test status
Simulation time 1160672703 ps
CPU time 5.19 seconds
Started Jul 23 05:46:55 PM PDT 24
Finished Jul 23 05:47:02 PM PDT 24
Peak memory 200360 kb
Host smart-e37ebbf6-ee7a-4656-82ce-7a306bdad5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862785569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.862785569
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2464755573
Short name T455
Test name
Test status
Simulation time 152457763 ps
CPU time 1.12 seconds
Started Jul 23 05:46:54 PM PDT 24
Finished Jul 23 05:46:58 PM PDT 24
Peak memory 200128 kb
Host smart-a857ae8f-ca78-4376-b19a-07bebc8dc822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464755573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2464755573
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.426696368
Short name T354
Test name
Test status
Simulation time 260193869 ps
CPU time 1.53 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:09 PM PDT 24
Peak memory 200244 kb
Host smart-0466f2ef-fd30-4a4c-98cc-d5531d048fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426696368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.426696368
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.705476438
Short name T278
Test name
Test status
Simulation time 2127886117 ps
CPU time 7.32 seconds
Started Jul 23 05:46:55 PM PDT 24
Finished Jul 23 05:47:05 PM PDT 24
Peak memory 200404 kb
Host smart-bbb5d51e-2570-4ee6-8a89-575e61475c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705476438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.705476438
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1617902450
Short name T287
Test name
Test status
Simulation time 144575522 ps
CPU time 1.95 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:46:57 PM PDT 24
Peak memory 200064 kb
Host smart-ddbafa06-cd58-4a6e-b3c5-cad5d191f601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617902450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1617902450
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.4048301307
Short name T438
Test name
Test status
Simulation time 78695919 ps
CPU time 0.86 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:08 PM PDT 24
Peak memory 200040 kb
Host smart-51820e73-47e3-46af-8713-fdae58273259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048301307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.4048301307
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1457792685
Short name T43
Test name
Test status
Simulation time 62243683 ps
CPU time 0.8 seconds
Started Jul 23 05:46:54 PM PDT 24
Finished Jul 23 05:46:58 PM PDT 24
Peak memory 199928 kb
Host smart-412c8613-ec0b-4497-85c1-cee8c0302953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457792685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1457792685
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1264569360
Short name T508
Test name
Test status
Simulation time 2166997918 ps
CPU time 9.18 seconds
Started Jul 23 05:46:54 PM PDT 24
Finished Jul 23 05:47:06 PM PDT 24
Peak memory 221788 kb
Host smart-520bd13d-5624-47d6-b4fb-e0c66968cab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264569360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1264569360
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.4290136467
Short name T383
Test name
Test status
Simulation time 243613961 ps
CPU time 1.04 seconds
Started Jul 23 05:46:53 PM PDT 24
Finished Jul 23 05:46:57 PM PDT 24
Peak memory 217516 kb
Host smart-248f1c46-6664-40fc-8636-5a76d0a91fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290136467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.4290136467
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.985806346
Short name T424
Test name
Test status
Simulation time 84290505 ps
CPU time 0.75 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:08 PM PDT 24
Peak memory 199848 kb
Host smart-c1a2e46d-7d69-43a6-aba0-f1b2f19b7873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985806346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.985806346
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2432897132
Short name T132
Test name
Test status
Simulation time 943083340 ps
CPU time 4.56 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:47:00 PM PDT 24
Peak memory 200356 kb
Host smart-401b875d-206d-4b11-91ce-655fa2c30459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432897132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2432897132
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.729156229
Short name T299
Test name
Test status
Simulation time 96163946 ps
CPU time 1.01 seconds
Started Jul 23 05:47:00 PM PDT 24
Finished Jul 23 05:47:04 PM PDT 24
Peak memory 200128 kb
Host smart-f8123942-c31a-4680-b9b2-52c847deebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729156229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.729156229
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1513720425
Short name T172
Test name
Test status
Simulation time 112731337 ps
CPU time 1.2 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:46:56 PM PDT 24
Peak memory 200356 kb
Host smart-59b8a387-8ced-4eda-ac69-84ea2b490ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513720425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1513720425
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.316413077
Short name T440
Test name
Test status
Simulation time 10708534417 ps
CPU time 34.86 seconds
Started Jul 23 05:46:53 PM PDT 24
Finished Jul 23 05:47:31 PM PDT 24
Peak memory 200440 kb
Host smart-01fe81d0-fd6d-4ff2-b65c-73c754c02ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316413077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.316413077
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1106885480
Short name T333
Test name
Test status
Simulation time 468944803 ps
CPU time 2.75 seconds
Started Jul 23 05:46:54 PM PDT 24
Finished Jul 23 05:46:59 PM PDT 24
Peak memory 200152 kb
Host smart-146e8650-4a91-4789-84e7-734414d3511e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106885480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1106885480
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.187955162
Short name T215
Test name
Test status
Simulation time 248249002 ps
CPU time 1.48 seconds
Started Jul 23 05:47:00 PM PDT 24
Finished Jul 23 05:47:04 PM PDT 24
Peak memory 200332 kb
Host smart-c976923c-e018-4c8e-8d89-7fe740a4f3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187955162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.187955162
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1913915727
Short name T154
Test name
Test status
Simulation time 64658745 ps
CPU time 0.82 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:07 PM PDT 24
Peak memory 199876 kb
Host smart-ca77731c-7582-4ca0-a3f0-5a0d47ce3601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913915727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1913915727
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2406877140
Short name T357
Test name
Test status
Simulation time 1887833316 ps
CPU time 7.56 seconds
Started Jul 23 05:47:05 PM PDT 24
Finished Jul 23 05:47:17 PM PDT 24
Peak memory 221776 kb
Host smart-eb0349a0-4a3f-4652-99a2-aa1ebe7061ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406877140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2406877140
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3666660849
Short name T421
Test name
Test status
Simulation time 244610548 ps
CPU time 1.24 seconds
Started Jul 23 05:47:08 PM PDT 24
Finished Jul 23 05:47:12 PM PDT 24
Peak memory 217508 kb
Host smart-0842ba05-b4f4-4207-810a-0c8855fddf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666660849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3666660849
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1488924492
Short name T519
Test name
Test status
Simulation time 172451095 ps
CPU time 0.86 seconds
Started Jul 23 05:46:54 PM PDT 24
Finished Jul 23 05:46:58 PM PDT 24
Peak memory 200180 kb
Host smart-221f076d-cd4c-4643-8e3e-985a3d7b2c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488924492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1488924492
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2166156062
Short name T292
Test name
Test status
Simulation time 1113238052 ps
CPU time 5.03 seconds
Started Jul 23 05:47:01 PM PDT 24
Finished Jul 23 05:47:08 PM PDT 24
Peak memory 200416 kb
Host smart-787882a0-2493-497f-a41b-9baf6e331fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166156062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2166156062
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1198572127
Short name T465
Test name
Test status
Simulation time 97662447 ps
CPU time 1.11 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:08 PM PDT 24
Peak memory 200144 kb
Host smart-31ad0a61-1fd9-4f67-8a87-72574d40400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198572127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1198572127
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1200928719
Short name T140
Test name
Test status
Simulation time 198871331 ps
CPU time 1.4 seconds
Started Jul 23 05:46:52 PM PDT 24
Finished Jul 23 05:46:56 PM PDT 24
Peak memory 200356 kb
Host smart-be64ca0f-cae9-4777-bde3-0f280faa3f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200928719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1200928719
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1695222097
Short name T31
Test name
Test status
Simulation time 8269310079 ps
CPU time 28.82 seconds
Started Jul 23 05:47:01 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 208736 kb
Host smart-7417502c-e5f8-4625-b5d9-61f1543570ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695222097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1695222097
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2872935883
Short name T428
Test name
Test status
Simulation time 363111726 ps
CPU time 2.55 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:09 PM PDT 24
Peak memory 200148 kb
Host smart-d63010d3-98fc-453c-808c-1e835fa40fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872935883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2872935883
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1676075998
Short name T273
Test name
Test status
Simulation time 223244372 ps
CPU time 1.37 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:07 PM PDT 24
Peak memory 200056 kb
Host smart-d89dbccc-0e9c-4fd0-97b9-8c7ff80a164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676075998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1676075998
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3010456633
Short name T63
Test name
Test status
Simulation time 64202440 ps
CPU time 0.77 seconds
Started Jul 23 05:47:06 PM PDT 24
Finished Jul 23 05:47:11 PM PDT 24
Peak memory 199876 kb
Host smart-235ebc53-b149-4891-b6c9-857c49a77c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010456633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3010456633
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1518497658
Short name T334
Test name
Test status
Simulation time 2360932889 ps
CPU time 8.68 seconds
Started Jul 23 05:47:07 PM PDT 24
Finished Jul 23 05:47:19 PM PDT 24
Peak memory 217944 kb
Host smart-dc0209d7-b32f-4629-a3f4-e6f50283ae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518497658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1518497658
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.4215696096
Short name T364
Test name
Test status
Simulation time 245081201 ps
CPU time 1.04 seconds
Started Jul 23 05:47:04 PM PDT 24
Finished Jul 23 05:47:10 PM PDT 24
Peak memory 217500 kb
Host smart-907920d3-43fc-474f-82a5-fe63ca1ad0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215696096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.4215696096
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2640569488
Short name T538
Test name
Test status
Simulation time 158108554 ps
CPU time 0.92 seconds
Started Jul 23 05:47:00 PM PDT 24
Finished Jul 23 05:47:04 PM PDT 24
Peak memory 199908 kb
Host smart-ddabf092-d8f3-4928-91d3-2260ae5114d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640569488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2640569488
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3514070272
Short name T482
Test name
Test status
Simulation time 1568256164 ps
CPU time 5.64 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:11 PM PDT 24
Peak memory 200392 kb
Host smart-4b57255c-463c-40ae-b3a6-e051b4d0bd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514070272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3514070272
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2416848510
Short name T174
Test name
Test status
Simulation time 158871589 ps
CPU time 1.1 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:07 PM PDT 24
Peak memory 200100 kb
Host smart-133fb489-d793-4db8-8cc4-fc9cc95243ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416848510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2416848510
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2349350881
Short name T288
Test name
Test status
Simulation time 195981279 ps
CPU time 1.49 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:07 PM PDT 24
Peak memory 200296 kb
Host smart-a0a294df-b7f4-4197-aa5e-5cad67f95927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349350881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2349350881
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.20300727
Short name T343
Test name
Test status
Simulation time 4034567912 ps
CPU time 15.18 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:22 PM PDT 24
Peak memory 208672 kb
Host smart-bcebf86a-17d5-4f51-9582-fd19ed36e43f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20300727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.20300727
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2075456648
Short name T44
Test name
Test status
Simulation time 261992018 ps
CPU time 1.72 seconds
Started Jul 23 05:47:05 PM PDT 24
Finished Jul 23 05:47:11 PM PDT 24
Peak memory 200152 kb
Host smart-5cc8d7f9-ce6a-4632-9a01-d68b439a4a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075456648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2075456648
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2688915477
Short name T521
Test name
Test status
Simulation time 114156586 ps
CPU time 1.03 seconds
Started Jul 23 05:47:01 PM PDT 24
Finished Jul 23 05:47:05 PM PDT 24
Peak memory 200032 kb
Host smart-39b0476b-3e84-41a5-adee-af95f2ee3b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688915477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2688915477
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1368962844
Short name T315
Test name
Test status
Simulation time 79117743 ps
CPU time 0.86 seconds
Started Jul 23 05:47:16 PM PDT 24
Finished Jul 23 05:47:22 PM PDT 24
Peak memory 199940 kb
Host smart-31b66f38-99ab-4331-a322-480039f3cb1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368962844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1368962844
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3970640316
Short name T232
Test name
Test status
Simulation time 1231117388 ps
CPU time 5.45 seconds
Started Jul 23 05:47:12 PM PDT 24
Finished Jul 23 05:47:21 PM PDT 24
Peak memory 217740 kb
Host smart-a747fad9-627d-4ca7-8ec1-c580897af8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970640316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3970640316
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2256917469
Short name T169
Test name
Test status
Simulation time 244582966 ps
CPU time 1.14 seconds
Started Jul 23 05:47:10 PM PDT 24
Finished Jul 23 05:47:15 PM PDT 24
Peak memory 217396 kb
Host smart-691868b4-7141-4bbb-a1d2-c9e44c964cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256917469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2256917469
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2318334571
Short name T16
Test name
Test status
Simulation time 177040865 ps
CPU time 0.87 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:06 PM PDT 24
Peak memory 199904 kb
Host smart-0f0a8da5-4c5e-4f0d-9df5-3f289c4ea0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318334571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2318334571
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.823863954
Short name T393
Test name
Test status
Simulation time 811662446 ps
CPU time 4.5 seconds
Started Jul 23 05:47:06 PM PDT 24
Finished Jul 23 05:47:14 PM PDT 24
Peak memory 200432 kb
Host smart-3ddf3d55-6eb9-43df-947f-9ace8461149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823863954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.823863954
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2377787096
Short name T121
Test name
Test status
Simulation time 176489791 ps
CPU time 1.2 seconds
Started Jul 23 05:47:02 PM PDT 24
Finished Jul 23 05:47:07 PM PDT 24
Peak memory 200148 kb
Host smart-3d96ee98-e040-4bd2-bcab-5e677cb0f95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377787096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2377787096
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.822714560
Short name T4
Test name
Test status
Simulation time 191740122 ps
CPU time 1.51 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:08 PM PDT 24
Peak memory 200356 kb
Host smart-4d713d28-0d94-4205-a4c9-588c2288335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822714560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.822714560
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1004222720
Short name T513
Test name
Test status
Simulation time 5813085154 ps
CPU time 19.35 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 200484 kb
Host smart-1a6fdccd-5dea-438c-b083-24975ab8a27c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004222720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1004222720
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.165490384
Short name T310
Test name
Test status
Simulation time 512442571 ps
CPU time 2.75 seconds
Started Jul 23 05:47:06 PM PDT 24
Finished Jul 23 05:47:12 PM PDT 24
Peak memory 200096 kb
Host smart-d4d72691-a314-4cf4-b924-f2e2a70f1964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165490384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.165490384
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.4200717364
Short name T395
Test name
Test status
Simulation time 203912270 ps
CPU time 1.22 seconds
Started Jul 23 05:47:03 PM PDT 24
Finished Jul 23 05:47:07 PM PDT 24
Peak memory 200056 kb
Host smart-91c85a15-22b1-4a4e-b7f5-315caa183a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200717364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.4200717364
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.4052112604
Short name T47
Test name
Test status
Simulation time 64819929 ps
CPU time 0.75 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:44 PM PDT 24
Peak memory 199928 kb
Host smart-c0eb121f-e3fd-46ae-8f83-aaf90e4a7a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052112604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.4052112604
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3793149635
Short name T432
Test name
Test status
Simulation time 1890840685 ps
CPU time 6.72 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:50 PM PDT 24
Peak memory 217820 kb
Host smart-4173f7cd-6911-46ab-84f0-eaf9f8690bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793149635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3793149635
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.738580560
Short name T306
Test name
Test status
Simulation time 244779544 ps
CPU time 1.08 seconds
Started Jul 23 05:45:43 PM PDT 24
Finished Jul 23 05:45:45 PM PDT 24
Peak memory 217452 kb
Host smart-07f31542-953a-4606-9aaa-8e4064df0bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738580560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.738580560
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.399175567
Short name T379
Test name
Test status
Simulation time 77779496 ps
CPU time 0.75 seconds
Started Jul 23 05:45:39 PM PDT 24
Finished Jul 23 05:45:41 PM PDT 24
Peak memory 199844 kb
Host smart-0d48993d-511a-4121-8ec4-3eb89b97167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399175567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.399175567
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.618454001
Short name T194
Test name
Test status
Simulation time 1039452224 ps
CPU time 4.99 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:46 PM PDT 24
Peak memory 200412 kb
Host smart-5d2268fe-3771-4c18-a499-733947028994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618454001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.618454001
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2991432548
Short name T60
Test name
Test status
Simulation time 8471175920 ps
CPU time 12.97 seconds
Started Jul 23 05:45:43 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 217080 kb
Host smart-c4bdff5e-14aa-4084-bdf7-01187df7a84f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991432548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2991432548
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2036464898
Short name T370
Test name
Test status
Simulation time 105621462 ps
CPU time 1 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:43 PM PDT 24
Peak memory 200080 kb
Host smart-dca7be50-2a65-4979-95a4-6263229171a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036464898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2036464898
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2164673811
Short name T401
Test name
Test status
Simulation time 255782414 ps
CPU time 1.54 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:42 PM PDT 24
Peak memory 200288 kb
Host smart-1b4e31eb-0b6c-4956-ae71-78ba3db9cc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164673811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2164673811
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3445875439
Short name T450
Test name
Test status
Simulation time 6705550995 ps
CPU time 27.7 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:46:11 PM PDT 24
Peak memory 216240 kb
Host smart-c862159d-650c-4ff9-b113-35815254b4c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445875439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3445875439
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3260203165
Short name T483
Test name
Test status
Simulation time 461161113 ps
CPU time 2.33 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:43 PM PDT 24
Peak memory 200212 kb
Host smart-b9ce327b-9aaf-4532-9b7d-60eccb82caa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260203165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3260203165
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3330696567
Short name T134
Test name
Test status
Simulation time 126872822 ps
CPU time 1.1 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:43 PM PDT 24
Peak memory 200056 kb
Host smart-1f4d1b8f-0d3c-4380-ae0f-c8b0235a0e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330696567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3330696567
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2929906514
Short name T296
Test name
Test status
Simulation time 79788235 ps
CPU time 0.79 seconds
Started Jul 23 05:47:12 PM PDT 24
Finished Jul 23 05:47:17 PM PDT 24
Peak memory 199824 kb
Host smart-494c19fe-6041-453d-aa0f-49499b503d8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929906514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2929906514
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1394551967
Short name T21
Test name
Test status
Simulation time 2363797621 ps
CPU time 7.69 seconds
Started Jul 23 05:47:18 PM PDT 24
Finished Jul 23 05:47:31 PM PDT 24
Peak memory 217080 kb
Host smart-6c3b1ca2-3b0c-421b-89d0-7356ab56255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394551967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1394551967
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3885898120
Short name T203
Test name
Test status
Simulation time 244532569 ps
CPU time 1.05 seconds
Started Jul 23 05:47:10 PM PDT 24
Finished Jul 23 05:47:15 PM PDT 24
Peak memory 217488 kb
Host smart-c78d3fc8-95c3-472a-a4e2-fa767e00f684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885898120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3885898120
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2255291430
Short name T13
Test name
Test status
Simulation time 104732774 ps
CPU time 0.79 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:19 PM PDT 24
Peak memory 199800 kb
Host smart-428bb0db-55d0-4ee0-a20d-f551ce59a9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255291430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2255291430
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2506568371
Short name T87
Test name
Test status
Simulation time 1381621977 ps
CPU time 5.7 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:24 PM PDT 24
Peak memory 200448 kb
Host smart-8e00e657-a961-4b19-9315-15e35211d165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506568371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2506568371
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.177778481
Short name T488
Test name
Test status
Simulation time 100732221 ps
CPU time 0.97 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:16 PM PDT 24
Peak memory 200140 kb
Host smart-0ee5b5d3-9559-41c8-9b7d-e422a9512bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177778481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.177778481
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3518855125
Short name T464
Test name
Test status
Simulation time 189367807 ps
CPU time 1.38 seconds
Started Jul 23 05:47:10 PM PDT 24
Finished Jul 23 05:47:16 PM PDT 24
Peak memory 200572 kb
Host smart-62c68322-3bdd-4bf8-a03b-0681119e7ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518855125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3518855125
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4261669441
Short name T305
Test name
Test status
Simulation time 414650857 ps
CPU time 2.4 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:20 PM PDT 24
Peak memory 200012 kb
Host smart-e69e1ee0-0b5d-4435-8fe8-767aaf4dfe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261669441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4261669441
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2728612273
Short name T231
Test name
Test status
Simulation time 290376100 ps
CPU time 1.66 seconds
Started Jul 23 05:47:10 PM PDT 24
Finished Jul 23 05:47:16 PM PDT 24
Peak memory 200300 kb
Host smart-b827e7c7-4e46-460a-9a3d-78dcfd60fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728612273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2728612273
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1962474272
Short name T439
Test name
Test status
Simulation time 72898023 ps
CPU time 0.85 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 199940 kb
Host smart-19eea0de-05d9-40ce-a339-9ddb6eef47c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962474272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1962474272
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2228057169
Short name T388
Test name
Test status
Simulation time 1220661990 ps
CPU time 5.99 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:22 PM PDT 24
Peak memory 217584 kb
Host smart-f3f032f7-1633-484f-8cf5-4e17c7223cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228057169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2228057169
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2202062233
Short name T433
Test name
Test status
Simulation time 243917221 ps
CPU time 1.09 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:16 PM PDT 24
Peak memory 217508 kb
Host smart-2fb435f5-62ba-49ac-b597-eeeed902c61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202062233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2202062233
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.45735369
Short name T151
Test name
Test status
Simulation time 109913820 ps
CPU time 0.77 seconds
Started Jul 23 05:47:16 PM PDT 24
Finished Jul 23 05:47:22 PM PDT 24
Peak memory 199960 kb
Host smart-4a912193-dcda-4470-8c3f-95db5570740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45735369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.45735369
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2941998211
Short name T458
Test name
Test status
Simulation time 1976828492 ps
CPU time 6.84 seconds
Started Jul 23 05:47:11 PM PDT 24
Finished Jul 23 05:47:22 PM PDT 24
Peak memory 200424 kb
Host smart-778c5182-abe9-4a39-8398-dc053ef2ec5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941998211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2941998211
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3879670242
Short name T532
Test name
Test status
Simulation time 99408694 ps
CPU time 0.99 seconds
Started Jul 23 05:47:10 PM PDT 24
Finished Jul 23 05:47:15 PM PDT 24
Peak memory 200136 kb
Host smart-c27d28f4-a4d2-40cc-b12c-91af91796f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879670242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3879670242
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3571109844
Short name T408
Test name
Test status
Simulation time 198415621 ps
CPU time 1.44 seconds
Started Jul 23 05:47:17 PM PDT 24
Finished Jul 23 05:47:23 PM PDT 24
Peak memory 200348 kb
Host smart-b8d8a365-8fe8-4655-8eb3-fb1c25e53601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571109844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3571109844
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.651236964
Short name T527
Test name
Test status
Simulation time 1441585990 ps
CPU time 5.53 seconds
Started Jul 23 05:47:13 PM PDT 24
Finished Jul 23 05:47:23 PM PDT 24
Peak memory 200364 kb
Host smart-d3acc51c-4540-4f97-92ae-9b5827bd14b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651236964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.651236964
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3460489584
Short name T312
Test name
Test status
Simulation time 122855711 ps
CPU time 1.62 seconds
Started Jul 23 05:47:12 PM PDT 24
Finished Jul 23 05:47:18 PM PDT 24
Peak memory 208340 kb
Host smart-21f2d3f7-84c7-48f7-b9bb-eb4a82baa879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460489584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3460489584
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1178021880
Short name T346
Test name
Test status
Simulation time 84237786 ps
CPU time 0.86 seconds
Started Jul 23 05:47:16 PM PDT 24
Finished Jul 23 05:47:23 PM PDT 24
Peak memory 200144 kb
Host smart-ca6a6c89-f732-443e-824f-a561f8fe0785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178021880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1178021880
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2389885396
Short name T344
Test name
Test status
Simulation time 61272975 ps
CPU time 0.83 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 199940 kb
Host smart-46693f4a-2e05-4277-9762-aabd046eedfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389885396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2389885396
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1504051775
Short name T41
Test name
Test status
Simulation time 1903793906 ps
CPU time 6.69 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:39 PM PDT 24
Peak memory 217820 kb
Host smart-836f5f7c-4bdf-4943-9a60-b0a511c481d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504051775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1504051775
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2685660838
Short name T505
Test name
Test status
Simulation time 251824229 ps
CPU time 1.04 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:26 PM PDT 24
Peak memory 208936 kb
Host smart-f6eeb5c9-0fc3-43aa-8ec8-3c22439122a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685660838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2685660838
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1590112738
Short name T423
Test name
Test status
Simulation time 171158151 ps
CPU time 0.9 seconds
Started Jul 23 05:47:16 PM PDT 24
Finished Jul 23 05:47:22 PM PDT 24
Peak memory 199920 kb
Host smart-9205d437-b250-4bdc-9182-def7027ddf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590112738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1590112738
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.849632456
Short name T141
Test name
Test status
Simulation time 1001671721 ps
CPU time 4.74 seconds
Started Jul 23 05:47:21 PM PDT 24
Finished Jul 23 05:47:31 PM PDT 24
Peak memory 200468 kb
Host smart-e9b1a026-5545-4ecf-9854-5900460fe53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849632456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.849632456
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.348036959
Short name T277
Test name
Test status
Simulation time 101661276 ps
CPU time 0.99 seconds
Started Jul 23 05:47:17 PM PDT 24
Finished Jul 23 05:47:23 PM PDT 24
Peak memory 200144 kb
Host smart-a20870ae-4141-4de1-9cf2-6d1fd2b42a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348036959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.348036959
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.740727460
Short name T534
Test name
Test status
Simulation time 205457905 ps
CPU time 1.57 seconds
Started Jul 23 05:47:21 PM PDT 24
Finished Jul 23 05:47:28 PM PDT 24
Peak memory 200348 kb
Host smart-246b23d6-303e-447e-bdfa-7d62f66a8c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740727460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.740727460
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2890099703
Short name T6
Test name
Test status
Simulation time 2708262077 ps
CPU time 12.35 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:37 PM PDT 24
Peak memory 208660 kb
Host smart-42af763a-09e1-47ff-9d62-be5282d2ca29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890099703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2890099703
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2426471797
Short name T51
Test name
Test status
Simulation time 137325499 ps
CPU time 1.65 seconds
Started Jul 23 05:47:17 PM PDT 24
Finished Jul 23 05:47:25 PM PDT 24
Peak memory 208296 kb
Host smart-8e5c5a07-a621-4c11-b89d-7bd4ca72eec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426471797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2426471797
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3563945390
Short name T495
Test name
Test status
Simulation time 62232362 ps
CPU time 0.8 seconds
Started Jul 23 05:47:19 PM PDT 24
Finished Jul 23 05:47:25 PM PDT 24
Peak memory 200096 kb
Host smart-16ac9a0e-b7c2-45b2-bc20-8bb8112ca93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563945390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3563945390
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2752988161
Short name T494
Test name
Test status
Simulation time 95528266 ps
CPU time 0.83 seconds
Started Jul 23 05:47:19 PM PDT 24
Finished Jul 23 05:47:25 PM PDT 24
Peak memory 199852 kb
Host smart-da04c938-9974-49ce-89b9-d4fdf62ed9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752988161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2752988161
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.884198785
Short name T28
Test name
Test status
Simulation time 1225121559 ps
CPU time 6.21 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 217536 kb
Host smart-47c8e319-ba59-4506-b333-8d539eb356ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884198785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.884198785
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3998919695
Short name T192
Test name
Test status
Simulation time 244189734 ps
CPU time 1.03 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:27 PM PDT 24
Peak memory 217508 kb
Host smart-bf3683b3-892f-43cd-bf26-37b7dce69c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998919695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3998919695
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1765686369
Short name T205
Test name
Test status
Simulation time 139566598 ps
CPU time 0.8 seconds
Started Jul 23 05:47:18 PM PDT 24
Finished Jul 23 05:47:24 PM PDT 24
Peak memory 199948 kb
Host smart-b78e09fa-70da-4c25-a154-1c2b60374315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765686369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1765686369
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1096343112
Short name T487
Test name
Test status
Simulation time 1489914797 ps
CPU time 5.39 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:32 PM PDT 24
Peak memory 200408 kb
Host smart-0868cb10-5ad8-486e-a38c-44e3d4b99e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096343112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1096343112
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2988779621
Short name T445
Test name
Test status
Simulation time 92235382 ps
CPU time 1 seconds
Started Jul 23 05:47:17 PM PDT 24
Finished Jul 23 05:47:24 PM PDT 24
Peak memory 199988 kb
Host smart-7145bcec-884b-4354-80d0-08556d323a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988779621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2988779621
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.4152576241
Short name T286
Test name
Test status
Simulation time 115580302 ps
CPU time 1.12 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:27 PM PDT 24
Peak memory 200380 kb
Host smart-6afcf9be-e0d5-440a-8322-db4eed165e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152576241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.4152576241
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3109171950
Short name T362
Test name
Test status
Simulation time 1820371957 ps
CPU time 6.78 seconds
Started Jul 23 05:47:21 PM PDT 24
Finished Jul 23 05:47:39 PM PDT 24
Peak memory 209856 kb
Host smart-824d325c-415e-4c7e-b604-fabf635365a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109171950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3109171950
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.26227924
Short name T125
Test name
Test status
Simulation time 240707886 ps
CPU time 1.69 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:28 PM PDT 24
Peak memory 200096 kb
Host smart-d1f33da1-a9c4-47b8-b5c2-25117de9960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26227924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.26227924
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2048670032
Short name T372
Test name
Test status
Simulation time 169148689 ps
CPU time 1.28 seconds
Started Jul 23 05:47:20 PM PDT 24
Finished Jul 23 05:47:27 PM PDT 24
Peak memory 200336 kb
Host smart-4947837c-fe1b-484a-a5f7-124b69b97be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048670032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2048670032
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2647094563
Short name T146
Test name
Test status
Simulation time 75066529 ps
CPU time 0.78 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 199928 kb
Host smart-65bae38a-c597-412b-8117-59615f5309b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647094563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2647094563
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1013230690
Short name T23
Test name
Test status
Simulation time 1900429544 ps
CPU time 7.06 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:39 PM PDT 24
Peak memory 221744 kb
Host smart-92441ee0-d026-41b4-a68f-7c312b40511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013230690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1013230690
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4228809013
Short name T323
Test name
Test status
Simulation time 245035274 ps
CPU time 1.02 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 217532 kb
Host smart-638b6dca-0c5a-4e83-84cf-5c11f1e70c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228809013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4228809013
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3039121897
Short name T19
Test name
Test status
Simulation time 184490598 ps
CPU time 0.88 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 199956 kb
Host smart-7ee1ead1-3376-46cc-a767-addca1d7dd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039121897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3039121897
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1786049235
Short name T266
Test name
Test status
Simulation time 766903589 ps
CPU time 4.1 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:35 PM PDT 24
Peak memory 200412 kb
Host smart-427d87d2-2cd3-4dc1-8d1a-69cd7e9ad91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786049235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1786049235
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1935341534
Short name T137
Test name
Test status
Simulation time 157951505 ps
CPU time 1.08 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 200132 kb
Host smart-dfa85e11-c882-4aed-9b5f-d0504be07f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935341534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1935341534
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1227781503
Short name T238
Test name
Test status
Simulation time 125872887 ps
CPU time 1.29 seconds
Started Jul 23 05:47:18 PM PDT 24
Finished Jul 23 05:47:25 PM PDT 24
Peak memory 200348 kb
Host smart-90795a1c-0af7-4cd7-88bf-717d86b69b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227781503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1227781503
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2508207341
Short name T441
Test name
Test status
Simulation time 3285395205 ps
CPU time 13.1 seconds
Started Jul 23 05:47:29 PM PDT 24
Finished Jul 23 05:47:49 PM PDT 24
Peak memory 210532 kb
Host smart-d65d4ebf-7938-4748-a9c6-2539e2ed66ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508207341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2508207341
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2824844856
Short name T403
Test name
Test status
Simulation time 314950457 ps
CPU time 1.84 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:34 PM PDT 24
Peak memory 200156 kb
Host smart-7a584ae2-a9ce-4b69-827e-cb7979e4f473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824844856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2824844856
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.639732344
Short name T70
Test name
Test status
Simulation time 228117912 ps
CPU time 1.35 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:32 PM PDT 24
Peak memory 200104 kb
Host smart-2a93e145-7851-4cb3-a8a6-cd03a8be84a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639732344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.639732344
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.561339684
Short name T167
Test name
Test status
Simulation time 69242101 ps
CPU time 0.81 seconds
Started Jul 23 05:47:24 PM PDT 24
Finished Jul 23 05:47:31 PM PDT 24
Peak memory 199952 kb
Host smart-b2d0fc24-370b-42b0-b6f6-a63879143330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561339684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.561339684
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.4088231857
Short name T250
Test name
Test status
Simulation time 1234460747 ps
CPU time 5.41 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:37 PM PDT 24
Peak memory 217836 kb
Host smart-043d7791-3857-464a-a254-2168902a9f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088231857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.4088231857
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.32432315
Short name T160
Test name
Test status
Simulation time 244416642 ps
CPU time 1.11 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:34 PM PDT 24
Peak memory 217504 kb
Host smart-b5902144-d6e9-4e23-a84d-598f85af011f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32432315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.32432315
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3715546614
Short name T262
Test name
Test status
Simulation time 105779494 ps
CPU time 0.78 seconds
Started Jul 23 05:47:29 PM PDT 24
Finished Jul 23 05:47:37 PM PDT 24
Peak memory 199840 kb
Host smart-f5901500-d049-4082-9506-4605aacc8f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715546614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3715546614
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.380120747
Short name T399
Test name
Test status
Simulation time 1114697460 ps
CPU time 5.06 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:40 PM PDT 24
Peak memory 200360 kb
Host smart-d2b83901-84ee-4dae-811a-04632f48dce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380120747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.380120747
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2064164030
Short name T152
Test name
Test status
Simulation time 101122055 ps
CPU time 1.02 seconds
Started Jul 23 05:47:29 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 200120 kb
Host smart-3c7024e6-6a96-406a-a57a-bd1be7991be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064164030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2064164030
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2024446875
Short name T461
Test name
Test status
Simulation time 125272197 ps
CPU time 1.2 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:34 PM PDT 24
Peak memory 200356 kb
Host smart-5cd87523-2884-4348-a67b-04065d057192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024446875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2024446875
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1256182020
Short name T183
Test name
Test status
Simulation time 9718311850 ps
CPU time 33.62 seconds
Started Jul 23 05:47:27 PM PDT 24
Finished Jul 23 05:48:08 PM PDT 24
Peak memory 208668 kb
Host smart-20db335e-d8ff-4f12-8125-6f72e55d4b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256182020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1256182020
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1533786739
Short name T77
Test name
Test status
Simulation time 503498733 ps
CPU time 2.59 seconds
Started Jul 23 05:47:26 PM PDT 24
Finished Jul 23 05:47:35 PM PDT 24
Peak memory 200188 kb
Host smart-37d17f75-4de5-4349-bded-acbe095b8acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533786739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1533786739
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3301238974
Short name T268
Test name
Test status
Simulation time 196400563 ps
CPU time 1.26 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 200060 kb
Host smart-b24cba39-7732-410e-91d1-aade47a6fb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301238974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3301238974
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2041701788
Short name T291
Test name
Test status
Simulation time 75446844 ps
CPU time 0.81 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:43 PM PDT 24
Peak memory 199892 kb
Host smart-9e32803a-54eb-4f6a-b531-9a990c9e75fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041701788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2041701788
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1275041242
Short name T537
Test name
Test status
Simulation time 1892757765 ps
CPU time 6.82 seconds
Started Jul 23 05:47:29 PM PDT 24
Finished Jul 23 05:47:43 PM PDT 24
Peak memory 217780 kb
Host smart-4b510fea-da5d-48bc-9464-d7daff47a59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275041242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1275041242
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.787706339
Short name T182
Test name
Test status
Simulation time 246242030 ps
CPU time 1.1 seconds
Started Jul 23 05:47:45 PM PDT 24
Finished Jul 23 05:47:51 PM PDT 24
Peak memory 217496 kb
Host smart-e7bdc98e-eba3-46aa-a1ee-52c95453df3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787706339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.787706339
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1690743103
Short name T14
Test name
Test status
Simulation time 162608832 ps
CPU time 0.94 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:42 PM PDT 24
Peak memory 199896 kb
Host smart-c50a2758-00ec-4e76-be5c-7f36f474d5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690743103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1690743103
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3577733685
Short name T30
Test name
Test status
Simulation time 1670121540 ps
CPU time 6.48 seconds
Started Jul 23 05:47:38 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 200360 kb
Host smart-a59148fa-9a66-4c3d-98d7-0b4f302198cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577733685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3577733685
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3925792324
Short name T416
Test name
Test status
Simulation time 98491179 ps
CPU time 0.97 seconds
Started Jul 23 05:47:28 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 200028 kb
Host smart-109422d8-fea6-42ca-b990-486ca9bc20a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925792324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3925792324
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.25882023
Short name T224
Test name
Test status
Simulation time 203949231 ps
CPU time 1.48 seconds
Started Jul 23 05:47:29 PM PDT 24
Finished Jul 23 05:47:37 PM PDT 24
Peak memory 200244 kb
Host smart-05784c10-9fcb-486a-b128-45d943ebe776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25882023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.25882023
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.702798710
Short name T381
Test name
Test status
Simulation time 118408745 ps
CPU time 1.14 seconds
Started Jul 23 05:47:34 PM PDT 24
Finished Jul 23 05:47:42 PM PDT 24
Peak memory 199896 kb
Host smart-8c9406b2-e57e-4d7d-80c8-0a87894cd5fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702798710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.702798710
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3442500005
Short name T138
Test name
Test status
Simulation time 249490030 ps
CPU time 1.71 seconds
Started Jul 23 05:47:25 PM PDT 24
Finished Jul 23 05:47:33 PM PDT 24
Peak memory 200156 kb
Host smart-1df64aec-e005-4f8d-be6c-f530b4209733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442500005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3442500005
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2557484755
Short name T331
Test name
Test status
Simulation time 77746196 ps
CPU time 0.79 seconds
Started Jul 23 05:47:32 PM PDT 24
Finished Jul 23 05:47:40 PM PDT 24
Peak memory 200088 kb
Host smart-f4ca94cc-0bb6-4c16-9067-caee1c5ba1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557484755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2557484755
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1985131640
Short name T380
Test name
Test status
Simulation time 66745638 ps
CPU time 0.75 seconds
Started Jul 23 05:47:33 PM PDT 24
Finished Jul 23 05:47:41 PM PDT 24
Peak memory 199904 kb
Host smart-bc3d7e3a-d765-46fa-bef8-cdb157c5dd36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985131640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1985131640
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1511969138
Short name T22
Test name
Test status
Simulation time 1231824232 ps
CPU time 5.29 seconds
Started Jul 23 05:47:38 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 221892 kb
Host smart-91b4feac-1b08-4c1d-b505-9a32dd5a3983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511969138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1511969138
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.479291680
Short name T511
Test name
Test status
Simulation time 245110199 ps
CPU time 1.14 seconds
Started Jul 23 05:47:37 PM PDT 24
Finished Jul 23 05:47:45 PM PDT 24
Peak memory 217452 kb
Host smart-4353186b-81bc-4e6d-a38a-2dd3e27c7fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479291680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.479291680
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2596198839
Short name T318
Test name
Test status
Simulation time 174455268 ps
CPU time 0.85 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:42 PM PDT 24
Peak memory 199872 kb
Host smart-60ee6c93-1c9d-4bda-9e58-b9d29296d90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596198839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2596198839
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.4148966894
Short name T233
Test name
Test status
Simulation time 953588978 ps
CPU time 4.84 seconds
Started Jul 23 05:47:39 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 200408 kb
Host smart-4bea5e55-58ef-4323-b4fa-f5c8986a10f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148966894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.4148966894
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.4204339801
Short name T202
Test name
Test status
Simulation time 186315127 ps
CPU time 1.24 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:44 PM PDT 24
Peak memory 200080 kb
Host smart-20b78cc2-5868-4517-a208-5004f8e7c99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204339801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.4204339801
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1154133750
Short name T221
Test name
Test status
Simulation time 119488088 ps
CPU time 1.28 seconds
Started Jul 23 05:47:31 PM PDT 24
Finished Jul 23 05:47:39 PM PDT 24
Peak memory 200344 kb
Host smart-fdbf9551-5bd5-458f-99b8-37e0afc5cad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154133750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1154133750
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4102280642
Short name T78
Test name
Test status
Simulation time 1428508317 ps
CPU time 5.65 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:48 PM PDT 24
Peak memory 200432 kb
Host smart-9b22b6dc-7ef2-429d-ab58-9c7ab9f3ab6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102280642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4102280642
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.285803505
Short name T149
Test name
Test status
Simulation time 355832748 ps
CPU time 2.27 seconds
Started Jul 23 05:47:32 PM PDT 24
Finished Jul 23 05:47:41 PM PDT 24
Peak memory 200164 kb
Host smart-a083cc86-7d13-4146-8815-1f2d7fbf5296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285803505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.285803505
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3687667326
Short name T469
Test name
Test status
Simulation time 158066974 ps
CPU time 1.26 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:44 PM PDT 24
Peak memory 200320 kb
Host smart-b1eaf151-1275-4797-be60-1c87387c36cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687667326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3687667326
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1022453147
Short name T316
Test name
Test status
Simulation time 69028647 ps
CPU time 0.72 seconds
Started Jul 23 05:47:37 PM PDT 24
Finished Jul 23 05:47:44 PM PDT 24
Peak memory 199932 kb
Host smart-f05d5fed-8cef-4b4d-a656-c772de7ba09c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022453147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1022453147
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3743983641
Short name T39
Test name
Test status
Simulation time 2361924085 ps
CPU time 8.36 seconds
Started Jul 23 05:47:39 PM PDT 24
Finished Jul 23 05:47:53 PM PDT 24
Peak memory 217932 kb
Host smart-4e846254-6bf0-4915-9c25-72b6197ddae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743983641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3743983641
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2762508695
Short name T382
Test name
Test status
Simulation time 245358515 ps
CPU time 1.02 seconds
Started Jul 23 05:47:31 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 209068 kb
Host smart-c2c5af40-1e32-4470-8c65-9b9ce54765a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762508695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2762508695
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2641610020
Short name T164
Test name
Test status
Simulation time 144661392 ps
CPU time 0.8 seconds
Started Jul 23 05:47:41 PM PDT 24
Finished Jul 23 05:47:47 PM PDT 24
Peak memory 199908 kb
Host smart-cec2dcb8-8bde-4f5d-9e03-011a779ce630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641610020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2641610020
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1724679021
Short name T150
Test name
Test status
Simulation time 867210789 ps
CPU time 4.66 seconds
Started Jul 23 05:47:33 PM PDT 24
Finished Jul 23 05:47:45 PM PDT 24
Peak memory 200420 kb
Host smart-f74de632-dcd0-4cab-804e-d37c215acf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724679021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1724679021
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1904637166
Short name T204
Test name
Test status
Simulation time 174827660 ps
CPU time 1.16 seconds
Started Jul 23 05:47:39 PM PDT 24
Finished Jul 23 05:47:47 PM PDT 24
Peak memory 200084 kb
Host smart-3f11842a-5ae8-4446-9f2c-adfb9f7ac5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904637166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1904637166
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4026754944
Short name T307
Test name
Test status
Simulation time 199151231 ps
CPU time 1.42 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:43 PM PDT 24
Peak memory 200260 kb
Host smart-8d0cf8c7-107e-437b-a6ca-ee34485abc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026754944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4026754944
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2532478088
Short name T526
Test name
Test status
Simulation time 9148566481 ps
CPU time 31.72 seconds
Started Jul 23 05:47:29 PM PDT 24
Finished Jul 23 05:48:08 PM PDT 24
Peak memory 209416 kb
Host smart-deae4007-c939-4429-9cbf-e4b919e0a7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532478088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2532478088
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1539269075
Short name T223
Test name
Test status
Simulation time 398658298 ps
CPU time 2.41 seconds
Started Jul 23 05:47:37 PM PDT 24
Finished Jul 23 05:47:45 PM PDT 24
Peak memory 200156 kb
Host smart-04a005c6-95b6-4073-aa7a-3da805f310ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539269075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1539269075
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4134215870
Short name T320
Test name
Test status
Simulation time 146867012 ps
CPU time 1.24 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:44 PM PDT 24
Peak memory 200328 kb
Host smart-d0f743d2-081c-4013-ad63-d41a35bc290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134215870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4134215870
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2547174069
Short name T397
Test name
Test status
Simulation time 67813119 ps
CPU time 0.75 seconds
Started Jul 23 05:47:47 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 199956 kb
Host smart-fa809a4f-5745-4ef5-b72c-abd75f2c38ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547174069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2547174069
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4288417302
Short name T481
Test name
Test status
Simulation time 1892506691 ps
CPU time 7.67 seconds
Started Jul 23 05:47:38 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 216768 kb
Host smart-97af9773-7842-4521-8ae3-39aeec659706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288417302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4288417302
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2636363217
Short name T189
Test name
Test status
Simulation time 243537170 ps
CPU time 1.1 seconds
Started Jul 23 05:47:42 PM PDT 24
Finished Jul 23 05:47:49 PM PDT 24
Peak memory 217492 kb
Host smart-62e47d66-5815-46a4-bdbe-ca7fe735cd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636363217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2636363217
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.535974148
Short name T11
Test name
Test status
Simulation time 148577657 ps
CPU time 0.86 seconds
Started Jul 23 05:47:34 PM PDT 24
Finished Jul 23 05:47:41 PM PDT 24
Peak memory 199928 kb
Host smart-c09f393d-4d58-44a2-bd3d-3814b245e736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535974148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.535974148
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3607824893
Short name T170
Test name
Test status
Simulation time 922951767 ps
CPU time 4.72 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:48 PM PDT 24
Peak memory 200404 kb
Host smart-ce94ed17-0297-4e65-9e92-5282d95c4707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607824893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3607824893
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3048249301
Short name T419
Test name
Test status
Simulation time 178568370 ps
CPU time 1.16 seconds
Started Jul 23 05:47:47 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 200148 kb
Host smart-850d0311-92a7-4215-9d5c-e826ec62217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048249301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3048249301
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1164100377
Short name T159
Test name
Test status
Simulation time 205065505 ps
CPU time 1.36 seconds
Started Jul 23 05:47:30 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 200356 kb
Host smart-fe062280-d14e-47b6-a7dd-55ca116e539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164100377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1164100377
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2077666730
Short name T216
Test name
Test status
Simulation time 2931763878 ps
CPU time 14.39 seconds
Started Jul 23 05:47:42 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 200420 kb
Host smart-c5221147-0bf9-498e-84ad-f82a88db6ac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077666730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2077666730
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1943641784
Short name T340
Test name
Test status
Simulation time 152734894 ps
CPU time 1.91 seconds
Started Jul 23 05:47:37 PM PDT 24
Finished Jul 23 05:47:45 PM PDT 24
Peak memory 200164 kb
Host smart-c86ac15b-f4a2-4e05-ad88-bd6bcb76747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943641784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1943641784
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.847898645
Short name T311
Test name
Test status
Simulation time 185111840 ps
CPU time 1.11 seconds
Started Jul 23 05:47:30 PM PDT 24
Finished Jul 23 05:47:38 PM PDT 24
Peak memory 200148 kb
Host smart-0c13d0fd-1375-4105-9049-214eceaa6189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847898645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.847898645
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1320984334
Short name T228
Test name
Test status
Simulation time 71283201 ps
CPU time 0.83 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:45:58 PM PDT 24
Peak memory 199928 kb
Host smart-444bc1ce-5a20-4e6e-85b9-44bab33416ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320984334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1320984334
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.14817642
Short name T26
Test name
Test status
Simulation time 1891388888 ps
CPU time 7.51 seconds
Started Jul 23 05:45:43 PM PDT 24
Finished Jul 23 05:45:52 PM PDT 24
Peak memory 217744 kb
Host smart-efadb35a-77c8-4c44-a12f-7154af7a7aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14817642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.14817642
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4016789342
Short name T471
Test name
Test status
Simulation time 244997089 ps
CPU time 1.11 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:42 PM PDT 24
Peak memory 217564 kb
Host smart-734769fc-0e9c-4c86-991d-48f9c81fc7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016789342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4016789342
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2200036745
Short name T283
Test name
Test status
Simulation time 153829042 ps
CPU time 0.88 seconds
Started Jul 23 05:45:42 PM PDT 24
Finished Jul 23 05:45:45 PM PDT 24
Peak memory 199868 kb
Host smart-da3a97bc-de58-4c58-bbf1-201ffb05c5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200036745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2200036745
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4178926554
Short name T371
Test name
Test status
Simulation time 1572092091 ps
CPU time 5.88 seconds
Started Jul 23 05:45:37 PM PDT 24
Finished Jul 23 05:45:44 PM PDT 24
Peak memory 200364 kb
Host smart-a019a08b-3cfe-4cc4-9125-c7936ec93a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178926554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4178926554
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2132007329
Short name T65
Test name
Test status
Simulation time 8326644405 ps
CPU time 13.24 seconds
Started Jul 23 05:45:42 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 217264 kb
Host smart-a4e923a3-8a7d-4327-807f-3ababede0332
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132007329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2132007329
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1447224262
Short name T256
Test name
Test status
Simulation time 106230583 ps
CPU time 1 seconds
Started Jul 23 05:45:39 PM PDT 24
Finished Jul 23 05:45:41 PM PDT 24
Peak memory 200096 kb
Host smart-ef96eebe-0318-4a3a-ad3e-db25e9d8acb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447224262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1447224262
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3140565534
Short name T145
Test name
Test status
Simulation time 246403275 ps
CPU time 1.6 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:45:44 PM PDT 24
Peak memory 200344 kb
Host smart-e4697306-46a7-44d8-ae8d-0d0c45cbd3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140565534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3140565534
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.827914893
Short name T525
Test name
Test status
Simulation time 14667139486 ps
CPU time 52.55 seconds
Started Jul 23 05:45:40 PM PDT 24
Finished Jul 23 05:46:34 PM PDT 24
Peak memory 216836 kb
Host smart-30a03b0e-4c5b-42a6-baa3-369c47cfec95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827914893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.827914893
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.4016080940
Short name T533
Test name
Test status
Simulation time 547993193 ps
CPU time 3.05 seconds
Started Jul 23 05:45:42 PM PDT 24
Finished Jul 23 05:45:47 PM PDT 24
Peak memory 200064 kb
Host smart-f7e74d63-bcd9-42eb-b3b7-da9b4ada499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016080940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.4016080940
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2970760408
Short name T123
Test name
Test status
Simulation time 106452773 ps
CPU time 0.95 seconds
Started Jul 23 05:45:41 PM PDT 24
Finished Jul 23 05:45:44 PM PDT 24
Peak memory 200064 kb
Host smart-2d06f9dd-bc3b-487f-b094-e1f62966c401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970760408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2970760408
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.825417580
Short name T158
Test name
Test status
Simulation time 67665034 ps
CPU time 0.77 seconds
Started Jul 23 05:47:38 PM PDT 24
Finished Jul 23 05:47:46 PM PDT 24
Peak memory 199916 kb
Host smart-b8c32e33-2011-4ca5-9c2f-cd8e523fe002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825417580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.825417580
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2129804673
Short name T475
Test name
Test status
Simulation time 1895839015 ps
CPU time 6.92 seconds
Started Jul 23 05:47:34 PM PDT 24
Finished Jul 23 05:47:47 PM PDT 24
Peak memory 217784 kb
Host smart-b5459b30-7fa2-4359-ab35-bba35f7be29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129804673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2129804673
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2940216183
Short name T531
Test name
Test status
Simulation time 243954065 ps
CPU time 1.05 seconds
Started Jul 23 05:47:47 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 217492 kb
Host smart-de5f4ec9-30a3-47a4-ae0c-2713974f4f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940216183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2940216183
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1732682120
Short name T347
Test name
Test status
Simulation time 130444846 ps
CPU time 0.82 seconds
Started Jul 23 05:47:38 PM PDT 24
Finished Jul 23 05:47:46 PM PDT 24
Peak memory 199940 kb
Host smart-d85e6f0c-eba8-4fcc-9760-d84be1f875e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732682120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1732682120
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2081613976
Short name T529
Test name
Test status
Simulation time 1286034661 ps
CPU time 5.48 seconds
Started Jul 23 05:47:38 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 200420 kb
Host smart-39af0a7e-0e29-4b57-9542-2c723bb4a605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081613976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2081613976
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2455544916
Short name T411
Test name
Test status
Simulation time 113694034 ps
CPU time 1 seconds
Started Jul 23 05:47:36 PM PDT 24
Finished Jul 23 05:47:44 PM PDT 24
Peak memory 200044 kb
Host smart-1d61cfd7-320d-4777-9873-44a77f066391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455544916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2455544916
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1986656216
Short name T390
Test name
Test status
Simulation time 193904563 ps
CPU time 1.37 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:47:43 PM PDT 24
Peak memory 200328 kb
Host smart-f141fe5f-8d07-4510-885a-fe6beab8a9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986656216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1986656216
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2837727249
Short name T122
Test name
Test status
Simulation time 5779779833 ps
CPU time 25.07 seconds
Started Jul 23 05:47:35 PM PDT 24
Finished Jul 23 05:48:06 PM PDT 24
Peak memory 208644 kb
Host smart-00526fd1-68ae-4399-9e8c-eb026851d666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837727249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2837727249
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.812741254
Short name T515
Test name
Test status
Simulation time 139364562 ps
CPU time 1.81 seconds
Started Jul 23 05:47:39 PM PDT 24
Finished Jul 23 05:47:47 PM PDT 24
Peak memory 200148 kb
Host smart-cceea590-1c9a-4dbe-a8ae-07e68281b181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812741254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.812741254
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3183196271
Short name T193
Test name
Test status
Simulation time 117236149 ps
CPU time 0.96 seconds
Started Jul 23 05:47:45 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 200128 kb
Host smart-e8345858-874c-4237-88de-8c5d3e19bf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183196271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3183196271
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3213757966
Short name T491
Test name
Test status
Simulation time 62614208 ps
CPU time 0.79 seconds
Started Jul 23 05:47:46 PM PDT 24
Finished Jul 23 05:47:51 PM PDT 24
Peak memory 199928 kb
Host smart-5cdc7ae0-012c-47a6-bbf7-ca5a4895c6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213757966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3213757966
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.797192822
Short name T42
Test name
Test status
Simulation time 1901261330 ps
CPU time 7.22 seconds
Started Jul 23 05:47:48 PM PDT 24
Finished Jul 23 05:47:59 PM PDT 24
Peak memory 217796 kb
Host smart-5683f017-440d-4192-93b7-67f0bab82b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797192822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.797192822
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4038671884
Short name T264
Test name
Test status
Simulation time 243542187 ps
CPU time 1.12 seconds
Started Jul 23 05:47:45 PM PDT 24
Finished Jul 23 05:47:51 PM PDT 24
Peak memory 217560 kb
Host smart-56fcd92e-0a27-4c27-b91a-99083a43f43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038671884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4038671884
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3511958007
Short name T420
Test name
Test status
Simulation time 128787439 ps
CPU time 0.86 seconds
Started Jul 23 05:47:43 PM PDT 24
Finished Jul 23 05:47:49 PM PDT 24
Peak memory 199944 kb
Host smart-a265d4f5-4c66-4653-bf87-3fc4acfdaa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511958007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3511958007
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.4180622961
Short name T214
Test name
Test status
Simulation time 826738564 ps
CPU time 4.25 seconds
Started Jul 23 05:47:41 PM PDT 24
Finished Jul 23 05:47:51 PM PDT 24
Peak memory 200352 kb
Host smart-089f6148-7274-49f8-9999-394ed9805a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180622961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.4180622961
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2553479782
Short name T222
Test name
Test status
Simulation time 187315263 ps
CPU time 1.29 seconds
Started Jul 23 05:47:49 PM PDT 24
Finished Jul 23 05:47:54 PM PDT 24
Peak memory 200128 kb
Host smart-14616ea7-087d-4e41-b663-175003c853f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553479782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2553479782
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1044960079
Short name T255
Test name
Test status
Simulation time 204331582 ps
CPU time 1.37 seconds
Started Jul 23 05:47:45 PM PDT 24
Finished Jul 23 05:47:51 PM PDT 24
Peak memory 200344 kb
Host smart-a2cf5a91-be24-44b8-9264-912813e60465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044960079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1044960079
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2475898382
Short name T452
Test name
Test status
Simulation time 5878362103 ps
CPU time 26.99 seconds
Started Jul 23 05:47:48 PM PDT 24
Finished Jul 23 05:48:19 PM PDT 24
Peak memory 208588 kb
Host smart-df90d169-a01c-4174-96ed-c371d1f7b375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475898382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2475898382
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3601141372
Short name T265
Test name
Test status
Simulation time 148990457 ps
CPU time 1.82 seconds
Started Jul 23 05:47:46 PM PDT 24
Finished Jul 23 05:47:52 PM PDT 24
Peak memory 200128 kb
Host smart-e8176cd7-3b1b-4a56-badd-af1c85f6407a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601141372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3601141372
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3655122678
Short name T522
Test name
Test status
Simulation time 66654650 ps
CPU time 0.81 seconds
Started Jul 23 05:47:41 PM PDT 24
Finished Jul 23 05:47:48 PM PDT 24
Peak memory 200132 kb
Host smart-97c22810-8645-4ff1-973f-a88313d61b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655122678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3655122678
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.668087134
Short name T498
Test name
Test status
Simulation time 78570331 ps
CPU time 0.82 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:01 PM PDT 24
Peak memory 199856 kb
Host smart-3d94f713-adf6-4ec9-ab55-45010a25139a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668087134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.668087134
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3639080117
Short name T24
Test name
Test status
Simulation time 1220081494 ps
CPU time 5.74 seconds
Started Jul 23 05:47:46 PM PDT 24
Finished Jul 23 05:47:56 PM PDT 24
Peak memory 217572 kb
Host smart-6f470d2a-dfb0-423f-b7aa-8a74f90f7af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639080117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3639080117
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1349589436
Short name T493
Test name
Test status
Simulation time 243856992 ps
CPU time 1.19 seconds
Started Jul 23 05:47:46 PM PDT 24
Finished Jul 23 05:47:51 PM PDT 24
Peak memory 217500 kb
Host smart-8f04312b-f159-47cc-aded-e9f07b787c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349589436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1349589436
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2032930807
Short name T17
Test name
Test status
Simulation time 74651050 ps
CPU time 0.74 seconds
Started Jul 23 05:47:49 PM PDT 24
Finished Jul 23 05:47:54 PM PDT 24
Peak memory 199940 kb
Host smart-19883d5d-4c98-4e06-ac0c-48f525257450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032930807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2032930807
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1453568056
Short name T484
Test name
Test status
Simulation time 1749759900 ps
CPU time 6.62 seconds
Started Jul 23 05:47:46 PM PDT 24
Finished Jul 23 05:47:57 PM PDT 24
Peak memory 200680 kb
Host smart-6d4d7718-49e6-44b2-a108-78725895b3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453568056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1453568056
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2324752695
Short name T358
Test name
Test status
Simulation time 112575442 ps
CPU time 1 seconds
Started Jul 23 05:47:44 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 200124 kb
Host smart-8226018e-28c3-402f-a6bc-fac21c249c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324752695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2324752695
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.594523591
Short name T336
Test name
Test status
Simulation time 236413057 ps
CPU time 1.45 seconds
Started Jul 23 05:47:44 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 200348 kb
Host smart-25d7e980-9ced-4bf1-a5d7-1f4ddb5af94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594523591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.594523591
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1703983723
Short name T234
Test name
Test status
Simulation time 4769811702 ps
CPU time 17.06 seconds
Started Jul 23 05:47:55 PM PDT 24
Finished Jul 23 05:48:14 PM PDT 24
Peak memory 208656 kb
Host smart-1e03c44a-05cc-4018-9f07-1c1129fad343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703983723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1703983723
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.4021613336
Short name T415
Test name
Test status
Simulation time 527327326 ps
CPU time 2.65 seconds
Started Jul 23 05:47:43 PM PDT 24
Finished Jul 23 05:47:51 PM PDT 24
Peak memory 200152 kb
Host smart-d44f8b26-2bf1-4196-b2bf-52fc5c0cc0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021613336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.4021613336
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.627838365
Short name T407
Test name
Test status
Simulation time 140361991 ps
CPU time 1.1 seconds
Started Jul 23 05:47:45 PM PDT 24
Finished Jul 23 05:47:50 PM PDT 24
Peak memory 200032 kb
Host smart-dba5710c-ab1c-4feb-9d29-c66d47bba6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627838365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.627838365
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.91642518
Short name T130
Test name
Test status
Simulation time 74702870 ps
CPU time 0.8 seconds
Started Jul 23 05:47:56 PM PDT 24
Finished Jul 23 05:48:00 PM PDT 24
Peak memory 199916 kb
Host smart-665da696-c0b7-47d3-b6c3-00619972a828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91642518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.91642518
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.4023480743
Short name T181
Test name
Test status
Simulation time 2337920047 ps
CPU time 8.16 seconds
Started Jul 23 05:47:55 PM PDT 24
Finished Jul 23 05:48:04 PM PDT 24
Peak memory 217848 kb
Host smart-1edf43ac-081b-4530-a5f3-5a981c834a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023480743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4023480743
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1811667318
Short name T284
Test name
Test status
Simulation time 244065587 ps
CPU time 1.11 seconds
Started Jul 23 05:47:56 PM PDT 24
Finished Jul 23 05:48:01 PM PDT 24
Peak memory 217516 kb
Host smart-2faf08b4-98a5-4289-84cb-d05ada1e0ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811667318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1811667318
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3939790996
Short name T345
Test name
Test status
Simulation time 215290609 ps
CPU time 0.93 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:01 PM PDT 24
Peak memory 199908 kb
Host smart-fe6acb2c-2911-403b-90aa-b18c0d9faa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939790996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3939790996
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2521012751
Short name T46
Test name
Test status
Simulation time 999834214 ps
CPU time 4.79 seconds
Started Jul 23 05:47:58 PM PDT 24
Finished Jul 23 05:48:07 PM PDT 24
Peak memory 200264 kb
Host smart-efa07be0-0cfc-4009-a0ff-22b676ec47b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521012751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2521012751
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.171533894
Short name T249
Test name
Test status
Simulation time 146664874 ps
CPU time 1.22 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 200136 kb
Host smart-7aab7f9c-10e9-4430-aa89-7775d96bc2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171533894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.171533894
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.224879861
Short name T329
Test name
Test status
Simulation time 113148699 ps
CPU time 1.25 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 200312 kb
Host smart-beae7e0b-43c3-4a48-a605-8491012e4176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224879861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.224879861
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3188252512
Short name T10
Test name
Test status
Simulation time 2902087951 ps
CPU time 15.19 seconds
Started Jul 23 05:47:58 PM PDT 24
Finished Jul 23 05:48:17 PM PDT 24
Peak memory 208668 kb
Host smart-4a561c0e-88a0-4d4a-b3fe-ae39b6f873e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188252512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3188252512
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3496904413
Short name T282
Test name
Test status
Simulation time 144901750 ps
CPU time 1.88 seconds
Started Jul 23 05:47:58 PM PDT 24
Finished Jul 23 05:48:03 PM PDT 24
Peak memory 200164 kb
Host smart-900dd659-b96b-4f71-a04a-6ca8d6484d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496904413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3496904413
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3297290571
Short name T171
Test name
Test status
Simulation time 150648242 ps
CPU time 1.26 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 200380 kb
Host smart-69777e17-c612-4fbf-9b69-1b77c4489373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297290571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3297290571
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2709730279
Short name T451
Test name
Test status
Simulation time 71905075 ps
CPU time 0.8 seconds
Started Jul 23 05:47:58 PM PDT 24
Finished Jul 23 05:48:03 PM PDT 24
Peak memory 199936 kb
Host smart-372c722d-1aac-4015-81c7-7545d4579b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709730279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2709730279
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2909788379
Short name T536
Test name
Test status
Simulation time 1227588585 ps
CPU time 5.54 seconds
Started Jul 23 05:47:56 PM PDT 24
Finished Jul 23 05:48:05 PM PDT 24
Peak memory 221792 kb
Host smart-32f6aa06-5261-4a66-99be-542594b86581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909788379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2909788379
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2242194669
Short name T240
Test name
Test status
Simulation time 244625283 ps
CPU time 1.14 seconds
Started Jul 23 05:47:58 PM PDT 24
Finished Jul 23 05:48:03 PM PDT 24
Peak memory 217504 kb
Host smart-0ae7407e-8d3f-451a-8195-57e4c32ba9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242194669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2242194669
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2411763266
Short name T271
Test name
Test status
Simulation time 100624651 ps
CPU time 0.77 seconds
Started Jul 23 05:47:59 PM PDT 24
Finished Jul 23 05:48:03 PM PDT 24
Peak memory 199936 kb
Host smart-baabbfaa-a1fb-4af5-9b0b-51074ec3fa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411763266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2411763266
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2309436554
Short name T225
Test name
Test status
Simulation time 1074823334 ps
CPU time 4.97 seconds
Started Jul 23 05:47:56 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 200324 kb
Host smart-fafc51c2-fd95-436f-a6e1-9b8e915a7f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309436554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2309436554
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.529782437
Short name T473
Test name
Test status
Simulation time 150867412 ps
CPU time 1.09 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:03 PM PDT 24
Peak memory 200124 kb
Host smart-9b5c489a-10ad-43e9-9565-02cc739e002e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529782437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.529782437
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1247986398
Short name T360
Test name
Test status
Simulation time 238276294 ps
CPU time 1.42 seconds
Started Jul 23 05:47:55 PM PDT 24
Finished Jul 23 05:47:58 PM PDT 24
Peak memory 200340 kb
Host smart-baef1878-5702-4d39-9304-86ba9a880428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247986398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1247986398
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2772024849
Short name T242
Test name
Test status
Simulation time 9632157045 ps
CPU time 34.83 seconds
Started Jul 23 05:47:56 PM PDT 24
Finished Jul 23 05:48:35 PM PDT 24
Peak memory 200440 kb
Host smart-d9549b7d-a19c-4158-bf84-d2db58927722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772024849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2772024849
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.830428262
Short name T313
Test name
Test status
Simulation time 540127235 ps
CPU time 2.78 seconds
Started Jul 23 05:47:58 PM PDT 24
Finished Jul 23 05:48:05 PM PDT 24
Peak memory 200008 kb
Host smart-71375442-8dc3-4c3e-bc2c-68dd31e5cc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830428262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.830428262
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2038869468
Short name T404
Test name
Test status
Simulation time 64276256 ps
CPU time 0.78 seconds
Started Jul 23 05:47:57 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 200148 kb
Host smart-9cd36b7f-0708-4c6d-9a1f-47a93a26d261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038869468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2038869468
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4025112566
Short name T67
Test name
Test status
Simulation time 72484720 ps
CPU time 0.74 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:17 PM PDT 24
Peak memory 199784 kb
Host smart-fc02ee7c-2aaf-4090-972f-5297f9b1f58b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025112566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4025112566
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1789011064
Short name T374
Test name
Test status
Simulation time 1228076133 ps
CPU time 5.5 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:23 PM PDT 24
Peak memory 217756 kb
Host smart-54260205-8671-4307-b5af-f5e505b26676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789011064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1789011064
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2963196103
Short name T302
Test name
Test status
Simulation time 244239357 ps
CPU time 1.09 seconds
Started Jul 23 05:48:04 PM PDT 24
Finished Jul 23 05:48:09 PM PDT 24
Peak memory 217456 kb
Host smart-5627c4e5-eb0b-4548-8907-be9e627a99fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963196103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2963196103
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3183142621
Short name T463
Test name
Test status
Simulation time 156954211 ps
CPU time 0.84 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:12 PM PDT 24
Peak memory 199956 kb
Host smart-ba9d6fe8-3494-40b9-8a1c-9cbf0d5ef5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183142621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3183142621
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2265578260
Short name T72
Test name
Test status
Simulation time 1399248136 ps
CPU time 5.46 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:20 PM PDT 24
Peak memory 200376 kb
Host smart-7ab04838-7be9-442d-b09e-eb5c4aafde77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265578260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2265578260
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2529177335
Short name T136
Test name
Test status
Simulation time 105288193 ps
CPU time 0.98 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:12 PM PDT 24
Peak memory 200132 kb
Host smart-147f948f-b25f-424f-b7ed-8b611b53cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529177335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2529177335
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1628489475
Short name T477
Test name
Test status
Simulation time 257618779 ps
CPU time 1.68 seconds
Started Jul 23 05:47:55 PM PDT 24
Finished Jul 23 05:47:58 PM PDT 24
Peak memory 200264 kb
Host smart-1914d30d-598e-4081-b089-26664b85f205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628489475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1628489475
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3248381173
Short name T114
Test name
Test status
Simulation time 6139499373 ps
CPU time 22.97 seconds
Started Jul 23 05:48:12 PM PDT 24
Finished Jul 23 05:48:42 PM PDT 24
Peak memory 200416 kb
Host smart-49d7c32d-3237-4865-8355-8105ce089857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248381173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3248381173
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.732267430
Short name T350
Test name
Test status
Simulation time 260529497 ps
CPU time 1.78 seconds
Started Jul 23 05:48:05 PM PDT 24
Finished Jul 23 05:48:10 PM PDT 24
Peak memory 200136 kb
Host smart-7ab2cce7-19cc-49eb-ba42-12b3d005dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732267430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.732267430
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2417081056
Short name T206
Test name
Test status
Simulation time 68650143 ps
CPU time 0.79 seconds
Started Jul 23 05:48:05 PM PDT 24
Finished Jul 23 05:48:10 PM PDT 24
Peak memory 199944 kb
Host smart-4ecc5b5c-1d66-41e1-bf36-37ac25f28f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417081056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2417081056
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3140657554
Short name T27
Test name
Test status
Simulation time 2361973836 ps
CPU time 8.72 seconds
Started Jul 23 05:48:09 PM PDT 24
Finished Jul 23 05:48:29 PM PDT 24
Peak memory 221844 kb
Host smart-f399b6e9-6e15-4129-b424-55884a4d8d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140657554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3140657554
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.883908206
Short name T187
Test name
Test status
Simulation time 244359666 ps
CPU time 1.1 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:14 PM PDT 24
Peak memory 217492 kb
Host smart-9d251571-8b30-4176-b25f-490bab50b254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883908206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.883908206
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.607419049
Short name T18
Test name
Test status
Simulation time 103279684 ps
CPU time 0.82 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:14 PM PDT 24
Peak memory 199956 kb
Host smart-9a70d926-63e3-4799-896e-ccac4d93e878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607419049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.607419049
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.34000725
Short name T314
Test name
Test status
Simulation time 791362490 ps
CPU time 3.8 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:20 PM PDT 24
Peak memory 200424 kb
Host smart-e29e8e6b-e6e9-4934-b9d8-e33ae7e4c958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34000725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.34000725
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1143707267
Short name T226
Test name
Test status
Simulation time 100899618 ps
CPU time 0.95 seconds
Started Jul 23 05:48:05 PM PDT 24
Finished Jul 23 05:48:10 PM PDT 24
Peak memory 200096 kb
Host smart-3d45fdc3-e77c-4956-8c39-605c945813de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143707267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1143707267
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2680914408
Short name T68
Test name
Test status
Simulation time 118523225 ps
CPU time 1.19 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:48:14 PM PDT 24
Peak memory 200308 kb
Host smart-bfd2fcb7-cffb-4cbc-890e-128f5a78d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680914408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2680914408
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.16492810
Short name T76
Test name
Test status
Simulation time 12102965002 ps
CPU time 41.26 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:53 PM PDT 24
Peak memory 200444 kb
Host smart-03e2bd4a-3f63-4d3d-9c64-1a58f514217d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16492810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.16492810
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2754539683
Short name T353
Test name
Test status
Simulation time 396952354 ps
CPU time 2.05 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:13 PM PDT 24
Peak memory 200128 kb
Host smart-f4e1b070-0b34-44e9-83c5-b3c3245f249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754539683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2754539683
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2968331962
Short name T165
Test name
Test status
Simulation time 237328051 ps
CPU time 1.45 seconds
Started Jul 23 05:48:06 PM PDT 24
Finished Jul 23 05:48:12 PM PDT 24
Peak memory 200404 kb
Host smart-9d472d18-9ddc-4ce7-9d2d-7468c5207643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968331962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2968331962
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2443930300
Short name T448
Test name
Test status
Simulation time 66660274 ps
CPU time 0.78 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:20 PM PDT 24
Peak memory 199876 kb
Host smart-b017c364-2788-4415-b0ff-868ea796e487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443930300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2443930300
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3376964468
Short name T237
Test name
Test status
Simulation time 1900163686 ps
CPU time 7.14 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:28 PM PDT 24
Peak memory 221640 kb
Host smart-9b7629c6-bf42-4f0b-8639-288214169e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376964468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3376964468
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2704354520
Short name T276
Test name
Test status
Simulation time 244909450 ps
CPU time 1.06 seconds
Started Jul 23 05:48:09 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 217568 kb
Host smart-d4cdfaed-a2ac-4d43-a4ba-dc08d147e466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704354520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2704354520
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2684319355
Short name T503
Test name
Test status
Simulation time 197030698 ps
CPU time 0.93 seconds
Started Jul 23 05:48:07 PM PDT 24
Finished Jul 23 05:48:13 PM PDT 24
Peak memory 199944 kb
Host smart-5167fcee-37a2-42df-a40b-70d5663d212c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684319355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2684319355
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1031451733
Short name T507
Test name
Test status
Simulation time 1672243901 ps
CPU time 6.69 seconds
Started Jul 23 05:48:09 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 200264 kb
Host smart-bdbdf2a6-9c0b-49cd-8247-72821111b697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031451733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1031451733
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2303726055
Short name T56
Test name
Test status
Simulation time 193161386 ps
CPU time 1.31 seconds
Started Jul 23 05:48:09 PM PDT 24
Finished Jul 23 05:48:17 PM PDT 24
Peak memory 200340 kb
Host smart-216aab29-d1b7-417f-b5f9-cf84c6646681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303726055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2303726055
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3772453974
Short name T259
Test name
Test status
Simulation time 4397533204 ps
CPU time 20.43 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:34 PM PDT 24
Peak memory 208896 kb
Host smart-0ec63771-c0cf-4fbd-8273-1568622e7592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772453974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3772453974
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2872462978
Short name T117
Test name
Test status
Simulation time 386274582 ps
CPU time 2.07 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:17 PM PDT 24
Peak memory 200140 kb
Host smart-b1cbe36e-e26d-4d4e-8879-a03728c93a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872462978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2872462978
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3795596701
Short name T208
Test name
Test status
Simulation time 134824724 ps
CPU time 1.23 seconds
Started Jul 23 05:48:05 PM PDT 24
Finished Jul 23 05:48:12 PM PDT 24
Peak memory 200128 kb
Host smart-c96111bf-d733-42a2-92fd-82d0362ee439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795596701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3795596701
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1136775394
Short name T436
Test name
Test status
Simulation time 86365147 ps
CPU time 0.87 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:21 PM PDT 24
Peak memory 199880 kb
Host smart-b1d45725-0ea1-4f84-ac16-b5f78300c1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136775394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1136775394
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1082176229
Short name T35
Test name
Test status
Simulation time 1223502962 ps
CPU time 6.08 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:23 PM PDT 24
Peak memory 217844 kb
Host smart-e03791a1-a500-46c7-82d5-d70dc5b78b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082176229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1082176229
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2552616873
Short name T163
Test name
Test status
Simulation time 254034922 ps
CPU time 1.09 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:17 PM PDT 24
Peak memory 217492 kb
Host smart-073bbf57-4c78-4922-a481-c171246b9051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552616873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2552616873
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.15184925
Short name T207
Test name
Test status
Simulation time 92446528 ps
CPU time 0.74 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:15 PM PDT 24
Peak memory 199948 kb
Host smart-e222e0ed-11a6-47ca-986b-256ef6721eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15184925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.15184925
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.119682795
Short name T394
Test name
Test status
Simulation time 1460967059 ps
CPU time 5.24 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:20 PM PDT 24
Peak memory 200412 kb
Host smart-1f9bc9c5-0525-42a2-835f-1819b65c55d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119682795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.119682795
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2385281643
Short name T410
Test name
Test status
Simulation time 144023921 ps
CPU time 1.12 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 200108 kb
Host smart-ab44844d-9046-4104-ba87-7638d6dfda8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385281643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2385281643
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1250755569
Short name T210
Test name
Test status
Simulation time 259568605 ps
CPU time 1.56 seconds
Started Jul 23 05:48:08 PM PDT 24
Finished Jul 23 05:48:16 PM PDT 24
Peak memory 200348 kb
Host smart-ece4b2b0-2789-4d52-81d0-36f3d4c3a17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250755569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1250755569
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3390583241
Short name T512
Test name
Test status
Simulation time 733572769 ps
CPU time 3.06 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 200236 kb
Host smart-8d5d8e62-8e71-4d2e-9bf9-de61b7f1e121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390583241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3390583241
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3184767508
Short name T490
Test name
Test status
Simulation time 138230876 ps
CPU time 1.79 seconds
Started Jul 23 05:48:09 PM PDT 24
Finished Jul 23 05:48:18 PM PDT 24
Peak memory 200124 kb
Host smart-5f4177b3-92da-41e2-b748-7c1959a15281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184767508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3184767508
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1470744103
Short name T236
Test name
Test status
Simulation time 241778219 ps
CPU time 1.4 seconds
Started Jul 23 05:48:10 PM PDT 24
Finished Jul 23 05:48:18 PM PDT 24
Peak memory 200312 kb
Host smart-b1f78a97-a36d-4e0b-84df-43808df0f90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470744103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1470744103
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.286108130
Short name T417
Test name
Test status
Simulation time 73655923 ps
CPU time 0.8 seconds
Started Jul 23 05:48:19 PM PDT 24
Finished Jul 23 05:48:24 PM PDT 24
Peak memory 199920 kb
Host smart-8046d8a0-95cf-4a79-810a-d8c14fa74580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286108130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.286108130
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3108049884
Short name T518
Test name
Test status
Simulation time 1888095862 ps
CPU time 7.09 seconds
Started Jul 23 05:48:18 PM PDT 24
Finished Jul 23 05:48:29 PM PDT 24
Peak memory 217796 kb
Host smart-fb631ba4-82a3-4155-9d3f-6849b148fa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108049884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3108049884
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1504575533
Short name T48
Test name
Test status
Simulation time 244909736 ps
CPU time 1.07 seconds
Started Jul 23 05:48:15 PM PDT 24
Finished Jul 23 05:48:22 PM PDT 24
Peak memory 217508 kb
Host smart-d3d2b47c-4a6c-4dbb-9f3d-f7a7a03dba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504575533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1504575533
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3014136642
Short name T396
Test name
Test status
Simulation time 74689771 ps
CPU time 0.77 seconds
Started Jul 23 05:48:24 PM PDT 24
Finished Jul 23 05:48:27 PM PDT 24
Peak memory 199956 kb
Host smart-36e2ff16-3a6c-4155-bf71-85109f12a5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014136642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3014136642
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3878105594
Short name T317
Test name
Test status
Simulation time 1867122009 ps
CPU time 6.8 seconds
Started Jul 23 05:48:20 PM PDT 24
Finished Jul 23 05:48:30 PM PDT 24
Peak memory 200452 kb
Host smart-9cf00d09-9c99-42d6-97ee-468fb9a48794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878105594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3878105594
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2078444975
Short name T124
Test name
Test status
Simulation time 175023259 ps
CPU time 1.26 seconds
Started Jul 23 05:48:11 PM PDT 24
Finished Jul 23 05:48:19 PM PDT 24
Peak memory 200144 kb
Host smart-0c021b10-4b10-4227-b887-8d9b4192c2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078444975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2078444975
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3228391283
Short name T267
Test name
Test status
Simulation time 116064343 ps
CPU time 1.19 seconds
Started Jul 23 05:48:27 PM PDT 24
Finished Jul 23 05:48:32 PM PDT 24
Peak memory 200356 kb
Host smart-70611edf-f126-4e66-95b6-ed1c7c6a0517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228391283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3228391283
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2227688536
Short name T378
Test name
Test status
Simulation time 6518340631 ps
CPU time 27.61 seconds
Started Jul 23 05:48:27 PM PDT 24
Finished Jul 23 05:48:58 PM PDT 24
Peak memory 208708 kb
Host smart-5b77731b-921a-48e7-893e-628a3b5a15cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227688536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2227688536
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2424436036
Short name T352
Test name
Test status
Simulation time 378501118 ps
CPU time 2.29 seconds
Started Jul 23 05:48:24 PM PDT 24
Finished Jul 23 05:48:29 PM PDT 24
Peak memory 200148 kb
Host smart-8d32dbfa-bdef-48cc-8322-e551de592867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424436036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2424436036
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3421440586
Short name T118
Test name
Test status
Simulation time 265039419 ps
CPU time 1.54 seconds
Started Jul 23 05:48:13 PM PDT 24
Finished Jul 23 05:48:21 PM PDT 24
Peak memory 200084 kb
Host smart-c768c8ca-b1d1-4130-8502-6b67dd154520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421440586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3421440586
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1074862769
Short name T161
Test name
Test status
Simulation time 78066892 ps
CPU time 0.82 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:45:56 PM PDT 24
Peak memory 199920 kb
Host smart-d9df4e6d-5e16-41c7-9439-ba89703b9783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074862769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1074862769
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.219206685
Short name T476
Test name
Test status
Simulation time 1892457481 ps
CPU time 7.43 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:46:01 PM PDT 24
Peak memory 217696 kb
Host smart-1e28d8e5-bca8-48f0-b680-2e18c906b496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219206685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.219206685
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.492794174
Short name T198
Test name
Test status
Simulation time 244991603 ps
CPU time 1.08 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:45:55 PM PDT 24
Peak memory 217560 kb
Host smart-4e6f3868-50a8-41f6-a472-614cb13ace25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492794174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.492794174
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2977333495
Short name T144
Test name
Test status
Simulation time 169199940 ps
CPU time 0.9 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:45:56 PM PDT 24
Peak memory 199944 kb
Host smart-5511a60d-42ca-415e-a32b-5c5b41b27b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977333495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2977333495
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2600466362
Short name T298
Test name
Test status
Simulation time 1459583947 ps
CPU time 5.47 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:46:01 PM PDT 24
Peak memory 200420 kb
Host smart-a75298df-7c28-40c0-b470-c0b9b25bab4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600466362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2600466362
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1703275844
Short name T281
Test name
Test status
Simulation time 102445013 ps
CPU time 1.03 seconds
Started Jul 23 05:45:50 PM PDT 24
Finished Jul 23 05:45:52 PM PDT 24
Peak memory 200144 kb
Host smart-aea727b8-5234-4f50-b184-477467876002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703275844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1703275844
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3557294975
Short name T422
Test name
Test status
Simulation time 202240458 ps
CPU time 1.57 seconds
Started Jul 23 05:45:50 PM PDT 24
Finished Jul 23 05:45:53 PM PDT 24
Peak memory 200308 kb
Host smart-c508b54c-7603-4a48-b700-97cbe0a7fcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557294975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3557294975
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2671776485
Short name T89
Test name
Test status
Simulation time 7919673615 ps
CPU time 28.11 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:46:23 PM PDT 24
Peak memory 209408 kb
Host smart-36accef8-0a27-44d5-9885-87e15f5a82b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671776485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2671776485
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.852789280
Short name T212
Test name
Test status
Simulation time 433581878 ps
CPU time 2.49 seconds
Started Jul 23 05:45:54 PM PDT 24
Finished Jul 23 05:46:00 PM PDT 24
Peak memory 208348 kb
Host smart-2884c4fd-ecc7-476b-b1ab-78768e70ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852789280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.852789280
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1220820814
Short name T449
Test name
Test status
Simulation time 116833301 ps
CPU time 1.07 seconds
Started Jul 23 05:45:50 PM PDT 24
Finished Jul 23 05:45:53 PM PDT 24
Peak memory 200148 kb
Host smart-44ddad9f-22ef-4f1f-a539-585e2ce2092f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220820814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1220820814
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1200175719
Short name T248
Test name
Test status
Simulation time 82147597 ps
CPU time 0.81 seconds
Started Jul 23 05:45:50 PM PDT 24
Finished Jul 23 05:45:52 PM PDT 24
Peak memory 199940 kb
Host smart-07b8516b-b5a6-44e5-9a2c-1205a9a1f2bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200175719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1200175719
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1679341807
Short name T308
Test name
Test status
Simulation time 1900097050 ps
CPU time 6.9 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:46:03 PM PDT 24
Peak memory 221776 kb
Host smart-d25990d5-b199-47ee-bceb-0c6758992cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679341807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1679341807
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3413467007
Short name T367
Test name
Test status
Simulation time 245286683 ps
CPU time 1.09 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:45:56 PM PDT 24
Peak memory 217492 kb
Host smart-6d915654-aaa1-4c19-8d72-c58e6e15b7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413467007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3413467007
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2869896131
Short name T392
Test name
Test status
Simulation time 150499805 ps
CPU time 0.81 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 199940 kb
Host smart-fed8647c-d63d-442d-aa51-5a2431b6c1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869896131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2869896131
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1704061672
Short name T479
Test name
Test status
Simulation time 1528467026 ps
CPU time 5.83 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:46:00 PM PDT 24
Peak memory 200404 kb
Host smart-ae542bf2-b455-4232-bfbd-5d40284d5e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704061672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1704061672
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.633605058
Short name T269
Test name
Test status
Simulation time 143700223 ps
CPU time 1.14 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:45:55 PM PDT 24
Peak memory 200136 kb
Host smart-a14d4a49-213f-4960-9565-b5bbf8bb8317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633605058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.633605058
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.365479380
Short name T131
Test name
Test status
Simulation time 123951220 ps
CPU time 1.3 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:45:58 PM PDT 24
Peak memory 200336 kb
Host smart-0d695333-5b0c-49c8-a659-54274108e5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365479380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.365479380
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3833061874
Short name T196
Test name
Test status
Simulation time 19446304752 ps
CPU time 63.55 seconds
Started Jul 23 05:45:51 PM PDT 24
Finished Jul 23 05:46:56 PM PDT 24
Peak memory 200452 kb
Host smart-17306356-659c-4ce6-b002-1bddad90e19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833061874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3833061874
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2438609958
Short name T32
Test name
Test status
Simulation time 158578903 ps
CPU time 1.91 seconds
Started Jul 23 05:45:54 PM PDT 24
Finished Jul 23 05:46:00 PM PDT 24
Peak memory 199888 kb
Host smart-673c2da1-0955-4ee2-8e4b-a572946de5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438609958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2438609958
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1994146949
Short name T301
Test name
Test status
Simulation time 192325310 ps
CPU time 1.38 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:45:58 PM PDT 24
Peak memory 199992 kb
Host smart-19f85ee9-056f-483d-bd1c-cba3d0a24ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994146949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1994146949
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.753894356
Short name T129
Test name
Test status
Simulation time 59489899 ps
CPU time 0.72 seconds
Started Jul 23 05:45:56 PM PDT 24
Finished Jul 23 05:45:59 PM PDT 24
Peak memory 199884 kb
Host smart-52ba0fc8-55c7-4c28-a0ee-4c0f7176d7ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753894356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.753894356
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.339742992
Short name T73
Test name
Test status
Simulation time 244074162 ps
CPU time 1.12 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 217560 kb
Host smart-4d7997ad-9f82-46ef-867d-303551b020af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339742992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.339742992
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3506339006
Short name T322
Test name
Test status
Simulation time 128943839 ps
CPU time 0.83 seconds
Started Jul 23 05:45:54 PM PDT 24
Finished Jul 23 05:45:59 PM PDT 24
Peak memory 199700 kb
Host smart-02987efc-4a8d-458d-bc2b-d2efed19c1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506339006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3506339006
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.436432170
Short name T337
Test name
Test status
Simulation time 1930622850 ps
CPU time 7.08 seconds
Started Jul 23 05:45:54 PM PDT 24
Finished Jul 23 05:46:04 PM PDT 24
Peak memory 200412 kb
Host smart-19bff756-74fc-4b1f-9296-dba00ee1bde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436432170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.436432170
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3435205649
Short name T489
Test name
Test status
Simulation time 147913879 ps
CPU time 1.05 seconds
Started Jul 23 05:45:52 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 200140 kb
Host smart-8f67238f-8313-42b6-850f-9f6dcf4f6450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435205649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3435205649
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1020434442
Short name T184
Test name
Test status
Simulation time 237065520 ps
CPU time 1.55 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 200352 kb
Host smart-bc90faee-6d52-49c4-9f9e-6321fec08cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020434442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1020434442
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1423830023
Short name T139
Test name
Test status
Simulation time 9934610071 ps
CPU time 39.81 seconds
Started Jul 23 05:45:49 PM PDT 24
Finished Jul 23 05:46:30 PM PDT 24
Peak memory 200484 kb
Host smart-9e8dbd32-ee6d-41cd-9d43-1740245a3c26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423830023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1423830023
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.819642229
Short name T389
Test name
Test status
Simulation time 100649557 ps
CPU time 0.99 seconds
Started Jul 23 05:45:53 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 200140 kb
Host smart-b73703ee-03f3-4783-bd59-98848c86662e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819642229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.819642229
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2831147760
Short name T496
Test name
Test status
Simulation time 110707473 ps
CPU time 0.96 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:05 PM PDT 24
Peak memory 199884 kb
Host smart-b5dd1a63-556d-4606-98d7-42bf81c6fb9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831147760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2831147760
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.611698491
Short name T261
Test name
Test status
Simulation time 1920079183 ps
CPU time 6.86 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:08 PM PDT 24
Peak memory 221728 kb
Host smart-db522d43-f16e-4ab9-8190-c8a6726fa63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611698491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.611698491
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1976616715
Short name T366
Test name
Test status
Simulation time 244611895 ps
CPU time 1.13 seconds
Started Jul 23 05:45:59 PM PDT 24
Finished Jul 23 05:46:01 PM PDT 24
Peak memory 217512 kb
Host smart-d5516a0d-0c3d-4c84-8c67-8798ac951782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976616715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1976616715
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2173695096
Short name T297
Test name
Test status
Simulation time 82859803 ps
CPU time 0.79 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:04 PM PDT 24
Peak memory 199932 kb
Host smart-b3ae8270-2132-450f-b064-f6c051ef6e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173695096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2173695096
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2416050311
Short name T376
Test name
Test status
Simulation time 1221382535 ps
CPU time 4.84 seconds
Started Jul 23 05:45:57 PM PDT 24
Finished Jul 23 05:46:03 PM PDT 24
Peak memory 200324 kb
Host smart-ee71ff41-33f7-4258-a419-6de7d3605439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416050311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2416050311
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4165806842
Short name T459
Test name
Test status
Simulation time 146786375 ps
CPU time 1.13 seconds
Started Jul 23 05:46:03 PM PDT 24
Finished Jul 23 05:46:05 PM PDT 24
Peak memory 200140 kb
Host smart-2fd6ad6f-d0d2-41a8-85cf-ed1fd2aae248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165806842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4165806842
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2987040669
Short name T426
Test name
Test status
Simulation time 218873288 ps
CPU time 1.46 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:03 PM PDT 24
Peak memory 200264 kb
Host smart-62169a2a-d786-42fa-850a-d7426322f3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987040669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2987040669
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1189959742
Short name T470
Test name
Test status
Simulation time 1676011101 ps
CPU time 8.15 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:11 PM PDT 24
Peak memory 200444 kb
Host smart-a63c5ad0-3a59-492d-9b88-ab40b1ba0b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189959742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1189959742
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1877218640
Short name T156
Test name
Test status
Simulation time 506778091 ps
CPU time 2.67 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:04 PM PDT 24
Peak memory 200140 kb
Host smart-1a81e329-014d-4bbe-924d-883df729a561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877218640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1877218640
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2246281045
Short name T400
Test name
Test status
Simulation time 212156899 ps
CPU time 1.35 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:05 PM PDT 24
Peak memory 200144 kb
Host smart-1b5f09fc-c12f-44cc-bbbb-675c2df20511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246281045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2246281045
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3924983761
Short name T272
Test name
Test status
Simulation time 71582173 ps
CPU time 0.78 seconds
Started Jul 23 05:46:04 PM PDT 24
Finished Jul 23 05:46:05 PM PDT 24
Peak memory 199928 kb
Host smart-a4de8189-37da-4b0c-ad4d-266005209a0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924983761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3924983761
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1415549745
Short name T365
Test name
Test status
Simulation time 1225163890 ps
CPU time 5.56 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:09 PM PDT 24
Peak memory 217736 kb
Host smart-3d82858a-1caf-4563-89ef-06ce161d6530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415549745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1415549745
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.4182418663
Short name T135
Test name
Test status
Simulation time 244654105 ps
CPU time 1.09 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:05 PM PDT 24
Peak memory 217452 kb
Host smart-2e8287ca-59d5-466d-ad6f-5c1596b42deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182418663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.4182418663
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2232994717
Short name T218
Test name
Test status
Simulation time 190202449 ps
CPU time 0.87 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:12 PM PDT 24
Peak memory 199884 kb
Host smart-2c658425-f09f-48d4-bf17-79e454612ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232994717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2232994717
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.4229525446
Short name T330
Test name
Test status
Simulation time 1354825284 ps
CPU time 5.38 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:17 PM PDT 24
Peak memory 200340 kb
Host smart-5a048d25-dfac-4fe6-bc7b-a3443ede7065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229525446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.4229525446
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2813314651
Short name T523
Test name
Test status
Simulation time 173655536 ps
CPU time 1.28 seconds
Started Jul 23 05:46:01 PM PDT 24
Finished Jul 23 05:46:04 PM PDT 24
Peak memory 200084 kb
Host smart-97d5fee7-e457-4621-8584-0267139717a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813314651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2813314651
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.202954178
Short name T442
Test name
Test status
Simulation time 234658446 ps
CPU time 1.43 seconds
Started Jul 23 05:46:02 PM PDT 24
Finished Jul 23 05:46:05 PM PDT 24
Peak memory 200320 kb
Host smart-55344c7a-4616-4722-be90-fe6fe16b697b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202954178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.202954178
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2761825166
Short name T45
Test name
Test status
Simulation time 7322333587 ps
CPU time 30.71 seconds
Started Jul 23 05:46:09 PM PDT 24
Finished Jul 23 05:46:42 PM PDT 24
Peak memory 200448 kb
Host smart-5017523f-f3fe-4f9a-899d-8eccc13568d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761825166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2761825166
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3865252293
Short name T289
Test name
Test status
Simulation time 514453734 ps
CPU time 2.87 seconds
Started Jul 23 05:46:00 PM PDT 24
Finished Jul 23 05:46:05 PM PDT 24
Peak memory 200068 kb
Host smart-a0c6bdd9-2777-4c12-bbdb-7a915e211b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865252293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3865252293
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2021286455
Short name T303
Test name
Test status
Simulation time 131025188 ps
CPU time 1.01 seconds
Started Jul 23 05:46:01 PM PDT 24
Finished Jul 23 05:46:03 PM PDT 24
Peak memory 200116 kb
Host smart-7e7fc5f4-75e2-428e-9b91-80fa02fe3817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021286455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2021286455
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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