Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9285

1

T4

42

T7

35

T11

256

auto[1]

12061

1

T2

4

T3

4

T4

19

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6531	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	7135	1			T1	1		T2	2		T3	2
reset_info_cp[2]	3328	1			T2	1		T3	1		T4	4
reset_info_cp[4]	4370	1			T2	1		T3	1		T4	14
reset_info_cp[8]	115	1			T11	1		T22	3		T23	1
reset_info_cp[16]	127	1			T12	3		T22	3		T23	1
reset_info_cp[32]	118	1			T11	2		T22	3		T23	1
reset_info_cp[64]	125	1			T11	2		T12	2		T22	4
reset_info_cp[128]	117	1			T4	1		T10	1		T11	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3434	1			T4	11		T7	7		T11	90
reset_info_cp[1]	auto[1]	3081	1			T2	1		T3	1		T4	10
reset_info_cp[2]	auto[0]	1128	1			T4	3		T7	6		T11	36
reset_info_cp[2]	auto[1]	2200	1			T2	1		T3	1		T4	1
reset_info_cp[4]	auto[0]	1617	1			T4	9		T7	6		T11	50
reset_info_cp[4]	auto[1]	2753	1			T2	1		T3	1		T4	5
reset_info_cp[8]	auto[0]	37	1			T11	1		T22	1		T23	1
reset_info_cp[8]	auto[1]	78	1			T22	2		T25	1		T26	1
reset_info_cp[16]	auto[0]	52	1			T12	1		T22	2		T83	1
reset_info_cp[16]	auto[1]	75	1			T12	2		T22	1		T23	1
reset_info_cp[32]	auto[0]	38	1			T11	1		T22	1		T23	1
reset_info_cp[32]	auto[1]	80	1			T11	1		T22	2		T25	1
reset_info_cp[64]	auto[0]	54	1			T11	2		T12	1		T23	2
reset_info_cp[64]	auto[1]	71	1			T12	1		T22	4		T25	1
reset_info_cp[128]	auto[0]	51	1			T4	1		T11	1		T12	2
reset_info_cp[128]	auto[1]	66	1			T10	1		T11	1		T22	1