Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T534 /workspace/coverage/default/23.rstmgr_reset.103109529 Jul 24 07:07:07 PM PDT 24 Jul 24 07:07:13 PM PDT 24 1320749513 ps
T535 /workspace/coverage/default/38.rstmgr_por_stretcher.1772885128 Jul 24 07:07:34 PM PDT 24 Jul 24 07:07:35 PM PDT 24 90789645 ps
T536 /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2276674444 Jul 24 07:06:55 PM PDT 24 Jul 24 07:06:56 PM PDT 24 110239866 ps
T537 /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1754838026 Jul 24 07:06:39 PM PDT 24 Jul 24 07:06:40 PM PDT 24 105707757 ps
T538 /workspace/coverage/default/37.rstmgr_stress_all.1129647207 Jul 24 07:07:36 PM PDT 24 Jul 24 07:08:32 PM PDT 24 15585187440 ps
T56 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3604219934 Jul 24 05:22:56 PM PDT 24 Jul 24 05:22:58 PM PDT 24 503325831 ps
T57 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3839303137 Jul 24 05:23:20 PM PDT 24 Jul 24 05:23:23 PM PDT 24 876380456 ps
T59 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.858291525 Jul 24 05:23:06 PM PDT 24 Jul 24 05:23:08 PM PDT 24 88829719 ps
T58 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3143190507 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:09 PM PDT 24 488207155 ps
T60 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2363234448 Jul 24 05:22:59 PM PDT 24 Jul 24 05:23:00 PM PDT 24 86496597 ps
T92 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1594711905 Jul 24 05:22:48 PM PDT 24 Jul 24 05:22:50 PM PDT 24 130319297 ps
T67 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1784098996 Jul 24 05:22:55 PM PDT 24 Jul 24 05:22:58 PM PDT 24 929003043 ps
T74 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1151167408 Jul 24 05:23:06 PM PDT 24 Jul 24 05:23:09 PM PDT 24 892169727 ps
T539 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2601919494 Jul 24 05:22:57 PM PDT 24 Jul 24 05:22:58 PM PDT 24 89742553 ps
T93 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1042552734 Jul 24 05:22:55 PM PDT 24 Jul 24 05:22:56 PM PDT 24 71203316 ps
T61 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.163823839 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:06 PM PDT 24 176495749 ps
T75 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2256688853 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:08 PM PDT 24 208606444 ps
T76 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2671613151 Jul 24 05:22:55 PM PDT 24 Jul 24 05:22:57 PM PDT 24 184866796 ps
T77 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2171462332 Jul 24 05:23:07 PM PDT 24 Jul 24 05:23:09 PM PDT 24 505125519 ps
T78 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3439034037 Jul 24 05:23:05 PM PDT 24 Jul 24 05:23:08 PM PDT 24 905741873 ps
T540 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.469168474 Jul 24 05:23:24 PM PDT 24 Jul 24 05:23:25 PM PDT 24 66861437 ps
T79 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1702180671 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:05 PM PDT 24 344947775 ps
T80 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1413023379 Jul 24 05:23:06 PM PDT 24 Jul 24 05:23:08 PM PDT 24 216123136 ps
T81 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.560790711 Jul 24 05:22:56 PM PDT 24 Jul 24 05:22:59 PM PDT 24 439450915 ps
T94 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3869315682 Jul 24 05:23:06 PM PDT 24 Jul 24 05:23:07 PM PDT 24 68532405 ps
T541 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.214556145 Jul 24 05:22:52 PM PDT 24 Jul 24 05:22:53 PM PDT 24 98860338 ps
T82 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2148994995 Jul 24 05:22:55 PM PDT 24 Jul 24 05:22:57 PM PDT 24 127403896 ps
T542 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1744932241 Jul 24 05:23:12 PM PDT 24 Jul 24 05:23:13 PM PDT 24 63535022 ps
T543 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3110264585 Jul 24 05:23:01 PM PDT 24 Jul 24 05:23:08 PM PDT 24 464485461 ps
T102 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3264149892 Jul 24 05:22:58 PM PDT 24 Jul 24 05:23:00 PM PDT 24 326484571 ps
T103 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1138911908 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:53 PM PDT 24 143371099 ps
T95 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1015810707 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:02 PM PDT 24 68824212 ps
T96 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1452793220 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:04 PM PDT 24 55688671 ps
T544 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1757747128 Jul 24 05:22:56 PM PDT 24 Jul 24 05:22:58 PM PDT 24 201199082 ps
T97 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3497546508 Jul 24 05:23:08 PM PDT 24 Jul 24 05:23:09 PM PDT 24 83623861 ps
T545 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3308978703 Jul 24 05:22:58 PM PDT 24 Jul 24 05:23:01 PM PDT 24 270831927 ps
T104 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1781042430 Jul 24 05:23:17 PM PDT 24 Jul 24 05:23:21 PM PDT 24 1361755535 ps
T98 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3036344660 Jul 24 05:23:17 PM PDT 24 Jul 24 05:23:19 PM PDT 24 126372926 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.904157540 Jul 24 05:23:05 PM PDT 24 Jul 24 05:23:11 PM PDT 24 492775613 ps
T547 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4024979133 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:09 PM PDT 24 802366310 ps
T548 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3321898370 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:04 PM PDT 24 73322521 ps
T99 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2348693969 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:02 PM PDT 24 206984379 ps
T549 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1521928215 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:04 PM PDT 24 136569574 ps
T550 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2687562307 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:05 PM PDT 24 453782939 ps
T100 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1704587767 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:03 PM PDT 24 122320237 ps
T551 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3075160394 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:04 PM PDT 24 392661901 ps
T106 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2878761406 Jul 24 05:23:05 PM PDT 24 Jul 24 05:23:08 PM PDT 24 890125684 ps
T101 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.795514988 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:05 PM PDT 24 194653042 ps
T552 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2684253440 Jul 24 05:22:50 PM PDT 24 Jul 24 05:22:51 PM PDT 24 82521745 ps
T553 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4003750092 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:03 PM PDT 24 115152360 ps
T554 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1503477752 Jul 24 05:22:52 PM PDT 24 Jul 24 05:22:55 PM PDT 24 409282791 ps
T555 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.351580021 Jul 24 05:22:53 PM PDT 24 Jul 24 05:22:54 PM PDT 24 107080731 ps
T556 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2097273351 Jul 24 05:22:55 PM PDT 24 Jul 24 05:22:59 PM PDT 24 793212475 ps
T557 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1654651433 Jul 24 05:22:58 PM PDT 24 Jul 24 05:23:00 PM PDT 24 173153360 ps
T558 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3771997342 Jul 24 05:22:57 PM PDT 24 Jul 24 05:22:58 PM PDT 24 68498861 ps
T559 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3632048542 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:06 PM PDT 24 179898576 ps
T560 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2856380208 Jul 24 05:23:06 PM PDT 24 Jul 24 05:23:08 PM PDT 24 205736039 ps
T561 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2856879552 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:06 PM PDT 24 142784662 ps
T562 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1851454414 Jul 24 05:23:01 PM PDT 24 Jul 24 05:23:02 PM PDT 24 67231788 ps
T563 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3361382402 Jul 24 05:23:07 PM PDT 24 Jul 24 05:23:08 PM PDT 24 64038353 ps
T564 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3134757464 Jul 24 05:23:15 PM PDT 24 Jul 24 05:23:17 PM PDT 24 130280882 ps
T565 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.261100322 Jul 24 05:22:59 PM PDT 24 Jul 24 05:23:00 PM PDT 24 60915111 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1338744877 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:04 PM PDT 24 153531334 ps
T567 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2906340321 Jul 24 05:23:06 PM PDT 24 Jul 24 05:23:09 PM PDT 24 162369203 ps
T568 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4282931330 Jul 24 05:22:53 PM PDT 24 Jul 24 05:22:54 PM PDT 24 72699882 ps
T569 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2060028189 Jul 24 05:22:58 PM PDT 24 Jul 24 05:23:00 PM PDT 24 174537712 ps
T570 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2690338424 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:02 PM PDT 24 67982957 ps
T571 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.901964539 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:06 PM PDT 24 885410239 ps
T572 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.719786279 Jul 24 05:22:56 PM PDT 24 Jul 24 05:22:58 PM PDT 24 160399193 ps
T573 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2845324481 Jul 24 05:23:05 PM PDT 24 Jul 24 05:23:07 PM PDT 24 175791019 ps
T574 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1163520256 Jul 24 05:23:11 PM PDT 24 Jul 24 05:23:12 PM PDT 24 120457547 ps
T575 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2890415939 Jul 24 05:23:05 PM PDT 24 Jul 24 05:23:08 PM PDT 24 419244828 ps
T576 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1971105158 Jul 24 05:22:50 PM PDT 24 Jul 24 05:22:51 PM PDT 24 124787329 ps
T577 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2163570212 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:52 PM PDT 24 80442321 ps
T107 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1211044948 Jul 24 05:22:52 PM PDT 24 Jul 24 05:22:56 PM PDT 24 899333245 ps
T578 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2553717223 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:04 PM PDT 24 107456271 ps
T579 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2191614463 Jul 24 05:22:50 PM PDT 24 Jul 24 05:22:51 PM PDT 24 117448651 ps
T580 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.376684310 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:07 PM PDT 24 623583949 ps
T581 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.570441176 Jul 24 05:23:01 PM PDT 24 Jul 24 05:23:02 PM PDT 24 59273693 ps
T582 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2838114305 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:04 PM PDT 24 106069842 ps
T108 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3601950286 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:03 PM PDT 24 504154204 ps
T583 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.875612653 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:01 PM PDT 24 102409311 ps
T584 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.790387326 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:02 PM PDT 24 82360745 ps
T585 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4149528317 Jul 24 05:22:57 PM PDT 24 Jul 24 05:22:58 PM PDT 24 87372691 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.619491717 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:05 PM PDT 24 501316478 ps
T587 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.695389445 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:03 PM PDT 24 94605456 ps
T588 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3443903426 Jul 24 05:22:59 PM PDT 24 Jul 24 05:23:02 PM PDT 24 191782307 ps
T589 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1256665444 Jul 24 05:23:13 PM PDT 24 Jul 24 05:23:14 PM PDT 24 73497261 ps
T590 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2034629748 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:53 PM PDT 24 215077839 ps
T591 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3891570138 Jul 24 05:22:52 PM PDT 24 Jul 24 05:22:54 PM PDT 24 264412060 ps
T592 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.28056328 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:54 PM PDT 24 199990431 ps
T593 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3094915120 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:05 PM PDT 24 179606415 ps
T105 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1629343446 Jul 24 05:22:50 PM PDT 24 Jul 24 05:22:53 PM PDT 24 774489276 ps
T594 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2747670233 Jul 24 05:22:57 PM PDT 24 Jul 24 05:22:59 PM PDT 24 476869026 ps
T595 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1533626435 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:06 PM PDT 24 135241217 ps
T596 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.659337606 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:06 PM PDT 24 174075717 ps
T597 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3113519519 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:01 PM PDT 24 226444492 ps
T598 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.453228323 Jul 24 05:23:06 PM PDT 24 Jul 24 05:23:08 PM PDT 24 361410129 ps
T599 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3207259174 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:05 PM PDT 24 430710281 ps
T600 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2845846752 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:05 PM PDT 24 279231826 ps
T601 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2701761986 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:02 PM PDT 24 202282165 ps
T602 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1084089754 Jul 24 05:23:05 PM PDT 24 Jul 24 05:23:06 PM PDT 24 63025710 ps
T603 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1186686644 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:05 PM PDT 24 161698920 ps
T604 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1296423540 Jul 24 05:23:32 PM PDT 24 Jul 24 05:23:39 PM PDT 24 162356137 ps
T605 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3018979801 Jul 24 05:23:16 PM PDT 24 Jul 24 05:23:19 PM PDT 24 888411635 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3319385105 Jul 24 05:23:10 PM PDT 24 Jul 24 05:23:12 PM PDT 24 134528024 ps
T607 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.739356973 Jul 24 05:23:09 PM PDT 24 Jul 24 05:23:12 PM PDT 24 792332353 ps
T608 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3212551972 Jul 24 05:23:01 PM PDT 24 Jul 24 05:23:02 PM PDT 24 114188465 ps
T609 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2076239598 Jul 24 05:22:49 PM PDT 24 Jul 24 05:22:50 PM PDT 24 104405923 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3858671151 Jul 24 05:22:50 PM PDT 24 Jul 24 05:22:54 PM PDT 24 903154286 ps
T611 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3583222244 Jul 24 05:23:13 PM PDT 24 Jul 24 05:23:14 PM PDT 24 181446339 ps
T612 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1334307295 Jul 24 05:23:08 PM PDT 24 Jul 24 05:23:09 PM PDT 24 159939948 ps
T613 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2144788814 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:06 PM PDT 24 114866643 ps
T614 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3587452404 Jul 24 05:22:58 PM PDT 24 Jul 24 05:22:59 PM PDT 24 232448070 ps
T615 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1107765781 Jul 24 05:23:07 PM PDT 24 Jul 24 05:23:08 PM PDT 24 71863186 ps
T616 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3190997449 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:09 PM PDT 24 582788241 ps
T617 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2038161802 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:05 PM PDT 24 121107886 ps
T618 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1455976842 Jul 24 05:22:54 PM PDT 24 Jul 24 05:22:56 PM PDT 24 192150112 ps
T619 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2659713723 Jul 24 05:23:06 PM PDT 24 Jul 24 05:23:08 PM PDT 24 93328658 ps
T620 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2565432739 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:04 PM PDT 24 257112474 ps

Test location /workspace/coverage/default/38.rstmgr_stress_all.39541101
Short name T7
Test name
Test status
Simulation time 1305708558 ps
CPU time 6.45 seconds
Started Jul 24 07:07:38 PM PDT 24
Finished Jul 24 07:07:45 PM PDT 24
Peak memory 200380 kb
Host smart-9ce23df0-5b39-4879-a489-9920d33975a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39541101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.39541101
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.936729464
Short name T55
Test name
Test status
Simulation time 305482565 ps
CPU time 2 seconds
Started Jul 24 07:06:54 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 208352 kb
Host smart-4b6ea2f0-4bb1-46b6-adee-e778a57a0bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936729464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.936729464
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1151167408
Short name T74
Test name
Test status
Simulation time 892169727 ps
CPU time 2.83 seconds
Started Jul 24 05:23:06 PM PDT 24
Finished Jul 24 05:23:09 PM PDT 24
Peak memory 200072 kb
Host smart-6b2fb0db-79fe-44cc-8380-7c7f079d3ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151167408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1151167408
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2498590960
Short name T47
Test name
Test status
Simulation time 8588229894 ps
CPU time 14.74 seconds
Started Jul 24 07:06:41 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 217076 kb
Host smart-b29608d9-e434-4c73-9d6a-531b4d44a09a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498590960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2498590960
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1162791725
Short name T25
Test name
Test status
Simulation time 1220588788 ps
CPU time 5.29 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:07:01 PM PDT 24
Peak memory 216828 kb
Host smart-c9e5c862-1c65-4580-8ce6-3bab026b7f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162791725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1162791725
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.4029255498
Short name T88
Test name
Test status
Simulation time 13372267353 ps
CPU time 43.44 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:50 PM PDT 24
Peak memory 200440 kb
Host smart-bdb5ad38-9981-46c5-9ac7-e86695c208c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029255498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.4029255498
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1702180671
Short name T79
Test name
Test status
Simulation time 344947775 ps
CPU time 2.68 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 216324 kb
Host smart-aaa2147c-d610-4cde-a6b8-e98bd3e3b327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702180671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1702180671
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.201022026
Short name T12
Test name
Test status
Simulation time 3910183811 ps
CPU time 16.4 seconds
Started Jul 24 07:07:47 PM PDT 24
Finished Jul 24 07:08:03 PM PDT 24
Peak memory 208696 kb
Host smart-07be2499-8a1b-4e7d-ae5d-983b74f57025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201022026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.201022026
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3960027295
Short name T24
Test name
Test status
Simulation time 73490596 ps
CPU time 0.83 seconds
Started Jul 24 07:07:14 PM PDT 24
Finished Jul 24 07:07:15 PM PDT 24
Peak memory 199908 kb
Host smart-e0aacae0-8679-43b4-a429-fa1b47e6f102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960027295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3960027295
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1802732387
Short name T124
Test name
Test status
Simulation time 186734647 ps
CPU time 1.19 seconds
Started Jul 24 07:06:30 PM PDT 24
Finished Jul 24 07:06:32 PM PDT 24
Peak memory 200148 kb
Host smart-f754cd11-59bf-4892-9579-e4c2a78a1872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802732387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1802732387
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.996424134
Short name T50
Test name
Test status
Simulation time 1223836021 ps
CPU time 6.24 seconds
Started Jul 24 07:06:27 PM PDT 24
Finished Jul 24 07:06:34 PM PDT 24
Peak memory 221756 kb
Host smart-2e94bcdd-1ee8-4dec-b79d-40003c81a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996424134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.996424134
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2906340321
Short name T567
Test name
Test status
Simulation time 162369203 ps
CPU time 2.25 seconds
Started Jul 24 05:23:06 PM PDT 24
Finished Jul 24 05:23:09 PM PDT 24
Peak memory 208168 kb
Host smart-b05f8711-83cf-4e24-a36b-c57fb22b2781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906340321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2906340321
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1629343446
Short name T105
Test name
Test status
Simulation time 774489276 ps
CPU time 2.72 seconds
Started Jul 24 05:22:50 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 199984 kb
Host smart-99980226-21c1-48ff-950b-9857c43d5e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629343446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1629343446
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2015890717
Short name T71
Test name
Test status
Simulation time 109448301 ps
CPU time 1 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:54 PM PDT 24
Peak memory 200140 kb
Host smart-e60f79a4-e027-4389-8c81-9b9dd7d0384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015890717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2015890717
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1042552734
Short name T93
Test name
Test status
Simulation time 71203316 ps
CPU time 0.83 seconds
Started Jul 24 05:22:55 PM PDT 24
Finished Jul 24 05:22:56 PM PDT 24
Peak memory 199856 kb
Host smart-f4f633c5-79d5-4c23-b900-13f06d284d03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042552734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1042552734
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.4145042851
Short name T14
Test name
Test status
Simulation time 191831833 ps
CPU time 0.89 seconds
Started Jul 24 07:06:26 PM PDT 24
Finished Jul 24 07:06:27 PM PDT 24
Peak memory 200028 kb
Host smart-ce7a37c4-e798-427f-a69d-87baee35a872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145042851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.4145042851
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2502126488
Short name T118
Test name
Test status
Simulation time 244361461 ps
CPU time 1.07 seconds
Started Jul 24 07:06:52 PM PDT 24
Finished Jul 24 07:06:54 PM PDT 24
Peak memory 217480 kb
Host smart-1bd39f27-640a-405e-998a-7962bd7f09f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502126488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2502126488
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2059851301
Short name T342
Test name
Test status
Simulation time 1895718450 ps
CPU time 7.13 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:07:01 PM PDT 24
Peak memory 217740 kb
Host smart-b4ec2d1f-18bd-4d0e-9765-3209698aec31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059851301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2059851301
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1211044948
Short name T107
Test name
Test status
Simulation time 899333245 ps
CPU time 3.24 seconds
Started Jul 24 05:22:52 PM PDT 24
Finished Jul 24 05:22:56 PM PDT 24
Peak memory 200068 kb
Host smart-79178ca4-aa5f-41dd-a76a-865be93b5c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211044948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1211044948
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3601950286
Short name T108
Test name
Test status
Simulation time 504154204 ps
CPU time 1.93 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:03 PM PDT 24
Peak memory 200016 kb
Host smart-79e7fe32-a4d9-4b0f-a467-8bdc8e56d391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601950286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3601950286
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1503477752
Short name T554
Test name
Test status
Simulation time 409282791 ps
CPU time 2.53 seconds
Started Jul 24 05:22:52 PM PDT 24
Finished Jul 24 05:22:55 PM PDT 24
Peak memory 199976 kb
Host smart-152a0fc6-4baf-4a52-ba8e-3e709bd811b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503477752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
503477752
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3143190507
Short name T58
Test name
Test status
Simulation time 488207155 ps
CPU time 5.57 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:09 PM PDT 24
Peak memory 199972 kb
Host smart-2e189783-6138-4c08-89bf-5b71a031b0f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143190507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
143190507
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.214556145
Short name T541
Test name
Test status
Simulation time 98860338 ps
CPU time 0.8 seconds
Started Jul 24 05:22:52 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 199852 kb
Host smart-fed9fe0a-4dfe-4464-9682-d558018bc549
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214556145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.214556145
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3212551972
Short name T608
Test name
Test status
Simulation time 114188465 ps
CPU time 1.16 seconds
Started Jul 24 05:23:01 PM PDT 24
Finished Jul 24 05:23:02 PM PDT 24
Peak memory 208116 kb
Host smart-f2dbbf76-b6ec-4fee-8bfc-0597ac5feb67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212551972 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3212551972
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3321898370
Short name T548
Test name
Test status
Simulation time 73322521 ps
CPU time 0.81 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:04 PM PDT 24
Peak memory 199724 kb
Host smart-22c426c1-d673-4fd6-9d7b-bad103ed0622
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321898370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3321898370
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1971105158
Short name T576
Test name
Test status
Simulation time 124787329 ps
CPU time 1.1 seconds
Started Jul 24 05:22:50 PM PDT 24
Finished Jul 24 05:22:51 PM PDT 24
Peak memory 199828 kb
Host smart-5ef3f9d8-dd4a-47ce-9f83-d038121f4d8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971105158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1971105158
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2038161802
Short name T617
Test name
Test status
Simulation time 121107886 ps
CPU time 1.65 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 208108 kb
Host smart-bbeec306-9baa-4577-a72b-1149d5211ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038161802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2038161802
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.619491717
Short name T586
Test name
Test status
Simulation time 501316478 ps
CPU time 1.92 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 200028 kb
Host smart-687211f0-ae86-40a7-a477-f5b8b5c41a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619491717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
619491717
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3891570138
Short name T591
Test name
Test status
Simulation time 264412060 ps
CPU time 1.85 seconds
Started Jul 24 05:22:52 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 200016 kb
Host smart-fa25df33-d562-4d10-a8a2-448f3bfdd0a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891570138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
891570138
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.904157540
Short name T546
Test name
Test status
Simulation time 492775613 ps
CPU time 5.6 seconds
Started Jul 24 05:23:05 PM PDT 24
Finished Jul 24 05:23:11 PM PDT 24
Peak memory 199940 kb
Host smart-333b7551-cbfd-4e9a-ab32-aaa3154fb3c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904157540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.904157540
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.695389445
Short name T587
Test name
Test status
Simulation time 94605456 ps
CPU time 0.86 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:03 PM PDT 24
Peak memory 199812 kb
Host smart-96915906-b073-4fce-8107-2c635fde4090
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695389445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.695389445
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2076239598
Short name T609
Test name
Test status
Simulation time 104405923 ps
CPU time 0.91 seconds
Started Jul 24 05:22:49 PM PDT 24
Finished Jul 24 05:22:50 PM PDT 24
Peak memory 199980 kb
Host smart-0861f549-0307-4c9c-9e09-8714072e3857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076239598 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2076239598
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2163570212
Short name T577
Test name
Test status
Simulation time 80442321 ps
CPU time 0.9 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:52 PM PDT 24
Peak memory 199912 kb
Host smart-1526c48d-56c2-43a6-aea5-f12ded0d5b0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163570212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2163570212
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1138911908
Short name T103
Test name
Test status
Simulation time 143371099 ps
CPU time 1.99 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 200044 kb
Host smart-82c06957-4ff6-42e0-8508-8b9225f0751f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138911908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1138911908
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2060028189
Short name T569
Test name
Test status
Simulation time 174537712 ps
CPU time 1.65 seconds
Started Jul 24 05:22:58 PM PDT 24
Finished Jul 24 05:23:00 PM PDT 24
Peak memory 208324 kb
Host smart-41ce540d-29b3-43e0-8e32-dfb9024c5b62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060028189 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2060028189
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2601919494
Short name T539
Test name
Test status
Simulation time 89742553 ps
CPU time 0.87 seconds
Started Jul 24 05:22:57 PM PDT 24
Finished Jul 24 05:22:58 PM PDT 24
Peak memory 199808 kb
Host smart-081e3148-da9d-44ab-8db9-447217e976fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601919494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2601919494
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2856380208
Short name T560
Test name
Test status
Simulation time 205736039 ps
CPU time 1.53 seconds
Started Jul 24 05:23:06 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 200016 kb
Host smart-1fb2cf7c-18ce-4998-a77f-6bcfdfb8ad4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856380208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2856380208
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1654651433
Short name T557
Test name
Test status
Simulation time 173153360 ps
CPU time 2.54 seconds
Started Jul 24 05:22:58 PM PDT 24
Finished Jul 24 05:23:00 PM PDT 24
Peak memory 208268 kb
Host smart-814638b4-2601-41a5-92d9-660864f98144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654651433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1654651433
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.901964539
Short name T571
Test name
Test status
Simulation time 885410239 ps
CPU time 3 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:06 PM PDT 24
Peak memory 200108 kb
Host smart-bdd9ed5d-7e03-4007-85aa-f386e080eaa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901964539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.901964539
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2148994995
Short name T82
Test name
Test status
Simulation time 127403896 ps
CPU time 0.96 seconds
Started Jul 24 05:22:55 PM PDT 24
Finished Jul 24 05:22:57 PM PDT 24
Peak memory 199956 kb
Host smart-49ea75df-427c-4954-a279-72846f34d4e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148994995 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2148994995
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1084089754
Short name T602
Test name
Test status
Simulation time 63025710 ps
CPU time 0.75 seconds
Started Jul 24 05:23:05 PM PDT 24
Finished Jul 24 05:23:06 PM PDT 24
Peak memory 199860 kb
Host smart-fe5c3ebd-4741-4531-8fed-400e52fc6fc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084089754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1084089754
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2348693969
Short name T99
Test name
Test status
Simulation time 206984379 ps
CPU time 1.47 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:02 PM PDT 24
Peak memory 199996 kb
Host smart-7795f814-0481-4e03-a2c7-511289d597a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348693969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2348693969
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2565432739
Short name T620
Test name
Test status
Simulation time 257112474 ps
CPU time 1.92 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:04 PM PDT 24
Peak memory 208220 kb
Host smart-ec25cc33-e3e6-4eb0-8685-b99009af0765
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565432739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2565432739
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3604219934
Short name T56
Test name
Test status
Simulation time 503325831 ps
CPU time 2.11 seconds
Started Jul 24 05:22:56 PM PDT 24
Finished Jul 24 05:22:58 PM PDT 24
Peak memory 200116 kb
Host smart-e76b0c5a-5988-4b99-b043-e81efdfd4572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604219934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3604219934
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2845324481
Short name T573
Test name
Test status
Simulation time 175791019 ps
CPU time 1.6 seconds
Started Jul 24 05:23:05 PM PDT 24
Finished Jul 24 05:23:07 PM PDT 24
Peak memory 208380 kb
Host smart-d6118ee4-35dd-466a-8426-1113e2795c95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845324481 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2845324481
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3771997342
Short name T558
Test name
Test status
Simulation time 68498861 ps
CPU time 0.76 seconds
Started Jul 24 05:22:57 PM PDT 24
Finished Jul 24 05:22:58 PM PDT 24
Peak memory 199792 kb
Host smart-2ea0d860-3e79-40d7-a7c6-adde7b5c9e57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771997342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3771997342
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.795514988
Short name T101
Test name
Test status
Simulation time 194653042 ps
CPU time 1.46 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 199992 kb
Host smart-4093c0f5-dfbb-40c3-b220-5520d5fc1b46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795514988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.795514988
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3075160394
Short name T551
Test name
Test status
Simulation time 392661901 ps
CPU time 2.87 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:04 PM PDT 24
Peak memory 212096 kb
Host smart-da0273ae-8830-4854-a6d1-14c18e9a3d50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075160394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3075160394
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2890415939
Short name T575
Test name
Test status
Simulation time 419244828 ps
CPU time 1.85 seconds
Started Jul 24 05:23:05 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 200100 kb
Host smart-d4e49489-e432-4b0d-b88f-bbd171850ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890415939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2890415939
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1533626435
Short name T595
Test name
Test status
Simulation time 135241217 ps
CPU time 1.46 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:06 PM PDT 24
Peak memory 208236 kb
Host smart-48683cee-9a06-4587-bb9b-ff5c85d24012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533626435 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1533626435
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3869315682
Short name T94
Test name
Test status
Simulation time 68532405 ps
CPU time 0.9 seconds
Started Jul 24 05:23:06 PM PDT 24
Finished Jul 24 05:23:07 PM PDT 24
Peak memory 199824 kb
Host smart-d54e3647-a869-4872-af1f-c294a6224828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869315682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3869315682
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2553717223
Short name T578
Test name
Test status
Simulation time 107456271 ps
CPU time 1.24 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:04 PM PDT 24
Peak memory 200024 kb
Host smart-bcf64db7-8bb8-44d5-919c-3f3a1ddc41e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553717223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2553717223
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.376684310
Short name T580
Test name
Test status
Simulation time 623583949 ps
CPU time 3.95 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:07 PM PDT 24
Peak memory 212152 kb
Host smart-e8a3f7ce-585f-41b4-9cea-5de837e03e89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376684310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.376684310
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3018979801
Short name T605
Test name
Test status
Simulation time 888411635 ps
CPU time 2.96 seconds
Started Jul 24 05:23:16 PM PDT 24
Finished Jul 24 05:23:19 PM PDT 24
Peak memory 200028 kb
Host smart-0b652da6-8402-4462-8ce2-5602aa48d248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018979801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3018979801
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.659337606
Short name T596
Test name
Test status
Simulation time 174075717 ps
CPU time 1.64 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:06 PM PDT 24
Peak memory 208236 kb
Host smart-e4a805d9-be31-4c79-8b47-ba04494b3600
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659337606 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.659337606
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1744932241
Short name T542
Test name
Test status
Simulation time 63535022 ps
CPU time 0.76 seconds
Started Jul 24 05:23:12 PM PDT 24
Finished Jul 24 05:23:13 PM PDT 24
Peak memory 199672 kb
Host smart-27550969-e1a1-45d6-b3cd-8731370900d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744932241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1744932241
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1256665444
Short name T589
Test name
Test status
Simulation time 73497261 ps
CPU time 0.95 seconds
Started Jul 24 05:23:13 PM PDT 24
Finished Jul 24 05:23:14 PM PDT 24
Peak memory 199924 kb
Host smart-a4d3c3e7-cfc9-4d24-936e-b108b9d64699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256665444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1256665444
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3094915120
Short name T593
Test name
Test status
Simulation time 179606415 ps
CPU time 2.54 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 208224 kb
Host smart-c8dc743a-5367-4c77-b431-ef964a79e249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094915120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3094915120
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1781042430
Short name T104
Test name
Test status
Simulation time 1361755535 ps
CPU time 3.59 seconds
Started Jul 24 05:23:17 PM PDT 24
Finished Jul 24 05:23:21 PM PDT 24
Peak memory 200184 kb
Host smart-8017e230-286b-4015-bf49-759755c4e744
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781042430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1781042430
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3583222244
Short name T611
Test name
Test status
Simulation time 181446339 ps
CPU time 1.26 seconds
Started Jul 24 05:23:13 PM PDT 24
Finished Jul 24 05:23:14 PM PDT 24
Peak memory 208260 kb
Host smart-945b3e43-54da-4d40-ba69-3f15f384f9a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583222244 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3583222244
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3361382402
Short name T563
Test name
Test status
Simulation time 64038353 ps
CPU time 0.78 seconds
Started Jul 24 05:23:07 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 199860 kb
Host smart-57b6f529-00c5-44f0-9f90-6099048eb571
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361382402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3361382402
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2845846752
Short name T600
Test name
Test status
Simulation time 279231826 ps
CPU time 1.66 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 200000 kb
Host smart-9a1f272d-0674-495e-9316-0c2eee9c2984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845846752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2845846752
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3839303137
Short name T57
Test name
Test status
Simulation time 876380456 ps
CPU time 2.95 seconds
Started Jul 24 05:23:20 PM PDT 24
Finished Jul 24 05:23:23 PM PDT 24
Peak memory 199944 kb
Host smart-3e4a28ca-af46-41ac-8ba6-a487328c5dd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839303137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3839303137
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3319385105
Short name T606
Test name
Test status
Simulation time 134528024 ps
CPU time 1.06 seconds
Started Jul 24 05:23:10 PM PDT 24
Finished Jul 24 05:23:12 PM PDT 24
Peak memory 200256 kb
Host smart-b3bba7c3-1bd2-4388-9093-3df9e3c1226f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319385105 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3319385105
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1851454414
Short name T562
Test name
Test status
Simulation time 67231788 ps
CPU time 0.72 seconds
Started Jul 24 05:23:01 PM PDT 24
Finished Jul 24 05:23:02 PM PDT 24
Peak memory 199804 kb
Host smart-3809ec63-4c46-40df-b2cb-a3c2bc6858b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851454414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1851454414
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2856879552
Short name T561
Test name
Test status
Simulation time 142784662 ps
CPU time 1.14 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:06 PM PDT 24
Peak memory 199896 kb
Host smart-0f3df537-8cb3-430f-99c0-27424da4d98d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856879552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2856879552
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.739356973
Short name T607
Test name
Test status
Simulation time 792332353 ps
CPU time 3.13 seconds
Started Jul 24 05:23:09 PM PDT 24
Finished Jul 24 05:23:12 PM PDT 24
Peak memory 200088 kb
Host smart-a5dec0dc-6d02-406e-9223-ead3d82cdd96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739356973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.739356973
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3134757464
Short name T564
Test name
Test status
Simulation time 130280882 ps
CPU time 1.37 seconds
Started Jul 24 05:23:15 PM PDT 24
Finished Jul 24 05:23:17 PM PDT 24
Peak memory 208320 kb
Host smart-d6662909-866f-49b4-9d18-0431c2c7a3ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134757464 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3134757464
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.469168474
Short name T540
Test name
Test status
Simulation time 66861437 ps
CPU time 0.78 seconds
Started Jul 24 05:23:24 PM PDT 24
Finished Jul 24 05:23:25 PM PDT 24
Peak memory 199920 kb
Host smart-04dbe0b0-89cb-4356-b623-eb3cbca3bc7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469168474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.469168474
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3036344660
Short name T98
Test name
Test status
Simulation time 126372926 ps
CPU time 1.22 seconds
Started Jul 24 05:23:17 PM PDT 24
Finished Jul 24 05:23:19 PM PDT 24
Peak memory 200080 kb
Host smart-efedcfb5-c611-4ec3-8657-7e2fa406a792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036344660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3036344660
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3190997449
Short name T616
Test name
Test status
Simulation time 582788241 ps
CPU time 4.46 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:09 PM PDT 24
Peak memory 208192 kb
Host smart-ced87c07-ba63-47f9-a45b-840422c5a5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190997449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3190997449
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3207259174
Short name T599
Test name
Test status
Simulation time 430710281 ps
CPU time 1.96 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 200068 kb
Host smart-633c14b9-766c-44f5-9d9f-e28941dffc59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207259174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3207259174
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1163520256
Short name T574
Test name
Test status
Simulation time 120457547 ps
CPU time 1.07 seconds
Started Jul 24 05:23:11 PM PDT 24
Finished Jul 24 05:23:12 PM PDT 24
Peak memory 199872 kb
Host smart-fcbe5782-a041-4516-91dc-33e7af6a4ede
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163520256 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1163520256
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1452793220
Short name T96
Test name
Test status
Simulation time 55688671 ps
CPU time 0.74 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:04 PM PDT 24
Peak memory 199860 kb
Host smart-392dd111-5616-43ca-96ea-062308e85fcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452793220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1452793220
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3497546508
Short name T97
Test name
Test status
Simulation time 83623861 ps
CPU time 1 seconds
Started Jul 24 05:23:08 PM PDT 24
Finished Jul 24 05:23:09 PM PDT 24
Peak memory 199976 kb
Host smart-999dbb38-3fbb-4ac4-b1ca-bd07c963ca5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497546508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3497546508
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1296423540
Short name T604
Test name
Test status
Simulation time 162356137 ps
CPU time 2.21 seconds
Started Jul 24 05:23:32 PM PDT 24
Finished Jul 24 05:23:39 PM PDT 24
Peak memory 211612 kb
Host smart-1ef9b6ef-5d4b-4da0-9cdf-723780bff38e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296423540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1296423540
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2878761406
Short name T106
Test name
Test status
Simulation time 890125684 ps
CPU time 2.97 seconds
Started Jul 24 05:23:05 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 200204 kb
Host smart-00ba5aa8-2e9f-44ae-89ef-e15b270ae0dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878761406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2878761406
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3632048542
Short name T559
Test name
Test status
Simulation time 179898576 ps
CPU time 1.72 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:06 PM PDT 24
Peak memory 208312 kb
Host smart-2ec15deb-d9d0-4862-9065-c9eb233c921d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632048542 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3632048542
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1107765781
Short name T615
Test name
Test status
Simulation time 71863186 ps
CPU time 0.78 seconds
Started Jul 24 05:23:07 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 199832 kb
Host smart-49f46921-a920-4ed8-8c94-12522e0b7b05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107765781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1107765781
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2659713723
Short name T619
Test name
Test status
Simulation time 93328658 ps
CPU time 1.14 seconds
Started Jul 24 05:23:06 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 199892 kb
Host smart-68987903-3760-4293-b19a-d473c05d807d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659713723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2659713723
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.858291525
Short name T59
Test name
Test status
Simulation time 88829719 ps
CPU time 1.27 seconds
Started Jul 24 05:23:06 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 208020 kb
Host smart-e5881cb3-6822-4adc-8963-d8445e1002e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858291525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.858291525
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3439034037
Short name T78
Test name
Test status
Simulation time 905741873 ps
CPU time 2.99 seconds
Started Jul 24 05:23:05 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 200076 kb
Host smart-58622d94-5d8a-4078-be35-14e8654383c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439034037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3439034037
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1338744877
Short name T566
Test name
Test status
Simulation time 153531334 ps
CPU time 1.92 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:04 PM PDT 24
Peak memory 199960 kb
Host smart-06cef8cc-b039-41f7-8fcc-cd6cd2496792
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338744877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
338744877
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4024979133
Short name T547
Test name
Test status
Simulation time 802366310 ps
CPU time 4.88 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:09 PM PDT 24
Peak memory 199956 kb
Host smart-409a53eb-5bc4-4f4d-b120-7817ad6764c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024979133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.4
024979133
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4003750092
Short name T553
Test name
Test status
Simulation time 115152360 ps
CPU time 0.91 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:03 PM PDT 24
Peak memory 199736 kb
Host smart-71f01d00-07ac-4ace-bd0f-952fa5f5b709
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003750092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4
003750092
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1455976842
Short name T618
Test name
Test status
Simulation time 192150112 ps
CPU time 1.85 seconds
Started Jul 24 05:22:54 PM PDT 24
Finished Jul 24 05:22:56 PM PDT 24
Peak memory 208312 kb
Host smart-88e09da0-bd23-422e-b126-89759515cd17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455976842 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1455976842
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.790387326
Short name T584
Test name
Test status
Simulation time 82360745 ps
CPU time 0.83 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:02 PM PDT 24
Peak memory 199748 kb
Host smart-38cd5984-74e2-4e4e-9e7a-392f92d6238e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790387326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.790387326
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1594711905
Short name T92
Test name
Test status
Simulation time 130319297 ps
CPU time 1.08 seconds
Started Jul 24 05:22:48 PM PDT 24
Finished Jul 24 05:22:50 PM PDT 24
Peak memory 199920 kb
Host smart-75cfe4fd-1235-4b33-998f-bab141cb0af1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594711905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1594711905
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2034629748
Short name T590
Test name
Test status
Simulation time 215077839 ps
CPU time 1.68 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 208228 kb
Host smart-d6bc59a3-14f4-41b9-ba61-3c1b84d91408
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034629748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2034629748
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2687562307
Short name T550
Test name
Test status
Simulation time 453782939 ps
CPU time 2.53 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 200000 kb
Host smart-c7d0eb43-01dc-4140-b301-1e6c49c5b03d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687562307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
687562307
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3308978703
Short name T545
Test name
Test status
Simulation time 270831927 ps
CPU time 3.12 seconds
Started Jul 24 05:22:58 PM PDT 24
Finished Jul 24 05:23:01 PM PDT 24
Peak memory 199968 kb
Host smart-5a598fea-9a74-4192-9d42-ca288ca6636a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308978703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
308978703
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2191614463
Short name T579
Test name
Test status
Simulation time 117448651 ps
CPU time 0.88 seconds
Started Jul 24 05:22:50 PM PDT 24
Finished Jul 24 05:22:51 PM PDT 24
Peak memory 199800 kb
Host smart-265e40ea-882b-4cf4-962e-f1c1ea312ff1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191614463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
191614463
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2838114305
Short name T582
Test name
Test status
Simulation time 106069842 ps
CPU time 1.08 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:04 PM PDT 24
Peak memory 211200 kb
Host smart-dadcb0ca-fe94-40b9-8406-e0a0ccdf304b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838114305 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2838114305
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4282931330
Short name T568
Test name
Test status
Simulation time 72699882 ps
CPU time 0.77 seconds
Started Jul 24 05:22:53 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 199768 kb
Host smart-7bfa9d85-88be-4d49-87b5-d533dd0bba13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282931330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4282931330
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.875612653
Short name T583
Test name
Test status
Simulation time 102409311 ps
CPU time 1.25 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:01 PM PDT 24
Peak memory 200012 kb
Host smart-f1560bde-66f1-4942-aae0-ae0748f86e12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875612653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.875612653
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3443903426
Short name T588
Test name
Test status
Simulation time 191782307 ps
CPU time 2.84 seconds
Started Jul 24 05:22:59 PM PDT 24
Finished Jul 24 05:23:02 PM PDT 24
Peak memory 211532 kb
Host smart-ad0e83ca-3d83-4ba3-89d8-3e7fa22b407a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443903426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3443903426
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3858671151
Short name T610
Test name
Test status
Simulation time 903154286 ps
CPU time 3.32 seconds
Started Jul 24 05:22:50 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 200004 kb
Host smart-b2337419-52ab-492a-8f20-8bf8774667fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858671151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3858671151
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.453228323
Short name T598
Test name
Test status
Simulation time 361410129 ps
CPU time 2.42 seconds
Started Jul 24 05:23:06 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 199988 kb
Host smart-32495867-ffc0-47b4-95d3-90e20ee9d199
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453228323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.453228323
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2097273351
Short name T556
Test name
Test status
Simulation time 793212475 ps
CPU time 4.62 seconds
Started Jul 24 05:22:55 PM PDT 24
Finished Jul 24 05:22:59 PM PDT 24
Peak memory 199964 kb
Host smart-099a0c57-7764-420e-8998-29e57abea47e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097273351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
097273351
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.351580021
Short name T555
Test name
Test status
Simulation time 107080731 ps
CPU time 0.85 seconds
Started Jul 24 05:22:53 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 199860 kb
Host smart-dbf7a4e2-a77f-4562-8a68-271de3597cef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351580021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.351580021
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1413023379
Short name T80
Test name
Test status
Simulation time 216123136 ps
CPU time 1.41 seconds
Started Jul 24 05:23:06 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 208160 kb
Host smart-53936287-847a-4dd5-b60d-6da058ea2bc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413023379 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1413023379
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2684253440
Short name T552
Test name
Test status
Simulation time 82521745 ps
CPU time 0.79 seconds
Started Jul 24 05:22:50 PM PDT 24
Finished Jul 24 05:22:51 PM PDT 24
Peak memory 199800 kb
Host smart-507387be-8b1e-40ba-b422-a9fc4d6d996d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684253440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2684253440
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3587452404
Short name T614
Test name
Test status
Simulation time 232448070 ps
CPU time 1.54 seconds
Started Jul 24 05:22:58 PM PDT 24
Finished Jul 24 05:22:59 PM PDT 24
Peak memory 200052 kb
Host smart-df4f9c52-c341-465f-aca8-cf00ad18c848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587452404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3587452404
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.28056328
Short name T592
Test name
Test status
Simulation time 199990431 ps
CPU time 2.9 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 208052 kb
Host smart-9eb09603-7c0d-4ba1-bf72-3aa7359a40d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28056328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.28056328
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1521928215
Short name T549
Test name
Test status
Simulation time 136569574 ps
CPU time 1.53 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:04 PM PDT 24
Peak memory 208400 kb
Host smart-526b393f-491e-4431-a583-36300bdd4d72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521928215 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1521928215
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1015810707
Short name T95
Test name
Test status
Simulation time 68824212 ps
CPU time 0.86 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:02 PM PDT 24
Peak memory 200028 kb
Host smart-30afecb6-32f4-4eb8-ab72-6ee140cccf4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015810707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1015810707
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2144788814
Short name T613
Test name
Test status
Simulation time 114866643 ps
CPU time 1.17 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:06 PM PDT 24
Peak memory 199912 kb
Host smart-5d1a5914-2432-415a-bf34-79acd978c3f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144788814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2144788814
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.560790711
Short name T81
Test name
Test status
Simulation time 439450915 ps
CPU time 3.55 seconds
Started Jul 24 05:22:56 PM PDT 24
Finished Jul 24 05:22:59 PM PDT 24
Peak memory 211608 kb
Host smart-e84beef2-13e4-4ad7-93d7-e3e972a2221a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560790711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.560790711
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2171462332
Short name T77
Test name
Test status
Simulation time 505125519 ps
CPU time 1.98 seconds
Started Jul 24 05:23:07 PM PDT 24
Finished Jul 24 05:23:09 PM PDT 24
Peak memory 200080 kb
Host smart-7b9379e4-eb3e-4ed7-8aa2-843d4395beee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171462332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2171462332
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.163823839
Short name T61
Test name
Test status
Simulation time 176495749 ps
CPU time 1.65 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:06 PM PDT 24
Peak memory 208332 kb
Host smart-74b1c42a-2da2-40b2-ae01-e02319624668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163823839 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.163823839
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2690338424
Short name T570
Test name
Test status
Simulation time 67982957 ps
CPU time 0.79 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:02 PM PDT 24
Peak memory 199960 kb
Host smart-98962cb1-1341-4bb8-a62d-0c8d11e757c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690338424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2690338424
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3113519519
Short name T597
Test name
Test status
Simulation time 226444492 ps
CPU time 1.43 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:01 PM PDT 24
Peak memory 200048 kb
Host smart-ba65414e-b88c-4938-8154-9db2b2907a03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113519519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3113519519
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1757747128
Short name T544
Test name
Test status
Simulation time 201199082 ps
CPU time 1.59 seconds
Started Jul 24 05:22:56 PM PDT 24
Finished Jul 24 05:22:58 PM PDT 24
Peak memory 208212 kb
Host smart-d50d513d-acad-4d3b-9c33-e79ef10e604a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757747128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1757747128
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1186686644
Short name T603
Test name
Test status
Simulation time 161698920 ps
CPU time 1.33 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 208384 kb
Host smart-23da3fcb-7c5b-429c-94a8-4135d89386ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186686644 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1186686644
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.570441176
Short name T581
Test name
Test status
Simulation time 59273693 ps
CPU time 0.79 seconds
Started Jul 24 05:23:01 PM PDT 24
Finished Jul 24 05:23:02 PM PDT 24
Peak memory 199744 kb
Host smart-1e86a5e9-b532-4e29-953a-bc666aae7cc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570441176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.570441176
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1704587767
Short name T100
Test name
Test status
Simulation time 122320237 ps
CPU time 1.2 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:03 PM PDT 24
Peak memory 200108 kb
Host smart-16b5dce9-40af-45d5-8cb8-1e245ae3a2bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704587767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1704587767
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3264149892
Short name T102
Test name
Test status
Simulation time 326484571 ps
CPU time 2.11 seconds
Started Jul 24 05:22:58 PM PDT 24
Finished Jul 24 05:23:00 PM PDT 24
Peak memory 211216 kb
Host smart-fae221d3-120e-4c57-bc88-713f87fd3710
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264149892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3264149892
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3110264585
Short name T543
Test name
Test status
Simulation time 464485461 ps
CPU time 2.03 seconds
Started Jul 24 05:23:01 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 199996 kb
Host smart-e61a060e-d3f8-4e9e-a6ab-1ad31b9d10ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110264585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3110264585
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1334307295
Short name T612
Test name
Test status
Simulation time 159939948 ps
CPU time 1.05 seconds
Started Jul 24 05:23:08 PM PDT 24
Finished Jul 24 05:23:09 PM PDT 24
Peak memory 199988 kb
Host smart-ae4e6f35-8b03-47ff-9f6a-7da113c5d886
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334307295 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1334307295
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.261100322
Short name T565
Test name
Test status
Simulation time 60915111 ps
CPU time 0.77 seconds
Started Jul 24 05:22:59 PM PDT 24
Finished Jul 24 05:23:00 PM PDT 24
Peak memory 199868 kb
Host smart-0a38d338-2136-408a-a342-e3e07b1e568c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261100322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.261100322
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.719786279
Short name T572
Test name
Test status
Simulation time 160399193 ps
CPU time 1.25 seconds
Started Jul 24 05:22:56 PM PDT 24
Finished Jul 24 05:22:58 PM PDT 24
Peak memory 199932 kb
Host smart-79b53335-cb9e-4a6f-84c5-d58bfd30e51d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719786279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.719786279
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2363234448
Short name T60
Test name
Test status
Simulation time 86496597 ps
CPU time 1.12 seconds
Started Jul 24 05:22:59 PM PDT 24
Finished Jul 24 05:23:00 PM PDT 24
Peak memory 199824 kb
Host smart-9c692409-9b0e-4f4a-835e-8305f5a82f97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363234448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2363234448
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2747670233
Short name T594
Test name
Test status
Simulation time 476869026 ps
CPU time 1.96 seconds
Started Jul 24 05:22:57 PM PDT 24
Finished Jul 24 05:22:59 PM PDT 24
Peak memory 200076 kb
Host smart-3b1c0fec-66a3-4691-b858-4b8559eb1ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747670233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2747670233
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2671613151
Short name T76
Test name
Test status
Simulation time 184866796 ps
CPU time 1.41 seconds
Started Jul 24 05:22:55 PM PDT 24
Finished Jul 24 05:22:57 PM PDT 24
Peak memory 208180 kb
Host smart-d946f715-65ff-4ec8-9ece-143ab08e57a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671613151 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2671613151
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4149528317
Short name T585
Test name
Test status
Simulation time 87372691 ps
CPU time 0.85 seconds
Started Jul 24 05:22:57 PM PDT 24
Finished Jul 24 05:22:58 PM PDT 24
Peak memory 199808 kb
Host smart-2080610e-5c53-4b59-b973-49da9ed48f4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149528317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4149528317
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2701761986
Short name T601
Test name
Test status
Simulation time 202282165 ps
CPU time 1.45 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:02 PM PDT 24
Peak memory 200064 kb
Host smart-51baedc1-3408-4ab7-a5fa-23dd414373c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701761986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2701761986
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2256688853
Short name T75
Test name
Test status
Simulation time 208606444 ps
CPU time 3.23 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:08 PM PDT 24
Peak memory 199976 kb
Host smart-015905eb-009f-4d1d-8618-143b29b0012f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256688853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2256688853
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1784098996
Short name T67
Test name
Test status
Simulation time 929003043 ps
CPU time 3.3 seconds
Started Jul 24 05:22:55 PM PDT 24
Finished Jul 24 05:22:58 PM PDT 24
Peak memory 200116 kb
Host smart-d8261d52-e7dd-488b-8e95-8d5f35711407
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784098996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1784098996
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3105015191
Short name T501
Test name
Test status
Simulation time 79039084 ps
CPU time 0.73 seconds
Started Jul 24 07:06:27 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 199964 kb
Host smart-dfa8f560-c2bd-499f-813f-4c1c962454bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105015191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3105015191
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1809986948
Short name T469
Test name
Test status
Simulation time 1226411784 ps
CPU time 5.63 seconds
Started Jul 24 07:06:29 PM PDT 24
Finished Jul 24 07:06:35 PM PDT 24
Peak memory 217380 kb
Host smart-8be304bd-e6da-4d6f-a2ea-09a1020ce6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809986948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1809986948
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1968627375
Short name T278
Test name
Test status
Simulation time 244242080 ps
CPU time 1.1 seconds
Started Jul 24 07:06:30 PM PDT 24
Finished Jul 24 07:06:31 PM PDT 24
Peak memory 217592 kb
Host smart-56035419-035b-4f15-ad54-e1c61ff0f1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968627375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1968627375
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2951123879
Short name T326
Test name
Test status
Simulation time 80038380 ps
CPU time 0.74 seconds
Started Jul 24 07:06:37 PM PDT 24
Finished Jul 24 07:06:37 PM PDT 24
Peak memory 199956 kb
Host smart-475a316c-124d-47b1-b472-8a099f8583e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951123879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2951123879
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.479774795
Short name T349
Test name
Test status
Simulation time 2274544353 ps
CPU time 8.6 seconds
Started Jul 24 07:06:27 PM PDT 24
Finished Jul 24 07:06:36 PM PDT 24
Peak memory 200644 kb
Host smart-db137abd-f500-4473-8717-bb7289358f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479774795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.479774795
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.228965695
Short name T68
Test name
Test status
Simulation time 28350178834 ps
CPU time 51.14 seconds
Started Jul 24 07:06:33 PM PDT 24
Finished Jul 24 07:07:24 PM PDT 24
Peak memory 217732 kb
Host smart-c66ab1c7-367b-4030-b370-4daf7056fba3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228965695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.228965695
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.580831034
Short name T231
Test name
Test status
Simulation time 105999581 ps
CPU time 1.06 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:35 PM PDT 24
Peak memory 200132 kb
Host smart-2eecd235-a87a-4542-bf26-590ded23e09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580831034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.580831034
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3286793135
Short name T308
Test name
Test status
Simulation time 195823149 ps
CPU time 1.29 seconds
Started Jul 24 07:06:36 PM PDT 24
Finished Jul 24 07:06:38 PM PDT 24
Peak memory 200344 kb
Host smart-f1129a25-4189-4678-8150-40b7b2779b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286793135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3286793135
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2191666103
Short name T23
Test name
Test status
Simulation time 7464626713 ps
CPU time 27.37 seconds
Started Jul 24 07:06:30 PM PDT 24
Finished Jul 24 07:06:57 PM PDT 24
Peak memory 200468 kb
Host smart-49e76d1a-fa44-4914-a4ab-8abff33f875c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191666103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2191666103
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2947865245
Short name T470
Test name
Test status
Simulation time 138691230 ps
CPU time 1.7 seconds
Started Jul 24 07:06:31 PM PDT 24
Finished Jul 24 07:06:33 PM PDT 24
Peak memory 208368 kb
Host smart-611f80bc-61ed-430e-a68e-f697bea35d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947865245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2947865245
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2384878493
Short name T411
Test name
Test status
Simulation time 123989999 ps
CPU time 0.91 seconds
Started Jul 24 07:06:28 PM PDT 24
Finished Jul 24 07:06:29 PM PDT 24
Peak memory 200160 kb
Host smart-7f2d5633-eb95-455c-9fe5-ef97d42003ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384878493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2384878493
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2428894094
Short name T218
Test name
Test status
Simulation time 82746508 ps
CPU time 0.78 seconds
Started Jul 24 07:06:38 PM PDT 24
Finished Jul 24 07:06:39 PM PDT 24
Peak memory 199932 kb
Host smart-61619467-31ec-4a56-abd8-f6d319838ac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428894094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2428894094
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3716562449
Short name T373
Test name
Test status
Simulation time 244613931 ps
CPU time 1.05 seconds
Started Jul 24 07:06:28 PM PDT 24
Finished Jul 24 07:06:29 PM PDT 24
Peak memory 217472 kb
Host smart-347539a8-77ea-467b-9f94-f4c68116fa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716562449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3716562449
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3098627327
Short name T341
Test name
Test status
Simulation time 1583955139 ps
CPU time 6.16 seconds
Started Jul 24 07:06:27 PM PDT 24
Finished Jul 24 07:06:34 PM PDT 24
Peak memory 200460 kb
Host smart-f0db11f9-9396-46c1-9403-573914ce53a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098627327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3098627327
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1436435396
Short name T69
Test name
Test status
Simulation time 8282844075 ps
CPU time 15.24 seconds
Started Jul 24 07:06:29 PM PDT 24
Finished Jul 24 07:06:44 PM PDT 24
Peak memory 217632 kb
Host smart-da02e47f-935e-46cb-8b33-4f26e6585802
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436435396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1436435396
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.577491763
Short name T13
Test name
Test status
Simulation time 200275472 ps
CPU time 1.4 seconds
Started Jul 24 07:06:26 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 200272 kb
Host smart-69b0e1cd-bd9b-42ec-9134-b641b382dc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577491763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.577491763
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3594276022
Short name T488
Test name
Test status
Simulation time 3763023529 ps
CPU time 13.14 seconds
Started Jul 24 07:06:28 PM PDT 24
Finished Jul 24 07:06:41 PM PDT 24
Peak memory 210360 kb
Host smart-042439ae-c25b-4372-8cf7-d3b885418109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594276022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3594276022
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.420582358
Short name T325
Test name
Test status
Simulation time 129109442 ps
CPU time 1.59 seconds
Started Jul 24 07:06:37 PM PDT 24
Finished Jul 24 07:06:39 PM PDT 24
Peak memory 200200 kb
Host smart-c6805291-f21a-4ddc-8888-39876040a1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420582358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.420582358
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2851290558
Short name T179
Test name
Test status
Simulation time 157276348 ps
CPU time 1.08 seconds
Started Jul 24 07:06:27 PM PDT 24
Finished Jul 24 07:06:28 PM PDT 24
Peak memory 200144 kb
Host smart-d859e7a6-4cda-4f46-aa4e-476c39f8697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851290558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2851290558
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3185639687
Short name T527
Test name
Test status
Simulation time 76779733 ps
CPU time 0.79 seconds
Started Jul 24 07:07:11 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 199932 kb
Host smart-dade3d26-0748-4a8b-8be9-775a2f2430e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185639687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3185639687
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1195254215
Short name T397
Test name
Test status
Simulation time 2349139909 ps
CPU time 8.89 seconds
Started Jul 24 07:06:48 PM PDT 24
Finished Jul 24 07:06:57 PM PDT 24
Peak memory 217964 kb
Host smart-37a942bd-99a4-47b9-a844-1cd4e9205d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195254215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1195254215
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4268679820
Short name T429
Test name
Test status
Simulation time 192655122 ps
CPU time 0.9 seconds
Started Jul 24 07:06:46 PM PDT 24
Finished Jul 24 07:06:47 PM PDT 24
Peak memory 199972 kb
Host smart-550ead04-7166-4a8d-8409-702bb908c7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268679820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4268679820
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2097535202
Short name T112
Test name
Test status
Simulation time 1528035176 ps
CPU time 5.8 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:53 PM PDT 24
Peak memory 200380 kb
Host smart-99690e43-a415-40db-9f95-5bb72388bb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097535202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2097535202
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2371101961
Short name T239
Test name
Test status
Simulation time 91778504 ps
CPU time 1 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:49 PM PDT 24
Peak memory 200188 kb
Host smart-ee59608e-09d9-40ab-bb2e-dc20dd433ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371101961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2371101961
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3401784222
Short name T148
Test name
Test status
Simulation time 126914318 ps
CPU time 1.34 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:49 PM PDT 24
Peak memory 200396 kb
Host smart-203a8099-ed9a-48a4-baac-f75e5706d127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401784222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3401784222
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2756311640
Short name T424
Test name
Test status
Simulation time 2835713015 ps
CPU time 10.67 seconds
Started Jul 24 07:06:46 PM PDT 24
Finished Jul 24 07:06:57 PM PDT 24
Peak memory 208632 kb
Host smart-595ad258-70cd-4bf0-a683-2902db5b577e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756311640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2756311640
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3838886450
Short name T192
Test name
Test status
Simulation time 154701826 ps
CPU time 1.88 seconds
Started Jul 24 07:06:46 PM PDT 24
Finished Jul 24 07:06:48 PM PDT 24
Peak memory 200160 kb
Host smart-5e360782-4db0-4a54-9efb-46089a909270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838886450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3838886450
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1967014172
Short name T393
Test name
Test status
Simulation time 88899532 ps
CPU time 0.9 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:48 PM PDT 24
Peak memory 200104 kb
Host smart-afa54f7a-6926-42b6-94da-83729e8dd16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967014172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1967014172
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.126930141
Short name T514
Test name
Test status
Simulation time 83790144 ps
CPU time 0.83 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:54 PM PDT 24
Peak memory 199932 kb
Host smart-0ba35a91-3d96-46ac-bb22-dd71d30a8f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126930141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.126930141
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1671578432
Short name T54
Test name
Test status
Simulation time 2354959556 ps
CPU time 8.5 seconds
Started Jul 24 07:06:54 PM PDT 24
Finished Jul 24 07:07:03 PM PDT 24
Peak memory 217884 kb
Host smart-02c43537-ab84-4b55-8761-14724c51cf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671578432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1671578432
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3193076240
Short name T188
Test name
Test status
Simulation time 244327937 ps
CPU time 1.08 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:06:57 PM PDT 24
Peak memory 217476 kb
Host smart-42578009-d610-42d1-a0c6-f88e793f4bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193076240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3193076240
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.868732121
Short name T135
Test name
Test status
Simulation time 235537297 ps
CPU time 0.96 seconds
Started Jul 24 07:06:54 PM PDT 24
Finished Jul 24 07:06:55 PM PDT 24
Peak memory 199924 kb
Host smart-784ddd00-4a8b-44ab-95e5-f2e991ad927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868732121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.868732121
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.170042901
Short name T423
Test name
Test status
Simulation time 978548429 ps
CPU time 5.31 seconds
Started Jul 24 07:06:57 PM PDT 24
Finished Jul 24 07:07:02 PM PDT 24
Peak memory 200388 kb
Host smart-829431ef-fef0-4f98-8ef0-2bfbbeeff689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170042901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.170042901
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3756727237
Short name T294
Test name
Test status
Simulation time 139956584 ps
CPU time 1.13 seconds
Started Jul 24 07:06:54 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 200116 kb
Host smart-c4d885bb-5366-4237-b92d-d153811ffa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756727237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3756727237
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1569078675
Short name T137
Test name
Test status
Simulation time 181862599 ps
CPU time 1.48 seconds
Started Jul 24 07:06:56 PM PDT 24
Finished Jul 24 07:06:58 PM PDT 24
Peak memory 200292 kb
Host smart-053dd4dd-be7f-4a2b-ba86-d7fa56445e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569078675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1569078675
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1159519372
Short name T466
Test name
Test status
Simulation time 590700024 ps
CPU time 2.82 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 200280 kb
Host smart-b06c0679-8520-4676-aa91-0f646ad0314b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159519372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1159519372
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2845627038
Short name T292
Test name
Test status
Simulation time 357331812 ps
CPU time 2.22 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 200112 kb
Host smart-269fbd81-1308-4ab3-ac2e-425c99fdf3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845627038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2845627038
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3294206368
Short name T403
Test name
Test status
Simulation time 114526995 ps
CPU time 1.01 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:54 PM PDT 24
Peak memory 200144 kb
Host smart-1c657bb1-4e23-4f4d-bba1-2bda1556cc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294206368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3294206368
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3593381549
Short name T143
Test name
Test status
Simulation time 88622008 ps
CPU time 0.82 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 199844 kb
Host smart-6a5d2951-8ba0-4656-b8a9-ed834eaf2c7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593381549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3593381549
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1874654285
Short name T455
Test name
Test status
Simulation time 2376792444 ps
CPU time 8.35 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:07:03 PM PDT 24
Peak memory 221780 kb
Host smart-7fa81e72-1d1a-46e8-b353-2af7db2ab861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874654285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1874654285
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3577691041
Short name T524
Test name
Test status
Simulation time 244247029 ps
CPU time 1.1 seconds
Started Jul 24 07:06:54 PM PDT 24
Finished Jul 24 07:06:55 PM PDT 24
Peak memory 217524 kb
Host smart-a55ee3e2-0e85-40f3-9c63-105e5f96ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577691041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3577691041
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.475847396
Short name T407
Test name
Test status
Simulation time 116039434 ps
CPU time 0.86 seconds
Started Jul 24 07:06:54 PM PDT 24
Finished Jul 24 07:06:55 PM PDT 24
Peak memory 199980 kb
Host smart-bd3560f9-e078-4c39-8e47-b03ccc3d8ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475847396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.475847396
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.166622934
Short name T245
Test name
Test status
Simulation time 1609967395 ps
CPU time 7.04 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:07:02 PM PDT 24
Peak memory 200420 kb
Host smart-9b868b7e-248c-4c3c-b399-1f5d4b3a53d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166622934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.166622934
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1040316310
Short name T413
Test name
Test status
Simulation time 167984511 ps
CPU time 1.23 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 200116 kb
Host smart-ad385f6d-d92c-48ee-8d81-53ca4976d1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040316310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1040316310
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1734291891
Short name T331
Test name
Test status
Simulation time 114400794 ps
CPU time 1.18 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:06:57 PM PDT 24
Peak memory 200256 kb
Host smart-c0fa1490-cf7b-4625-b800-c24f3926a96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734291891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1734291891
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1627335943
Short name T506
Test name
Test status
Simulation time 10041271931 ps
CPU time 37.85 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:07:34 PM PDT 24
Peak memory 200420 kb
Host smart-d03205ba-79c7-42e0-9957-9b1a2b708386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627335943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1627335943
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2087343819
Short name T417
Test name
Test status
Simulation time 120118780 ps
CPU time 1.51 seconds
Started Jul 24 07:06:52 PM PDT 24
Finished Jul 24 07:06:54 PM PDT 24
Peak memory 200332 kb
Host smart-f0e57515-b933-4125-adba-0b06624f351c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087343819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2087343819
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2398007357
Short name T296
Test name
Test status
Simulation time 165156226 ps
CPU time 1.05 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:54 PM PDT 24
Peak memory 200168 kb
Host smart-562ac79c-9280-48cd-803d-7b380b9dee7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398007357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2398007357
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3323949678
Short name T157
Test name
Test status
Simulation time 88739037 ps
CPU time 0.83 seconds
Started Jul 24 07:06:54 PM PDT 24
Finished Jul 24 07:06:55 PM PDT 24
Peak memory 199916 kb
Host smart-0a8a47b2-0d69-461f-9398-b06db2e14654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323949678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3323949678
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2704125998
Short name T489
Test name
Test status
Simulation time 243535786 ps
CPU time 1.08 seconds
Started Jul 24 07:06:58 PM PDT 24
Finished Jul 24 07:06:59 PM PDT 24
Peak memory 217488 kb
Host smart-3aafdede-d671-4c86-b38c-421f226a61b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704125998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2704125998
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2176751968
Short name T237
Test name
Test status
Simulation time 203785376 ps
CPU time 0.89 seconds
Started Jul 24 07:06:56 PM PDT 24
Finished Jul 24 07:06:57 PM PDT 24
Peak memory 199968 kb
Host smart-3dd2f453-8ad1-4b27-873e-455537bc66e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176751968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2176751968
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.4017514109
Short name T236
Test name
Test status
Simulation time 1392295502 ps
CPU time 5.6 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:58 PM PDT 24
Peak memory 200396 kb
Host smart-e209dbb7-dcfc-4fbe-815a-d1a6869301b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017514109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.4017514109
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2276674444
Short name T536
Test name
Test status
Simulation time 110239866 ps
CPU time 1.03 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 200148 kb
Host smart-423aab41-14ad-4b8b-9720-5a9a30091e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276674444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2276674444
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2353244358
Short name T382
Test name
Test status
Simulation time 110230711 ps
CPU time 1.23 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:54 PM PDT 24
Peak memory 200412 kb
Host smart-3e97641f-c7ed-45f6-8163-da4f888bbb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353244358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2353244358
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1957596265
Short name T392
Test name
Test status
Simulation time 1695535509 ps
CPU time 7.96 seconds
Started Jul 24 07:06:58 PM PDT 24
Finished Jul 24 07:07:06 PM PDT 24
Peak memory 200460 kb
Host smart-a25dbdc6-36d0-44e8-bab7-e736f342cf6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957596265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1957596265
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3568256049
Short name T311
Test name
Test status
Simulation time 127404496 ps
CPU time 1.68 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:55 PM PDT 24
Peak memory 208356 kb
Host smart-73724499-65e7-4129-bcb1-e41c30e98180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568256049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3568256049
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.72213036
Short name T221
Test name
Test status
Simulation time 72025985 ps
CPU time 0.78 seconds
Started Jul 24 07:06:52 PM PDT 24
Finished Jul 24 07:06:53 PM PDT 24
Peak memory 199808 kb
Host smart-fe6323c3-a8d9-4cc2-b8fc-8d6699d177a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72213036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.72213036
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.528529019
Short name T372
Test name
Test status
Simulation time 244695714 ps
CPU time 1.06 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:54 PM PDT 24
Peak memory 217520 kb
Host smart-087acdea-b02f-431f-ac1d-be0c11b70a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528529019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.528529019
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.945897031
Short name T249
Test name
Test status
Simulation time 227615976 ps
CPU time 0.91 seconds
Started Jul 24 07:06:57 PM PDT 24
Finished Jul 24 07:06:58 PM PDT 24
Peak memory 199948 kb
Host smart-772245d3-3bcf-4b9d-b2aa-87bc8f204a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945897031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.945897031
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3338143278
Short name T315
Test name
Test status
Simulation time 923361551 ps
CPU time 4.63 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:58 PM PDT 24
Peak memory 200376 kb
Host smart-96493725-4caa-40a0-9d8e-13f57cab7098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338143278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3338143278
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2077274719
Short name T422
Test name
Test status
Simulation time 139492420 ps
CPU time 1.12 seconds
Started Jul 24 07:06:58 PM PDT 24
Finished Jul 24 07:06:59 PM PDT 24
Peak memory 200148 kb
Host smart-8ab01905-61ae-43e4-9c4b-7c56973cd7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077274719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2077274719
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3119836416
Short name T480
Test name
Test status
Simulation time 193909177 ps
CPU time 1.39 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:06:57 PM PDT 24
Peak memory 200340 kb
Host smart-8bfb9c07-a3aa-430a-9518-9f91847758ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119836416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3119836416
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1017041150
Short name T359
Test name
Test status
Simulation time 11081822145 ps
CPU time 38.49 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:07:34 PM PDT 24
Peak memory 200440 kb
Host smart-c52cf529-9a5d-4492-8e3a-9f1c09d4d887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017041150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1017041150
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1187428639
Short name T351
Test name
Test status
Simulation time 118410376 ps
CPU time 1.54 seconds
Started Jul 24 07:07:19 PM PDT 24
Finished Jul 24 07:07:20 PM PDT 24
Peak memory 200208 kb
Host smart-ba2e7d66-9753-4938-82b1-9866914cfc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187428639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1187428639
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3940006251
Short name T234
Test name
Test status
Simulation time 105371605 ps
CPU time 0.92 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:06:55 PM PDT 24
Peak memory 200176 kb
Host smart-81b57b5f-c9a5-4eb9-a5af-4b0cc39fe228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940006251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3940006251
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3954960955
Short name T133
Test name
Test status
Simulation time 71287701 ps
CPU time 0.75 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:07 PM PDT 24
Peak memory 199888 kb
Host smart-b88392fb-5690-4297-b787-5d127b469478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954960955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3954960955
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1919898279
Short name T435
Test name
Test status
Simulation time 1891924130 ps
CPU time 7.49 seconds
Started Jul 24 07:06:52 PM PDT 24
Finished Jul 24 07:07:00 PM PDT 24
Peak memory 216828 kb
Host smart-26b32b19-fa76-4625-9062-3bc21c584a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919898279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1919898279
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2332175014
Short name T150
Test name
Test status
Simulation time 243666209 ps
CPU time 1.12 seconds
Started Jul 24 07:06:54 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 217488 kb
Host smart-df8029ee-ddf3-4653-b14c-aae4e2728650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332175014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2332175014
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.885207120
Short name T220
Test name
Test status
Simulation time 98152429 ps
CPU time 0.81 seconds
Started Jul 24 07:06:54 PM PDT 24
Finished Jul 24 07:06:55 PM PDT 24
Peak memory 199960 kb
Host smart-ad746bff-66bc-49d0-8a5d-0fc4752aa0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885207120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.885207120
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1281163010
Short name T84
Test name
Test status
Simulation time 1656750285 ps
CPU time 6.64 seconds
Started Jul 24 07:06:53 PM PDT 24
Finished Jul 24 07:07:01 PM PDT 24
Peak memory 200408 kb
Host smart-876dd633-5cd1-4855-8210-25ed25af27f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281163010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1281163010
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.697608949
Short name T318
Test name
Test status
Simulation time 140247149 ps
CPU time 1.12 seconds
Started Jul 24 07:06:51 PM PDT 24
Finished Jul 24 07:06:52 PM PDT 24
Peak memory 200072 kb
Host smart-c1b62c23-defd-4f02-a10e-83030cdd15ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697608949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.697608949
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.907554064
Short name T165
Test name
Test status
Simulation time 107706464 ps
CPU time 1.23 seconds
Started Jul 24 07:06:55 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 200356 kb
Host smart-8be00162-4a6e-486c-ae75-175906fad568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907554064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.907554064
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3023361302
Short name T531
Test name
Test status
Simulation time 6704078354 ps
CPU time 23.35 seconds
Started Jul 24 07:07:03 PM PDT 24
Finished Jul 24 07:07:26 PM PDT 24
Peak memory 200480 kb
Host smart-2e71e917-185d-4a2e-bc32-77d0d3e029a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023361302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3023361302
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1877146499
Short name T457
Test name
Test status
Simulation time 217206805 ps
CPU time 1.5 seconds
Started Jul 24 07:07:01 PM PDT 24
Finished Jul 24 07:07:03 PM PDT 24
Peak memory 200140 kb
Host smart-a42538d2-d3c0-4938-b222-9f48e4fdcbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877146499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1877146499
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.424741736
Short name T171
Test name
Test status
Simulation time 70618919 ps
CPU time 0.78 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:01 PM PDT 24
Peak memory 199964 kb
Host smart-a1046025-f08d-4507-afac-b54fc114f877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424741736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.424741736
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.110665108
Short name T31
Test name
Test status
Simulation time 2167391212 ps
CPU time 8.2 seconds
Started Jul 24 07:07:05 PM PDT 24
Finished Jul 24 07:07:13 PM PDT 24
Peak memory 217796 kb
Host smart-967d7822-708d-4a7d-8bc5-d536adeadc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110665108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.110665108
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3742017194
Short name T298
Test name
Test status
Simulation time 244078023 ps
CPU time 1.03 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:07 PM PDT 24
Peak memory 217444 kb
Host smart-e9d26d88-0e0d-4adf-a86f-22eb92f05bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742017194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3742017194
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2622036801
Short name T17
Test name
Test status
Simulation time 189110844 ps
CPU time 0.96 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:01 PM PDT 24
Peak memory 199956 kb
Host smart-862b20f2-5422-4f57-ae10-76a0de4d87cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622036801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2622036801
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1697756420
Short name T430
Test name
Test status
Simulation time 1430241707 ps
CPU time 5.48 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:06 PM PDT 24
Peak memory 200416 kb
Host smart-26f0b1ba-2317-4e54-9d77-4ae46bf57302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697756420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1697756420
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.4159225594
Short name T324
Test name
Test status
Simulation time 92691981 ps
CPU time 1.06 seconds
Started Jul 24 07:07:02 PM PDT 24
Finished Jul 24 07:07:03 PM PDT 24
Peak memory 200104 kb
Host smart-c48c5ef0-5825-4d11-a0b3-77065930f75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159225594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.4159225594
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1040116487
Short name T400
Test name
Test status
Simulation time 202151098 ps
CPU time 1.35 seconds
Started Jul 24 07:07:03 PM PDT 24
Finished Jul 24 07:07:04 PM PDT 24
Peak memory 200304 kb
Host smart-78bc93ef-d46c-4ca9-8fb8-dfddef6aecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040116487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1040116487
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.876371192
Short name T242
Test name
Test status
Simulation time 3696678226 ps
CPU time 16.09 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:22 PM PDT 24
Peak memory 208604 kb
Host smart-71859c02-9c88-4e45-a5d9-b5f0d337865e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876371192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.876371192
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1899745766
Short name T452
Test name
Test status
Simulation time 130528151 ps
CPU time 1.68 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:02 PM PDT 24
Peak memory 208360 kb
Host smart-359aebbd-a286-495f-829f-75b5c5b6fa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899745766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1899745766
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1232804150
Short name T432
Test name
Test status
Simulation time 156247990 ps
CPU time 1.24 seconds
Started Jul 24 07:07:02 PM PDT 24
Finished Jul 24 07:07:03 PM PDT 24
Peak memory 200184 kb
Host smart-ec38ef62-bace-4d3e-844f-51b02e975e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232804150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1232804150
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2453450747
Short name T241
Test name
Test status
Simulation time 61990850 ps
CPU time 0.78 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:00 PM PDT 24
Peak memory 200144 kb
Host smart-69820da0-dd46-4b5a-b66f-ee314413a3d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453450747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2453450747
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3189218566
Short name T378
Test name
Test status
Simulation time 2346765207 ps
CPU time 8.74 seconds
Started Jul 24 07:07:01 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 217952 kb
Host smart-be3a121d-9626-4991-b400-d0d366b8519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189218566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3189218566
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.180346032
Short name T334
Test name
Test status
Simulation time 245080990 ps
CPU time 1.1 seconds
Started Jul 24 07:07:03 PM PDT 24
Finished Jul 24 07:07:04 PM PDT 24
Peak memory 217500 kb
Host smart-61a6d92a-3e4f-4560-9bdc-a7b363e5e25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180346032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.180346032
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2884379388
Short name T16
Test name
Test status
Simulation time 108982367 ps
CPU time 0.78 seconds
Started Jul 24 07:07:01 PM PDT 24
Finished Jul 24 07:07:02 PM PDT 24
Peak memory 199928 kb
Host smart-f31e01ff-b5c1-497f-b84a-57b8c5e4b58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884379388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2884379388
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3238326009
Short name T431
Test name
Test status
Simulation time 1613886463 ps
CPU time 6.11 seconds
Started Jul 24 07:07:01 PM PDT 24
Finished Jul 24 07:07:08 PM PDT 24
Peak memory 200392 kb
Host smart-3f8774e8-7da9-4d7a-b1ad-84bedb2d3af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238326009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3238326009
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3493650066
Short name T226
Test name
Test status
Simulation time 108913648 ps
CPU time 1.13 seconds
Started Jul 24 07:07:02 PM PDT 24
Finished Jul 24 07:07:03 PM PDT 24
Peak memory 200128 kb
Host smart-61919d33-ea2e-4cd3-ae96-d1742f07ecdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493650066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3493650066
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1612898041
Short name T238
Test name
Test status
Simulation time 192244569 ps
CPU time 1.47 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:02 PM PDT 24
Peak memory 200296 kb
Host smart-fd017b04-1c91-4a17-b8fd-19a0a07e072b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612898041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1612898041
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3848353524
Short name T460
Test name
Test status
Simulation time 123440781 ps
CPU time 1.58 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:02 PM PDT 24
Peak memory 208308 kb
Host smart-d4ed1428-6751-4360-a863-3bb1c7008cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848353524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3848353524
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3582661524
Short name T363
Test name
Test status
Simulation time 107400182 ps
CPU time 0.91 seconds
Started Jul 24 07:06:59 PM PDT 24
Finished Jul 24 07:07:00 PM PDT 24
Peak memory 200164 kb
Host smart-83f39964-3345-4636-85a0-1ec32fcbfaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582661524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3582661524
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3972451120
Short name T523
Test name
Test status
Simulation time 55329473 ps
CPU time 0.78 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:01 PM PDT 24
Peak memory 199952 kb
Host smart-bef3cde6-8fdf-459c-b78a-ef37d1d9cf30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972451120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3972451120
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.4125966915
Short name T266
Test name
Test status
Simulation time 1888590227 ps
CPU time 7.17 seconds
Started Jul 24 07:07:05 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 221708 kb
Host smart-838c12f8-5caa-42cf-9606-08f5dbdb86d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125966915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.4125966915
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1958386360
Short name T214
Test name
Test status
Simulation time 244282209 ps
CPU time 1.1 seconds
Started Jul 24 07:06:58 PM PDT 24
Finished Jul 24 07:06:59 PM PDT 24
Peak memory 217484 kb
Host smart-fa648835-e087-4263-99bb-51d6d49c36f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958386360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1958386360
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.757862591
Short name T5
Test name
Test status
Simulation time 112786716 ps
CPU time 0.82 seconds
Started Jul 24 07:07:02 PM PDT 24
Finished Jul 24 07:07:03 PM PDT 24
Peak memory 199928 kb
Host smart-3beb19a6-5b77-47b5-b97c-3774707779e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757862591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.757862591
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1315383642
Short name T504
Test name
Test status
Simulation time 1600287983 ps
CPU time 7.06 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:07 PM PDT 24
Peak memory 200380 kb
Host smart-cebc37d0-672e-42d6-a400-1a1c241d6711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315383642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1315383642
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.217549868
Short name T2
Test name
Test status
Simulation time 104485070 ps
CPU time 1.02 seconds
Started Jul 24 07:07:02 PM PDT 24
Finished Jul 24 07:07:04 PM PDT 24
Peak memory 200152 kb
Host smart-915021fa-e5a4-4183-89a9-edbc5f8c21e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217549868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.217549868
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2334765791
Short name T428
Test name
Test status
Simulation time 243359178 ps
CPU time 1.53 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:02 PM PDT 24
Peak memory 200384 kb
Host smart-f7603a31-24bf-411c-8954-48316fb1f391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334765791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2334765791
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3394018056
Short name T109
Test name
Test status
Simulation time 12669556732 ps
CPU time 42.2 seconds
Started Jul 24 07:07:01 PM PDT 24
Finished Jul 24 07:07:44 PM PDT 24
Peak memory 208704 kb
Host smart-c17c9445-f08c-4480-987c-7f57c0ee8250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394018056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3394018056
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.911377923
Short name T306
Test name
Test status
Simulation time 338947355 ps
CPU time 2.23 seconds
Started Jul 24 07:07:03 PM PDT 24
Finished Jul 24 07:07:06 PM PDT 24
Peak memory 208356 kb
Host smart-76cc2982-c77c-437c-a9ec-11236e6e1d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911377923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.911377923
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3907267519
Short name T502
Test name
Test status
Simulation time 126657096 ps
CPU time 1.08 seconds
Started Jul 24 07:07:02 PM PDT 24
Finished Jul 24 07:07:04 PM PDT 24
Peak memory 200168 kb
Host smart-0fce9148-8ca2-4cd5-b218-03db925519e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907267519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3907267519
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1102925919
Short name T235
Test name
Test status
Simulation time 71077041 ps
CPU time 0.81 seconds
Started Jul 24 07:07:07 PM PDT 24
Finished Jul 24 07:07:08 PM PDT 24
Peak memory 199980 kb
Host smart-1b36aec2-e220-4087-9834-9d3b362bce22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102925919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1102925919
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1543666971
Short name T304
Test name
Test status
Simulation time 1223540292 ps
CPU time 5.64 seconds
Started Jul 24 07:06:58 PM PDT 24
Finished Jul 24 07:07:04 PM PDT 24
Peak memory 217528 kb
Host smart-889d7ad4-0f1c-4719-a7ba-ee95894028c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543666971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1543666971
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.704715965
Short name T258
Test name
Test status
Simulation time 244250208 ps
CPU time 1.09 seconds
Started Jul 24 07:07:04 PM PDT 24
Finished Jul 24 07:07:05 PM PDT 24
Peak memory 217476 kb
Host smart-e4dba848-6c81-4f87-b446-785bbd1d031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704715965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.704715965
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2153093649
Short name T250
Test name
Test status
Simulation time 163497910 ps
CPU time 0.89 seconds
Started Jul 24 07:07:02 PM PDT 24
Finished Jul 24 07:07:03 PM PDT 24
Peak memory 199948 kb
Host smart-f37276ee-2301-4f31-9af7-bf2a8ff9636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153093649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2153093649
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3873710493
Short name T454
Test name
Test status
Simulation time 924988903 ps
CPU time 4.53 seconds
Started Jul 24 07:07:01 PM PDT 24
Finished Jul 24 07:07:05 PM PDT 24
Peak memory 200416 kb
Host smart-b1f19f01-e65f-47ae-8695-50e36fcfca79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873710493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3873710493
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2960299305
Short name T156
Test name
Test status
Simulation time 152273189 ps
CPU time 1.1 seconds
Started Jul 24 07:07:00 PM PDT 24
Finished Jul 24 07:07:01 PM PDT 24
Peak memory 200164 kb
Host smart-c8701902-226e-46f5-8efb-a0f8d6f4c45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960299305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2960299305
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.4209585403
Short name T355
Test name
Test status
Simulation time 120648409 ps
CPU time 1.27 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:08 PM PDT 24
Peak memory 200304 kb
Host smart-62d27f0b-c366-4875-a2fd-d2c1202e7ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209585403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.4209585403
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2838745584
Short name T87
Test name
Test status
Simulation time 7106167556 ps
CPU time 23.83 seconds
Started Jul 24 07:07:08 PM PDT 24
Finished Jul 24 07:07:32 PM PDT 24
Peak memory 208672 kb
Host smart-860c0bf8-b444-4aa8-a899-a698285ac4dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838745584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2838745584
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3334542539
Short name T246
Test name
Test status
Simulation time 372739960 ps
CPU time 2.36 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:09 PM PDT 24
Peak memory 200116 kb
Host smart-05e342d4-1886-4ba1-9093-4ce8089b032c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334542539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3334542539
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3817011670
Short name T173
Test name
Test status
Simulation time 74325735 ps
CPU time 0.8 seconds
Started Jul 24 07:07:01 PM PDT 24
Finished Jul 24 07:07:03 PM PDT 24
Peak memory 200180 kb
Host smart-edfbe6d4-b089-4f09-916a-c218e8b10de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817011670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3817011670
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2312510828
Short name T299
Test name
Test status
Simulation time 73404281 ps
CPU time 0.79 seconds
Started Jul 24 07:06:35 PM PDT 24
Finished Jul 24 07:06:36 PM PDT 24
Peak memory 199956 kb
Host smart-6cad4b35-f8c6-4aea-ab37-5a5e678cbadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312510828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2312510828
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1439705133
Short name T28
Test name
Test status
Simulation time 2345759679 ps
CPU time 9.92 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:44 PM PDT 24
Peak memory 217836 kb
Host smart-257ca4e1-16e1-42ca-8cba-fbe91b70d583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439705133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1439705133
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.184375216
Short name T36
Test name
Test status
Simulation time 244816425 ps
CPU time 1.06 seconds
Started Jul 24 07:06:33 PM PDT 24
Finished Jul 24 07:06:34 PM PDT 24
Peak memory 217524 kb
Host smart-9c4ff877-6964-4b76-ae75-4210bfd96639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184375216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.184375216
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2789934887
Short name T476
Test name
Test status
Simulation time 178022722 ps
CPU time 0.95 seconds
Started Jul 24 07:06:33 PM PDT 24
Finished Jul 24 07:06:35 PM PDT 24
Peak memory 200008 kb
Host smart-73d6da3d-fc96-4ee1-958c-359931fcb53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789934887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2789934887
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2641117978
Short name T83
Test name
Test status
Simulation time 944212762 ps
CPU time 4.81 seconds
Started Jul 24 07:06:35 PM PDT 24
Finished Jul 24 07:06:40 PM PDT 24
Peak memory 200432 kb
Host smart-8247cef0-8e50-4efc-a3ef-0a4b612ca4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641117978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2641117978
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1560707550
Short name T63
Test name
Test status
Simulation time 8281681017 ps
CPU time 16.69 seconds
Started Jul 24 07:06:38 PM PDT 24
Finished Jul 24 07:06:55 PM PDT 24
Peak memory 217060 kb
Host smart-712ed94f-8ea2-4f30-83a7-db54d09aea9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560707550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1560707550
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2387364496
Short name T155
Test name
Test status
Simulation time 108408398 ps
CPU time 1.01 seconds
Started Jul 24 07:06:38 PM PDT 24
Finished Jul 24 07:06:39 PM PDT 24
Peak memory 200132 kb
Host smart-9eb15757-1598-4fca-a2bc-e49ce7c4737f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387364496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2387364496
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3425868041
Short name T492
Test name
Test status
Simulation time 112814868 ps
CPU time 1.26 seconds
Started Jul 24 07:06:37 PM PDT 24
Finished Jul 24 07:06:38 PM PDT 24
Peak memory 200360 kb
Host smart-67d29880-a674-439f-a2c1-6ce9bfecef72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425868041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3425868041
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1323362302
Short name T483
Test name
Test status
Simulation time 9815406113 ps
CPU time 33.16 seconds
Started Jul 24 07:06:35 PM PDT 24
Finished Jul 24 07:07:08 PM PDT 24
Peak memory 200420 kb
Host smart-6b0559b1-0695-4885-88e3-09495ca7617a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323362302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1323362302
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1906457345
Short name T450
Test name
Test status
Simulation time 391911532 ps
CPU time 2.72 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:36 PM PDT 24
Peak memory 200148 kb
Host smart-b4676d44-353e-4a2b-9c76-92f4dfd3e122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906457345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1906457345
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3544340122
Short name T138
Test name
Test status
Simulation time 135743755 ps
CPU time 1.12 seconds
Started Jul 24 07:06:39 PM PDT 24
Finished Jul 24 07:06:40 PM PDT 24
Peak memory 200152 kb
Host smart-79b2f7ce-4fa7-40eb-99eb-bf056da439d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544340122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3544340122
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.4046504902
Short name T144
Test name
Test status
Simulation time 79152351 ps
CPU time 0.83 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:07 PM PDT 24
Peak memory 199916 kb
Host smart-ac22c265-cc3e-4aea-9da0-f6de0752ef1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046504902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.4046504902
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.858770854
Short name T347
Test name
Test status
Simulation time 1224085679 ps
CPU time 5.76 seconds
Started Jul 24 07:07:05 PM PDT 24
Finished Jul 24 07:07:11 PM PDT 24
Peak memory 217864 kb
Host smart-443b076a-c6e3-49a0-879a-c104c2dca3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858770854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.858770854
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1300516312
Short name T120
Test name
Test status
Simulation time 243782742 ps
CPU time 1.07 seconds
Started Jul 24 07:07:09 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 217452 kb
Host smart-99e7b0b8-3f45-4186-8859-2dfc70a080c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300516312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1300516312
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1188096162
Short name T20
Test name
Test status
Simulation time 97078057 ps
CPU time 0.81 seconds
Started Jul 24 07:07:07 PM PDT 24
Finished Jul 24 07:07:09 PM PDT 24
Peak memory 199992 kb
Host smart-eee48f4b-f944-40a6-92e7-665b4c79f403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188096162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1188096162
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1423332713
Short name T510
Test name
Test status
Simulation time 1723929153 ps
CPU time 6.11 seconds
Started Jul 24 07:07:08 PM PDT 24
Finished Jul 24 07:07:14 PM PDT 24
Peak memory 200376 kb
Host smart-8e59d561-c246-4d4d-90d9-c1fcba5df42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423332713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1423332713
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2381115884
Short name T303
Test name
Test status
Simulation time 101694035 ps
CPU time 1.02 seconds
Started Jul 24 07:07:09 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 200152 kb
Host smart-a1a5a10d-4458-470f-9c14-573223414681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381115884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2381115884
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3617030971
Short name T222
Test name
Test status
Simulation time 195282306 ps
CPU time 1.46 seconds
Started Jul 24 07:07:07 PM PDT 24
Finished Jul 24 07:07:09 PM PDT 24
Peak memory 200344 kb
Host smart-8cad29f1-4b62-4236-b51e-176e9d2d16f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617030971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3617030971
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2077917523
Short name T444
Test name
Test status
Simulation time 13720133973 ps
CPU time 49.04 seconds
Started Jul 24 07:07:10 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 208660 kb
Host smart-b04022a3-e43a-4aad-b3ac-686298ddb796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077917523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2077917523
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.844224270
Short name T416
Test name
Test status
Simulation time 352540487 ps
CPU time 2.25 seconds
Started Jul 24 07:07:09 PM PDT 24
Finished Jul 24 07:07:11 PM PDT 24
Peak memory 200072 kb
Host smart-6569d7d6-c7e1-4ccc-8a7e-5818fca62f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844224270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.844224270
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.878802598
Short name T500
Test name
Test status
Simulation time 247077594 ps
CPU time 1.41 seconds
Started Jul 24 07:07:09 PM PDT 24
Finished Jul 24 07:07:11 PM PDT 24
Peak memory 200224 kb
Host smart-00fc9261-41e6-4c10-9e67-fa32c3dbfdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878802598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.878802598
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2724811978
Short name T199
Test name
Test status
Simulation time 62576759 ps
CPU time 0.79 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:07 PM PDT 24
Peak memory 199940 kb
Host smart-9e975ae8-ad6d-4b51-97f9-0933db75813f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724811978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2724811978
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.974064676
Short name T44
Test name
Test status
Simulation time 1220661190 ps
CPU time 6.12 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:13 PM PDT 24
Peak memory 221728 kb
Host smart-1f184b25-6ddd-41fb-9289-0731a961317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974064676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.974064676
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1778764142
Short name T532
Test name
Test status
Simulation time 244775117 ps
CPU time 1.08 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:07 PM PDT 24
Peak memory 217440 kb
Host smart-12fe5342-95a2-458d-86d0-4496e1bd1ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778764142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1778764142
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3396198922
Short name T461
Test name
Test status
Simulation time 100688932 ps
CPU time 0.85 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:07 PM PDT 24
Peak memory 199876 kb
Host smart-d4cb5b51-c994-41b8-b5a7-10f68fa67b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396198922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3396198922
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2794603059
Short name T110
Test name
Test status
Simulation time 2270265502 ps
CPU time 7.91 seconds
Started Jul 24 07:07:10 PM PDT 24
Finished Jul 24 07:07:19 PM PDT 24
Peak memory 200456 kb
Host smart-6082f990-2c78-4319-b297-c5ad5165f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794603059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2794603059
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2064792566
Short name T401
Test name
Test status
Simulation time 178149612 ps
CPU time 1.13 seconds
Started Jul 24 07:07:10 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 200132 kb
Host smart-563b3e4e-e29d-4d8e-8966-3357fced9468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064792566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2064792566
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2378596158
Short name T269
Test name
Test status
Simulation time 191663174 ps
CPU time 1.37 seconds
Started Jul 24 07:07:09 PM PDT 24
Finished Jul 24 07:07:11 PM PDT 24
Peak memory 200356 kb
Host smart-633f41c7-dd64-4cd1-bcdb-0e06ed90f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378596158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2378596158
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2830159989
Short name T89
Test name
Test status
Simulation time 11439584436 ps
CPU time 45.44 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:52 PM PDT 24
Peak memory 200484 kb
Host smart-9f42fff1-d75c-4ec9-b778-ae9f56f227b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830159989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2830159989
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.4026128435
Short name T323
Test name
Test status
Simulation time 140815831 ps
CPU time 1.83 seconds
Started Jul 24 07:07:08 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 208428 kb
Host smart-cafe3162-dc36-4d56-9feb-3f3905c41db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026128435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4026128435
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3356966750
Short name T520
Test name
Test status
Simulation time 84659804 ps
CPU time 0.88 seconds
Started Jul 24 07:07:07 PM PDT 24
Finished Jul 24 07:07:09 PM PDT 24
Peak memory 200084 kb
Host smart-de6890a3-df6f-441e-85b8-3bff95abfd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356966750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3356966750
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2703915326
Short name T447
Test name
Test status
Simulation time 76733209 ps
CPU time 0.75 seconds
Started Jul 24 07:07:05 PM PDT 24
Finished Jul 24 07:07:06 PM PDT 24
Peak memory 199964 kb
Host smart-803e21ea-45c9-4f15-a7f4-8c3d8512846c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703915326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2703915326
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2970048501
Short name T30
Test name
Test status
Simulation time 1891589896 ps
CPU time 7.02 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:14 PM PDT 24
Peak memory 217476 kb
Host smart-fc5a8765-6435-4cbf-ae71-cde178f67f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970048501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2970048501
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3008158216
Short name T437
Test name
Test status
Simulation time 244662153 ps
CPU time 1.12 seconds
Started Jul 24 07:07:09 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 217444 kb
Host smart-71a3f727-38cf-4b0e-9951-16080e84201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008158216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3008158216
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2235257521
Short name T202
Test name
Test status
Simulation time 125164380 ps
CPU time 0.82 seconds
Started Jul 24 07:07:10 PM PDT 24
Finished Jul 24 07:07:11 PM PDT 24
Peak memory 199976 kb
Host smart-590e666d-4a3a-40b8-9906-9d5e8a597e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235257521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2235257521
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1068046453
Short name T508
Test name
Test status
Simulation time 1509135562 ps
CPU time 6.12 seconds
Started Jul 24 07:07:10 PM PDT 24
Finished Jul 24 07:07:16 PM PDT 24
Peak memory 200380 kb
Host smart-326549a0-e901-4155-b4a4-568fae0195f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068046453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1068046453
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.661081732
Short name T177
Test name
Test status
Simulation time 144207277 ps
CPU time 1.12 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:08 PM PDT 24
Peak memory 200152 kb
Host smart-5f309de6-d7b9-4dc9-8518-2bd4d2db706c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661081732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.661081732
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1707813415
Short name T467
Test name
Test status
Simulation time 113904343 ps
CPU time 1.16 seconds
Started Jul 24 07:07:08 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 200368 kb
Host smart-8ffd7584-b5d2-4f98-b4dc-38c48c92ce4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707813415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1707813415
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3064042606
Short name T131
Test name
Test status
Simulation time 242277853 ps
CPU time 1.47 seconds
Started Jul 24 07:07:10 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 200128 kb
Host smart-530255d8-a405-4b87-9be2-fc834f76526f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064042606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3064042606
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3768563187
Short name T142
Test name
Test status
Simulation time 150331202 ps
CPU time 1.91 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:09 PM PDT 24
Peak memory 200172 kb
Host smart-a7e6be71-b894-46f2-b43e-d285016646b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768563187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3768563187
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2304813432
Short name T40
Test name
Test status
Simulation time 271031231 ps
CPU time 1.52 seconds
Started Jul 24 07:07:11 PM PDT 24
Finished Jul 24 07:07:13 PM PDT 24
Peak memory 200360 kb
Host smart-a0c63ef6-0f22-458b-b845-4fecdfad318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304813432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2304813432
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1929592188
Short name T412
Test name
Test status
Simulation time 61610372 ps
CPU time 0.8 seconds
Started Jul 24 07:07:08 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 199940 kb
Host smart-67cfaaef-dc62-44ce-9cbf-008d643e8d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929592188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1929592188
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.245270101
Short name T42
Test name
Test status
Simulation time 1909330253 ps
CPU time 7.6 seconds
Started Jul 24 07:07:08 PM PDT 24
Finished Jul 24 07:07:16 PM PDT 24
Peak memory 217812 kb
Host smart-e435a9c1-4565-454a-ae34-224f823b645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245270101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.245270101
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1249853934
Short name T485
Test name
Test status
Simulation time 243990652 ps
CPU time 1.13 seconds
Started Jul 24 07:07:11 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 217556 kb
Host smart-ba3b65c1-e524-48d7-8a51-3e5e517e5a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249853934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1249853934
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.537633427
Short name T293
Test name
Test status
Simulation time 133605210 ps
CPU time 0.81 seconds
Started Jul 24 07:07:09 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 199932 kb
Host smart-ebe710f8-67f4-45ef-a855-f2b49a478365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537633427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.537633427
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.103109529
Short name T534
Test name
Test status
Simulation time 1320749513 ps
CPU time 5.51 seconds
Started Jul 24 07:07:07 PM PDT 24
Finished Jul 24 07:07:13 PM PDT 24
Peak memory 200360 kb
Host smart-6cae1bb4-9756-4816-ace2-b617cd0d1d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103109529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.103109529
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3083919767
Short name T345
Test name
Test status
Simulation time 182370721 ps
CPU time 1.23 seconds
Started Jul 24 07:07:07 PM PDT 24
Finished Jul 24 07:07:08 PM PDT 24
Peak memory 200152 kb
Host smart-772eae0a-fe1d-459d-aa85-8f4dbdc53def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083919767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3083919767
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3122802800
Short name T312
Test name
Test status
Simulation time 246582225 ps
CPU time 1.52 seconds
Started Jul 24 07:07:09 PM PDT 24
Finished Jul 24 07:07:11 PM PDT 24
Peak memory 200324 kb
Host smart-c61faa83-d58f-431e-ac5b-604a0d6dfa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122802800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3122802800
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.961224275
Short name T86
Test name
Test status
Simulation time 2154422113 ps
CPU time 7.78 seconds
Started Jul 24 07:07:07 PM PDT 24
Finished Jul 24 07:07:15 PM PDT 24
Peak memory 200488 kb
Host smart-601cf98c-85f1-4910-8efa-e5c80a5276b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961224275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.961224275
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3781178837
Short name T301
Test name
Test status
Simulation time 423907480 ps
CPU time 2.61 seconds
Started Jul 24 07:07:09 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 208372 kb
Host smart-3fb73220-9ead-4712-9133-8118db1172ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781178837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3781178837
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1150543670
Short name T370
Test name
Test status
Simulation time 227570422 ps
CPU time 1.4 seconds
Started Jul 24 07:07:08 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 200072 kb
Host smart-797095f0-b379-4ad3-a997-812df4b2ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150543670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1150543670
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1537036683
Short name T146
Test name
Test status
Simulation time 77498962 ps
CPU time 0.8 seconds
Started Jul 24 07:07:05 PM PDT 24
Finished Jul 24 07:07:06 PM PDT 24
Peak memory 199956 kb
Host smart-1342153e-3978-4958-bc89-b99b2f791a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537036683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1537036683
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1322235810
Short name T49
Test name
Test status
Simulation time 1232047874 ps
CPU time 6.08 seconds
Started Jul 24 07:07:12 PM PDT 24
Finished Jul 24 07:07:18 PM PDT 24
Peak memory 221792 kb
Host smart-22324d80-8a20-4a36-8c75-a31428ddb99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322235810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1322235810
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3771217888
Short name T9
Test name
Test status
Simulation time 244858504 ps
CPU time 1.18 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:07 PM PDT 24
Peak memory 217496 kb
Host smart-93b0de66-30ec-4eb1-974c-71f10d157664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771217888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3771217888
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.104938738
Short name T340
Test name
Test status
Simulation time 229658558 ps
CPU time 0.94 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:07 PM PDT 24
Peak memory 199976 kb
Host smart-8bde0c4f-cbd9-44a6-b4a7-a431c2c9c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104938738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.104938738
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2134402232
Short name T425
Test name
Test status
Simulation time 1785298673 ps
CPU time 6.84 seconds
Started Jul 24 07:07:10 PM PDT 24
Finished Jul 24 07:07:17 PM PDT 24
Peak memory 200436 kb
Host smart-4003ce25-e020-4e30-9589-af910ff3fe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134402232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2134402232
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3302659911
Short name T445
Test name
Test status
Simulation time 103413633 ps
CPU time 1.09 seconds
Started Jul 24 07:07:10 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 200084 kb
Host smart-a606332d-1a38-405b-b24f-e5c42f75bab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302659911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3302659911
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.585024274
Short name T125
Test name
Test status
Simulation time 114404177 ps
CPU time 1.17 seconds
Started Jul 24 07:07:10 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 200312 kb
Host smart-c9b10632-6d96-40d0-a15e-25d968cc09da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585024274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.585024274
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1596385379
Short name T491
Test name
Test status
Simulation time 13857843201 ps
CPU time 54.34 seconds
Started Jul 24 07:07:05 PM PDT 24
Finished Jul 24 07:07:59 PM PDT 24
Peak memory 200508 kb
Host smart-9b4cd8da-4e54-4755-8206-bd74652a0a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596385379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1596385379
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2606521569
Short name T115
Test name
Test status
Simulation time 445820616 ps
CPU time 2.41 seconds
Started Jul 24 07:07:07 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 208324 kb
Host smart-77ffb807-d477-43a0-80f5-fec942acb70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606521569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2606521569
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3632353981
Short name T448
Test name
Test status
Simulation time 130112764 ps
CPU time 1.05 seconds
Started Jul 24 07:07:07 PM PDT 24
Finished Jul 24 07:07:09 PM PDT 24
Peak memory 200120 kb
Host smart-04daa836-4958-4bc6-86ee-b2d5672adced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632353981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3632353981
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1773170728
Short name T223
Test name
Test status
Simulation time 71409047 ps
CPU time 0.74 seconds
Started Jul 24 07:07:13 PM PDT 24
Finished Jul 24 07:07:14 PM PDT 24
Peak memory 199944 kb
Host smart-afc90398-f2f2-42a9-ba98-d0dcc664e6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773170728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1773170728
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2986671179
Short name T507
Test name
Test status
Simulation time 2347016808 ps
CPU time 8.74 seconds
Started Jul 24 07:07:16 PM PDT 24
Finished Jul 24 07:07:25 PM PDT 24
Peak memory 221892 kb
Host smart-87d1185e-2a77-4d49-a0a6-5d3005a0a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986671179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2986671179
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3359559095
Short name T175
Test name
Test status
Simulation time 246485062 ps
CPU time 1.09 seconds
Started Jul 24 07:07:12 PM PDT 24
Finished Jul 24 07:07:13 PM PDT 24
Peak memory 217440 kb
Host smart-c452b5b3-e6da-4cb7-a1cd-7ecd437af061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359559095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3359559095
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3138978168
Short name T280
Test name
Test status
Simulation time 233739076 ps
CPU time 0.96 seconds
Started Jul 24 07:07:09 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 199964 kb
Host smart-8f75f9fc-5db3-49d0-9bbc-b28dd65d50d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138978168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3138978168
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.269642499
Short name T183
Test name
Test status
Simulation time 995789914 ps
CPU time 5.18 seconds
Started Jul 24 07:07:06 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 200388 kb
Host smart-6044d4bb-da85-4974-83ed-a60b881fd429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269642499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.269642499
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1368817787
Short name T371
Test name
Test status
Simulation time 153273088 ps
CPU time 1.13 seconds
Started Jul 24 07:07:14 PM PDT 24
Finished Jul 24 07:07:15 PM PDT 24
Peak memory 200152 kb
Host smart-79011a5a-30a0-407e-a415-97c2f668c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368817787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1368817787
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3195864603
Short name T147
Test name
Test status
Simulation time 111065523 ps
CPU time 1.25 seconds
Started Jul 24 07:07:10 PM PDT 24
Finished Jul 24 07:07:12 PM PDT 24
Peak memory 200412 kb
Host smart-1fa52f1f-5237-45a6-bec2-9a6d9ffcfe92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195864603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3195864603
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1140902946
Short name T22
Test name
Test status
Simulation time 10681654206 ps
CPU time 40.09 seconds
Started Jul 24 07:07:16 PM PDT 24
Finished Jul 24 07:07:57 PM PDT 24
Peak memory 208636 kb
Host smart-3afddf1c-c804-4901-99a1-9c56571e9743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140902946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1140902946
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1476172270
Short name T117
Test name
Test status
Simulation time 534444489 ps
CPU time 3.01 seconds
Started Jul 24 07:07:13 PM PDT 24
Finished Jul 24 07:07:16 PM PDT 24
Peak memory 200132 kb
Host smart-9732bc16-6474-459e-ae7a-0eaf5f18996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476172270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1476172270
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1724932450
Short name T170
Test name
Test status
Simulation time 189111449 ps
CPU time 1.23 seconds
Started Jul 24 07:07:08 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 200148 kb
Host smart-b6618f14-e205-437f-8bf9-188925c2d131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724932450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1724932450
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3626880780
Short name T314
Test name
Test status
Simulation time 61493031 ps
CPU time 0.75 seconds
Started Jul 24 07:07:13 PM PDT 24
Finished Jul 24 07:07:14 PM PDT 24
Peak memory 199980 kb
Host smart-53b4e2ae-4432-4ad4-b8f6-6d438ddabe4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626880780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3626880780
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.396068780
Short name T386
Test name
Test status
Simulation time 1859535981 ps
CPU time 7.6 seconds
Started Jul 24 07:07:21 PM PDT 24
Finished Jul 24 07:07:29 PM PDT 24
Peak memory 221736 kb
Host smart-a29f24d0-1b05-4c4a-a490-8a28ae9faa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396068780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.396068780
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2295608932
Short name T229
Test name
Test status
Simulation time 245907637 ps
CPU time 1.06 seconds
Started Jul 24 07:07:13 PM PDT 24
Finished Jul 24 07:07:14 PM PDT 24
Peak memory 217524 kb
Host smart-f4f1dc87-2554-460a-8631-bfa83b9ddf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295608932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2295608932
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1922617922
Short name T477
Test name
Test status
Simulation time 166069749 ps
CPU time 0.91 seconds
Started Jul 24 07:07:15 PM PDT 24
Finished Jul 24 07:07:16 PM PDT 24
Peak memory 199964 kb
Host smart-935e20e9-b248-43ee-9899-c3a4da47f74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922617922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1922617922
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.182275962
Short name T279
Test name
Test status
Simulation time 1627868265 ps
CPU time 6.52 seconds
Started Jul 24 07:07:13 PM PDT 24
Finished Jul 24 07:07:20 PM PDT 24
Peak memory 200240 kb
Host smart-d89cd9b2-2ada-486a-8cda-ab5223dfc137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182275962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.182275962
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3998162150
Short name T379
Test name
Test status
Simulation time 148690452 ps
CPU time 1.24 seconds
Started Jul 24 07:07:12 PM PDT 24
Finished Jul 24 07:07:14 PM PDT 24
Peak memory 200140 kb
Host smart-a140fc3b-698a-4f40-86dd-7e62407b52df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998162150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3998162150
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.578857218
Short name T287
Test name
Test status
Simulation time 197248249 ps
CPU time 1.35 seconds
Started Jul 24 07:07:13 PM PDT 24
Finished Jul 24 07:07:15 PM PDT 24
Peak memory 200292 kb
Host smart-e5050da3-2e8e-4430-b9a2-ed217d288f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578857218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.578857218
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1588579359
Short name T260
Test name
Test status
Simulation time 1320503354 ps
CPU time 5.81 seconds
Started Jul 24 07:07:13 PM PDT 24
Finished Jul 24 07:07:19 PM PDT 24
Peak memory 200320 kb
Host smart-f6a448d3-7006-4a0b-8b1c-e0c55ec0073b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588579359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1588579359
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3359491284
Short name T129
Test name
Test status
Simulation time 313663893 ps
CPU time 2.12 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:23 PM PDT 24
Peak memory 208376 kb
Host smart-b185ef31-d01d-4ff9-8362-8ef34765042e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359491284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3359491284
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1710469680
Short name T360
Test name
Test status
Simulation time 140533167 ps
CPU time 1.03 seconds
Started Jul 24 07:07:15 PM PDT 24
Finished Jul 24 07:07:16 PM PDT 24
Peak memory 200160 kb
Host smart-f57f5b9c-35d4-46a1-a5a5-a123dd70d051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710469680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1710469680
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2039340831
Short name T65
Test name
Test status
Simulation time 58035830 ps
CPU time 0.74 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 199916 kb
Host smart-e810feca-9890-4435-b592-10478c11895a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039340831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2039340831
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3461012535
Short name T26
Test name
Test status
Simulation time 1888336468 ps
CPU time 7.65 seconds
Started Jul 24 07:07:21 PM PDT 24
Finished Jul 24 07:07:29 PM PDT 24
Peak memory 221712 kb
Host smart-3051d1e3-452c-4609-a7fe-a9922bc3ccd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461012535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3461012535
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.909885914
Short name T197
Test name
Test status
Simulation time 243582659 ps
CPU time 1.19 seconds
Started Jul 24 07:07:12 PM PDT 24
Finished Jul 24 07:07:14 PM PDT 24
Peak memory 217528 kb
Host smart-c7799cf2-e904-4593-9fd7-e83dfdc3c0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909885914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.909885914
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3643684469
Short name T18
Test name
Test status
Simulation time 142413648 ps
CPU time 0.85 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 199916 kb
Host smart-baabfd1d-f3f1-4628-8ebf-89e1ce83281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643684469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3643684469
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1930010986
Short name T201
Test name
Test status
Simulation time 1077451543 ps
CPU time 4.58 seconds
Started Jul 24 07:07:14 PM PDT 24
Finished Jul 24 07:07:18 PM PDT 24
Peak memory 200448 kb
Host smart-098fd0c2-411d-4c8b-970e-8a1211883829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930010986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1930010986
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1847065247
Short name T153
Test name
Test status
Simulation time 170206638 ps
CPU time 1.21 seconds
Started Jul 24 07:07:12 PM PDT 24
Finished Jul 24 07:07:13 PM PDT 24
Peak memory 200164 kb
Host smart-f558be3b-4845-45f1-b05c-946404daeba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847065247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1847065247
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2389125298
Short name T509
Test name
Test status
Simulation time 232149770 ps
CPU time 1.55 seconds
Started Jul 24 07:07:16 PM PDT 24
Finished Jul 24 07:07:18 PM PDT 24
Peak memory 200340 kb
Host smart-73533f2a-989f-45e8-a88a-5b3087e42b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389125298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2389125298
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.4096851573
Short name T490
Test name
Test status
Simulation time 1538459370 ps
CPU time 6.75 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:27 PM PDT 24
Peak memory 200384 kb
Host smart-dccebd38-009c-4365-b556-826ff282ab56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096851573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.4096851573
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2563165733
Short name T394
Test name
Test status
Simulation time 262734687 ps
CPU time 1.95 seconds
Started Jul 24 07:07:14 PM PDT 24
Finished Jul 24 07:07:16 PM PDT 24
Peak memory 200116 kb
Host smart-c0ae705c-81af-4e0e-a2b7-895a5d087e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563165733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2563165733
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2019837643
Short name T376
Test name
Test status
Simulation time 226124416 ps
CPU time 1.38 seconds
Started Jul 24 07:07:13 PM PDT 24
Finished Jul 24 07:07:14 PM PDT 24
Peak memory 200320 kb
Host smart-2973efa2-9108-4cad-8a45-4ce5765a7a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019837643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2019837643
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1482180528
Short name T310
Test name
Test status
Simulation time 1908287546 ps
CPU time 6.69 seconds
Started Jul 24 07:07:12 PM PDT 24
Finished Jul 24 07:07:19 PM PDT 24
Peak memory 217588 kb
Host smart-18e97f60-c651-4af7-8a15-531f8c84e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482180528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1482180528
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1366626463
Short name T119
Test name
Test status
Simulation time 244064751 ps
CPU time 1.08 seconds
Started Jul 24 07:07:12 PM PDT 24
Finished Jul 24 07:07:13 PM PDT 24
Peak memory 217488 kb
Host smart-06b93ebe-37b4-4884-ba68-fb707770ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366626463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1366626463
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3457766381
Short name T526
Test name
Test status
Simulation time 227997644 ps
CPU time 1 seconds
Started Jul 24 07:07:31 PM PDT 24
Finished Jul 24 07:07:32 PM PDT 24
Peak memory 199948 kb
Host smart-7a80ed60-4c34-4c1e-8e1a-e16ebedec27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457766381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3457766381
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1255637147
Short name T284
Test name
Test status
Simulation time 1661127381 ps
CPU time 6.04 seconds
Started Jul 24 07:07:11 PM PDT 24
Finished Jul 24 07:07:18 PM PDT 24
Peak memory 200420 kb
Host smart-90fd130f-2e0a-4fb1-8849-965f9a4120f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255637147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1255637147
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2994332496
Short name T415
Test name
Test status
Simulation time 103648571 ps
CPU time 0.99 seconds
Started Jul 24 07:07:14 PM PDT 24
Finished Jul 24 07:07:15 PM PDT 24
Peak memory 200156 kb
Host smart-e690804f-a5d8-4856-8cdd-3e9a08c800e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994332496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2994332496
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1389220331
Short name T196
Test name
Test status
Simulation time 256495577 ps
CPU time 1.62 seconds
Started Jul 24 07:07:13 PM PDT 24
Finished Jul 24 07:07:15 PM PDT 24
Peak memory 200352 kb
Host smart-c2271dbf-877b-4523-b60e-1594e88a62e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389220331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1389220331
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1459118933
Short name T228
Test name
Test status
Simulation time 12840665988 ps
CPU time 46.82 seconds
Started Jul 24 07:07:30 PM PDT 24
Finished Jul 24 07:08:17 PM PDT 24
Peak memory 208676 kb
Host smart-f92c10aa-4e5b-4a53-a1e5-095c72c1d399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459118933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1459118933
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.828078577
Short name T521
Test name
Test status
Simulation time 390362491 ps
CPU time 2.25 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:23 PM PDT 24
Peak memory 200120 kb
Host smart-7982e111-991e-472c-b062-e44d4b61275f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828078577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.828078577
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3861343415
Short name T352
Test name
Test status
Simulation time 101620124 ps
CPU time 0.95 seconds
Started Jul 24 07:07:14 PM PDT 24
Finished Jul 24 07:07:16 PM PDT 24
Peak memory 200164 kb
Host smart-646d6e4b-2dc6-41fe-a4ac-296249c27e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861343415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3861343415
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2747423382
Short name T263
Test name
Test status
Simulation time 80372182 ps
CPU time 0.9 seconds
Started Jul 24 07:07:21 PM PDT 24
Finished Jul 24 07:07:22 PM PDT 24
Peak memory 199916 kb
Host smart-f9ffb4d2-5e85-49ec-b7ea-a02af8122597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747423382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2747423382
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2427577430
Short name T45
Test name
Test status
Simulation time 1886554660 ps
CPU time 8.18 seconds
Started Jul 24 07:07:23 PM PDT 24
Finished Jul 24 07:07:31 PM PDT 24
Peak memory 229864 kb
Host smart-013b4404-2692-41c6-9065-19c69a95cd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427577430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2427577430
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3133802403
Short name T276
Test name
Test status
Simulation time 244115787 ps
CPU time 1.14 seconds
Started Jul 24 07:07:28 PM PDT 24
Finished Jul 24 07:07:30 PM PDT 24
Peak memory 217484 kb
Host smart-451869a2-4efb-443b-8c84-09fd0be284e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133802403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3133802403
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.784118594
Short name T390
Test name
Test status
Simulation time 206122681 ps
CPU time 0.95 seconds
Started Jul 24 07:07:14 PM PDT 24
Finished Jul 24 07:07:15 PM PDT 24
Peak memory 199960 kb
Host smart-3363f845-24af-4c2e-99d4-8dcff4e9cdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784118594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.784118594
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2630976240
Short name T441
Test name
Test status
Simulation time 1477664546 ps
CPU time 5.65 seconds
Started Jul 24 07:07:13 PM PDT 24
Finished Jul 24 07:07:19 PM PDT 24
Peak memory 200460 kb
Host smart-4f7d8bec-06a0-4886-838d-c4df7b558ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630976240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2630976240
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2171002682
Short name T440
Test name
Test status
Simulation time 173654536 ps
CPU time 1.24 seconds
Started Jul 24 07:07:23 PM PDT 24
Finished Jul 24 07:07:24 PM PDT 24
Peak memory 200184 kb
Host smart-3cb05149-75c8-4581-a7b6-1a6ad18e80ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171002682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2171002682
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2482525492
Short name T332
Test name
Test status
Simulation time 118831017 ps
CPU time 1.26 seconds
Started Jul 24 07:07:15 PM PDT 24
Finished Jul 24 07:07:16 PM PDT 24
Peak memory 200340 kb
Host smart-2c7170cf-efdf-4002-a19f-52c9e4dea880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482525492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2482525492
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2566210948
Short name T484
Test name
Test status
Simulation time 1914720357 ps
CPU time 9.23 seconds
Started Jul 24 07:07:19 PM PDT 24
Finished Jul 24 07:07:29 PM PDT 24
Peak memory 200448 kb
Host smart-442c2057-db06-4f70-9134-a5937723c5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566210948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2566210948
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1773422670
Short name T426
Test name
Test status
Simulation time 147574006 ps
CPU time 1.77 seconds
Started Jul 24 07:07:11 PM PDT 24
Finished Jul 24 07:07:14 PM PDT 24
Peak memory 200080 kb
Host smart-6f13d0e7-a9cf-4ed2-9754-8eedc58d5e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773422670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1773422670
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2242640891
Short name T123
Test name
Test status
Simulation time 99912161 ps
CPU time 0.92 seconds
Started Jul 24 07:07:14 PM PDT 24
Finished Jul 24 07:07:15 PM PDT 24
Peak memory 200140 kb
Host smart-a267fdef-ba58-4909-b557-6298f1d210c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242640891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2242640891
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3064115239
Short name T270
Test name
Test status
Simulation time 69399897 ps
CPU time 0.76 seconds
Started Jul 24 07:06:33 PM PDT 24
Finished Jul 24 07:06:34 PM PDT 24
Peak memory 199960 kb
Host smart-5c00baca-9ec2-4a74-a2a7-a3970f1ae985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064115239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3064115239
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.309195243
Short name T368
Test name
Test status
Simulation time 2369726113 ps
CPU time 8.54 seconds
Started Jul 24 07:06:42 PM PDT 24
Finished Jul 24 07:06:51 PM PDT 24
Peak memory 217808 kb
Host smart-2acc7b66-53a8-46a3-b0ef-9d6c77df1045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309195243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.309195243
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3777870665
Short name T472
Test name
Test status
Simulation time 243535957 ps
CPU time 1.07 seconds
Started Jul 24 07:06:35 PM PDT 24
Finished Jul 24 07:06:36 PM PDT 24
Peak memory 217528 kb
Host smart-c4a98456-db66-4104-bba5-1bb6c42090d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777870665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3777870665
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.325241962
Short name T528
Test name
Test status
Simulation time 95360157 ps
CPU time 0.75 seconds
Started Jul 24 07:06:36 PM PDT 24
Finished Jul 24 07:06:37 PM PDT 24
Peak memory 199876 kb
Host smart-9ce4e888-007e-436f-9c3d-078befde259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325241962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.325241962
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.4144791650
Short name T295
Test name
Test status
Simulation time 2101169614 ps
CPU time 7.69 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:42 PM PDT 24
Peak memory 200488 kb
Host smart-41997d79-784e-4037-b167-6e025440175e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144791650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4144791650
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1534739777
Short name T35
Test name
Test status
Simulation time 101829063 ps
CPU time 1.02 seconds
Started Jul 24 07:06:33 PM PDT 24
Finished Jul 24 07:06:34 PM PDT 24
Peak memory 200156 kb
Host smart-5474cf50-8aa8-4bf7-b37c-4434b0aaf4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534739777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1534739777
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.957397817
Short name T343
Test name
Test status
Simulation time 193322279 ps
CPU time 1.44 seconds
Started Jul 24 07:06:37 PM PDT 24
Finished Jul 24 07:06:39 PM PDT 24
Peak memory 200340 kb
Host smart-a8d8428b-6b69-44cc-a4ff-52dbc2b96278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957397817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.957397817
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1778465491
Short name T111
Test name
Test status
Simulation time 8097142929 ps
CPU time 30.07 seconds
Started Jul 24 07:06:33 PM PDT 24
Finished Jul 24 07:07:04 PM PDT 24
Peak memory 216688 kb
Host smart-915e61ff-555c-4551-9516-5e5e4cb1d551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778465491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1778465491
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.196487366
Short name T203
Test name
Test status
Simulation time 246208538 ps
CPU time 1.8 seconds
Started Jul 24 07:06:37 PM PDT 24
Finished Jul 24 07:06:39 PM PDT 24
Peak memory 200136 kb
Host smart-bdfcabda-b391-4427-9edf-5664597d7a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196487366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.196487366
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3228302189
Short name T316
Test name
Test status
Simulation time 171457764 ps
CPU time 1.37 seconds
Started Jul 24 07:06:37 PM PDT 24
Finished Jul 24 07:06:39 PM PDT 24
Peak memory 200400 kb
Host smart-5471bf1c-7ffa-4b2f-bd55-ca2eea60ca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228302189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3228302189
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.595824198
Short name T385
Test name
Test status
Simulation time 70166327 ps
CPU time 0.83 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 199916 kb
Host smart-44544488-24ec-4f99-90e6-74a4db949bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595824198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.595824198
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.437526500
Short name T449
Test name
Test status
Simulation time 1873583381 ps
CPU time 6.92 seconds
Started Jul 24 07:07:22 PM PDT 24
Finished Jul 24 07:07:29 PM PDT 24
Peak memory 221324 kb
Host smart-2f0781b0-b7b8-4ef6-9ec9-e0842e1dc810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437526500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.437526500
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1476600770
Short name T384
Test name
Test status
Simulation time 245491129 ps
CPU time 1.05 seconds
Started Jul 24 07:07:18 PM PDT 24
Finished Jul 24 07:07:19 PM PDT 24
Peak memory 217512 kb
Host smart-5dd9120f-0c93-455c-abdb-108bc081d57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476600770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1476600770
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2368532797
Short name T1
Test name
Test status
Simulation time 85658402 ps
CPU time 0.76 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 199892 kb
Host smart-9ce60c7c-6d44-4a85-8d4d-51c01af28ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368532797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2368532797
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2912483054
Short name T207
Test name
Test status
Simulation time 774917663 ps
CPU time 3.96 seconds
Started Jul 24 07:07:21 PM PDT 24
Finished Jul 24 07:07:25 PM PDT 24
Peak memory 200472 kb
Host smart-74d90dcc-cfd1-4979-a193-2d3010620ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912483054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2912483054
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1578021279
Short name T518
Test name
Test status
Simulation time 170279985 ps
CPU time 1.2 seconds
Started Jul 24 07:07:28 PM PDT 24
Finished Jul 24 07:07:30 PM PDT 24
Peak memory 200144 kb
Host smart-2f0b64f8-181a-470f-a218-fa1bc9b0474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578021279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1578021279
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2050299625
Short name T268
Test name
Test status
Simulation time 231283692 ps
CPU time 1.55 seconds
Started Jul 24 07:07:25 PM PDT 24
Finished Jul 24 07:07:27 PM PDT 24
Peak memory 200300 kb
Host smart-2bd10b4a-4f69-491f-a0fb-175f432ed725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050299625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2050299625
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1701009015
Short name T456
Test name
Test status
Simulation time 1626262128 ps
CPU time 6.84 seconds
Started Jul 24 07:07:22 PM PDT 24
Finished Jul 24 07:07:29 PM PDT 24
Peak memory 200396 kb
Host smart-e5fe0f87-778e-4ac2-829a-8bfa8a819306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701009015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1701009015
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4091550818
Short name T297
Test name
Test status
Simulation time 309946632 ps
CPU time 2.09 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:23 PM PDT 24
Peak memory 208316 kb
Host smart-68d31674-74b8-4214-8e02-5fc7b7d7151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091550818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4091550818
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3102319115
Short name T38
Test name
Test status
Simulation time 252832573 ps
CPU time 1.48 seconds
Started Jul 24 07:07:23 PM PDT 24
Finished Jul 24 07:07:25 PM PDT 24
Peak memory 200152 kb
Host smart-f3713d55-e089-40ba-bbdd-208a73c81581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102319115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3102319115
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3948123082
Short name T377
Test name
Test status
Simulation time 65234092 ps
CPU time 0.81 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 199916 kb
Host smart-ccb81bf0-205c-476b-944b-712fcdd39085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948123082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3948123082
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2777939077
Short name T519
Test name
Test status
Simulation time 1887134577 ps
CPU time 7.17 seconds
Started Jul 24 07:07:19 PM PDT 24
Finished Jul 24 07:07:27 PM PDT 24
Peak memory 221764 kb
Host smart-55d14919-c04f-435b-a5b2-6469e6af0b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777939077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2777939077
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3327957663
Short name T189
Test name
Test status
Simulation time 245166646 ps
CPU time 1.12 seconds
Started Jul 24 07:07:25 PM PDT 24
Finished Jul 24 07:07:26 PM PDT 24
Peak memory 217428 kb
Host smart-4b0c721c-eed2-4b0f-b47e-b731aaf36d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327957663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3327957663
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3003958800
Short name T172
Test name
Test status
Simulation time 188285750 ps
CPU time 0.93 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:22 PM PDT 24
Peak memory 199952 kb
Host smart-5862e2a7-6e0e-4da8-a9f5-91b025538b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003958800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3003958800
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1579780210
Short name T420
Test name
Test status
Simulation time 2068963361 ps
CPU time 8.5 seconds
Started Jul 24 07:07:25 PM PDT 24
Finished Jul 24 07:07:34 PM PDT 24
Peak memory 200364 kb
Host smart-0236097c-3158-4778-9547-091f6477e4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579780210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1579780210
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3166999184
Short name T525
Test name
Test status
Simulation time 142904038 ps
CPU time 1.11 seconds
Started Jul 24 07:07:21 PM PDT 24
Finished Jul 24 07:07:22 PM PDT 24
Peak memory 200152 kb
Host smart-c71612bf-194f-42e7-8bf9-c6434c99b1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166999184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3166999184
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.876791620
Short name T216
Test name
Test status
Simulation time 121490969 ps
CPU time 1.22 seconds
Started Jul 24 07:07:21 PM PDT 24
Finished Jul 24 07:07:22 PM PDT 24
Peak memory 200372 kb
Host smart-a142451b-6de6-459b-9145-7d5309bbd831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876791620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.876791620
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2880053471
Short name T337
Test name
Test status
Simulation time 10592446266 ps
CPU time 41.41 seconds
Started Jul 24 07:07:22 PM PDT 24
Finished Jul 24 07:08:04 PM PDT 24
Peak memory 208632 kb
Host smart-612d59bd-99ec-462c-b6c5-f35fa05e6176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880053471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2880053471
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.957776456
Short name T113
Test name
Test status
Simulation time 396288275 ps
CPU time 2.14 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:07:39 PM PDT 24
Peak memory 200132 kb
Host smart-02e0884f-67dd-43b9-ac6a-ac1bf3209b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957776456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.957776456
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1015801825
Short name T169
Test name
Test status
Simulation time 220113350 ps
CPU time 1.48 seconds
Started Jul 24 07:07:19 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 200116 kb
Host smart-336ac020-74fd-4ca6-b4fe-995c8390d185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015801825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1015801825
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3873949526
Short name T473
Test name
Test status
Simulation time 59407046 ps
CPU time 0.72 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 199968 kb
Host smart-715af283-23ec-4b5f-b965-48c36dffe380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873949526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3873949526
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2759095693
Short name T290
Test name
Test status
Simulation time 1883510088 ps
CPU time 7.48 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:28 PM PDT 24
Peak memory 221336 kb
Host smart-70c13197-fa11-4102-a3bc-f2e710f23694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759095693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2759095693
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4076303401
Short name T364
Test name
Test status
Simulation time 244317936 ps
CPU time 1.09 seconds
Started Jul 24 07:07:23 PM PDT 24
Finished Jul 24 07:07:24 PM PDT 24
Peak memory 217580 kb
Host smart-1b2a0e4d-44c7-4e24-a143-b65fb0ed90cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076303401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4076303401
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2800855861
Short name T204
Test name
Test status
Simulation time 115739550 ps
CPU time 0.78 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:22 PM PDT 24
Peak memory 199952 kb
Host smart-44c8534a-256f-4e99-a680-7e81645ff13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800855861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2800855861
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2264254024
Short name T213
Test name
Test status
Simulation time 1258372083 ps
CPU time 5.41 seconds
Started Jul 24 07:07:23 PM PDT 24
Finished Jul 24 07:07:29 PM PDT 24
Peak memory 200280 kb
Host smart-8c31e291-e0a6-425c-b1d1-ab9d23e65b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264254024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2264254024
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3700774207
Short name T313
Test name
Test status
Simulation time 97995685 ps
CPU time 1.05 seconds
Started Jul 24 07:07:23 PM PDT 24
Finished Jul 24 07:07:24 PM PDT 24
Peak memory 200008 kb
Host smart-7f9f2d02-6358-452e-9b72-18bf19c59d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700774207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3700774207
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.627699846
Short name T333
Test name
Test status
Simulation time 189706107 ps
CPU time 1.43 seconds
Started Jul 24 07:07:19 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 200312 kb
Host smart-29b7e4d1-c15e-479f-adba-cd105d6ebeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627699846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.627699846
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.4011648454
Short name T11
Test name
Test status
Simulation time 15112773704 ps
CPU time 52.91 seconds
Started Jul 24 07:07:21 PM PDT 24
Finished Jul 24 07:08:14 PM PDT 24
Peak memory 216868 kb
Host smart-e1ac3cda-507b-4ef5-8f6c-998d5e4ee598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011648454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.4011648454
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.376721645
Short name T127
Test name
Test status
Simulation time 133570230 ps
CPU time 1.59 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 208368 kb
Host smart-aa5f95d0-17c4-4902-b769-214083487030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376721645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.376721645
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2773925363
Short name T185
Test name
Test status
Simulation time 164581480 ps
CPU time 1.15 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 200156 kb
Host smart-ce79ef1a-fc93-49f0-974a-1cc8ba5a95f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773925363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2773925363
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1376287042
Short name T439
Test name
Test status
Simulation time 78530563 ps
CPU time 0.81 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 199972 kb
Host smart-ba804e83-9671-4503-99de-2f892f0afc82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376287042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1376287042
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3067048342
Short name T344
Test name
Test status
Simulation time 1232206476 ps
CPU time 5.47 seconds
Started Jul 24 07:07:23 PM PDT 24
Finished Jul 24 07:07:29 PM PDT 24
Peak memory 217812 kb
Host smart-f55d3fee-f8af-495e-9d7c-bc2a4f32f530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067048342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3067048342
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.807494733
Short name T408
Test name
Test status
Simulation time 244705141 ps
CPU time 1.07 seconds
Started Jul 24 07:07:18 PM PDT 24
Finished Jul 24 07:07:19 PM PDT 24
Peak memory 217400 kb
Host smart-d0e5b891-65ee-4518-9c46-883112fb0961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807494733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.807494733
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.299434544
Short name T274
Test name
Test status
Simulation time 105731558 ps
CPU time 0.8 seconds
Started Jul 24 07:07:21 PM PDT 24
Finished Jul 24 07:07:22 PM PDT 24
Peak memory 199956 kb
Host smart-621a180b-baf6-4e9b-9758-e6da5de809d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299434544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.299434544
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1457633917
Short name T517
Test name
Test status
Simulation time 748581806 ps
CPU time 4 seconds
Started Jul 24 07:07:27 PM PDT 24
Finished Jul 24 07:07:31 PM PDT 24
Peak memory 200352 kb
Host smart-67a2ef71-83e9-446b-987c-82839a7370b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457633917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1457633917
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.455830206
Short name T210
Test name
Test status
Simulation time 190496943 ps
CPU time 1.3 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:22 PM PDT 24
Peak memory 200136 kb
Host smart-08ab9660-07ec-43ee-be89-6dceced2d955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455830206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.455830206
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1930145190
Short name T479
Test name
Test status
Simulation time 253417532 ps
CPU time 1.59 seconds
Started Jul 24 07:07:19 PM PDT 24
Finished Jul 24 07:07:20 PM PDT 24
Peak memory 200312 kb
Host smart-4e0690a3-e4db-4524-b62a-73c48700c32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930145190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1930145190
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.841608701
Short name T265
Test name
Test status
Simulation time 7995475259 ps
CPU time 37.54 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:59 PM PDT 24
Peak memory 208732 kb
Host smart-b099d25c-b124-4f88-bc76-253a531497b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841608701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.841608701
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.4183494770
Short name T522
Test name
Test status
Simulation time 121897303 ps
CPU time 1.56 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:21 PM PDT 24
Peak memory 208336 kb
Host smart-4c9c3fa1-5e0f-464c-9134-9406b94228be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183494770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.4183494770
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1298468741
Short name T487
Test name
Test status
Simulation time 210564351 ps
CPU time 1.29 seconds
Started Jul 24 07:07:23 PM PDT 24
Finished Jul 24 07:07:24 PM PDT 24
Peak memory 200148 kb
Host smart-e0eb28c6-93cf-4fd0-a7e1-9c996a320693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298468741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1298468741
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2512239788
Short name T321
Test name
Test status
Simulation time 164607507 ps
CPU time 0.96 seconds
Started Jul 24 07:07:28 PM PDT 24
Finished Jul 24 07:07:29 PM PDT 24
Peak memory 199960 kb
Host smart-6b600471-325f-4390-9a6c-ca99d4965436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512239788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2512239788
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1303227856
Short name T409
Test name
Test status
Simulation time 1228876346 ps
CPU time 5.92 seconds
Started Jul 24 07:07:29 PM PDT 24
Finished Jul 24 07:07:36 PM PDT 24
Peak memory 217844 kb
Host smart-2e2b0f61-7bcf-4e4a-bbf3-f305d102ea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303227856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1303227856
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3206162243
Short name T8
Test name
Test status
Simulation time 244239349 ps
CPU time 1.05 seconds
Started Jul 24 07:07:33 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 217556 kb
Host smart-5be3883d-0b71-4d16-80e5-ef326cb2e16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206162243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3206162243
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1392422398
Short name T402
Test name
Test status
Simulation time 189193997 ps
CPU time 0.95 seconds
Started Jul 24 07:07:23 PM PDT 24
Finished Jul 24 07:07:24 PM PDT 24
Peak memory 199824 kb
Host smart-5a049a51-255f-4e03-9791-1a3530feaa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392422398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1392422398
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3510705784
Short name T443
Test name
Test status
Simulation time 925710933 ps
CPU time 4.89 seconds
Started Jul 24 07:07:23 PM PDT 24
Finished Jul 24 07:07:28 PM PDT 24
Peak memory 200448 kb
Host smart-544686a6-fb09-42b9-b08a-96bebf57e4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510705784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3510705784
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1626210108
Short name T149
Test name
Test status
Simulation time 148081860 ps
CPU time 1.15 seconds
Started Jul 24 07:07:38 PM PDT 24
Finished Jul 24 07:07:39 PM PDT 24
Peak memory 200156 kb
Host smart-eb9cb511-0f43-4a39-b9e6-64615937d9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626210108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1626210108
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2223910858
Short name T184
Test name
Test status
Simulation time 111356165 ps
CPU time 1.27 seconds
Started Jul 24 07:07:20 PM PDT 24
Finished Jul 24 07:07:22 PM PDT 24
Peak memory 200368 kb
Host smart-53b281b4-0afc-4f2b-9fad-8f15afb5e7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223910858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2223910858
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2264610524
Short name T383
Test name
Test status
Simulation time 1314747383 ps
CPU time 6.46 seconds
Started Jul 24 07:07:25 PM PDT 24
Finished Jul 24 07:07:32 PM PDT 24
Peak memory 208616 kb
Host smart-12ecb11f-c2e4-44e4-835d-cab0fd810cba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264610524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2264610524
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2453349640
Short name T126
Test name
Test status
Simulation time 123666569 ps
CPU time 1.57 seconds
Started Jul 24 07:07:33 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 208364 kb
Host smart-57d12768-9cc2-4435-8a50-9c43d001619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453349640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2453349640
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.767323883
Short name T350
Test name
Test status
Simulation time 100656090 ps
CPU time 0.88 seconds
Started Jul 24 07:07:29 PM PDT 24
Finished Jul 24 07:07:30 PM PDT 24
Peak memory 200132 kb
Host smart-778b1726-0443-4f14-b2f3-7f6430933803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767323883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.767323883
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3113303320
Short name T418
Test name
Test status
Simulation time 67277916 ps
CPU time 0.72 seconds
Started Jul 24 07:07:32 PM PDT 24
Finished Jul 24 07:07:33 PM PDT 24
Peak memory 199940 kb
Host smart-1c7e60fd-cd4b-4cfc-83eb-0dd4c42cb6a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113303320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3113303320
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3821372138
Short name T374
Test name
Test status
Simulation time 1890917112 ps
CPU time 7.38 seconds
Started Jul 24 07:07:27 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 217520 kb
Host smart-9a8467b9-f3ab-42da-9ee1-84b08350969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821372138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3821372138
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2835209420
Short name T224
Test name
Test status
Simulation time 243940872 ps
CPU time 1.19 seconds
Started Jul 24 07:07:33 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 217484 kb
Host smart-b4fcb714-7915-4489-b6e9-0a69ece41ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835209420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2835209420
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1510727475
Short name T254
Test name
Test status
Simulation time 152731877 ps
CPU time 0.89 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 199980 kb
Host smart-6443ec71-757a-45ad-bbb5-cccc1f390d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510727475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1510727475
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1427908562
Short name T442
Test name
Test status
Simulation time 681871824 ps
CPU time 3.6 seconds
Started Jul 24 07:07:33 PM PDT 24
Finished Jul 24 07:07:36 PM PDT 24
Peak memory 200328 kb
Host smart-7a7e5ba4-4469-4301-ad3a-a4f8ec7e57d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427908562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1427908562
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.47472493
Short name T257
Test name
Test status
Simulation time 155826842 ps
CPU time 1.12 seconds
Started Jul 24 07:07:32 PM PDT 24
Finished Jul 24 07:07:34 PM PDT 24
Peak memory 200044 kb
Host smart-fae5d7ce-640d-4401-9e96-911416202067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47472493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.47472493
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.962503906
Short name T494
Test name
Test status
Simulation time 227413345 ps
CPU time 1.46 seconds
Started Jul 24 07:07:53 PM PDT 24
Finished Jul 24 07:07:55 PM PDT 24
Peak memory 200324 kb
Host smart-a1e4dfdf-3db8-463f-86bd-015522b19694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962503906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.962503906
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3552665522
Short name T357
Test name
Test status
Simulation time 5885699095 ps
CPU time 26.92 seconds
Started Jul 24 07:07:28 PM PDT 24
Finished Jul 24 07:07:55 PM PDT 24
Peak memory 200520 kb
Host smart-d4726aca-9cc9-45fa-b218-6f47cff0b862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552665522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3552665522
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.7834142
Short name T72
Test name
Test status
Simulation time 317744693 ps
CPU time 2.02 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:07:38 PM PDT 24
Peak memory 200108 kb
Host smart-03f2ef77-ce1e-40b9-b5da-d0d09ab7b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7834142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.7834142
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.367419722
Short name T114
Test name
Test status
Simulation time 261373089 ps
CPU time 1.48 seconds
Started Jul 24 07:07:28 PM PDT 24
Finished Jul 24 07:07:29 PM PDT 24
Peak memory 200140 kb
Host smart-510283e6-0812-40a0-98df-26b0cb67482a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367419722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.367419722
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.983964180
Short name T348
Test name
Test status
Simulation time 66124561 ps
CPU time 0.81 seconds
Started Jul 24 07:07:53 PM PDT 24
Finished Jul 24 07:07:54 PM PDT 24
Peak memory 199928 kb
Host smart-c542d3d5-c55c-4830-8bc5-7dd7258b276b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983964180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.983964180
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3916727657
Short name T533
Test name
Test status
Simulation time 1888459990 ps
CPU time 7.89 seconds
Started Jul 24 07:07:26 PM PDT 24
Finished Jul 24 07:07:34 PM PDT 24
Peak memory 217396 kb
Host smart-1cb30ce7-2c97-4619-9ca0-12897704ce08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916727657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3916727657
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2767505488
Short name T70
Test name
Test status
Simulation time 243451285 ps
CPU time 1.15 seconds
Started Jul 24 07:07:28 PM PDT 24
Finished Jul 24 07:07:29 PM PDT 24
Peak memory 217500 kb
Host smart-9ff4dc8f-2790-4ab8-bda9-f13846b2a9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767505488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2767505488
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.859151334
Short name T381
Test name
Test status
Simulation time 173737800 ps
CPU time 0.85 seconds
Started Jul 24 07:07:29 PM PDT 24
Finished Jul 24 07:07:31 PM PDT 24
Peak memory 199940 kb
Host smart-5e8d8bd2-a8dc-42c2-96d1-71d2101a415c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859151334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.859151334
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3705123238
Short name T346
Test name
Test status
Simulation time 1339507708 ps
CPU time 6.01 seconds
Started Jul 24 07:07:53 PM PDT 24
Finished Jul 24 07:07:59 PM PDT 24
Peak memory 200436 kb
Host smart-0f1cc59a-53bd-46f7-941a-6e8dfe7a3ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705123238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3705123238
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1329930126
Short name T436
Test name
Test status
Simulation time 174901905 ps
CPU time 1.36 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:07:38 PM PDT 24
Peak memory 200316 kb
Host smart-543d199c-194d-44bf-bab4-1e006f93f4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329930126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1329930126
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3573353164
Short name T182
Test name
Test status
Simulation time 198613940 ps
CPU time 1.57 seconds
Started Jul 24 07:07:33 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 200328 kb
Host smart-5a6e85ec-8a77-4a78-a48e-cb3e91ed9204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573353164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3573353164
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.4207620266
Short name T398
Test name
Test status
Simulation time 6803500677 ps
CPU time 30.33 seconds
Started Jul 24 07:07:26 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 208696 kb
Host smart-1f1eedde-8bb3-4b49-8256-71a1c5c9bbc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207620266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.4207620266
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.241665412
Short name T6
Test name
Test status
Simulation time 133166617 ps
CPU time 1.62 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:36 PM PDT 24
Peak memory 208360 kb
Host smart-cf19a82d-913f-433e-a20a-d84d905a067d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241665412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.241665412
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3417064204
Short name T272
Test name
Test status
Simulation time 307199146 ps
CPU time 1.74 seconds
Started Jul 24 07:07:27 PM PDT 24
Finished Jul 24 07:07:28 PM PDT 24
Peak memory 200360 kb
Host smart-81650e51-6ada-4f1d-ac9c-dbf6d8fbf20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417064204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3417064204
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.739660884
Short name T465
Test name
Test status
Simulation time 79332746 ps
CPU time 0.87 seconds
Started Jul 24 07:07:35 PM PDT 24
Finished Jul 24 07:07:36 PM PDT 24
Peak memory 199924 kb
Host smart-9b9d580b-cf5c-447b-912e-f8162a4a5a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739660884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.739660884
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2908339235
Short name T46
Test name
Test status
Simulation time 1232756609 ps
CPU time 5.46 seconds
Started Jul 24 07:07:32 PM PDT 24
Finished Jul 24 07:07:38 PM PDT 24
Peak memory 217620 kb
Host smart-4007dd3d-fd54-44f0-9df1-bf15d83273b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908339235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2908339235
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4036031591
Short name T396
Test name
Test status
Simulation time 244701463 ps
CPU time 1.06 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 217384 kb
Host smart-caa6560a-9d28-48c3-a66f-a79dbc33d286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036031591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4036031591
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.590014373
Short name T282
Test name
Test status
Simulation time 101331130 ps
CPU time 0.8 seconds
Started Jul 24 07:07:33 PM PDT 24
Finished Jul 24 07:07:34 PM PDT 24
Peak memory 199976 kb
Host smart-6d84e169-d4f6-4398-a346-7f42bbde17d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590014373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.590014373
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.4024801500
Short name T91
Test name
Test status
Simulation time 885157766 ps
CPU time 4.12 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:07:41 PM PDT 24
Peak memory 200456 kb
Host smart-1ea9d947-f1a8-4e7f-9c67-0801077bf00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024801500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.4024801500
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3414268477
Short name T166
Test name
Test status
Simulation time 144866494 ps
CPU time 1.09 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 200148 kb
Host smart-2f06b667-7eeb-4d5a-904b-fc5781ee4059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414268477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3414268477
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.891968244
Short name T164
Test name
Test status
Simulation time 120245721 ps
CPU time 1.2 seconds
Started Jul 24 07:07:27 PM PDT 24
Finished Jul 24 07:07:28 PM PDT 24
Peak memory 200360 kb
Host smart-ed22611c-07ea-4d53-93f6-d2b53b796ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891968244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.891968244
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1129647207
Short name T538
Test name
Test status
Simulation time 15585187440 ps
CPU time 55.61 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:08:32 PM PDT 24
Peak memory 208648 kb
Host smart-23a6c15f-ec35-4f91-b384-4e1a044af31c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129647207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1129647207
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1504067343
Short name T471
Test name
Test status
Simulation time 152243331 ps
CPU time 1.98 seconds
Started Jul 24 07:07:29 PM PDT 24
Finished Jul 24 07:07:32 PM PDT 24
Peak memory 200188 kb
Host smart-a4c403c9-afa5-4564-8a5b-ffb1238228f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504067343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1504067343
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1016129358
Short name T421
Test name
Test status
Simulation time 105527059 ps
CPU time 0.92 seconds
Started Jul 24 07:07:27 PM PDT 24
Finished Jul 24 07:07:28 PM PDT 24
Peak memory 200152 kb
Host smart-61c400d5-b73c-48cf-a666-75a02a7f9dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016129358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1016129358
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3827488933
Short name T191
Test name
Test status
Simulation time 96863651 ps
CPU time 0.87 seconds
Started Jul 24 07:07:37 PM PDT 24
Finished Jul 24 07:07:38 PM PDT 24
Peak memory 199884 kb
Host smart-bd1a648f-ea5e-44a0-b75e-c9debc8a4f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827488933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3827488933
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.774703080
Short name T505
Test name
Test status
Simulation time 1891222185 ps
CPU time 8.01 seconds
Started Jul 24 07:07:39 PM PDT 24
Finished Jul 24 07:07:47 PM PDT 24
Peak memory 221816 kb
Host smart-fd984b3b-25fb-4679-aea7-ad2ed813ffd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774703080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.774703080
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.386245586
Short name T244
Test name
Test status
Simulation time 244663613 ps
CPU time 1.03 seconds
Started Jul 24 07:07:39 PM PDT 24
Finished Jul 24 07:07:40 PM PDT 24
Peak memory 217492 kb
Host smart-e679d033-c15f-48a9-a4b2-aea295bb540f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386245586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.386245586
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1772885128
Short name T535
Test name
Test status
Simulation time 90789645 ps
CPU time 0.76 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 199992 kb
Host smart-f80cce0a-eda8-4d53-9b68-db4d3532a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772885128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1772885128
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2786299550
Short name T291
Test name
Test status
Simulation time 1804289998 ps
CPU time 7.55 seconds
Started Jul 24 07:07:40 PM PDT 24
Finished Jul 24 07:07:48 PM PDT 24
Peak memory 200448 kb
Host smart-48ec9b89-0fe9-44e7-963d-779e5d6dccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786299550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2786299550
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.735463414
Short name T51
Test name
Test status
Simulation time 150163562 ps
CPU time 1.16 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 200156 kb
Host smart-a101c213-87cc-4acf-bb46-bc29f1d7b5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735463414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.735463414
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.635705035
Short name T264
Test name
Test status
Simulation time 108446402 ps
CPU time 1.24 seconds
Started Jul 24 07:07:40 PM PDT 24
Finished Jul 24 07:07:41 PM PDT 24
Peak memory 200388 kb
Host smart-3da80596-fad2-4c2e-aff5-8b0ff0b8a263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635705035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.635705035
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.4207474964
Short name T255
Test name
Test status
Simulation time 144949895 ps
CPU time 1.86 seconds
Started Jul 24 07:07:38 PM PDT 24
Finished Jul 24 07:07:40 PM PDT 24
Peak memory 200148 kb
Host smart-b941bd49-7af4-4837-a805-2466954928de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207474964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4207474964
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2821225650
Short name T434
Test name
Test status
Simulation time 129411548 ps
CPU time 1.06 seconds
Started Jul 24 07:07:41 PM PDT 24
Finished Jul 24 07:07:42 PM PDT 24
Peak memory 200320 kb
Host smart-13559565-2b51-4198-b8d1-c593564d85bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821225650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2821225650
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1681489469
Short name T387
Test name
Test status
Simulation time 65901766 ps
CPU time 0.77 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:07:37 PM PDT 24
Peak memory 199920 kb
Host smart-11d9774e-a7d9-43b3-804d-2fb6406bede4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681489469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1681489469
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1421416780
Short name T289
Test name
Test status
Simulation time 1906964223 ps
CPU time 7.54 seconds
Started Jul 24 07:07:33 PM PDT 24
Finished Jul 24 07:07:41 PM PDT 24
Peak memory 221728 kb
Host smart-4165d3f8-3803-4434-8857-9d161a836bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421416780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1421416780
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3891857839
Short name T62
Test name
Test status
Simulation time 243898013 ps
CPU time 1.1 seconds
Started Jul 24 07:07:38 PM PDT 24
Finished Jul 24 07:07:39 PM PDT 24
Peak memory 217508 kb
Host smart-202c77f2-1a06-486e-8c81-f7d7438511b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891857839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3891857839
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1696665849
Short name T451
Test name
Test status
Simulation time 75277861 ps
CPU time 0.72 seconds
Started Jul 24 07:07:40 PM PDT 24
Finished Jul 24 07:07:41 PM PDT 24
Peak memory 199960 kb
Host smart-3318f673-b23c-47b0-97d0-c983c5816d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696665849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1696665849
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.816591789
Short name T248
Test name
Test status
Simulation time 1030173874 ps
CPU time 5.24 seconds
Started Jul 24 07:07:35 PM PDT 24
Finished Jul 24 07:07:40 PM PDT 24
Peak memory 200400 kb
Host smart-7f13d2b8-ee1b-4190-8637-62d748fe719b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816591789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.816591789
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.705273600
Short name T134
Test name
Test status
Simulation time 152123959 ps
CPU time 1.08 seconds
Started Jul 24 07:07:33 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 200168 kb
Host smart-a9635398-c56a-4dd8-ab7e-933f2f2514fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705273600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.705273600
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3934807266
Short name T433
Test name
Test status
Simulation time 246819577 ps
CPU time 1.5 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:07:38 PM PDT 24
Peak memory 200252 kb
Host smart-8a615d4a-b903-4d42-b849-cc64f89ad868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934807266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3934807266
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1672231516
Short name T209
Test name
Test status
Simulation time 3038022668 ps
CPU time 13.68 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:07:50 PM PDT 24
Peak memory 208632 kb
Host smart-99b08ef9-0994-44f2-ae19-ef7bfcb7f487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672231516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1672231516
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1831981505
Short name T267
Test name
Test status
Simulation time 339528794 ps
CPU time 2.08 seconds
Started Jul 24 07:07:39 PM PDT 24
Finished Jul 24 07:07:42 PM PDT 24
Peak memory 200152 kb
Host smart-40ffd4e4-9f64-4883-87b9-96427ccfb3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831981505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1831981505
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1307996838
Short name T512
Test name
Test status
Simulation time 92738492 ps
CPU time 0.91 seconds
Started Jul 24 07:07:39 PM PDT 24
Finished Jul 24 07:07:40 PM PDT 24
Peak memory 200164 kb
Host smart-fc303cf2-4923-4eeb-a4d2-bf1edc0d276d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307996838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1307996838
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.232480845
Short name T180
Test name
Test status
Simulation time 66902213 ps
CPU time 0.74 seconds
Started Jul 24 07:06:42 PM PDT 24
Finished Jul 24 07:06:43 PM PDT 24
Peak memory 199956 kb
Host smart-68f71a9e-0e77-4900-8857-1a611c021280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232480845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.232480845
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.102408681
Short name T34
Test name
Test status
Simulation time 2347210206 ps
CPU time 7.89 seconds
Started Jul 24 07:06:38 PM PDT 24
Finished Jul 24 07:06:46 PM PDT 24
Peak memory 217940 kb
Host smart-674d0931-8811-461d-b07e-2ccd4a37df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102408681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.102408681
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.747931159
Short name T481
Test name
Test status
Simulation time 244994429 ps
CPU time 1.05 seconds
Started Jul 24 07:06:35 PM PDT 24
Finished Jul 24 07:06:36 PM PDT 24
Peak memory 217396 kb
Host smart-ebcb590e-0d3b-4e20-b8f4-380a5d9ca914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747931159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.747931159
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2801857465
Short name T498
Test name
Test status
Simulation time 132449283 ps
CPU time 0.89 seconds
Started Jul 24 07:06:37 PM PDT 24
Finished Jul 24 07:06:38 PM PDT 24
Peak memory 199936 kb
Host smart-7d0edd7b-3fd1-4e85-b698-7e42481b641e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801857465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2801857465
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2542997346
Short name T458
Test name
Test status
Simulation time 979531882 ps
CPU time 4.62 seconds
Started Jul 24 07:06:38 PM PDT 24
Finished Jul 24 07:06:43 PM PDT 24
Peak memory 200284 kb
Host smart-73254110-7136-401e-a96d-7ada6290a607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542997346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2542997346
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3050621783
Short name T64
Test name
Test status
Simulation time 20153363104 ps
CPU time 30.41 seconds
Started Jul 24 07:06:39 PM PDT 24
Finished Jul 24 07:07:10 PM PDT 24
Peak memory 218268 kb
Host smart-57ceb195-b3ab-42f6-bcf4-0d4aab0e2035
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050621783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3050621783
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3981469359
Short name T286
Test name
Test status
Simulation time 110079166 ps
CPU time 1.09 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:35 PM PDT 24
Peak memory 200104 kb
Host smart-e9c6488b-1a46-43b2-935d-02e5748301ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981469359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3981469359
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.900464619
Short name T227
Test name
Test status
Simulation time 249446033 ps
CPU time 1.45 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:36 PM PDT 24
Peak memory 200348 kb
Host smart-89ed7c03-7eda-40c4-9bcb-97f197098fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900464619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.900464619
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.907722162
Short name T446
Test name
Test status
Simulation time 2004927316 ps
CPU time 9.06 seconds
Started Jul 24 07:06:34 PM PDT 24
Finished Jul 24 07:06:44 PM PDT 24
Peak memory 208640 kb
Host smart-4611efa5-9d5b-42ff-840f-9756d2877cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907722162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.907722162
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1583045106
Short name T365
Test name
Test status
Simulation time 419399201 ps
CPU time 2.27 seconds
Started Jul 24 07:06:36 PM PDT 24
Finished Jul 24 07:06:39 PM PDT 24
Peak memory 208288 kb
Host smart-737ffeac-30eb-4f51-9820-f266076f3945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583045106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1583045106
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.260859572
Short name T232
Test name
Test status
Simulation time 161071687 ps
CPU time 1.14 seconds
Started Jul 24 07:06:36 PM PDT 24
Finished Jul 24 07:06:37 PM PDT 24
Peak memory 200096 kb
Host smart-cdf225ab-a918-4fd9-8f7d-e5c7a131e684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260859572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.260859572
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.4213075692
Short name T367
Test name
Test status
Simulation time 58569037 ps
CPU time 0.77 seconds
Started Jul 24 07:07:33 PM PDT 24
Finished Jul 24 07:07:34 PM PDT 24
Peak memory 199896 kb
Host smart-116242de-13cc-400f-a52a-f0476b860212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213075692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.4213075692
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3522766867
Short name T366
Test name
Test status
Simulation time 1891912705 ps
CPU time 7.48 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:42 PM PDT 24
Peak memory 217584 kb
Host smart-c3a17f12-7465-4c17-a097-9703344a2b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522766867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3522766867
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1572370476
Short name T307
Test name
Test status
Simulation time 243955978 ps
CPU time 1.13 seconds
Started Jul 24 07:07:39 PM PDT 24
Finished Jul 24 07:07:40 PM PDT 24
Peak memory 217492 kb
Host smart-1b43dd71-e712-4a10-becc-e69ce40290a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572370476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1572370476
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3036685120
Short name T219
Test name
Test status
Simulation time 90328251 ps
CPU time 0.8 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:55 PM PDT 24
Peak memory 199936 kb
Host smart-a3af8b88-d93c-464c-a5b4-7d0003e91b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036685120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3036685120
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2582239402
Short name T478
Test name
Test status
Simulation time 2215431543 ps
CPU time 7.77 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:07:44 PM PDT 24
Peak memory 200544 kb
Host smart-f7234fe8-cf93-401b-b547-4dc2412ee129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582239402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2582239402
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1808534378
Short name T530
Test name
Test status
Simulation time 152818261 ps
CPU time 1.2 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:07:37 PM PDT 24
Peak memory 200140 kb
Host smart-fd93d471-fbb2-47fe-993d-6ae9225a361b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808534378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1808534378
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.12852722
Short name T233
Test name
Test status
Simulation time 121666161 ps
CPU time 1.18 seconds
Started Jul 24 07:07:37 PM PDT 24
Finished Jul 24 07:07:38 PM PDT 24
Peak memory 200352 kb
Host smart-102ebf0a-d32a-4b5f-ad94-5301198a4eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12852722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.12852722
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2492471045
Short name T305
Test name
Test status
Simulation time 12935597209 ps
CPU time 43.2 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:08:19 PM PDT 24
Peak memory 200472 kb
Host smart-b2890db7-1e92-4789-8fce-00c37c430289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492471045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2492471045
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.4018332549
Short name T206
Test name
Test status
Simulation time 354251553 ps
CPU time 2.25 seconds
Started Jul 24 07:07:40 PM PDT 24
Finished Jul 24 07:07:43 PM PDT 24
Peak memory 200144 kb
Host smart-c13cf2bf-2f56-4f54-a0bd-8de9c2b1df70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018332549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4018332549
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3254563615
Short name T163
Test name
Test status
Simulation time 70737964 ps
CPU time 0.78 seconds
Started Jul 24 07:07:36 PM PDT 24
Finished Jul 24 07:07:37 PM PDT 24
Peak memory 200052 kb
Host smart-2b0f8c89-83f0-477c-ac65-e63ab9b27818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254563615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3254563615
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3300040913
Short name T154
Test name
Test status
Simulation time 72956836 ps
CPU time 0.78 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 199924 kb
Host smart-56b8bce2-025e-4858-b87f-fcede1995325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300040913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3300040913
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3746953458
Short name T27
Test name
Test status
Simulation time 2168747165 ps
CPU time 7.83 seconds
Started Jul 24 07:07:39 PM PDT 24
Finished Jul 24 07:07:47 PM PDT 24
Peak memory 217860 kb
Host smart-59656501-5954-4779-8465-890dd20f8ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746953458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3746953458
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.199576134
Short name T121
Test name
Test status
Simulation time 244622716 ps
CPU time 1.21 seconds
Started Jul 24 07:07:35 PM PDT 24
Finished Jul 24 07:07:36 PM PDT 24
Peak memory 217536 kb
Host smart-4a44b59b-ba92-4c17-af8f-c707d6738efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199576134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.199576134
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4277136052
Short name T152
Test name
Test status
Simulation time 199541601 ps
CPU time 0.9 seconds
Started Jul 24 07:07:39 PM PDT 24
Finished Jul 24 07:07:40 PM PDT 24
Peak memory 199952 kb
Host smart-bd69b7be-4384-4a52-b3c6-b8fb2f3be428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277136052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4277136052
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3624526852
Short name T190
Test name
Test status
Simulation time 1496711336 ps
CPU time 6.4 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:41 PM PDT 24
Peak memory 200468 kb
Host smart-14f9efba-a5b5-473c-974b-cc54b05f81bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624526852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3624526852
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4112113745
Short name T475
Test name
Test status
Simulation time 108108096 ps
CPU time 1.03 seconds
Started Jul 24 07:07:39 PM PDT 24
Finished Jul 24 07:07:40 PM PDT 24
Peak memory 200164 kb
Host smart-878ab7d3-1e97-44a0-978d-7ae3597492b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112113745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4112113745
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2968969285
Short name T438
Test name
Test status
Simulation time 187860039 ps
CPU time 1.33 seconds
Started Jul 24 07:07:38 PM PDT 24
Finished Jul 24 07:07:39 PM PDT 24
Peak memory 200328 kb
Host smart-55995f19-39f1-4599-b99c-3b30ec31ef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968969285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2968969285
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2873602098
Short name T261
Test name
Test status
Simulation time 2165003508 ps
CPU time 9.35 seconds
Started Jul 24 07:07:35 PM PDT 24
Finished Jul 24 07:07:44 PM PDT 24
Peak memory 208644 kb
Host smart-f0d3bed9-e126-40fa-8bc8-37c4cd2de917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873602098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2873602098
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2852371626
Short name T453
Test name
Test status
Simulation time 425704245 ps
CPU time 2.26 seconds
Started Jul 24 07:07:35 PM PDT 24
Finished Jul 24 07:07:37 PM PDT 24
Peak memory 208528 kb
Host smart-fb0ea243-016c-441e-9dbf-2ddcae29c32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852371626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2852371626
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2827369637
Short name T317
Test name
Test status
Simulation time 134823080 ps
CPU time 1.07 seconds
Started Jul 24 07:07:38 PM PDT 24
Finished Jul 24 07:07:39 PM PDT 24
Peak memory 200128 kb
Host smart-f0b9a10a-9030-4bb0-b0b3-396ac1a8c573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827369637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2827369637
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2958846123
Short name T247
Test name
Test status
Simulation time 72691532 ps
CPU time 0.81 seconds
Started Jul 24 07:07:47 PM PDT 24
Finished Jul 24 07:07:48 PM PDT 24
Peak memory 199948 kb
Host smart-68766834-248e-4640-ade2-236417437eda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958846123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2958846123
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3710221196
Short name T389
Test name
Test status
Simulation time 2347626733 ps
CPU time 9.08 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:08:03 PM PDT 24
Peak memory 217944 kb
Host smart-39f72cfe-4f73-4b2b-a883-6df8f4e249fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710221196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3710221196
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.158103447
Short name T37
Test name
Test status
Simulation time 243532489 ps
CPU time 1.04 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:55 PM PDT 24
Peak memory 217496 kb
Host smart-9d8bf8dd-d5fc-4c77-b7e7-7209a553579c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158103447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.158103447
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.433528891
Short name T459
Test name
Test status
Simulation time 117396980 ps
CPU time 0.81 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 199928 kb
Host smart-34c8ed08-ff7e-4b4c-945b-dec2f17b200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433528891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.433528891
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.100305804
Short name T211
Test name
Test status
Simulation time 833196911 ps
CPU time 3.88 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:38 PM PDT 24
Peak memory 200468 kb
Host smart-7dbfd164-a2bb-4631-b304-2163fdc34466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100305804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.100305804
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1646780265
Short name T174
Test name
Test status
Simulation time 170538927 ps
CPU time 1.19 seconds
Started Jul 24 07:07:37 PM PDT 24
Finished Jul 24 07:07:38 PM PDT 24
Peak memory 200104 kb
Host smart-9c764849-1c8a-46e6-b21b-595f42889a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646780265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1646780265
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3255273920
Short name T181
Test name
Test status
Simulation time 196118356 ps
CPU time 1.37 seconds
Started Jul 24 07:07:40 PM PDT 24
Finished Jul 24 07:07:41 PM PDT 24
Peak memory 200336 kb
Host smart-3341547f-9514-4785-aba8-2914cb14cda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255273920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3255273920
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.729156549
Short name T515
Test name
Test status
Simulation time 2309678953 ps
CPU time 8.42 seconds
Started Jul 24 07:07:53 PM PDT 24
Finished Jul 24 07:08:01 PM PDT 24
Peak memory 208684 kb
Host smart-b25c9f31-fbd5-4ca9-9908-f32972a34b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729156549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.729156549
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.743473012
Short name T493
Test name
Test status
Simulation time 146274802 ps
CPU time 1.93 seconds
Started Jul 24 07:07:47 PM PDT 24
Finished Jul 24 07:07:49 PM PDT 24
Peak memory 200152 kb
Host smart-9a9a7735-9572-4e8f-89c8-3dde2613c56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743473012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.743473012
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.22693080
Short name T41
Test name
Test status
Simulation time 162818559 ps
CPU time 1.29 seconds
Started Jul 24 07:07:34 PM PDT 24
Finished Jul 24 07:07:35 PM PDT 24
Peak memory 200408 kb
Host smart-00bc8c7d-bbc5-4d08-aac7-2adaeebce851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22693080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.22693080
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2885775591
Short name T132
Test name
Test status
Simulation time 57655582 ps
CPU time 0.77 seconds
Started Jul 24 07:07:40 PM PDT 24
Finished Jul 24 07:07:41 PM PDT 24
Peak memory 199956 kb
Host smart-1a27f0c1-9b29-422c-b8ca-a923d09ac9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885775591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2885775591
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1005217419
Short name T497
Test name
Test status
Simulation time 1906662731 ps
CPU time 7.28 seconds
Started Jul 24 07:07:39 PM PDT 24
Finished Jul 24 07:07:46 PM PDT 24
Peak memory 217832 kb
Host smart-d68339ee-9309-4644-bc5f-a203f4a1ea6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005217419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1005217419
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.770064298
Short name T52
Test name
Test status
Simulation time 244316598 ps
CPU time 1.06 seconds
Started Jul 24 07:07:43 PM PDT 24
Finished Jul 24 07:07:44 PM PDT 24
Peak memory 217504 kb
Host smart-142697fe-44fe-4d5c-b0b8-259647b2e79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770064298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.770064298
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3897414348
Short name T217
Test name
Test status
Simulation time 88617786 ps
CPU time 0.8 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 199972 kb
Host smart-c3cc834f-0411-4564-a964-282abadd1eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897414348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3897414348
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2931214530
Short name T240
Test name
Test status
Simulation time 1495038469 ps
CPU time 5.99 seconds
Started Jul 24 07:07:57 PM PDT 24
Finished Jul 24 07:08:03 PM PDT 24
Peak memory 200484 kb
Host smart-29946646-d2bd-4c19-b987-49f17a2cc7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931214530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2931214530
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2161882314
Short name T474
Test name
Test status
Simulation time 149323840 ps
CPU time 1.13 seconds
Started Jul 24 07:07:38 PM PDT 24
Finished Jul 24 07:07:39 PM PDT 24
Peak memory 200132 kb
Host smart-63eb5eb8-835d-45e4-a759-4b2fe07f40c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161882314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2161882314
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2960827142
Short name T116
Test name
Test status
Simulation time 249909208 ps
CPU time 1.67 seconds
Started Jul 24 07:07:42 PM PDT 24
Finished Jul 24 07:07:44 PM PDT 24
Peak memory 200312 kb
Host smart-93281399-b09f-445d-bdb9-1b8116a9563a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960827142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2960827142
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3916454625
Short name T399
Test name
Test status
Simulation time 1566215852 ps
CPU time 6.26 seconds
Started Jul 24 07:07:48 PM PDT 24
Finished Jul 24 07:07:55 PM PDT 24
Peak memory 200440 kb
Host smart-f306e43c-f153-48d2-a67b-7225366b76bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916454625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3916454625
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1062980083
Short name T39
Test name
Test status
Simulation time 137563590 ps
CPU time 1.72 seconds
Started Jul 24 07:07:52 PM PDT 24
Finished Jul 24 07:07:53 PM PDT 24
Peak memory 200104 kb
Host smart-9775af24-93f2-4712-81af-9945ecbfaac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062980083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1062980083
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2624024006
Short name T356
Test name
Test status
Simulation time 65605958 ps
CPU time 0.77 seconds
Started Jul 24 07:07:40 PM PDT 24
Finished Jul 24 07:07:41 PM PDT 24
Peak memory 200132 kb
Host smart-ff2fc35a-b504-4e8f-89c9-3dc3faf646b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624024006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2624024006
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1548171961
Short name T329
Test name
Test status
Simulation time 57404658 ps
CPU time 0.72 seconds
Started Jul 24 07:07:51 PM PDT 24
Finished Jul 24 07:07:51 PM PDT 24
Peak memory 199956 kb
Host smart-1bce8b54-e0df-4c86-9514-f2edc12eb1b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548171961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1548171961
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3814337810
Short name T32
Test name
Test status
Simulation time 1227448610 ps
CPU time 6.3 seconds
Started Jul 24 07:07:58 PM PDT 24
Finished Jul 24 07:08:04 PM PDT 24
Peak memory 221884 kb
Host smart-256188bf-942a-4211-8d48-92a321c80647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814337810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3814337810
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1971249002
Short name T225
Test name
Test status
Simulation time 243667239 ps
CPU time 1.08 seconds
Started Jul 24 07:07:47 PM PDT 24
Finished Jul 24 07:07:48 PM PDT 24
Peak memory 217492 kb
Host smart-9b729d13-f481-483e-95e3-07112e03a395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971249002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1971249002
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.4136549695
Short name T140
Test name
Test status
Simulation time 118206736 ps
CPU time 0.84 seconds
Started Jul 24 07:07:41 PM PDT 24
Finished Jul 24 07:07:43 PM PDT 24
Peak memory 199948 kb
Host smart-0e68a993-b71c-48c4-9943-d1ef80e8621b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136549695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4136549695
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2768627638
Short name T256
Test name
Test status
Simulation time 1159658906 ps
CPU time 5.69 seconds
Started Jul 24 07:07:51 PM PDT 24
Finished Jul 24 07:07:57 PM PDT 24
Peak memory 200420 kb
Host smart-059d2796-6643-4288-9e66-f47e30b43e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768627638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2768627638
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.735817994
Short name T468
Test name
Test status
Simulation time 104941676 ps
CPU time 1 seconds
Started Jul 24 07:07:42 PM PDT 24
Finished Jul 24 07:07:44 PM PDT 24
Peak memory 200140 kb
Host smart-226ec5a7-8f9b-4648-82ed-2c60ae040d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735817994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.735817994
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.321143869
Short name T212
Test name
Test status
Simulation time 194524691 ps
CPU time 1.51 seconds
Started Jul 24 07:07:58 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 200356 kb
Host smart-e0dbd3cc-c7cc-46ea-ac3a-cdedc75e75bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321143869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.321143869
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.701808931
Short name T482
Test name
Test status
Simulation time 137939572 ps
CPU time 1.63 seconds
Started Jul 24 07:07:38 PM PDT 24
Finished Jul 24 07:07:40 PM PDT 24
Peak memory 200152 kb
Host smart-7ae09bbc-917c-40e8-b722-0b775ffc2736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701808931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.701808931
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.4117411341
Short name T362
Test name
Test status
Simulation time 152440863 ps
CPU time 1.28 seconds
Started Jul 24 07:07:40 PM PDT 24
Finished Jul 24 07:07:42 PM PDT 24
Peak memory 200324 kb
Host smart-ed916ccd-e8ec-4077-9005-cb34fe52fd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117411341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.4117411341
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.813340888
Short name T160
Test name
Test status
Simulation time 66499000 ps
CPU time 0.82 seconds
Started Jul 24 07:07:39 PM PDT 24
Finished Jul 24 07:07:40 PM PDT 24
Peak memory 199948 kb
Host smart-6742ce86-e17b-406c-a5de-b097b2f6ed6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813340888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.813340888
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1854696977
Short name T529
Test name
Test status
Simulation time 1880547746 ps
CPU time 7.56 seconds
Started Jul 24 07:07:41 PM PDT 24
Finished Jul 24 07:07:49 PM PDT 24
Peak memory 221772 kb
Host smart-f9f9ea26-cb4e-423e-9b6b-5fa8a50fe7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854696977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1854696977
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2756520805
Short name T187
Test name
Test status
Simulation time 244315992 ps
CPU time 1.11 seconds
Started Jul 24 07:07:49 PM PDT 24
Finished Jul 24 07:07:50 PM PDT 24
Peak memory 217540 kb
Host smart-23d13157-5781-478d-9abf-0b72698a9921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756520805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2756520805
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1224287651
Short name T130
Test name
Test status
Simulation time 175439273 ps
CPU time 0.88 seconds
Started Jul 24 07:07:52 PM PDT 24
Finished Jul 24 07:07:53 PM PDT 24
Peak memory 200008 kb
Host smart-da718779-9579-47f2-b6a7-6ef5352300d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224287651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1224287651
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2954102601
Short name T162
Test name
Test status
Simulation time 1212546401 ps
CPU time 4.88 seconds
Started Jul 24 07:07:52 PM PDT 24
Finished Jul 24 07:07:58 PM PDT 24
Peak memory 200404 kb
Host smart-e773b3a0-7ce5-4ddd-a216-bbd20fa49a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954102601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2954102601
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.762465966
Short name T405
Test name
Test status
Simulation time 147074262 ps
CPU time 1.19 seconds
Started Jul 24 07:07:41 PM PDT 24
Finished Jul 24 07:07:43 PM PDT 24
Peak memory 200120 kb
Host smart-a0be3a11-c6ce-40f9-bd51-fb0b32605622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762465966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.762465966
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2729801389
Short name T128
Test name
Test status
Simulation time 124035762 ps
CPU time 1.19 seconds
Started Jul 24 07:07:42 PM PDT 24
Finished Jul 24 07:07:43 PM PDT 24
Peak memory 200312 kb
Host smart-7abc5db5-c9c5-4e95-a789-6c3080219608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729801389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2729801389
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.804550183
Short name T391
Test name
Test status
Simulation time 9257354597 ps
CPU time 31.58 seconds
Started Jul 24 07:07:45 PM PDT 24
Finished Jul 24 07:08:17 PM PDT 24
Peak memory 208636 kb
Host smart-3aca90fa-9453-4c6c-ac44-829b4785d3f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804550183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.804550183
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3228129084
Short name T427
Test name
Test status
Simulation time 144439412 ps
CPU time 1.72 seconds
Started Jul 24 07:07:47 PM PDT 24
Finished Jul 24 07:07:49 PM PDT 24
Peak memory 200112 kb
Host smart-e74388c3-fbb2-46d6-ae7b-23a77af07c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228129084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3228129084
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1280668380
Short name T262
Test name
Test status
Simulation time 155441897 ps
CPU time 1.29 seconds
Started Jul 24 07:07:42 PM PDT 24
Finished Jul 24 07:07:44 PM PDT 24
Peak memory 200344 kb
Host smart-de6b1ca8-113e-45bf-99cb-692980673171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280668380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1280668380
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2477476810
Short name T66
Test name
Test status
Simulation time 52328760 ps
CPU time 0.74 seconds
Started Jul 24 07:07:47 PM PDT 24
Finished Jul 24 07:07:48 PM PDT 24
Peak memory 200144 kb
Host smart-2e865f6e-a9c8-44bc-9f27-cdc427786067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477476810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2477476810
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2635101957
Short name T48
Test name
Test status
Simulation time 1917053216 ps
CPU time 7.41 seconds
Started Jul 24 07:07:41 PM PDT 24
Finished Jul 24 07:07:49 PM PDT 24
Peak memory 217820 kb
Host smart-5bdb4354-b8f3-4248-b741-054a88b31267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635101957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2635101957
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.4075603872
Short name T195
Test name
Test status
Simulation time 245159364 ps
CPU time 1.08 seconds
Started Jul 24 07:07:42 PM PDT 24
Finished Jul 24 07:07:44 PM PDT 24
Peak memory 217560 kb
Host smart-537e4d29-6629-4021-986f-939a23ec559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075603872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.4075603872
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3244651124
Short name T21
Test name
Test status
Simulation time 173859222 ps
CPU time 0.96 seconds
Started Jul 24 07:07:44 PM PDT 24
Finished Jul 24 07:07:45 PM PDT 24
Peak memory 199932 kb
Host smart-e25f306c-e392-4a38-a63f-bbd649d16359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244651124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3244651124
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3068210613
Short name T273
Test name
Test status
Simulation time 914455451 ps
CPU time 5.07 seconds
Started Jul 24 07:07:42 PM PDT 24
Finished Jul 24 07:07:48 PM PDT 24
Peak memory 200448 kb
Host smart-11909336-2b40-4955-8a64-9ade60c231fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068210613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3068210613
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1123108597
Short name T302
Test name
Test status
Simulation time 96239286 ps
CPU time 1.04 seconds
Started Jul 24 07:07:43 PM PDT 24
Finished Jul 24 07:07:44 PM PDT 24
Peak memory 200128 kb
Host smart-039bb2e5-11f3-4df3-b72b-b8f93b35bf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123108597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1123108597
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1046618808
Short name T200
Test name
Test status
Simulation time 250623964 ps
CPU time 1.5 seconds
Started Jul 24 07:07:45 PM PDT 24
Finished Jul 24 07:07:46 PM PDT 24
Peak memory 200348 kb
Host smart-c1fdb138-2407-4b44-9c64-5dfa09782284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046618808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1046618808
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1336697398
Short name T361
Test name
Test status
Simulation time 15573855524 ps
CPU time 56.06 seconds
Started Jul 24 07:07:43 PM PDT 24
Finished Jul 24 07:08:39 PM PDT 24
Peak memory 200420 kb
Host smart-7bd9dbac-7014-4305-8fae-1dd3d9b20df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336697398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1336697398
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2556088681
Short name T193
Test name
Test status
Simulation time 141779222 ps
CPU time 1.94 seconds
Started Jul 24 07:07:42 PM PDT 24
Finished Jul 24 07:07:45 PM PDT 24
Peak memory 200224 kb
Host smart-25d8c3e3-2792-4141-9e26-59bfe205de09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556088681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2556088681
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1454041029
Short name T322
Test name
Test status
Simulation time 136290664 ps
CPU time 1.21 seconds
Started Jul 24 07:07:42 PM PDT 24
Finished Jul 24 07:07:44 PM PDT 24
Peak memory 200188 kb
Host smart-414382ea-1c94-43fc-b5bc-ac31963437f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454041029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1454041029
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3976178186
Short name T309
Test name
Test status
Simulation time 78165647 ps
CPU time 0.86 seconds
Started Jul 24 07:07:53 PM PDT 24
Finished Jul 24 07:07:54 PM PDT 24
Peak memory 199956 kb
Host smart-75835feb-64ea-44f2-85ed-557158640efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976178186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3976178186
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2480373254
Short name T330
Test name
Test status
Simulation time 2187808044 ps
CPU time 8.54 seconds
Started Jul 24 07:07:47 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 221796 kb
Host smart-14fef9e4-55fa-4875-b683-cb1ecae65e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480373254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2480373254
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3851964553
Short name T194
Test name
Test status
Simulation time 244742131 ps
CPU time 1.11 seconds
Started Jul 24 07:07:52 PM PDT 24
Finished Jul 24 07:07:54 PM PDT 24
Peak memory 217500 kb
Host smart-13b1e178-2ae0-4b61-b1aa-cc9e5879e4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851964553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3851964553
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.536408009
Short name T375
Test name
Test status
Simulation time 87160528 ps
CPU time 0.74 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:55 PM PDT 24
Peak memory 199972 kb
Host smart-91fac14e-c487-4c8b-a593-a8dde6502b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536408009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.536408009
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3573366851
Short name T85
Test name
Test status
Simulation time 845294814 ps
CPU time 4.61 seconds
Started Jul 24 07:07:49 PM PDT 24
Finished Jul 24 07:07:54 PM PDT 24
Peak memory 200404 kb
Host smart-9b2f237a-3d62-400a-85c8-d45c70456be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573366851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3573366851
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.4181318402
Short name T151
Test name
Test status
Simulation time 148451508 ps
CPU time 1.09 seconds
Started Jul 24 07:07:52 PM PDT 24
Finished Jul 24 07:07:54 PM PDT 24
Peak memory 200164 kb
Host smart-9b5d32a0-d0b6-4e0b-b9c2-1858757cb37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181318402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.4181318402
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2308200629
Short name T3
Test name
Test status
Simulation time 199570144 ps
CPU time 1.56 seconds
Started Jul 24 07:07:49 PM PDT 24
Finished Jul 24 07:07:51 PM PDT 24
Peak memory 200364 kb
Host smart-b679d7c7-c6c1-4720-b21d-a82d6b168a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308200629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2308200629
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2803933613
Short name T328
Test name
Test status
Simulation time 17053414495 ps
CPU time 54.87 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:08:50 PM PDT 24
Peak memory 208632 kb
Host smart-e9d4a6a5-95be-4207-9fd1-9f328068949b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803933613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2803933613
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3354871823
Short name T319
Test name
Test status
Simulation time 147232156 ps
CPU time 1.95 seconds
Started Jul 24 07:07:46 PM PDT 24
Finished Jul 24 07:07:48 PM PDT 24
Peak memory 200028 kb
Host smart-d943a833-2c49-405b-927c-d2a12df8d12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354871823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3354871823
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1578334071
Short name T285
Test name
Test status
Simulation time 151827293 ps
CPU time 1.31 seconds
Started Jul 24 07:07:51 PM PDT 24
Finished Jul 24 07:07:53 PM PDT 24
Peak memory 200368 kb
Host smart-a3ab4b6d-eb76-4ba9-b84d-e07df885e797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578334071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1578334071
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4060918933
Short name T511
Test name
Test status
Simulation time 75366456 ps
CPU time 0.8 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:55 PM PDT 24
Peak memory 199984 kb
Host smart-d5660a0e-89c6-476c-ba10-64f79cd81977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060918933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4060918933
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2841302292
Short name T499
Test name
Test status
Simulation time 1212947652 ps
CPU time 5.67 seconds
Started Jul 24 07:07:53 PM PDT 24
Finished Jul 24 07:07:59 PM PDT 24
Peak memory 217592 kb
Host smart-b97cd7d4-5bbf-48bf-9a07-0be8cd1d9f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841302292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2841302292
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.810981595
Short name T320
Test name
Test status
Simulation time 244235683 ps
CPU time 1.09 seconds
Started Jul 24 07:07:51 PM PDT 24
Finished Jul 24 07:07:53 PM PDT 24
Peak memory 217516 kb
Host smart-829e4169-e7bf-4580-8e4a-250ab270041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810981595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.810981595
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.128568246
Short name T141
Test name
Test status
Simulation time 194817683 ps
CPU time 0.94 seconds
Started Jul 24 07:07:51 PM PDT 24
Finished Jul 24 07:07:52 PM PDT 24
Peak memory 199972 kb
Host smart-50983c8c-a39d-4385-9a56-1487c32f0480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128568246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.128568246
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3680545833
Short name T338
Test name
Test status
Simulation time 844028990 ps
CPU time 4.44 seconds
Started Jul 24 07:07:53 PM PDT 24
Finished Jul 24 07:07:58 PM PDT 24
Peak memory 200448 kb
Host smart-9df2257c-2315-4964-8a10-772daf17f812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680545833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3680545833
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3583692556
Short name T10
Test name
Test status
Simulation time 158701980 ps
CPU time 1.19 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200128 kb
Host smart-71e0565b-705d-41c5-91e8-ae673fad7653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583692556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3583692556
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2746002901
Short name T253
Test name
Test status
Simulation time 117749554 ps
CPU time 1.23 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200372 kb
Host smart-5e57547c-f2ea-49d7-b226-3253fbcf15ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746002901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2746002901
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1152419531
Short name T335
Test name
Test status
Simulation time 772154338 ps
CPU time 3.99 seconds
Started Jul 24 07:07:48 PM PDT 24
Finished Jul 24 07:07:52 PM PDT 24
Peak memory 200352 kb
Host smart-57070992-f27b-4a60-9870-5de669093023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152419531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1152419531
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.582781094
Short name T388
Test name
Test status
Simulation time 324291996 ps
CPU time 2.27 seconds
Started Jul 24 07:07:47 PM PDT 24
Finished Jul 24 07:07:49 PM PDT 24
Peak memory 200168 kb
Host smart-b41f19db-e500-4b6f-9099-664999ded0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582781094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.582781094
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.4236086199
Short name T158
Test name
Test status
Simulation time 149582201 ps
CPU time 1.17 seconds
Started Jul 24 07:07:53 PM PDT 24
Finished Jul 24 07:07:54 PM PDT 24
Peak memory 200316 kb
Host smart-9e4dbc40-c5d2-4303-8b85-98e29c07e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236086199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.4236086199
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3019365959
Short name T178
Test name
Test status
Simulation time 103650292 ps
CPU time 0.92 seconds
Started Jul 24 07:07:55 PM PDT 24
Finished Jul 24 07:07:57 PM PDT 24
Peak memory 199972 kb
Host smart-b50096af-8c9b-4fae-b086-3189796e7f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019365959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3019365959
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2374405810
Short name T353
Test name
Test status
Simulation time 1875761728 ps
CPU time 7.81 seconds
Started Jul 24 07:07:52 PM PDT 24
Finished Jul 24 07:08:00 PM PDT 24
Peak memory 217816 kb
Host smart-06193b36-379d-42ca-8dad-69e908e059a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374405810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2374405810
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1082028829
Short name T288
Test name
Test status
Simulation time 244446787 ps
CPU time 1.02 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:55 PM PDT 24
Peak memory 217496 kb
Host smart-da4737d3-7c0b-4aa1-867e-2d50b3cfcfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082028829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1082028829
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1609995746
Short name T395
Test name
Test status
Simulation time 241655856 ps
CPU time 0.97 seconds
Started Jul 24 07:07:47 PM PDT 24
Finished Jul 24 07:07:48 PM PDT 24
Peak memory 199952 kb
Host smart-2e73ffe1-3332-46cd-8a8e-e473fc6cde9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609995746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1609995746
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2747721333
Short name T419
Test name
Test status
Simulation time 632902351 ps
CPU time 3.58 seconds
Started Jul 24 07:07:53 PM PDT 24
Finished Jul 24 07:07:57 PM PDT 24
Peak memory 200360 kb
Host smart-a5be5071-7665-4c9c-a482-52ac45406bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747721333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2747721333
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1486883803
Short name T230
Test name
Test status
Simulation time 94825997 ps
CPU time 0.99 seconds
Started Jul 24 07:07:53 PM PDT 24
Finished Jul 24 07:07:54 PM PDT 24
Peak memory 200156 kb
Host smart-76f2dd8e-bf4d-482f-a79c-b25ce9b305b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486883803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1486883803
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.555069216
Short name T145
Test name
Test status
Simulation time 115244784 ps
CPU time 1.17 seconds
Started Jul 24 07:07:52 PM PDT 24
Finished Jul 24 07:07:53 PM PDT 24
Peak memory 200336 kb
Host smart-0f72a22f-4af4-4316-98fa-52e39c3e8bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555069216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.555069216
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3810762552
Short name T73
Test name
Test status
Simulation time 5603872582 ps
CPU time 24.75 seconds
Started Jul 24 07:07:52 PM PDT 24
Finished Jul 24 07:08:17 PM PDT 24
Peak memory 208684 kb
Host smart-d863d52d-4fda-4b58-b349-f9282ab8f834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810762552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3810762552
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.817404926
Short name T327
Test name
Test status
Simulation time 351708420 ps
CPU time 2.35 seconds
Started Jul 24 07:07:47 PM PDT 24
Finished Jul 24 07:07:50 PM PDT 24
Peak memory 200168 kb
Host smart-e3d9a40e-3fae-472d-821a-5036e25c4c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817404926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.817404926
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2930442829
Short name T215
Test name
Test status
Simulation time 216291985 ps
CPU time 1.35 seconds
Started Jul 24 07:07:54 PM PDT 24
Finished Jul 24 07:07:56 PM PDT 24
Peak memory 200128 kb
Host smart-6e3809dd-96a9-42c0-b3f0-ea3d5e7a484f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930442829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2930442829
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.82410499
Short name T186
Test name
Test status
Simulation time 82870675 ps
CPU time 0.98 seconds
Started Jul 24 07:06:42 PM PDT 24
Finished Jul 24 07:06:43 PM PDT 24
Peak memory 199932 kb
Host smart-807ed0f6-acc3-479a-bc2f-1ed682894926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82410499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.82410499
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.461414810
Short name T33
Test name
Test status
Simulation time 1892786783 ps
CPU time 7.95 seconds
Started Jul 24 07:06:40 PM PDT 24
Finished Jul 24 07:06:48 PM PDT 24
Peak memory 217792 kb
Host smart-fb4c1b17-5e4a-4479-886a-bfaa0b6c7873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461414810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.461414810
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.4084696819
Short name T122
Test name
Test status
Simulation time 243693888 ps
CPU time 1.12 seconds
Started Jul 24 07:06:41 PM PDT 24
Finished Jul 24 07:06:42 PM PDT 24
Peak memory 217492 kb
Host smart-a374e405-da51-46ca-8427-e423a1eb493f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084696819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.4084696819
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.4133916012
Short name T19
Test name
Test status
Simulation time 133664356 ps
CPU time 0.91 seconds
Started Jul 24 07:06:43 PM PDT 24
Finished Jul 24 07:06:44 PM PDT 24
Peak memory 199976 kb
Host smart-81af15c3-b857-43ec-9c2f-c42e75460cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133916012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.4133916012
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3996168660
Short name T463
Test name
Test status
Simulation time 1078084802 ps
CPU time 5.6 seconds
Started Jul 24 07:06:37 PM PDT 24
Finished Jul 24 07:06:43 PM PDT 24
Peak memory 200424 kb
Host smart-37e7d716-13aa-4481-833d-5d2329e8f30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996168660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3996168660
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1754838026
Short name T537
Test name
Test status
Simulation time 105707757 ps
CPU time 1.04 seconds
Started Jul 24 07:06:39 PM PDT 24
Finished Jul 24 07:06:40 PM PDT 24
Peak memory 200164 kb
Host smart-ae82b963-3933-4ed3-a97c-c35ec832d0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754838026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1754838026
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3727542641
Short name T486
Test name
Test status
Simulation time 106656977 ps
CPU time 1.17 seconds
Started Jul 24 07:06:41 PM PDT 24
Finished Jul 24 07:06:43 PM PDT 24
Peak memory 200344 kb
Host smart-c44dbab3-265d-4e75-819a-c3e998502c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727542641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3727542641
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.4015754868
Short name T205
Test name
Test status
Simulation time 6653622452 ps
CPU time 28.21 seconds
Started Jul 24 07:06:42 PM PDT 24
Finished Jul 24 07:07:11 PM PDT 24
Peak memory 208680 kb
Host smart-6ae290ca-2104-4022-a8f2-1bed8e537c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015754868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.4015754868
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1603148138
Short name T283
Test name
Test status
Simulation time 488943089 ps
CPU time 2.53 seconds
Started Jul 24 07:06:40 PM PDT 24
Finished Jul 24 07:06:42 PM PDT 24
Peak memory 208352 kb
Host smart-ebbd87f5-5cf7-4dc4-8dd0-7dcc61e22f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603148138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1603148138
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.84590255
Short name T414
Test name
Test status
Simulation time 95036783 ps
CPU time 0.96 seconds
Started Jul 24 07:06:42 PM PDT 24
Finished Jul 24 07:06:43 PM PDT 24
Peak memory 200180 kb
Host smart-42f052a5-722b-4808-b13c-60ded028e737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84590255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.84590255
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.538882573
Short name T516
Test name
Test status
Simulation time 66207474 ps
CPU time 0.76 seconds
Started Jul 24 07:06:41 PM PDT 24
Finished Jul 24 07:06:42 PM PDT 24
Peak memory 199896 kb
Host smart-6494ac85-3f04-4d6a-91f8-cbb367f10c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538882573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.538882573
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3273873845
Short name T354
Test name
Test status
Simulation time 1894538725 ps
CPU time 7.66 seconds
Started Jul 24 07:06:42 PM PDT 24
Finished Jul 24 07:06:50 PM PDT 24
Peak memory 217900 kb
Host smart-935cacb8-1668-4828-b2a4-fc6e143ad5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273873845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3273873845
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3761890435
Short name T167
Test name
Test status
Simulation time 244330694 ps
CPU time 1.06 seconds
Started Jul 24 07:06:40 PM PDT 24
Finished Jul 24 07:06:41 PM PDT 24
Peak memory 217428 kb
Host smart-d03d1b6f-02fd-4114-8393-9fe1d01f59f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761890435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3761890435
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.862446643
Short name T15
Test name
Test status
Simulation time 104159680 ps
CPU time 0.8 seconds
Started Jul 24 07:06:40 PM PDT 24
Finished Jul 24 07:06:41 PM PDT 24
Peak memory 199920 kb
Host smart-d65b3372-8929-403a-a928-d9821b48b46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862446643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.862446643
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1428001374
Short name T259
Test name
Test status
Simulation time 645201923 ps
CPU time 3.46 seconds
Started Jul 24 07:06:49 PM PDT 24
Finished Jul 24 07:06:52 PM PDT 24
Peak memory 200392 kb
Host smart-9022dacf-5efe-4ede-98e4-36b026162972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428001374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1428001374
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3750847647
Short name T277
Test name
Test status
Simulation time 153661318 ps
CPU time 1.15 seconds
Started Jul 24 07:06:41 PM PDT 24
Finished Jul 24 07:06:43 PM PDT 24
Peak memory 200188 kb
Host smart-0e67c984-d399-48bf-917e-c94c4148dfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750847647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3750847647
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.610414503
Short name T252
Test name
Test status
Simulation time 254203223 ps
CPU time 1.54 seconds
Started Jul 24 07:06:41 PM PDT 24
Finished Jul 24 07:06:42 PM PDT 24
Peak memory 200308 kb
Host smart-ae86fb9c-4c6f-4dcc-a6b3-50d5cd4bdd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610414503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.610414503
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1968102572
Short name T369
Test name
Test status
Simulation time 5680372777 ps
CPU time 25.53 seconds
Started Jul 24 07:06:38 PM PDT 24
Finished Jul 24 07:07:04 PM PDT 24
Peak memory 200444 kb
Host smart-f6cfc69a-cd9d-4682-aeb7-9dbe092fe555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968102572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1968102572
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1461836885
Short name T513
Test name
Test status
Simulation time 370284846 ps
CPU time 2.23 seconds
Started Jul 24 07:06:39 PM PDT 24
Finished Jul 24 07:06:41 PM PDT 24
Peak memory 200132 kb
Host smart-355d031b-a146-4cc6-b241-21bba2810985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461836885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1461836885
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1891463726
Short name T136
Test name
Test status
Simulation time 153115909 ps
CPU time 1.29 seconds
Started Jul 24 07:06:40 PM PDT 24
Finished Jul 24 07:06:42 PM PDT 24
Peak memory 200324 kb
Host smart-f09a48ce-7c9e-436e-b874-bc01584455ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891463726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1891463726
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3996164676
Short name T176
Test name
Test status
Simulation time 67868187 ps
CPU time 0.77 seconds
Started Jul 24 07:06:39 PM PDT 24
Finished Jul 24 07:06:40 PM PDT 24
Peak memory 199956 kb
Host smart-41b09e48-045b-4547-a870-8d1198b0f446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996164676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3996164676
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2637614070
Short name T53
Test name
Test status
Simulation time 1218960789 ps
CPU time 5.59 seconds
Started Jul 24 07:06:40 PM PDT 24
Finished Jul 24 07:06:46 PM PDT 24
Peak memory 217480 kb
Host smart-edd48403-b676-4713-a1bf-bede4e514ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637614070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2637614070
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1260606043
Short name T464
Test name
Test status
Simulation time 245039273 ps
CPU time 1.13 seconds
Started Jul 24 07:06:41 PM PDT 24
Finished Jul 24 07:06:43 PM PDT 24
Peak memory 217568 kb
Host smart-7f265c74-762a-4e3c-929a-bb7c5e2eac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260606043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1260606043
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.6775181
Short name T159
Test name
Test status
Simulation time 150779785 ps
CPU time 0.88 seconds
Started Jul 24 07:06:42 PM PDT 24
Finished Jul 24 07:06:43 PM PDT 24
Peak memory 199960 kb
Host smart-519113bd-56e9-4e20-b3d2-5dd2881d6403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6775181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.6775181
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2858226532
Short name T495
Test name
Test status
Simulation time 793745387 ps
CPU time 4.5 seconds
Started Jul 24 07:06:41 PM PDT 24
Finished Jul 24 07:06:45 PM PDT 24
Peak memory 200416 kb
Host smart-50e96a05-cda5-45d4-9a2c-959eb2b6c6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858226532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2858226532
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3103865118
Short name T358
Test name
Test status
Simulation time 177827529 ps
CPU time 1.26 seconds
Started Jul 24 07:06:42 PM PDT 24
Finished Jul 24 07:06:44 PM PDT 24
Peak memory 200148 kb
Host smart-5970f703-6d05-46a4-a52a-befe614d39eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103865118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3103865118
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2214910032
Short name T198
Test name
Test status
Simulation time 194448541 ps
CPU time 1.41 seconds
Started Jul 24 07:06:40 PM PDT 24
Finished Jul 24 07:06:42 PM PDT 24
Peak memory 200308 kb
Host smart-355ea555-e671-443d-92af-f7976f1bae2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214910032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2214910032
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.4251436129
Short name T380
Test name
Test status
Simulation time 4093685986 ps
CPU time 18.53 seconds
Started Jul 24 07:06:39 PM PDT 24
Finished Jul 24 07:06:57 PM PDT 24
Peak memory 208696 kb
Host smart-e4277004-41fa-4a57-a548-48392c8a41e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251436129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.4251436129
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3019439186
Short name T271
Test name
Test status
Simulation time 120234290 ps
CPU time 1.6 seconds
Started Jul 24 07:06:44 PM PDT 24
Finished Jul 24 07:06:46 PM PDT 24
Peak memory 200216 kb
Host smart-79bb1197-beb2-4fe9-b191-88c8e6494232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019439186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3019439186
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2214961056
Short name T406
Test name
Test status
Simulation time 230290869 ps
CPU time 1.49 seconds
Started Jul 24 07:06:42 PM PDT 24
Finished Jul 24 07:06:44 PM PDT 24
Peak memory 200400 kb
Host smart-1a23976e-053b-4684-9175-51e1312d53aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214961056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2214961056
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3918525550
Short name T496
Test name
Test status
Simulation time 70575857 ps
CPU time 0.79 seconds
Started Jul 24 07:06:44 PM PDT 24
Finished Jul 24 07:06:45 PM PDT 24
Peak memory 199968 kb
Host smart-59f88a2b-e3ab-4bbb-a7c7-03e3e878a8ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918525550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3918525550
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.160438914
Short name T29
Test name
Test status
Simulation time 1895037224 ps
CPU time 7.88 seconds
Started Jul 24 07:06:48 PM PDT 24
Finished Jul 24 07:06:56 PM PDT 24
Peak memory 221756 kb
Host smart-342fe89b-7cea-44fc-972a-ad3828e49514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160438914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.160438914
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1716300730
Short name T251
Test name
Test status
Simulation time 243316319 ps
CPU time 1.23 seconds
Started Jul 24 07:06:46 PM PDT 24
Finished Jul 24 07:06:47 PM PDT 24
Peak memory 217512 kb
Host smart-0f21feee-b737-4b61-80fc-79b0db3c6afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716300730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1716300730
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2034513042
Short name T275
Test name
Test status
Simulation time 129616500 ps
CPU time 0.83 seconds
Started Jul 24 07:06:50 PM PDT 24
Finished Jul 24 07:06:51 PM PDT 24
Peak memory 199924 kb
Host smart-1c16e03f-64f2-440a-a8f2-a31c1153ee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034513042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2034513042
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1913018681
Short name T4
Test name
Test status
Simulation time 1596754626 ps
CPU time 6.24 seconds
Started Jul 24 07:06:46 PM PDT 24
Finished Jul 24 07:06:52 PM PDT 24
Peak memory 200428 kb
Host smart-a6cf737c-5135-46b4-a783-eabe1b489d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913018681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1913018681
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3607316136
Short name T300
Test name
Test status
Simulation time 158829069 ps
CPU time 1.21 seconds
Started Jul 24 07:06:46 PM PDT 24
Finished Jul 24 07:06:47 PM PDT 24
Peak memory 200144 kb
Host smart-b7960981-cb81-4d62-8ff2-2e700e0cf122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607316136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3607316136
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1615904473
Short name T336
Test name
Test status
Simulation time 114608631 ps
CPU time 1.3 seconds
Started Jul 24 07:06:41 PM PDT 24
Finished Jul 24 07:06:43 PM PDT 24
Peak memory 200352 kb
Host smart-efe12188-d563-472a-91aa-7040426dd353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615904473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1615904473
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1879506457
Short name T161
Test name
Test status
Simulation time 3050602309 ps
CPU time 11.63 seconds
Started Jul 24 07:06:52 PM PDT 24
Finished Jul 24 07:07:04 PM PDT 24
Peak memory 208668 kb
Host smart-f969f458-3a23-46d9-84a1-af57afabae28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879506457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1879506457
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3613234407
Short name T139
Test name
Test status
Simulation time 118827054 ps
CPU time 1.68 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:49 PM PDT 24
Peak memory 200160 kb
Host smart-3b5274ff-27dd-4e88-b9e0-0ba329415805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613234407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3613234407
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1712922467
Short name T410
Test name
Test status
Simulation time 129742674 ps
CPU time 1.17 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:49 PM PDT 24
Peak memory 200068 kb
Host smart-0740236a-f509-4086-8544-f458443562fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712922467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1712922467
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2216735945
Short name T462
Test name
Test status
Simulation time 78699073 ps
CPU time 0.86 seconds
Started Jul 24 07:06:45 PM PDT 24
Finished Jul 24 07:06:46 PM PDT 24
Peak memory 199968 kb
Host smart-449e1ad3-80bb-4f31-ae1e-2c7beece4dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216735945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2216735945
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3113283923
Short name T43
Test name
Test status
Simulation time 2153180259 ps
CPU time 8.44 seconds
Started Jul 24 07:06:52 PM PDT 24
Finished Jul 24 07:07:00 PM PDT 24
Peak memory 221784 kb
Host smart-93596566-d105-4bb0-88df-7a2b376dbf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113283923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3113283923
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1441584930
Short name T503
Test name
Test status
Simulation time 244413856 ps
CPU time 1.23 seconds
Started Jul 24 07:06:46 PM PDT 24
Finished Jul 24 07:06:47 PM PDT 24
Peak memory 217436 kb
Host smart-e6c4795b-5d53-44c9-958e-0c6ea98a9a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441584930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1441584930
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3364716690
Short name T243
Test name
Test status
Simulation time 121396881 ps
CPU time 0.81 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:48 PM PDT 24
Peak memory 200132 kb
Host smart-dc9dee10-12ff-439a-bcf6-2a508cd3c6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364716690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3364716690
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3706961011
Short name T90
Test name
Test status
Simulation time 1508827805 ps
CPU time 5.88 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:53 PM PDT 24
Peak memory 200468 kb
Host smart-e8a615de-9960-4c11-8b3f-288fb9dc154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706961011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3706961011
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1067129566
Short name T404
Test name
Test status
Simulation time 154234259 ps
CPU time 1.1 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:48 PM PDT 24
Peak memory 200088 kb
Host smart-5ff79c26-482e-4ce9-991c-d2921ec30fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067129566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1067129566
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1568736782
Short name T281
Test name
Test status
Simulation time 124855523 ps
CPU time 1.22 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:49 PM PDT 24
Peak memory 200372 kb
Host smart-c1b9c12f-6707-4aa8-a123-9d453a60220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568736782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1568736782
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.463064633
Short name T339
Test name
Test status
Simulation time 5252104949 ps
CPU time 21.31 seconds
Started Jul 24 07:06:45 PM PDT 24
Finished Jul 24 07:07:07 PM PDT 24
Peak memory 208732 kb
Host smart-f77d021b-af22-4aec-a629-1c08d50b2f9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463064633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.463064633
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3908225747
Short name T208
Test name
Test status
Simulation time 118864937 ps
CPU time 1.44 seconds
Started Jul 24 07:06:47 PM PDT 24
Finished Jul 24 07:06:48 PM PDT 24
Peak memory 200164 kb
Host smart-54666355-5980-4031-8a14-85be18438870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908225747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3908225747
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2045196092
Short name T168
Test name
Test status
Simulation time 127748197 ps
CPU time 1.04 seconds
Started Jul 24 07:06:52 PM PDT 24
Finished Jul 24 07:06:54 PM PDT 24
Peak memory 200136 kb
Host smart-994d7a7a-6623-45a6-9630-bbb0dd40f948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045196092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2045196092
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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