Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8528

1

T1

17

T3

80

T4

19

auto[1]

11314

1

T1

84

T2

4

T3

82

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6173	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6601	1			T1	27		T2	2		T3	54
reset_info_cp[2]	3109	1			T1	13		T2	1		T3	25
reset_info_cp[4]	4021	1			T1	21		T2	1		T3	40
reset_info_cp[8]	125	1			T3	1		T4	2		T25	2
reset_info_cp[16]	109	1			T3	1		T9	1		T14	2
reset_info_cp[32]	112	1			T4	1		T9	1		T12	1
reset_info_cp[64]	112	1			T1	1		T38	2		T81	2
reset_info_cp[128]	100	1			T4	1		T25	1		T26	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3172	1			T1	17		T3	29		T8	15
reset_info_cp[1]	auto[1]	2809	1			T1	9		T2	1		T3	24
reset_info_cp[2]	auto[0]	1026	1			T3	10		T9	2		T13	4
reset_info_cp[2]	auto[1]	2083	1			T1	13		T2	1		T3	15
reset_info_cp[4]	auto[0]	1438	1			T3	17		T9	8		T13	9
reset_info_cp[4]	auto[1]	2583	1			T1	21		T2	1		T3	23
reset_info_cp[8]	auto[0]	44	1			T3	1		T4	2		T68	1
reset_info_cp[8]	auto[1]	81	1			T25	2		T68	1		T35	2
reset_info_cp[16]	auto[0]	40	1			T14	1		T82	1		T61	1
reset_info_cp[16]	auto[1]	69	1			T3	1		T9	1		T14	1
reset_info_cp[32]	auto[0]	44	1			T4	1		T14	1		T61	1
reset_info_cp[32]	auto[1]	68	1			T9	1		T12	1		T13	1
reset_info_cp[64]	auto[0]	48	1			T38	1		T81	1		T65	1
reset_info_cp[64]	auto[1]	64	1			T1	1		T38	1		T81	1
reset_info_cp[128]	auto[0]	36	1			T4	1		T61	1		T73	1
reset_info_cp[128]	auto[1]	64	1			T25	1		T26	1		T35	1