Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T532 /workspace/coverage/default/10.rstmgr_sw_rst.1053459381 Jul 25 06:55:21 PM PDT 24 Jul 25 06:55:23 PM PDT 24 257569619 ps
T533 /workspace/coverage/default/1.rstmgr_stress_all.267491298 Jul 25 06:54:49 PM PDT 24 Jul 25 06:54:57 PM PDT 24 2019887249 ps
T534 /workspace/coverage/default/19.rstmgr_alert_test.2075837229 Jul 25 06:55:59 PM PDT 24 Jul 25 06:56:01 PM PDT 24 77871390 ps
T535 /workspace/coverage/default/5.rstmgr_reset.560202355 Jul 25 06:54:55 PM PDT 24 Jul 25 06:55:01 PM PDT 24 1468214805 ps
T536 /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3219319260 Jul 25 06:55:47 PM PDT 24 Jul 25 06:55:48 PM PDT 24 152403977 ps
T45 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1707816784 Jul 25 06:54:00 PM PDT 24 Jul 25 06:54:06 PM PDT 24 489071397 ps
T46 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1446354553 Jul 25 06:54:42 PM PDT 24 Jul 25 06:54:43 PM PDT 24 100995038 ps
T48 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3622610137 Jul 25 06:54:40 PM PDT 24 Jul 25 06:54:43 PM PDT 24 146066005 ps
T47 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1185621092 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:39 PM PDT 24 129161377 ps
T91 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3227308918 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:39 PM PDT 24 207320587 ps
T49 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1276452451 Jul 25 06:54:09 PM PDT 24 Jul 25 06:54:11 PM PDT 24 186611792 ps
T50 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3465968477 Jul 25 06:54:10 PM PDT 24 Jul 25 06:54:11 PM PDT 24 174406683 ps
T537 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2364644517 Jul 25 06:53:48 PM PDT 24 Jul 25 06:53:49 PM PDT 24 127405217 ps
T92 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4152423137 Jul 25 06:54:29 PM PDT 24 Jul 25 06:54:30 PM PDT 24 65365539 ps
T51 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1357338209 Jul 25 06:54:01 PM PDT 24 Jul 25 06:54:04 PM PDT 24 784046436 ps
T538 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1869537407 Jul 25 06:53:58 PM PDT 24 Jul 25 06:54:00 PM PDT 24 141859519 ps
T79 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4292712715 Jul 25 06:53:59 PM PDT 24 Jul 25 06:54:01 PM PDT 24 455869189 ps
T93 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2876773023 Jul 25 06:54:01 PM PDT 24 Jul 25 06:54:02 PM PDT 24 59738298 ps
T74 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2283557521 Jul 25 06:54:40 PM PDT 24 Jul 25 06:54:42 PM PDT 24 118201737 ps
T539 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.585492084 Jul 25 06:54:42 PM PDT 24 Jul 25 06:54:43 PM PDT 24 79041071 ps
T80 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3548871904 Jul 25 06:53:50 PM PDT 24 Jul 25 06:53:53 PM PDT 24 959963850 ps
T75 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3772405531 Jul 25 06:54:29 PM PDT 24 Jul 25 06:54:31 PM PDT 24 139082828 ps
T76 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1036210800 Jul 25 06:54:37 PM PDT 24 Jul 25 06:54:41 PM PDT 24 527111766 ps
T94 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1279824857 Jul 25 06:54:40 PM PDT 24 Jul 25 06:54:41 PM PDT 24 55150968 ps
T77 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1984846849 Jul 25 06:54:44 PM PDT 24 Jul 25 06:54:45 PM PDT 24 117408123 ps
T540 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1848769288 Jul 25 06:53:49 PM PDT 24 Jul 25 06:53:57 PM PDT 24 1549710065 ps
T95 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.679052466 Jul 25 06:54:00 PM PDT 24 Jul 25 06:54:02 PM PDT 24 202200553 ps
T78 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2633926346 Jul 25 06:54:37 PM PDT 24 Jul 25 06:54:40 PM PDT 24 962746800 ps
T541 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2702529837 Jul 25 06:54:39 PM PDT 24 Jul 25 06:54:41 PM PDT 24 141160995 ps
T96 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.712922637 Jul 25 06:54:42 PM PDT 24 Jul 25 06:54:44 PM PDT 24 122485666 ps
T101 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3621750400 Jul 25 06:53:49 PM PDT 24 Jul 25 06:53:51 PM PDT 24 443207106 ps
T100 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4096308823 Jul 25 06:53:58 PM PDT 24 Jul 25 06:54:01 PM PDT 24 404778212 ps
T103 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.252955012 Jul 25 06:54:11 PM PDT 24 Jul 25 06:54:13 PM PDT 24 511916196 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3246197800 Jul 25 06:53:48 PM PDT 24 Jul 25 06:53:50 PM PDT 24 159156184 ps
T543 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2312793741 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:40 PM PDT 24 131489469 ps
T104 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.165436681 Jul 25 06:54:41 PM PDT 24 Jul 25 06:54:45 PM PDT 24 948286597 ps
T544 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2298333342 Jul 25 06:53:48 PM PDT 24 Jul 25 06:53:50 PM PDT 24 234458982 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1777729298 Jul 25 06:53:49 PM PDT 24 Jul 25 06:53:51 PM PDT 24 149291485 ps
T546 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.691462757 Jul 25 06:54:26 PM PDT 24 Jul 25 06:54:29 PM PDT 24 786994085 ps
T97 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1768776220 Jul 25 06:54:21 PM PDT 24 Jul 25 06:54:22 PM PDT 24 77355114 ps
T547 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2049013900 Jul 25 06:54:10 PM PDT 24 Jul 25 06:54:11 PM PDT 24 67771902 ps
T548 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2266407325 Jul 25 06:54:29 PM PDT 24 Jul 25 06:54:30 PM PDT 24 87316050 ps
T98 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1859839346 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:40 PM PDT 24 130358393 ps
T102 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1389915850 Jul 25 06:53:46 PM PDT 24 Jul 25 06:53:48 PM PDT 24 455373707 ps
T99 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.929402273 Jul 25 06:54:28 PM PDT 24 Jul 25 06:54:30 PM PDT 24 245248952 ps
T549 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.105163254 Jul 25 06:54:28 PM PDT 24 Jul 25 06:54:30 PM PDT 24 106897646 ps
T105 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.908950534 Jul 25 06:54:42 PM PDT 24 Jul 25 06:54:45 PM PDT 24 422318681 ps
T550 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2701390795 Jul 25 06:54:08 PM PDT 24 Jul 25 06:54:09 PM PDT 24 140166501 ps
T551 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4016774552 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:39 PM PDT 24 86605937 ps
T552 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.437159718 Jul 25 06:54:07 PM PDT 24 Jul 25 06:54:08 PM PDT 24 181442923 ps
T553 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3030143041 Jul 25 06:54:18 PM PDT 24 Jul 25 06:54:20 PM PDT 24 426664215 ps
T554 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1938772435 Jul 25 06:54:18 PM PDT 24 Jul 25 06:54:19 PM PDT 24 190330122 ps
T555 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2302143588 Jul 25 06:54:07 PM PDT 24 Jul 25 06:54:08 PM PDT 24 67902462 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.78653463 Jul 25 06:53:49 PM PDT 24 Jul 25 06:53:50 PM PDT 24 83956207 ps
T557 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.428899067 Jul 25 06:54:18 PM PDT 24 Jul 25 06:54:20 PM PDT 24 523125462 ps
T558 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2843066720 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:41 PM PDT 24 405619550 ps
T559 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2865955972 Jul 25 06:53:48 PM PDT 24 Jul 25 06:53:50 PM PDT 24 133072079 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3815141766 Jul 25 06:53:48 PM PDT 24 Jul 25 06:53:49 PM PDT 24 66283008 ps
T561 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2266088163 Jul 25 06:54:29 PM PDT 24 Jul 25 06:54:30 PM PDT 24 195783994 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1805813698 Jul 25 06:54:09 PM PDT 24 Jul 25 06:54:10 PM PDT 24 94657041 ps
T563 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3064499227 Jul 25 06:54:42 PM PDT 24 Jul 25 06:54:43 PM PDT 24 116244920 ps
T564 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3914945945 Jul 25 06:54:29 PM PDT 24 Jul 25 06:54:32 PM PDT 24 797005401 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1078879140 Jul 25 06:53:49 PM PDT 24 Jul 25 06:53:51 PM PDT 24 218073291 ps
T106 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1492714090 Jul 25 06:54:30 PM PDT 24 Jul 25 06:54:32 PM PDT 24 434946130 ps
T566 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3820204978 Jul 25 06:53:46 PM PDT 24 Jul 25 06:53:49 PM PDT 24 181663710 ps
T567 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1160745008 Jul 25 06:53:59 PM PDT 24 Jul 25 06:54:10 PM PDT 24 2284087958 ps
T568 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.977415448 Jul 25 06:54:21 PM PDT 24 Jul 25 06:54:22 PM PDT 24 90450161 ps
T569 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3224624126 Jul 25 06:54:27 PM PDT 24 Jul 25 06:54:28 PM PDT 24 129166516 ps
T570 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1015006780 Jul 25 06:54:28 PM PDT 24 Jul 25 06:54:31 PM PDT 24 780908022 ps
T571 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1537278960 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:39 PM PDT 24 121237351 ps
T572 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.535733153 Jul 25 06:54:27 PM PDT 24 Jul 25 06:54:31 PM PDT 24 494497920 ps
T573 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2944826725 Jul 25 06:54:17 PM PDT 24 Jul 25 06:54:18 PM PDT 24 60660493 ps
T574 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2838674060 Jul 25 06:53:48 PM PDT 24 Jul 25 06:53:50 PM PDT 24 151535307 ps
T575 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1240714717 Jul 25 06:54:29 PM PDT 24 Jul 25 06:54:30 PM PDT 24 128039893 ps
T576 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.22552174 Jul 25 06:54:29 PM PDT 24 Jul 25 06:54:31 PM PDT 24 124659592 ps
T577 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3532743754 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:40 PM PDT 24 135159667 ps
T578 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2679337333 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:42 PM PDT 24 898206475 ps
T579 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.743435898 Jul 25 06:54:19 PM PDT 24 Jul 25 06:54:20 PM PDT 24 161772209 ps
T580 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.362308427 Jul 25 06:53:59 PM PDT 24 Jul 25 06:54:01 PM PDT 24 104200988 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2142425975 Jul 25 06:53:51 PM PDT 24 Jul 25 06:53:52 PM PDT 24 65899665 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.156909267 Jul 25 06:53:50 PM PDT 24 Jul 25 06:53:51 PM PDT 24 151400129 ps
T583 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1164904750 Jul 25 06:54:31 PM PDT 24 Jul 25 06:54:32 PM PDT 24 222864882 ps
T584 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3341191079 Jul 25 06:53:40 PM PDT 24 Jul 25 06:53:41 PM PDT 24 62324177 ps
T585 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2020859191 Jul 25 06:54:01 PM PDT 24 Jul 25 06:54:04 PM PDT 24 202610848 ps
T586 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1536573322 Jul 25 06:54:08 PM PDT 24 Jul 25 06:54:09 PM PDT 24 73485773 ps
T587 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1126848319 Jul 25 06:54:27 PM PDT 24 Jul 25 06:54:28 PM PDT 24 126025003 ps
T588 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.306964039 Jul 25 06:54:08 PM PDT 24 Jul 25 06:54:09 PM PDT 24 63286644 ps
T589 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2060223730 Jul 25 06:53:41 PM PDT 24 Jul 25 06:53:50 PM PDT 24 2273261928 ps
T590 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1206534832 Jul 25 06:54:08 PM PDT 24 Jul 25 06:54:11 PM PDT 24 791538715 ps
T591 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4262242460 Jul 25 06:54:40 PM PDT 24 Jul 25 06:54:42 PM PDT 24 193040393 ps
T592 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.356470831 Jul 25 06:53:47 PM PDT 24 Jul 25 06:53:49 PM PDT 24 200485020 ps
T593 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.383771845 Jul 25 06:54:28 PM PDT 24 Jul 25 06:54:29 PM PDT 24 54206223 ps
T594 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1681844151 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:39 PM PDT 24 178624013 ps
T595 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2206118632 Jul 25 06:54:27 PM PDT 24 Jul 25 06:54:28 PM PDT 24 72318010 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3836078512 Jul 25 06:54:01 PM PDT 24 Jul 25 06:54:03 PM PDT 24 109778258 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.571183538 Jul 25 06:53:58 PM PDT 24 Jul 25 06:53:59 PM PDT 24 146333404 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1305796980 Jul 25 06:53:51 PM PDT 24 Jul 25 06:53:53 PM PDT 24 158361417 ps
T114 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1324204793 Jul 25 06:54:28 PM PDT 24 Jul 25 06:54:31 PM PDT 24 898495311 ps
T599 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.456236477 Jul 25 06:54:29 PM PDT 24 Jul 25 06:54:31 PM PDT 24 347956958 ps
T600 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.567253893 Jul 25 06:54:27 PM PDT 24 Jul 25 06:54:28 PM PDT 24 71450241 ps
T601 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.120892370 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:39 PM PDT 24 85241399 ps
T602 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.565688797 Jul 25 06:54:42 PM PDT 24 Jul 25 06:54:43 PM PDT 24 63159036 ps
T603 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2464372663 Jul 25 06:53:59 PM PDT 24 Jul 25 06:54:01 PM PDT 24 206281884 ps
T604 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2338382183 Jul 25 06:54:10 PM PDT 24 Jul 25 06:54:14 PM PDT 24 508702117 ps
T605 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1589598737 Jul 25 06:54:30 PM PDT 24 Jul 25 06:54:31 PM PDT 24 96815508 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1345185410 Jul 25 06:54:38 PM PDT 24 Jul 25 06:54:40 PM PDT 24 422413590 ps
T607 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.937969544 Jul 25 06:53:59 PM PDT 24 Jul 25 06:54:00 PM PDT 24 67247801 ps
T608 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3112396880 Jul 25 06:54:18 PM PDT 24 Jul 25 06:54:21 PM PDT 24 423859521 ps
T609 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2177071630 Jul 25 06:54:07 PM PDT 24 Jul 25 06:54:09 PM PDT 24 506317211 ps
T610 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1630587852 Jul 25 06:54:07 PM PDT 24 Jul 25 06:54:09 PM PDT 24 101903033 ps
T611 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2315791430 Jul 25 06:53:40 PM PDT 24 Jul 25 06:53:41 PM PDT 24 107487676 ps
T612 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3624125971 Jul 25 06:53:50 PM PDT 24 Jul 25 06:53:51 PM PDT 24 225116072 ps
T613 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3821428058 Jul 25 06:53:48 PM PDT 24 Jul 25 06:53:53 PM PDT 24 1016546700 ps
T614 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1515684803 Jul 25 06:53:40 PM PDT 24 Jul 25 06:53:41 PM PDT 24 141064138 ps
T615 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.516020310 Jul 25 06:54:03 PM PDT 24 Jul 25 06:54:04 PM PDT 24 102158761 ps
T616 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3913974828 Jul 25 06:54:28 PM PDT 24 Jul 25 06:54:29 PM PDT 24 142331893 ps
T617 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3193716672 Jul 25 06:54:28 PM PDT 24 Jul 25 06:54:29 PM PDT 24 88071518 ps
T618 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3814498740 Jul 25 06:54:30 PM PDT 24 Jul 25 06:54:31 PM PDT 24 229998478 ps
T619 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1090248552 Jul 25 06:54:19 PM PDT 24 Jul 25 06:54:22 PM PDT 24 433327043 ps
T620 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1836607402 Jul 25 06:54:19 PM PDT 24 Jul 25 06:54:20 PM PDT 24 118077215 ps

Test location /workspace/coverage/default/19.rstmgr_stress_all.3267899256
Short name T3
Test name
Test status
Simulation time 4288985363 ps
CPU time 15.82 seconds
Started Jul 25 06:55:47 PM PDT 24
Finished Jul 25 06:56:03 PM PDT 24
Peak memory 208688 kb
Host smart-ce5edbcb-a725-4976-adcd-7822b6905507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267899256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3267899256
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3379323144
Short name T71
Test name
Test status
Simulation time 131909474 ps
CPU time 1.61 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 200204 kb
Host smart-f04b41af-c875-4c52-825c-898eb0031197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379323144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3379323144
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3465968477
Short name T50
Test name
Test status
Simulation time 174406683 ps
CPU time 1.6 seconds
Started Jul 25 06:54:10 PM PDT 24
Finished Jul 25 06:54:11 PM PDT 24
Peak memory 213788 kb
Host smart-b9801db5-15cd-4faf-954d-e6f4737d756b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465968477 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3465968477
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1126765759
Short name T52
Test name
Test status
Simulation time 16510500599 ps
CPU time 30.88 seconds
Started Jul 25 06:54:51 PM PDT 24
Finished Jul 25 06:55:22 PM PDT 24
Peak memory 218384 kb
Host smart-167855ec-17f3-45ed-a8fd-507fc1e6cb0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126765759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1126765759
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2013232551
Short name T26
Test name
Test status
Simulation time 1220584222 ps
CPU time 5.35 seconds
Started Jul 25 06:56:45 PM PDT 24
Finished Jul 25 06:56:50 PM PDT 24
Peak memory 217552 kb
Host smart-504e8282-5ea5-4e12-ae50-0322c85b2523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013232551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2013232551
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.4073763187
Short name T86
Test name
Test status
Simulation time 8972937379 ps
CPU time 29.12 seconds
Started Jul 25 06:55:33 PM PDT 24
Finished Jul 25 06:56:02 PM PDT 24
Peak memory 208604 kb
Host smart-6e676278-37aa-41a7-9861-819f7694518b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073763187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.4073763187
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.165436681
Short name T104
Test name
Test status
Simulation time 948286597 ps
CPU time 3.65 seconds
Started Jul 25 06:54:41 PM PDT 24
Finished Jul 25 06:54:45 PM PDT 24
Peak memory 200148 kb
Host smart-73028dce-2176-4b5f-8849-593e6b5b7a5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165436681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.165436681
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3412576488
Short name T65
Test name
Test status
Simulation time 248410166 ps
CPU time 1.41 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:45 PM PDT 24
Peak memory 200300 kb
Host smart-96d4e02a-c5b7-4472-bea1-5adef330404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412576488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3412576488
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1516612698
Short name T56
Test name
Test status
Simulation time 81607813 ps
CPU time 0.85 seconds
Started Jul 25 06:55:33 PM PDT 24
Finished Jul 25 06:55:34 PM PDT 24
Peak memory 199944 kb
Host smart-c34a1919-ff45-4b90-8186-fccd60fdf451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516612698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1516612698
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.690198768
Short name T113
Test name
Test status
Simulation time 2355255574 ps
CPU time 7.85 seconds
Started Jul 25 06:56:17 PM PDT 24
Finished Jul 25 06:56:25 PM PDT 24
Peak memory 217272 kb
Host smart-c04c0229-a1ba-43cf-8f55-a1242cc2d9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690198768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.690198768
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2821782990
Short name T62
Test name
Test status
Simulation time 112734737 ps
CPU time 0.98 seconds
Started Jul 25 06:54:50 PM PDT 24
Finished Jul 25 06:54:51 PM PDT 24
Peak memory 200148 kb
Host smart-cc425836-89e4-483b-b2e3-e5cad8bfd0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821782990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2821782990
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1777729298
Short name T545
Test name
Test status
Simulation time 149291485 ps
CPU time 1.4 seconds
Started Jul 25 06:53:49 PM PDT 24
Finished Jul 25 06:53:51 PM PDT 24
Peak memory 199860 kb
Host smart-acf25819-2264-4991-8218-4239ec11107a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777729298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1777729298
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3621750400
Short name T101
Test name
Test status
Simulation time 443207106 ps
CPU time 1.91 seconds
Started Jul 25 06:53:49 PM PDT 24
Finished Jul 25 06:53:51 PM PDT 24
Peak memory 200096 kb
Host smart-2a321292-6ddb-42da-9a03-444a53aba9b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621750400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3621750400
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1324204793
Short name T114
Test name
Test status
Simulation time 898495311 ps
CPU time 2.92 seconds
Started Jul 25 06:54:28 PM PDT 24
Finished Jul 25 06:54:31 PM PDT 24
Peak memory 200088 kb
Host smart-cf9753e2-f0ab-4f1d-a7ad-02b5999cbfbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324204793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1324204793
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3845105750
Short name T14
Test name
Test status
Simulation time 110748488 ps
CPU time 0.92 seconds
Started Jul 25 06:55:41 PM PDT 24
Finished Jul 25 06:55:42 PM PDT 24
Peak memory 200148 kb
Host smart-0579fb21-2ef1-471e-813b-ab0394c80e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845105750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3845105750
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3656184845
Short name T34
Test name
Test status
Simulation time 1895222540 ps
CPU time 6.8 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:55:41 PM PDT 24
Peak memory 217820 kb
Host smart-411f9db4-37ad-40eb-a866-521208b86a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656184845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3656184845
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.929402273
Short name T99
Test name
Test status
Simulation time 245248952 ps
CPU time 1.53 seconds
Started Jul 25 06:54:28 PM PDT 24
Finished Jul 25 06:54:30 PM PDT 24
Peak memory 200068 kb
Host smart-737b03b6-f107-49d8-b970-240e33480b39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929402273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.929402273
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2664639854
Short name T18
Test name
Test status
Simulation time 98275407 ps
CPU time 0.76 seconds
Started Jul 25 06:55:32 PM PDT 24
Finished Jul 25 06:55:33 PM PDT 24
Peak memory 199952 kb
Host smart-f74bbba5-2ee1-4811-806c-45b5a57814b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664639854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2664639854
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3820204978
Short name T566
Test name
Test status
Simulation time 181663710 ps
CPU time 2.51 seconds
Started Jul 25 06:53:46 PM PDT 24
Finished Jul 25 06:53:49 PM PDT 24
Peak memory 216284 kb
Host smart-154088bc-54aa-4e10-86e5-5984ab9d560f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820204978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3820204978
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3548871904
Short name T80
Test name
Test status
Simulation time 959963850 ps
CPU time 2.99 seconds
Started Jul 25 06:53:50 PM PDT 24
Finished Jul 25 06:53:53 PM PDT 24
Peak memory 200080 kb
Host smart-ef24d49d-60f6-4436-bb87-517ead3ab0fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548871904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3548871904
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2315791430
Short name T611
Test name
Test status
Simulation time 107487676 ps
CPU time 1.32 seconds
Started Jul 25 06:53:40 PM PDT 24
Finished Jul 25 06:53:41 PM PDT 24
Peak memory 200004 kb
Host smart-402262b0-3876-4bce-a50d-5550e119d18f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315791430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
315791430
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2060223730
Short name T589
Test name
Test status
Simulation time 2273261928 ps
CPU time 9.33 seconds
Started Jul 25 06:53:41 PM PDT 24
Finished Jul 25 06:53:50 PM PDT 24
Peak memory 200120 kb
Host smart-f5a33ac7-c2fa-4e94-9fe9-1c10eda6b9d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060223730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
060223730
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1515684803
Short name T614
Test name
Test status
Simulation time 141064138 ps
CPU time 0.88 seconds
Started Jul 25 06:53:40 PM PDT 24
Finished Jul 25 06:53:41 PM PDT 24
Peak memory 199876 kb
Host smart-5547c93c-03ae-4154-84a9-26ed577f1d2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515684803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
515684803
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1305796980
Short name T598
Test name
Test status
Simulation time 158361417 ps
CPU time 1.39 seconds
Started Jul 25 06:53:51 PM PDT 24
Finished Jul 25 06:53:53 PM PDT 24
Peak memory 208192 kb
Host smart-b213b506-2f10-4e5e-a6cd-bea07f0c94fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305796980 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1305796980
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3341191079
Short name T584
Test name
Test status
Simulation time 62324177 ps
CPU time 0.82 seconds
Started Jul 25 06:53:40 PM PDT 24
Finished Jul 25 06:53:41 PM PDT 24
Peak memory 199860 kb
Host smart-2de7d385-c2db-40ee-9373-046d2709f531
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341191079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3341191079
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3624125971
Short name T612
Test name
Test status
Simulation time 225116072 ps
CPU time 1.56 seconds
Started Jul 25 06:53:50 PM PDT 24
Finished Jul 25 06:53:51 PM PDT 24
Peak memory 200148 kb
Host smart-ebc10359-718e-4910-86c9-1ba325e19602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624125971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3624125971
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1389915850
Short name T102
Test name
Test status
Simulation time 455373707 ps
CPU time 1.89 seconds
Started Jul 25 06:53:46 PM PDT 24
Finished Jul 25 06:53:48 PM PDT 24
Peak memory 200056 kb
Host smart-da7030ab-0e7d-4df0-b552-aaa1cb80e3ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389915850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1389915850
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2298333342
Short name T544
Test name
Test status
Simulation time 234458982 ps
CPU time 1.65 seconds
Started Jul 25 06:53:48 PM PDT 24
Finished Jul 25 06:53:50 PM PDT 24
Peak memory 200024 kb
Host smart-82b1cb97-14cd-4015-bf0e-0147ab4b5dd3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298333342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
298333342
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1848769288
Short name T540
Test name
Test status
Simulation time 1549710065 ps
CPU time 8.14 seconds
Started Jul 25 06:53:49 PM PDT 24
Finished Jul 25 06:53:57 PM PDT 24
Peak memory 200064 kb
Host smart-652e32ef-22cb-4938-9e39-9174b375fcd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848769288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
848769288
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.78653463
Short name T556
Test name
Test status
Simulation time 83956207 ps
CPU time 0.78 seconds
Started Jul 25 06:53:49 PM PDT 24
Finished Jul 25 06:53:50 PM PDT 24
Peak memory 199792 kb
Host smart-1f0ec625-be4a-41cb-bcb1-81bc20df81cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78653463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.78653463
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.356470831
Short name T592
Test name
Test status
Simulation time 200485020 ps
CPU time 1.36 seconds
Started Jul 25 06:53:47 PM PDT 24
Finished Jul 25 06:53:49 PM PDT 24
Peak memory 208176 kb
Host smart-88b14022-6de3-40ba-9b8f-62c678a4486f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356470831 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.356470831
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3815141766
Short name T560
Test name
Test status
Simulation time 66283008 ps
CPU time 0.78 seconds
Started Jul 25 06:53:48 PM PDT 24
Finished Jul 25 06:53:49 PM PDT 24
Peak memory 199812 kb
Host smart-7592a03f-ec06-4fd7-95cf-e3c9696861fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815141766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3815141766
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2865955972
Short name T559
Test name
Test status
Simulation time 133072079 ps
CPU time 1.23 seconds
Started Jul 25 06:53:48 PM PDT 24
Finished Jul 25 06:53:50 PM PDT 24
Peak memory 200064 kb
Host smart-b2417f8a-aa55-41d5-81ff-c47a59fba5d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865955972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2865955972
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1126848319
Short name T587
Test name
Test status
Simulation time 126025003 ps
CPU time 0.94 seconds
Started Jul 25 06:54:27 PM PDT 24
Finished Jul 25 06:54:28 PM PDT 24
Peak memory 200016 kb
Host smart-3dea492a-28a1-49f1-81ba-ffc097646560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126848319 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1126848319
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2266407325
Short name T548
Test name
Test status
Simulation time 87316050 ps
CPU time 0.88 seconds
Started Jul 25 06:54:29 PM PDT 24
Finished Jul 25 06:54:30 PM PDT 24
Peak memory 199876 kb
Host smart-9d252666-52c3-49a1-ab4d-ce54796c32b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266407325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2266407325
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1164904750
Short name T583
Test name
Test status
Simulation time 222864882 ps
CPU time 1.63 seconds
Started Jul 25 06:54:31 PM PDT 24
Finished Jul 25 06:54:32 PM PDT 24
Peak memory 200056 kb
Host smart-fa8083b3-6385-4dbe-ba8d-d5b576390eb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164904750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1164904750
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3772405531
Short name T75
Test name
Test status
Simulation time 139082828 ps
CPU time 1.77 seconds
Started Jul 25 06:54:29 PM PDT 24
Finished Jul 25 06:54:31 PM PDT 24
Peak memory 208184 kb
Host smart-a9322ca5-54c7-4c58-b0ce-478ad09f279b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772405531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3772405531
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3224624126
Short name T569
Test name
Test status
Simulation time 129166516 ps
CPU time 0.99 seconds
Started Jul 25 06:54:27 PM PDT 24
Finished Jul 25 06:54:28 PM PDT 24
Peak memory 200004 kb
Host smart-f2c5c53c-9953-4ff7-ab45-70b02fbc668a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224624126 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3224624126
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.567253893
Short name T600
Test name
Test status
Simulation time 71450241 ps
CPU time 0.79 seconds
Started Jul 25 06:54:27 PM PDT 24
Finished Jul 25 06:54:28 PM PDT 24
Peak memory 199860 kb
Host smart-d4d92986-32a6-4bdd-9ac8-a69fcbbf9590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567253893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.567253893
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3814498740
Short name T618
Test name
Test status
Simulation time 229998478 ps
CPU time 1.44 seconds
Started Jul 25 06:54:30 PM PDT 24
Finished Jul 25 06:54:31 PM PDT 24
Peak memory 200136 kb
Host smart-265bc168-d518-4c79-bcca-637d7b14804b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814498740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3814498740
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.535733153
Short name T572
Test name
Test status
Simulation time 494497920 ps
CPU time 3.1 seconds
Started Jul 25 06:54:27 PM PDT 24
Finished Jul 25 06:54:31 PM PDT 24
Peak memory 211832 kb
Host smart-c5a3ec24-27a2-4d57-9ecd-5d9e4d7dd703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535733153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.535733153
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1492714090
Short name T106
Test name
Test status
Simulation time 434946130 ps
CPU time 1.74 seconds
Started Jul 25 06:54:30 PM PDT 24
Finished Jul 25 06:54:32 PM PDT 24
Peak memory 200080 kb
Host smart-89e9bb52-12ca-4985-b857-f6404e1cf3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492714090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1492714090
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3913974828
Short name T616
Test name
Test status
Simulation time 142331893 ps
CPU time 1.1 seconds
Started Jul 25 06:54:28 PM PDT 24
Finished Jul 25 06:54:29 PM PDT 24
Peak memory 199940 kb
Host smart-308ec0a1-3dd2-48a6-be8f-85b84ba2f2fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913974828 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3913974828
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.383771845
Short name T593
Test name
Test status
Simulation time 54206223 ps
CPU time 0.76 seconds
Started Jul 25 06:54:28 PM PDT 24
Finished Jul 25 06:54:29 PM PDT 24
Peak memory 199868 kb
Host smart-3b5f4286-e5c2-4139-b409-f114f5fa92fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383771845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.383771845
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.105163254
Short name T549
Test name
Test status
Simulation time 106897646 ps
CPU time 1.53 seconds
Started Jul 25 06:54:28 PM PDT 24
Finished Jul 25 06:54:30 PM PDT 24
Peak memory 208192 kb
Host smart-1818c6e0-741d-4dd1-9996-9a91463893d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105163254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.105163254
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1015006780
Short name T570
Test name
Test status
Simulation time 780908022 ps
CPU time 2.98 seconds
Started Jul 25 06:54:28 PM PDT 24
Finished Jul 25 06:54:31 PM PDT 24
Peak memory 200092 kb
Host smart-a2d8cc29-655c-4479-ba89-b7afb9a63edb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015006780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1015006780
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2266088163
Short name T561
Test name
Test status
Simulation time 195783994 ps
CPU time 1.23 seconds
Started Jul 25 06:54:29 PM PDT 24
Finished Jul 25 06:54:30 PM PDT 24
Peak memory 199972 kb
Host smart-233390ef-0b17-40ea-985d-2f9a4d2aad38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266088163 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2266088163
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2206118632
Short name T595
Test name
Test status
Simulation time 72318010 ps
CPU time 0.78 seconds
Started Jul 25 06:54:27 PM PDT 24
Finished Jul 25 06:54:28 PM PDT 24
Peak memory 199792 kb
Host smart-7c632250-1afa-442d-a36b-f7610f87fcd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206118632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2206118632
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1589598737
Short name T605
Test name
Test status
Simulation time 96815508 ps
CPU time 1.29 seconds
Started Jul 25 06:54:30 PM PDT 24
Finished Jul 25 06:54:31 PM PDT 24
Peak memory 200120 kb
Host smart-92627afe-ca1a-4e2b-971b-cc98de1c003e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589598737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1589598737
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.456236477
Short name T599
Test name
Test status
Simulation time 347956958 ps
CPU time 2.28 seconds
Started Jul 25 06:54:29 PM PDT 24
Finished Jul 25 06:54:31 PM PDT 24
Peak memory 208268 kb
Host smart-e50a117f-b242-4d20-be35-32c4b1a2904f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456236477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.456236477
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3914945945
Short name T564
Test name
Test status
Simulation time 797005401 ps
CPU time 2.77 seconds
Started Jul 25 06:54:29 PM PDT 24
Finished Jul 25 06:54:32 PM PDT 24
Peak memory 200064 kb
Host smart-f0a4f095-1812-446d-ba07-fd5f182b7165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914945945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3914945945
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3064499227
Short name T563
Test name
Test status
Simulation time 116244920 ps
CPU time 0.95 seconds
Started Jul 25 06:54:42 PM PDT 24
Finished Jul 25 06:54:43 PM PDT 24
Peak memory 199992 kb
Host smart-c583f5fc-af65-4354-85a7-206d2b1e81e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064499227 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3064499227
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4152423137
Short name T92
Test name
Test status
Simulation time 65365539 ps
CPU time 0.79 seconds
Started Jul 25 06:54:29 PM PDT 24
Finished Jul 25 06:54:30 PM PDT 24
Peak memory 199912 kb
Host smart-462054c5-ba29-4294-8b04-c7a87c5b6238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152423137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.4152423137
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3227308918
Short name T91
Test name
Test status
Simulation time 207320587 ps
CPU time 1.5 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:39 PM PDT 24
Peak memory 200052 kb
Host smart-b6dc03a0-1989-4c29-8e9f-45a45197ecf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227308918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3227308918
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.22552174
Short name T576
Test name
Test status
Simulation time 124659592 ps
CPU time 1.79 seconds
Started Jul 25 06:54:29 PM PDT 24
Finished Jul 25 06:54:31 PM PDT 24
Peak memory 208136 kb
Host smart-c49107b8-c863-4abf-ac6b-dbab5f9a0804
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22552174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.22552174
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.691462757
Short name T546
Test name
Test status
Simulation time 786994085 ps
CPU time 2.63 seconds
Started Jul 25 06:54:26 PM PDT 24
Finished Jul 25 06:54:29 PM PDT 24
Peak memory 200080 kb
Host smart-1aac3f13-2528-4fd1-afaf-42f5961ae9f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691462757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.691462757
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1185621092
Short name T47
Test name
Test status
Simulation time 129161377 ps
CPU time 1.06 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:39 PM PDT 24
Peak memory 208168 kb
Host smart-fa5a230e-b60f-4b3b-8cc4-dc450ebd75f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185621092 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1185621092
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.120892370
Short name T601
Test name
Test status
Simulation time 85241399 ps
CPU time 0.87 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:39 PM PDT 24
Peak memory 199876 kb
Host smart-6dca59b6-0435-4908-a917-4b9ec2e507c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120892370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.120892370
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1446354553
Short name T46
Test name
Test status
Simulation time 100995038 ps
CPU time 1.25 seconds
Started Jul 25 06:54:42 PM PDT 24
Finished Jul 25 06:54:43 PM PDT 24
Peak memory 200068 kb
Host smart-60777762-a582-4ada-9069-f9339f3b5fbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446354553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1446354553
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2702529837
Short name T541
Test name
Test status
Simulation time 141160995 ps
CPU time 2.09 seconds
Started Jul 25 06:54:39 PM PDT 24
Finished Jul 25 06:54:41 PM PDT 24
Peak memory 211572 kb
Host smart-93662704-a600-42a6-9cf8-5e0dfc26ba50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702529837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2702529837
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2633926346
Short name T78
Test name
Test status
Simulation time 962746800 ps
CPU time 3.34 seconds
Started Jul 25 06:54:37 PM PDT 24
Finished Jul 25 06:54:40 PM PDT 24
Peak memory 200072 kb
Host smart-fd504400-6191-46a9-ad08-63bc512cb52a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633926346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2633926346
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1681844151
Short name T594
Test name
Test status
Simulation time 178624013 ps
CPU time 1.08 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:39 PM PDT 24
Peak memory 208188 kb
Host smart-b7cd8dfd-aeb2-4ccc-aaad-634d0d0ef68f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681844151 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1681844151
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.565688797
Short name T602
Test name
Test status
Simulation time 63159036 ps
CPU time 0.78 seconds
Started Jul 25 06:54:42 PM PDT 24
Finished Jul 25 06:54:43 PM PDT 24
Peak memory 199872 kb
Host smart-76e5ef08-9240-4251-aa20-4814169b2fde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565688797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.565688797
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1537278960
Short name T571
Test name
Test status
Simulation time 121237351 ps
CPU time 0.98 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:39 PM PDT 24
Peak memory 199932 kb
Host smart-d1fab15e-4ca3-4cb4-b5f7-9959dea373aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537278960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1537278960
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2843066720
Short name T558
Test name
Test status
Simulation time 405619550 ps
CPU time 3.16 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:41 PM PDT 24
Peak memory 216252 kb
Host smart-41c776ab-b842-4253-a07f-5cf627ac726e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843066720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2843066720
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1345185410
Short name T606
Test name
Test status
Simulation time 422413590 ps
CPU time 1.87 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:40 PM PDT 24
Peak memory 200068 kb
Host smart-02440c84-63be-4d47-b9a4-14834c19420f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345185410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1345185410
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1984846849
Short name T77
Test name
Test status
Simulation time 117408123 ps
CPU time 0.91 seconds
Started Jul 25 06:54:44 PM PDT 24
Finished Jul 25 06:54:45 PM PDT 24
Peak memory 199948 kb
Host smart-389ad5b2-4021-461c-8653-ccce37e77e51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984846849 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1984846849
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.585492084
Short name T539
Test name
Test status
Simulation time 79041071 ps
CPU time 0.8 seconds
Started Jul 25 06:54:42 PM PDT 24
Finished Jul 25 06:54:43 PM PDT 24
Peak memory 199872 kb
Host smart-dab492fa-a183-422a-a2a9-80eb56020407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585492084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.585492084
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3532743754
Short name T577
Test name
Test status
Simulation time 135159667 ps
CPU time 1.25 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:40 PM PDT 24
Peak memory 200024 kb
Host smart-f8251150-aec6-4a9e-8dca-26752a5870b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532743754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3532743754
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1036210800
Short name T76
Test name
Test status
Simulation time 527111766 ps
CPU time 3.3 seconds
Started Jul 25 06:54:37 PM PDT 24
Finished Jul 25 06:54:41 PM PDT 24
Peak memory 212096 kb
Host smart-3dc57b61-c586-459d-a2a5-952e0cdfb681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036210800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1036210800
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2312793741
Short name T543
Test name
Test status
Simulation time 131489469 ps
CPU time 1.15 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:40 PM PDT 24
Peak memory 208212 kb
Host smart-79b75fee-012d-4552-8d7a-6a46ae2e4ab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312793741 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2312793741
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4016774552
Short name T551
Test name
Test status
Simulation time 86605937 ps
CPU time 0.88 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:39 PM PDT 24
Peak memory 199912 kb
Host smart-be79a466-9dd8-4a19-9613-8825c21ac4b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016774552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4016774552
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.712922637
Short name T96
Test name
Test status
Simulation time 122485666 ps
CPU time 1.13 seconds
Started Jul 25 06:54:42 PM PDT 24
Finished Jul 25 06:54:44 PM PDT 24
Peak memory 199928 kb
Host smart-8f172139-cb63-4fb6-ab67-02c831aa70d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712922637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.712922637
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2283557521
Short name T74
Test name
Test status
Simulation time 118201737 ps
CPU time 1.68 seconds
Started Jul 25 06:54:40 PM PDT 24
Finished Jul 25 06:54:42 PM PDT 24
Peak memory 208196 kb
Host smart-61a633f6-65f0-43c7-90de-02d4c20e1880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283557521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2283557521
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2679337333
Short name T578
Test name
Test status
Simulation time 898206475 ps
CPU time 3.28 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:42 PM PDT 24
Peak memory 200128 kb
Host smart-ae63db86-1242-4e7a-8524-d557b293e714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679337333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2679337333
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4262242460
Short name T591
Test name
Test status
Simulation time 193040393 ps
CPU time 1.24 seconds
Started Jul 25 06:54:40 PM PDT 24
Finished Jul 25 06:54:42 PM PDT 24
Peak memory 208148 kb
Host smart-1b163d54-86f0-4de3-a646-bbb563486510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262242460 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4262242460
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1279824857
Short name T94
Test name
Test status
Simulation time 55150968 ps
CPU time 0.74 seconds
Started Jul 25 06:54:40 PM PDT 24
Finished Jul 25 06:54:41 PM PDT 24
Peak memory 199868 kb
Host smart-dac6cf32-f0b1-4d61-b73d-d849edba39ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279824857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1279824857
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1859839346
Short name T98
Test name
Test status
Simulation time 130358393 ps
CPU time 1.16 seconds
Started Jul 25 06:54:38 PM PDT 24
Finished Jul 25 06:54:40 PM PDT 24
Peak memory 199800 kb
Host smart-be2517ae-ff4e-4d16-b122-6dfb8b943f33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859839346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1859839346
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3622610137
Short name T48
Test name
Test status
Simulation time 146066005 ps
CPU time 2.2 seconds
Started Jul 25 06:54:40 PM PDT 24
Finished Jul 25 06:54:43 PM PDT 24
Peak memory 208232 kb
Host smart-99188803-9b99-4aad-8456-28369314830f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622610137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3622610137
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.908950534
Short name T105
Test name
Test status
Simulation time 422318681 ps
CPU time 1.74 seconds
Started Jul 25 06:54:42 PM PDT 24
Finished Jul 25 06:54:45 PM PDT 24
Peak memory 200076 kb
Host smart-7d162ed3-4f2e-42bd-9c3e-bfcca7627df6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908950534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.908950534
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2838674060
Short name T574
Test name
Test status
Simulation time 151535307 ps
CPU time 1.94 seconds
Started Jul 25 06:53:48 PM PDT 24
Finished Jul 25 06:53:50 PM PDT 24
Peak memory 200068 kb
Host smart-465ddc06-1ce5-4241-b03d-99b22e5c4cda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838674060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
838674060
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3821428058
Short name T613
Test name
Test status
Simulation time 1016546700 ps
CPU time 4.88 seconds
Started Jul 25 06:53:48 PM PDT 24
Finished Jul 25 06:53:53 PM PDT 24
Peak memory 200060 kb
Host smart-5a5aee37-1acd-4416-90bf-e118a9ee1309
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821428058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
821428058
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2364644517
Short name T537
Test name
Test status
Simulation time 127405217 ps
CPU time 0.86 seconds
Started Jul 25 06:53:48 PM PDT 24
Finished Jul 25 06:53:49 PM PDT 24
Peak memory 199872 kb
Host smart-11694ae3-b8c4-4c62-8e51-aefe81144041
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364644517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
364644517
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3246197800
Short name T542
Test name
Test status
Simulation time 159156184 ps
CPU time 1.47 seconds
Started Jul 25 06:53:48 PM PDT 24
Finished Jul 25 06:53:50 PM PDT 24
Peak memory 208280 kb
Host smart-a280e331-13d5-4158-be4e-a27cc408e668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246197800 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3246197800
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2142425975
Short name T581
Test name
Test status
Simulation time 65899665 ps
CPU time 0.77 seconds
Started Jul 25 06:53:51 PM PDT 24
Finished Jul 25 06:53:52 PM PDT 24
Peak memory 199872 kb
Host smart-1a52b471-1071-4810-851a-70191a63d801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142425975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2142425975
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.156909267
Short name T582
Test name
Test status
Simulation time 151400129 ps
CPU time 1.16 seconds
Started Jul 25 06:53:50 PM PDT 24
Finished Jul 25 06:53:51 PM PDT 24
Peak memory 199936 kb
Host smart-a414de1f-b88d-4ecb-a774-92b24ee2de19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156909267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.156909267
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1078879140
Short name T565
Test name
Test status
Simulation time 218073291 ps
CPU time 1.78 seconds
Started Jul 25 06:53:49 PM PDT 24
Finished Jul 25 06:53:51 PM PDT 24
Peak memory 208060 kb
Host smart-043e1efa-a793-46a4-a71c-50cb1405ab4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078879140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1078879140
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.362308427
Short name T580
Test name
Test status
Simulation time 104200988 ps
CPU time 1.31 seconds
Started Jul 25 06:53:59 PM PDT 24
Finished Jul 25 06:54:01 PM PDT 24
Peak memory 200008 kb
Host smart-8b325d0f-0c36-4baf-ad8d-b496bfaf4c7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362308427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.362308427
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1160745008
Short name T567
Test name
Test status
Simulation time 2284087958 ps
CPU time 10.94 seconds
Started Jul 25 06:53:59 PM PDT 24
Finished Jul 25 06:54:10 PM PDT 24
Peak memory 200076 kb
Host smart-b8ff5ba4-4bac-451b-8aea-cfec3674ceaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160745008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
160745008
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.571183538
Short name T597
Test name
Test status
Simulation time 146333404 ps
CPU time 0.99 seconds
Started Jul 25 06:53:58 PM PDT 24
Finished Jul 25 06:53:59 PM PDT 24
Peak memory 199872 kb
Host smart-ac40b109-7062-47e2-b266-74fc2d335d50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571183538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.571183538
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3836078512
Short name T596
Test name
Test status
Simulation time 109778258 ps
CPU time 1.13 seconds
Started Jul 25 06:54:01 PM PDT 24
Finished Jul 25 06:54:03 PM PDT 24
Peak memory 208192 kb
Host smart-1765a535-bb6c-4e69-ae76-9350675faa8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836078512 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3836078512
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.937969544
Short name T607
Test name
Test status
Simulation time 67247801 ps
CPU time 0.8 seconds
Started Jul 25 06:53:59 PM PDT 24
Finished Jul 25 06:54:00 PM PDT 24
Peak memory 199800 kb
Host smart-8a9a9b56-5367-4e8d-a961-94271c50e6fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937969544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.937969544
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2464372663
Short name T603
Test name
Test status
Simulation time 206281884 ps
CPU time 1.51 seconds
Started Jul 25 06:53:59 PM PDT 24
Finished Jul 25 06:54:01 PM PDT 24
Peak memory 200084 kb
Host smart-08955b80-e623-49bc-a842-be8c594c2048
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464372663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2464372663
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2020859191
Short name T585
Test name
Test status
Simulation time 202610848 ps
CPU time 2.96 seconds
Started Jul 25 06:54:01 PM PDT 24
Finished Jul 25 06:54:04 PM PDT 24
Peak memory 216172 kb
Host smart-5623a4cb-c5ff-4c71-b9ff-405012d19fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020859191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2020859191
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4292712715
Short name T79
Test name
Test status
Simulation time 455869189 ps
CPU time 1.85 seconds
Started Jul 25 06:53:59 PM PDT 24
Finished Jul 25 06:54:01 PM PDT 24
Peak memory 200056 kb
Host smart-0e1db2ac-f510-4918-b9df-2d1b693788b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292712715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.4292712715
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.516020310
Short name T615
Test name
Test status
Simulation time 102158761 ps
CPU time 1.48 seconds
Started Jul 25 06:54:03 PM PDT 24
Finished Jul 25 06:54:04 PM PDT 24
Peak memory 208252 kb
Host smart-7316783e-31ea-4242-8c00-6ed340adcb05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516020310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.516020310
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1707816784
Short name T45
Test name
Test status
Simulation time 489071397 ps
CPU time 5.75 seconds
Started Jul 25 06:54:00 PM PDT 24
Finished Jul 25 06:54:06 PM PDT 24
Peak memory 216368 kb
Host smart-2592ab00-ec41-4fee-963e-590083b096d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707816784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
707816784
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1869537407
Short name T538
Test name
Test status
Simulation time 141859519 ps
CPU time 0.98 seconds
Started Jul 25 06:53:58 PM PDT 24
Finished Jul 25 06:54:00 PM PDT 24
Peak memory 199776 kb
Host smart-d3c42257-9d19-4b92-89e5-2a988c758d64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869537407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
869537407
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.437159718
Short name T552
Test name
Test status
Simulation time 181442923 ps
CPU time 1.11 seconds
Started Jul 25 06:54:07 PM PDT 24
Finished Jul 25 06:54:08 PM PDT 24
Peak memory 199952 kb
Host smart-c9295530-0e85-4fe4-b9a2-85be94dcc86c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437159718 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.437159718
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2876773023
Short name T93
Test name
Test status
Simulation time 59738298 ps
CPU time 0.85 seconds
Started Jul 25 06:54:01 PM PDT 24
Finished Jul 25 06:54:02 PM PDT 24
Peak memory 199872 kb
Host smart-b7d4546a-2f46-42c5-82ee-558fa18eede5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876773023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2876773023
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.679052466
Short name T95
Test name
Test status
Simulation time 202200553 ps
CPU time 1.54 seconds
Started Jul 25 06:54:00 PM PDT 24
Finished Jul 25 06:54:02 PM PDT 24
Peak memory 200096 kb
Host smart-ddb56c01-e8d2-4919-972e-a959c06763dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679052466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.679052466
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4096308823
Short name T100
Test name
Test status
Simulation time 404778212 ps
CPU time 2.77 seconds
Started Jul 25 06:53:58 PM PDT 24
Finished Jul 25 06:54:01 PM PDT 24
Peak memory 208188 kb
Host smart-819a2505-b0c7-4e0b-b9ea-7c0177da113b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096308823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.4096308823
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1357338209
Short name T51
Test name
Test status
Simulation time 784046436 ps
CPU time 2.99 seconds
Started Jul 25 06:54:01 PM PDT 24
Finished Jul 25 06:54:04 PM PDT 24
Peak memory 200196 kb
Host smart-9b73d26a-e7b5-4e7d-97c9-5f2df12c107c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357338209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1357338209
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2302143588
Short name T555
Test name
Test status
Simulation time 67902462 ps
CPU time 0.81 seconds
Started Jul 25 06:54:07 PM PDT 24
Finished Jul 25 06:54:08 PM PDT 24
Peak memory 199852 kb
Host smart-daccb9a6-9651-4c03-8a3b-27e92cefd576
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302143588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2302143588
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1536573322
Short name T586
Test name
Test status
Simulation time 73485773 ps
CPU time 0.93 seconds
Started Jul 25 06:54:08 PM PDT 24
Finished Jul 25 06:54:09 PM PDT 24
Peak memory 199944 kb
Host smart-08da1ccb-2314-4889-b44e-326ff76b683f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536573322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1536573322
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1630587852
Short name T610
Test name
Test status
Simulation time 101903033 ps
CPU time 1.44 seconds
Started Jul 25 06:54:07 PM PDT 24
Finished Jul 25 06:54:09 PM PDT 24
Peak memory 208216 kb
Host smart-1f28d271-503d-4072-be7e-69632c4e0507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630587852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1630587852
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2177071630
Short name T609
Test name
Test status
Simulation time 506317211 ps
CPU time 1.84 seconds
Started Jul 25 06:54:07 PM PDT 24
Finished Jul 25 06:54:09 PM PDT 24
Peak memory 200136 kb
Host smart-a82577a9-25d6-4b18-9d97-0706a881e76f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177071630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2177071630
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1276452451
Short name T49
Test name
Test status
Simulation time 186611792 ps
CPU time 1.34 seconds
Started Jul 25 06:54:09 PM PDT 24
Finished Jul 25 06:54:11 PM PDT 24
Peak memory 208164 kb
Host smart-4322c6b8-770f-4df8-8575-b467dad0509f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276452451 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1276452451
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.306964039
Short name T588
Test name
Test status
Simulation time 63286644 ps
CPU time 0.81 seconds
Started Jul 25 06:54:08 PM PDT 24
Finished Jul 25 06:54:09 PM PDT 24
Peak memory 199860 kb
Host smart-97bdf26a-2444-4298-ad61-27c58236d077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306964039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.306964039
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2701390795
Short name T550
Test name
Test status
Simulation time 140166501 ps
CPU time 1.17 seconds
Started Jul 25 06:54:08 PM PDT 24
Finished Jul 25 06:54:09 PM PDT 24
Peak memory 199940 kb
Host smart-78582e23-c8c2-4520-bc1b-f5e4ddfa984b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701390795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2701390795
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2338382183
Short name T604
Test name
Test status
Simulation time 508702117 ps
CPU time 3.53 seconds
Started Jul 25 06:54:10 PM PDT 24
Finished Jul 25 06:54:14 PM PDT 24
Peak memory 208240 kb
Host smart-4409e71f-dcda-4359-b49a-f71919a4d07f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338382183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2338382183
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.252955012
Short name T103
Test name
Test status
Simulation time 511916196 ps
CPU time 2.16 seconds
Started Jul 25 06:54:11 PM PDT 24
Finished Jul 25 06:54:13 PM PDT 24
Peak memory 200124 kb
Host smart-7e368c43-d01b-4bc3-867e-033dfea1debf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252955012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
252955012
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1938772435
Short name T554
Test name
Test status
Simulation time 190330122 ps
CPU time 1.18 seconds
Started Jul 25 06:54:18 PM PDT 24
Finished Jul 25 06:54:19 PM PDT 24
Peak memory 208192 kb
Host smart-fe949a38-434c-4155-968a-f42e677d4201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938772435 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1938772435
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2049013900
Short name T547
Test name
Test status
Simulation time 67771902 ps
CPU time 0.79 seconds
Started Jul 25 06:54:10 PM PDT 24
Finished Jul 25 06:54:11 PM PDT 24
Peak memory 199872 kb
Host smart-bf3447cc-c867-4aa5-9b20-d58d57171fbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049013900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2049013900
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.743435898
Short name T579
Test name
Test status
Simulation time 161772209 ps
CPU time 1.17 seconds
Started Jul 25 06:54:19 PM PDT 24
Finished Jul 25 06:54:20 PM PDT 24
Peak memory 199904 kb
Host smart-1c206a1d-3c26-48b2-bfee-4e0e7ef0cae5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743435898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.743435898
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1805813698
Short name T562
Test name
Test status
Simulation time 94657041 ps
CPU time 1.37 seconds
Started Jul 25 06:54:09 PM PDT 24
Finished Jul 25 06:54:10 PM PDT 24
Peak memory 216100 kb
Host smart-29346992-d236-44a4-a856-067072bf1748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805813698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1805813698
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1206534832
Short name T590
Test name
Test status
Simulation time 791538715 ps
CPU time 2.87 seconds
Started Jul 25 06:54:08 PM PDT 24
Finished Jul 25 06:54:11 PM PDT 24
Peak memory 200056 kb
Host smart-7d6ce0b3-08a3-4c1b-8ace-4f2670510468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206534832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1206534832
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1836607402
Short name T620
Test name
Test status
Simulation time 118077215 ps
CPU time 0.99 seconds
Started Jul 25 06:54:19 PM PDT 24
Finished Jul 25 06:54:20 PM PDT 24
Peak memory 208256 kb
Host smart-3f71a144-8b4e-48f7-866a-3a951439764b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836607402 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1836607402
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.977415448
Short name T568
Test name
Test status
Simulation time 90450161 ps
CPU time 0.88 seconds
Started Jul 25 06:54:21 PM PDT 24
Finished Jul 25 06:54:22 PM PDT 24
Peak memory 199900 kb
Host smart-77cdc8f1-5c66-478b-91c4-3e19071b0714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977415448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.977415448
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1768776220
Short name T97
Test name
Test status
Simulation time 77355114 ps
CPU time 0.95 seconds
Started Jul 25 06:54:21 PM PDT 24
Finished Jul 25 06:54:22 PM PDT 24
Peak memory 199964 kb
Host smart-df3725ae-e1c7-4213-a8d6-80e20ea18f5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768776220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1768776220
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1090248552
Short name T619
Test name
Test status
Simulation time 433327043 ps
CPU time 2.85 seconds
Started Jul 25 06:54:19 PM PDT 24
Finished Jul 25 06:54:22 PM PDT 24
Peak memory 211640 kb
Host smart-9828d822-6ba1-4f5c-8779-6631f24d0625
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090248552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1090248552
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.428899067
Short name T557
Test name
Test status
Simulation time 523125462 ps
CPU time 1.87 seconds
Started Jul 25 06:54:18 PM PDT 24
Finished Jul 25 06:54:20 PM PDT 24
Peak memory 200064 kb
Host smart-f3a253b9-9638-4761-b0b4-6063a5793a2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428899067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
428899067
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1240714717
Short name T575
Test name
Test status
Simulation time 128039893 ps
CPU time 1.44 seconds
Started Jul 25 06:54:29 PM PDT 24
Finished Jul 25 06:54:30 PM PDT 24
Peak memory 208384 kb
Host smart-663d1521-070f-43ee-9fbf-c2b7952a2f99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240714717 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1240714717
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2944826725
Short name T573
Test name
Test status
Simulation time 60660493 ps
CPU time 0.78 seconds
Started Jul 25 06:54:17 PM PDT 24
Finished Jul 25 06:54:18 PM PDT 24
Peak memory 199860 kb
Host smart-d8b1e628-534f-4a34-9a20-f73a360f80f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944826725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2944826725
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3193716672
Short name T617
Test name
Test status
Simulation time 88071518 ps
CPU time 0.98 seconds
Started Jul 25 06:54:28 PM PDT 24
Finished Jul 25 06:54:29 PM PDT 24
Peak memory 199796 kb
Host smart-fef6a520-ae59-42fd-bec9-58cbb7c2db1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193716672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3193716672
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3112396880
Short name T608
Test name
Test status
Simulation time 423859521 ps
CPU time 2.86 seconds
Started Jul 25 06:54:18 PM PDT 24
Finished Jul 25 06:54:21 PM PDT 24
Peak memory 208144 kb
Host smart-3a9f54cf-9bf6-4523-b423-51028a6d56f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112396880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3112396880
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3030143041
Short name T553
Test name
Test status
Simulation time 426664215 ps
CPU time 1.75 seconds
Started Jul 25 06:54:18 PM PDT 24
Finished Jul 25 06:54:20 PM PDT 24
Peak memory 200092 kb
Host smart-2ca160bc-7f04-4b74-8cca-7b54bfd1d75b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030143041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3030143041
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1302995859
Short name T347
Test name
Test status
Simulation time 80315153 ps
CPU time 0.8 seconds
Started Jul 25 06:54:51 PM PDT 24
Finished Jul 25 06:54:52 PM PDT 24
Peak memory 199984 kb
Host smart-36649598-c234-4210-a532-1bbeb705483b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302995859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1302995859
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.4141977996
Short name T31
Test name
Test status
Simulation time 1881838305 ps
CPU time 7.18 seconds
Started Jul 25 06:54:50 PM PDT 24
Finished Jul 25 06:54:57 PM PDT 24
Peak memory 221680 kb
Host smart-3341be54-94d0-4e74-92cc-53a06aa079c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141977996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.4141977996
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1862350695
Short name T377
Test name
Test status
Simulation time 245042361 ps
CPU time 1.04 seconds
Started Jul 25 06:54:48 PM PDT 24
Finished Jul 25 06:54:50 PM PDT 24
Peak memory 217476 kb
Host smart-f9397a8c-408e-489e-9051-793cae2a8aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862350695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1862350695
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1305379046
Short name T271
Test name
Test status
Simulation time 227374738 ps
CPU time 0.97 seconds
Started Jul 25 06:54:52 PM PDT 24
Finished Jul 25 06:54:54 PM PDT 24
Peak memory 199956 kb
Host smart-72dece66-88c3-42b4-8289-a03c1df47f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305379046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1305379046
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3927178045
Short name T275
Test name
Test status
Simulation time 1441126015 ps
CPU time 5.72 seconds
Started Jul 25 06:54:47 PM PDT 24
Finished Jul 25 06:54:53 PM PDT 24
Peak memory 200416 kb
Host smart-f5983ddd-9bf8-460e-a89c-6988838ddfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927178045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3927178045
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.484752668
Short name T59
Test name
Test status
Simulation time 8290670945 ps
CPU time 14.78 seconds
Started Jul 25 06:54:48 PM PDT 24
Finished Jul 25 06:55:03 PM PDT 24
Peak memory 217688 kb
Host smart-c381a1f7-8523-4046-91f8-35604bc5dcb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484752668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.484752668
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.677694762
Short name T181
Test name
Test status
Simulation time 173458038 ps
CPU time 1.15 seconds
Started Jul 25 06:54:49 PM PDT 24
Finished Jul 25 06:54:50 PM PDT 24
Peak memory 200100 kb
Host smart-325a99d5-80c0-4fde-998b-3e49c18b59da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677694762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.677694762
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3388120864
Short name T484
Test name
Test status
Simulation time 124030571 ps
CPU time 1.21 seconds
Started Jul 25 06:54:44 PM PDT 24
Finished Jul 25 06:54:45 PM PDT 24
Peak memory 200396 kb
Host smart-6f2348ea-34cc-477e-aeb0-95708bd5ca59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388120864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3388120864
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.374325484
Short name T314
Test name
Test status
Simulation time 171870588 ps
CPU time 1.33 seconds
Started Jul 25 06:54:48 PM PDT 24
Finished Jul 25 06:54:50 PM PDT 24
Peak memory 200196 kb
Host smart-77011d95-1637-451b-8772-1cceea0ec460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374325484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.374325484
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3606868248
Short name T401
Test name
Test status
Simulation time 272747639 ps
CPU time 1.84 seconds
Started Jul 25 06:54:49 PM PDT 24
Finished Jul 25 06:54:51 PM PDT 24
Peak memory 200152 kb
Host smart-982d8124-bbb8-495f-919d-72aad00f019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606868248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3606868248
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.675905236
Short name T360
Test name
Test status
Simulation time 111956110 ps
CPU time 0.93 seconds
Started Jul 25 06:54:48 PM PDT 24
Finished Jul 25 06:54:49 PM PDT 24
Peak memory 200180 kb
Host smart-696f644c-7850-4cd6-9034-338e2da72c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675905236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.675905236
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3249716375
Short name T510
Test name
Test status
Simulation time 79122210 ps
CPU time 0.82 seconds
Started Jul 25 06:54:50 PM PDT 24
Finished Jul 25 06:54:51 PM PDT 24
Peak memory 199892 kb
Host smart-94de024b-6975-4d0d-a40c-c341a7027b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249716375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3249716375
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1819658413
Short name T44
Test name
Test status
Simulation time 1219297604 ps
CPU time 5.33 seconds
Started Jul 25 06:54:49 PM PDT 24
Finished Jul 25 06:54:54 PM PDT 24
Peak memory 217808 kb
Host smart-e5d1232e-c723-4ab3-a922-7318b8de86ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819658413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1819658413
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.689549593
Short name T245
Test name
Test status
Simulation time 244234311 ps
CPU time 1.19 seconds
Started Jul 25 06:54:54 PM PDT 24
Finished Jul 25 06:54:55 PM PDT 24
Peak memory 217544 kb
Host smart-27e3ae23-7f73-4b4a-a983-3b2632d1df3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689549593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.689549593
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2941313588
Short name T269
Test name
Test status
Simulation time 81789932 ps
CPU time 0.77 seconds
Started Jul 25 06:54:49 PM PDT 24
Finished Jul 25 06:54:50 PM PDT 24
Peak memory 199956 kb
Host smart-8096ddbb-a40e-411a-913e-22f1c0aabddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941313588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2941313588
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2930304610
Short name T432
Test name
Test status
Simulation time 1426077666 ps
CPU time 5.92 seconds
Started Jul 25 06:54:50 PM PDT 24
Finished Jul 25 06:54:56 PM PDT 24
Peak memory 200396 kb
Host smart-aa70234d-7853-45c5-a9b3-b64567a41c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930304610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2930304610
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.4082362414
Short name T427
Test name
Test status
Simulation time 117274174 ps
CPU time 1.21 seconds
Started Jul 25 06:54:51 PM PDT 24
Finished Jul 25 06:54:53 PM PDT 24
Peak memory 200368 kb
Host smart-29e503dd-79c9-48e0-9afb-4a85ef9b7785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082362414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4082362414
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.267491298
Short name T533
Test name
Test status
Simulation time 2019887249 ps
CPU time 7.59 seconds
Started Jul 25 06:54:49 PM PDT 24
Finished Jul 25 06:54:57 PM PDT 24
Peak memory 208604 kb
Host smart-cb3b23c6-003d-4683-87bf-7cf2f17b4039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267491298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.267491298
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2309141993
Short name T359
Test name
Test status
Simulation time 462068488 ps
CPU time 2.58 seconds
Started Jul 25 06:54:53 PM PDT 24
Finished Jul 25 06:54:56 PM PDT 24
Peak memory 200164 kb
Host smart-66af4530-8402-4b91-a80f-0861fbadbb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309141993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2309141993
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1526770572
Short name T151
Test name
Test status
Simulation time 111998752 ps
CPU time 0.94 seconds
Started Jul 25 06:54:50 PM PDT 24
Finished Jul 25 06:54:51 PM PDT 24
Peak memory 200004 kb
Host smart-f0506619-8a9f-440f-9224-9674555f4e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526770572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1526770572
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3575127244
Short name T282
Test name
Test status
Simulation time 99272532 ps
CPU time 0.87 seconds
Started Jul 25 06:55:20 PM PDT 24
Finished Jul 25 06:55:21 PM PDT 24
Peak memory 199956 kb
Host smart-51800ba2-c670-4804-949b-5d9dcc08d4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575127244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3575127244
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.681135166
Short name T35
Test name
Test status
Simulation time 2343212034 ps
CPU time 8.52 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:29 PM PDT 24
Peak memory 221236 kb
Host smart-84c87662-9e7f-40c3-b9d3-a0826ab21825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681135166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.681135166
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2584870270
Short name T447
Test name
Test status
Simulation time 243736477 ps
CPU time 1.07 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:22 PM PDT 24
Peak memory 217572 kb
Host smart-fb33ef12-888b-4e41-9e82-9978c668e570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584870270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2584870270
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4097356914
Short name T157
Test name
Test status
Simulation time 216791094 ps
CPU time 1.1 seconds
Started Jul 25 06:55:22 PM PDT 24
Finished Jul 25 06:55:23 PM PDT 24
Peak memory 199952 kb
Host smart-871cb73e-becd-4f42-b7c1-6331531ea525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097356914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4097356914
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3925593850
Short name T142
Test name
Test status
Simulation time 1513412738 ps
CPU time 6.12 seconds
Started Jul 25 06:55:19 PM PDT 24
Finished Jul 25 06:55:26 PM PDT 24
Peak memory 200412 kb
Host smart-aec9ce9c-874c-4291-bd14-1519b747675d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925593850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3925593850
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2556487230
Short name T257
Test name
Test status
Simulation time 111749539 ps
CPU time 1.02 seconds
Started Jul 25 06:55:20 PM PDT 24
Finished Jul 25 06:55:21 PM PDT 24
Peak memory 200144 kb
Host smart-d48dea6a-0007-4690-a1b6-b59b1b513385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556487230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2556487230
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.192011565
Short name T281
Test name
Test status
Simulation time 118689880 ps
CPU time 1.19 seconds
Started Jul 25 06:55:23 PM PDT 24
Finished Jul 25 06:55:25 PM PDT 24
Peak memory 200352 kb
Host smart-84865e1e-8a0d-4ac0-8d55-9e767965e703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192011565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.192011565
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1698841624
Short name T165
Test name
Test status
Simulation time 503038399 ps
CPU time 2.36 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:24 PM PDT 24
Peak memory 200400 kb
Host smart-493b0363-7601-4f12-9201-f34895a56208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698841624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1698841624
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1053459381
Short name T532
Test name
Test status
Simulation time 257569619 ps
CPU time 1.81 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:23 PM PDT 24
Peak memory 200128 kb
Host smart-2dd90344-39f6-43a9-85cf-171c27d71db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053459381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1053459381
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1273605769
Short name T374
Test name
Test status
Simulation time 103691125 ps
CPU time 0.96 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:23 PM PDT 24
Peak memory 200140 kb
Host smart-e6ca998c-72a2-4c00-8f32-713659db093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273605769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1273605769
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3721001081
Short name T524
Test name
Test status
Simulation time 2365178312 ps
CPU time 7.91 seconds
Started Jul 25 06:55:18 PM PDT 24
Finished Jul 25 06:55:26 PM PDT 24
Peak memory 217904 kb
Host smart-d8810359-6c57-4cc9-addf-279673d062d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721001081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3721001081
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2544283778
Short name T198
Test name
Test status
Simulation time 244243941 ps
CPU time 1.07 seconds
Started Jul 25 06:59:27 PM PDT 24
Finished Jul 25 06:59:29 PM PDT 24
Peak memory 217476 kb
Host smart-45e1cd3e-a4b5-45b2-9cd9-4315ef90fcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544283778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2544283778
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3302083381
Short name T391
Test name
Test status
Simulation time 69957090 ps
CPU time 0.71 seconds
Started Jul 25 06:55:20 PM PDT 24
Finished Jul 25 06:55:20 PM PDT 24
Peak memory 199952 kb
Host smart-8112c727-d4be-4b7c-82ae-5f116ff939ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302083381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3302083381
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3914902044
Short name T191
Test name
Test status
Simulation time 1205328842 ps
CPU time 4.81 seconds
Started Jul 25 06:55:22 PM PDT 24
Finished Jul 25 06:55:27 PM PDT 24
Peak memory 200456 kb
Host smart-2500ee41-5094-4e87-a796-40d81aa1a716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914902044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3914902044
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.853374168
Short name T491
Test name
Test status
Simulation time 174032837 ps
CPU time 1.19 seconds
Started Jul 25 06:55:19 PM PDT 24
Finished Jul 25 06:55:20 PM PDT 24
Peak memory 200092 kb
Host smart-a1e23625-6070-4243-9120-a4abadb35031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853374168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.853374168
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3874403952
Short name T183
Test name
Test status
Simulation time 114859693 ps
CPU time 1.18 seconds
Started Jul 25 06:55:19 PM PDT 24
Finished Jul 25 06:55:20 PM PDT 24
Peak memory 200388 kb
Host smart-ca0f6baf-9129-4344-8ae3-d6d2028e1f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874403952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3874403952
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3801457600
Short name T312
Test name
Test status
Simulation time 6463708758 ps
CPU time 30.76 seconds
Started Jul 25 06:55:33 PM PDT 24
Finished Jul 25 06:56:04 PM PDT 24
Peak memory 200476 kb
Host smart-96cfa5b7-b415-45fd-88f8-3a34e96fd309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801457600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3801457600
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2906087375
Short name T380
Test name
Test status
Simulation time 324040823 ps
CPU time 2.12 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:23 PM PDT 24
Peak memory 200204 kb
Host smart-8d968f59-ab87-4350-8b4a-ce5d8bed6b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906087375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2906087375
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.637951165
Short name T304
Test name
Test status
Simulation time 260693987 ps
CPU time 1.5 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:23 PM PDT 24
Peak memory 200132 kb
Host smart-4290f612-75cd-4fb6-9fe1-6f6cf6f43735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637951165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.637951165
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3385570501
Short name T354
Test name
Test status
Simulation time 75412654 ps
CPU time 0.82 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:55:35 PM PDT 24
Peak memory 199944 kb
Host smart-eb92f096-a697-4ec7-9ef2-095cf378de29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385570501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3385570501
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1602177531
Short name T318
Test name
Test status
Simulation time 2346595712 ps
CPU time 8.31 seconds
Started Jul 25 06:55:38 PM PDT 24
Finished Jul 25 06:55:47 PM PDT 24
Peak memory 217940 kb
Host smart-7518c70d-ba88-45b5-93b0-1b5cd378538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602177531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1602177531
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.798514632
Short name T132
Test name
Test status
Simulation time 245829419 ps
CPU time 1.04 seconds
Started Jul 25 06:55:35 PM PDT 24
Finished Jul 25 06:55:36 PM PDT 24
Peak memory 217456 kb
Host smart-b6d30e6b-8249-4e7c-bce4-15d928d87f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798514632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.798514632
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.260485818
Short name T286
Test name
Test status
Simulation time 213666340 ps
CPU time 0.92 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:55:35 PM PDT 24
Peak memory 199956 kb
Host smart-2eb89213-cc23-4ee7-aae2-29e6265877a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260485818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.260485818
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.606339174
Short name T84
Test name
Test status
Simulation time 1536325743 ps
CPU time 6.14 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:55:40 PM PDT 24
Peak memory 200416 kb
Host smart-056920a6-c40f-4ffd-b9cb-3dd6735600bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606339174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.606339174
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.681346737
Short name T118
Test name
Test status
Simulation time 156241376 ps
CPU time 1.1 seconds
Started Jul 25 06:55:33 PM PDT 24
Finished Jul 25 06:55:34 PM PDT 24
Peak memory 200188 kb
Host smart-085a79cc-524c-4fc9-9559-cc565e0ec664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681346737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.681346737
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1130417278
Short name T461
Test name
Test status
Simulation time 258363080 ps
CPU time 1.46 seconds
Started Jul 25 06:55:33 PM PDT 24
Finished Jul 25 06:55:35 PM PDT 24
Peak memory 200344 kb
Host smart-01e14259-14b6-4526-b4ad-b89797c72d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130417278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1130417278
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.772128226
Short name T494
Test name
Test status
Simulation time 8988515509 ps
CPU time 31.15 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:56:05 PM PDT 24
Peak memory 208680 kb
Host smart-b184d524-3dab-46b2-b906-27c9edd200c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772128226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.772128226
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.105285888
Short name T135
Test name
Test status
Simulation time 305654853 ps
CPU time 2.1 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:55:36 PM PDT 24
Peak memory 208356 kb
Host smart-c2c793e1-4b99-487a-9dba-9139949a6596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105285888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.105285888
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.694043041
Short name T164
Test name
Test status
Simulation time 145997676 ps
CPU time 1.03 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:55:35 PM PDT 24
Peak memory 200160 kb
Host smart-25adf48e-42a0-4cd7-8719-182ee9d80b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694043041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.694043041
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.959184817
Short name T268
Test name
Test status
Simulation time 75021991 ps
CPU time 0.81 seconds
Started Jul 25 06:55:32 PM PDT 24
Finished Jul 25 06:55:33 PM PDT 24
Peak memory 199904 kb
Host smart-aecc52cf-cdf8-4746-b7a0-e03dfb3a1cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959184817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.959184817
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1257992568
Short name T297
Test name
Test status
Simulation time 244416757 ps
CPU time 1.03 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:55:36 PM PDT 24
Peak memory 217560 kb
Host smart-f0cc30ff-6884-4181-bf7f-4fea87f2a311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257992568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1257992568
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1354011098
Short name T431
Test name
Test status
Simulation time 176065803 ps
CPU time 0.85 seconds
Started Jul 25 06:55:32 PM PDT 24
Finished Jul 25 06:55:33 PM PDT 24
Peak memory 199964 kb
Host smart-25657fb3-4260-4886-b206-6bccd6ffb359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354011098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1354011098
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3729599788
Short name T39
Test name
Test status
Simulation time 1889375312 ps
CPU time 6.82 seconds
Started Jul 25 06:55:40 PM PDT 24
Finished Jul 25 06:55:47 PM PDT 24
Peak memory 200404 kb
Host smart-69def287-51b5-4ba4-bd0a-b9de03b25509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729599788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3729599788
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2419188692
Short name T521
Test name
Test status
Simulation time 103443366 ps
CPU time 0.97 seconds
Started Jul 25 06:55:35 PM PDT 24
Finished Jul 25 06:55:36 PM PDT 24
Peak memory 200144 kb
Host smart-81401e24-16ee-48a1-a39f-7a05492d868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419188692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2419188692
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.589670011
Short name T317
Test name
Test status
Simulation time 198440970 ps
CPU time 1.44 seconds
Started Jul 25 06:55:33 PM PDT 24
Finished Jul 25 06:55:34 PM PDT 24
Peak memory 200324 kb
Host smart-4592c22a-4e79-4af4-97e1-b96efec3216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589670011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.589670011
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3435600741
Short name T395
Test name
Test status
Simulation time 459037626 ps
CPU time 2.41 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:55:36 PM PDT 24
Peak memory 200164 kb
Host smart-32bc4d1c-7442-4f3d-bf4d-c9e25e4db94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435600741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3435600741
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3745449392
Short name T174
Test name
Test status
Simulation time 58996536 ps
CPU time 0.83 seconds
Started Jul 25 06:55:35 PM PDT 24
Finished Jul 25 06:55:36 PM PDT 24
Peak memory 199944 kb
Host smart-ded2312d-cc44-4032-9c50-0403c2846cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745449392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3745449392
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.4153835821
Short name T215
Test name
Test status
Simulation time 1875369369 ps
CPU time 7.86 seconds
Started Jul 25 06:55:35 PM PDT 24
Finished Jul 25 06:55:44 PM PDT 24
Peak memory 217812 kb
Host smart-dcfba51a-9840-4670-9caa-3c7a65512684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153835821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.4153835821
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2916000499
Short name T313
Test name
Test status
Simulation time 245457217 ps
CPU time 1.03 seconds
Started Jul 25 06:55:35 PM PDT 24
Finished Jul 25 06:55:36 PM PDT 24
Peak memory 217480 kb
Host smart-58490a5c-2a8f-44e9-8d90-9adbdb2e4128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916000499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2916000499
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1427737360
Short name T299
Test name
Test status
Simulation time 1124215270 ps
CPU time 5.11 seconds
Started Jul 25 06:55:32 PM PDT 24
Finished Jul 25 06:55:37 PM PDT 24
Peak memory 200424 kb
Host smart-ff1f01b4-2f33-4a47-931a-46d84b4bad53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427737360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1427737360
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.4208808679
Short name T122
Test name
Test status
Simulation time 163481978 ps
CPU time 1.12 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:55:35 PM PDT 24
Peak memory 200148 kb
Host smart-d97e0a74-2855-4368-a29a-1a424b39d34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208808679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.4208808679
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2130872795
Short name T525
Test name
Test status
Simulation time 253996103 ps
CPU time 1.42 seconds
Started Jul 25 06:55:41 PM PDT 24
Finished Jul 25 06:55:42 PM PDT 24
Peak memory 200340 kb
Host smart-f87340c1-face-4ac1-a82b-ebd7f5b27721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130872795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2130872795
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1360506894
Short name T487
Test name
Test status
Simulation time 2471556290 ps
CPU time 10.98 seconds
Started Jul 25 06:55:40 PM PDT 24
Finished Jul 25 06:55:51 PM PDT 24
Peak memory 200516 kb
Host smart-fba53623-d704-4dbd-87cc-80d69a579c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360506894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1360506894
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.4008887978
Short name T385
Test name
Test status
Simulation time 341498499 ps
CPU time 2.09 seconds
Started Jul 25 06:55:32 PM PDT 24
Finished Jul 25 06:55:34 PM PDT 24
Peak memory 208448 kb
Host smart-74d1e81b-e3de-42ec-b25b-e32e527ce807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008887978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4008887978
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3786885567
Short name T185
Test name
Test status
Simulation time 233987139 ps
CPU time 1.33 seconds
Started Jul 25 06:55:41 PM PDT 24
Finished Jul 25 06:55:43 PM PDT 24
Peak memory 200148 kb
Host smart-b5472c32-4d47-4ef4-a076-f5e406a9d4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786885567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3786885567
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.630396659
Short name T320
Test name
Test status
Simulation time 63993647 ps
CPU time 0.73 seconds
Started Jul 25 06:55:49 PM PDT 24
Finished Jul 25 06:55:50 PM PDT 24
Peak memory 199932 kb
Host smart-642ffe22-0c8f-4e05-b0f6-7dffbaf4369d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630396659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.630396659
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.369981347
Short name T30
Test name
Test status
Simulation time 1227740812 ps
CPU time 5.91 seconds
Started Jul 25 06:55:45 PM PDT 24
Finished Jul 25 06:55:51 PM PDT 24
Peak memory 216960 kb
Host smart-edcbcffd-bd9b-47b2-bbba-502d455ae820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369981347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.369981347
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.360489914
Short name T468
Test name
Test status
Simulation time 243659103 ps
CPU time 1.05 seconds
Started Jul 25 06:55:45 PM PDT 24
Finished Jul 25 06:55:46 PM PDT 24
Peak memory 217504 kb
Host smart-27dd549e-f14a-4e4a-bfed-d7b6d708e5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360489914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.360489914
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.846881328
Short name T199
Test name
Test status
Simulation time 238400280 ps
CPU time 0.94 seconds
Started Jul 25 06:55:34 PM PDT 24
Finished Jul 25 06:55:36 PM PDT 24
Peak memory 199952 kb
Host smart-c68ebadd-95fb-47cd-966b-00ab4b48a9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846881328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.846881328
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3008574333
Short name T232
Test name
Test status
Simulation time 891922048 ps
CPU time 4.82 seconds
Started Jul 25 06:55:40 PM PDT 24
Finished Jul 25 06:55:45 PM PDT 24
Peak memory 200380 kb
Host smart-5e172315-767c-4d5e-834d-c3ed50a4f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008574333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3008574333
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3748503488
Short name T497
Test name
Test status
Simulation time 151165511 ps
CPU time 1.12 seconds
Started Jul 25 06:55:47 PM PDT 24
Finished Jul 25 06:55:48 PM PDT 24
Peak memory 200140 kb
Host smart-d6744332-542a-4aaa-b409-7e8c250ff919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748503488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3748503488
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.316134905
Short name T501
Test name
Test status
Simulation time 123189820 ps
CPU time 1.27 seconds
Started Jul 25 06:55:33 PM PDT 24
Finished Jul 25 06:55:34 PM PDT 24
Peak memory 200344 kb
Host smart-f0d16b9e-157c-4c6b-95e8-599d2504b50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316134905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.316134905
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.362308033
Short name T251
Test name
Test status
Simulation time 9966693393 ps
CPU time 33.83 seconds
Started Jul 25 06:55:46 PM PDT 24
Finished Jul 25 06:56:20 PM PDT 24
Peak memory 200432 kb
Host smart-d9f6ed61-be01-4449-a266-fd7ef6de0123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362308033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.362308033
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2700698709
Short name T178
Test name
Test status
Simulation time 144285704 ps
CPU time 1.93 seconds
Started Jul 25 06:55:33 PM PDT 24
Finished Jul 25 06:55:35 PM PDT 24
Peak memory 200132 kb
Host smart-40bb4406-308d-4012-b463-94a755766d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700698709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2700698709
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3656875950
Short name T343
Test name
Test status
Simulation time 250731168 ps
CPU time 1.37 seconds
Started Jul 25 06:55:32 PM PDT 24
Finished Jul 25 06:55:33 PM PDT 24
Peak memory 200188 kb
Host smart-b09a5412-2417-4088-bfb4-10940b7eb022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656875950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3656875950
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1558809396
Short name T415
Test name
Test status
Simulation time 72029069 ps
CPU time 0.77 seconds
Started Jul 25 06:55:49 PM PDT 24
Finished Jul 25 06:55:50 PM PDT 24
Peak memory 199956 kb
Host smart-6ddca3a5-0124-4941-acc8-cfdfae3f4c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558809396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1558809396
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2162171675
Short name T32
Test name
Test status
Simulation time 1223840516 ps
CPU time 5.38 seconds
Started Jul 25 06:55:46 PM PDT 24
Finished Jul 25 06:55:51 PM PDT 24
Peak memory 221768 kb
Host smart-64faeb0e-7313-4597-8334-518f4711e091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162171675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2162171675
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.563980318
Short name T331
Test name
Test status
Simulation time 244748650 ps
CPU time 1.13 seconds
Started Jul 25 06:55:50 PM PDT 24
Finished Jul 25 06:55:51 PM PDT 24
Peak memory 217496 kb
Host smart-bbcc1a2f-ff3f-4bc7-9e3f-9a6eee480138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563980318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.563980318
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2954505962
Short name T155
Test name
Test status
Simulation time 220997873 ps
CPU time 1 seconds
Started Jul 25 06:55:49 PM PDT 24
Finished Jul 25 06:55:51 PM PDT 24
Peak memory 199960 kb
Host smart-463e4515-508c-4554-ab3c-9f034f861371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954505962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2954505962
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2415949973
Short name T425
Test name
Test status
Simulation time 975787697 ps
CPU time 5.18 seconds
Started Jul 25 06:55:48 PM PDT 24
Finished Jul 25 06:55:53 PM PDT 24
Peak memory 200404 kb
Host smart-90f418cb-1036-4c88-aabf-bd159ad03c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415949973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2415949973
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.922822401
Short name T244
Test name
Test status
Simulation time 157621941 ps
CPU time 1.1 seconds
Started Jul 25 06:55:48 PM PDT 24
Finished Jul 25 06:55:50 PM PDT 24
Peak memory 200132 kb
Host smart-44296889-c958-40b1-85d6-f6740a569e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922822401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.922822401
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.686010384
Short name T485
Test name
Test status
Simulation time 108023868 ps
CPU time 1.2 seconds
Started Jul 25 06:55:47 PM PDT 24
Finished Jul 25 06:55:48 PM PDT 24
Peak memory 200344 kb
Host smart-f7ae7d88-dea0-4f85-baeb-0bb29c0fb04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686010384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.686010384
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2151467696
Short name T301
Test name
Test status
Simulation time 8461257331 ps
CPU time 29.88 seconds
Started Jul 25 06:55:53 PM PDT 24
Finished Jul 25 06:56:23 PM PDT 24
Peak memory 200480 kb
Host smart-56e9e7a9-6c0f-4adf-b6e8-ca4345adc71a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151467696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2151467696
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.954271039
Short name T443
Test name
Test status
Simulation time 362160901 ps
CPU time 2.27 seconds
Started Jul 25 06:55:49 PM PDT 24
Finished Jul 25 06:55:51 PM PDT 24
Peak memory 200192 kb
Host smart-11fe0d58-e6cd-4ac8-bf1d-11655c77f8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954271039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.954271039
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3709651681
Short name T150
Test name
Test status
Simulation time 215696953 ps
CPU time 1.24 seconds
Started Jul 25 06:55:44 PM PDT 24
Finished Jul 25 06:55:46 PM PDT 24
Peak memory 200092 kb
Host smart-a4109f5a-d120-4a0b-8b52-d60f5a163bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709651681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3709651681
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2744621401
Short name T358
Test name
Test status
Simulation time 68742729 ps
CPU time 0.74 seconds
Started Jul 25 06:55:46 PM PDT 24
Finished Jul 25 06:55:47 PM PDT 24
Peak memory 199944 kb
Host smart-661ba3bd-0b52-425c-9355-b2769fce8fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744621401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2744621401
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2557263421
Short name T27
Test name
Test status
Simulation time 1890594012 ps
CPU time 6.88 seconds
Started Jul 25 06:55:50 PM PDT 24
Finished Jul 25 06:55:57 PM PDT 24
Peak memory 221788 kb
Host smart-bd764b4f-b7e8-488c-b6d2-3ff344f5406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557263421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2557263421
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2500822449
Short name T396
Test name
Test status
Simulation time 244865697 ps
CPU time 1.14 seconds
Started Jul 25 06:55:49 PM PDT 24
Finished Jul 25 06:55:50 PM PDT 24
Peak memory 217468 kb
Host smart-bff1414a-fce4-4f3f-8a92-88785f5bcef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500822449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2500822449
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2029671771
Short name T23
Test name
Test status
Simulation time 216118909 ps
CPU time 0.95 seconds
Started Jul 25 06:55:50 PM PDT 24
Finished Jul 25 06:55:51 PM PDT 24
Peak memory 199940 kb
Host smart-c62338ae-543e-473b-9623-80e1b8f677ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029671771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2029671771
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.763748454
Short name T392
Test name
Test status
Simulation time 830824680 ps
CPU time 4.18 seconds
Started Jul 25 06:55:50 PM PDT 24
Finished Jul 25 06:55:55 PM PDT 24
Peak memory 199792 kb
Host smart-045e4811-1f2e-4659-bb24-64f1cc7c39a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763748454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.763748454
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1598157835
Short name T372
Test name
Test status
Simulation time 189532907 ps
CPU time 1.28 seconds
Started Jul 25 06:55:47 PM PDT 24
Finished Jul 25 06:55:48 PM PDT 24
Peak memory 200184 kb
Host smart-d1a7b97d-a476-4f5f-bcb1-f935a9d2fb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598157835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1598157835
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.384127752
Short name T221
Test name
Test status
Simulation time 201992537 ps
CPU time 1.38 seconds
Started Jul 25 06:55:48 PM PDT 24
Finished Jul 25 06:55:50 PM PDT 24
Peak memory 200348 kb
Host smart-7bf6499b-2672-4281-9fcd-f86bafd6078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384127752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.384127752
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1857146947
Short name T109
Test name
Test status
Simulation time 11677245722 ps
CPU time 42.92 seconds
Started Jul 25 06:55:48 PM PDT 24
Finished Jul 25 06:56:31 PM PDT 24
Peak memory 208648 kb
Host smart-22173a87-0710-41bc-b246-eeaf15453553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857146947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1857146947
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1379912985
Short name T394
Test name
Test status
Simulation time 518453516 ps
CPU time 2.84 seconds
Started Jul 25 06:55:49 PM PDT 24
Finished Jul 25 06:55:52 PM PDT 24
Peak memory 200136 kb
Host smart-87d74566-7f60-4adf-b5e0-d34818cfcfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379912985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1379912985
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1517925134
Short name T184
Test name
Test status
Simulation time 77533497 ps
CPU time 0.85 seconds
Started Jul 25 06:55:46 PM PDT 24
Finished Jul 25 06:55:47 PM PDT 24
Peak memory 200164 kb
Host smart-f3b9293a-f128-4275-97d0-d2143efe6ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517925134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1517925134
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1269274085
Short name T467
Test name
Test status
Simulation time 77160040 ps
CPU time 0.81 seconds
Started Jul 25 06:55:48 PM PDT 24
Finished Jul 25 06:55:49 PM PDT 24
Peak memory 199952 kb
Host smart-7277103e-2282-4972-bfbd-ca9bd1bc994e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269274085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1269274085
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1981051551
Short name T249
Test name
Test status
Simulation time 1911217090 ps
CPU time 7.2 seconds
Started Jul 25 06:55:45 PM PDT 24
Finished Jul 25 06:55:53 PM PDT 24
Peak memory 217784 kb
Host smart-d570a68c-b80a-4828-9396-a1dde2196c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981051551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1981051551
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1278627221
Short name T66
Test name
Test status
Simulation time 243906313 ps
CPU time 1.11 seconds
Started Jul 25 06:55:46 PM PDT 24
Finished Jul 25 06:55:48 PM PDT 24
Peak memory 217504 kb
Host smart-dac8ed9f-ede6-49f1-8cd2-9538bed3fe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278627221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1278627221
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3878429128
Short name T316
Test name
Test status
Simulation time 231111784 ps
CPU time 0.93 seconds
Started Jul 25 06:55:55 PM PDT 24
Finished Jul 25 06:55:56 PM PDT 24
Peak memory 199912 kb
Host smart-c7bb876b-25dc-4777-a181-9f44cade5912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878429128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3878429128
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2720212430
Short name T243
Test name
Test status
Simulation time 816043458 ps
CPU time 4.16 seconds
Started Jul 25 06:55:54 PM PDT 24
Finished Jul 25 06:55:58 PM PDT 24
Peak memory 200412 kb
Host smart-71714634-fd9c-4ca9-afc4-957bc2c5fb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720212430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2720212430
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3219319260
Short name T536
Test name
Test status
Simulation time 152403977 ps
CPU time 1.2 seconds
Started Jul 25 06:55:47 PM PDT 24
Finished Jul 25 06:55:48 PM PDT 24
Peak memory 200124 kb
Host smart-e3268a56-4f73-46a1-8f45-4e8ce4c255be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219319260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3219319260
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1160381523
Short name T140
Test name
Test status
Simulation time 121738830 ps
CPU time 1.13 seconds
Started Jul 25 06:55:50 PM PDT 24
Finished Jul 25 06:55:52 PM PDT 24
Peak memory 199540 kb
Host smart-1e1b5878-f186-45ea-b731-ef7acc0234cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160381523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1160381523
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2918028007
Short name T240
Test name
Test status
Simulation time 8806972343 ps
CPU time 28.69 seconds
Started Jul 25 06:55:50 PM PDT 24
Finished Jul 25 06:56:19 PM PDT 24
Peak memory 208700 kb
Host smart-cb785221-dd8d-4039-aba4-ff847e2ec5c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918028007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2918028007
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2173596868
Short name T500
Test name
Test status
Simulation time 469491749 ps
CPU time 2.78 seconds
Started Jul 25 06:55:49 PM PDT 24
Finished Jul 25 06:55:52 PM PDT 24
Peak memory 200148 kb
Host smart-f2e45a5f-c304-42b7-a124-716c296d7c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173596868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2173596868
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.664147233
Short name T149
Test name
Test status
Simulation time 118164637 ps
CPU time 0.93 seconds
Started Jul 25 06:55:54 PM PDT 24
Finished Jul 25 06:55:55 PM PDT 24
Peak memory 200156 kb
Host smart-bdfb09ef-896c-4784-9f27-47129f95b78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664147233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.664147233
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2075837229
Short name T534
Test name
Test status
Simulation time 77871390 ps
CPU time 0.83 seconds
Started Jul 25 06:55:59 PM PDT 24
Finished Jul 25 06:56:01 PM PDT 24
Peak memory 199988 kb
Host smart-0e222146-6cea-4f54-8347-0dccabbfd84e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075837229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2075837229
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2552482531
Short name T531
Test name
Test status
Simulation time 1896339260 ps
CPU time 7.77 seconds
Started Jul 25 06:55:45 PM PDT 24
Finished Jul 25 06:55:53 PM PDT 24
Peak memory 221712 kb
Host smart-c243fa68-b059-4d17-8f57-bcbd2397e609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552482531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2552482531
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3241324188
Short name T449
Test name
Test status
Simulation time 244032679 ps
CPU time 1.06 seconds
Started Jul 25 06:55:54 PM PDT 24
Finished Jul 25 06:55:55 PM PDT 24
Peak memory 217544 kb
Host smart-7a6f98f6-6b9d-48df-80a6-3b6ca0917bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241324188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3241324188
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3757899835
Short name T223
Test name
Test status
Simulation time 204776002 ps
CPU time 0.94 seconds
Started Jul 25 06:55:47 PM PDT 24
Finished Jul 25 06:55:48 PM PDT 24
Peak memory 199960 kb
Host smart-54fcd611-168c-406a-a7d1-f671bc063893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757899835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3757899835
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2765603710
Short name T481
Test name
Test status
Simulation time 1555337376 ps
CPU time 7.11 seconds
Started Jul 25 06:55:46 PM PDT 24
Finished Jul 25 06:55:53 PM PDT 24
Peak memory 200408 kb
Host smart-a1967569-57df-41c1-9eff-2d13df9bf2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765603710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2765603710
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.74133655
Short name T296
Test name
Test status
Simulation time 99074223 ps
CPU time 1 seconds
Started Jul 25 06:55:48 PM PDT 24
Finished Jul 25 06:55:49 PM PDT 24
Peak memory 200132 kb
Host smart-a7020ad6-a003-40c3-8fea-54f8e08dd989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74133655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.74133655
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.923764389
Short name T146
Test name
Test status
Simulation time 113526537 ps
CPU time 1.2 seconds
Started Jul 25 06:55:49 PM PDT 24
Finished Jul 25 06:55:50 PM PDT 24
Peak memory 200328 kb
Host smart-afe81134-51de-4a07-a20e-71228e593818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923764389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.923764389
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4210444721
Short name T482
Test name
Test status
Simulation time 152273675 ps
CPU time 1.88 seconds
Started Jul 25 06:55:46 PM PDT 24
Finished Jul 25 06:55:48 PM PDT 24
Peak memory 200156 kb
Host smart-4c3f1c91-c5b0-4cc2-a1c1-531d7d872064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210444721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4210444721
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4257546335
Short name T515
Test name
Test status
Simulation time 191164545 ps
CPU time 1.21 seconds
Started Jul 25 06:55:46 PM PDT 24
Finished Jul 25 06:55:47 PM PDT 24
Peak memory 200152 kb
Host smart-6862b6c7-c35c-4b53-bcde-a244c80aef5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257546335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4257546335
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2616564676
Short name T225
Test name
Test status
Simulation time 89497441 ps
CPU time 0.85 seconds
Started Jul 25 06:55:00 PM PDT 24
Finished Jul 25 06:55:01 PM PDT 24
Peak memory 199952 kb
Host smart-0f4d32e5-693b-4f21-9572-f8d506a08738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616564676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2616564676
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2722324969
Short name T263
Test name
Test status
Simulation time 2347843252 ps
CPU time 9.47 seconds
Started Jul 25 06:54:51 PM PDT 24
Finished Jul 25 06:55:00 PM PDT 24
Peak memory 217960 kb
Host smart-91ebcf2f-a9d5-4042-9a22-6050a594fb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722324969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2722324969
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.524971995
Short name T70
Test name
Test status
Simulation time 244291146 ps
CPU time 1.07 seconds
Started Jul 25 06:54:50 PM PDT 24
Finished Jul 25 06:54:52 PM PDT 24
Peak memory 217504 kb
Host smart-b459fafc-3c90-4aae-8110-7e34a78d3e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524971995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.524971995
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1839276829
Short name T19
Test name
Test status
Simulation time 166950348 ps
CPU time 0.86 seconds
Started Jul 25 06:54:49 PM PDT 24
Finished Jul 25 06:54:50 PM PDT 24
Peak memory 199936 kb
Host smart-6e76a943-d778-47e5-9d0c-1cb5fe9ac711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839276829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1839276829
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3572429473
Short name T188
Test name
Test status
Simulation time 740156394 ps
CPU time 3.98 seconds
Started Jul 25 06:54:53 PM PDT 24
Finished Jul 25 06:54:57 PM PDT 24
Peak memory 200424 kb
Host smart-d22bc049-54c1-44c6-b0e8-7dcd6d9fe0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572429473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3572429473
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1701451254
Short name T53
Test name
Test status
Simulation time 8381514090 ps
CPU time 12.85 seconds
Started Jul 25 06:55:01 PM PDT 24
Finished Jul 25 06:55:14 PM PDT 24
Peak memory 217232 kb
Host smart-87e99c4c-3e4c-4a5d-9ecf-1c1ed5d8fd61
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701451254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1701451254
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3381093057
Short name T124
Test name
Test status
Simulation time 106624086 ps
CPU time 1.02 seconds
Started Jul 25 06:54:49 PM PDT 24
Finished Jul 25 06:54:50 PM PDT 24
Peak memory 200132 kb
Host smart-3a763eaa-7f13-47f0-bab6-b06bdbcd9929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381093057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3381093057
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.573777750
Short name T464
Test name
Test status
Simulation time 129075748 ps
CPU time 1.29 seconds
Started Jul 25 06:54:52 PM PDT 24
Finished Jul 25 06:54:53 PM PDT 24
Peak memory 200348 kb
Host smart-dfd8a173-71c8-43f1-9d5c-55757380668a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573777750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.573777750
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3803562314
Short name T337
Test name
Test status
Simulation time 9679321466 ps
CPU time 36.16 seconds
Started Jul 25 06:54:51 PM PDT 24
Finished Jul 25 06:55:27 PM PDT 24
Peak memory 208752 kb
Host smart-5321f21a-f510-40c7-95b7-1115a3973af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803562314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3803562314
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3296829490
Short name T413
Test name
Test status
Simulation time 138034626 ps
CPU time 1.79 seconds
Started Jul 25 06:54:54 PM PDT 24
Finished Jul 25 06:54:56 PM PDT 24
Peak memory 200164 kb
Host smart-167d6fe3-de3d-4ee6-bb65-0b4713f0652b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296829490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3296829490
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1895570829
Short name T322
Test name
Test status
Simulation time 195985849 ps
CPU time 1.17 seconds
Started Jul 25 06:54:49 PM PDT 24
Finished Jul 25 06:54:50 PM PDT 24
Peak memory 200152 kb
Host smart-0976657a-cc69-4e4e-9f92-14d26c6f1d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895570829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1895570829
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.4282198664
Short name T212
Test name
Test status
Simulation time 91862458 ps
CPU time 0.83 seconds
Started Jul 25 06:55:58 PM PDT 24
Finished Jul 25 06:55:59 PM PDT 24
Peak memory 199932 kb
Host smart-119b9411-afd4-495b-a1e0-e67413142eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282198664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.4282198664
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.17974621
Short name T384
Test name
Test status
Simulation time 1224876261 ps
CPU time 5.94 seconds
Started Jul 25 06:55:58 PM PDT 24
Finished Jul 25 06:56:04 PM PDT 24
Peak memory 221824 kb
Host smart-4007dea9-1c99-4c0c-8376-deb1107ff3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17974621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.17974621
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2666704863
Short name T7
Test name
Test status
Simulation time 243407732 ps
CPU time 1.13 seconds
Started Jul 25 06:55:57 PM PDT 24
Finished Jul 25 06:55:58 PM PDT 24
Peak memory 217548 kb
Host smart-db462486-ddbb-4731-b2c8-7c2f6fac2dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666704863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2666704863
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3371130689
Short name T473
Test name
Test status
Simulation time 98701677 ps
CPU time 0.79 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:55:56 PM PDT 24
Peak memory 199972 kb
Host smart-d73ce5d0-4e4d-49b4-84b2-fed15ef78f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371130689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3371130689
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.4054146764
Short name T163
Test name
Test status
Simulation time 856043967 ps
CPU time 4.27 seconds
Started Jul 25 06:55:58 PM PDT 24
Finished Jul 25 06:56:03 PM PDT 24
Peak memory 200408 kb
Host smart-9295b3f8-bffd-4bdd-9505-60eb955c63f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054146764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.4054146764
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3697599928
Short name T115
Test name
Test status
Simulation time 145316869 ps
CPU time 1.13 seconds
Started Jul 25 06:55:57 PM PDT 24
Finished Jul 25 06:55:58 PM PDT 24
Peak memory 200136 kb
Host smart-b7f1400f-66d3-4cb0-aa0e-b21ac5ec8de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697599928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3697599928
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2282510846
Short name T69
Test name
Test status
Simulation time 249528651 ps
CPU time 1.39 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:55:58 PM PDT 24
Peak memory 200340 kb
Host smart-f1e86dfd-23e9-4752-a52b-7373aa0f3f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282510846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2282510846
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2079263363
Short name T144
Test name
Test status
Simulation time 7505636354 ps
CPU time 27.26 seconds
Started Jul 25 06:55:59 PM PDT 24
Finished Jul 25 06:56:27 PM PDT 24
Peak memory 208676 kb
Host smart-042e4fb4-fadb-42f1-8ead-1940048529c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079263363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2079263363
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.4217801100
Short name T265
Test name
Test status
Simulation time 331292070 ps
CPU time 1.93 seconds
Started Jul 25 06:55:57 PM PDT 24
Finished Jul 25 06:55:59 PM PDT 24
Peak memory 200136 kb
Host smart-7fe2a058-1fe0-42bd-b900-0e3ad52dc5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217801100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.4217801100
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3453343475
Short name T530
Test name
Test status
Simulation time 162109814 ps
CPU time 1.22 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:55:57 PM PDT 24
Peak memory 200136 kb
Host smart-11272ada-0aae-4b48-8aec-549b786357dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453343475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3453343475
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1001720077
Short name T278
Test name
Test status
Simulation time 93204047 ps
CPU time 0.84 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:55:58 PM PDT 24
Peak memory 199968 kb
Host smart-3e14041b-7e63-472e-8f31-73b7211377b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001720077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1001720077
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3008899403
Short name T28
Test name
Test status
Simulation time 1230745206 ps
CPU time 6.13 seconds
Started Jul 25 06:55:58 PM PDT 24
Finished Jul 25 06:56:04 PM PDT 24
Peak memory 221740 kb
Host smart-96f0f35d-3faa-4ee8-a92a-4e3c85493844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008899403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3008899403
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.4233079623
Short name T136
Test name
Test status
Simulation time 244660222 ps
CPU time 1.04 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:55:58 PM PDT 24
Peak memory 217496 kb
Host smart-567d815d-667d-45c8-a5ce-a3b8dfc5e9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233079623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.4233079623
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2405040677
Short name T371
Test name
Test status
Simulation time 189073643 ps
CPU time 0.87 seconds
Started Jul 25 06:55:59 PM PDT 24
Finished Jul 25 06:56:00 PM PDT 24
Peak memory 199932 kb
Host smart-f1074bba-e06f-41b2-9501-369e502c6957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405040677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2405040677
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.688606751
Short name T107
Test name
Test status
Simulation time 1629590691 ps
CPU time 6.44 seconds
Started Jul 25 06:55:59 PM PDT 24
Finished Jul 25 06:56:06 PM PDT 24
Peak memory 200416 kb
Host smart-989838cd-3731-418d-a99e-3b2ade0daad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688606751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.688606751
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.583009907
Short name T386
Test name
Test status
Simulation time 102485421 ps
CPU time 0.95 seconds
Started Jul 25 06:55:55 PM PDT 24
Finished Jul 25 06:55:56 PM PDT 24
Peak memory 200072 kb
Host smart-19663d77-4722-45f2-b244-b5d178e8d4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583009907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.583009907
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.989477544
Short name T397
Test name
Test status
Simulation time 122583089 ps
CPU time 1.18 seconds
Started Jul 25 06:55:57 PM PDT 24
Finished Jul 25 06:55:59 PM PDT 24
Peak memory 200388 kb
Host smart-a15ad091-2245-4baf-8bf1-7789e9eefba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989477544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.989477544
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2502614035
Short name T419
Test name
Test status
Simulation time 6401285346 ps
CPU time 22.82 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:56:19 PM PDT 24
Peak memory 208672 kb
Host smart-db49af67-a0b0-4f6a-94a2-bc4bb92553e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502614035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2502614035
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.610605350
Short name T190
Test name
Test status
Simulation time 252702508 ps
CPU time 1.75 seconds
Started Jul 25 06:55:59 PM PDT 24
Finished Jul 25 06:56:00 PM PDT 24
Peak memory 200152 kb
Host smart-b97c3072-5117-4925-bdfe-e3003c62e80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610605350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.610605350
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1159315067
Short name T279
Test name
Test status
Simulation time 150540704 ps
CPU time 1.06 seconds
Started Jul 25 06:55:58 PM PDT 24
Finished Jul 25 06:55:59 PM PDT 24
Peak memory 200152 kb
Host smart-c0145730-06f7-4374-98e5-599afea67034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159315067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1159315067
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1090726421
Short name T367
Test name
Test status
Simulation time 86564795 ps
CPU time 0.81 seconds
Started Jul 25 06:55:55 PM PDT 24
Finished Jul 25 06:55:56 PM PDT 24
Peak memory 199984 kb
Host smart-59c79044-4830-4612-af3e-8dc686855971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090726421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1090726421
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.138076566
Short name T438
Test name
Test status
Simulation time 1890332169 ps
CPU time 8.1 seconds
Started Jul 25 06:55:58 PM PDT 24
Finished Jul 25 06:56:06 PM PDT 24
Peak memory 221708 kb
Host smart-a0f34a70-989e-4ad5-9e05-ad226fc984bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138076566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.138076566
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1829202693
Short name T426
Test name
Test status
Simulation time 244732280 ps
CPU time 1.09 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:55:58 PM PDT 24
Peak memory 217568 kb
Host smart-a18907cb-005f-4227-85e0-6d32f5d887bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829202693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1829202693
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3474437422
Short name T424
Test name
Test status
Simulation time 128954173 ps
CPU time 0.82 seconds
Started Jul 25 06:55:57 PM PDT 24
Finished Jul 25 06:55:59 PM PDT 24
Peak memory 199960 kb
Host smart-253a3aca-ebaa-4f03-9c1a-76f75b692d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474437422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3474437422
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1955931642
Short name T173
Test name
Test status
Simulation time 968962797 ps
CPU time 5.08 seconds
Started Jul 25 06:56:00 PM PDT 24
Finished Jul 25 06:56:05 PM PDT 24
Peak memory 200416 kb
Host smart-b2259f4f-4ca2-494b-802e-98c1b9ce2fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955931642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1955931642
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1473510342
Short name T326
Test name
Test status
Simulation time 174995338 ps
CPU time 1.19 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:55:58 PM PDT 24
Peak memory 200084 kb
Host smart-cfae114c-d6c8-40c8-a062-32a77d84fd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473510342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1473510342
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2175998638
Short name T488
Test name
Test status
Simulation time 248150183 ps
CPU time 1.43 seconds
Started Jul 25 06:55:58 PM PDT 24
Finished Jul 25 06:56:00 PM PDT 24
Peak memory 200344 kb
Host smart-475ed632-78ec-4195-b621-108444396030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175998638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2175998638
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1816731941
Short name T452
Test name
Test status
Simulation time 3386386547 ps
CPU time 13.91 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:56:10 PM PDT 24
Peak memory 200244 kb
Host smart-7eafbec5-9f1d-47c0-aeca-2672b07aa15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816731941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1816731941
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3246999616
Short name T111
Test name
Test status
Simulation time 526832764 ps
CPU time 3 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:56:00 PM PDT 24
Peak memory 200160 kb
Host smart-0e5f46be-6437-4c4d-8452-8a19bcb3b2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246999616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3246999616
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2722519857
Short name T197
Test name
Test status
Simulation time 113652410 ps
CPU time 0.92 seconds
Started Jul 25 06:55:55 PM PDT 24
Finished Jul 25 06:55:56 PM PDT 24
Peak memory 200148 kb
Host smart-d51e8e25-f842-484f-9e7a-78f9dec0a7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722519857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2722519857
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1075200405
Short name T324
Test name
Test status
Simulation time 73705207 ps
CPU time 0.79 seconds
Started Jul 25 06:55:55 PM PDT 24
Finished Jul 25 06:55:56 PM PDT 24
Peak memory 199916 kb
Host smart-4c21f83a-03a0-4728-a24e-f2d60452beee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075200405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1075200405
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2550864070
Short name T12
Test name
Test status
Simulation time 1893048359 ps
CPU time 7.09 seconds
Started Jul 25 06:55:59 PM PDT 24
Finished Jul 25 06:56:07 PM PDT 24
Peak memory 217800 kb
Host smart-275a0636-0c97-48ff-a32a-35ed16ecc960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550864070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2550864070
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.678993667
Short name T116
Test name
Test status
Simulation time 243530667 ps
CPU time 1.12 seconds
Started Jul 25 06:55:57 PM PDT 24
Finished Jul 25 06:55:58 PM PDT 24
Peak memory 217472 kb
Host smart-1cec69e6-ab75-4734-bd00-c635ab352f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678993667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.678993667
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.620292893
Short name T459
Test name
Test status
Simulation time 117904106 ps
CPU time 0.84 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:55:57 PM PDT 24
Peak memory 199912 kb
Host smart-cab50ea4-90a5-4f95-9f68-132f09585af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620292893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.620292893
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3023077534
Short name T266
Test name
Test status
Simulation time 1448124819 ps
CPU time 5.68 seconds
Started Jul 25 06:55:57 PM PDT 24
Finished Jul 25 06:56:03 PM PDT 24
Peak memory 200464 kb
Host smart-7748d939-c46a-48aa-8e41-f56a6198eca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023077534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3023077534
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1583149411
Short name T457
Test name
Test status
Simulation time 99113228 ps
CPU time 1 seconds
Started Jul 25 06:55:58 PM PDT 24
Finished Jul 25 06:55:59 PM PDT 24
Peak memory 200132 kb
Host smart-caf2813f-5f1a-420b-ad97-f4d9367f078d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583149411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1583149411
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2450527030
Short name T182
Test name
Test status
Simulation time 250039372 ps
CPU time 1.56 seconds
Started Jul 25 06:55:57 PM PDT 24
Finished Jul 25 06:55:59 PM PDT 24
Peak memory 200344 kb
Host smart-80695990-84f8-475d-83d1-a941a672d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450527030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2450527030
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2512464163
Short name T247
Test name
Test status
Simulation time 4871908127 ps
CPU time 18.65 seconds
Started Jul 25 06:55:59 PM PDT 24
Finished Jul 25 06:56:18 PM PDT 24
Peak memory 200480 kb
Host smart-1b36e91e-0978-4012-be84-3888a1598b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512464163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2512464163
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1355306084
Short name T528
Test name
Test status
Simulation time 476903003 ps
CPU time 2.57 seconds
Started Jul 25 06:55:58 PM PDT 24
Finished Jul 25 06:56:01 PM PDT 24
Peak memory 200104 kb
Host smart-41e55f82-0b7e-4f98-a8b0-c00c22da1d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355306084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1355306084
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2216108235
Short name T187
Test name
Test status
Simulation time 69998046 ps
CPU time 0.76 seconds
Started Jul 25 06:55:59 PM PDT 24
Finished Jul 25 06:56:00 PM PDT 24
Peak memory 200196 kb
Host smart-a7aee6ac-043c-40ba-8ba4-9bff6f4ff7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216108235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2216108235
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1616824709
Short name T428
Test name
Test status
Simulation time 64413143 ps
CPU time 0.74 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 199912 kb
Host smart-e56da3e4-0427-40eb-b213-2d36df874bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616824709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1616824709
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2538229580
Short name T356
Test name
Test status
Simulation time 1226255006 ps
CPU time 5.64 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:13 PM PDT 24
Peak memory 221788 kb
Host smart-1da9b035-5b66-457b-a2ec-a1d7101e4ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538229580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2538229580
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1132308379
Short name T193
Test name
Test status
Simulation time 244540408 ps
CPU time 1.06 seconds
Started Jul 25 06:56:06 PM PDT 24
Finished Jul 25 06:56:08 PM PDT 24
Peak memory 217480 kb
Host smart-8078ed85-abc0-4502-bcd3-4f098b00db82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132308379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1132308379
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3276968126
Short name T520
Test name
Test status
Simulation time 175206984 ps
CPU time 0.95 seconds
Started Jul 25 06:55:56 PM PDT 24
Finished Jul 25 06:55:57 PM PDT 24
Peak memory 199916 kb
Host smart-27362135-da8d-46dd-8330-e68bf42c2edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276968126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3276968126
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3760199086
Short name T288
Test name
Test status
Simulation time 1232951081 ps
CPU time 5.86 seconds
Started Jul 25 06:55:59 PM PDT 24
Finished Jul 25 06:56:06 PM PDT 24
Peak memory 200408 kb
Host smart-b40d0966-9f2e-4384-bdbf-42c9d96cadec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760199086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3760199086
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.112860167
Short name T339
Test name
Test status
Simulation time 141986084 ps
CPU time 1.19 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 200188 kb
Host smart-cf16fdb8-c139-4b85-9107-3fec84018836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112860167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.112860167
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.831487004
Short name T389
Test name
Test status
Simulation time 255444431 ps
CPU time 1.54 seconds
Started Jul 25 06:55:58 PM PDT 24
Finished Jul 25 06:55:59 PM PDT 24
Peak memory 200352 kb
Host smart-a126cfe7-df5e-49c5-b1e2-f6bf7cf9c8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831487004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.831487004
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3340313909
Short name T85
Test name
Test status
Simulation time 4537568095 ps
CPU time 19.2 seconds
Started Jul 25 06:56:04 PM PDT 24
Finished Jul 25 06:56:23 PM PDT 24
Peak memory 200516 kb
Host smart-14ba9007-5bd7-411a-bc78-a1475cc169dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340313909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3340313909
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1109998210
Short name T414
Test name
Test status
Simulation time 117415953 ps
CPU time 1.46 seconds
Started Jul 25 06:56:05 PM PDT 24
Finished Jul 25 06:56:07 PM PDT 24
Peak memory 200108 kb
Host smart-22cf5b12-046f-4f89-96fb-201f07522034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109998210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1109998210
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.417831844
Short name T4
Test name
Test status
Simulation time 171735482 ps
CPU time 1.34 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:10 PM PDT 24
Peak memory 200360 kb
Host smart-8783d8df-d20f-4978-a63b-7b6fc76e8150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417831844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.417831844
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.317139209
Short name T216
Test name
Test status
Simulation time 81274244 ps
CPU time 0.81 seconds
Started Jul 25 06:56:09 PM PDT 24
Finished Jul 25 06:56:10 PM PDT 24
Peak memory 199944 kb
Host smart-1dc5ee53-c464-4ed6-9637-5ae38e7cc074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317139209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.317139209
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.598669257
Short name T256
Test name
Test status
Simulation time 2354343700 ps
CPU time 9.09 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:17 PM PDT 24
Peak memory 217936 kb
Host smart-fe2c08af-0b43-4c2b-b8ac-8db76f77155d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598669257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.598669257
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4154840241
Short name T411
Test name
Test status
Simulation time 245579226 ps
CPU time 1.06 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 217480 kb
Host smart-4a29417d-0da2-412b-8299-f0371ff55762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154840241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4154840241
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2049537102
Short name T253
Test name
Test status
Simulation time 160693278 ps
CPU time 0.85 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:08 PM PDT 24
Peak memory 199756 kb
Host smart-5fd86294-3eeb-4cab-b165-9a0159a4b48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049537102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2049537102
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.459383833
Short name T346
Test name
Test status
Simulation time 1741803910 ps
CPU time 7.43 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:15 PM PDT 24
Peak memory 200396 kb
Host smart-be4f2df8-acaf-49c4-994e-5fdbfb0bdd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459383833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.459383833
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1235208655
Short name T156
Test name
Test status
Simulation time 111070292 ps
CPU time 0.98 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:08 PM PDT 24
Peak memory 200152 kb
Host smart-9ae98b52-23b0-424b-9af2-e3a3e740cb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235208655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1235208655
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1141611313
Short name T529
Test name
Test status
Simulation time 227485867 ps
CPU time 1.42 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 200308 kb
Host smart-cdeaa240-27a4-4ab6-83e7-f243ead45714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141611313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1141611313
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.416337962
Short name T505
Test name
Test status
Simulation time 5621787659 ps
CPU time 23.24 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:30 PM PDT 24
Peak memory 200476 kb
Host smart-029806c6-eb29-47bb-9b2d-3d8e57b270a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416337962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.416337962
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1926598355
Short name T152
Test name
Test status
Simulation time 366404434 ps
CPU time 2.19 seconds
Started Jul 25 06:56:06 PM PDT 24
Finished Jul 25 06:56:08 PM PDT 24
Peak memory 200100 kb
Host smart-d3513c6b-e6e3-456f-80c9-0bea4a3cc837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926598355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1926598355
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2779845990
Short name T284
Test name
Test status
Simulation time 88568755 ps
CPU time 0.89 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:10 PM PDT 24
Peak memory 200188 kb
Host smart-338751db-f078-41dc-a98b-f3788cd177e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779845990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2779845990
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3485830730
Short name T168
Test name
Test status
Simulation time 65999646 ps
CPU time 0.79 seconds
Started Jul 25 06:56:06 PM PDT 24
Finished Jul 25 06:56:08 PM PDT 24
Peak memory 199952 kb
Host smart-6d81c43e-ef71-4796-90c5-bd4e1f8db153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485830730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3485830730
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3114406149
Short name T348
Test name
Test status
Simulation time 1221341329 ps
CPU time 5.6 seconds
Started Jul 25 06:56:06 PM PDT 24
Finished Jul 25 06:56:12 PM PDT 24
Peak memory 217476 kb
Host smart-7c2c8687-1eb2-4b73-808d-c721d0236891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114406149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3114406149
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.4140895250
Short name T523
Test name
Test status
Simulation time 244124315 ps
CPU time 1.13 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 217504 kb
Host smart-de251f2b-9130-432a-bea7-40c8c3ba8ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140895250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.4140895250
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3222013875
Short name T440
Test name
Test status
Simulation time 150985586 ps
CPU time 0.83 seconds
Started Jul 25 06:56:04 PM PDT 24
Finished Jul 25 06:56:05 PM PDT 24
Peak memory 199960 kb
Host smart-1521bd81-088d-451c-9f43-efd466672b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222013875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3222013875
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1727189535
Short name T110
Test name
Test status
Simulation time 1674624323 ps
CPU time 5.89 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:14 PM PDT 24
Peak memory 200436 kb
Host smart-eae2f5e5-bfed-48a0-b354-d4944887d62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727189535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1727189535
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2077521930
Short name T231
Test name
Test status
Simulation time 141785236 ps
CPU time 1.14 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 200184 kb
Host smart-0a9c7184-4b84-4f47-8c98-fcf7aa96bfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077521930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2077521930
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.301197624
Short name T483
Test name
Test status
Simulation time 190161377 ps
CPU time 1.32 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:08 PM PDT 24
Peak memory 200292 kb
Host smart-4260e2b9-b7a2-4621-abea-bb7585d23a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301197624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.301197624
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2688986295
Short name T108
Test name
Test status
Simulation time 9155691881 ps
CPU time 33.37 seconds
Started Jul 25 06:56:09 PM PDT 24
Finished Jul 25 06:56:43 PM PDT 24
Peak memory 200452 kb
Host smart-daedcf2d-96e0-40be-b214-60df2aaead63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688986295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2688986295
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1678309230
Short name T242
Test name
Test status
Simulation time 101912220 ps
CPU time 0.97 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 200136 kb
Host smart-27e6121b-b66f-4ccf-b270-c0e2b59fbbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678309230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1678309230
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2534979937
Short name T479
Test name
Test status
Simulation time 68495150 ps
CPU time 0.77 seconds
Started Jul 25 06:56:09 PM PDT 24
Finished Jul 25 06:56:10 PM PDT 24
Peak memory 199944 kb
Host smart-4f6d3a14-df19-42f9-93e2-f5da3e47007d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534979937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2534979937
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1208945080
Short name T8
Test name
Test status
Simulation time 1891675234 ps
CPU time 7.62 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:16 PM PDT 24
Peak memory 217816 kb
Host smart-26608a9c-5b83-4d19-941f-eaa5742a98fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208945080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1208945080
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2339925125
Short name T167
Test name
Test status
Simulation time 246317747 ps
CPU time 1.05 seconds
Started Jul 25 06:56:09 PM PDT 24
Finished Jul 25 06:56:10 PM PDT 24
Peak memory 217484 kb
Host smart-a45fb8d5-b360-443f-ba60-e0cbd955f176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339925125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2339925125
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2385203596
Short name T418
Test name
Test status
Simulation time 78822194 ps
CPU time 0.72 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 199968 kb
Host smart-d0ff6b34-8b3d-440e-bdb6-21738ffb8c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385203596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2385203596
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.4107756872
Short name T517
Test name
Test status
Simulation time 717070182 ps
CPU time 3.66 seconds
Started Jul 25 06:56:06 PM PDT 24
Finished Jul 25 06:56:10 PM PDT 24
Peak memory 200416 kb
Host smart-21961957-1fb4-48b7-8229-5deffbc9dd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107756872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4107756872
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.300614228
Short name T305
Test name
Test status
Simulation time 96406837 ps
CPU time 0.95 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:08 PM PDT 24
Peak memory 200148 kb
Host smart-d5c29170-19cb-464e-91c2-0185db6faf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300614228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.300614228
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3240692317
Short name T139
Test name
Test status
Simulation time 115945613 ps
CPU time 1.15 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:08 PM PDT 24
Peak memory 200280 kb
Host smart-0efa13e2-cd98-4ee5-81c7-2a578646a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240692317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3240692317
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2301355757
Short name T287
Test name
Test status
Simulation time 6041746500 ps
CPU time 26.88 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:34 PM PDT 24
Peak memory 200500 kb
Host smart-71f65620-06ab-45cf-801e-20cadccec699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301355757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2301355757
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.497387539
Short name T220
Test name
Test status
Simulation time 155445803 ps
CPU time 1.84 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:10 PM PDT 24
Peak memory 200156 kb
Host smart-19bf6290-09bb-4771-8291-0c8a8dfe7ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497387539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.497387539
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2895450107
Short name T176
Test name
Test status
Simulation time 286694701 ps
CPU time 1.52 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:10 PM PDT 24
Peak memory 200152 kb
Host smart-3d7f0a18-1a27-4876-b206-bdcbc95363f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895450107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2895450107
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.676757995
Short name T177
Test name
Test status
Simulation time 100749734 ps
CPU time 0.91 seconds
Started Jul 25 06:56:17 PM PDT 24
Finished Jul 25 06:56:18 PM PDT 24
Peak memory 199944 kb
Host smart-16d0c708-cdc4-4236-ab35-25f64da4462b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676757995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.676757995
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4114574200
Short name T42
Test name
Test status
Simulation time 1880996035 ps
CPU time 6.92 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:15 PM PDT 24
Peak memory 221764 kb
Host smart-cd310912-328e-4817-9377-a6d94eeedc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114574200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.4114574200
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2262017734
Short name T227
Test name
Test status
Simulation time 244692648 ps
CPU time 1.08 seconds
Started Jul 25 06:56:15 PM PDT 24
Finished Jul 25 06:56:16 PM PDT 24
Peak memory 217484 kb
Host smart-d7187cc4-cedc-438f-b6c7-3ff1f6d0ec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262017734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2262017734
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.330152983
Short name T508
Test name
Test status
Simulation time 175617206 ps
CPU time 0.87 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 199948 kb
Host smart-0c696bac-ca15-4373-9b99-525ef44bd141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330152983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.330152983
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3445523551
Short name T334
Test name
Test status
Simulation time 892379405 ps
CPU time 4.56 seconds
Started Jul 25 06:56:09 PM PDT 24
Finished Jul 25 06:56:14 PM PDT 24
Peak memory 200436 kb
Host smart-a57d26c0-71b4-4dc6-837e-5b46c18d27c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445523551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3445523551
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.919079055
Short name T137
Test name
Test status
Simulation time 156116584 ps
CPU time 1.18 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 200144 kb
Host smart-12950bc7-01b8-487d-b764-b031bb03a587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919079055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.919079055
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3454924041
Short name T349
Test name
Test status
Simulation time 120245199 ps
CPU time 1.23 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 200332 kb
Host smart-cfd796a8-9837-460a-b272-cfe9ffc6a21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454924041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3454924041
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.4081982
Short name T303
Test name
Test status
Simulation time 6619834566 ps
CPU time 28.73 seconds
Started Jul 25 06:56:24 PM PDT 24
Finished Jul 25 06:56:53 PM PDT 24
Peak memory 210784 kb
Host smart-8fb91d63-9520-4469-8d8a-7305acfc8eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.4081982
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1908933160
Short name T121
Test name
Test status
Simulation time 138208391 ps
CPU time 1.8 seconds
Started Jul 25 06:56:07 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 200152 kb
Host smart-cddc39d9-efe7-4993-ac13-96f730345129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908933160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1908933160
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1631014572
Short name T422
Test name
Test status
Simulation time 165791563 ps
CPU time 1.24 seconds
Started Jul 25 06:56:05 PM PDT 24
Finished Jul 25 06:56:07 PM PDT 24
Peak memory 200348 kb
Host smart-188082e7-d626-44c3-b6be-7cbc0b48f274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631014572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1631014572
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1427102153
Short name T250
Test name
Test status
Simulation time 84325422 ps
CPU time 0.81 seconds
Started Jul 25 06:56:15 PM PDT 24
Finished Jul 25 06:56:16 PM PDT 24
Peak memory 199944 kb
Host smart-f9d39e4f-c8bb-4b62-a67f-510cbe38cdac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427102153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1427102153
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2239288665
Short name T518
Test name
Test status
Simulation time 1222079292 ps
CPU time 5.55 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:31 PM PDT 24
Peak memory 217792 kb
Host smart-5a6bcb7e-05af-4ba8-9cfa-249200a8b751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239288665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2239288665
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.747503900
Short name T496
Test name
Test status
Simulation time 244236235 ps
CPU time 1.07 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:17 PM PDT 24
Peak memory 217576 kb
Host smart-7cf11825-2200-4925-9ef7-3ab3038b607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747503900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.747503900
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2876280078
Short name T475
Test name
Test status
Simulation time 158116854 ps
CPU time 0.83 seconds
Started Jul 25 06:56:15 PM PDT 24
Finished Jul 25 06:56:16 PM PDT 24
Peak memory 199956 kb
Host smart-489e39a9-059a-4ff4-a6a9-fa16049449d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876280078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2876280078
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1335268820
Short name T368
Test name
Test status
Simulation time 853422481 ps
CPU time 4.15 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:29 PM PDT 24
Peak memory 200400 kb
Host smart-7a4ce7db-0352-444c-bf9a-22363c0b1e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335268820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1335268820
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.243281890
Short name T519
Test name
Test status
Simulation time 149995342 ps
CPU time 1.14 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:18 PM PDT 24
Peak memory 200132 kb
Host smart-604ce2b1-05cc-478a-8488-0e1cebb81418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243281890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.243281890
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.468878159
Short name T512
Test name
Test status
Simulation time 126779773 ps
CPU time 1.28 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:18 PM PDT 24
Peak memory 200396 kb
Host smart-efb16026-4245-4331-ac72-4b93769259ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468878159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.468878159
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.333617118
Short name T423
Test name
Test status
Simulation time 3181644294 ps
CPU time 15.92 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:32 PM PDT 24
Peak memory 200464 kb
Host smart-51edbfb9-63b8-4541-ac3a-119c3dab5217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333617118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.333617118
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3043231786
Short name T454
Test name
Test status
Simulation time 145115405 ps
CPU time 1.63 seconds
Started Jul 25 06:56:15 PM PDT 24
Finished Jul 25 06:56:17 PM PDT 24
Peak memory 200160 kb
Host smart-5d1881cc-1723-49ed-917a-085f0292ffd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043231786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3043231786
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1372830431
Short name T131
Test name
Test status
Simulation time 58608920 ps
CPU time 0.77 seconds
Started Jul 25 06:56:17 PM PDT 24
Finished Jul 25 06:56:18 PM PDT 24
Peak memory 200156 kb
Host smart-9afc383d-5db2-4aaf-a7db-f7b064f9c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372830431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1372830431
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3683896490
Short name T58
Test name
Test status
Simulation time 67028809 ps
CPU time 0.73 seconds
Started Jul 25 06:54:59 PM PDT 24
Finished Jul 25 06:55:00 PM PDT 24
Peak memory 199960 kb
Host smart-2d88e141-82a2-4527-b532-35d02ca6bf89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683896490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3683896490
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3755575390
Short name T158
Test name
Test status
Simulation time 1234162662 ps
CPU time 5.76 seconds
Started Jul 25 06:55:03 PM PDT 24
Finished Jul 25 06:55:09 PM PDT 24
Peak memory 217828 kb
Host smart-f9a1ac25-434c-4c4a-ac8d-15a8330c1a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755575390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3755575390
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3616681503
Short name T439
Test name
Test status
Simulation time 244690942 ps
CPU time 1.01 seconds
Started Jul 25 06:54:59 PM PDT 24
Finished Jul 25 06:55:00 PM PDT 24
Peak memory 217468 kb
Host smart-1bf92543-2dbc-407c-b956-02df0c174c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616681503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3616681503
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3573408887
Short name T17
Test name
Test status
Simulation time 159411532 ps
CPU time 0.82 seconds
Started Jul 25 06:55:01 PM PDT 24
Finished Jul 25 06:55:02 PM PDT 24
Peak memory 199948 kb
Host smart-46d66863-b325-46ef-9360-0f377372b774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573408887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3573408887
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2622021892
Short name T87
Test name
Test status
Simulation time 780365619 ps
CPU time 4.17 seconds
Started Jul 25 06:55:02 PM PDT 24
Finished Jul 25 06:55:06 PM PDT 24
Peak memory 200408 kb
Host smart-e2c15377-14cb-4c97-9ed0-40c0f2dedbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622021892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2622021892
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3610135480
Short name T54
Test name
Test status
Simulation time 16510630725 ps
CPU time 26.28 seconds
Started Jul 25 06:54:58 PM PDT 24
Finished Jul 25 06:55:24 PM PDT 24
Peak memory 218180 kb
Host smart-211c1bf6-579a-4cc1-8628-7ead495fca04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610135480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3610135480
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4058412233
Short name T387
Test name
Test status
Simulation time 156531229 ps
CPU time 1.23 seconds
Started Jul 25 06:54:57 PM PDT 24
Finished Jul 25 06:54:59 PM PDT 24
Peak memory 200152 kb
Host smart-1d492ec2-f3be-449d-999f-87a2a3169415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058412233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4058412233
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1997943199
Short name T453
Test name
Test status
Simulation time 190112791 ps
CPU time 1.38 seconds
Started Jul 25 06:54:59 PM PDT 24
Finished Jul 25 06:55:00 PM PDT 24
Peak memory 200344 kb
Host smart-61243a92-3ee6-421f-8176-9aafa0a34827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997943199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1997943199
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.768715113
Short name T340
Test name
Test status
Simulation time 8131882213 ps
CPU time 34.4 seconds
Started Jul 25 06:55:03 PM PDT 24
Finished Jul 25 06:55:38 PM PDT 24
Peak memory 208684 kb
Host smart-b39d9f70-895c-4d42-91ee-0ee13b2bbeb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768715113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.768715113
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1786170453
Short name T522
Test name
Test status
Simulation time 340276072 ps
CPU time 2.28 seconds
Started Jul 25 06:55:00 PM PDT 24
Finished Jul 25 06:55:02 PM PDT 24
Peak memory 208348 kb
Host smart-138084ce-70e6-43ea-bf53-7ee750c8bcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786170453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1786170453
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3342554980
Short name T336
Test name
Test status
Simulation time 218277018 ps
CPU time 1.48 seconds
Started Jul 25 06:55:00 PM PDT 24
Finished Jul 25 06:55:02 PM PDT 24
Peak memory 200136 kb
Host smart-28ca823e-a65f-427d-9a1f-db42ab7e02c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342554980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3342554980
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1014249720
Short name T252
Test name
Test status
Simulation time 68031700 ps
CPU time 0.77 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:26 PM PDT 24
Peak memory 199940 kb
Host smart-6c93204d-ce3e-4395-957a-70f3d75d82a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014249720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1014249720
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.4290267061
Short name T486
Test name
Test status
Simulation time 1895919786 ps
CPU time 6.78 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:23 PM PDT 24
Peak memory 217480 kb
Host smart-2b9a2bc9-4b0b-4c81-934b-1456fb5483e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290267061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.4290267061
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.4064463895
Short name T448
Test name
Test status
Simulation time 243782006 ps
CPU time 1.12 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:17 PM PDT 24
Peak memory 217540 kb
Host smart-3a400897-7637-400b-85e5-764c82230c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064463895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.4064463895
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2448415837
Short name T376
Test name
Test status
Simulation time 205283649 ps
CPU time 0.99 seconds
Started Jul 25 06:56:17 PM PDT 24
Finished Jul 25 06:56:18 PM PDT 24
Peak memory 199948 kb
Host smart-c7d3550f-7691-4625-95ff-2f18d2da524b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448415837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2448415837
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.823086863
Short name T13
Test name
Test status
Simulation time 1908472459 ps
CPU time 7.22 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:23 PM PDT 24
Peak memory 200500 kb
Host smart-fa2645d6-325d-4fd2-b721-0d7af87f92bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823086863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.823086863
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1688341298
Short name T241
Test name
Test status
Simulation time 176488337 ps
CPU time 1.22 seconds
Started Jul 25 06:56:18 PM PDT 24
Finished Jul 25 06:56:19 PM PDT 24
Peak memory 200116 kb
Host smart-9a7f4c2a-c99b-4c7a-b2f8-52dd980af73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688341298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1688341298
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3532174131
Short name T276
Test name
Test status
Simulation time 194065014 ps
CPU time 1.4 seconds
Started Jul 25 06:56:18 PM PDT 24
Finished Jul 25 06:56:20 PM PDT 24
Peak memory 200348 kb
Host smart-d8ebe336-2f43-4e6f-99c3-91481310b9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532174131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3532174131
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1572888106
Short name T129
Test name
Test status
Simulation time 7876845732 ps
CPU time 27.65 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:44 PM PDT 24
Peak memory 209492 kb
Host smart-a675d2b5-931c-4914-bdbb-c09b6998faef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572888106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1572888106
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.502377365
Short name T166
Test name
Test status
Simulation time 371460178 ps
CPU time 2.44 seconds
Started Jul 25 06:56:18 PM PDT 24
Finished Jul 25 06:56:21 PM PDT 24
Peak memory 200192 kb
Host smart-90c44ae6-4305-40de-bc69-8ac5b7942d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502377365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.502377365
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3888711763
Short name T300
Test name
Test status
Simulation time 162743703 ps
CPU time 1.23 seconds
Started Jul 25 06:56:18 PM PDT 24
Finished Jul 25 06:56:19 PM PDT 24
Peak memory 200156 kb
Host smart-3e0be4a8-6f32-453a-8b6d-4096059d137d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888711763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3888711763
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1817513456
Short name T235
Test name
Test status
Simulation time 56192060 ps
CPU time 0.73 seconds
Started Jul 25 06:56:18 PM PDT 24
Finished Jul 25 06:56:19 PM PDT 24
Peak memory 199948 kb
Host smart-68250bcd-30f4-414c-8981-fb6f48fd83fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817513456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1817513456
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1332824155
Short name T308
Test name
Test status
Simulation time 244649386 ps
CPU time 1.06 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:17 PM PDT 24
Peak memory 217508 kb
Host smart-30093657-ef00-4c9b-8f53-76bed85851d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332824155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1332824155
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.4095399136
Short name T16
Test name
Test status
Simulation time 189413169 ps
CPU time 0.87 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:17 PM PDT 24
Peak memory 199948 kb
Host smart-7329e41d-6d77-4bb4-9f5f-986ad99b4c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095399136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.4095399136
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.683689146
Short name T9
Test name
Test status
Simulation time 1104209020 ps
CPU time 5.04 seconds
Started Jul 25 06:56:18 PM PDT 24
Finished Jul 25 06:56:23 PM PDT 24
Peak memory 200448 kb
Host smart-7fa000bb-dfb6-463c-97e7-cd32ebaa8de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683689146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.683689146
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3134069657
Short name T400
Test name
Test status
Simulation time 152575372 ps
CPU time 1.12 seconds
Started Jul 25 06:56:15 PM PDT 24
Finished Jul 25 06:56:16 PM PDT 24
Peak memory 200092 kb
Host smart-c3d50354-b325-4559-9cc3-3fb994c61132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134069657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3134069657
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1643511805
Short name T205
Test name
Test status
Simulation time 250525224 ps
CPU time 1.46 seconds
Started Jul 25 06:56:24 PM PDT 24
Finished Jul 25 06:56:25 PM PDT 24
Peak memory 200328 kb
Host smart-099692cc-11f6-41df-855e-bc9ecdf4e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643511805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1643511805
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2564527978
Short name T406
Test name
Test status
Simulation time 4583742491 ps
CPU time 19.8 seconds
Started Jul 25 06:56:38 PM PDT 24
Finished Jul 25 06:56:58 PM PDT 24
Peak memory 208688 kb
Host smart-03d3d430-4904-4c0d-936f-716d45aeecf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564527978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2564527978
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2024743545
Short name T503
Test name
Test status
Simulation time 142161822 ps
CPU time 1.91 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:18 PM PDT 24
Peak memory 200132 kb
Host smart-af1f7d2a-7147-4fde-9370-73d91646cebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024743545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2024743545
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.4209840734
Short name T362
Test name
Test status
Simulation time 160871969 ps
CPU time 1.37 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:18 PM PDT 24
Peak memory 200304 kb
Host smart-cc227e19-09ee-40d0-8718-d7c944a57863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209840734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.4209840734
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.763380773
Short name T298
Test name
Test status
Simulation time 56702432 ps
CPU time 0.76 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:26 PM PDT 24
Peak memory 199952 kb
Host smart-ca533f18-ea1a-4a82-8912-9a4213554145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763380773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.763380773
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2146634754
Short name T219
Test name
Test status
Simulation time 2353225947 ps
CPU time 8.63 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:33 PM PDT 24
Peak memory 217852 kb
Host smart-1f061c94-ce0b-40cf-a11d-7b85b8245274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146634754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2146634754
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2501692169
Short name T458
Test name
Test status
Simulation time 243901393 ps
CPU time 1.11 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:26 PM PDT 24
Peak memory 217476 kb
Host smart-7e41f595-d76e-4902-b6b7-873d1949a1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501692169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2501692169
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3692078030
Short name T442
Test name
Test status
Simulation time 230113093 ps
CPU time 0.91 seconds
Started Jul 25 06:56:15 PM PDT 24
Finished Jul 25 06:56:16 PM PDT 24
Peak memory 199904 kb
Host smart-304a0365-dd4f-4411-9776-3405cbe98c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692078030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3692078030
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3575156566
Short name T234
Test name
Test status
Simulation time 743419527 ps
CPU time 3.9 seconds
Started Jul 25 06:56:16 PM PDT 24
Finished Jul 25 06:56:20 PM PDT 24
Peak memory 200408 kb
Host smart-db288d2a-c59b-4eb8-9c9d-a6e47471a7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575156566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3575156566
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2578334332
Short name T206
Test name
Test status
Simulation time 108747617 ps
CPU time 1.05 seconds
Started Jul 25 06:56:26 PM PDT 24
Finished Jul 25 06:56:27 PM PDT 24
Peak memory 200144 kb
Host smart-d5077c2c-85ea-409b-ad60-5331c9f55f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578334332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2578334332
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2884031309
Short name T267
Test name
Test status
Simulation time 250148552 ps
CPU time 1.43 seconds
Started Jul 25 06:56:24 PM PDT 24
Finished Jul 25 06:56:26 PM PDT 24
Peak memory 200332 kb
Host smart-e4fd03d0-09a1-4f62-8298-aca29fc548d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884031309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2884031309
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1368282688
Short name T272
Test name
Test status
Simulation time 4528809351 ps
CPU time 19.96 seconds
Started Jul 25 06:56:26 PM PDT 24
Finished Jul 25 06:56:46 PM PDT 24
Peak memory 200488 kb
Host smart-c6be50e9-565f-4e94-8d0b-9d5201d8b1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368282688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1368282688
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2261923195
Short name T421
Test name
Test status
Simulation time 286993419 ps
CPU time 2.05 seconds
Started Jul 25 06:56:26 PM PDT 24
Finished Jul 25 06:56:28 PM PDT 24
Peak memory 200160 kb
Host smart-b688bbcd-0398-4ccb-9b69-9fd9e1393a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261923195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2261923195
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.415938745
Short name T237
Test name
Test status
Simulation time 138611403 ps
CPU time 1.16 seconds
Started Jul 25 06:56:17 PM PDT 24
Finished Jul 25 06:56:18 PM PDT 24
Peak memory 200128 kb
Host smart-f5a0a363-584d-41f3-952c-1acfd0c76196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415938745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.415938745
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.4005677668
Short name T170
Test name
Test status
Simulation time 60744061 ps
CPU time 0.73 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:25 PM PDT 24
Peak memory 199912 kb
Host smart-7c6f5136-bebc-48a8-a377-a5146c604915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005677668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.4005677668
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3683391806
Short name T412
Test name
Test status
Simulation time 1228371421 ps
CPU time 5.81 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:31 PM PDT 24
Peak memory 221772 kb
Host smart-28d9d2b5-e454-408d-8ea9-3309f14db625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683391806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3683391806
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1540838286
Short name T180
Test name
Test status
Simulation time 244491066 ps
CPU time 1.03 seconds
Started Jul 25 06:56:24 PM PDT 24
Finished Jul 25 06:56:25 PM PDT 24
Peak memory 217472 kb
Host smart-86ca6a23-33c3-410b-99be-c8e9b1a46120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540838286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1540838286
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1278604513
Short name T15
Test name
Test status
Simulation time 118703092 ps
CPU time 0.77 seconds
Started Jul 25 06:56:24 PM PDT 24
Finished Jul 25 06:56:25 PM PDT 24
Peak memory 199896 kb
Host smart-02be08d2-00e2-496a-81b2-2eaf3fb06046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278604513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1278604513
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2991077200
Short name T83
Test name
Test status
Simulation time 1326410833 ps
CPU time 5.12 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:30 PM PDT 24
Peak memory 200412 kb
Host smart-f7a54eff-36fa-4851-a88b-82671db98595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991077200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2991077200
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2433588311
Short name T361
Test name
Test status
Simulation time 105609088 ps
CPU time 1 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:26 PM PDT 24
Peak memory 200144 kb
Host smart-5d14597b-5453-4d2c-8547-bc7a9f6d34b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433588311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2433588311
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1782376626
Short name T127
Test name
Test status
Simulation time 203900129 ps
CPU time 1.42 seconds
Started Jul 25 06:56:24 PM PDT 24
Finished Jul 25 06:56:25 PM PDT 24
Peak memory 200356 kb
Host smart-6736fc77-185b-42ef-a0ba-2fda0a2c7735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782376626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1782376626
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3824532236
Short name T341
Test name
Test status
Simulation time 2534925038 ps
CPU time 9.56 seconds
Started Jul 25 06:56:26 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 208648 kb
Host smart-ce70e044-b9ce-45a9-9dbf-946c479fce36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824532236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3824532236
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2853803102
Short name T218
Test name
Test status
Simulation time 370417739 ps
CPU time 2.38 seconds
Started Jul 25 06:56:23 PM PDT 24
Finished Jul 25 06:56:26 PM PDT 24
Peak memory 200140 kb
Host smart-92725cf4-6636-48af-8f1f-0368d458fbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853803102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2853803102
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3118818796
Short name T383
Test name
Test status
Simulation time 115523806 ps
CPU time 1.01 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:26 PM PDT 24
Peak memory 200148 kb
Host smart-9228bdae-f0f6-4d3c-aaa1-95c5f2f638b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118818796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3118818796
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3462140195
Short name T444
Test name
Test status
Simulation time 67526185 ps
CPU time 0.81 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:35 PM PDT 24
Peak memory 199936 kb
Host smart-42f1e0a8-ac31-4a75-9f04-a9d84176c8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462140195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3462140195
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.672673000
Short name T430
Test name
Test status
Simulation time 1890345227 ps
CPU time 7.66 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:42 PM PDT 24
Peak memory 217736 kb
Host smart-49937086-ca39-4264-b024-c3170e628e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672673000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.672673000
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3718818738
Short name T130
Test name
Test status
Simulation time 245458654 ps
CPU time 1.07 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 217488 kb
Host smart-9a1fa37e-1421-4a18-9937-f326609f56c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718818738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3718818738
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2766373943
Short name T527
Test name
Test status
Simulation time 177361895 ps
CPU time 0.87 seconds
Started Jul 25 06:56:25 PM PDT 24
Finished Jul 25 06:56:26 PM PDT 24
Peak memory 199956 kb
Host smart-8ff7555c-bb30-4fc0-86b4-48f90e26244a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766373943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2766373943
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3746332185
Short name T495
Test name
Test status
Simulation time 927751852 ps
CPU time 4.65 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:41 PM PDT 24
Peak memory 200360 kb
Host smart-6c12910e-fd9c-4f0b-a577-0784ced1aad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746332185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3746332185
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3129808203
Short name T248
Test name
Test status
Simulation time 142983745 ps
CPU time 1.1 seconds
Started Jul 25 06:56:33 PM PDT 24
Finished Jul 25 06:56:34 PM PDT 24
Peak memory 200132 kb
Host smart-e5751811-b578-4c7a-a5f8-291eae68c17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129808203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3129808203
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2989979789
Short name T292
Test name
Test status
Simulation time 122118314 ps
CPU time 1.21 seconds
Started Jul 25 06:56:26 PM PDT 24
Finished Jul 25 06:56:27 PM PDT 24
Peak memory 200364 kb
Host smart-05abfc2c-22db-4f7f-9376-2ca84c360cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989979789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2989979789
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1913596658
Short name T186
Test name
Test status
Simulation time 8795361056 ps
CPU time 36.22 seconds
Started Jul 25 06:56:35 PM PDT 24
Finished Jul 25 06:57:11 PM PDT 24
Peak memory 208712 kb
Host smart-cd872882-e173-480a-826e-f0026429477e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913596658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1913596658
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3867957999
Short name T6
Test name
Test status
Simulation time 296163823 ps
CPU time 1.95 seconds
Started Jul 25 06:56:41 PM PDT 24
Finished Jul 25 06:56:43 PM PDT 24
Peak memory 208344 kb
Host smart-0adac215-5158-4345-9034-dedf11858566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867957999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3867957999
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1491061190
Short name T141
Test name
Test status
Simulation time 169741094 ps
CPU time 1.3 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:37 PM PDT 24
Peak memory 200400 kb
Host smart-2049f7b7-e632-4ad1-b8e1-b9f0a9b70262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491061190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1491061190
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2748986642
Short name T436
Test name
Test status
Simulation time 81817559 ps
CPU time 0.84 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:35 PM PDT 24
Peak memory 199964 kb
Host smart-d1ec1c39-cf19-4f9b-9864-4918cbd3affc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748986642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2748986642
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2256850383
Short name T499
Test name
Test status
Simulation time 2355796058 ps
CPU time 9.22 seconds
Started Jul 25 06:56:35 PM PDT 24
Finished Jul 25 06:56:45 PM PDT 24
Peak memory 217848 kb
Host smart-e1420678-50d3-442e-9d0c-d742507cf69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256850383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2256850383
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1109211924
Short name T514
Test name
Test status
Simulation time 244246733 ps
CPU time 1.06 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:35 PM PDT 24
Peak memory 217496 kb
Host smart-8715feea-3b72-44a0-9db6-8d6dd03e961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109211924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1109211924
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1747712485
Short name T226
Test name
Test status
Simulation time 227861582 ps
CPU time 0.97 seconds
Started Jul 25 06:56:35 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 199956 kb
Host smart-e8f1b89a-2605-42d0-ad67-2d2c2a662e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747712485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1747712485
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1283168592
Short name T403
Test name
Test status
Simulation time 1545635661 ps
CPU time 6.22 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:40 PM PDT 24
Peak memory 200452 kb
Host smart-de309581-5db1-4c38-8b2e-cb63f66d1a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283168592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1283168592
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1112077581
Short name T437
Test name
Test status
Simulation time 144484359 ps
CPU time 1.08 seconds
Started Jul 25 06:56:33 PM PDT 24
Finished Jul 25 06:56:35 PM PDT 24
Peak memory 200096 kb
Host smart-1c1fd3ba-390c-4795-886c-d93511220da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112077581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1112077581
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1219945857
Short name T402
Test name
Test status
Simulation time 250866246 ps
CPU time 1.49 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:37 PM PDT 24
Peak memory 200220 kb
Host smart-b3515625-76cf-4c10-b71a-d0afb13db8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219945857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1219945857
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2487926693
Short name T88
Test name
Test status
Simulation time 5212536614 ps
CPU time 18.34 seconds
Started Jul 25 06:56:38 PM PDT 24
Finished Jul 25 06:56:57 PM PDT 24
Peak memory 200468 kb
Host smart-7dbb4b54-4909-4d1a-b984-17899f98fd8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487926693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2487926693
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.404702356
Short name T446
Test name
Test status
Simulation time 358790351 ps
CPU time 2.43 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:37 PM PDT 24
Peak memory 200100 kb
Host smart-01a0b50b-0340-425e-ba86-2d73cec4f81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404702356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.404702356
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.810781735
Short name T471
Test name
Test status
Simulation time 117195807 ps
CPU time 0.92 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:37 PM PDT 24
Peak memory 200168 kb
Host smart-e723c184-53db-4727-b150-5df2b2fe0f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810781735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.810781735
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2880344009
Short name T370
Test name
Test status
Simulation time 70321788 ps
CPU time 0.79 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:37 PM PDT 24
Peak memory 199948 kb
Host smart-ce3377b9-2c77-4295-89c2-e84eca5fe2e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880344009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2880344009
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2340435689
Short name T366
Test name
Test status
Simulation time 1908263674 ps
CPU time 7.52 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:42 PM PDT 24
Peak memory 217792 kb
Host smart-d65cb32d-0184-4379-a24d-cc9803cddfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340435689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2340435689
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1887452756
Short name T119
Test name
Test status
Simulation time 244279898 ps
CPU time 1.03 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 217480 kb
Host smart-b6cd56f8-3a97-473a-85cd-79f162368782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887452756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1887452756
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3712877478
Short name T148
Test name
Test status
Simulation time 136695852 ps
CPU time 0.87 seconds
Started Jul 25 06:56:35 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 199992 kb
Host smart-62abe91f-aa71-42df-817d-60f15db13075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712877478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3712877478
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.376102791
Short name T202
Test name
Test status
Simulation time 1338340035 ps
CPU time 5.64 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:42 PM PDT 24
Peak memory 200476 kb
Host smart-dec2afef-17b8-44e3-96a3-2620b7232d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376102791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.376102791
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.159300645
Short name T207
Test name
Test status
Simulation time 154661692 ps
CPU time 1.25 seconds
Started Jul 25 06:56:35 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 200136 kb
Host smart-555b2db5-5698-4e64-9420-4c0ef8d86729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159300645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.159300645
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2278084241
Short name T230
Test name
Test status
Simulation time 234401096 ps
CPU time 1.51 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 200332 kb
Host smart-2beea790-56a3-4ac3-9d03-3070c9d58894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278084241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2278084241
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.61358326
Short name T262
Test name
Test status
Simulation time 9724769422 ps
CPU time 33.86 seconds
Started Jul 25 06:56:39 PM PDT 24
Finished Jul 25 06:57:13 PM PDT 24
Peak memory 200508 kb
Host smart-3072049b-cde9-4a2b-8327-93f32f25496d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61358326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.61358326
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.4070275583
Short name T147
Test name
Test status
Simulation time 481577807 ps
CPU time 2.57 seconds
Started Jul 25 06:56:35 PM PDT 24
Finished Jul 25 06:56:37 PM PDT 24
Peak memory 208356 kb
Host smart-4588a4a3-0cdb-4a65-8b2a-0701122e53c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070275583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.4070275583
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1537440260
Short name T355
Test name
Test status
Simulation time 256540885 ps
CPU time 1.39 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 200156 kb
Host smart-6bdd9427-f44e-4253-b10c-9122730ecbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537440260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1537440260
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.80071111
Short name T405
Test name
Test status
Simulation time 70731145 ps
CPU time 0.79 seconds
Started Jul 25 06:56:35 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 199964 kb
Host smart-4b547806-c0bb-40d5-92b7-2bd29fd3ea67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80071111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.80071111
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3973348814
Short name T480
Test name
Test status
Simulation time 1233590138 ps
CPU time 5.37 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:40 PM PDT 24
Peak memory 217776 kb
Host smart-c24b123a-2604-4fc2-bb69-04bda7fe173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973348814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3973348814
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.783153507
Short name T516
Test name
Test status
Simulation time 244001061 ps
CPU time 1.1 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:37 PM PDT 24
Peak memory 217480 kb
Host smart-0355f85e-dc88-4349-9535-2166dc3a6e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783153507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.783153507
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.258798511
Short name T189
Test name
Test status
Simulation time 144814497 ps
CPU time 0.79 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:35 PM PDT 24
Peak memory 199972 kb
Host smart-0111914d-496e-433a-9d40-edacd75aa1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258798511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.258798511
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2777300830
Short name T277
Test name
Test status
Simulation time 915950625 ps
CPU time 4.57 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:40 PM PDT 24
Peak memory 200416 kb
Host smart-e16d2b57-736a-441f-a802-8855648ef2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777300830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2777300830
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.942276006
Short name T365
Test name
Test status
Simulation time 113578605 ps
CPU time 1.03 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:37 PM PDT 24
Peak memory 200156 kb
Host smart-da724bba-c3c0-4c0c-83cc-1e7485307cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942276006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.942276006
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.662826917
Short name T327
Test name
Test status
Simulation time 238406520 ps
CPU time 1.54 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:38 PM PDT 24
Peak memory 200336 kb
Host smart-8e888d7e-deb4-472f-997d-4f15d877e6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662826917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.662826917
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.838756762
Short name T293
Test name
Test status
Simulation time 3345435394 ps
CPU time 15.49 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:49 PM PDT 24
Peak memory 200476 kb
Host smart-c6b2c703-a5f5-4b93-83f0-3c77d9f90f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838756762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.838756762
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3817834969
Short name T399
Test name
Test status
Simulation time 366742031 ps
CPU time 2.25 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 200196 kb
Host smart-eda8fc0e-919b-4a75-88f1-a834fe411e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817834969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3817834969
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.536216849
Short name T200
Test name
Test status
Simulation time 104621747 ps
CPU time 0.92 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:35 PM PDT 24
Peak memory 200132 kb
Host smart-1d8be8a5-46fc-4b8c-a78f-bd447ce7834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536216849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.536216849
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2061227369
Short name T204
Test name
Test status
Simulation time 76915923 ps
CPU time 0.82 seconds
Started Jul 25 06:56:43 PM PDT 24
Finished Jul 25 06:56:44 PM PDT 24
Peak memory 199944 kb
Host smart-1f0afbec-aefd-49de-91c2-ee199530b6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061227369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2061227369
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3957948398
Short name T37
Test name
Test status
Simulation time 2377380074 ps
CPU time 8.06 seconds
Started Jul 25 06:56:47 PM PDT 24
Finished Jul 25 06:56:55 PM PDT 24
Peak memory 221900 kb
Host smart-09c63925-2178-4ff4-bc95-8dfdbb0d932d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957948398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3957948398
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.920533709
Short name T466
Test name
Test status
Simulation time 243917619 ps
CPU time 1.07 seconds
Started Jul 25 06:56:45 PM PDT 24
Finished Jul 25 06:56:46 PM PDT 24
Peak memory 217532 kb
Host smart-dc74af29-bc80-4d59-bfa6-4bda7e1c3b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920533709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.920533709
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3003611800
Short name T22
Test name
Test status
Simulation time 141195273 ps
CPU time 0.81 seconds
Started Jul 25 06:56:35 PM PDT 24
Finished Jul 25 06:56:36 PM PDT 24
Peak memory 199940 kb
Host smart-4cd6e058-0bc8-49a1-bc36-eda0549d70ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003611800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3003611800
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.43732066
Short name T460
Test name
Test status
Simulation time 849075704 ps
CPU time 4.53 seconds
Started Jul 25 06:56:34 PM PDT 24
Finished Jul 25 06:56:38 PM PDT 24
Peak memory 200404 kb
Host smart-9f1596c8-8166-4385-a59d-aa1f5499d4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43732066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.43732066
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1249898885
Short name T175
Test name
Test status
Simulation time 189070893 ps
CPU time 1.31 seconds
Started Jul 25 06:56:45 PM PDT 24
Finished Jul 25 06:56:47 PM PDT 24
Peak memory 200116 kb
Host smart-4e0c100e-1b52-417e-ab28-3d3046455c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249898885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1249898885
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.665063006
Short name T307
Test name
Test status
Simulation time 224858591 ps
CPU time 1.43 seconds
Started Jul 25 06:56:43 PM PDT 24
Finished Jul 25 06:56:45 PM PDT 24
Peak memory 200356 kb
Host smart-219004b3-ddc9-433d-8758-465364829934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665063006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.665063006
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.427940583
Short name T408
Test name
Test status
Simulation time 3275677589 ps
CPU time 14.37 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:58 PM PDT 24
Peak memory 208628 kb
Host smart-caa21bb9-a99e-40b5-8a27-0e67339f3c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427940583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.427940583
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3407717540
Short name T511
Test name
Test status
Simulation time 129609273 ps
CPU time 1.45 seconds
Started Jul 25 06:56:36 PM PDT 24
Finished Jul 25 06:56:38 PM PDT 24
Peak memory 200172 kb
Host smart-ac8dc5d9-1f3e-434c-b497-317a32a8d1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407717540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3407717540
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3070564832
Short name T434
Test name
Test status
Simulation time 143831491 ps
CPU time 1.06 seconds
Started Jul 25 06:56:37 PM PDT 24
Finished Jul 25 06:56:39 PM PDT 24
Peak memory 200152 kb
Host smart-22cc95d2-2f36-4550-a56e-ea15ec525b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070564832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3070564832
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.416565500
Short name T194
Test name
Test status
Simulation time 83197153 ps
CPU time 0.83 seconds
Started Jul 25 06:56:48 PM PDT 24
Finished Jul 25 06:56:49 PM PDT 24
Peak memory 199944 kb
Host smart-88f051fd-9a93-4a09-bcfb-dda7a26aba36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416565500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.416565500
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3043836693
Short name T10
Test name
Test status
Simulation time 245316658 ps
CPU time 1.02 seconds
Started Jul 25 06:56:43 PM PDT 24
Finished Jul 25 06:56:44 PM PDT 24
Peak memory 217556 kb
Host smart-84d92817-5d43-4b6f-8162-d015b3532ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043836693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3043836693
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1423030290
Short name T229
Test name
Test status
Simulation time 192820330 ps
CPU time 0.89 seconds
Started Jul 25 06:56:46 PM PDT 24
Finished Jul 25 06:56:47 PM PDT 24
Peak memory 199964 kb
Host smart-8ff788c9-60e3-4702-9938-b414e70c67ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423030290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1423030290
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2516045831
Short name T264
Test name
Test status
Simulation time 824990272 ps
CPU time 4.12 seconds
Started Jul 25 06:56:46 PM PDT 24
Finished Jul 25 06:56:50 PM PDT 24
Peak memory 200400 kb
Host smart-5b59e9c7-24b0-47cf-9059-eb7be71b0554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516045831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2516045831
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2178360515
Short name T211
Test name
Test status
Simulation time 105316168 ps
CPU time 0.99 seconds
Started Jul 25 06:56:42 PM PDT 24
Finished Jul 25 06:56:43 PM PDT 24
Peak memory 200144 kb
Host smart-9299232c-0f58-43e8-bd9f-ef78eda2f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178360515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2178360515
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.49594758
Short name T493
Test name
Test status
Simulation time 206235063 ps
CPU time 1.34 seconds
Started Jul 25 06:56:42 PM PDT 24
Finished Jul 25 06:56:43 PM PDT 24
Peak memory 200348 kb
Host smart-3552322e-0ac6-4b1a-b216-ed93346e460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49594758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.49594758
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3717069630
Short name T270
Test name
Test status
Simulation time 6849300960 ps
CPU time 24.56 seconds
Started Jul 25 06:56:45 PM PDT 24
Finished Jul 25 06:57:10 PM PDT 24
Peak memory 200524 kb
Host smart-7cbab3c0-9844-46e4-8c02-b6dc76c2f3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717069630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3717069630
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1111291527
Short name T228
Test name
Test status
Simulation time 314876607 ps
CPU time 1.88 seconds
Started Jul 25 06:56:43 PM PDT 24
Finished Jul 25 06:56:45 PM PDT 24
Peak memory 200088 kb
Host smart-d8ec6e02-1a8f-4e23-b43f-db93d586420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111291527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1111291527
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2210349813
Short name T55
Test name
Test status
Simulation time 54081448 ps
CPU time 0.72 seconds
Started Jul 25 06:55:00 PM PDT 24
Finished Jul 25 06:55:00 PM PDT 24
Peak memory 199944 kb
Host smart-307b8592-e4aa-4ef8-96cd-4faf989626be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210349813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2210349813
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2716528263
Short name T43
Test name
Test status
Simulation time 2384623556 ps
CPU time 8.62 seconds
Started Jul 25 06:55:02 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 217988 kb
Host smart-f0c76e38-9bc4-49e0-8949-a0ffda081feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716528263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2716528263
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2981765188
Short name T239
Test name
Test status
Simulation time 244279788 ps
CPU time 1.09 seconds
Started Jul 25 06:55:02 PM PDT 24
Finished Jul 25 06:55:03 PM PDT 24
Peak memory 217504 kb
Host smart-a87dc94f-ec46-4219-93c1-41c001c92ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981765188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2981765188
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1861350015
Short name T378
Test name
Test status
Simulation time 113324899 ps
CPU time 0.79 seconds
Started Jul 25 06:55:00 PM PDT 24
Finished Jul 25 06:55:01 PM PDT 24
Peak memory 199988 kb
Host smart-5d097109-d78d-4e1f-a037-a3be6217821f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861350015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1861350015
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.295178172
Short name T280
Test name
Test status
Simulation time 1599251606 ps
CPU time 5.91 seconds
Started Jul 25 06:55:01 PM PDT 24
Finished Jul 25 06:55:07 PM PDT 24
Peak memory 200412 kb
Host smart-a1d988f6-0ba3-446a-aef0-829c89e7c971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295178172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.295178172
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1850129207
Short name T60
Test name
Test status
Simulation time 8371349691 ps
CPU time 12.5 seconds
Started Jul 25 06:55:00 PM PDT 24
Finished Jul 25 06:55:13 PM PDT 24
Peak memory 221292 kb
Host smart-d7c01ae5-408a-43de-8cf9-9997327c7654
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850129207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1850129207
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3173323084
Short name T507
Test name
Test status
Simulation time 100278701 ps
CPU time 0.99 seconds
Started Jul 25 06:55:02 PM PDT 24
Finished Jul 25 06:55:03 PM PDT 24
Peak memory 200128 kb
Host smart-a208d854-1939-4cd1-b587-18b609852bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173323084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3173323084
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2820386683
Short name T490
Test name
Test status
Simulation time 116742097 ps
CPU time 1.29 seconds
Started Jul 25 06:54:58 PM PDT 24
Finished Jul 25 06:54:59 PM PDT 24
Peak memory 200344 kb
Host smart-f15b442d-8356-4087-875e-f657233e2cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820386683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2820386683
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2469581226
Short name T333
Test name
Test status
Simulation time 842283024 ps
CPU time 4.74 seconds
Started Jul 25 06:55:00 PM PDT 24
Finished Jul 25 06:55:05 PM PDT 24
Peak memory 208580 kb
Host smart-14700bf0-ae69-412d-be80-f9d55ba224b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469581226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2469581226
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3420912141
Short name T338
Test name
Test status
Simulation time 120745050 ps
CPU time 1.5 seconds
Started Jul 25 06:54:58 PM PDT 24
Finished Jul 25 06:54:59 PM PDT 24
Peak memory 200148 kb
Host smart-d953950c-c433-471b-8eb6-ddadeabd0579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420912141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3420912141
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1240958340
Short name T162
Test name
Test status
Simulation time 119581045 ps
CPU time 1.12 seconds
Started Jul 25 06:55:01 PM PDT 24
Finished Jul 25 06:55:03 PM PDT 24
Peak memory 200144 kb
Host smart-8836150a-89d5-4ed1-a492-3c1407a00aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240958340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1240958340
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.384517423
Short name T478
Test name
Test status
Simulation time 64207209 ps
CPU time 0.79 seconds
Started Jul 25 06:57:10 PM PDT 24
Finished Jul 25 06:57:11 PM PDT 24
Peak memory 199960 kb
Host smart-b792f203-eeb8-4313-8650-4abbe85239c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384517423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.384517423
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2143483880
Short name T325
Test name
Test status
Simulation time 1891049209 ps
CPU time 7.98 seconds
Started Jul 25 06:56:48 PM PDT 24
Finished Jul 25 06:56:56 PM PDT 24
Peak memory 215856 kb
Host smart-8771f4ab-5d03-474a-9203-c70d15147358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143483880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2143483880
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3056181075
Short name T306
Test name
Test status
Simulation time 244324132 ps
CPU time 1.14 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:46 PM PDT 24
Peak memory 217564 kb
Host smart-893cf29f-db7c-4bf5-95ec-dcc0ca21e23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056181075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3056181075
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1041623100
Short name T504
Test name
Test status
Simulation time 106364561 ps
CPU time 0.77 seconds
Started Jul 25 06:56:43 PM PDT 24
Finished Jul 25 06:56:43 PM PDT 24
Peak memory 199964 kb
Host smart-9edb246c-ca1f-4d78-9d05-3027b7c921d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041623100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1041623100
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2723243421
Short name T90
Test name
Test status
Simulation time 918330098 ps
CPU time 4.7 seconds
Started Jul 25 06:56:46 PM PDT 24
Finished Jul 25 06:56:51 PM PDT 24
Peak memory 200416 kb
Host smart-ed403cd1-7564-4ee7-ba26-3f3d421e5eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723243421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2723243421
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1343772419
Short name T513
Test name
Test status
Simulation time 187484499 ps
CPU time 1.23 seconds
Started Jul 25 06:56:51 PM PDT 24
Finished Jul 25 06:56:52 PM PDT 24
Peak memory 200124 kb
Host smart-0369c0a2-80d6-4c0f-bd08-b7e9d0a5633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343772419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1343772419
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.574198229
Short name T451
Test name
Test status
Simulation time 244791551 ps
CPU time 1.54 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:45 PM PDT 24
Peak memory 200352 kb
Host smart-ecd4b266-2cfa-4e48-a81f-ce3b8470a18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574198229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.574198229
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2618239642
Short name T25
Test name
Test status
Simulation time 6413835127 ps
CPU time 21.04 seconds
Started Jul 25 06:56:47 PM PDT 24
Finished Jul 25 06:57:08 PM PDT 24
Peak memory 200464 kb
Host smart-c451f897-72de-4f80-a9f7-0eebe0b5f723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618239642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2618239642
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2607919977
Short name T172
Test name
Test status
Simulation time 141439227 ps
CPU time 1.91 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:46 PM PDT 24
Peak memory 200152 kb
Host smart-c29e3b9d-ef2e-42bf-8a19-7180de338288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607919977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2607919977
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3391727502
Short name T120
Test name
Test status
Simulation time 111238869 ps
CPU time 1.05 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:45 PM PDT 24
Peak memory 200128 kb
Host smart-e4a80270-785c-4e9f-8641-997598de77c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391727502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3391727502
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1312026877
Short name T128
Test name
Test status
Simulation time 72873270 ps
CPU time 0.83 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:45 PM PDT 24
Peak memory 199948 kb
Host smart-7020dbea-f943-495f-ad18-f72461e3c57d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312026877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1312026877
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.30908495
Short name T41
Test name
Test status
Simulation time 1236007249 ps
CPU time 5.45 seconds
Started Jul 25 06:56:48 PM PDT 24
Finished Jul 25 06:56:53 PM PDT 24
Peak memory 217820 kb
Host smart-cefe6bf7-bfe0-4613-8cd7-366b0238fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30908495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.30908495
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4094181003
Short name T125
Test name
Test status
Simulation time 244609592 ps
CPU time 1.04 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:46 PM PDT 24
Peak memory 217468 kb
Host smart-ce086145-0be8-4079-aa8f-e299b659585b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094181003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4094181003
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.654491178
Short name T375
Test name
Test status
Simulation time 202191114 ps
CPU time 0.88 seconds
Started Jul 25 06:56:43 PM PDT 24
Finished Jul 25 06:56:44 PM PDT 24
Peak memory 199936 kb
Host smart-4c1440c1-27ea-4ca7-bc83-0789d3c47936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654491178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.654491178
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.4201156804
Short name T89
Test name
Test status
Simulation time 772445937 ps
CPU time 4 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:48 PM PDT 24
Peak memory 200408 kb
Host smart-0a38c3a4-009c-491d-b02f-a2d60dfeb0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201156804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.4201156804
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1784767184
Short name T64
Test name
Test status
Simulation time 150105820 ps
CPU time 1.16 seconds
Started Jul 25 06:56:46 PM PDT 24
Finished Jul 25 06:56:48 PM PDT 24
Peak memory 200144 kb
Host smart-04b20d98-052c-4655-b8ab-a42eb195b6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784767184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1784767184
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.9541251
Short name T302
Test name
Test status
Simulation time 227356026 ps
CPU time 1.52 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:46 PM PDT 24
Peak memory 200328 kb
Host smart-270e50f4-4acc-436d-96ac-3dbf209739d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9541251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.9541251
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1520215594
Short name T126
Test name
Test status
Simulation time 1603381656 ps
CPU time 6.57 seconds
Started Jul 25 06:56:48 PM PDT 24
Finished Jul 25 06:56:55 PM PDT 24
Peak memory 199476 kb
Host smart-eda4f92f-bb7c-4822-a18d-c53c499c6e04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520215594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1520215594
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3440788305
Short name T112
Test name
Test status
Simulation time 474085951 ps
CPU time 2.56 seconds
Started Jul 25 06:56:45 PM PDT 24
Finished Jul 25 06:56:47 PM PDT 24
Peak memory 208344 kb
Host smart-20c2c7aa-2901-445e-9e16-095a882eb132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440788305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3440788305
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3104922692
Short name T208
Test name
Test status
Simulation time 161954650 ps
CPU time 1.26 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:45 PM PDT 24
Peak memory 200352 kb
Host smart-5f8785de-b1e3-4cfd-8cca-fa450d542de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104922692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3104922692
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.346466574
Short name T390
Test name
Test status
Simulation time 74733036 ps
CPU time 0.8 seconds
Started Jul 25 06:56:45 PM PDT 24
Finished Jul 25 06:56:45 PM PDT 24
Peak memory 199940 kb
Host smart-be3ebbca-e68e-47fa-ba1c-2f4baf7bf8d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346466574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.346466574
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2803800073
Short name T40
Test name
Test status
Simulation time 2165882268 ps
CPU time 8.16 seconds
Started Jul 25 06:56:45 PM PDT 24
Finished Jul 25 06:56:53 PM PDT 24
Peak memory 217844 kb
Host smart-6f376772-755d-40a8-bebf-778e160d1288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803800073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2803800073
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.708440535
Short name T255
Test name
Test status
Simulation time 244235189 ps
CPU time 1.05 seconds
Started Jul 25 06:56:44 PM PDT 24
Finished Jul 25 06:56:46 PM PDT 24
Peak memory 217500 kb
Host smart-eab3ea87-16fd-423f-93d0-f3456748095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708440535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.708440535
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.860388497
Short name T474
Test name
Test status
Simulation time 104998744 ps
CPU time 0.79 seconds
Started Jul 25 06:56:46 PM PDT 24
Finished Jul 25 06:56:47 PM PDT 24
Peak memory 199952 kb
Host smart-1c71c28e-5ef2-4f47-8588-d48ea3f28fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860388497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.860388497
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1631268631
Short name T210
Test name
Test status
Simulation time 2035209922 ps
CPU time 6.95 seconds
Started Jul 25 06:56:47 PM PDT 24
Finished Jul 25 06:56:54 PM PDT 24
Peak memory 200416 kb
Host smart-704f97a3-d169-49d3-818c-21cee9d50b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631268631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1631268631
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3904582469
Short name T492
Test name
Test status
Simulation time 157065677 ps
CPU time 1.18 seconds
Started Jul 25 06:56:42 PM PDT 24
Finished Jul 25 06:56:43 PM PDT 24
Peak memory 200144 kb
Host smart-afbaa4c4-4749-45e6-a0c9-6d23553bdf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904582469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3904582469
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.609923859
Short name T63
Test name
Test status
Simulation time 114370082 ps
CPU time 1.18 seconds
Started Jul 25 06:56:42 PM PDT 24
Finished Jul 25 06:56:43 PM PDT 24
Peak memory 200392 kb
Host smart-a7d53095-fed2-4189-886f-569fc9968976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609923859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.609923859
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1746429309
Short name T61
Test name
Test status
Simulation time 7117302484 ps
CPU time 23.98 seconds
Started Jul 25 06:56:46 PM PDT 24
Finished Jul 25 06:57:10 PM PDT 24
Peak memory 208664 kb
Host smart-a93d6df5-a8f3-4d66-ba75-f88563c48130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746429309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1746429309
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1519591356
Short name T369
Test name
Test status
Simulation time 156996214 ps
CPU time 1.85 seconds
Started Jul 25 06:56:43 PM PDT 24
Finished Jul 25 06:56:45 PM PDT 24
Peak memory 200152 kb
Host smart-25cd573e-1563-45f2-a4bb-b1a5ae9971c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519591356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1519591356
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3959024660
Short name T145
Test name
Test status
Simulation time 169695380 ps
CPU time 1.35 seconds
Started Jul 25 06:56:47 PM PDT 24
Finished Jul 25 06:56:49 PM PDT 24
Peak memory 200356 kb
Host smart-ba7bb004-24e0-43f3-abb3-b3d7b2d10981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959024660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3959024660
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.840680908
Short name T310
Test name
Test status
Simulation time 56246727 ps
CPU time 0.77 seconds
Started Jul 25 06:56:55 PM PDT 24
Finished Jul 25 06:56:56 PM PDT 24
Peak memory 199956 kb
Host smart-87a0eed0-a753-48e7-9722-8d755845d67b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840680908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.840680908
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3802349179
Short name T398
Test name
Test status
Simulation time 1891383504 ps
CPU time 7.18 seconds
Started Jul 25 06:56:53 PM PDT 24
Finished Jul 25 06:57:00 PM PDT 24
Peak memory 217840 kb
Host smart-77c7729f-9b22-44e3-9532-e10ca1b87a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802349179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3802349179
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4165350841
Short name T441
Test name
Test status
Simulation time 244736797 ps
CPU time 1.04 seconds
Started Jul 25 06:56:52 PM PDT 24
Finished Jul 25 06:56:53 PM PDT 24
Peak memory 217480 kb
Host smart-f34d5ead-ae58-420a-bc11-77b6066d6802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165350841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4165350841
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1341554106
Short name T363
Test name
Test status
Simulation time 170122832 ps
CPU time 0.83 seconds
Started Jul 25 06:56:45 PM PDT 24
Finished Jul 25 06:56:46 PM PDT 24
Peak memory 199948 kb
Host smart-fd03c7a9-dec7-4520-b509-6e20673a5f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341554106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1341554106
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1384776803
Short name T68
Test name
Test status
Simulation time 1521626676 ps
CPU time 5.91 seconds
Started Jul 25 06:56:52 PM PDT 24
Finished Jul 25 06:56:58 PM PDT 24
Peak memory 200472 kb
Host smart-cbe5b371-8216-4495-9888-e458da21e0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384776803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1384776803
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.4139392810
Short name T258
Test name
Test status
Simulation time 140791135 ps
CPU time 1.15 seconds
Started Jul 25 06:56:52 PM PDT 24
Finished Jul 25 06:56:54 PM PDT 24
Peak memory 200084 kb
Host smart-b1e50c5c-06c9-44d2-b8e5-b20cd165710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139392810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.4139392810
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3392854248
Short name T285
Test name
Test status
Simulation time 231607404 ps
CPU time 1.47 seconds
Started Jul 25 06:56:45 PM PDT 24
Finished Jul 25 06:56:47 PM PDT 24
Peak memory 200396 kb
Host smart-9cacb61a-7ef1-486e-be57-d242427240fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392854248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3392854248
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2708240768
Short name T410
Test name
Test status
Simulation time 7229221114 ps
CPU time 25.89 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:57:20 PM PDT 24
Peak memory 208660 kb
Host smart-6e7cb35e-129f-4875-9523-930dc2f0620a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708240768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2708240768
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3382611535
Short name T161
Test name
Test status
Simulation time 144941334 ps
CPU time 1.85 seconds
Started Jul 25 06:56:56 PM PDT 24
Finished Jul 25 06:56:58 PM PDT 24
Peak memory 199564 kb
Host smart-cfa305e9-cb24-46c0-82b2-e47dfb429b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382611535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3382611535
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.4065546218
Short name T294
Test name
Test status
Simulation time 65525321 ps
CPU time 0.8 seconds
Started Jul 25 06:56:53 PM PDT 24
Finished Jul 25 06:56:54 PM PDT 24
Peak memory 200128 kb
Host smart-bcd9ad89-975d-4c02-8af5-e36834e7bb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065546218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.4065546218
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3904028924
Short name T133
Test name
Test status
Simulation time 77612759 ps
CPU time 0.82 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:56:55 PM PDT 24
Peak memory 199964 kb
Host smart-519a8963-8deb-46e2-8dfc-8f175f0edcff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904028924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3904028924
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3774265958
Short name T477
Test name
Test status
Simulation time 2194183209 ps
CPU time 7.72 seconds
Started Jul 25 06:56:52 PM PDT 24
Finished Jul 25 06:57:00 PM PDT 24
Peak memory 217860 kb
Host smart-4144f5e7-f616-4d14-8c36-a6e3b5344137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774265958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3774265958
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3540833406
Short name T502
Test name
Test status
Simulation time 244622945 ps
CPU time 1.17 seconds
Started Jul 25 06:56:55 PM PDT 24
Finished Jul 25 06:56:56 PM PDT 24
Peak memory 217504 kb
Host smart-3ab89833-4373-4418-96e2-be339e52f3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540833406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3540833406
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3147616551
Short name T20
Test name
Test status
Simulation time 111987867 ps
CPU time 0.84 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:56:55 PM PDT 24
Peak memory 199960 kb
Host smart-31254aea-ef76-47d2-a57a-843aad649cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147616551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3147616551
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3863442566
Short name T82
Test name
Test status
Simulation time 717490061 ps
CPU time 3.89 seconds
Started Jul 25 06:56:53 PM PDT 24
Finished Jul 25 06:56:57 PM PDT 24
Peak memory 200376 kb
Host smart-c6e974d2-2294-433c-91a0-584fb7651f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863442566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3863442566
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.4224653414
Short name T260
Test name
Test status
Simulation time 99199229 ps
CPU time 1.03 seconds
Started Jul 25 06:56:52 PM PDT 24
Finished Jul 25 06:56:53 PM PDT 24
Peak memory 200172 kb
Host smart-6d1080d8-ebfe-4571-a82c-8ff2ff0bdbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224653414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.4224653414
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2885328954
Short name T319
Test name
Test status
Simulation time 117528267 ps
CPU time 1.17 seconds
Started Jul 25 06:56:59 PM PDT 24
Finished Jul 25 06:57:01 PM PDT 24
Peak memory 200324 kb
Host smart-9a094ea2-e2a6-4895-a875-ac0b0fd9baa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885328954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2885328954
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1846912966
Short name T73
Test name
Test status
Simulation time 1438412272 ps
CPU time 5.76 seconds
Started Jul 25 06:56:51 PM PDT 24
Finished Jul 25 06:56:57 PM PDT 24
Peak memory 208620 kb
Host smart-b1f3f4ac-03b3-4c80-8854-27fddf44a552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846912966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1846912966
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3708820068
Short name T24
Test name
Test status
Simulation time 128149354 ps
CPU time 1.68 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:56:56 PM PDT 24
Peak memory 208360 kb
Host smart-54205808-9721-4e17-adfc-975a21bfb60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708820068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3708820068
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3425239882
Short name T364
Test name
Test status
Simulation time 112857925 ps
CPU time 0.94 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:56:55 PM PDT 24
Peak memory 200152 kb
Host smart-d7e3c24d-2b91-43b7-aafb-ac0d21266a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425239882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3425239882
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.298749302
Short name T323
Test name
Test status
Simulation time 74165577 ps
CPU time 0.81 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:56:55 PM PDT 24
Peak memory 199936 kb
Host smart-6470dea1-2ca6-4158-b70c-d5db137479d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298749302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.298749302
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2969931443
Short name T506
Test name
Test status
Simulation time 1233332968 ps
CPU time 5.95 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:57:00 PM PDT 24
Peak memory 217488 kb
Host smart-f5967397-0890-4aa8-b754-5c7b59e350c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969931443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2969931443
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4226658296
Short name T315
Test name
Test status
Simulation time 244624063 ps
CPU time 1.07 seconds
Started Jul 25 06:56:55 PM PDT 24
Finished Jul 25 06:56:56 PM PDT 24
Peak memory 217472 kb
Host smart-d9e0e879-7870-48ac-85f1-9eab24253dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226658296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4226658296
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1175894556
Short name T373
Test name
Test status
Simulation time 85324804 ps
CPU time 0.75 seconds
Started Jul 25 06:56:51 PM PDT 24
Finished Jul 25 06:56:52 PM PDT 24
Peak memory 199956 kb
Host smart-1122462f-6e2c-4608-9c56-65b6d0434bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175894556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1175894556
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.10438477
Short name T254
Test name
Test status
Simulation time 1700409588 ps
CPU time 7.39 seconds
Started Jul 25 06:56:55 PM PDT 24
Finished Jul 25 06:57:03 PM PDT 24
Peak memory 200420 kb
Host smart-e1297236-34a3-4677-9435-0ab3d8d1fc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10438477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.10438477
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3137714462
Short name T351
Test name
Test status
Simulation time 183981649 ps
CPU time 1.24 seconds
Started Jul 25 06:56:52 PM PDT 24
Finished Jul 25 06:56:53 PM PDT 24
Peak memory 200084 kb
Host smart-ad7f53f0-fa79-4f93-b722-b8a5de593f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137714462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3137714462
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1351275228
Short name T246
Test name
Test status
Simulation time 119774917 ps
CPU time 1.17 seconds
Started Jul 25 06:56:52 PM PDT 24
Finished Jul 25 06:56:53 PM PDT 24
Peak memory 200396 kb
Host smart-d89e6982-27df-4c93-a04a-367918ab7920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351275228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1351275228
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1635433659
Short name T261
Test name
Test status
Simulation time 8401350804 ps
CPU time 27.99 seconds
Started Jul 25 06:56:56 PM PDT 24
Finished Jul 25 06:57:24 PM PDT 24
Peak memory 199840 kb
Host smart-ade2d561-2503-46ee-a147-10731c121ae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635433659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1635433659
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.4174470916
Short name T291
Test name
Test status
Simulation time 297578408 ps
CPU time 1.96 seconds
Started Jul 25 06:56:52 PM PDT 24
Finished Jul 25 06:56:54 PM PDT 24
Peak memory 208284 kb
Host smart-aaa87ada-7d9d-4f46-8829-446042929a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174470916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.4174470916
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.500957902
Short name T321
Test name
Test status
Simulation time 158235063 ps
CPU time 1.06 seconds
Started Jul 25 06:56:59 PM PDT 24
Finished Jul 25 06:57:00 PM PDT 24
Peak memory 200128 kb
Host smart-41aeb0e5-52ff-437b-a4b8-cfa5b7a5da50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500957902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.500957902
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.331919020
Short name T526
Test name
Test status
Simulation time 71860610 ps
CPU time 0.74 seconds
Started Jul 25 06:56:53 PM PDT 24
Finished Jul 25 06:56:54 PM PDT 24
Peak memory 199948 kb
Host smart-11d78b24-dbc2-47eb-8762-9061bdeaa467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331919020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.331919020
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3039999330
Short name T489
Test name
Test status
Simulation time 2203350087 ps
CPU time 7.99 seconds
Started Jul 25 06:56:53 PM PDT 24
Finished Jul 25 06:57:01 PM PDT 24
Peak memory 216976 kb
Host smart-46e29d37-e25d-40d8-8e37-b60899aa5b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039999330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3039999330
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2520865098
Short name T192
Test name
Test status
Simulation time 244700636 ps
CPU time 1.04 seconds
Started Jul 25 06:56:57 PM PDT 24
Finished Jul 25 06:56:58 PM PDT 24
Peak memory 217536 kb
Host smart-517a7c39-6e94-469b-ad7e-2c4aec8d26e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520865098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2520865098
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2962388160
Short name T21
Test name
Test status
Simulation time 148108950 ps
CPU time 0.85 seconds
Started Jul 25 06:56:56 PM PDT 24
Finished Jul 25 06:56:57 PM PDT 24
Peak memory 199904 kb
Host smart-8431e058-d9ed-432b-b106-45b541b9d294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962388160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2962388160
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1875520026
Short name T81
Test name
Test status
Simulation time 1001663720 ps
CPU time 5.05 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:56:59 PM PDT 24
Peak memory 200408 kb
Host smart-06f19d28-452c-492b-a8e3-4e9587768fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875520026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1875520026
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2689183643
Short name T159
Test name
Test status
Simulation time 98571972 ps
CPU time 0.95 seconds
Started Jul 25 06:56:52 PM PDT 24
Finished Jul 25 06:56:53 PM PDT 24
Peak memory 200132 kb
Host smart-dbfc8392-b4f7-44b6-95d3-eeb12d8202b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689183643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2689183643
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1135980042
Short name T353
Test name
Test status
Simulation time 244615475 ps
CPU time 1.61 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:56:56 PM PDT 24
Peak memory 200384 kb
Host smart-703b78a3-a2c0-43ae-b904-d7ac6e9b9af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135980042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1135980042
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2989166978
Short name T344
Test name
Test status
Simulation time 4858936708 ps
CPU time 22.92 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:57:17 PM PDT 24
Peak memory 208716 kb
Host smart-16c12a5f-1e86-4fda-958a-9d61a9a1e8cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989166978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2989166978
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2862680451
Short name T233
Test name
Test status
Simulation time 137985197 ps
CPU time 1.64 seconds
Started Jul 25 06:56:53 PM PDT 24
Finished Jul 25 06:56:54 PM PDT 24
Peak memory 208348 kb
Host smart-53624f20-1ac3-4df9-8309-3d542a35930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862680451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2862680451
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1993512519
Short name T259
Test name
Test status
Simulation time 107611462 ps
CPU time 0.99 seconds
Started Jul 25 06:56:57 PM PDT 24
Finished Jul 25 06:56:58 PM PDT 24
Peak memory 200128 kb
Host smart-312950ba-8091-42ef-a24e-dfbc6cf066c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993512519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1993512519
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.238549516
Short name T463
Test name
Test status
Simulation time 68040551 ps
CPU time 0.78 seconds
Started Jul 25 06:56:53 PM PDT 24
Finished Jul 25 06:56:54 PM PDT 24
Peak memory 199948 kb
Host smart-015eb04c-4590-4981-a2ed-cbb0c6bddc07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238549516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.238549516
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.103474099
Short name T465
Test name
Test status
Simulation time 2352964009 ps
CPU time 8.52 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:57:03 PM PDT 24
Peak memory 217852 kb
Host smart-95cd1841-01f8-4d6c-8ee7-c73240f6c5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103474099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.103474099
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2874194187
Short name T404
Test name
Test status
Simulation time 244026826 ps
CPU time 1.08 seconds
Started Jul 25 06:56:53 PM PDT 24
Finished Jul 25 06:56:54 PM PDT 24
Peak memory 217496 kb
Host smart-8f779200-54d2-4c54-8a9c-11cc25e12895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874194187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2874194187
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1951744868
Short name T236
Test name
Test status
Simulation time 141908842 ps
CPU time 0.8 seconds
Started Jul 25 06:56:57 PM PDT 24
Finished Jul 25 06:56:58 PM PDT 24
Peak memory 199952 kb
Host smart-045ee412-4982-47ab-998a-ab81a0b6fcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951744868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1951744868
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3643813508
Short name T196
Test name
Test status
Simulation time 1113087796 ps
CPU time 4.91 seconds
Started Jul 25 06:56:58 PM PDT 24
Finished Jul 25 06:57:03 PM PDT 24
Peak memory 200392 kb
Host smart-76d73043-7b1a-4bc1-aa32-e8f80729e16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643813508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3643813508
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1805265179
Short name T273
Test name
Test status
Simulation time 144744715 ps
CPU time 1.09 seconds
Started Jul 25 06:56:55 PM PDT 24
Finished Jul 25 06:56:56 PM PDT 24
Peak memory 200092 kb
Host smart-85098f45-7533-40cd-a68e-414291d82080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805265179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1805265179
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1670466419
Short name T417
Test name
Test status
Simulation time 209533946 ps
CPU time 1.39 seconds
Started Jul 25 06:56:55 PM PDT 24
Finished Jul 25 06:56:57 PM PDT 24
Peak memory 200352 kb
Host smart-c6e1a051-871e-4ea4-b066-2626c049c8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670466419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1670466419
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2332279624
Short name T345
Test name
Test status
Simulation time 4306889211 ps
CPU time 13.71 seconds
Started Jul 25 06:56:55 PM PDT 24
Finished Jul 25 06:57:09 PM PDT 24
Peak memory 208632 kb
Host smart-85e1f348-d42e-4d03-884f-6111c2cf6234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332279624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2332279624
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1727174831
Short name T72
Test name
Test status
Simulation time 375458069 ps
CPU time 2.55 seconds
Started Jul 25 06:56:56 PM PDT 24
Finished Jul 25 06:56:58 PM PDT 24
Peak memory 200156 kb
Host smart-2a305597-9094-4f23-a3c1-481ae920aa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727174831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1727174831
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4191407045
Short name T201
Test name
Test status
Simulation time 243402008 ps
CPU time 1.43 seconds
Started Jul 25 06:56:54 PM PDT 24
Finished Jul 25 06:56:56 PM PDT 24
Peak memory 200316 kb
Host smart-4921eef5-6e12-494e-b447-4b99d7bf0eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191407045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4191407045
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3221880848
Short name T382
Test name
Test status
Simulation time 67452239 ps
CPU time 0.76 seconds
Started Jul 25 06:57:00 PM PDT 24
Finished Jul 25 06:57:01 PM PDT 24
Peak memory 199912 kb
Host smart-7d4b8e7d-fe37-48a5-a915-e5629a2a5a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221880848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3221880848
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3493865162
Short name T33
Test name
Test status
Simulation time 2375181589 ps
CPU time 8.18 seconds
Started Jul 25 06:57:02 PM PDT 24
Finished Jul 25 06:57:11 PM PDT 24
Peak memory 217144 kb
Host smart-3e140b86-df1a-4142-8604-396115aa504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493865162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3493865162
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.4081843797
Short name T138
Test name
Test status
Simulation time 243906392 ps
CPU time 1.1 seconds
Started Jul 25 06:57:00 PM PDT 24
Finished Jul 25 06:57:01 PM PDT 24
Peak memory 217488 kb
Host smart-5dae9808-b5cd-4fc9-9d2e-392d7e700e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081843797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.4081843797
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.237654930
Short name T309
Test name
Test status
Simulation time 205162119 ps
CPU time 0.98 seconds
Started Jul 25 06:57:01 PM PDT 24
Finished Jul 25 06:57:02 PM PDT 24
Peak memory 199988 kb
Host smart-8a41c01b-2ac9-4e60-9642-e9509444a1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237654930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.237654930
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3247650195
Short name T329
Test name
Test status
Simulation time 1222656981 ps
CPU time 5.28 seconds
Started Jul 25 06:57:00 PM PDT 24
Finished Jul 25 06:57:06 PM PDT 24
Peak memory 200416 kb
Host smart-64caca72-c484-4969-ac80-637aa7d67672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247650195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3247650195
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.302632088
Short name T435
Test name
Test status
Simulation time 113107934 ps
CPU time 1.11 seconds
Started Jul 25 06:57:03 PM PDT 24
Finished Jul 25 06:57:04 PM PDT 24
Peak memory 200180 kb
Host smart-37da14c4-4b29-44d0-a150-02dc2f7969ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302632088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.302632088
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.300292928
Short name T143
Test name
Test status
Simulation time 197273995 ps
CPU time 1.39 seconds
Started Jul 25 06:57:01 PM PDT 24
Finished Jul 25 06:57:02 PM PDT 24
Peak memory 200340 kb
Host smart-11695c3e-02a9-466b-8ef0-fa12e92ca087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300292928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.300292928
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2207176397
Short name T38
Test name
Test status
Simulation time 2610126678 ps
CPU time 11.95 seconds
Started Jul 25 06:57:02 PM PDT 24
Finished Jul 25 06:57:14 PM PDT 24
Peak memory 208680 kb
Host smart-0888d967-9000-455d-9228-9aa19cf259ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207176397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2207176397
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1875441541
Short name T290
Test name
Test status
Simulation time 254659850 ps
CPU time 1.73 seconds
Started Jul 25 06:57:03 PM PDT 24
Finished Jul 25 06:57:05 PM PDT 24
Peak memory 200160 kb
Host smart-c32ace3f-fb4c-43cd-94c5-2ac560cfb274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875441541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1875441541
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2117024194
Short name T469
Test name
Test status
Simulation time 73038051 ps
CPU time 0.87 seconds
Started Jul 25 06:57:02 PM PDT 24
Finished Jul 25 06:57:03 PM PDT 24
Peak memory 200144 kb
Host smart-942711bf-5c7e-46ec-8ec0-0eeff0bd123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117024194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2117024194
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1055380822
Short name T134
Test name
Test status
Simulation time 83702219 ps
CPU time 0.83 seconds
Started Jul 25 06:57:05 PM PDT 24
Finished Jul 25 06:57:06 PM PDT 24
Peak memory 199932 kb
Host smart-a4e3aeff-e5dd-4ecc-990f-78162d102cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055380822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1055380822
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1279900428
Short name T420
Test name
Test status
Simulation time 1898464761 ps
CPU time 6.92 seconds
Started Jul 25 06:57:10 PM PDT 24
Finished Jul 25 06:57:17 PM PDT 24
Peak memory 216812 kb
Host smart-c771354f-2ffe-4179-a79e-1e2e8f9cf3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279900428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1279900428
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3448665458
Short name T117
Test name
Test status
Simulation time 249164528 ps
CPU time 1.08 seconds
Started Jul 25 06:57:01 PM PDT 24
Finished Jul 25 06:57:02 PM PDT 24
Peak memory 217584 kb
Host smart-db50bd2f-5f37-48a6-94fe-6bdbf69f9b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448665458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3448665458
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2550179106
Short name T5
Test name
Test status
Simulation time 195371285 ps
CPU time 0.88 seconds
Started Jul 25 06:56:59 PM PDT 24
Finished Jul 25 06:57:00 PM PDT 24
Peak memory 199904 kb
Host smart-d699e126-53fb-40f9-bb19-6de482d2b727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550179106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2550179106
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2488480063
Short name T283
Test name
Test status
Simulation time 1997595428 ps
CPU time 7.09 seconds
Started Jul 25 06:57:01 PM PDT 24
Finished Jul 25 06:57:08 PM PDT 24
Peak memory 200408 kb
Host smart-937f951b-138d-4dee-af86-876c61a9a3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488480063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2488480063
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3678797301
Short name T445
Test name
Test status
Simulation time 158995630 ps
CPU time 1.29 seconds
Started Jul 25 06:57:02 PM PDT 24
Finished Jul 25 06:57:04 PM PDT 24
Peak memory 200140 kb
Host smart-c29d623d-1908-4bec-8956-ba5c19f2d301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678797301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3678797301
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3668590666
Short name T67
Test name
Test status
Simulation time 187039513 ps
CPU time 1.38 seconds
Started Jul 25 06:57:02 PM PDT 24
Finished Jul 25 06:57:03 PM PDT 24
Peak memory 200328 kb
Host smart-46f84aaf-4332-4ce5-989a-e4ba179215f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668590666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3668590666
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.82083413
Short name T388
Test name
Test status
Simulation time 3618061889 ps
CPU time 12.48 seconds
Started Jul 25 06:57:01 PM PDT 24
Finished Jul 25 06:57:13 PM PDT 24
Peak memory 208672 kb
Host smart-3a26c5b9-1497-4370-9106-e62a71974525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82083413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.82083413
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.215810996
Short name T409
Test name
Test status
Simulation time 477946958 ps
CPU time 2.48 seconds
Started Jul 25 06:57:06 PM PDT 24
Finished Jul 25 06:57:08 PM PDT 24
Peak memory 200136 kb
Host smart-19057307-ae17-436c-b25f-a7503d100010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215810996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.215810996
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.176310846
Short name T328
Test name
Test status
Simulation time 128829723 ps
CPU time 0.95 seconds
Started Jul 25 06:57:00 PM PDT 24
Finished Jul 25 06:57:01 PM PDT 24
Peak memory 200196 kb
Host smart-9403be02-026f-4b6d-b835-a5b89f3c558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176310846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.176310846
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2362933705
Short name T381
Test name
Test status
Simulation time 67950944 ps
CPU time 0.73 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 199952 kb
Host smart-bd9e0fe8-f93d-46df-b767-d642d75e5a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362933705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2362933705
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3164868334
Short name T352
Test name
Test status
Simulation time 1903596046 ps
CPU time 6.77 seconds
Started Jul 25 06:55:11 PM PDT 24
Finished Jul 25 06:55:17 PM PDT 24
Peak memory 217788 kb
Host smart-f7aba12b-dcba-4dcc-9001-360c59425687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164868334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3164868334
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2496494437
Short name T222
Test name
Test status
Simulation time 244368192 ps
CPU time 1.05 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 217364 kb
Host smart-44f61c23-b8a2-4234-8a1c-8177788cffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496494437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2496494437
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.996440333
Short name T342
Test name
Test status
Simulation time 161273381 ps
CPU time 0.86 seconds
Started Jul 25 06:55:02 PM PDT 24
Finished Jul 25 06:55:03 PM PDT 24
Peak memory 199944 kb
Host smart-6165fc9a-ab5a-4f22-8378-7c39e6d9d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996440333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.996440333
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.560202355
Short name T535
Test name
Test status
Simulation time 1468214805 ps
CPU time 5.36 seconds
Started Jul 25 06:54:55 PM PDT 24
Finished Jul 25 06:55:01 PM PDT 24
Peak memory 200416 kb
Host smart-691cb25a-a7bb-43a9-a622-382c5473404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560202355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.560202355
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3224900011
Short name T498
Test name
Test status
Simulation time 173608135 ps
CPU time 1.26 seconds
Started Jul 25 06:55:11 PM PDT 24
Finished Jul 25 06:55:12 PM PDT 24
Peak memory 200136 kb
Host smart-4056d91a-db6a-4012-83ff-0aae7cf4418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224900011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3224900011
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.466364131
Short name T2
Test name
Test status
Simulation time 119160855 ps
CPU time 1.21 seconds
Started Jul 25 06:54:59 PM PDT 24
Finished Jul 25 06:55:00 PM PDT 24
Peak memory 200376 kb
Host smart-5e1871e7-16aa-413e-9873-fb4c7368da13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466364131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.466364131
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3702049835
Short name T357
Test name
Test status
Simulation time 4527909213 ps
CPU time 20.19 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:30 PM PDT 24
Peak memory 208684 kb
Host smart-ea4f00f6-683b-43e8-9a98-e65764faeb55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702049835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3702049835
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.453230399
Short name T450
Test name
Test status
Simulation time 140155968 ps
CPU time 1.74 seconds
Started Jul 25 06:55:01 PM PDT 24
Finished Jul 25 06:55:03 PM PDT 24
Peak memory 200160 kb
Host smart-fd2e7e53-2461-4946-bca0-7f42326252a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453230399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.453230399
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2755929971
Short name T472
Test name
Test status
Simulation time 130117169 ps
CPU time 1.23 seconds
Started Jul 25 06:55:02 PM PDT 24
Finished Jul 25 06:55:04 PM PDT 24
Peak memory 200140 kb
Host smart-2ea834f1-1b6d-4f4f-9eaf-c4a20ecdca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755929971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2755929971
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.397821071
Short name T274
Test name
Test status
Simulation time 72784220 ps
CPU time 0.77 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 199940 kb
Host smart-a9ced894-b4fd-41e1-8c50-2a600bba247b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397821071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.397821071
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3116037953
Short name T29
Test name
Test status
Simulation time 1895263898 ps
CPU time 7.22 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:17 PM PDT 24
Peak memory 217772 kb
Host smart-c10585e0-2ba0-4687-9a3b-5aae626e0aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116037953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3116037953
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1388931326
Short name T407
Test name
Test status
Simulation time 244191027 ps
CPU time 1.05 seconds
Started Jul 25 06:55:11 PM PDT 24
Finished Jul 25 06:55:12 PM PDT 24
Peak memory 217484 kb
Host smart-0c604d4e-b1bf-4609-b4ec-a11132849c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388931326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1388931326
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3301145935
Short name T379
Test name
Test status
Simulation time 166651164 ps
CPU time 0.82 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 200004 kb
Host smart-940cff83-f6e6-456b-8b8b-d35c2f301869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301145935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3301145935
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.21835025
Short name T416
Test name
Test status
Simulation time 1683749825 ps
CPU time 6.68 seconds
Started Jul 25 06:55:12 PM PDT 24
Finished Jul 25 06:55:18 PM PDT 24
Peak memory 200404 kb
Host smart-039bf55a-a47b-4753-bb58-ec3e1a3aeaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21835025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.21835025
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3665784973
Short name T455
Test name
Test status
Simulation time 167901445 ps
CPU time 1.14 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 200116 kb
Host smart-160b970f-1960-4698-8452-e374cc68340a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665784973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3665784973
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.509957922
Short name T332
Test name
Test status
Simulation time 200998815 ps
CPU time 1.35 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:12 PM PDT 24
Peak memory 200332 kb
Host smart-86b7b17a-69bc-422a-be4a-e4c52e7ff390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509957922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.509957922
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.4158382113
Short name T350
Test name
Test status
Simulation time 8698810728 ps
CPU time 29.91 seconds
Started Jul 25 06:55:13 PM PDT 24
Finished Jul 25 06:55:43 PM PDT 24
Peak memory 208652 kb
Host smart-2f979b3b-671d-4440-a93f-1c29a249ce1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158382113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.4158382113
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1777311843
Short name T11
Test name
Test status
Simulation time 123622895 ps
CPU time 1.43 seconds
Started Jul 25 06:55:09 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 200156 kb
Host smart-3ca7073a-e930-46b6-9fa6-3848320c8d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777311843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1777311843
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1706295610
Short name T169
Test name
Test status
Simulation time 112121627 ps
CPU time 1.18 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:12 PM PDT 24
Peak memory 200108 kb
Host smart-8a43a7fd-34db-4321-a159-d2a8754bb454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706295610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1706295610
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1792668983
Short name T57
Test name
Test status
Simulation time 74656932 ps
CPU time 0.76 seconds
Started Jul 25 06:55:09 PM PDT 24
Finished Jul 25 06:55:10 PM PDT 24
Peak memory 199968 kb
Host smart-002f7551-fc4c-4fd3-8fd2-f3c7bf1157f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792668983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1792668983
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1811974677
Short name T1
Test name
Test status
Simulation time 2358252013 ps
CPU time 7.91 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:18 PM PDT 24
Peak memory 221784 kb
Host smart-5cd24ee4-8de7-4dfe-bc1e-6d5dfef0673e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811974677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1811974677
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1151284970
Short name T203
Test name
Test status
Simulation time 244331207 ps
CPU time 1.08 seconds
Started Jul 25 06:55:12 PM PDT 24
Finished Jul 25 06:55:13 PM PDT 24
Peak memory 217544 kb
Host smart-6d2f81d0-15d0-4917-9fe7-87300297c80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151284970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1151284970
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1328767308
Short name T224
Test name
Test status
Simulation time 179490429 ps
CPU time 0.83 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 199948 kb
Host smart-8465475b-9d67-4caf-8d6a-b5ca0cb1f06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328767308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1328767308
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1243993057
Short name T509
Test name
Test status
Simulation time 1525128960 ps
CPU time 5.66 seconds
Started Jul 25 06:55:09 PM PDT 24
Finished Jul 25 06:55:15 PM PDT 24
Peak memory 200436 kb
Host smart-53548a18-b413-445a-baba-c4786d59a1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243993057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1243993057
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2132197337
Short name T289
Test name
Test status
Simulation time 108732249 ps
CPU time 1 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 200180 kb
Host smart-eebd419b-26fa-4cf3-bec5-d9f904a62267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132197337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2132197337
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4146827489
Short name T171
Test name
Test status
Simulation time 186774306 ps
CPU time 1.32 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 200352 kb
Host smart-42d2c2d5-8f50-41d4-ba12-b9e98d7dae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146827489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4146827489
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1871524702
Short name T476
Test name
Test status
Simulation time 2910553862 ps
CPU time 15.11 seconds
Started Jul 25 06:55:12 PM PDT 24
Finished Jul 25 06:55:27 PM PDT 24
Peak memory 208680 kb
Host smart-0449d4c8-a11d-4af8-9d5f-1305f2d30fab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871524702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1871524702
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.910300012
Short name T160
Test name
Test status
Simulation time 146449320 ps
CPU time 1.81 seconds
Started Jul 25 06:56:08 PM PDT 24
Finished Jul 25 06:56:10 PM PDT 24
Peak memory 200164 kb
Host smart-2f4a5593-2ced-40d5-9a15-d75b66365230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910300012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.910300012
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2146391431
Short name T238
Test name
Test status
Simulation time 131564164 ps
CPU time 1.06 seconds
Started Jul 25 06:55:10 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 200144 kb
Host smart-ceae8454-fb1a-430b-9269-4db6e47add2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146391431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2146391431
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2321667197
Short name T154
Test name
Test status
Simulation time 70998572 ps
CPU time 0.8 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:22 PM PDT 24
Peak memory 199960 kb
Host smart-36b13dd8-8aec-4cae-befd-1a9ee8e07708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321667197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2321667197
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3108262039
Short name T36
Test name
Test status
Simulation time 1229796015 ps
CPU time 5.87 seconds
Started Jul 25 06:55:19 PM PDT 24
Finished Jul 25 06:55:25 PM PDT 24
Peak memory 221752 kb
Host smart-499720f3-eca1-4135-a5ac-6b0822e1eaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108262039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3108262039
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1623716983
Short name T123
Test name
Test status
Simulation time 244535431 ps
CPU time 1.14 seconds
Started Jul 25 06:55:19 PM PDT 24
Finished Jul 25 06:55:20 PM PDT 24
Peak memory 217540 kb
Host smart-552b16e7-d0dc-4b66-a404-99e6aa667238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623716983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1623716983
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.572636976
Short name T330
Test name
Test status
Simulation time 224872226 ps
CPU time 1.1 seconds
Started Jul 25 06:55:23 PM PDT 24
Finished Jul 25 06:55:24 PM PDT 24
Peak memory 199952 kb
Host smart-ac8a744c-a37a-42d5-a3ed-8ad01892f9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572636976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.572636976
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2621767716
Short name T209
Test name
Test status
Simulation time 1379243501 ps
CPU time 5.63 seconds
Started Jul 25 06:55:19 PM PDT 24
Finished Jul 25 06:55:25 PM PDT 24
Peak memory 200372 kb
Host smart-0b078699-a349-4f87-ac3a-9df42afe3c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621767716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2621767716
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.183238752
Short name T433
Test name
Test status
Simulation time 108446363 ps
CPU time 0.99 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:23 PM PDT 24
Peak memory 200124 kb
Host smart-363d908e-50e8-498b-9ddc-985869ea0da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183238752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.183238752
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1884429961
Short name T179
Test name
Test status
Simulation time 205939405 ps
CPU time 1.37 seconds
Started Jul 25 06:55:20 PM PDT 24
Finished Jul 25 06:55:21 PM PDT 24
Peak memory 200284 kb
Host smart-e54f95f8-4d8e-48ba-9039-6a7ffb75cc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884429961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1884429961
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2476705608
Short name T335
Test name
Test status
Simulation time 7941464621 ps
CPU time 30.35 seconds
Started Jul 25 06:55:22 PM PDT 24
Finished Jul 25 06:55:53 PM PDT 24
Peak memory 200460 kb
Host smart-732fb27a-076f-48bf-9c9f-b94adec0f585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476705608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2476705608
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2530377222
Short name T429
Test name
Test status
Simulation time 352106995 ps
CPU time 2.21 seconds
Started Jul 25 06:55:18 PM PDT 24
Finished Jul 25 06:55:20 PM PDT 24
Peak memory 200100 kb
Host smart-40adc8df-7f3e-48ee-b069-18aa6da65c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530377222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2530377222
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2699928065
Short name T213
Test name
Test status
Simulation time 240288638 ps
CPU time 1.49 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:23 PM PDT 24
Peak memory 200156 kb
Host smart-b8e71645-d4b6-4298-acf9-207e9dc188f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699928065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2699928065
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1026263088
Short name T311
Test name
Test status
Simulation time 85896677 ps
CPU time 0.82 seconds
Started Jul 25 06:55:24 PM PDT 24
Finished Jul 25 06:55:25 PM PDT 24
Peak memory 199952 kb
Host smart-6dcff85c-c8a0-40cd-8be1-53e862ea5d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026263088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1026263088
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3669969178
Short name T217
Test name
Test status
Simulation time 1225745100 ps
CPU time 5.47 seconds
Started Jul 25 06:55:20 PM PDT 24
Finished Jul 25 06:55:26 PM PDT 24
Peak memory 217808 kb
Host smart-4bd1ae08-02f2-479c-b085-c05cdab86e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669969178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3669969178
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3762293465
Short name T470
Test name
Test status
Simulation time 243447474 ps
CPU time 1.11 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:22 PM PDT 24
Peak memory 217496 kb
Host smart-2dc6e6a9-19db-447c-9e0c-556c4dc2d10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762293465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3762293465
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.4290917018
Short name T295
Test name
Test status
Simulation time 125535124 ps
CPU time 0.8 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:22 PM PDT 24
Peak memory 199960 kb
Host smart-7a710245-c1bd-430a-a859-b065b0ca18b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290917018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.4290917018
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.899502243
Short name T456
Test name
Test status
Simulation time 1955786736 ps
CPU time 7.51 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:29 PM PDT 24
Peak memory 200448 kb
Host smart-758a7922-1ef4-4e65-b5a5-2a253f5cc6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899502243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.899502243
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.547857678
Short name T214
Test name
Test status
Simulation time 115699281 ps
CPU time 1.04 seconds
Started Jul 25 06:55:21 PM PDT 24
Finished Jul 25 06:55:23 PM PDT 24
Peak memory 200144 kb
Host smart-66ee9a3d-b9e0-45b0-b6cd-f3989fb4e0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547857678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.547857678
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3449163840
Short name T393
Test name
Test status
Simulation time 124106259 ps
CPU time 1.18 seconds
Started Jul 25 06:55:20 PM PDT 24
Finished Jul 25 06:55:21 PM PDT 24
Peak memory 200368 kb
Host smart-bf021d28-f8a8-4876-b147-30b4e2a37ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449163840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3449163840
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.273219713
Short name T153
Test name
Test status
Simulation time 2345130200 ps
CPU time 11.93 seconds
Started Jul 25 06:55:20 PM PDT 24
Finished Jul 25 06:55:32 PM PDT 24
Peak memory 200476 kb
Host smart-094a5c25-150d-45a4-bc09-1b9f7627ba73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273219713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.273219713
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4009232510
Short name T462
Test name
Test status
Simulation time 468277107 ps
CPU time 2.5 seconds
Started Jul 25 06:55:22 PM PDT 24
Finished Jul 25 06:55:24 PM PDT 24
Peak memory 200188 kb
Host smart-f5a4fb67-fab3-4aa9-bfcb-7c3c35ffe0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009232510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4009232510
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2468256738
Short name T195
Test name
Test status
Simulation time 165456675 ps
CPU time 1.32 seconds
Started Jul 25 06:55:20 PM PDT 24
Finished Jul 25 06:55:21 PM PDT 24
Peak memory 200304 kb
Host smart-e5db58b0-53de-42e3-9c90-d1ada0a6dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468256738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2468256738
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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