Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8044

1

T2

27

T3

18

T4

23

auto[1]

11123

1

T2

19

T3

29

T4

22

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5921	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6477	1			T1	1		T2	11		T3	19
reset_info_cp[2]	3001	1			T2	8		T3	7		T4	13
reset_info_cp[4]	3865	1			T2	9		T3	11		T4	9
reset_info_cp[8]	109	1			T6	1		T50	3		T27	5
reset_info_cp[16]	98	1			T6	1		T10	2		T50	1
reset_info_cp[32]	109	1			T2	1		T5	1		T50	2
reset_info_cp[64]	106	1			T2	2		T12	1		T50	3
reset_info_cp[128]	101	1			T10	1		T50	1		T26	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3180	1			T2	7		T3	7		T4	5
reset_info_cp[1]	auto[1]	2677	1			T2	3		T3	11		T4	8
reset_info_cp[2]	auto[0]	880	1			T2	3		T3	3		T4	7
reset_info_cp[2]	auto[1]	2121	1			T2	5		T3	4		T4	6
reset_info_cp[4]	auto[0]	1344	1			T2	5		T3	1		T4	6
reset_info_cp[4]	auto[1]	2521	1			T2	4		T3	10		T4	3
reset_info_cp[8]	auto[0]	53	1			T27	3		T138	1		T97	1
reset_info_cp[8]	auto[1]	56	1			T6	1		T50	3		T27	2
reset_info_cp[16]	auto[0]	29	1			T10	2		T139	1		T140	1
reset_info_cp[16]	auto[1]	69	1			T6	1		T50	1		T91	1
reset_info_cp[32]	auto[0]	45	1			T2	1		T50	1		T61	1
reset_info_cp[32]	auto[1]	64	1			T5	1		T50	1		T27	1
reset_info_cp[64]	auto[0]	54	1			T2	2		T50	2		T27	1
reset_info_cp[64]	auto[1]	52	1			T12	1		T50	1		T34	1
reset_info_cp[128]	auto[0]	43	1			T10	1		T93	1		T96	1
reset_info_cp[128]	auto[1]	58	1			T50	1		T26	2		T91	1