Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T546 /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2525631326 Jul 26 07:01:33 PM PDT 24 Jul 26 07:01:35 PM PDT 24 243568549 ps
T547 /workspace/coverage/default/38.rstmgr_alert_test.3465111923 Jul 26 07:02:07 PM PDT 24 Jul 26 07:02:08 PM PDT 24 58488373 ps
T548 /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.329920543 Jul 26 07:01:39 PM PDT 24 Jul 26 07:01:40 PM PDT 24 146566011 ps
T549 /workspace/coverage/default/25.rstmgr_stress_all.289173567 Jul 26 07:01:35 PM PDT 24 Jul 26 07:02:10 PM PDT 24 10920524894 ps
T550 /workspace/coverage/default/5.rstmgr_por_stretcher.4229867175 Jul 26 07:01:17 PM PDT 24 Jul 26 07:01:18 PM PDT 24 209749883 ps
T74 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2911760815 Jul 26 07:00:50 PM PDT 24 Jul 26 07:00:53 PM PDT 24 396916409 ps
T68 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1940238174 Jul 26 07:00:40 PM PDT 24 Jul 26 07:00:41 PM PDT 24 96997296 ps
T75 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2237910436 Jul 26 07:00:51 PM PDT 24 Jul 26 07:00:53 PM PDT 24 272991326 ps
T69 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3142623264 Jul 26 07:00:59 PM PDT 24 Jul 26 07:01:01 PM PDT 24 424620525 ps
T70 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.965114388 Jul 26 07:00:56 PM PDT 24 Jul 26 07:00:57 PM PDT 24 68068133 ps
T76 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2082388267 Jul 26 07:01:06 PM PDT 24 Jul 26 07:01:08 PM PDT 24 259108099 ps
T99 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2281095496 Jul 26 07:00:55 PM PDT 24 Jul 26 07:00:56 PM PDT 24 65157322 ps
T71 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.652055806 Jul 26 07:00:55 PM PDT 24 Jul 26 07:00:56 PM PDT 24 170651318 ps
T72 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2919251551 Jul 26 07:00:55 PM PDT 24 Jul 26 07:00:56 PM PDT 24 115023012 ps
T80 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4286348006 Jul 26 07:00:55 PM PDT 24 Jul 26 07:00:56 PM PDT 24 118521788 ps
T108 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.993793699 Jul 26 07:00:56 PM PDT 24 Jul 26 07:00:57 PM PDT 24 81026674 ps
T100 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1047789742 Jul 26 07:00:57 PM PDT 24 Jul 26 07:00:58 PM PDT 24 81980980 ps
T109 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.990250227 Jul 26 07:00:44 PM PDT 24 Jul 26 07:00:48 PM PDT 24 267789000 ps
T101 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2358643917 Jul 26 07:00:52 PM PDT 24 Jul 26 07:00:53 PM PDT 24 93122832 ps
T85 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.707167241 Jul 26 07:00:44 PM PDT 24 Jul 26 07:00:46 PM PDT 24 128980292 ps
T551 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.283256272 Jul 26 07:00:45 PM PDT 24 Jul 26 07:00:46 PM PDT 24 71570544 ps
T552 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1240870900 Jul 26 07:00:40 PM PDT 24 Jul 26 07:00:40 PM PDT 24 83114392 ps
T102 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3112846725 Jul 26 07:00:50 PM PDT 24 Jul 26 07:00:51 PM PDT 24 81484072 ps
T103 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1132315501 Jul 26 07:00:51 PM PDT 24 Jul 26 07:00:53 PM PDT 24 194452234 ps
T86 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3466775370 Jul 26 07:00:59 PM PDT 24 Jul 26 07:01:00 PM PDT 24 190857112 ps
T87 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.852383154 Jul 26 07:00:46 PM PDT 24 Jul 26 07:00:47 PM PDT 24 167201826 ps
T135 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1267794799 Jul 26 07:00:46 PM PDT 24 Jul 26 07:00:52 PM PDT 24 1163283526 ps
T88 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.930330664 Jul 26 07:01:02 PM PDT 24 Jul 26 07:01:03 PM PDT 24 109824272 ps
T89 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2410567404 Jul 26 07:00:47 PM PDT 24 Jul 26 07:00:49 PM PDT 24 470863626 ps
T104 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1830483313 Jul 26 07:01:06 PM PDT 24 Jul 26 07:01:08 PM PDT 24 217906946 ps
T105 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3403649014 Jul 26 07:00:46 PM PDT 24 Jul 26 07:00:47 PM PDT 24 78945953 ps
T106 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4261055953 Jul 26 07:00:59 PM PDT 24 Jul 26 07:01:00 PM PDT 24 64832978 ps
T90 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2836666017 Jul 26 07:00:57 PM PDT 24 Jul 26 07:01:00 PM PDT 24 399236032 ps
T553 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1873973107 Jul 26 07:00:43 PM PDT 24 Jul 26 07:00:44 PM PDT 24 72742392 ps
T554 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.156454054 Jul 26 07:00:59 PM PDT 24 Jul 26 07:01:00 PM PDT 24 137776570 ps
T107 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2181799951 Jul 26 07:00:57 PM PDT 24 Jul 26 07:00:59 PM PDT 24 517108887 ps
T121 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2588362168 Jul 26 07:00:55 PM PDT 24 Jul 26 07:00:56 PM PDT 24 166330090 ps
T114 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2969809275 Jul 26 07:00:46 PM PDT 24 Jul 26 07:00:49 PM PDT 24 788254973 ps
T555 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2278089412 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:55 PM PDT 24 83913507 ps
T556 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3920016546 Jul 26 07:00:57 PM PDT 24 Jul 26 07:00:59 PM PDT 24 124122768 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3630268552 Jul 26 07:00:48 PM PDT 24 Jul 26 07:00:50 PM PDT 24 428125557 ps
T558 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.300493028 Jul 26 07:00:55 PM PDT 24 Jul 26 07:00:56 PM PDT 24 156982166 ps
T559 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4130002227 Jul 26 07:00:43 PM PDT 24 Jul 26 07:00:45 PM PDT 24 215282637 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2359051781 Jul 26 07:00:46 PM PDT 24 Jul 26 07:00:48 PM PDT 24 156615183 ps
T561 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3832778722 Jul 26 07:00:56 PM PDT 24 Jul 26 07:00:58 PM PDT 24 262950276 ps
T562 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1800370365 Jul 26 07:00:49 PM PDT 24 Jul 26 07:00:51 PM PDT 24 157072277 ps
T563 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1219709178 Jul 26 07:00:47 PM PDT 24 Jul 26 07:00:48 PM PDT 24 74900695 ps
T564 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3142898590 Jul 26 07:00:45 PM PDT 24 Jul 26 07:00:51 PM PDT 24 1188166075 ps
T110 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2537811408 Jul 26 07:00:53 PM PDT 24 Jul 26 07:00:55 PM PDT 24 241411780 ps
T120 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.744199449 Jul 26 07:00:57 PM PDT 24 Jul 26 07:00:59 PM PDT 24 200029988 ps
T565 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2722902860 Jul 26 07:00:49 PM PDT 24 Jul 26 07:00:55 PM PDT 24 482249126 ps
T111 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.583072699 Jul 26 07:00:57 PM PDT 24 Jul 26 07:00:59 PM PDT 24 156077365 ps
T566 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1539477490 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:55 PM PDT 24 69280238 ps
T567 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3986411309 Jul 26 07:00:40 PM PDT 24 Jul 26 07:00:41 PM PDT 24 118981796 ps
T568 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1638667947 Jul 26 07:00:45 PM PDT 24 Jul 26 07:00:46 PM PDT 24 138730287 ps
T117 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3165889530 Jul 26 07:00:46 PM PDT 24 Jul 26 07:00:48 PM PDT 24 476452538 ps
T115 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.7754687 Jul 26 07:00:52 PM PDT 24 Jul 26 07:00:56 PM PDT 24 846247895 ps
T118 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2703365476 Jul 26 07:01:06 PM PDT 24 Jul 26 07:01:08 PM PDT 24 415985492 ps
T112 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2638454503 Jul 26 07:00:57 PM PDT 24 Jul 26 07:01:02 PM PDT 24 711242886 ps
T569 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4026903599 Jul 26 07:00:49 PM PDT 24 Jul 26 07:00:51 PM PDT 24 137113001 ps
T570 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3497022584 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:55 PM PDT 24 127405649 ps
T571 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.193723406 Jul 26 07:00:44 PM PDT 24 Jul 26 07:00:53 PM PDT 24 2012210509 ps
T572 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3036741518 Jul 26 07:00:53 PM PDT 24 Jul 26 07:00:54 PM PDT 24 117782283 ps
T573 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4007914987 Jul 26 07:00:51 PM PDT 24 Jul 26 07:00:54 PM PDT 24 456903612 ps
T574 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.803890870 Jul 26 07:00:59 PM PDT 24 Jul 26 07:01:00 PM PDT 24 106730323 ps
T575 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1852219582 Jul 26 07:01:02 PM PDT 24 Jul 26 07:01:03 PM PDT 24 62857277 ps
T576 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.574066227 Jul 26 07:00:44 PM PDT 24 Jul 26 07:00:45 PM PDT 24 115666343 ps
T130 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3579774214 Jul 26 07:01:02 PM PDT 24 Jul 26 07:01:04 PM PDT 24 419784995 ps
T577 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2804025768 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:55 PM PDT 24 68818381 ps
T131 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3517805090 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:56 PM PDT 24 497245217 ps
T578 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1063773726 Jul 26 07:00:51 PM PDT 24 Jul 26 07:00:52 PM PDT 24 103647583 ps
T579 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.770739317 Jul 26 07:00:46 PM PDT 24 Jul 26 07:00:48 PM PDT 24 127732271 ps
T580 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.823396055 Jul 26 07:00:56 PM PDT 24 Jul 26 07:00:58 PM PDT 24 495538854 ps
T581 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4002320602 Jul 26 07:00:58 PM PDT 24 Jul 26 07:00:59 PM PDT 24 133986108 ps
T582 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1734035517 Jul 26 07:00:48 PM PDT 24 Jul 26 07:00:50 PM PDT 24 247990490 ps
T583 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1089949521 Jul 26 07:00:51 PM PDT 24 Jul 26 07:00:52 PM PDT 24 89706816 ps
T584 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3966854837 Jul 26 07:00:49 PM PDT 24 Jul 26 07:00:50 PM PDT 24 84027949 ps
T116 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3056213553 Jul 26 07:00:58 PM PDT 24 Jul 26 07:01:01 PM PDT 24 883991067 ps
T585 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.313961683 Jul 26 07:01:09 PM PDT 24 Jul 26 07:01:10 PM PDT 24 198244078 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.639515075 Jul 26 07:00:50 PM PDT 24 Jul 26 07:00:51 PM PDT 24 75863860 ps
T587 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1574348015 Jul 26 07:01:01 PM PDT 24 Jul 26 07:01:03 PM PDT 24 422704819 ps
T588 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3374034658 Jul 26 07:00:57 PM PDT 24 Jul 26 07:01:01 PM PDT 24 412234869 ps
T589 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1730091330 Jul 26 07:01:00 PM PDT 24 Jul 26 07:01:02 PM PDT 24 188079443 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1631706913 Jul 26 07:00:44 PM PDT 24 Jul 26 07:00:45 PM PDT 24 107487909 ps
T591 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1546062298 Jul 26 07:00:58 PM PDT 24 Jul 26 07:00:59 PM PDT 24 105496945 ps
T592 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1436038520 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:56 PM PDT 24 105232599 ps
T593 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4011508033 Jul 26 07:00:56 PM PDT 24 Jul 26 07:00:58 PM PDT 24 120108700 ps
T594 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1065702083 Jul 26 07:00:50 PM PDT 24 Jul 26 07:00:51 PM PDT 24 79274667 ps
T595 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1145199252 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:55 PM PDT 24 74404702 ps
T596 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1081703799 Jul 26 07:00:43 PM PDT 24 Jul 26 07:00:46 PM PDT 24 182453499 ps
T597 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4132041686 Jul 26 07:00:57 PM PDT 24 Jul 26 07:00:59 PM PDT 24 178905646 ps
T598 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3941913998 Jul 26 07:00:47 PM PDT 24 Jul 26 07:00:49 PM PDT 24 359863704 ps
T599 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1660846710 Jul 26 07:01:03 PM PDT 24 Jul 26 07:01:04 PM PDT 24 67489219 ps
T133 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1707937396 Jul 26 07:01:01 PM PDT 24 Jul 26 07:01:04 PM PDT 24 916528905 ps
T600 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3870975850 Jul 26 07:01:08 PM PDT 24 Jul 26 07:01:10 PM PDT 24 132947482 ps
T601 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2444086558 Jul 26 07:00:52 PM PDT 24 Jul 26 07:00:53 PM PDT 24 63439075 ps
T602 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.743958968 Jul 26 07:00:45 PM PDT 24 Jul 26 07:00:47 PM PDT 24 114652888 ps
T134 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.702849105 Jul 26 07:01:02 PM PDT 24 Jul 26 07:01:04 PM PDT 24 422163210 ps
T603 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.378180961 Jul 26 07:01:05 PM PDT 24 Jul 26 07:01:06 PM PDT 24 68576515 ps
T604 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.810361464 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:55 PM PDT 24 116916304 ps
T605 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3623047344 Jul 26 07:00:46 PM PDT 24 Jul 26 07:00:49 PM PDT 24 290949731 ps
T606 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1901971652 Jul 26 07:00:53 PM PDT 24 Jul 26 07:00:54 PM PDT 24 58827324 ps
T607 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.844143109 Jul 26 07:00:58 PM PDT 24 Jul 26 07:01:00 PM PDT 24 131659404 ps
T132 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.328538766 Jul 26 07:00:55 PM PDT 24 Jul 26 07:00:57 PM PDT 24 413412204 ps
T608 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2650602058 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:56 PM PDT 24 188869121 ps
T92 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1037692718 Jul 26 07:00:46 PM PDT 24 Jul 26 07:00:48 PM PDT 24 96832733 ps
T609 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2760935980 Jul 26 07:00:43 PM PDT 24 Jul 26 07:00:44 PM PDT 24 83984612 ps
T610 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1192548844 Jul 26 07:01:01 PM PDT 24 Jul 26 07:01:02 PM PDT 24 132813847 ps
T611 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.834389540 Jul 26 07:00:54 PM PDT 24 Jul 26 07:00:58 PM PDT 24 495080951 ps
T612 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2075859459 Jul 26 07:01:09 PM PDT 24 Jul 26 07:01:10 PM PDT 24 73493678 ps
T613 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1260210058 Jul 26 07:00:57 PM PDT 24 Jul 26 07:00:58 PM PDT 24 182231136 ps
T614 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2739564960 Jul 26 07:00:59 PM PDT 24 Jul 26 07:01:03 PM PDT 24 450324724 ps
T615 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3229657845 Jul 26 07:00:48 PM PDT 24 Jul 26 07:00:48 PM PDT 24 77576259 ps
T616 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2835206414 Jul 26 07:00:55 PM PDT 24 Jul 26 07:00:57 PM PDT 24 444367902 ps
T113 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.635633873 Jul 26 07:00:45 PM PDT 24 Jul 26 07:00:48 PM PDT 24 882168321 ps
T119 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1642719592 Jul 26 07:00:52 PM PDT 24 Jul 26 07:00:54 PM PDT 24 433159621 ps
T617 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1231775958 Jul 26 07:00:52 PM PDT 24 Jul 26 07:00:55 PM PDT 24 386651314 ps
T618 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3201131083 Jul 26 07:01:04 PM PDT 24 Jul 26 07:01:05 PM PDT 24 105455940 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3645418661 Jul 26 07:00:47 PM PDT 24 Jul 26 07:00:50 PM PDT 24 936780664 ps
T620 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3879129564 Jul 26 07:00:45 PM PDT 24 Jul 26 07:00:47 PM PDT 24 195530007 ps

Test location /workspace/coverage/default/49.rstmgr_stress_all.2135524057
Short name T5
Test name
Test status
Simulation time 4720193455 ps
CPU time 18.67 seconds
Started Jul 26 07:02:19 PM PDT 24
Finished Jul 26 07:02:38 PM PDT 24
Peak memory 200380 kb
Host smart-ba33bf28-f806-4fa3-b59d-f455962f23d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135524057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2135524057
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.383110237
Short name T8
Test name
Test status
Simulation time 392274899 ps
CPU time 2.56 seconds
Started Jul 26 07:01:58 PM PDT 24
Finished Jul 26 07:02:01 PM PDT 24
Peak memory 200072 kb
Host smart-7a2b9723-d3e5-4004-a5a7-afe392ea0894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383110237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.383110237
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4286348006
Short name T80
Test name
Test status
Simulation time 118521788 ps
CPU time 1.18 seconds
Started Jul 26 07:00:55 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 208116 kb
Host smart-be9a32aa-8ec3-4c89-8da2-77531a849410
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286348006 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.4286348006
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.745116320
Short name T9
Test name
Test status
Simulation time 8291422774 ps
CPU time 13.37 seconds
Started Jul 26 07:01:00 PM PDT 24
Finished Jul 26 07:01:13 PM PDT 24
Peak memory 217616 kb
Host smart-e0b89645-6c73-42af-9e2b-e362915c5c97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745116320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.745116320
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.760043280
Short name T50
Test name
Test status
Simulation time 10746899300 ps
CPU time 36.68 seconds
Started Jul 26 07:01:34 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 200408 kb
Host smart-4e9550a0-0dad-442d-96b6-1e6c516d666a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760043280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.760043280
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.380199123
Short name T34
Test name
Test status
Simulation time 2145430271 ps
CPU time 7.64 seconds
Started Jul 26 07:01:51 PM PDT 24
Finished Jul 26 07:01:59 PM PDT 24
Peak memory 217420 kb
Host smart-68ba9cf7-b396-4df1-8c8c-5d7935cf15ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380199123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.380199123
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2969809275
Short name T114
Test name
Test status
Simulation time 788254973 ps
CPU time 2.97 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:49 PM PDT 24
Peak memory 200020 kb
Host smart-9ca1178e-6dfc-4f9c-aef0-723eba7143e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969809275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2969809275
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2166442294
Short name T96
Test name
Test status
Simulation time 2577380171 ps
CPU time 12.79 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:33 PM PDT 24
Peak memory 200440 kb
Host smart-4ac188f1-46cd-4f1e-afb1-6cfc3a20b910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166442294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2166442294
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1226693221
Short name T164
Test name
Test status
Simulation time 92910136 ps
CPU time 0.98 seconds
Started Jul 26 07:01:02 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 200072 kb
Host smart-b5ca24fe-9f49-4f9d-917b-7ac0554e00da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226693221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1226693221
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.491073647
Short name T146
Test name
Test status
Simulation time 69655171 ps
CPU time 0.82 seconds
Started Jul 26 07:01:03 PM PDT 24
Finished Jul 26 07:01:04 PM PDT 24
Peak memory 199872 kb
Host smart-3bb0557f-5dd7-4ec1-94c1-a176dc1bdf17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491073647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.491073647
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2903235102
Short name T138
Test name
Test status
Simulation time 176990494 ps
CPU time 1.29 seconds
Started Jul 26 07:01:36 PM PDT 24
Finished Jul 26 07:01:38 PM PDT 24
Peak memory 200296 kb
Host smart-bd13b130-1ecc-44fd-aec4-05a98d117e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903235102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2903235102
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.309399597
Short name T33
Test name
Test status
Simulation time 1221008330 ps
CPU time 5.66 seconds
Started Jul 26 07:01:43 PM PDT 24
Finished Jul 26 07:01:49 PM PDT 24
Peak memory 216672 kb
Host smart-9be7ec66-6dfd-4e71-b451-bbc681d91f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309399597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.309399597
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2537811408
Short name T110
Test name
Test status
Simulation time 241411780 ps
CPU time 1.92 seconds
Started Jul 26 07:00:53 PM PDT 24
Finished Jul 26 07:00:55 PM PDT 24
Peak memory 199944 kb
Host smart-3b493958-a4c5-4d3a-bb44-1e2ad93110fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537811408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2537811408
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2358643917
Short name T101
Test name
Test status
Simulation time 93122832 ps
CPU time 1.07 seconds
Started Jul 26 07:00:52 PM PDT 24
Finished Jul 26 07:00:53 PM PDT 24
Peak memory 199828 kb
Host smart-d959c4ad-8339-4abd-89f0-9f1e156f29b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358643917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2358643917
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1642719592
Short name T119
Test name
Test status
Simulation time 433159621 ps
CPU time 1.65 seconds
Started Jul 26 07:00:52 PM PDT 24
Finished Jul 26 07:00:54 PM PDT 24
Peak memory 199976 kb
Host smart-95b139e4-e996-47a3-a84f-16f37687aa3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642719592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1642719592
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3517805090
Short name T131
Test name
Test status
Simulation time 497245217 ps
CPU time 1.88 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 208216 kb
Host smart-ec3aec7a-e159-4913-aa50-ac764c121bac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517805090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3517805090
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2069473255
Short name T6
Test name
Test status
Simulation time 1224624932 ps
CPU time 5.52 seconds
Started Jul 26 07:01:36 PM PDT 24
Finished Jul 26 07:01:41 PM PDT 24
Peak memory 217372 kb
Host smart-00413247-a9e1-4114-ab8b-d4d008fe05a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069473255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2069473255
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3418382967
Short name T10
Test name
Test status
Simulation time 271455177 ps
CPU time 1.47 seconds
Started Jul 26 07:01:00 PM PDT 24
Finished Jul 26 07:01:02 PM PDT 24
Peak memory 200136 kb
Host smart-6158fae9-3874-414d-bec5-9bc56585ff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418382967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3418382967
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2911760815
Short name T74
Test name
Test status
Simulation time 396916409 ps
CPU time 2.88 seconds
Started Jul 26 07:00:50 PM PDT 24
Finished Jul 26 07:00:53 PM PDT 24
Peak memory 208192 kb
Host smart-d1c0becd-55fa-4489-bc11-f4980a5290b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911760815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2911760815
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3193125894
Short name T16
Test name
Test status
Simulation time 183320431 ps
CPU time 0.86 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:21 PM PDT 24
Peak memory 199892 kb
Host smart-eb786ae6-a010-4b7b-97d5-0a44c4a7570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193125894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3193125894
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3056213553
Short name T116
Test name
Test status
Simulation time 883991067 ps
CPU time 3.09 seconds
Started Jul 26 07:00:58 PM PDT 24
Finished Jul 26 07:01:01 PM PDT 24
Peak memory 200108 kb
Host smart-5625b341-d1dc-4f56-86b0-3fe71f1cde58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056213553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3056213553
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.635633873
Short name T113
Test name
Test status
Simulation time 882168321 ps
CPU time 3.07 seconds
Started Jul 26 07:00:45 PM PDT 24
Finished Jul 26 07:00:48 PM PDT 24
Peak memory 199968 kb
Host smart-eb3bce71-d65e-4079-aa08-ca1e4c913d01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635633873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
635633873
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1037692718
Short name T92
Test name
Test status
Simulation time 96832733 ps
CPU time 1.31 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:48 PM PDT 24
Peak memory 199948 kb
Host smart-2fc55fe3-5a0c-4182-b055-66c3b6a68a50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037692718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
037692718
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3142898590
Short name T564
Test name
Test status
Simulation time 1188166075 ps
CPU time 5.32 seconds
Started Jul 26 07:00:45 PM PDT 24
Finished Jul 26 07:00:51 PM PDT 24
Peak memory 199940 kb
Host smart-ab7c9953-8de4-4e74-88ba-86b672890259
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142898590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
142898590
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1940238174
Short name T68
Test name
Test status
Simulation time 96997296 ps
CPU time 0.8 seconds
Started Jul 26 07:00:40 PM PDT 24
Finished Jul 26 07:00:41 PM PDT 24
Peak memory 199760 kb
Host smart-2c22ae5f-4996-461a-8981-0badb7a2feb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940238174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
940238174
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1081703799
Short name T596
Test name
Test status
Simulation time 182453499 ps
CPU time 1.84 seconds
Started Jul 26 07:00:43 PM PDT 24
Finished Jul 26 07:00:46 PM PDT 24
Peak memory 208228 kb
Host smart-5ce83f18-7f34-4fd4-8268-762b561ab6ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081703799 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1081703799
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2760935980
Short name T609
Test name
Test status
Simulation time 83984612 ps
CPU time 0.85 seconds
Started Jul 26 07:00:43 PM PDT 24
Finished Jul 26 07:00:44 PM PDT 24
Peak memory 199780 kb
Host smart-436749b7-63b6-4414-af80-3faf6bd33efb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760935980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2760935980
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4026903599
Short name T569
Test name
Test status
Simulation time 137113001 ps
CPU time 1.16 seconds
Started Jul 26 07:00:49 PM PDT 24
Finished Jul 26 07:00:51 PM PDT 24
Peak memory 199828 kb
Host smart-b7f73b96-97b5-4ed5-b6b8-48efa7afc688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026903599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.4026903599
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2359051781
Short name T560
Test name
Test status
Simulation time 156615183 ps
CPU time 1.97 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:48 PM PDT 24
Peak memory 199988 kb
Host smart-4d9eb1d6-e7a7-4f9e-94a8-87488933cbe2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359051781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
359051781
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2722902860
Short name T565
Test name
Test status
Simulation time 482249126 ps
CPU time 5.69 seconds
Started Jul 26 07:00:49 PM PDT 24
Finished Jul 26 07:00:55 PM PDT 24
Peak memory 199916 kb
Host smart-bf320ce2-21b2-4a58-9555-47c24007cce8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722902860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
722902860
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1240870900
Short name T552
Test name
Test status
Simulation time 83114392 ps
CPU time 0.77 seconds
Started Jul 26 07:00:40 PM PDT 24
Finished Jul 26 07:00:40 PM PDT 24
Peak memory 199828 kb
Host smart-12ef8bb0-c7fd-418e-8906-6c70df9c939f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240870900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
240870900
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.852383154
Short name T87
Test name
Test status
Simulation time 167201826 ps
CPU time 1.52 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:47 PM PDT 24
Peak memory 208320 kb
Host smart-d0dfb2b7-e220-4af3-b862-65f66db323ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852383154 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.852383154
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1873973107
Short name T553
Test name
Test status
Simulation time 72742392 ps
CPU time 0.77 seconds
Started Jul 26 07:00:43 PM PDT 24
Finished Jul 26 07:00:44 PM PDT 24
Peak memory 199780 kb
Host smart-c1fd453f-105c-445f-8dfa-94199f8ce2f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873973107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1873973107
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1063773726
Short name T578
Test name
Test status
Simulation time 103647583 ps
CPU time 1.21 seconds
Started Jul 26 07:00:51 PM PDT 24
Finished Jul 26 07:00:52 PM PDT 24
Peak memory 200060 kb
Host smart-cb1818b4-cfa7-4fca-9afa-0c48f355685f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063773726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1063773726
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3941913998
Short name T598
Test name
Test status
Simulation time 359863704 ps
CPU time 2.29 seconds
Started Jul 26 07:00:47 PM PDT 24
Finished Jul 26 07:00:49 PM PDT 24
Peak memory 208124 kb
Host smart-300c071e-d1c6-4848-aa1e-9bdb614510c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941913998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3941913998
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3645418661
Short name T619
Test name
Test status
Simulation time 936780664 ps
CPU time 3.11 seconds
Started Jul 26 07:00:47 PM PDT 24
Finished Jul 26 07:00:50 PM PDT 24
Peak memory 200016 kb
Host smart-9016d806-7964-4479-a282-bff755768034
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645418661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3645418661
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.993793699
Short name T108
Test name
Test status
Simulation time 81026674 ps
CPU time 0.84 seconds
Started Jul 26 07:00:56 PM PDT 24
Finished Jul 26 07:00:57 PM PDT 24
Peak memory 199780 kb
Host smart-a9846fd5-616b-4352-a50a-fcfe7ec325c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993793699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.993793699
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.300493028
Short name T558
Test name
Test status
Simulation time 156982166 ps
CPU time 1.21 seconds
Started Jul 26 07:00:55 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 199888 kb
Host smart-334e1b76-8a14-459e-ac59-7a2f46805960
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300493028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.300493028
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.834389540
Short name T611
Test name
Test status
Simulation time 495080951 ps
CPU time 3.39 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:58 PM PDT 24
Peak memory 208176 kb
Host smart-8adff680-df95-42f0-835e-7dd211991d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834389540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.834389540
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.702849105
Short name T134
Test name
Test status
Simulation time 422163210 ps
CPU time 1.91 seconds
Started Jul 26 07:01:02 PM PDT 24
Finished Jul 26 07:01:04 PM PDT 24
Peak memory 200020 kb
Host smart-440b889b-2018-4a67-bff4-f638896f9c69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702849105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.702849105
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4132041686
Short name T597
Test name
Test status
Simulation time 178905646 ps
CPU time 1.69 seconds
Started Jul 26 07:00:57 PM PDT 24
Finished Jul 26 07:00:59 PM PDT 24
Peak memory 208056 kb
Host smart-bb13e7b2-0da9-46c0-b3bf-096f58d53d47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132041686 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.4132041686
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1539477490
Short name T566
Test name
Test status
Simulation time 69280238 ps
CPU time 0.82 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:55 PM PDT 24
Peak memory 199772 kb
Host smart-26e82f3a-fec9-47f9-b12c-b7f7fd723d02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539477490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1539477490
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1260210058
Short name T613
Test name
Test status
Simulation time 182231136 ps
CPU time 1.26 seconds
Started Jul 26 07:00:57 PM PDT 24
Finished Jul 26 07:00:58 PM PDT 24
Peak memory 199804 kb
Host smart-d0d911d2-dd76-408a-822f-1f792b1d3b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260210058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1260210058
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2836666017
Short name T90
Test name
Test status
Simulation time 399236032 ps
CPU time 2.65 seconds
Started Jul 26 07:00:57 PM PDT 24
Finished Jul 26 07:01:00 PM PDT 24
Peak memory 208112 kb
Host smart-2ee42eb7-b035-4ffd-b7e8-b89c56c05138
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836666017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2836666017
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3579774214
Short name T130
Test name
Test status
Simulation time 419784995 ps
CPU time 1.89 seconds
Started Jul 26 07:01:02 PM PDT 24
Finished Jul 26 07:01:04 PM PDT 24
Peak memory 200016 kb
Host smart-43ba4e8f-cbe4-46a1-972f-7507f147199e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579774214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3579774214
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2919251551
Short name T72
Test name
Test status
Simulation time 115023012 ps
CPU time 1.22 seconds
Started Jul 26 07:00:55 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 208108 kb
Host smart-63be11b1-59ab-49e1-a59b-ed325164a8ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919251551 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2919251551
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1901971652
Short name T606
Test name
Test status
Simulation time 58827324 ps
CPU time 0.81 seconds
Started Jul 26 07:00:53 PM PDT 24
Finished Jul 26 07:00:54 PM PDT 24
Peak memory 199804 kb
Host smart-f51fe866-c410-4c26-b551-c3f5e80a3e6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901971652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1901971652
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.652055806
Short name T71
Test name
Test status
Simulation time 170651318 ps
CPU time 1.23 seconds
Started Jul 26 07:00:55 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 199856 kb
Host smart-a42e0b75-3cc0-40fd-848b-1ea5647c4760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652055806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.652055806
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.823396055
Short name T580
Test name
Test status
Simulation time 495538854 ps
CPU time 1.87 seconds
Started Jul 26 07:00:56 PM PDT 24
Finished Jul 26 07:00:58 PM PDT 24
Peak memory 200048 kb
Host smart-6cbb2ea8-32c3-4b23-b75a-c4f9c992527c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823396055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.823396055
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3201131083
Short name T618
Test name
Test status
Simulation time 105455940 ps
CPU time 0.98 seconds
Started Jul 26 07:01:04 PM PDT 24
Finished Jul 26 07:01:05 PM PDT 24
Peak memory 199832 kb
Host smart-a3eb77b5-95a1-4130-9793-b7924f840c39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201131083 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3201131083
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.378180961
Short name T603
Test name
Test status
Simulation time 68576515 ps
CPU time 0.82 seconds
Started Jul 26 07:01:05 PM PDT 24
Finished Jul 26 07:01:06 PM PDT 24
Peak memory 199808 kb
Host smart-0d593a96-d59e-42fb-b20c-700b5ee5ca51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378180961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.378180961
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1546062298
Short name T591
Test name
Test status
Simulation time 105496945 ps
CPU time 1.18 seconds
Started Jul 26 07:00:58 PM PDT 24
Finished Jul 26 07:00:59 PM PDT 24
Peak memory 200024 kb
Host smart-b85b3385-d1e2-41ee-9ca7-33ec00cc6129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546062298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1546062298
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2638454503
Short name T112
Test name
Test status
Simulation time 711242886 ps
CPU time 4.54 seconds
Started Jul 26 07:00:57 PM PDT 24
Finished Jul 26 07:01:02 PM PDT 24
Peak memory 208096 kb
Host smart-146785a6-e194-4e13-b11e-199ffa27aa28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638454503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2638454503
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2650602058
Short name T608
Test name
Test status
Simulation time 188869121 ps
CPU time 1.87 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 208224 kb
Host smart-c39eb438-65aa-480c-bf23-aa075057149d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650602058 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2650602058
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2075859459
Short name T612
Test name
Test status
Simulation time 73493678 ps
CPU time 0.77 seconds
Started Jul 26 07:01:09 PM PDT 24
Finished Jul 26 07:01:10 PM PDT 24
Peak memory 199708 kb
Host smart-980405f5-a83f-4e46-af57-99847f54f573
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075859459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2075859459
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1192548844
Short name T610
Test name
Test status
Simulation time 132813847 ps
CPU time 1.08 seconds
Started Jul 26 07:01:01 PM PDT 24
Finished Jul 26 07:01:02 PM PDT 24
Peak memory 199748 kb
Host smart-932b8c6a-1744-48d7-8f03-9a799555e774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192548844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1192548844
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3870975850
Short name T600
Test name
Test status
Simulation time 132947482 ps
CPU time 1.68 seconds
Started Jul 26 07:01:08 PM PDT 24
Finished Jul 26 07:01:10 PM PDT 24
Peak memory 216308 kb
Host smart-cc665a5b-7282-4047-9919-bca0004f67d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870975850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3870975850
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2703365476
Short name T118
Test name
Test status
Simulation time 415985492 ps
CPU time 1.74 seconds
Started Jul 26 07:01:06 PM PDT 24
Finished Jul 26 07:01:08 PM PDT 24
Peak memory 200008 kb
Host smart-1bc9911d-983d-4d89-95a0-a082e234c496
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703365476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2703365476
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3466775370
Short name T86
Test name
Test status
Simulation time 190857112 ps
CPU time 1.24 seconds
Started Jul 26 07:00:59 PM PDT 24
Finished Jul 26 07:01:00 PM PDT 24
Peak memory 199916 kb
Host smart-b51d76c6-1e21-4c39-b997-c02207f3d915
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466775370 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3466775370
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2804025768
Short name T577
Test name
Test status
Simulation time 68818381 ps
CPU time 0.8 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:55 PM PDT 24
Peak memory 199740 kb
Host smart-b97ab07d-179b-46c0-82b6-d627c9bedf6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804025768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2804025768
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1231775958
Short name T617
Test name
Test status
Simulation time 386651314 ps
CPU time 2.65 seconds
Started Jul 26 07:00:52 PM PDT 24
Finished Jul 26 07:00:55 PM PDT 24
Peak memory 208124 kb
Host smart-5d712efb-a9b5-4ecd-846b-5ea772bf0ced
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231775958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1231775958
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.744199449
Short name T120
Test name
Test status
Simulation time 200029988 ps
CPU time 1.41 seconds
Started Jul 26 07:00:57 PM PDT 24
Finished Jul 26 07:00:59 PM PDT 24
Peak memory 208084 kb
Host smart-9f586926-09d7-4ef9-b58c-bc2e8bbf0ba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744199449 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.744199449
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2444086558
Short name T601
Test name
Test status
Simulation time 63439075 ps
CPU time 0.76 seconds
Started Jul 26 07:00:52 PM PDT 24
Finished Jul 26 07:00:53 PM PDT 24
Peak memory 199716 kb
Host smart-96e1fb53-6dfa-4017-a63c-66e3874be489
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444086558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2444086558
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1145199252
Short name T595
Test name
Test status
Simulation time 74404702 ps
CPU time 1.05 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:55 PM PDT 24
Peak memory 199860 kb
Host smart-62cf909c-3a73-480d-a28e-96ccc0da9c33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145199252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1145199252
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2739564960
Short name T614
Test name
Test status
Simulation time 450324724 ps
CPU time 3.48 seconds
Started Jul 26 07:00:59 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 208112 kb
Host smart-4930e7b2-c9d2-4d04-b79c-599b1a5af6cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739564960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2739564960
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2835206414
Short name T616
Test name
Test status
Simulation time 444367902 ps
CPU time 1.81 seconds
Started Jul 26 07:00:55 PM PDT 24
Finished Jul 26 07:00:57 PM PDT 24
Peak memory 200004 kb
Host smart-316acf9b-e37d-4fd2-b415-e2a2adaf0e54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835206414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2835206414
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.810361464
Short name T604
Test name
Test status
Simulation time 116916304 ps
CPU time 1.11 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:55 PM PDT 24
Peak memory 208108 kb
Host smart-8419f2c8-95c4-431f-83e5-60076d093349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810361464 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.810361464
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1660846710
Short name T599
Test name
Test status
Simulation time 67489219 ps
CPU time 0.76 seconds
Started Jul 26 07:01:03 PM PDT 24
Finished Jul 26 07:01:04 PM PDT 24
Peak memory 199800 kb
Host smart-54d951ae-971c-44be-98a2-7aa7fe636802
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660846710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1660846710
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1047789742
Short name T100
Test name
Test status
Simulation time 81980980 ps
CPU time 0.98 seconds
Started Jul 26 07:00:57 PM PDT 24
Finished Jul 26 07:00:58 PM PDT 24
Peak memory 199824 kb
Host smart-f05150af-ee19-4676-b316-1b1810e80657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047789742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1047789742
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2082388267
Short name T76
Test name
Test status
Simulation time 259108099 ps
CPU time 2.05 seconds
Started Jul 26 07:01:06 PM PDT 24
Finished Jul 26 07:01:08 PM PDT 24
Peak memory 208140 kb
Host smart-950a0270-95af-4960-b324-6dd3e6ee6bbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082388267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2082388267
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1574348015
Short name T587
Test name
Test status
Simulation time 422704819 ps
CPU time 1.75 seconds
Started Jul 26 07:01:01 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 199964 kb
Host smart-b11c38b7-04d4-4cdc-964d-1e7343029e29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574348015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1574348015
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.313961683
Short name T585
Test name
Test status
Simulation time 198244078 ps
CPU time 1.24 seconds
Started Jul 26 07:01:09 PM PDT 24
Finished Jul 26 07:01:10 PM PDT 24
Peak memory 208104 kb
Host smart-fc4c3f1b-35af-4212-89f7-a66da47c894f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313961683 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.313961683
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4261055953
Short name T106
Test name
Test status
Simulation time 64832978 ps
CPU time 0.81 seconds
Started Jul 26 07:00:59 PM PDT 24
Finished Jul 26 07:01:00 PM PDT 24
Peak memory 199796 kb
Host smart-d3a5bfd5-0592-47f4-b307-2aabcd2a183f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261055953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4261055953
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1830483313
Short name T104
Test name
Test status
Simulation time 217906946 ps
CPU time 1.47 seconds
Started Jul 26 07:01:06 PM PDT 24
Finished Jul 26 07:01:08 PM PDT 24
Peak memory 199992 kb
Host smart-72020bc9-1e04-48b2-bf38-966eea26adf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830483313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1830483313
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3374034658
Short name T588
Test name
Test status
Simulation time 412234869 ps
CPU time 2.98 seconds
Started Jul 26 07:00:57 PM PDT 24
Finished Jul 26 07:01:01 PM PDT 24
Peak memory 208192 kb
Host smart-9dbf5ef9-cba2-4947-aff0-e1da60728b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374034658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3374034658
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2181799951
Short name T107
Test name
Test status
Simulation time 517108887 ps
CPU time 1.91 seconds
Started Jul 26 07:00:57 PM PDT 24
Finished Jul 26 07:00:59 PM PDT 24
Peak memory 199816 kb
Host smart-dc8ec87e-176f-4e6b-8db0-8e1d42d75af2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181799951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2181799951
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3036741518
Short name T572
Test name
Test status
Simulation time 117782283 ps
CPU time 0.97 seconds
Started Jul 26 07:00:53 PM PDT 24
Finished Jul 26 07:00:54 PM PDT 24
Peak memory 199908 kb
Host smart-6322dabe-455d-4930-aff7-caeaf5912358
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036741518 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3036741518
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1852219582
Short name T575
Test name
Test status
Simulation time 62857277 ps
CPU time 0.77 seconds
Started Jul 26 07:01:02 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 199844 kb
Host smart-46250a3c-adca-4b37-869c-a9c532b65b15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852219582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1852219582
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3832778722
Short name T561
Test name
Test status
Simulation time 262950276 ps
CPU time 1.48 seconds
Started Jul 26 07:00:56 PM PDT 24
Finished Jul 26 07:00:58 PM PDT 24
Peak memory 208216 kb
Host smart-cd96c82e-1779-4e10-9ff1-0bd3968d3f09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832778722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3832778722
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.583072699
Short name T111
Test name
Test status
Simulation time 156077365 ps
CPU time 2.21 seconds
Started Jul 26 07:00:57 PM PDT 24
Finished Jul 26 07:00:59 PM PDT 24
Peak memory 208120 kb
Host smart-f96e4070-40ed-4875-bff9-52775b346750
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583072699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.583072699
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4130002227
Short name T559
Test name
Test status
Simulation time 215282637 ps
CPU time 1.46 seconds
Started Jul 26 07:00:43 PM PDT 24
Finished Jul 26 07:00:45 PM PDT 24
Peak memory 199940 kb
Host smart-5488a4f5-402d-4ad8-a7c0-672f483b4b71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130002227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.4
130002227
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.193723406
Short name T571
Test name
Test status
Simulation time 2012210509 ps
CPU time 9.45 seconds
Started Jul 26 07:00:44 PM PDT 24
Finished Jul 26 07:00:53 PM PDT 24
Peak memory 199956 kb
Host smart-8e45e214-ee60-4f18-8e91-602d27c72f34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193723406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.193723406
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3986411309
Short name T567
Test name
Test status
Simulation time 118981796 ps
CPU time 0.91 seconds
Started Jul 26 07:00:40 PM PDT 24
Finished Jul 26 07:00:41 PM PDT 24
Peak memory 199828 kb
Host smart-572c2a2a-c24b-4d99-a307-247a5e52b658
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986411309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
986411309
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1638667947
Short name T568
Test name
Test status
Simulation time 138730287 ps
CPU time 1.05 seconds
Started Jul 26 07:00:45 PM PDT 24
Finished Jul 26 07:00:46 PM PDT 24
Peak memory 208120 kb
Host smart-c97c0ac9-db83-4a67-9b89-6d2496292c44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638667947 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1638667947
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1065702083
Short name T594
Test name
Test status
Simulation time 79274667 ps
CPU time 0.8 seconds
Started Jul 26 07:00:50 PM PDT 24
Finished Jul 26 07:00:51 PM PDT 24
Peak memory 199860 kb
Host smart-e4b13e8c-30f6-4145-8eac-77a4805c6afe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065702083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1065702083
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1219709178
Short name T563
Test name
Test status
Simulation time 74900695 ps
CPU time 0.93 seconds
Started Jul 26 07:00:47 PM PDT 24
Finished Jul 26 07:00:48 PM PDT 24
Peak memory 199856 kb
Host smart-f02db1e2-8ec5-498f-b724-65efa36808f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219709178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1219709178
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.770739317
Short name T579
Test name
Test status
Simulation time 127732271 ps
CPU time 1.71 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:48 PM PDT 24
Peak memory 199912 kb
Host smart-fc31f330-475f-484b-9908-09c5306a3fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770739317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.770739317
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2410567404
Short name T89
Test name
Test status
Simulation time 470863626 ps
CPU time 2 seconds
Started Jul 26 07:00:47 PM PDT 24
Finished Jul 26 07:00:49 PM PDT 24
Peak memory 200076 kb
Host smart-ec5f7017-ea33-4a52-92c3-35f3000a2550
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410567404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2410567404
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4007914987
Short name T573
Test name
Test status
Simulation time 456903612 ps
CPU time 2.7 seconds
Started Jul 26 07:00:51 PM PDT 24
Finished Jul 26 07:00:54 PM PDT 24
Peak memory 199912 kb
Host smart-633d25b8-a51d-4768-856b-7b1f8363bf38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007914987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
007914987
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1267794799
Short name T135
Test name
Test status
Simulation time 1163283526 ps
CPU time 6.09 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:52 PM PDT 24
Peak memory 199980 kb
Host smart-b26897e9-7ff9-4da0-8151-e556132c0f91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267794799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
267794799
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3966854837
Short name T584
Test name
Test status
Simulation time 84027949 ps
CPU time 0.8 seconds
Started Jul 26 07:00:49 PM PDT 24
Finished Jul 26 07:00:50 PM PDT 24
Peak memory 199732 kb
Host smart-648ab006-cfb1-4608-b9d8-21cbd61b6aa1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966854837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
966854837
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.707167241
Short name T85
Test name
Test status
Simulation time 128980292 ps
CPU time 1.39 seconds
Started Jul 26 07:00:44 PM PDT 24
Finished Jul 26 07:00:46 PM PDT 24
Peak memory 208316 kb
Host smart-e0e3b3b8-b759-434c-8c05-b930f940420e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707167241 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.707167241
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.639515075
Short name T586
Test name
Test status
Simulation time 75863860 ps
CPU time 0.78 seconds
Started Jul 26 07:00:50 PM PDT 24
Finished Jul 26 07:00:51 PM PDT 24
Peak memory 199816 kb
Host smart-6e79ed16-a3a4-41e4-8cc9-d09774e65cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639515075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.639515075
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3403649014
Short name T105
Test name
Test status
Simulation time 78945953 ps
CPU time 0.91 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:47 PM PDT 24
Peak memory 199880 kb
Host smart-45d6771b-4dbd-4810-a5d2-373def997c05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403649014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3403649014
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2237910436
Short name T75
Test name
Test status
Simulation time 272991326 ps
CPU time 1.96 seconds
Started Jul 26 07:00:51 PM PDT 24
Finished Jul 26 07:00:53 PM PDT 24
Peak memory 208116 kb
Host smart-8e19bf22-5d25-4eec-9312-e6f44cedc7dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237910436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2237910436
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3630268552
Short name T557
Test name
Test status
Simulation time 428125557 ps
CPU time 1.88 seconds
Started Jul 26 07:00:48 PM PDT 24
Finished Jul 26 07:00:50 PM PDT 24
Peak memory 200020 kb
Host smart-e9e65ad7-6e2e-4b08-9ec0-30b71f353489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630268552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3630268552
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1800370365
Short name T562
Test name
Test status
Simulation time 157072277 ps
CPU time 1.95 seconds
Started Jul 26 07:00:49 PM PDT 24
Finished Jul 26 07:00:51 PM PDT 24
Peak memory 208180 kb
Host smart-2964723f-2deb-4627-85c4-a80c7cb16822
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800370365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
800370365
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.990250227
Short name T109
Test name
Test status
Simulation time 267789000 ps
CPU time 3.32 seconds
Started Jul 26 07:00:44 PM PDT 24
Finished Jul 26 07:00:48 PM PDT 24
Peak memory 199916 kb
Host smart-b5adfc7f-bae3-4199-ae11-2bf78cc9d624
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990250227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.990250227
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1089949521
Short name T583
Test name
Test status
Simulation time 89706816 ps
CPU time 0.85 seconds
Started Jul 26 07:00:51 PM PDT 24
Finished Jul 26 07:00:52 PM PDT 24
Peak memory 199852 kb
Host smart-9b360e22-f563-43df-9486-1c9d8dbd2250
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089949521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
089949521
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2588362168
Short name T121
Test name
Test status
Simulation time 166330090 ps
CPU time 1.51 seconds
Started Jul 26 07:00:55 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 208240 kb
Host smart-d8c0b088-fbec-4ca6-b11a-7e3ce47bf2a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588362168 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2588362168
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.283256272
Short name T551
Test name
Test status
Simulation time 71570544 ps
CPU time 0.8 seconds
Started Jul 26 07:00:45 PM PDT 24
Finished Jul 26 07:00:46 PM PDT 24
Peak memory 199796 kb
Host smart-a87ad550-8521-42a2-9b67-e9385f6eb117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283256272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.283256272
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1734035517
Short name T582
Test name
Test status
Simulation time 247990490 ps
CPU time 1.62 seconds
Started Jul 26 07:00:48 PM PDT 24
Finished Jul 26 07:00:50 PM PDT 24
Peak memory 199980 kb
Host smart-0dd09435-1afd-430c-aba5-195fa5889dc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734035517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1734035517
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1631706913
Short name T590
Test name
Test status
Simulation time 107487909 ps
CPU time 1.52 seconds
Started Jul 26 07:00:44 PM PDT 24
Finished Jul 26 07:00:45 PM PDT 24
Peak memory 208112 kb
Host smart-9df6182c-df0f-4be2-89ea-6e5213b0c173
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631706913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1631706913
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.156454054
Short name T554
Test name
Test status
Simulation time 137776570 ps
CPU time 1.45 seconds
Started Jul 26 07:00:59 PM PDT 24
Finished Jul 26 07:01:00 PM PDT 24
Peak memory 208268 kb
Host smart-9e1d7d60-4ba1-40df-8e32-0535f6e4f102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156454054 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.156454054
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3112846725
Short name T102
Test name
Test status
Simulation time 81484072 ps
CPU time 0.86 seconds
Started Jul 26 07:00:50 PM PDT 24
Finished Jul 26 07:00:51 PM PDT 24
Peak memory 199808 kb
Host smart-27d5db9b-5eac-436a-9562-059a70aed343
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112846725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3112846725
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3879129564
Short name T620
Test name
Test status
Simulation time 195530007 ps
CPU time 1.36 seconds
Started Jul 26 07:00:45 PM PDT 24
Finished Jul 26 07:00:47 PM PDT 24
Peak memory 200000 kb
Host smart-d795c588-0602-4629-9ce4-d1d928735b79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879129564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3879129564
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.743958968
Short name T602
Test name
Test status
Simulation time 114652888 ps
CPU time 1.6 seconds
Started Jul 26 07:00:45 PM PDT 24
Finished Jul 26 07:00:47 PM PDT 24
Peak memory 216268 kb
Host smart-5144a211-a205-44d6-9d6b-7e9931aaa08d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743958968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.743958968
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3165889530
Short name T117
Test name
Test status
Simulation time 476452538 ps
CPU time 1.85 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:48 PM PDT 24
Peak memory 200020 kb
Host smart-8068a457-adb0-4f2c-bbd1-b4d093664f10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165889530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3165889530
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1730091330
Short name T589
Test name
Test status
Simulation time 188079443 ps
CPU time 1.36 seconds
Started Jul 26 07:01:00 PM PDT 24
Finished Jul 26 07:01:02 PM PDT 24
Peak memory 208108 kb
Host smart-2710ba53-e752-4e09-b198-be18b912f5eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730091330 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1730091330
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3229657845
Short name T615
Test name
Test status
Simulation time 77576259 ps
CPU time 0.83 seconds
Started Jul 26 07:00:48 PM PDT 24
Finished Jul 26 07:00:48 PM PDT 24
Peak memory 199744 kb
Host smart-a642e4c4-0947-42c4-856d-3f89eca9bae7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229657845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3229657845
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.574066227
Short name T576
Test name
Test status
Simulation time 115666343 ps
CPU time 1.14 seconds
Started Jul 26 07:00:44 PM PDT 24
Finished Jul 26 07:00:45 PM PDT 24
Peak memory 200132 kb
Host smart-8b355f70-6b52-4df0-901f-a68b140ea922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574066227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.574066227
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3623047344
Short name T605
Test name
Test status
Simulation time 290949731 ps
CPU time 2.25 seconds
Started Jul 26 07:00:46 PM PDT 24
Finished Jul 26 07:00:49 PM PDT 24
Peak memory 208208 kb
Host smart-7d68d7db-1514-4bd7-acbe-08a1a91fa0b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623047344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3623047344
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.7754687
Short name T115
Test name
Test status
Simulation time 846247895 ps
CPU time 2.9 seconds
Started Jul 26 07:00:52 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 200132 kb
Host smart-5e1558d5-713b-4d98-b0fc-537df5add542
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7754687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.7754687
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3920016546
Short name T556
Test name
Test status
Simulation time 124122768 ps
CPU time 1.38 seconds
Started Jul 26 07:00:57 PM PDT 24
Finished Jul 26 07:00:59 PM PDT 24
Peak memory 208344 kb
Host smart-eefaed59-2986-4098-ad4b-67f720b4c869
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920016546 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3920016546
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.965114388
Short name T70
Test name
Test status
Simulation time 68068133 ps
CPU time 0.78 seconds
Started Jul 26 07:00:56 PM PDT 24
Finished Jul 26 07:00:57 PM PDT 24
Peak memory 199788 kb
Host smart-b39dc1fc-9d2c-4adc-9a32-de500b694dfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965114388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.965114388
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1132315501
Short name T103
Test name
Test status
Simulation time 194452234 ps
CPU time 1.51 seconds
Started Jul 26 07:00:51 PM PDT 24
Finished Jul 26 07:00:53 PM PDT 24
Peak memory 199992 kb
Host smart-8fad09aa-9eb9-4081-98a3-1a386651c1bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132315501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1132315501
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1436038520
Short name T592
Test name
Test status
Simulation time 105232599 ps
CPU time 1.48 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 208184 kb
Host smart-4d8abc6d-de5f-4de6-a170-488a30e079dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436038520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1436038520
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3142623264
Short name T69
Test name
Test status
Simulation time 424620525 ps
CPU time 1.79 seconds
Started Jul 26 07:00:59 PM PDT 24
Finished Jul 26 07:01:01 PM PDT 24
Peak memory 200104 kb
Host smart-78c8ebfa-6413-4050-b347-b00311661818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142623264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3142623264
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3497022584
Short name T570
Test name
Test status
Simulation time 127405649 ps
CPU time 0.98 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:55 PM PDT 24
Peak memory 199900 kb
Host smart-06fa7d7a-5327-4c78-ad52-1c2f847a34b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497022584 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3497022584
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2278089412
Short name T555
Test name
Test status
Simulation time 83913507 ps
CPU time 0.86 seconds
Started Jul 26 07:00:54 PM PDT 24
Finished Jul 26 07:00:55 PM PDT 24
Peak memory 199828 kb
Host smart-38a38fae-cc3e-4143-a777-ede18ca45c72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278089412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2278089412
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4002320602
Short name T581
Test name
Test status
Simulation time 133986108 ps
CPU time 1.34 seconds
Started Jul 26 07:00:58 PM PDT 24
Finished Jul 26 07:00:59 PM PDT 24
Peak memory 208244 kb
Host smart-9bb63cd5-0ea2-4656-a881-59d7f6904d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002320602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.4002320602
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.844143109
Short name T607
Test name
Test status
Simulation time 131659404 ps
CPU time 1.91 seconds
Started Jul 26 07:00:58 PM PDT 24
Finished Jul 26 07:01:00 PM PDT 24
Peak memory 208132 kb
Host smart-9d59320d-0569-4997-9431-aea3b00169db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844143109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.844143109
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.328538766
Short name T132
Test name
Test status
Simulation time 413412204 ps
CPU time 1.9 seconds
Started Jul 26 07:00:55 PM PDT 24
Finished Jul 26 07:00:57 PM PDT 24
Peak memory 199988 kb
Host smart-01703753-580f-4d52-b93a-4d5009bef183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328538766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
328538766
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.930330664
Short name T88
Test name
Test status
Simulation time 109824272 ps
CPU time 0.98 seconds
Started Jul 26 07:01:02 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 199960 kb
Host smart-201b93fa-c204-4524-a0f2-adc8f4e17a2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930330664 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.930330664
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2281095496
Short name T99
Test name
Test status
Simulation time 65157322 ps
CPU time 0.74 seconds
Started Jul 26 07:00:55 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 199728 kb
Host smart-9b16427e-836d-4c97-b2a8-b200e54c298f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281095496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2281095496
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.803890870
Short name T574
Test name
Test status
Simulation time 106730323 ps
CPU time 1.21 seconds
Started Jul 26 07:00:59 PM PDT 24
Finished Jul 26 07:01:00 PM PDT 24
Peak memory 200056 kb
Host smart-e4575315-3ac1-4096-8b76-8f14daac9eb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803890870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.803890870
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4011508033
Short name T593
Test name
Test status
Simulation time 120108700 ps
CPU time 1.81 seconds
Started Jul 26 07:00:56 PM PDT 24
Finished Jul 26 07:00:58 PM PDT 24
Peak memory 208128 kb
Host smart-20cf07c6-ed1e-459f-8c80-fa3be0daeff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011508033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4011508033
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1707937396
Short name T133
Test name
Test status
Simulation time 916528905 ps
CPU time 3.08 seconds
Started Jul 26 07:01:01 PM PDT 24
Finished Jul 26 07:01:04 PM PDT 24
Peak memory 200064 kb
Host smart-278e4d66-49b8-40d7-bd0b-134aa9c6378d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707937396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1707937396
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1018956572
Short name T510
Test name
Test status
Simulation time 1228375551 ps
CPU time 5.43 seconds
Started Jul 26 07:01:03 PM PDT 24
Finished Jul 26 07:01:08 PM PDT 24
Peak memory 217688 kb
Host smart-ae47d489-c545-4ddb-9bb2-71b2443cec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018956572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1018956572
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1241064387
Short name T460
Test name
Test status
Simulation time 244625825 ps
CPU time 1.05 seconds
Started Jul 26 07:01:03 PM PDT 24
Finished Jul 26 07:01:05 PM PDT 24
Peak memory 217328 kb
Host smart-ed45f33a-0721-4638-9ee4-f150b1444885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241064387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1241064387
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1408990876
Short name T494
Test name
Test status
Simulation time 217949630 ps
CPU time 0.92 seconds
Started Jul 26 07:00:56 PM PDT 24
Finished Jul 26 07:00:57 PM PDT 24
Peak memory 199740 kb
Host smart-8bb003b2-85f8-4f12-8800-6abd7dfd465a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408990876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1408990876
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.4253978811
Short name T416
Test name
Test status
Simulation time 879155222 ps
CPU time 5.12 seconds
Started Jul 26 07:00:58 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 200360 kb
Host smart-442ec598-3f98-4bd5-b987-de7546dc538b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253978811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.4253978811
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2804840363
Short name T82
Test name
Test status
Simulation time 8376513082 ps
CPU time 12.89 seconds
Started Jul 26 07:01:13 PM PDT 24
Finished Jul 26 07:01:26 PM PDT 24
Peak memory 217548 kb
Host smart-74df66e7-175f-40b7-b83d-340f9f58ed3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804840363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2804840363
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.4292419715
Short name T252
Test name
Test status
Simulation time 120938736 ps
CPU time 1.19 seconds
Started Jul 26 07:01:06 PM PDT 24
Finished Jul 26 07:01:07 PM PDT 24
Peak memory 200292 kb
Host smart-f600c8b0-851f-4b8f-921a-78754ce16290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292419715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.4292419715
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1672005572
Short name T311
Test name
Test status
Simulation time 5533917074 ps
CPU time 26.81 seconds
Started Jul 26 07:01:15 PM PDT 24
Finished Jul 26 07:01:42 PM PDT 24
Peak memory 208472 kb
Host smart-9c6db6de-c8dc-41c0-8605-578e34e29845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672005572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1672005572
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2093219403
Short name T409
Test name
Test status
Simulation time 348075696 ps
CPU time 1.89 seconds
Started Jul 26 07:01:00 PM PDT 24
Finished Jul 26 07:01:02 PM PDT 24
Peak memory 199936 kb
Host smart-a9121bda-ca30-4db2-897f-36c438073a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093219403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2093219403
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2870021401
Short name T256
Test name
Test status
Simulation time 69413953 ps
CPU time 0.83 seconds
Started Jul 26 07:01:10 PM PDT 24
Finished Jul 26 07:01:11 PM PDT 24
Peak memory 199960 kb
Host smart-51079c3a-43cf-4a09-b437-6725c764bb87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870021401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2870021401
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2303409387
Short name T64
Test name
Test status
Simulation time 1230709178 ps
CPU time 5.51 seconds
Started Jul 26 07:01:01 PM PDT 24
Finished Jul 26 07:01:07 PM PDT 24
Peak memory 222020 kb
Host smart-63b466be-3bbf-4867-b8cc-183f08ee6e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303409387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2303409387
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1818400755
Short name T437
Test name
Test status
Simulation time 244456574 ps
CPU time 1.1 seconds
Started Jul 26 07:01:03 PM PDT 24
Finished Jul 26 07:01:04 PM PDT 24
Peak memory 217408 kb
Host smart-f310a83c-425a-467f-b5df-ab5e4257cb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818400755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1818400755
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1965142754
Short name T211
Test name
Test status
Simulation time 93151367 ps
CPU time 0.77 seconds
Started Jul 26 07:01:09 PM PDT 24
Finished Jul 26 07:01:10 PM PDT 24
Peak memory 199868 kb
Host smart-4dd6cf09-4a00-45cf-a816-577e40fe87fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965142754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1965142754
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3570553502
Short name T318
Test name
Test status
Simulation time 1048462147 ps
CPU time 4.7 seconds
Started Jul 26 07:01:13 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 200344 kb
Host smart-2a84a1ed-9d13-49c2-8db6-e8baa8619c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570553502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3570553502
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3614227444
Short name T77
Test name
Test status
Simulation time 8288019493 ps
CPU time 14.77 seconds
Started Jul 26 07:01:03 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 217192 kb
Host smart-e652a5b6-200b-40c3-a05e-18cd703b056f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614227444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3614227444
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2305400085
Short name T433
Test name
Test status
Simulation time 146993427 ps
CPU time 1.12 seconds
Started Jul 26 07:01:04 PM PDT 24
Finished Jul 26 07:01:05 PM PDT 24
Peak memory 200044 kb
Host smart-de299579-695f-4d69-8a94-42e9bb780e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305400085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2305400085
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1971012343
Short name T325
Test name
Test status
Simulation time 252407672 ps
CPU time 1.47 seconds
Started Jul 26 07:01:15 PM PDT 24
Finished Jul 26 07:01:17 PM PDT 24
Peak memory 200280 kb
Host smart-6ddee747-f742-413e-b5fa-4d120aebe6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971012343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1971012343
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2503377101
Short name T185
Test name
Test status
Simulation time 478028402 ps
CPU time 2.51 seconds
Started Jul 26 07:01:08 PM PDT 24
Finished Jul 26 07:01:11 PM PDT 24
Peak memory 200268 kb
Host smart-56f47380-7291-4388-80f4-39c2ba1628bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503377101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2503377101
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3795614409
Short name T57
Test name
Test status
Simulation time 500419369 ps
CPU time 2.53 seconds
Started Jul 26 07:01:03 PM PDT 24
Finished Jul 26 07:01:06 PM PDT 24
Peak memory 200064 kb
Host smart-b711965b-7d7a-4461-880f-71d7af207231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795614409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3795614409
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1699141163
Short name T179
Test name
Test status
Simulation time 155033449 ps
CPU time 1.11 seconds
Started Jul 26 07:01:08 PM PDT 24
Finished Jul 26 07:01:09 PM PDT 24
Peak memory 200148 kb
Host smart-2421c109-4d32-4464-a0a8-331930af5dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699141163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1699141163
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2648275925
Short name T161
Test name
Test status
Simulation time 73321548 ps
CPU time 0.78 seconds
Started Jul 26 07:01:23 PM PDT 24
Finished Jul 26 07:01:24 PM PDT 24
Peak memory 199884 kb
Host smart-ba4280a7-d5b3-4fee-a8b8-acc5a56288f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648275925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2648275925
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1067124142
Short name T420
Test name
Test status
Simulation time 1233499484 ps
CPU time 5.4 seconds
Started Jul 26 07:01:15 PM PDT 24
Finished Jul 26 07:01:21 PM PDT 24
Peak memory 217752 kb
Host smart-7930f78b-03fc-499e-ad9e-e8628055d7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067124142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1067124142
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2999440161
Short name T183
Test name
Test status
Simulation time 244789099 ps
CPU time 1.09 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 217464 kb
Host smart-a23cf466-5c8e-4554-a00c-1feeb6b9f507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999440161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2999440161
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2026060311
Short name T319
Test name
Test status
Simulation time 172870997 ps
CPU time 0.84 seconds
Started Jul 26 07:01:16 PM PDT 24
Finished Jul 26 07:01:17 PM PDT 24
Peak memory 199880 kb
Host smart-10258d96-3bce-4b94-8998-4df0487e14c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026060311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2026060311
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3130835455
Short name T339
Test name
Test status
Simulation time 1907167630 ps
CPU time 6.92 seconds
Started Jul 26 07:01:15 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 200276 kb
Host smart-0e4e7302-b730-4cc0-b0a2-14316b865377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130835455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3130835455
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1131199573
Short name T137
Test name
Test status
Simulation time 178536065 ps
CPU time 1.2 seconds
Started Jul 26 07:01:15 PM PDT 24
Finished Jul 26 07:01:16 PM PDT 24
Peak memory 200044 kb
Host smart-82c6c261-a3e2-4d2a-b973-62143689b4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131199573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1131199573
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3133691813
Short name T501
Test name
Test status
Simulation time 112992646 ps
CPU time 1.14 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 200320 kb
Host smart-d41f61e8-4c3c-4644-9709-d6b1fe0a8be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133691813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3133691813
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.856070859
Short name T95
Test name
Test status
Simulation time 12433163621 ps
CPU time 40.15 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:59 PM PDT 24
Peak memory 208616 kb
Host smart-adfebfd5-eb77-4109-b088-ef1bc19ae2ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856070859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.856070859
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1512938972
Short name T63
Test name
Test status
Simulation time 139903561 ps
CPU time 1.7 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 200080 kb
Host smart-427c63d6-5558-4ca8-8476-74adc2599177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512938972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1512938972
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.960248009
Short name T364
Test name
Test status
Simulation time 109192620 ps
CPU time 0.98 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 200100 kb
Host smart-ee6b7210-1402-4bba-94b4-799fd91295a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960248009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.960248009
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3464839733
Short name T150
Test name
Test status
Simulation time 73148599 ps
CPU time 0.76 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:01:20 PM PDT 24
Peak memory 199888 kb
Host smart-ea8bd65e-df8e-44ca-8b97-ab7cd383681a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464839733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3464839733
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3493072906
Short name T47
Test name
Test status
Simulation time 1228007701 ps
CPU time 5.37 seconds
Started Jul 26 07:01:25 PM PDT 24
Finished Jul 26 07:01:31 PM PDT 24
Peak memory 221676 kb
Host smart-23c8a729-62d1-43b7-a746-d494dae739fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493072906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3493072906
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2201281484
Short name T196
Test name
Test status
Simulation time 244115319 ps
CPU time 1.06 seconds
Started Jul 26 07:01:36 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 217384 kb
Host smart-15f7d32b-b322-4a59-970f-ce2191ba2725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201281484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2201281484
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1678550991
Short name T435
Test name
Test status
Simulation time 95415932 ps
CPU time 0.78 seconds
Started Jul 26 07:01:28 PM PDT 24
Finished Jul 26 07:01:29 PM PDT 24
Peak memory 199880 kb
Host smart-46911744-9f6f-4e3e-a6cf-0fe8ac1464e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678550991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1678550991
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1166970872
Short name T288
Test name
Test status
Simulation time 1469665088 ps
CPU time 5.54 seconds
Started Jul 26 07:01:23 PM PDT 24
Finished Jul 26 07:01:29 PM PDT 24
Peak memory 200420 kb
Host smart-6c3354c9-9d1d-4f2c-a882-cd4ca6a1b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166970872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1166970872
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.4219942735
Short name T349
Test name
Test status
Simulation time 173066793 ps
CPU time 1.14 seconds
Started Jul 26 07:01:22 PM PDT 24
Finished Jul 26 07:01:24 PM PDT 24
Peak memory 200000 kb
Host smart-20d60163-3a4a-4d5b-9ac9-3863c61f8a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219942735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.4219942735
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2852632874
Short name T167
Test name
Test status
Simulation time 111907632 ps
CPU time 1.16 seconds
Started Jul 26 07:01:27 PM PDT 24
Finished Jul 26 07:01:28 PM PDT 24
Peak memory 200312 kb
Host smart-3a1eea48-7064-41ab-9854-c2a5b05a0b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852632874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2852632874
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1914671277
Short name T97
Test name
Test status
Simulation time 2638295258 ps
CPU time 11.39 seconds
Started Jul 26 07:01:24 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 200320 kb
Host smart-e3ec62ca-4cdc-46cd-b1f5-5f506d065d7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914671277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1914671277
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1471741360
Short name T298
Test name
Test status
Simulation time 142278398 ps
CPU time 1.71 seconds
Started Jul 26 07:01:25 PM PDT 24
Finished Jul 26 07:01:27 PM PDT 24
Peak memory 208216 kb
Host smart-e6edca49-40f1-4e18-a79d-102ec40c0485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471741360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1471741360
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2348792820
Short name T206
Test name
Test status
Simulation time 210567002 ps
CPU time 1.2 seconds
Started Jul 26 07:01:31 PM PDT 24
Finished Jul 26 07:01:32 PM PDT 24
Peak memory 200088 kb
Host smart-a0be359a-5024-4060-a3d3-f7a17066736f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348792820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2348792820
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2438023610
Short name T525
Test name
Test status
Simulation time 79859414 ps
CPU time 0.78 seconds
Started Jul 26 07:01:34 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 199904 kb
Host smart-9042068f-9861-42e1-bd62-e9aa3ad13a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438023610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2438023610
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2763473796
Short name T45
Test name
Test status
Simulation time 1225206864 ps
CPU time 5.63 seconds
Started Jul 26 07:01:21 PM PDT 24
Finished Jul 26 07:01:27 PM PDT 24
Peak memory 217700 kb
Host smart-dc8e079e-976e-46fa-9368-23d452dd4f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763473796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2763473796
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3882484250
Short name T496
Test name
Test status
Simulation time 244122435 ps
CPU time 1.09 seconds
Started Jul 26 07:01:24 PM PDT 24
Finished Jul 26 07:01:26 PM PDT 24
Peak memory 217320 kb
Host smart-f16e45e6-2894-4277-95d5-9d69daafd86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882484250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3882484250
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.4265084167
Short name T512
Test name
Test status
Simulation time 144536766 ps
CPU time 0.83 seconds
Started Jul 26 07:01:24 PM PDT 24
Finished Jul 26 07:01:25 PM PDT 24
Peak memory 199796 kb
Host smart-edd703b7-766f-425b-af2c-8cb8cb815137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265084167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.4265084167
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3377017509
Short name T404
Test name
Test status
Simulation time 1901093642 ps
CPU time 6.84 seconds
Started Jul 26 07:01:28 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 200344 kb
Host smart-437aa9c4-48fd-45ef-a96f-61c6e34f6417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377017509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3377017509
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1686530125
Short name T294
Test name
Test status
Simulation time 102327050 ps
CPU time 1 seconds
Started Jul 26 07:01:22 PM PDT 24
Finished Jul 26 07:01:23 PM PDT 24
Peak memory 200084 kb
Host smart-d1884418-f61f-4294-b5cd-da89b267bdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686530125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1686530125
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.4220762449
Short name T244
Test name
Test status
Simulation time 205939574 ps
CPU time 1.39 seconds
Started Jul 26 07:01:25 PM PDT 24
Finished Jul 26 07:01:26 PM PDT 24
Peak memory 200284 kb
Host smart-d424a93d-f36d-461e-8390-d0588c683370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220762449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.4220762449
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1638982065
Short name T395
Test name
Test status
Simulation time 5824443477 ps
CPU time 26.12 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:47 PM PDT 24
Peak memory 200468 kb
Host smart-72ecbf9d-0917-4109-ae17-46f16132d687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638982065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1638982065
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.8683611
Short name T223
Test name
Test status
Simulation time 390907647 ps
CPU time 2.39 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 200084 kb
Host smart-e4713130-20a9-4e24-a729-118d5333823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8683611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.8683611
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2338178557
Short name T140
Test name
Test status
Simulation time 241790626 ps
CPU time 1.43 seconds
Started Jul 26 07:01:27 PM PDT 24
Finished Jul 26 07:01:29 PM PDT 24
Peak memory 200260 kb
Host smart-c322decb-ddba-4d45-8b29-21e8cc7cd2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338178557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2338178557
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2392018011
Short name T340
Test name
Test status
Simulation time 75072829 ps
CPU time 0.79 seconds
Started Jul 26 07:01:34 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 199884 kb
Host smart-31c91788-cda0-4cab-9bd8-423b26fc67c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392018011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2392018011
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.32643925
Short name T410
Test name
Test status
Simulation time 1893214153 ps
CPU time 6.78 seconds
Started Jul 26 07:01:23 PM PDT 24
Finished Jul 26 07:01:30 PM PDT 24
Peak memory 217664 kb
Host smart-9345d48e-8baf-45de-b80c-1d1849c46d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32643925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.32643925
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.129646452
Short name T498
Test name
Test status
Simulation time 245206957 ps
CPU time 1.04 seconds
Started Jul 26 07:01:23 PM PDT 24
Finished Jul 26 07:01:24 PM PDT 24
Peak memory 217444 kb
Host smart-f651a604-54fe-4715-968e-2bec846d72ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129646452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.129646452
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2270369558
Short name T215
Test name
Test status
Simulation time 1407632602 ps
CPU time 5.09 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:25 PM PDT 24
Peak memory 200388 kb
Host smart-aa848714-b571-4781-85d2-d3f952ae1bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270369558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2270369558
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1138559374
Short name T49
Test name
Test status
Simulation time 149194922 ps
CPU time 1.15 seconds
Started Jul 26 07:01:21 PM PDT 24
Finished Jul 26 07:01:23 PM PDT 24
Peak memory 200072 kb
Host smart-8f07f436-1fd5-4461-9f7a-20b36a520125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138559374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1138559374
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.793629591
Short name T411
Test name
Test status
Simulation time 122568111 ps
CPU time 1.23 seconds
Started Jul 26 07:01:23 PM PDT 24
Finished Jul 26 07:01:24 PM PDT 24
Peak memory 200140 kb
Host smart-cf74a2db-acd5-45b0-92ff-486cf33dcdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793629591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.793629591
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2293188756
Short name T334
Test name
Test status
Simulation time 691613865 ps
CPU time 2.72 seconds
Started Jul 26 07:01:23 PM PDT 24
Finished Jul 26 07:01:26 PM PDT 24
Peak memory 200272 kb
Host smart-6742313f-1b62-451a-bef1-88822cff09ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293188756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2293188756
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1411107646
Short name T31
Test name
Test status
Simulation time 506026914 ps
CPU time 2.73 seconds
Started Jul 26 07:01:25 PM PDT 24
Finished Jul 26 07:01:28 PM PDT 24
Peak memory 200140 kb
Host smart-39766e03-1670-403e-bc88-b61d68fa5fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411107646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1411107646
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4238982383
Short name T214
Test name
Test status
Simulation time 117531656 ps
CPU time 1.04 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 200084 kb
Host smart-171e6ad4-4b96-4554-a4d7-701bcd96c4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238982383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4238982383
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.155431822
Short name T347
Test name
Test status
Simulation time 65319286 ps
CPU time 0.76 seconds
Started Jul 26 07:01:23 PM PDT 24
Finished Jul 26 07:01:24 PM PDT 24
Peak memory 199888 kb
Host smart-56b7a4fc-bd63-4016-a877-7b30d80115c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155431822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.155431822
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3095064986
Short name T491
Test name
Test status
Simulation time 1233674466 ps
CPU time 5.38 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:26 PM PDT 24
Peak memory 221676 kb
Host smart-2ceb825b-418a-4db8-94f1-81b9fe83704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095064986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3095064986
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3914234728
Short name T224
Test name
Test status
Simulation time 244274030 ps
CPU time 1.02 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:21 PM PDT 24
Peak memory 217436 kb
Host smart-ba1096f0-357f-4113-a8c7-9a7a2d7f9d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914234728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3914234728
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2770998423
Short name T397
Test name
Test status
Simulation time 194244210 ps
CPU time 0.95 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 199892 kb
Host smart-f3a5afd9-a040-486a-8299-5627a73236f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770998423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2770998423
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.867820888
Short name T91
Test name
Test status
Simulation time 860986453 ps
CPU time 4.68 seconds
Started Jul 26 07:01:27 PM PDT 24
Finished Jul 26 07:01:32 PM PDT 24
Peak memory 200352 kb
Host smart-eeeaa63d-450e-4b0b-bbbf-97b5fafe8078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867820888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.867820888
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1338134626
Short name T360
Test name
Test status
Simulation time 170689042 ps
CPU time 1.24 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:20 PM PDT 24
Peak memory 200000 kb
Host smart-e235346b-dc53-4cff-9c10-cbae789ebc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338134626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1338134626
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1109737597
Short name T376
Test name
Test status
Simulation time 120444472 ps
CPU time 1.16 seconds
Started Jul 26 07:01:27 PM PDT 24
Finished Jul 26 07:01:29 PM PDT 24
Peak memory 200320 kb
Host smart-e7fd86cd-715d-4146-a473-a88b86b69ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109737597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1109737597
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3952812143
Short name T457
Test name
Test status
Simulation time 9086184734 ps
CPU time 38.95 seconds
Started Jul 26 07:01:22 PM PDT 24
Finished Jul 26 07:02:02 PM PDT 24
Peak memory 209524 kb
Host smart-87649a10-a542-4d8f-aed9-aa6375fec11e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952812143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3952812143
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2889599195
Short name T174
Test name
Test status
Simulation time 264901035 ps
CPU time 1.86 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:20 PM PDT 24
Peak memory 200052 kb
Host smart-7995df5d-629b-4e83-9752-3792c4c45dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889599195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2889599195
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1229430090
Short name T245
Test name
Test status
Simulation time 65160909 ps
CPU time 0.74 seconds
Started Jul 26 07:01:25 PM PDT 24
Finished Jul 26 07:01:26 PM PDT 24
Peak memory 200012 kb
Host smart-c4c1f4c4-ce44-4319-8e17-23046b40dd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229430090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1229430090
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3022479286
Short name T233
Test name
Test status
Simulation time 84778229 ps
CPU time 0.8 seconds
Started Jul 26 07:01:38 PM PDT 24
Finished Jul 26 07:01:39 PM PDT 24
Peak memory 199848 kb
Host smart-ce1e1385-8843-4d97-8e1e-7bf81ca3c960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022479286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3022479286
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3319710292
Short name T38
Test name
Test status
Simulation time 1224453873 ps
CPU time 6.24 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:01:25 PM PDT 24
Peak memory 217420 kb
Host smart-4be287bb-8d37-49f8-8d84-e22bc41d56b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319710292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3319710292
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.769087224
Short name T141
Test name
Test status
Simulation time 244450693 ps
CPU time 1.05 seconds
Started Jul 26 07:01:29 PM PDT 24
Finished Jul 26 07:01:30 PM PDT 24
Peak memory 217320 kb
Host smart-4d469f74-0eca-4d1c-9366-aac9791dd32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769087224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.769087224
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.233474479
Short name T221
Test name
Test status
Simulation time 239204537 ps
CPU time 0.98 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:01:20 PM PDT 24
Peak memory 199756 kb
Host smart-c6d2554d-57a1-4dcd-948f-8fb74612f97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233474479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.233474479
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2732043921
Short name T466
Test name
Test status
Simulation time 850321212 ps
CPU time 4.45 seconds
Started Jul 26 07:01:22 PM PDT 24
Finished Jul 26 07:01:26 PM PDT 24
Peak memory 200364 kb
Host smart-b18169e4-ec9a-43fb-8150-1459acbb2ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732043921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2732043921
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3006389156
Short name T448
Test name
Test status
Simulation time 155494944 ps
CPU time 1.16 seconds
Started Jul 26 07:01:24 PM PDT 24
Finished Jul 26 07:01:31 PM PDT 24
Peak memory 200132 kb
Host smart-dfb945ec-8778-4bf5-bf47-026774242c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006389156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3006389156
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2182103373
Short name T417
Test name
Test status
Simulation time 123080668 ps
CPU time 1.18 seconds
Started Jul 26 07:01:22 PM PDT 24
Finished Jul 26 07:01:23 PM PDT 24
Peak memory 200296 kb
Host smart-07c4b3b6-bd31-4d72-8b0a-7db61bfebdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182103373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2182103373
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.208354137
Short name T209
Test name
Test status
Simulation time 531487322 ps
CPU time 2.88 seconds
Started Jul 26 07:01:26 PM PDT 24
Finished Jul 26 07:01:29 PM PDT 24
Peak memory 200092 kb
Host smart-1ae1d736-d629-4743-884b-248f6bc569a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208354137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.208354137
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1043930800
Short name T192
Test name
Test status
Simulation time 226398184 ps
CPU time 1.35 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:20 PM PDT 24
Peak memory 200060 kb
Host smart-c138426f-ec6b-4117-8f10-fc7f0cc5e6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043930800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1043930800
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1503324742
Short name T426
Test name
Test status
Simulation time 55697273 ps
CPU time 0.73 seconds
Started Jul 26 07:01:32 PM PDT 24
Finished Jul 26 07:01:33 PM PDT 24
Peak memory 199740 kb
Host smart-4d775bf1-894b-44ef-a294-0ed0548686f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503324742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1503324742
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.830538192
Short name T37
Test name
Test status
Simulation time 1892705199 ps
CPU time 8.05 seconds
Started Jul 26 07:01:26 PM PDT 24
Finished Jul 26 07:01:34 PM PDT 24
Peak memory 221668 kb
Host smart-bcb21e44-ebcc-4d61-a05e-11bdbdc271fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830538192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.830538192
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4126863457
Short name T178
Test name
Test status
Simulation time 244239881 ps
CPU time 1.02 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:36 PM PDT 24
Peak memory 217512 kb
Host smart-f350ffad-94f0-4254-adc4-11aaaaa68f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126863457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.4126863457
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2245252115
Short name T17
Test name
Test status
Simulation time 139284605 ps
CPU time 0.88 seconds
Started Jul 26 07:01:38 PM PDT 24
Finished Jul 26 07:01:39 PM PDT 24
Peak memory 199896 kb
Host smart-73a34dc3-7c39-40ec-9b6a-67a1cd60c52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245252115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2245252115
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3874260717
Short name T216
Test name
Test status
Simulation time 953788766 ps
CPU time 4.48 seconds
Started Jul 26 07:01:52 PM PDT 24
Finished Jul 26 07:01:57 PM PDT 24
Peak memory 200340 kb
Host smart-dcccf8d2-8d79-4a11-ad1c-bdd158c98074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874260717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3874260717
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1830162882
Short name T304
Test name
Test status
Simulation time 174690058 ps
CPU time 1.26 seconds
Started Jul 26 07:01:32 PM PDT 24
Finished Jul 26 07:01:33 PM PDT 24
Peak memory 200044 kb
Host smart-f3e40513-991f-44cd-bd45-7a9f1fc8ecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830162882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1830162882
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1543926804
Short name T279
Test name
Test status
Simulation time 131273133 ps
CPU time 1.15 seconds
Started Jul 26 07:01:37 PM PDT 24
Finished Jul 26 07:01:38 PM PDT 24
Peak memory 200280 kb
Host smart-c0cd67ea-6873-4a3d-b5f1-ca3c316091e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543926804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1543926804
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1042197998
Short name T285
Test name
Test status
Simulation time 1359619500 ps
CPU time 6.08 seconds
Started Jul 26 07:01:36 PM PDT 24
Finished Jul 26 07:01:43 PM PDT 24
Peak memory 208596 kb
Host smart-fa7c96c1-1156-4f14-869c-232125c1d57c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042197998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1042197998
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3431280982
Short name T193
Test name
Test status
Simulation time 121363288 ps
CPU time 1.54 seconds
Started Jul 26 07:01:38 PM PDT 24
Finished Jul 26 07:01:45 PM PDT 24
Peak memory 208216 kb
Host smart-14e0d0b8-2600-4c43-bacf-04de9d718549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431280982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3431280982
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3464201642
Short name T13
Test name
Test status
Simulation time 127284839 ps
CPU time 0.98 seconds
Started Jul 26 07:01:53 PM PDT 24
Finished Jul 26 07:01:54 PM PDT 24
Peak memory 200040 kb
Host smart-fe3b7231-2864-4804-bd01-8f02bb4b7964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464201642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3464201642
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2653082638
Short name T489
Test name
Test status
Simulation time 81783721 ps
CPU time 0.89 seconds
Started Jul 26 07:01:32 PM PDT 24
Finished Jul 26 07:01:33 PM PDT 24
Peak memory 199892 kb
Host smart-504f1c46-0a2f-45bc-9b38-1127ed6d26a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653082638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2653082638
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1673557375
Short name T40
Test name
Test status
Simulation time 2329765393 ps
CPU time 7.9 seconds
Started Jul 26 07:01:31 PM PDT 24
Finished Jul 26 07:01:39 PM PDT 24
Peak memory 217216 kb
Host smart-114af2a8-8c1d-4f8f-8566-f64019476bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673557375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1673557375
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2376142849
Short name T230
Test name
Test status
Simulation time 244026168 ps
CPU time 1.09 seconds
Started Jul 26 07:01:28 PM PDT 24
Finished Jul 26 07:01:29 PM PDT 24
Peak memory 217464 kb
Host smart-eea754b2-b2f1-4711-880e-c11bee1a3b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376142849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2376142849
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.501643831
Short name T251
Test name
Test status
Simulation time 115538997 ps
CPU time 0.83 seconds
Started Jul 26 07:01:34 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 199852 kb
Host smart-af31c6b1-0875-4937-acbf-33907a8b02a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501643831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.501643831
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1561523216
Short name T4
Test name
Test status
Simulation time 1492076409 ps
CPU time 5.9 seconds
Started Jul 26 07:01:38 PM PDT 24
Finished Jul 26 07:01:45 PM PDT 24
Peak memory 200304 kb
Host smart-bba1c620-e601-4818-8f8c-38d9777be30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561523216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1561523216
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.4170850660
Short name T454
Test name
Test status
Simulation time 176243144 ps
CPU time 1.13 seconds
Started Jul 26 07:01:30 PM PDT 24
Finished Jul 26 07:01:31 PM PDT 24
Peak memory 200016 kb
Host smart-a5e99004-e87e-4d8c-a3b9-ec968141db51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170850660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.4170850660
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2808460812
Short name T197
Test name
Test status
Simulation time 113453047 ps
CPU time 1.19 seconds
Started Jul 26 07:01:50 PM PDT 24
Finished Jul 26 07:01:51 PM PDT 24
Peak memory 200280 kb
Host smart-3f1a26e9-dd74-4339-9593-93a679c90afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808460812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2808460812
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1415489545
Short name T189
Test name
Test status
Simulation time 12608139663 ps
CPU time 41.63 seconds
Started Jul 26 07:01:32 PM PDT 24
Finished Jul 26 07:02:14 PM PDT 24
Peak memory 200248 kb
Host smart-0b62ac03-9438-4078-8534-cf7ee7badfa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415489545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1415489545
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3298634733
Short name T511
Test name
Test status
Simulation time 326203570 ps
CPU time 2.21 seconds
Started Jul 26 07:01:39 PM PDT 24
Finished Jul 26 07:01:42 PM PDT 24
Peak memory 200116 kb
Host smart-dbc5fb88-3afa-40ef-b23f-f04c69ec9c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298634733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3298634733
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3520693202
Short name T159
Test name
Test status
Simulation time 169784070 ps
CPU time 1.12 seconds
Started Jul 26 07:01:51 PM PDT 24
Finished Jul 26 07:01:52 PM PDT 24
Peak memory 200040 kb
Host smart-08d270ca-baab-46b9-8aec-a7519288fc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520693202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3520693202
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1369884744
Short name T532
Test name
Test status
Simulation time 68107594 ps
CPU time 0.82 seconds
Started Jul 26 07:01:34 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 199892 kb
Host smart-faf98bcc-0c80-4a26-80ec-62f21a6c3f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369884744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1369884744
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.533223689
Short name T453
Test name
Test status
Simulation time 2184458583 ps
CPU time 7.52 seconds
Started Jul 26 07:01:56 PM PDT 24
Finished Jul 26 07:02:03 PM PDT 24
Peak memory 216880 kb
Host smart-7aac1445-4d9f-4c1b-bf10-f3d9591a3afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533223689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.533223689
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1577057038
Short name T400
Test name
Test status
Simulation time 243748541 ps
CPU time 1.06 seconds
Started Jul 26 07:01:25 PM PDT 24
Finished Jul 26 07:01:26 PM PDT 24
Peak memory 217408 kb
Host smart-912eb706-87ce-495e-8ce9-046cfca959be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577057038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1577057038
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2821047268
Short name T519
Test name
Test status
Simulation time 167903123 ps
CPU time 0.96 seconds
Started Jul 26 07:01:26 PM PDT 24
Finished Jul 26 07:01:27 PM PDT 24
Peak memory 199888 kb
Host smart-0ea42a86-4de4-45ad-b77a-9011b016a6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821047268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2821047268
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1708909677
Short name T335
Test name
Test status
Simulation time 1955596613 ps
CPU time 7.02 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:43 PM PDT 24
Peak memory 200360 kb
Host smart-c532f1ab-76e1-4086-8e8a-aabc4f777009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708909677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1708909677
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2253956162
Short name T350
Test name
Test status
Simulation time 151449549 ps
CPU time 1.09 seconds
Started Jul 26 07:01:41 PM PDT 24
Finished Jul 26 07:01:42 PM PDT 24
Peak memory 200288 kb
Host smart-17870f37-b49f-44a5-91f7-edf45874ff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253956162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2253956162
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3355994921
Short name T440
Test name
Test status
Simulation time 198832644 ps
CPU time 1.46 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:36 PM PDT 24
Peak memory 200312 kb
Host smart-d3ef62ee-4e80-4a85-aed4-b92658a0d9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355994921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3355994921
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.257867178
Short name T482
Test name
Test status
Simulation time 464779867 ps
CPU time 2.37 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:38 PM PDT 24
Peak memory 200088 kb
Host smart-f1a15f0f-2439-4c47-9779-51a81c1c782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257867178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.257867178
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2339107406
Short name T210
Test name
Test status
Simulation time 67572413 ps
CPU time 0.73 seconds
Started Jul 26 07:01:50 PM PDT 24
Finished Jul 26 07:01:51 PM PDT 24
Peak memory 199844 kb
Host smart-59dc151d-75af-403b-9de9-96efcdf6eb18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339107406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2339107406
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3701518493
Short name T315
Test name
Test status
Simulation time 2179007578 ps
CPU time 7.33 seconds
Started Jul 26 07:01:41 PM PDT 24
Finished Jul 26 07:01:49 PM PDT 24
Peak memory 221736 kb
Host smart-fcdc16e1-1e72-4b75-badf-75e26dda35f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701518493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3701518493
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1017925078
Short name T520
Test name
Test status
Simulation time 244494679 ps
CPU time 1.07 seconds
Started Jul 26 07:01:45 PM PDT 24
Finished Jul 26 07:01:46 PM PDT 24
Peak memory 217388 kb
Host smart-6aca19f0-56ca-401b-b7e2-c560be6dfa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017925078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1017925078
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2185537948
Short name T316
Test name
Test status
Simulation time 220164703 ps
CPU time 1.03 seconds
Started Jul 26 07:01:40 PM PDT 24
Finished Jul 26 07:01:41 PM PDT 24
Peak memory 199868 kb
Host smart-ea5630c3-10f1-4099-be7d-3a10b62daa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185537948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2185537948
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1276852651
Short name T176
Test name
Test status
Simulation time 929243579 ps
CPU time 4.14 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:40 PM PDT 24
Peak memory 200376 kb
Host smart-604ec9c7-35c0-440c-8c09-70c04551d566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276852651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1276852651
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1062147161
Short name T264
Test name
Test status
Simulation time 168746010 ps
CPU time 1.11 seconds
Started Jul 26 07:01:37 PM PDT 24
Finished Jul 26 07:01:39 PM PDT 24
Peak memory 200084 kb
Host smart-f7bec501-c545-4889-a0b2-a48178bee5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062147161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1062147161
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3545058087
Short name T12
Test name
Test status
Simulation time 246744474 ps
CPU time 1.53 seconds
Started Jul 26 07:01:29 PM PDT 24
Finished Jul 26 07:01:31 PM PDT 24
Peak memory 200556 kb
Host smart-19e84245-3499-47e2-86d8-f20a7b40b82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545058087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3545058087
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2654015569
Short name T439
Test name
Test status
Simulation time 3888475261 ps
CPU time 16.84 seconds
Started Jul 26 07:01:39 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 208560 kb
Host smart-c4fef0e8-3e4a-43a9-9f3c-ff05e3b2ae21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654015569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2654015569
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.185355205
Short name T484
Test name
Test status
Simulation time 119398880 ps
CPU time 1.5 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 200152 kb
Host smart-944f1356-3161-4bf6-b74d-bc3fca5e2faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185355205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.185355205
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2678275890
Short name T394
Test name
Test status
Simulation time 157536072 ps
CPU time 1.27 seconds
Started Jul 26 07:01:30 PM PDT 24
Finished Jul 26 07:01:31 PM PDT 24
Peak memory 200280 kb
Host smart-25744494-0282-4b77-b2ee-db7f32f4bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678275890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2678275890
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3019318259
Short name T458
Test name
Test status
Simulation time 84205083 ps
CPU time 0.84 seconds
Started Jul 26 07:01:05 PM PDT 24
Finished Jul 26 07:01:06 PM PDT 24
Peak memory 199852 kb
Host smart-a2e88b80-d592-400b-9c2e-c4e362445795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019318259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3019318259
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4179735119
Short name T26
Test name
Test status
Simulation time 1886578109 ps
CPU time 6.54 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:01:25 PM PDT 24
Peak memory 216876 kb
Host smart-e8d14e0e-4f40-44cf-bb86-5e217a0d0641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179735119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4179735119
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.151125147
Short name T62
Test name
Test status
Simulation time 244530762 ps
CPU time 1.04 seconds
Started Jul 26 07:01:09 PM PDT 24
Finished Jul 26 07:01:10 PM PDT 24
Peak memory 217420 kb
Host smart-255bbe78-4934-4d26-af2f-ea58ca204661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151125147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.151125147
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2037437379
Short name T187
Test name
Test status
Simulation time 198947851 ps
CPU time 0.89 seconds
Started Jul 26 07:01:16 PM PDT 24
Finished Jul 26 07:01:17 PM PDT 24
Peak memory 199788 kb
Host smart-8cc81bc6-5c8a-4f7d-b508-e13e7895b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037437379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2037437379
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1932984732
Short name T529
Test name
Test status
Simulation time 1239407041 ps
CPU time 4.87 seconds
Started Jul 26 07:01:08 PM PDT 24
Finished Jul 26 07:01:13 PM PDT 24
Peak memory 200356 kb
Host smart-a5621371-a03b-4515-8702-4c9acf9552ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932984732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1932984732
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3557198582
Short name T78
Test name
Test status
Simulation time 16749617691 ps
CPU time 25.46 seconds
Started Jul 26 07:01:04 PM PDT 24
Finished Jul 26 07:01:29 PM PDT 24
Peak memory 217136 kb
Host smart-c6a9691a-ca81-4b2d-84e7-ce5d60a38e7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557198582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3557198582
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1608536863
Short name T156
Test name
Test status
Simulation time 171533542 ps
CPU time 1.25 seconds
Started Jul 26 07:01:11 PM PDT 24
Finished Jul 26 07:01:13 PM PDT 24
Peak memory 200136 kb
Host smart-794f8770-3b92-4008-8822-b184af2eff20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608536863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1608536863
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3289684728
Short name T518
Test name
Test status
Simulation time 249777559 ps
CPU time 1.5 seconds
Started Jul 26 07:01:01 PM PDT 24
Finished Jul 26 07:01:02 PM PDT 24
Peak memory 200288 kb
Host smart-43c579bc-5b8a-47f2-bc59-99aacf0f4f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289684728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3289684728
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.4198816860
Short name T392
Test name
Test status
Simulation time 1876553353 ps
CPU time 7.37 seconds
Started Jul 26 07:01:07 PM PDT 24
Finished Jul 26 07:01:14 PM PDT 24
Peak memory 200340 kb
Host smart-6dcdfc24-6587-4642-83cf-0a0ba8f3348b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198816860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.4198816860
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3099003778
Short name T445
Test name
Test status
Simulation time 340740066 ps
CPU time 2.38 seconds
Started Jul 26 07:01:09 PM PDT 24
Finished Jul 26 07:01:11 PM PDT 24
Peak memory 200100 kb
Host smart-b29f3c90-d095-4d32-bedf-2bf4db410513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099003778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3099003778
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2053702123
Short name T329
Test name
Test status
Simulation time 106691922 ps
CPU time 0.97 seconds
Started Jul 26 07:01:04 PM PDT 24
Finished Jul 26 07:01:05 PM PDT 24
Peak memory 200048 kb
Host smart-e1150f0a-7787-4dc5-bd55-fd9840cbdb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053702123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2053702123
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2321997610
Short name T204
Test name
Test status
Simulation time 82356747 ps
CPU time 0.76 seconds
Started Jul 26 07:01:47 PM PDT 24
Finished Jul 26 07:01:48 PM PDT 24
Peak memory 199844 kb
Host smart-afe09f1b-dc45-448c-ac92-241ce52a7570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321997610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2321997610
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.715379501
Short name T488
Test name
Test status
Simulation time 1894300792 ps
CPU time 6.72 seconds
Started Jul 26 07:01:46 PM PDT 24
Finished Jul 26 07:01:53 PM PDT 24
Peak memory 221668 kb
Host smart-62f0aa10-b112-446b-9938-7ee0d0926d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715379501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.715379501
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3804810210
Short name T465
Test name
Test status
Simulation time 243858843 ps
CPU time 1.11 seconds
Started Jul 26 07:01:32 PM PDT 24
Finished Jul 26 07:01:33 PM PDT 24
Peak memory 217412 kb
Host smart-ab407fb5-1618-499b-a525-9e9992ba9c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804810210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3804810210
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.654164815
Short name T240
Test name
Test status
Simulation time 134249137 ps
CPU time 0.8 seconds
Started Jul 26 07:01:24 PM PDT 24
Finished Jul 26 07:01:25 PM PDT 24
Peak memory 199864 kb
Host smart-1456dd7f-2393-44e4-8d1b-17d513b65f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654164815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.654164815
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1845731564
Short name T263
Test name
Test status
Simulation time 1005876706 ps
CPU time 5.28 seconds
Started Jul 26 07:01:32 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 200348 kb
Host smart-a1a7cbf2-29ef-46ce-ae31-3fca44f12d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845731564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1845731564
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1290805504
Short name T432
Test name
Test status
Simulation time 153606825 ps
CPU time 1.08 seconds
Started Jul 26 07:01:43 PM PDT 24
Finished Jul 26 07:01:44 PM PDT 24
Peak memory 200064 kb
Host smart-f9069fd9-41ec-4e4c-80cd-212d14989cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290805504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1290805504
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3149754758
Short name T434
Test name
Test status
Simulation time 265457980 ps
CPU time 1.49 seconds
Started Jul 26 07:01:36 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 200276 kb
Host smart-36c17f02-6dd8-4b88-a6ff-6170816f33be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149754758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3149754758
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.4053638102
Short name T336
Test name
Test status
Simulation time 1641619337 ps
CPU time 7.27 seconds
Started Jul 26 07:01:57 PM PDT 24
Finished Jul 26 07:02:04 PM PDT 24
Peak memory 208492 kb
Host smart-c5259d68-3c76-46ef-a4b5-e0042748726c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053638102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.4053638102
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3041213065
Short name T455
Test name
Test status
Simulation time 109953913 ps
CPU time 1.37 seconds
Started Jul 26 07:01:42 PM PDT 24
Finished Jul 26 07:01:44 PM PDT 24
Peak memory 200300 kb
Host smart-c6d54c02-0d37-41f7-aecd-19c418c80b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041213065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3041213065
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2787257039
Short name T441
Test name
Test status
Simulation time 151700829 ps
CPU time 1.14 seconds
Started Jul 26 07:01:36 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 200304 kb
Host smart-c4afdf43-f551-4fef-9d16-2a0ee2aad63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787257039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2787257039
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3856945545
Short name T428
Test name
Test status
Simulation time 68447686 ps
CPU time 0.72 seconds
Started Jul 26 07:01:45 PM PDT 24
Finished Jul 26 07:01:46 PM PDT 24
Peak memory 199848 kb
Host smart-42d3e064-131b-4f68-89cb-9c33ee240f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856945545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3856945545
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2875845925
Short name T436
Test name
Test status
Simulation time 1891165957 ps
CPU time 7.24 seconds
Started Jul 26 07:01:53 PM PDT 24
Finished Jul 26 07:02:00 PM PDT 24
Peak memory 217468 kb
Host smart-4c858c9c-2e6b-4e33-948d-af7d624814a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875845925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2875845925
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.214454534
Short name T296
Test name
Test status
Simulation time 244244418 ps
CPU time 1.09 seconds
Started Jul 26 07:01:38 PM PDT 24
Finished Jul 26 07:01:40 PM PDT 24
Peak memory 217484 kb
Host smart-a1e8d094-8650-4e6a-9ff0-d73e26ee1134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214454534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.214454534
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.613855097
Short name T500
Test name
Test status
Simulation time 132694307 ps
CPU time 0.78 seconds
Started Jul 26 07:01:39 PM PDT 24
Finished Jul 26 07:01:40 PM PDT 24
Peak memory 199848 kb
Host smart-93c448a2-d6ca-45d0-a96e-6686f28c0825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613855097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.613855097
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1466417594
Short name T122
Test name
Test status
Simulation time 1604384111 ps
CPU time 6.3 seconds
Started Jul 26 07:01:38 PM PDT 24
Finished Jul 26 07:01:44 PM PDT 24
Peak memory 200420 kb
Host smart-7ba5e062-c83a-4624-88c2-70cafbed8d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466417594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1466417594
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1981115601
Short name T359
Test name
Test status
Simulation time 108163707 ps
CPU time 1.01 seconds
Started Jul 26 07:01:36 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 200064 kb
Host smart-7f39b405-6ef4-4fd0-b5f0-11b68749b5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981115601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1981115601
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1909558058
Short name T471
Test name
Test status
Simulation time 199735878 ps
CPU time 1.33 seconds
Started Jul 26 07:01:39 PM PDT 24
Finished Jul 26 07:01:40 PM PDT 24
Peak memory 200240 kb
Host smart-4f4cccfb-f521-4349-a69b-eff14582393d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909558058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1909558058
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3722857703
Short name T190
Test name
Test status
Simulation time 2975765545 ps
CPU time 13.3 seconds
Started Jul 26 07:01:50 PM PDT 24
Finished Jul 26 07:02:04 PM PDT 24
Peak memory 200444 kb
Host smart-bbc2ec67-0927-4eeb-82ad-30cb7ffcbae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722857703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3722857703
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.813749303
Short name T468
Test name
Test status
Simulation time 512871613 ps
CPU time 2.69 seconds
Started Jul 26 07:01:38 PM PDT 24
Finished Jul 26 07:01:41 PM PDT 24
Peak memory 200044 kb
Host smart-9b34dfb2-cde2-43ae-a9dd-60590bbb4afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813749303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.813749303
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1471548952
Short name T225
Test name
Test status
Simulation time 114624901 ps
CPU time 0.98 seconds
Started Jul 26 07:01:37 PM PDT 24
Finished Jul 26 07:01:38 PM PDT 24
Peak memory 200080 kb
Host smart-5f9f8237-ddab-43e6-ac74-c2e551b7a0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471548952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1471548952
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3441534739
Short name T191
Test name
Test status
Simulation time 68664623 ps
CPU time 0.77 seconds
Started Jul 26 07:01:52 PM PDT 24
Finished Jul 26 07:01:53 PM PDT 24
Peak memory 199840 kb
Host smart-dcb9ddb2-20ab-4776-8776-148e65346e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441534739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3441534739
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2454824126
Short name T399
Test name
Test status
Simulation time 244440414 ps
CPU time 1.07 seconds
Started Jul 26 07:01:34 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 217352 kb
Host smart-80e9c030-c3c4-4c2b-82b6-9f618d7b90f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454824126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2454824126
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.626336123
Short name T356
Test name
Test status
Simulation time 168492808 ps
CPU time 0.88 seconds
Started Jul 26 07:01:57 PM PDT 24
Finished Jul 26 07:01:58 PM PDT 24
Peak memory 199964 kb
Host smart-065b250e-2779-4a4a-b0eb-4d71f8a8e270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626336123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.626336123
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1507389960
Short name T173
Test name
Test status
Simulation time 990493073 ps
CPU time 4.7 seconds
Started Jul 26 07:01:38 PM PDT 24
Finished Jul 26 07:01:43 PM PDT 24
Peak memory 200336 kb
Host smart-5e30ec76-afb1-4e56-a00d-b90213ce7b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507389960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1507389960
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.805121493
Short name T461
Test name
Test status
Simulation time 137158437 ps
CPU time 1.13 seconds
Started Jul 26 07:01:32 PM PDT 24
Finished Jul 26 07:01:33 PM PDT 24
Peak memory 200096 kb
Host smart-5a85f748-551d-43a2-a2bd-bcf13e1c22f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805121493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.805121493
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.133420394
Short name T320
Test name
Test status
Simulation time 205782612 ps
CPU time 1.42 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 200280 kb
Host smart-bc3406d5-00ad-4988-8338-b086a4e43131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133420394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.133420394
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1849107261
Short name T476
Test name
Test status
Simulation time 13431469671 ps
CPU time 43.97 seconds
Started Jul 26 07:01:51 PM PDT 24
Finished Jul 26 07:02:35 PM PDT 24
Peak memory 200412 kb
Host smart-43c0bde8-79ee-40b4-8d60-af51807a1069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849107261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1849107261
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3842902961
Short name T126
Test name
Test status
Simulation time 531702425 ps
CPU time 2.68 seconds
Started Jul 26 07:01:39 PM PDT 24
Finished Jul 26 07:01:42 PM PDT 24
Peak memory 200160 kb
Host smart-83c8000b-631a-48a8-ab85-ee0c794b76d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842902961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3842902961
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3664497031
Short name T345
Test name
Test status
Simulation time 76617263 ps
CPU time 0.79 seconds
Started Jul 26 07:01:40 PM PDT 24
Finished Jul 26 07:01:41 PM PDT 24
Peak memory 200052 kb
Host smart-39285bd5-535c-4a24-9b02-a503b576f1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664497031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3664497031
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3913608386
Short name T182
Test name
Test status
Simulation time 73705316 ps
CPU time 0.76 seconds
Started Jul 26 07:01:34 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 199872 kb
Host smart-01a24c69-ec17-456d-b861-6b2d64811985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913608386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3913608386
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3035136662
Short name T424
Test name
Test status
Simulation time 244207776 ps
CPU time 1.09 seconds
Started Jul 26 07:01:59 PM PDT 24
Finished Jul 26 07:02:00 PM PDT 24
Peak memory 217444 kb
Host smart-5c7269c1-5c95-4e9e-9c8e-df58bbbeb662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035136662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3035136662
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.264357587
Short name T543
Test name
Test status
Simulation time 161372282 ps
CPU time 0.84 seconds
Started Jul 26 07:01:39 PM PDT 24
Finished Jul 26 07:01:40 PM PDT 24
Peak memory 199872 kb
Host smart-fe31d663-c985-4a53-8b90-0b5b7b9b2b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264357587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.264357587
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2171060884
Short name T412
Test name
Test status
Simulation time 1030005443 ps
CPU time 4.92 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:02:00 PM PDT 24
Peak memory 200316 kb
Host smart-83e1db0a-edf2-4bc4-b2e6-c7df4558fed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171060884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2171060884
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3544082913
Short name T536
Test name
Test status
Simulation time 108574026 ps
CPU time 0.99 seconds
Started Jul 26 07:01:45 PM PDT 24
Finished Jul 26 07:01:46 PM PDT 24
Peak memory 200044 kb
Host smart-877cc26d-1e25-41d2-a60b-e292d45f8c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544082913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3544082913
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3757050738
Short name T497
Test name
Test status
Simulation time 197326444 ps
CPU time 1.36 seconds
Started Jul 26 07:01:50 PM PDT 24
Finished Jul 26 07:01:51 PM PDT 24
Peak memory 200240 kb
Host smart-702328e8-f5ff-4dcb-98d3-c041fa74c9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757050738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3757050738
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2810490221
Short name T317
Test name
Test status
Simulation time 3536217656 ps
CPU time 13.97 seconds
Started Jul 26 07:01:33 PM PDT 24
Finished Jul 26 07:01:47 PM PDT 24
Peak memory 200320 kb
Host smart-9aff7fe9-7113-4e70-ac8b-28c028c0ba57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810490221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2810490221
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3063650041
Short name T473
Test name
Test status
Simulation time 146207443 ps
CPU time 1.76 seconds
Started Jul 26 07:01:40 PM PDT 24
Finished Jul 26 07:01:42 PM PDT 24
Peak memory 200064 kb
Host smart-a510d7d1-afab-4912-9cda-b05122fff0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063650041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3063650041
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.733138308
Short name T253
Test name
Test status
Simulation time 116360716 ps
CPU time 1.09 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 199992 kb
Host smart-76f9d067-8b6b-49ff-a0bc-f74ba2adc95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733138308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.733138308
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1807795923
Short name T333
Test name
Test status
Simulation time 81457370 ps
CPU time 0.86 seconds
Started Jul 26 07:01:34 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 199880 kb
Host smart-f8ef23ff-f2f4-47be-b92e-512aa94fb94e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807795923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1807795923
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4149766147
Short name T158
Test name
Test status
Simulation time 250655240 ps
CPU time 1.04 seconds
Started Jul 26 07:01:41 PM PDT 24
Finished Jul 26 07:01:42 PM PDT 24
Peak memory 217372 kb
Host smart-bd25bee9-56f5-4b1e-b2ee-6d5a0ae7edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149766147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4149766147
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1990914666
Short name T20
Test name
Test status
Simulation time 146399576 ps
CPU time 0.8 seconds
Started Jul 26 07:01:34 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 199848 kb
Host smart-0ea3530d-7603-4e55-8885-6c5991c3468e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990914666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1990914666
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2925263966
Short name T303
Test name
Test status
Simulation time 1495593014 ps
CPU time 5.44 seconds
Started Jul 26 07:01:37 PM PDT 24
Finished Jul 26 07:01:42 PM PDT 24
Peak memory 200348 kb
Host smart-a2ed9ca4-efe6-47d9-b4ac-b703596d66f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925263966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2925263966
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2062584401
Short name T275
Test name
Test status
Simulation time 112573763 ps
CPU time 1 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 200076 kb
Host smart-1be63401-e49b-4b41-9ef4-56d0ac7fd570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062584401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2062584401
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.556420811
Short name T509
Test name
Test status
Simulation time 246074268 ps
CPU time 1.52 seconds
Started Jul 26 07:01:38 PM PDT 24
Finished Jul 26 07:01:40 PM PDT 24
Peak memory 200276 kb
Host smart-0a97a1e6-bcbb-4f58-9a50-a716589cbcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556420811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.556420811
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1666136990
Short name T456
Test name
Test status
Simulation time 16058949050 ps
CPU time 50.72 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:02:26 PM PDT 24
Peak memory 200372 kb
Host smart-7244b588-cd87-42cc-ad4c-38c63eb82b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666136990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1666136990
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3315265964
Short name T247
Test name
Test status
Simulation time 343612271 ps
CPU time 2.33 seconds
Started Jul 26 07:01:58 PM PDT 24
Finished Jul 26 07:02:00 PM PDT 24
Peak memory 200032 kb
Host smart-85e5a751-bf8f-47f3-beed-bc8ca7ce8262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315265964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3315265964
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.329920543
Short name T548
Test name
Test status
Simulation time 146566011 ps
CPU time 1.05 seconds
Started Jul 26 07:01:39 PM PDT 24
Finished Jul 26 07:01:40 PM PDT 24
Peak memory 200064 kb
Host smart-b267c3cb-1b86-4b11-a6b1-354c3f461ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329920543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.329920543
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1786820207
Short name T180
Test name
Test status
Simulation time 84407570 ps
CPU time 0.82 seconds
Started Jul 26 07:01:39 PM PDT 24
Finished Jul 26 07:01:40 PM PDT 24
Peak memory 199824 kb
Host smart-82d3fa99-2935-4603-8355-19af25cdfd5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786820207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1786820207
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.919487967
Short name T431
Test name
Test status
Simulation time 1879712444 ps
CPU time 7.66 seconds
Started Jul 26 07:01:40 PM PDT 24
Finished Jul 26 07:01:48 PM PDT 24
Peak memory 221764 kb
Host smart-78f600d5-9d9e-42f8-8402-53ade04ab82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919487967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.919487967
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.116709256
Short name T248
Test name
Test status
Simulation time 244405910 ps
CPU time 1.06 seconds
Started Jul 26 07:01:44 PM PDT 24
Finished Jul 26 07:01:46 PM PDT 24
Peak memory 217444 kb
Host smart-3ca72adf-d939-484c-9492-3d71c92af174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116709256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.116709256
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3181519879
Short name T451
Test name
Test status
Simulation time 219996410 ps
CPU time 0.91 seconds
Started Jul 26 07:01:50 PM PDT 24
Finished Jul 26 07:01:51 PM PDT 24
Peak memory 199856 kb
Host smart-4ce88ece-fc10-4f74-b1c6-def7e6193234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181519879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3181519879
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.4096380979
Short name T2
Test name
Test status
Simulation time 684539296 ps
CPU time 3.44 seconds
Started Jul 26 07:01:48 PM PDT 24
Finished Jul 26 07:01:51 PM PDT 24
Peak memory 200344 kb
Host smart-02bc1e39-f88c-4369-a725-e979f5fd3c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096380979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.4096380979
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.172988492
Short name T421
Test name
Test status
Simulation time 148999029 ps
CPU time 1.14 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 200024 kb
Host smart-89950dd8-44bc-4381-bf12-7de2a2488977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172988492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.172988492
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3991455295
Short name T427
Test name
Test status
Simulation time 114118775 ps
CPU time 1.18 seconds
Started Jul 26 07:02:00 PM PDT 24
Finished Jul 26 07:02:01 PM PDT 24
Peak memory 200256 kb
Host smart-8edd8ce2-359d-4230-b780-df60ec5e95ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991455295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3991455295
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.289173567
Short name T549
Test name
Test status
Simulation time 10920524894 ps
CPU time 34.45 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:02:10 PM PDT 24
Peak memory 208616 kb
Host smart-9a9f6d1f-187b-4153-a145-878e891bd747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289173567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.289173567
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3462002775
Short name T299
Test name
Test status
Simulation time 120774432 ps
CPU time 1.46 seconds
Started Jul 26 07:01:41 PM PDT 24
Finished Jul 26 07:01:43 PM PDT 24
Peak memory 200036 kb
Host smart-25dbc9d6-49b7-4f2e-b669-4ce44aeaa301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462002775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3462002775
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2016009292
Short name T446
Test name
Test status
Simulation time 106316695 ps
CPU time 0.99 seconds
Started Jul 26 07:01:41 PM PDT 24
Finished Jul 26 07:01:42 PM PDT 24
Peak memory 200036 kb
Host smart-d2608981-8d12-48be-b8f9-d9b8122874c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016009292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2016009292
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3080466381
Short name T353
Test name
Test status
Simulation time 64272248 ps
CPU time 0.75 seconds
Started Jul 26 07:01:51 PM PDT 24
Finished Jul 26 07:01:57 PM PDT 24
Peak memory 199876 kb
Host smart-d4b78d0c-fe66-4ad6-9bc3-cfdea93f3c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080466381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3080466381
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3494149398
Short name T447
Test name
Test status
Simulation time 1887040823 ps
CPU time 6.66 seconds
Started Jul 26 07:01:38 PM PDT 24
Finished Jul 26 07:01:45 PM PDT 24
Peak memory 217728 kb
Host smart-5585a111-15ca-46d1-ac88-7afa8162709e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494149398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3494149398
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2525631326
Short name T546
Test name
Test status
Simulation time 243568549 ps
CPU time 1.17 seconds
Started Jul 26 07:01:33 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 217476 kb
Host smart-d8eedce6-2e31-4dd0-81b6-f23a579dc2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525631326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2525631326
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.386959704
Short name T306
Test name
Test status
Simulation time 118912304 ps
CPU time 0.83 seconds
Started Jul 26 07:01:53 PM PDT 24
Finished Jul 26 07:01:54 PM PDT 24
Peak memory 199900 kb
Host smart-152e28f3-585f-4995-a9c3-5399490335d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386959704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.386959704
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2375524275
Short name T3
Test name
Test status
Simulation time 828286863 ps
CPU time 4.3 seconds
Started Jul 26 07:01:49 PM PDT 24
Finished Jul 26 07:01:53 PM PDT 24
Peak memory 200304 kb
Host smart-a5a36ec0-8490-4b86-8180-3ca9479449e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375524275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2375524275
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3311426960
Short name T505
Test name
Test status
Simulation time 154567198 ps
CPU time 1.19 seconds
Started Jul 26 07:01:45 PM PDT 24
Finished Jul 26 07:01:46 PM PDT 24
Peak memory 200068 kb
Host smart-74f9be92-bf02-45b4-8628-6aa557dc1c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311426960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3311426960
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1678690788
Short name T408
Test name
Test status
Simulation time 182282432 ps
CPU time 1.41 seconds
Started Jul 26 07:01:41 PM PDT 24
Finished Jul 26 07:01:42 PM PDT 24
Peak memory 200236 kb
Host smart-0df83279-7ad5-4668-9013-48a9e4db3e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678690788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1678690788
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1345501052
Short name T29
Test name
Test status
Simulation time 322651011 ps
CPU time 1.76 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:57 PM PDT 24
Peak memory 200120 kb
Host smart-973d52fa-a8c2-4733-aa28-3643e97e7085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345501052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1345501052
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3114158239
Short name T154
Test name
Test status
Simulation time 285148612 ps
CPU time 1.91 seconds
Started Jul 26 07:01:39 PM PDT 24
Finished Jul 26 07:01:41 PM PDT 24
Peak memory 200104 kb
Host smart-d7b44dca-1f3c-4270-9f9c-67c3ee4ec931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114158239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3114158239
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3264407305
Short name T166
Test name
Test status
Simulation time 217995907 ps
CPU time 1.34 seconds
Started Jul 26 07:01:35 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 200080 kb
Host smart-df583608-e9cf-4134-8c5d-0cd3ab7f345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264407305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3264407305
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2722597479
Short name T531
Test name
Test status
Simulation time 78817020 ps
CPU time 0.78 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 199948 kb
Host smart-7ed794f0-02a1-4d02-a3b8-8055949a8723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722597479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2722597479
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2561950228
Short name T503
Test name
Test status
Simulation time 2174431133 ps
CPU time 7.99 seconds
Started Jul 26 07:01:51 PM PDT 24
Finished Jul 26 07:01:59 PM PDT 24
Peak memory 217780 kb
Host smart-bd2ca3ae-affd-413c-98b9-7524607ce914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561950228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2561950228
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.900934398
Short name T234
Test name
Test status
Simulation time 244119104 ps
CPU time 1.12 seconds
Started Jul 26 07:02:01 PM PDT 24
Finished Jul 26 07:02:02 PM PDT 24
Peak memory 217392 kb
Host smart-47d3197a-5275-485a-81c1-d66e00773563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900934398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.900934398
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2113348542
Short name T425
Test name
Test status
Simulation time 76290039 ps
CPU time 0.74 seconds
Started Jul 26 07:01:47 PM PDT 24
Finished Jul 26 07:01:48 PM PDT 24
Peak memory 199836 kb
Host smart-b6812881-237e-489b-a371-1e8d2637a4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113348542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2113348542
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.30739254
Short name T370
Test name
Test status
Simulation time 981829953 ps
CPU time 4.88 seconds
Started Jul 26 07:01:56 PM PDT 24
Finished Jul 26 07:02:01 PM PDT 24
Peak memory 200404 kb
Host smart-b66878b0-8f0d-453e-bc03-e49bc6a54f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30739254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.30739254
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2348746178
Short name T377
Test name
Test status
Simulation time 176939061 ps
CPU time 1.16 seconds
Started Jul 26 07:01:59 PM PDT 24
Finished Jul 26 07:02:00 PM PDT 24
Peak memory 200000 kb
Host smart-c871bc3e-a7ec-48fe-a094-47f4eafa39fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348746178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2348746178
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3441056899
Short name T309
Test name
Test status
Simulation time 122904829 ps
CPU time 1.27 seconds
Started Jul 26 07:01:53 PM PDT 24
Finished Jul 26 07:01:54 PM PDT 24
Peak memory 200356 kb
Host smart-c526c990-7a6c-4716-9185-29343050b6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441056899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3441056899
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2053439135
Short name T227
Test name
Test status
Simulation time 3117635688 ps
CPU time 15.15 seconds
Started Jul 26 07:01:54 PM PDT 24
Finished Jul 26 07:02:10 PM PDT 24
Peak memory 200392 kb
Host smart-5b2b7569-54c7-42c1-9b38-022b6260b972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053439135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2053439135
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1929092888
Short name T237
Test name
Test status
Simulation time 482710753 ps
CPU time 2.7 seconds
Started Jul 26 07:02:02 PM PDT 24
Finished Jul 26 07:02:05 PM PDT 24
Peak memory 208232 kb
Host smart-6d040c7b-b6a6-476a-b225-30d6e413813a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929092888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1929092888
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3513193579
Short name T186
Test name
Test status
Simulation time 245496655 ps
CPU time 1.29 seconds
Started Jul 26 07:02:02 PM PDT 24
Finished Jul 26 07:02:04 PM PDT 24
Peak memory 200100 kb
Host smart-9287bed6-155a-4ccf-9bb9-26bdae786167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513193579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3513193579
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1428476711
Short name T477
Test name
Test status
Simulation time 57820566 ps
CPU time 0.72 seconds
Started Jul 26 07:01:47 PM PDT 24
Finished Jul 26 07:01:48 PM PDT 24
Peak memory 199848 kb
Host smart-9594f746-2c3c-4d95-98c4-8c4bb0042b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428476711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1428476711
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.660201361
Short name T55
Test name
Test status
Simulation time 2360725728 ps
CPU time 7.92 seconds
Started Jul 26 07:01:46 PM PDT 24
Finished Jul 26 07:01:54 PM PDT 24
Peak memory 217808 kb
Host smart-7bb16220-9741-40d7-b3cb-f1a7d4cec9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660201361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.660201361
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.692145548
Short name T475
Test name
Test status
Simulation time 244951004 ps
CPU time 1.15 seconds
Started Jul 26 07:01:42 PM PDT 24
Finished Jul 26 07:01:44 PM PDT 24
Peak memory 217464 kb
Host smart-3b17f194-48fb-4593-ae33-cbbe472a460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692145548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.692145548
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.168167983
Short name T194
Test name
Test status
Simulation time 106694237 ps
CPU time 0.76 seconds
Started Jul 26 07:01:44 PM PDT 24
Finished Jul 26 07:01:45 PM PDT 24
Peak memory 199896 kb
Host smart-c35a9b91-b654-46fc-a19a-c1c58042a37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168167983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.168167983
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3832898849
Short name T462
Test name
Test status
Simulation time 1490550177 ps
CPU time 5.48 seconds
Started Jul 26 07:01:49 PM PDT 24
Finished Jul 26 07:01:54 PM PDT 24
Peak memory 200368 kb
Host smart-89112aba-b6d8-4b77-999d-c3e5f512ef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832898849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3832898849
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.10667753
Short name T419
Test name
Test status
Simulation time 153941268 ps
CPU time 1.09 seconds
Started Jul 26 07:01:51 PM PDT 24
Finished Jul 26 07:01:52 PM PDT 24
Peak memory 200092 kb
Host smart-b70b3a2f-6a02-4d35-837a-464046e16011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10667753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.10667753
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2444395090
Short name T262
Test name
Test status
Simulation time 190283236 ps
CPU time 1.4 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 200232 kb
Host smart-fe6fc672-6224-4c30-9189-40caae890ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444395090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2444395090
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1803225598
Short name T523
Test name
Test status
Simulation time 5743530540 ps
CPU time 18.95 seconds
Started Jul 26 07:02:01 PM PDT 24
Finished Jul 26 07:02:20 PM PDT 24
Peak memory 200464 kb
Host smart-d8082c12-cab6-4ed8-bd98-262198e92e48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803225598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1803225598
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.423270879
Short name T348
Test name
Test status
Simulation time 332833524 ps
CPU time 2.34 seconds
Started Jul 26 07:01:53 PM PDT 24
Finished Jul 26 07:01:55 PM PDT 24
Peak memory 208248 kb
Host smart-29235e6c-87c6-490c-9969-5485bab51640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423270879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.423270879
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3112877779
Short name T362
Test name
Test status
Simulation time 173908270 ps
CPU time 1.16 seconds
Started Jul 26 07:01:57 PM PDT 24
Finished Jul 26 07:01:58 PM PDT 24
Peak memory 200076 kb
Host smart-af8a0600-0d25-443e-b42c-e577c1f5ad11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112877779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3112877779
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1074084109
Short name T490
Test name
Test status
Simulation time 78579079 ps
CPU time 0.77 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 199880 kb
Host smart-1d56ac5a-4d42-4828-bc17-a1d4d487865a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074084109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1074084109
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2571400819
Short name T480
Test name
Test status
Simulation time 1901873735 ps
CPU time 7.85 seconds
Started Jul 26 07:02:01 PM PDT 24
Finished Jul 26 07:02:09 PM PDT 24
Peak memory 217824 kb
Host smart-1368e094-6872-4513-8c3c-cd983850dfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571400819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2571400819
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3435889356
Short name T495
Test name
Test status
Simulation time 243748790 ps
CPU time 1.08 seconds
Started Jul 26 07:01:53 PM PDT 24
Finished Jul 26 07:01:55 PM PDT 24
Peak memory 217420 kb
Host smart-3373c456-81f2-49f0-8470-1b9613886d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435889356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3435889356
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3557880153
Short name T21
Test name
Test status
Simulation time 192784679 ps
CPU time 0.94 seconds
Started Jul 26 07:01:43 PM PDT 24
Finished Jul 26 07:01:44 PM PDT 24
Peak memory 199736 kb
Host smart-64b0cf82-9f74-4c88-b887-a88d992dc4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557880153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3557880153
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2433875641
Short name T331
Test name
Test status
Simulation time 1014125529 ps
CPU time 5.39 seconds
Started Jul 26 07:01:47 PM PDT 24
Finished Jul 26 07:01:53 PM PDT 24
Peak memory 200288 kb
Host smart-0a0817fe-608d-44fc-b5b3-1aa8870751e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433875641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2433875641
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1905611685
Short name T162
Test name
Test status
Simulation time 181248474 ps
CPU time 1.26 seconds
Started Jul 26 07:01:54 PM PDT 24
Finished Jul 26 07:01:55 PM PDT 24
Peak memory 200048 kb
Host smart-d5ed33b0-8b00-461d-be0e-ac8e5dfcb95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905611685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1905611685
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.4097635117
Short name T396
Test name
Test status
Simulation time 117235592 ps
CPU time 1.2 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 200256 kb
Host smart-7feb0ba0-169b-4305-a0cf-6a7981538f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097635117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.4097635117
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1639802331
Short name T338
Test name
Test status
Simulation time 9522474019 ps
CPU time 34.97 seconds
Started Jul 26 07:02:01 PM PDT 24
Finished Jul 26 07:02:36 PM PDT 24
Peak memory 208648 kb
Host smart-ae4c73fe-d165-4813-8037-85627efff243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639802331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1639802331
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2029509048
Short name T286
Test name
Test status
Simulation time 118497621 ps
CPU time 1.56 seconds
Started Jul 26 07:01:47 PM PDT 24
Finished Jul 26 07:01:48 PM PDT 24
Peak memory 208232 kb
Host smart-2e48d51a-846a-468c-9e8e-15da60868acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029509048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2029509048
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.363526658
Short name T429
Test name
Test status
Simulation time 253819003 ps
CPU time 1.36 seconds
Started Jul 26 07:01:54 PM PDT 24
Finished Jul 26 07:01:55 PM PDT 24
Peak memory 200280 kb
Host smart-1c3dda3e-1a45-457c-a51a-4dca78c121fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363526658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.363526658
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1573024205
Short name T459
Test name
Test status
Simulation time 67985575 ps
CPU time 0.74 seconds
Started Jul 26 07:01:09 PM PDT 24
Finished Jul 26 07:01:10 PM PDT 24
Peak memory 199864 kb
Host smart-916cfc97-e804-47e1-87dc-c51598d659ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573024205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1573024205
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3663741177
Short name T52
Test name
Test status
Simulation time 1230797255 ps
CPU time 5.7 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:23 PM PDT 24
Peak memory 221808 kb
Host smart-5c88870e-1e06-450b-98b0-3b03d2dd5da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663741177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3663741177
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3722287778
Short name T249
Test name
Test status
Simulation time 245080803 ps
CPU time 1.09 seconds
Started Jul 26 07:01:02 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 217432 kb
Host smart-0e7710a4-62d3-467b-97f3-f9c353bd3a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722287778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3722287778
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.4015644661
Short name T236
Test name
Test status
Simulation time 180664212 ps
CPU time 0.89 seconds
Started Jul 26 07:01:05 PM PDT 24
Finished Jul 26 07:01:06 PM PDT 24
Peak memory 199796 kb
Host smart-28afa6f1-1e38-4a92-a3cd-0bd3df2b0a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015644661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.4015644661
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2614838562
Short name T492
Test name
Test status
Simulation time 1427093533 ps
CPU time 6.04 seconds
Started Jul 26 07:01:09 PM PDT 24
Finished Jul 26 07:01:15 PM PDT 24
Peak memory 200348 kb
Host smart-0c70e299-20ed-4ffe-a233-4beb15d833c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614838562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2614838562
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2546784043
Short name T208
Test name
Test status
Simulation time 166572395 ps
CPU time 1.26 seconds
Started Jul 26 07:01:02 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 200088 kb
Host smart-651f0a1b-e89c-49c1-a55f-007d603ada6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546784043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2546784043
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2347917853
Short name T172
Test name
Test status
Simulation time 190902629 ps
CPU time 1.48 seconds
Started Jul 26 07:01:16 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 200260 kb
Host smart-c06710aa-3cea-44a1-beaf-f5d3aab94e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347917853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2347917853
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2855673248
Short name T357
Test name
Test status
Simulation time 2296805540 ps
CPU time 9.24 seconds
Started Jul 26 07:01:01 PM PDT 24
Finished Jul 26 07:01:10 PM PDT 24
Peak memory 208632 kb
Host smart-3a1355b1-e938-4671-92cb-ac38f0fe14ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855673248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2855673248
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3933126214
Short name T324
Test name
Test status
Simulation time 383816886 ps
CPU time 2.39 seconds
Started Jul 26 07:01:03 PM PDT 24
Finished Jul 26 07:01:06 PM PDT 24
Peak memory 200052 kb
Host smart-2b072e36-2a9c-4ad3-9d19-dcc162680a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933126214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3933126214
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3848122477
Short name T379
Test name
Test status
Simulation time 181241968 ps
CPU time 1.2 seconds
Started Jul 26 07:01:08 PM PDT 24
Finished Jul 26 07:01:10 PM PDT 24
Peak memory 200088 kb
Host smart-4f0ab065-be3a-4746-a4c1-f0bdda0c7615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848122477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3848122477
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.902612038
Short name T504
Test name
Test status
Simulation time 63988137 ps
CPU time 0.77 seconds
Started Jul 26 07:02:02 PM PDT 24
Finished Jul 26 07:02:03 PM PDT 24
Peak memory 199848 kb
Host smart-9ebc6c0d-f7e4-4052-b14e-e64a6c18696e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902612038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.902612038
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2882230780
Short name T464
Test name
Test status
Simulation time 2336420198 ps
CPU time 8.14 seconds
Started Jul 26 07:02:01 PM PDT 24
Finished Jul 26 07:02:10 PM PDT 24
Peak memory 217848 kb
Host smart-4e7fd006-328e-403d-abcf-cfbeea875b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882230780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2882230780
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2561788736
Short name T258
Test name
Test status
Simulation time 243779909 ps
CPU time 1.07 seconds
Started Jul 26 07:01:57 PM PDT 24
Finished Jul 26 07:01:58 PM PDT 24
Peak memory 217508 kb
Host smart-4d7e9889-671a-4279-8e93-d7cf665a2e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561788736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2561788736
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2762604522
Short name T485
Test name
Test status
Simulation time 187773868 ps
CPU time 0.91 seconds
Started Jul 26 07:01:49 PM PDT 24
Finished Jul 26 07:01:50 PM PDT 24
Peak memory 199852 kb
Host smart-fd182f1f-061e-43a1-9d9f-dbe375533ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762604522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2762604522
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.396853402
Short name T527
Test name
Test status
Simulation time 1267086521 ps
CPU time 4.86 seconds
Started Jul 26 07:02:00 PM PDT 24
Finished Jul 26 07:02:05 PM PDT 24
Peak memory 200308 kb
Host smart-fb4c9ede-06cc-4a62-875f-19cb6037c9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396853402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.396853402
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.675470036
Short name T463
Test name
Test status
Simulation time 107652287 ps
CPU time 0.97 seconds
Started Jul 26 07:01:41 PM PDT 24
Finished Jul 26 07:01:42 PM PDT 24
Peak memory 200104 kb
Host smart-58458fce-a404-43a2-a0fa-99e8dfdf2b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675470036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.675470036
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3145926362
Short name T73
Test name
Test status
Simulation time 119785493 ps
CPU time 1.15 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 200276 kb
Host smart-d7cb8b64-3df0-439c-9e73-811150cbc677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145926362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3145926362
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2714985686
Short name T516
Test name
Test status
Simulation time 3888728873 ps
CPU time 16.76 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:26 PM PDT 24
Peak memory 208564 kb
Host smart-cc810740-0786-4fb5-be80-52777aa19b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714985686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2714985686
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2315111001
Short name T413
Test name
Test status
Simulation time 137747574 ps
CPU time 1.62 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 200160 kb
Host smart-64b9f780-8cc0-4238-b8cf-c95b4206bc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315111001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2315111001
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3602364874
Short name T145
Test name
Test status
Simulation time 128122266 ps
CPU time 0.95 seconds
Started Jul 26 07:01:40 PM PDT 24
Finished Jul 26 07:01:41 PM PDT 24
Peak memory 200112 kb
Host smart-bb3e041c-9e41-48be-afc9-14ee7d833c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602364874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3602364874
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1029002859
Short name T337
Test name
Test status
Simulation time 69899780 ps
CPU time 0.78 seconds
Started Jul 26 07:01:51 PM PDT 24
Finished Jul 26 07:01:52 PM PDT 24
Peak memory 199840 kb
Host smart-616b6c28-4b99-4ece-ab28-e2f66f40020a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029002859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1029002859
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.994478664
Short name T39
Test name
Test status
Simulation time 2370768012 ps
CPU time 7.92 seconds
Started Jul 26 07:01:59 PM PDT 24
Finished Jul 26 07:02:07 PM PDT 24
Peak memory 217676 kb
Host smart-aa139af6-53cf-467f-980b-b1901aad30ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994478664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.994478664
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.463702103
Short name T255
Test name
Test status
Simulation time 244244731 ps
CPU time 1.07 seconds
Started Jul 26 07:01:46 PM PDT 24
Finished Jul 26 07:01:47 PM PDT 24
Peak memory 217408 kb
Host smart-a485a5a3-782f-4587-a352-79a3079a6cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463702103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.463702103
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2893608548
Short name T18
Test name
Test status
Simulation time 190743964 ps
CPU time 0.92 seconds
Started Jul 26 07:02:07 PM PDT 24
Finished Jul 26 07:02:18 PM PDT 24
Peak memory 199964 kb
Host smart-f18d23e2-7cb8-48f4-aaa3-a8008b7670c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893608548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2893608548
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2092605076
Short name T528
Test name
Test status
Simulation time 1930172232 ps
CPU time 7.13 seconds
Started Jul 26 07:01:51 PM PDT 24
Finished Jul 26 07:01:58 PM PDT 24
Peak memory 200308 kb
Host smart-6d2baaaf-8859-472a-aad6-5fd50a995259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092605076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2092605076
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.803410454
Short name T267
Test name
Test status
Simulation time 96356039 ps
CPU time 1.02 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 199920 kb
Host smart-f9e18c37-081a-44eb-86c0-d722726ac172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803410454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.803410454
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3987902227
Short name T380
Test name
Test status
Simulation time 191190888 ps
CPU time 1.28 seconds
Started Jul 26 07:01:58 PM PDT 24
Finished Jul 26 07:01:59 PM PDT 24
Peak memory 200236 kb
Host smart-ed32a52d-e863-4e70-b5e5-6eb7b9c258f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987902227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3987902227
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1768024113
Short name T157
Test name
Test status
Simulation time 285113835 ps
CPU time 1.73 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:57 PM PDT 24
Peak memory 200076 kb
Host smart-e36ec09c-22ab-4e96-ada1-4984ef4a1530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768024113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1768024113
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2794239256
Short name T171
Test name
Test status
Simulation time 479027054 ps
CPU time 2.46 seconds
Started Jul 26 07:02:07 PM PDT 24
Finished Jul 26 07:02:09 PM PDT 24
Peak memory 208344 kb
Host smart-60f963b7-5bfb-4f89-ab60-6aa759d2b1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794239256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2794239256
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2020409053
Short name T343
Test name
Test status
Simulation time 120820090 ps
CPU time 1.17 seconds
Started Jul 26 07:01:57 PM PDT 24
Finished Jul 26 07:01:59 PM PDT 24
Peak memory 200156 kb
Host smart-7bdb0f5b-9638-4d34-bed4-cc89fcd5e66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020409053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2020409053
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1716286690
Short name T280
Test name
Test status
Simulation time 85898378 ps
CPU time 0.86 seconds
Started Jul 26 07:02:06 PM PDT 24
Finished Jul 26 07:02:07 PM PDT 24
Peak memory 199960 kb
Host smart-a8ceae04-f4f0-41ec-a460-06e680b153ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716286690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1716286690
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1548341738
Short name T51
Test name
Test status
Simulation time 1229754302 ps
CPU time 5.83 seconds
Started Jul 26 07:01:56 PM PDT 24
Finished Jul 26 07:02:02 PM PDT 24
Peak memory 217700 kb
Host smart-d38835b7-c9a9-467c-a32e-e7ce1ac43bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548341738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1548341738
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1792065497
Short name T403
Test name
Test status
Simulation time 245291498 ps
CPU time 1.1 seconds
Started Jul 26 07:01:58 PM PDT 24
Finished Jul 26 07:02:00 PM PDT 24
Peak memory 217560 kb
Host smart-272c320a-61d5-46f3-9464-1df5b8761949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792065497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1792065497
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2257838696
Short name T243
Test name
Test status
Simulation time 199667086 ps
CPU time 0.86 seconds
Started Jul 26 07:02:05 PM PDT 24
Finished Jul 26 07:02:06 PM PDT 24
Peak memory 199844 kb
Host smart-0879f51d-5f13-44b3-8bf2-064324d35cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257838696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2257838696
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3682438540
Short name T261
Test name
Test status
Simulation time 1967840141 ps
CPU time 6.8 seconds
Started Jul 26 07:01:56 PM PDT 24
Finished Jul 26 07:02:03 PM PDT 24
Peak memory 200340 kb
Host smart-0363816c-4097-4ecd-bfa6-f0151e6683ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682438540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3682438540
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.556672625
Short name T289
Test name
Test status
Simulation time 106994724 ps
CPU time 0.97 seconds
Started Jul 26 07:02:06 PM PDT 24
Finished Jul 26 07:02:08 PM PDT 24
Peak memory 200072 kb
Host smart-51e03348-de30-4617-86f9-f85db0aa6cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556672625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.556672625
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.371010161
Short name T128
Test name
Test status
Simulation time 116655516 ps
CPU time 1.2 seconds
Started Jul 26 07:01:50 PM PDT 24
Finished Jul 26 07:01:51 PM PDT 24
Peak memory 200324 kb
Host smart-4a55d1b1-5477-4c2a-9de0-4d4cad83ceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371010161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.371010161
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2311488099
Short name T367
Test name
Test status
Simulation time 8887941452 ps
CPU time 30.74 seconds
Started Jul 26 07:01:54 PM PDT 24
Finished Jul 26 07:02:25 PM PDT 24
Peak memory 200372 kb
Host smart-f79ceda8-3cca-45cd-8a4f-5132147decc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311488099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2311488099
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4005185522
Short name T390
Test name
Test status
Simulation time 123774937 ps
CPU time 1.51 seconds
Started Jul 26 07:02:00 PM PDT 24
Finished Jul 26 07:02:01 PM PDT 24
Peak memory 200124 kb
Host smart-897249b0-ad0e-4050-bd7e-03dd7699268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005185522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4005185522
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1940309713
Short name T423
Test name
Test status
Simulation time 81398159 ps
CPU time 0.84 seconds
Started Jul 26 07:01:54 PM PDT 24
Finished Jul 26 07:01:55 PM PDT 24
Peak memory 200012 kb
Host smart-48098b04-d7dc-4183-8b8a-1f53bcb9da88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940309713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1940309713
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.543665787
Short name T344
Test name
Test status
Simulation time 68950813 ps
CPU time 0.79 seconds
Started Jul 26 07:01:50 PM PDT 24
Finished Jul 26 07:01:51 PM PDT 24
Peak memory 199880 kb
Host smart-fcde5d43-a19b-4299-8320-93ecaa2c70a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543665787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.543665787
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.184549541
Short name T507
Test name
Test status
Simulation time 2341834431 ps
CPU time 7.82 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:02:03 PM PDT 24
Peak memory 217092 kb
Host smart-26e76adb-1095-4e39-aaca-663a3f7853c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184549541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.184549541
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3135974321
Short name T201
Test name
Test status
Simulation time 245907599 ps
CPU time 1.02 seconds
Started Jul 26 07:01:52 PM PDT 24
Finished Jul 26 07:01:53 PM PDT 24
Peak memory 217404 kb
Host smart-0d395232-187a-4f12-bad9-35b6e665d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135974321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3135974321
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3727336442
Short name T23
Test name
Test status
Simulation time 193903267 ps
CPU time 0.85 seconds
Started Jul 26 07:01:57 PM PDT 24
Finished Jul 26 07:01:58 PM PDT 24
Peak memory 199880 kb
Host smart-69a5332c-5426-47f9-8139-329fa20906bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727336442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3727336442
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1471337349
Short name T342
Test name
Test status
Simulation time 1459631494 ps
CPU time 5.94 seconds
Started Jul 26 07:01:54 PM PDT 24
Finished Jul 26 07:02:00 PM PDT 24
Peak memory 200308 kb
Host smart-6f4e1234-ada9-4975-a711-f2a2dbd418d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471337349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1471337349
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3296627728
Short name T170
Test name
Test status
Simulation time 184333171 ps
CPU time 1.14 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 200076 kb
Host smart-bee90c1d-03a5-461e-bd0c-e4cf8239a4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296627728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3296627728
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3738052059
Short name T438
Test name
Test status
Simulation time 122574645 ps
CPU time 1.3 seconds
Started Jul 26 07:02:02 PM PDT 24
Finished Jul 26 07:02:04 PM PDT 24
Peak memory 200276 kb
Host smart-ba8016a5-afde-4fef-a69e-de54f4aabf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738052059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3738052059
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2825290512
Short name T212
Test name
Test status
Simulation time 163701503 ps
CPU time 1.06 seconds
Started Jul 26 07:02:10 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 200048 kb
Host smart-369775e9-17d9-4617-9940-0e6b6708ec8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825290512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2825290512
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3157774364
Short name T58
Test name
Test status
Simulation time 244415345 ps
CPU time 1.33 seconds
Started Jul 26 07:01:54 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 200052 kb
Host smart-cd137ab7-0942-4bd1-9180-7094ce176867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157774364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3157774364
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.349859576
Short name T291
Test name
Test status
Simulation time 63945546 ps
CPU time 0.74 seconds
Started Jul 26 07:01:57 PM PDT 24
Finished Jul 26 07:01:58 PM PDT 24
Peak memory 199876 kb
Host smart-fb686769-24a5-49e3-99e5-64e37caebeb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349859576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.349859576
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1495190666
Short name T508
Test name
Test status
Simulation time 1881500600 ps
CPU time 7.34 seconds
Started Jul 26 07:01:59 PM PDT 24
Finished Jul 26 07:02:07 PM PDT 24
Peak memory 217724 kb
Host smart-301a2564-d1a7-4606-95ef-5574bdae0573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495190666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1495190666
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1851448320
Short name T84
Test name
Test status
Simulation time 245032012 ps
CPU time 1.08 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 217424 kb
Host smart-d1df634c-1d23-42bb-ba6f-2bcdf56c0c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851448320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1851448320
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2399698297
Short name T19
Test name
Test status
Simulation time 183830731 ps
CPU time 0.95 seconds
Started Jul 26 07:01:52 PM PDT 24
Finished Jul 26 07:01:53 PM PDT 24
Peak memory 199864 kb
Host smart-e604d0d8-48fc-419d-8e06-62f1f3f8ed5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399698297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2399698297
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.209393731
Short name T165
Test name
Test status
Simulation time 1306954592 ps
CPU time 5.54 seconds
Started Jul 26 07:01:49 PM PDT 24
Finished Jul 26 07:01:55 PM PDT 24
Peak memory 200344 kb
Host smart-2d40ab9e-a2af-4775-bdf1-620f86835d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209393731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.209393731
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.364417182
Short name T300
Test name
Test status
Simulation time 103744254 ps
CPU time 1.01 seconds
Started Jul 26 07:01:51 PM PDT 24
Finished Jul 26 07:01:52 PM PDT 24
Peak memory 200052 kb
Host smart-ca54d3f4-1d4b-49d2-8b03-1f5bbe9f38ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364417182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.364417182
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3229731429
Short name T524
Test name
Test status
Simulation time 123788476 ps
CPU time 1.22 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:57 PM PDT 24
Peak memory 200284 kb
Host smart-e5329967-30cd-4bc8-afd3-f0bee88469dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229731429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3229731429
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2701332007
Short name T537
Test name
Test status
Simulation time 915656624 ps
CPU time 3.79 seconds
Started Jul 26 07:02:01 PM PDT 24
Finished Jul 26 07:02:05 PM PDT 24
Peak memory 200248 kb
Host smart-d87993b1-3d81-4744-a2e4-f6fc373d13e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701332007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2701332007
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3457838375
Short name T226
Test name
Test status
Simulation time 321150092 ps
CPU time 2.24 seconds
Started Jul 26 07:01:54 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 200404 kb
Host smart-47d06fab-d465-43c9-bf7b-2ad94fc897af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457838375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3457838375
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.402297540
Short name T25
Test name
Test status
Simulation time 159944554 ps
CPU time 1.16 seconds
Started Jul 26 07:01:50 PM PDT 24
Finished Jul 26 07:01:51 PM PDT 24
Peak memory 199992 kb
Host smart-95c11f1b-63d1-4160-8c24-8c2567b03976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402297540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.402297540
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2187107391
Short name T160
Test name
Test status
Simulation time 70611102 ps
CPU time 0.77 seconds
Started Jul 26 07:02:07 PM PDT 24
Finished Jul 26 07:02:08 PM PDT 24
Peak memory 199928 kb
Host smart-b5c436fb-8e7e-4151-9a4d-7a06e03b79a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187107391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2187107391
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.977610713
Short name T43
Test name
Test status
Simulation time 1224827485 ps
CPU time 5.81 seconds
Started Jul 26 07:01:52 PM PDT 24
Finished Jul 26 07:01:58 PM PDT 24
Peak memory 221680 kb
Host smart-2fa57387-ed80-41a9-8d73-5c8d3dd16a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977610713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.977610713
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2342108055
Short name T322
Test name
Test status
Simulation time 244329772 ps
CPU time 1.04 seconds
Started Jul 26 07:01:57 PM PDT 24
Finished Jul 26 07:01:59 PM PDT 24
Peak memory 217408 kb
Host smart-a47934ba-0fea-441f-b58b-586112a729df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342108055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2342108055
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1298503615
Short name T384
Test name
Test status
Simulation time 194748440 ps
CPU time 0.88 seconds
Started Jul 26 07:01:51 PM PDT 24
Finished Jul 26 07:01:52 PM PDT 24
Peak memory 199904 kb
Host smart-2b425cd0-1390-45d7-96f6-e5fbdd0f6792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298503615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1298503615
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2369888835
Short name T123
Test name
Test status
Simulation time 1489093160 ps
CPU time 5.52 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:02:01 PM PDT 24
Peak memory 200252 kb
Host smart-fdab4aaa-2faf-4556-a69b-0f1bc4c3802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369888835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2369888835
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1829776308
Short name T153
Test name
Test status
Simulation time 167662515 ps
CPU time 1.23 seconds
Started Jul 26 07:02:02 PM PDT 24
Finished Jul 26 07:02:04 PM PDT 24
Peak memory 200024 kb
Host smart-08c08438-0f80-4065-adaa-3f54ab26a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829776308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1829776308
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1115282266
Short name T228
Test name
Test status
Simulation time 188575869 ps
CPU time 1.29 seconds
Started Jul 26 07:01:53 PM PDT 24
Finished Jul 26 07:01:54 PM PDT 24
Peak memory 200272 kb
Host smart-ca38ab52-d40e-49be-a71a-3782f007fc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115282266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1115282266
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.4048169665
Short name T314
Test name
Test status
Simulation time 232440429 ps
CPU time 1.44 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 200228 kb
Host smart-861ee33d-dc7c-4398-8d95-021d9dd5bbaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048169665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.4048169665
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4283539866
Short name T175
Test name
Test status
Simulation time 150443359 ps
CPU time 1.83 seconds
Started Jul 26 07:01:56 PM PDT 24
Finished Jul 26 07:01:58 PM PDT 24
Peak memory 200068 kb
Host smart-55134002-e924-4d75-9545-c522e3c38f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283539866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4283539866
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2682125788
Short name T220
Test name
Test status
Simulation time 81457633 ps
CPU time 0.85 seconds
Started Jul 26 07:01:47 PM PDT 24
Finished Jul 26 07:01:48 PM PDT 24
Peak memory 200088 kb
Host smart-ad5bcbb7-e056-4227-af03-e2d6cbd4209c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682125788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2682125788
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2173131558
Short name T323
Test name
Test status
Simulation time 75414240 ps
CPU time 0.79 seconds
Started Jul 26 07:01:58 PM PDT 24
Finished Jul 26 07:01:59 PM PDT 24
Peak memory 199872 kb
Host smart-31574145-66ef-460b-abba-0b10d69d4ff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173131558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2173131558
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4046520453
Short name T54
Test name
Test status
Simulation time 1227032482 ps
CPU time 5.21 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:02:00 PM PDT 24
Peak memory 217612 kb
Host smart-e8f1f0c3-8767-4083-9439-513bbca2f4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046520453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4046520453
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.284361771
Short name T444
Test name
Test status
Simulation time 244533047 ps
CPU time 1.09 seconds
Started Jul 26 07:02:07 PM PDT 24
Finished Jul 26 07:02:08 PM PDT 24
Peak memory 217440 kb
Host smart-af6399fa-3233-4c4e-a949-1a4b5d06f0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284361771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.284361771
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.987536319
Short name T274
Test name
Test status
Simulation time 184574510 ps
CPU time 0.87 seconds
Started Jul 26 07:02:13 PM PDT 24
Finished Jul 26 07:02:14 PM PDT 24
Peak memory 199916 kb
Host smart-b99c902b-f34c-44f2-9015-6204e8c122ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987536319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.987536319
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2982614834
Short name T486
Test name
Test status
Simulation time 2236264680 ps
CPU time 7.52 seconds
Started Jul 26 07:02:11 PM PDT 24
Finished Jul 26 07:02:24 PM PDT 24
Peak memory 200392 kb
Host smart-edcf685e-0dbe-424a-b840-f9196b01ef20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982614834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2982614834
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2475868780
Short name T502
Test name
Test status
Simulation time 102583058 ps
CPU time 0.99 seconds
Started Jul 26 07:02:05 PM PDT 24
Finished Jul 26 07:02:06 PM PDT 24
Peak memory 200072 kb
Host smart-d6c4a4e0-b00d-45d6-b555-fdbc362b0121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475868780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2475868780
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.79862420
Short name T292
Test name
Test status
Simulation time 184695678 ps
CPU time 1.3 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:10 PM PDT 24
Peak memory 200256 kb
Host smart-ed61e488-b310-48d5-abeb-680424799ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79862420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.79862420
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1754312499
Short name T375
Test name
Test status
Simulation time 16148202765 ps
CPU time 65.38 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:03:17 PM PDT 24
Peak memory 208620 kb
Host smart-df63562a-3bf2-4774-b8d0-55a7cfeafa74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754312499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1754312499
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.219638182
Short name T283
Test name
Test status
Simulation time 357110998 ps
CPU time 2.02 seconds
Started Jul 26 07:02:05 PM PDT 24
Finished Jul 26 07:02:07 PM PDT 24
Peak memory 200028 kb
Host smart-3343cbc6-1c89-4279-80fc-1bcfe6dbf09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219638182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.219638182
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2243062974
Short name T213
Test name
Test status
Simulation time 73328748 ps
CPU time 0.82 seconds
Started Jul 26 07:02:10 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 199988 kb
Host smart-baaf4ab3-c30c-45fe-9f28-4abc8170758c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243062974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2243062974
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3226974230
Short name T281
Test name
Test status
Simulation time 68487886 ps
CPU time 0.78 seconds
Started Jul 26 07:01:55 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 199792 kb
Host smart-83f84198-6a33-4da7-aee9-522d5e90b118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226974230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3226974230
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3088519370
Short name T65
Test name
Test status
Simulation time 1891621829 ps
CPU time 6.78 seconds
Started Jul 26 07:02:10 PM PDT 24
Finished Jul 26 07:02:17 PM PDT 24
Peak memory 217748 kb
Host smart-2673d7c7-be7a-41bd-8bd9-a351ceb318b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088519370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3088519370
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2511298063
Short name T372
Test name
Test status
Simulation time 243447014 ps
CPU time 1.18 seconds
Started Jul 26 07:02:01 PM PDT 24
Finished Jul 26 07:02:02 PM PDT 24
Peak memory 217420 kb
Host smart-5deafa88-492d-42a2-9fb3-61b6e59241eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511298063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2511298063
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2651704690
Short name T276
Test name
Test status
Simulation time 71896907 ps
CPU time 0.74 seconds
Started Jul 26 07:02:08 PM PDT 24
Finished Jul 26 07:02:08 PM PDT 24
Peak memory 199848 kb
Host smart-81e3f2bd-4378-4136-a232-8f7e65b2ba78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651704690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2651704690
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1163202160
Short name T542
Test name
Test status
Simulation time 2069555061 ps
CPU time 7.49 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:16 PM PDT 24
Peak memory 200340 kb
Host smart-c8c1981d-6de1-4428-9538-6e16b9af1b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163202160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1163202160
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3831918568
Short name T143
Test name
Test status
Simulation time 104363332 ps
CPU time 1.02 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 200064 kb
Host smart-65e0cc70-5062-4e61-abcf-465e2fa9fab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831918568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3831918568
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1282745905
Short name T42
Test name
Test status
Simulation time 192781060 ps
CPU time 1.42 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 200236 kb
Host smart-720f9a21-9c3f-4353-839e-33b8d960aa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282745905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1282745905
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3285564295
Short name T27
Test name
Test status
Simulation time 7625720493 ps
CPU time 34 seconds
Started Jul 26 07:01:56 PM PDT 24
Finished Jul 26 07:02:30 PM PDT 24
Peak memory 208576 kb
Host smart-9fcd08ce-ecb3-4622-af83-fa357a5dedd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285564295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3285564295
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1376807486
Short name T142
Test name
Test status
Simulation time 376079038 ps
CPU time 2.38 seconds
Started Jul 26 07:01:57 PM PDT 24
Finished Jul 26 07:01:59 PM PDT 24
Peak memory 200084 kb
Host smart-53b60f97-0491-4062-884f-10887ea9a783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376807486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1376807486
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1469459248
Short name T499
Test name
Test status
Simulation time 112108131 ps
CPU time 0.99 seconds
Started Jul 26 07:02:10 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 200064 kb
Host smart-9416705c-2ca9-4990-ab55-68da11a48b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469459248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1469459248
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3465111923
Short name T547
Test name
Test status
Simulation time 58488373 ps
CPU time 0.74 seconds
Started Jul 26 07:02:07 PM PDT 24
Finished Jul 26 07:02:08 PM PDT 24
Peak memory 199872 kb
Host smart-e1458384-9d69-40dd-aa94-014b21600902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465111923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3465111923
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1437943077
Short name T177
Test name
Test status
Simulation time 2155466109 ps
CPU time 7.85 seconds
Started Jul 26 07:02:10 PM PDT 24
Finished Jul 26 07:02:18 PM PDT 24
Peak memory 217784 kb
Host smart-ecc30f98-decd-4d98-bc8d-3778e7488b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437943077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1437943077
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1945738192
Short name T389
Test name
Test status
Simulation time 244442500 ps
CPU time 1.1 seconds
Started Jul 26 07:01:56 PM PDT 24
Finished Jul 26 07:01:57 PM PDT 24
Peak memory 217412 kb
Host smart-33b3025a-5495-4a88-9e04-90c4e4ee7bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945738192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1945738192
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1028310747
Short name T287
Test name
Test status
Simulation time 227280074 ps
CPU time 0.93 seconds
Started Jul 26 07:02:14 PM PDT 24
Finished Jul 26 07:02:15 PM PDT 24
Peak memory 199952 kb
Host smart-f7b26063-320b-4fe3-b1cf-0990381b0bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028310747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1028310747
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.88016570
Short name T125
Test name
Test status
Simulation time 1895579351 ps
CPU time 6.94 seconds
Started Jul 26 07:02:14 PM PDT 24
Finished Jul 26 07:02:21 PM PDT 24
Peak memory 200336 kb
Host smart-0c6cbfcc-842a-4bca-ba63-b556cb16bf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88016570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.88016570
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2876609850
Short name T393
Test name
Test status
Simulation time 146823078 ps
CPU time 1.09 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 200132 kb
Host smart-41dba32a-bed8-4a48-a7c3-5fc2b72c05f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876609850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2876609850
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2540085943
Short name T151
Test name
Test status
Simulation time 113941194 ps
CPU time 1.14 seconds
Started Jul 26 07:02:00 PM PDT 24
Finished Jul 26 07:02:02 PM PDT 24
Peak memory 200316 kb
Host smart-3bd79dd8-e9dc-49df-a600-876001cad275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540085943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2540085943
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2842754377
Short name T328
Test name
Test status
Simulation time 3906904657 ps
CPU time 18.77 seconds
Started Jul 26 07:02:07 PM PDT 24
Finished Jul 26 07:02:25 PM PDT 24
Peak memory 200404 kb
Host smart-801685eb-51db-4475-ab51-b3aaab5e8edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842754377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2842754377
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.351490854
Short name T168
Test name
Test status
Simulation time 346654746 ps
CPU time 2.32 seconds
Started Jul 26 07:01:56 PM PDT 24
Finished Jul 26 07:01:59 PM PDT 24
Peak memory 200108 kb
Host smart-7ab68998-6898-4a45-af24-82795e342aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351490854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.351490854
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3226899799
Short name T266
Test name
Test status
Simulation time 278234386 ps
CPU time 1.64 seconds
Started Jul 26 07:02:02 PM PDT 24
Finished Jul 26 07:02:04 PM PDT 24
Peak memory 200272 kb
Host smart-10d567c6-7cdb-4106-9bac-baca95db7253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226899799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3226899799
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1893705139
Short name T406
Test name
Test status
Simulation time 70359001 ps
CPU time 0.74 seconds
Started Jul 26 07:02:08 PM PDT 24
Finished Jul 26 07:02:09 PM PDT 24
Peak memory 199888 kb
Host smart-d5a223db-13de-4842-9b52-fb6d7d6aea9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893705139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1893705139
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2431031633
Short name T53
Test name
Test status
Simulation time 1223496697 ps
CPU time 5.88 seconds
Started Jul 26 07:02:01 PM PDT 24
Finished Jul 26 07:02:07 PM PDT 24
Peak memory 221748 kb
Host smart-730524ad-6a32-45f8-a603-c78c917a14fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431031633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2431031633
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.138224045
Short name T533
Test name
Test status
Simulation time 244000293 ps
CPU time 1.08 seconds
Started Jul 26 07:02:02 PM PDT 24
Finished Jul 26 07:02:03 PM PDT 24
Peak memory 217752 kb
Host smart-a370a655-d4de-4acb-944c-de428cb529ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138224045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.138224045
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2927470253
Short name T385
Test name
Test status
Simulation time 144155665 ps
CPU time 0.82 seconds
Started Jul 26 07:02:07 PM PDT 24
Finished Jul 26 07:02:07 PM PDT 24
Peak memory 200180 kb
Host smart-2be32ace-f0ef-4433-a7be-fbb77947739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927470253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2927470253
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3312862126
Short name T467
Test name
Test status
Simulation time 1005076727 ps
CPU time 5.06 seconds
Started Jul 26 07:02:04 PM PDT 24
Finished Jul 26 07:02:09 PM PDT 24
Peak memory 200608 kb
Host smart-61539e0e-3949-448a-8600-a0a63f6595b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312862126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3312862126
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1556492938
Short name T369
Test name
Test status
Simulation time 158327710 ps
CPU time 1.1 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:10 PM PDT 24
Peak memory 200016 kb
Host smart-f8b55af8-4ba7-465e-9349-c52c230e08e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556492938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1556492938
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.37226386
Short name T235
Test name
Test status
Simulation time 255997227 ps
CPU time 1.44 seconds
Started Jul 26 07:01:58 PM PDT 24
Finished Jul 26 07:01:59 PM PDT 24
Peak memory 200296 kb
Host smart-4747b3ce-af9a-453b-956a-c54d2ba0bf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37226386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.37226386
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1738587249
Short name T242
Test name
Test status
Simulation time 3000517944 ps
CPU time 12.99 seconds
Started Jul 26 07:02:01 PM PDT 24
Finished Jul 26 07:02:14 PM PDT 24
Peak memory 208656 kb
Host smart-8d1d4db7-5642-438a-af08-c411fe212fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738587249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1738587249
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2552993669
Short name T67
Test name
Test status
Simulation time 309232550 ps
CPU time 1.99 seconds
Started Jul 26 07:02:05 PM PDT 24
Finished Jul 26 07:02:07 PM PDT 24
Peak memory 200088 kb
Host smart-1a05e242-409d-4c8a-b266-74cb8dd0f849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552993669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2552993669
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3525267449
Short name T290
Test name
Test status
Simulation time 155908468 ps
CPU time 1.28 seconds
Started Jul 26 07:02:02 PM PDT 24
Finished Jul 26 07:02:03 PM PDT 24
Peak memory 200296 kb
Host smart-8cc88638-8938-4517-994d-e483cb63d26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525267449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3525267449
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2599367702
Short name T538
Test name
Test status
Simulation time 58077937 ps
CPU time 0.75 seconds
Started Jul 26 07:01:15 PM PDT 24
Finished Jul 26 07:01:16 PM PDT 24
Peak memory 199900 kb
Host smart-3ab3fad4-c543-4717-93c1-70d5abac02bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599367702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2599367702
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2871688655
Short name T373
Test name
Test status
Simulation time 1892887519 ps
CPU time 7.55 seconds
Started Jul 26 07:01:04 PM PDT 24
Finished Jul 26 07:01:12 PM PDT 24
Peak memory 217704 kb
Host smart-0607b52d-a546-433c-bb19-112347c08cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871688655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2871688655
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1401125841
Short name T381
Test name
Test status
Simulation time 244900735 ps
CPU time 1.02 seconds
Started Jul 26 07:01:16 PM PDT 24
Finished Jul 26 07:01:17 PM PDT 24
Peak memory 217428 kb
Host smart-05736d1b-809f-47b3-82ab-27198ae6c929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401125841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1401125841
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.868777267
Short name T450
Test name
Test status
Simulation time 147030832 ps
CPU time 0.87 seconds
Started Jul 26 07:01:03 PM PDT 24
Finished Jul 26 07:01:04 PM PDT 24
Peak memory 199884 kb
Host smart-233b760a-7936-4239-aa27-42d90915dcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868777267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.868777267
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1966283894
Short name T443
Test name
Test status
Simulation time 757363328 ps
CPU time 3.66 seconds
Started Jul 26 07:01:07 PM PDT 24
Finished Jul 26 07:01:11 PM PDT 24
Peak memory 200464 kb
Host smart-71861761-501f-4366-9876-52457045a53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966283894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1966283894
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3201574791
Short name T81
Test name
Test status
Simulation time 16513576373 ps
CPU time 27.78 seconds
Started Jul 26 07:01:28 PM PDT 24
Finished Jul 26 07:01:55 PM PDT 24
Peak memory 217064 kb
Host smart-74de83b6-25f6-4445-9d52-907995dd93ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201574791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3201574791
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1409266374
Short name T472
Test name
Test status
Simulation time 160539573 ps
CPU time 1.19 seconds
Started Jul 26 07:01:01 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 200364 kb
Host smart-d56ef496-01ba-4239-bcd6-73702a9635b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409266374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1409266374
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1301212953
Short name T195
Test name
Test status
Simulation time 253484429 ps
CPU time 1.54 seconds
Started Jul 26 07:01:05 PM PDT 24
Finished Jul 26 07:01:07 PM PDT 24
Peak memory 200196 kb
Host smart-4408cd63-192f-4754-ac8e-7ef161a65826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301212953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1301212953
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3716186233
Short name T541
Test name
Test status
Simulation time 7087339920 ps
CPU time 25.75 seconds
Started Jul 26 07:01:08 PM PDT 24
Finished Jul 26 07:01:33 PM PDT 24
Peak memory 200400 kb
Host smart-d0ee7206-4e5a-4b5c-8200-c33aeb682379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716186233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3716186233
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.961611804
Short name T278
Test name
Test status
Simulation time 473498910 ps
CPU time 2.57 seconds
Started Jul 26 07:01:09 PM PDT 24
Finished Jul 26 07:01:11 PM PDT 24
Peak memory 200164 kb
Host smart-42318e62-2f70-41c1-b87e-b970bb6e148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961611804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.961611804
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.940424046
Short name T163
Test name
Test status
Simulation time 55439972 ps
CPU time 0.75 seconds
Started Jul 26 07:01:14 PM PDT 24
Finished Jul 26 07:01:15 PM PDT 24
Peak memory 200072 kb
Host smart-512646e7-ddef-4a04-afb6-b275d1939143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940424046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.940424046
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3188109836
Short name T149
Test name
Test status
Simulation time 76610793 ps
CPU time 0.8 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 199848 kb
Host smart-c597556d-d57d-4a32-8bc9-e4c92a28022e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188109836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3188109836
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.853264594
Short name T534
Test name
Test status
Simulation time 1886953962 ps
CPU time 6.65 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:19 PM PDT 24
Peak memory 217556 kb
Host smart-0025c044-045f-471d-a00c-6ff71f46af4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853264594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.853264594
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2667040394
Short name T305
Test name
Test status
Simulation time 245486049 ps
CPU time 1.06 seconds
Started Jul 26 07:02:17 PM PDT 24
Finished Jul 26 07:02:19 PM PDT 24
Peak memory 217472 kb
Host smart-2793fd93-9201-4452-96c0-ac6605c4a4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667040394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2667040394
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1616252476
Short name T382
Test name
Test status
Simulation time 109483522 ps
CPU time 0.76 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 199908 kb
Host smart-34b8bba8-420f-4e9e-ab85-874816304c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616252476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1616252476
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.558962942
Short name T93
Test name
Test status
Simulation time 1946593243 ps
CPU time 7.09 seconds
Started Jul 26 07:02:07 PM PDT 24
Finished Jul 26 07:02:15 PM PDT 24
Peak memory 200348 kb
Host smart-edffcf6b-601b-4739-81a3-7d0a2b28b651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558962942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.558962942
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4211421450
Short name T310
Test name
Test status
Simulation time 115080783 ps
CPU time 1.02 seconds
Started Jul 26 07:02:10 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 200072 kb
Host smart-7954eef1-1d67-4b3d-b3e2-ae80263abd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211421450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4211421450
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3989059519
Short name T198
Test name
Test status
Simulation time 255328291 ps
CPU time 1.44 seconds
Started Jul 26 07:02:05 PM PDT 24
Finished Jul 26 07:02:06 PM PDT 24
Peak memory 200236 kb
Host smart-209ea3be-1cd0-41d3-b448-4f6250f6aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989059519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3989059519
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3885204808
Short name T98
Test name
Test status
Simulation time 5079156951 ps
CPU time 18.74 seconds
Started Jul 26 07:02:20 PM PDT 24
Finished Jul 26 07:02:39 PM PDT 24
Peak memory 208636 kb
Host smart-2f655cdb-abc2-4285-88e2-2f17a63d15ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885204808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3885204808
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3494733957
Short name T526
Test name
Test status
Simulation time 117538675 ps
CPU time 1.48 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 200096 kb
Host smart-24f4625d-73a8-44ea-8a80-efdec74c1d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494733957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3494733957
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3298007163
Short name T202
Test name
Test status
Simulation time 157286092 ps
CPU time 1.25 seconds
Started Jul 26 07:02:11 PM PDT 24
Finished Jul 26 07:02:12 PM PDT 24
Peak memory 200300 kb
Host smart-f6a9cab4-f7ad-4452-b744-b42bf968a723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298007163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3298007163
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.4145382583
Short name T513
Test name
Test status
Simulation time 69570460 ps
CPU time 0.8 seconds
Started Jul 26 07:02:15 PM PDT 24
Finished Jul 26 07:02:16 PM PDT 24
Peak memory 199868 kb
Host smart-12549d32-11cc-4769-b3d0-9ba7cce44436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145382583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.4145382583
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1265320044
Short name T48
Test name
Test status
Simulation time 1229075087 ps
CPU time 6.05 seconds
Started Jul 26 07:02:13 PM PDT 24
Finished Jul 26 07:02:19 PM PDT 24
Peak memory 217752 kb
Host smart-9b0cfbc5-c771-439f-83c6-9641eea047ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265320044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1265320044
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.575040935
Short name T545
Test name
Test status
Simulation time 244569605 ps
CPU time 1.1 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:14 PM PDT 24
Peak memory 217372 kb
Host smart-ed676070-aab3-45ea-8f25-7ea08c21ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575040935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.575040935
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2121404374
Short name T200
Test name
Test status
Simulation time 223160778 ps
CPU time 0.94 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 199888 kb
Host smart-85ceffd7-4bc9-4816-b9fc-8e890511c388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121404374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2121404374
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.757155349
Short name T483
Test name
Test status
Simulation time 1274076733 ps
CPU time 5.54 seconds
Started Jul 26 07:02:13 PM PDT 24
Finished Jul 26 07:02:19 PM PDT 24
Peak memory 200344 kb
Host smart-97a63fc1-335d-499d-880c-328526603b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757155349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.757155349
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1271116124
Short name T355
Test name
Test status
Simulation time 110074768 ps
CPU time 0.99 seconds
Started Jul 26 07:02:08 PM PDT 24
Finished Jul 26 07:02:09 PM PDT 24
Peak memory 200072 kb
Host smart-96c62078-8c56-4fd8-81e3-4ad9c817fed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271116124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1271116124
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.165718159
Short name T330
Test name
Test status
Simulation time 222113391 ps
CPU time 1.45 seconds
Started Jul 26 07:02:11 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 200280 kb
Host smart-ca5d535a-40cc-40ee-8dfd-425afbdd943d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165718159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.165718159
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3531853358
Short name T284
Test name
Test status
Simulation time 1664035630 ps
CPU time 6.23 seconds
Started Jul 26 07:02:15 PM PDT 24
Finished Jul 26 07:02:21 PM PDT 24
Peak memory 200320 kb
Host smart-2b27a12b-a918-40d3-b035-553e32185e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531853358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3531853358
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2585589624
Short name T449
Test name
Test status
Simulation time 510498653 ps
CPU time 2.71 seconds
Started Jul 26 07:02:05 PM PDT 24
Finished Jul 26 07:02:08 PM PDT 24
Peak memory 200100 kb
Host smart-5bb571cd-8629-49a8-a523-8f2403429e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585589624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2585589624
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3864780558
Short name T341
Test name
Test status
Simulation time 72535506 ps
CPU time 0.83 seconds
Started Jul 26 07:02:14 PM PDT 24
Finished Jul 26 07:02:15 PM PDT 24
Peak memory 200080 kb
Host smart-c9d5d8af-31e2-4202-bc36-17a363a3ea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864780558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3864780558
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3576708249
Short name T398
Test name
Test status
Simulation time 75813611 ps
CPU time 0.78 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 199872 kb
Host smart-ebd8188e-f6b0-41dc-aca1-a4bc3553a2b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576708249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3576708249
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2103608369
Short name T46
Test name
Test status
Simulation time 1869715409 ps
CPU time 7.07 seconds
Started Jul 26 07:02:13 PM PDT 24
Finished Jul 26 07:02:20 PM PDT 24
Peak memory 217452 kb
Host smart-57964ec5-0fea-4787-908c-6c26cb0be47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103608369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2103608369
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3677822502
Short name T388
Test name
Test status
Simulation time 245121574 ps
CPU time 1.05 seconds
Started Jul 26 07:02:14 PM PDT 24
Finished Jul 26 07:02:16 PM PDT 24
Peak memory 217416 kb
Host smart-b3187524-8b1e-471f-b964-f29a69c00419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677822502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3677822502
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1501114717
Short name T493
Test name
Test status
Simulation time 105615282 ps
CPU time 0.75 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:09 PM PDT 24
Peak memory 199892 kb
Host smart-abd35cb1-6ef9-4c0d-bac5-4791ccb03f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501114717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1501114717
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.657878695
Short name T11
Test name
Test status
Simulation time 1708496800 ps
CPU time 6.88 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:16 PM PDT 24
Peak memory 200320 kb
Host smart-0e942d0d-172b-4490-926a-748f5f71b0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657878695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.657878695
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3260402600
Short name T282
Test name
Test status
Simulation time 154324683 ps
CPU time 1.23 seconds
Started Jul 26 07:02:13 PM PDT 24
Finished Jul 26 07:02:14 PM PDT 24
Peak memory 200048 kb
Host smart-62209610-8bae-4db8-85a3-e2d79ea14f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260402600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3260402600
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.669070315
Short name T148
Test name
Test status
Simulation time 197535840 ps
CPU time 1.31 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 200128 kb
Host smart-0eb86cc9-91f9-41b9-8c9a-3a74b085ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669070315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.669070315
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1949956479
Short name T479
Test name
Test status
Simulation time 3704052385 ps
CPU time 18.93 seconds
Started Jul 26 07:02:16 PM PDT 24
Finished Jul 26 07:02:35 PM PDT 24
Peak memory 200352 kb
Host smart-75e458f1-bca2-44ac-9073-ab2480501b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949956479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1949956479
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.4149283803
Short name T127
Test name
Test status
Simulation time 355709529 ps
CPU time 2.03 seconds
Started Jul 26 07:02:15 PM PDT 24
Finished Jul 26 07:02:17 PM PDT 24
Peak memory 200056 kb
Host smart-a15d42ac-050b-49f7-82b0-efdf7dbfdec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149283803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.4149283803
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2945934480
Short name T327
Test name
Test status
Simulation time 191789227 ps
CPU time 1.25 seconds
Started Jul 26 07:02:06 PM PDT 24
Finished Jul 26 07:02:08 PM PDT 24
Peak memory 200092 kb
Host smart-d290c091-dd1c-495a-907d-265c17f667ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945934480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2945934480
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1049698857
Short name T302
Test name
Test status
Simulation time 67158624 ps
CPU time 0.78 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:10 PM PDT 24
Peak memory 199844 kb
Host smart-f04141f2-2026-4e80-8acd-080c46e1063e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049698857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1049698857
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3326857021
Short name T44
Test name
Test status
Simulation time 1224501029 ps
CPU time 6.28 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:18 PM PDT 24
Peak memory 216964 kb
Host smart-3ffc2901-5ad5-4cf4-b8c0-68020ce93684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326857021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3326857021
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2758039426
Short name T374
Test name
Test status
Simulation time 244459182 ps
CPU time 1.14 seconds
Started Jul 26 07:02:14 PM PDT 24
Finished Jul 26 07:02:15 PM PDT 24
Peak memory 217320 kb
Host smart-40c048f5-c848-40ae-b3e5-ded7c3a6a62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758039426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2758039426
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3754132816
Short name T254
Test name
Test status
Simulation time 205782168 ps
CPU time 0.95 seconds
Started Jul 26 07:02:11 PM PDT 24
Finished Jul 26 07:02:12 PM PDT 24
Peak memory 199856 kb
Host smart-53229520-36dc-41c7-8c84-adc667cd2d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754132816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3754132816
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1406333733
Short name T94
Test name
Test status
Simulation time 791907348 ps
CPU time 4.12 seconds
Started Jul 26 07:02:20 PM PDT 24
Finished Jul 26 07:02:25 PM PDT 24
Peak memory 200352 kb
Host smart-9926edd8-17e1-4363-b9e1-b5ec4958e01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406333733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1406333733
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2707903026
Short name T326
Test name
Test status
Simulation time 112863152 ps
CPU time 1.06 seconds
Started Jul 26 07:02:11 PM PDT 24
Finished Jul 26 07:02:12 PM PDT 24
Peak memory 200016 kb
Host smart-286beebb-b5d4-470a-80d8-de98928c6ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707903026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2707903026
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.4002624041
Short name T386
Test name
Test status
Simulation time 114813830 ps
CPU time 1.15 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 200276 kb
Host smart-af5bd42d-1359-47ff-a881-2a64b1dfafa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002624041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.4002624041
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1193858705
Short name T271
Test name
Test status
Simulation time 6877795409 ps
CPU time 24.8 seconds
Started Jul 26 07:02:24 PM PDT 24
Finished Jul 26 07:02:49 PM PDT 24
Peak memory 200356 kb
Host smart-60739f3c-af02-4a0a-8f07-9bc5fc99428f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193858705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1193858705
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4104069294
Short name T383
Test name
Test status
Simulation time 264412891 ps
CPU time 1.84 seconds
Started Jul 26 07:02:10 PM PDT 24
Finished Jul 26 07:02:12 PM PDT 24
Peak memory 200080 kb
Host smart-ffe53c5f-13bd-4b9c-99d0-36eda2eb381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104069294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4104069294
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3914598519
Short name T207
Test name
Test status
Simulation time 138206326 ps
CPU time 1.03 seconds
Started Jul 26 07:02:16 PM PDT 24
Finished Jul 26 07:02:17 PM PDT 24
Peak memory 200100 kb
Host smart-8df40116-0671-455e-ab58-12a45a140fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914598519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3914598519
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2996755227
Short name T1
Test name
Test status
Simulation time 81816496 ps
CPU time 0.79 seconds
Started Jul 26 07:02:06 PM PDT 24
Finished Jul 26 07:02:06 PM PDT 24
Peak memory 199868 kb
Host smart-51d450fa-db56-482e-9d13-5e5640e4743b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996755227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2996755227
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.4081405026
Short name T387
Test name
Test status
Simulation time 1227173548 ps
CPU time 5.41 seconds
Started Jul 26 07:02:24 PM PDT 24
Finished Jul 26 07:02:30 PM PDT 24
Peak memory 217360 kb
Host smart-d612cb77-5b0f-4f55-8e83-0b08afdccee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081405026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.4081405026
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2013005403
Short name T297
Test name
Test status
Simulation time 244291276 ps
CPU time 1.1 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 217500 kb
Host smart-7c77a866-831f-4ea9-b0c0-6ec785bfbea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013005403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2013005403
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2589504098
Short name T232
Test name
Test status
Simulation time 173403972 ps
CPU time 0.85 seconds
Started Jul 26 07:02:15 PM PDT 24
Finished Jul 26 07:02:16 PM PDT 24
Peak memory 199844 kb
Host smart-fc02c2e6-dcff-4585-9255-d5f3c72d612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589504098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2589504098
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.290809810
Short name T14
Test name
Test status
Simulation time 898863848 ps
CPU time 4.34 seconds
Started Jul 26 07:02:28 PM PDT 24
Finished Jul 26 07:02:32 PM PDT 24
Peak memory 200340 kb
Host smart-d53a1d80-00ff-455c-8b52-92ceea51796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290809810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.290809810
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2030291132
Short name T540
Test name
Test status
Simulation time 150987614 ps
CPU time 1.03 seconds
Started Jul 26 07:02:14 PM PDT 24
Finished Jul 26 07:02:15 PM PDT 24
Peak memory 200080 kb
Host smart-82e7c2e7-b9b2-42cc-a958-1bac7d351926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030291132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2030291132
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3467331660
Short name T169
Test name
Test status
Simulation time 227149014 ps
CPU time 1.49 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:14 PM PDT 24
Peak memory 200272 kb
Host smart-b5edf58c-df09-43b6-8752-9bcd19e90cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467331660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3467331660
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.798993498
Short name T7
Test name
Test status
Simulation time 142279568 ps
CPU time 1.11 seconds
Started Jul 26 07:02:13 PM PDT 24
Finished Jul 26 07:02:14 PM PDT 24
Peak memory 199920 kb
Host smart-977790ac-af1c-45e1-bdf9-91fb4ddb0da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798993498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.798993498
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3010007129
Short name T60
Test name
Test status
Simulation time 147700200 ps
CPU time 1.74 seconds
Started Jul 26 07:02:13 PM PDT 24
Finished Jul 26 07:02:15 PM PDT 24
Peak memory 200096 kb
Host smart-42e81fa1-db39-431b-ae59-37b79bcbe918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010007129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3010007129
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.677216532
Short name T514
Test name
Test status
Simulation time 113274845 ps
CPU time 0.9 seconds
Started Jul 26 07:02:12 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 200036 kb
Host smart-3174a81f-12c6-4569-8e99-7c49f44df555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677216532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.677216532
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.355463898
Short name T205
Test name
Test status
Simulation time 82899031 ps
CPU time 0.82 seconds
Started Jul 26 07:02:11 PM PDT 24
Finished Jul 26 07:02:12 PM PDT 24
Peak memory 199888 kb
Host smart-160cf61c-64aa-4cff-a89d-ddac118b58a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355463898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.355463898
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.540068647
Short name T405
Test name
Test status
Simulation time 1224296852 ps
CPU time 5.74 seconds
Started Jul 26 07:02:07 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 216824 kb
Host smart-f58f35cb-7526-4b82-ac51-3c6abaf100fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540068647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.540068647
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3365971302
Short name T238
Test name
Test status
Simulation time 244231668 ps
CPU time 1.14 seconds
Started Jul 26 07:02:18 PM PDT 24
Finished Jul 26 07:02:19 PM PDT 24
Peak memory 217404 kb
Host smart-37807283-f5c4-45e3-9016-ffac907952db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365971302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3365971302
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.602667875
Short name T15
Test name
Test status
Simulation time 122527304 ps
CPU time 0.82 seconds
Started Jul 26 07:02:17 PM PDT 24
Finished Jul 26 07:02:18 PM PDT 24
Peak memory 199884 kb
Host smart-fdc9e173-c96a-4161-8e0e-a25a7313d506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602667875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.602667875
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1317688502
Short name T61
Test name
Test status
Simulation time 984868663 ps
CPU time 4.74 seconds
Started Jul 26 07:02:15 PM PDT 24
Finished Jul 26 07:02:20 PM PDT 24
Peak memory 200340 kb
Host smart-6bafe758-f3d2-439c-8a94-17bc749b25c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317688502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1317688502
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.559354786
Short name T136
Test name
Test status
Simulation time 101364631 ps
CPU time 0.94 seconds
Started Jul 26 07:02:15 PM PDT 24
Finished Jul 26 07:02:17 PM PDT 24
Peak memory 200092 kb
Host smart-316f0b87-b28e-4f25-a17a-8e6c9a3bd196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559354786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.559354786
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2769393819
Short name T308
Test name
Test status
Simulation time 199275021 ps
CPU time 1.39 seconds
Started Jul 26 07:02:24 PM PDT 24
Finished Jul 26 07:02:26 PM PDT 24
Peak memory 200200 kb
Host smart-6fe2f246-94aa-46b1-9971-56996d85d712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769393819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2769393819
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3043457434
Short name T544
Test name
Test status
Simulation time 1962509719 ps
CPU time 8.7 seconds
Started Jul 26 07:02:02 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 200464 kb
Host smart-582690fe-b5fb-43a9-9352-cd9a8feec4da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043457434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3043457434
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3397550402
Short name T332
Test name
Test status
Simulation time 376918440 ps
CPU time 2.36 seconds
Started Jul 26 07:02:22 PM PDT 24
Finished Jul 26 07:02:24 PM PDT 24
Peak memory 200096 kb
Host smart-6d519795-797e-4125-891d-a20e483b4bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397550402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3397550402
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3212844758
Short name T452
Test name
Test status
Simulation time 178402451 ps
CPU time 1.33 seconds
Started Jul 26 07:02:06 PM PDT 24
Finished Jul 26 07:02:08 PM PDT 24
Peak memory 200312 kb
Host smart-94886f8b-9527-4c74-85ce-dfba53493cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212844758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3212844758
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.863192547
Short name T32
Test name
Test status
Simulation time 87822438 ps
CPU time 0.84 seconds
Started Jul 26 07:02:26 PM PDT 24
Finished Jul 26 07:02:27 PM PDT 24
Peak memory 199892 kb
Host smart-2bb65bb2-e4c6-4b0b-997d-04e5f3477b1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863192547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.863192547
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1057262729
Short name T36
Test name
Test status
Simulation time 1224465206 ps
CPU time 5.48 seconds
Started Jul 26 07:02:18 PM PDT 24
Finished Jul 26 07:02:23 PM PDT 24
Peak memory 216924 kb
Host smart-ef8fe6f6-a250-4eeb-ab6a-b67c4fcdac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057262729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1057262729
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.206390964
Short name T188
Test name
Test status
Simulation time 243913319 ps
CPU time 1.05 seconds
Started Jul 26 07:02:21 PM PDT 24
Finished Jul 26 07:02:22 PM PDT 24
Peak memory 217408 kb
Host smart-7ee875eb-ab09-4e81-a490-7a76957cfee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206390964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.206390964
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4179898153
Short name T365
Test name
Test status
Simulation time 116484824 ps
CPU time 0.74 seconds
Started Jul 26 07:02:16 PM PDT 24
Finished Jul 26 07:02:17 PM PDT 24
Peak memory 199936 kb
Host smart-d5d99a05-d5b3-4e05-a6fb-e552ae5dfa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179898153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4179898153
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2964253386
Short name T124
Test name
Test status
Simulation time 2141967515 ps
CPU time 8.45 seconds
Started Jul 26 07:02:09 PM PDT 24
Finished Jul 26 07:02:18 PM PDT 24
Peak memory 200420 kb
Host smart-1f3b5c8f-18a9-4f7b-bbe3-35473396a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964253386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2964253386
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1826235625
Short name T259
Test name
Test status
Simulation time 178661961 ps
CPU time 1.21 seconds
Started Jul 26 07:02:13 PM PDT 24
Finished Jul 26 07:02:25 PM PDT 24
Peak memory 200052 kb
Host smart-eb134e00-4e8c-4710-bef5-d581b3eeb980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826235625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1826235625
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3569956750
Short name T430
Test name
Test status
Simulation time 248324263 ps
CPU time 1.41 seconds
Started Jul 26 07:02:15 PM PDT 24
Finished Jul 26 07:02:16 PM PDT 24
Peak memory 200344 kb
Host smart-220b30e0-22cf-46d0-a214-418cf2d9294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569956750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3569956750
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2679092712
Short name T442
Test name
Test status
Simulation time 7281169538 ps
CPU time 25.19 seconds
Started Jul 26 07:02:17 PM PDT 24
Finished Jul 26 07:02:42 PM PDT 24
Peak memory 200484 kb
Host smart-31610703-6da6-4008-a1e3-a551104061c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679092712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2679092712
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2053537535
Short name T277
Test name
Test status
Simulation time 129988204 ps
CPU time 1.64 seconds
Started Jul 26 07:02:18 PM PDT 24
Finished Jul 26 07:02:20 PM PDT 24
Peak memory 200104 kb
Host smart-ac9dd76d-7e3c-4b78-9f00-238d32166a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053537535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2053537535
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3451107537
Short name T506
Test name
Test status
Simulation time 128316654 ps
CPU time 1.08 seconds
Started Jul 26 07:02:27 PM PDT 24
Finished Jul 26 07:02:28 PM PDT 24
Peak memory 200100 kb
Host smart-1273c73e-4602-4081-bc14-e84f82760763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451107537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3451107537
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.183058601
Short name T181
Test name
Test status
Simulation time 68372686 ps
CPU time 0.81 seconds
Started Jul 26 07:02:27 PM PDT 24
Finished Jul 26 07:02:28 PM PDT 24
Peak memory 199888 kb
Host smart-6a167d26-5fa2-417e-a874-8d305ba701ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183058601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.183058601
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.4241656430
Short name T41
Test name
Test status
Simulation time 1888505047 ps
CPU time 6.87 seconds
Started Jul 26 07:02:32 PM PDT 24
Finished Jul 26 07:02:39 PM PDT 24
Peak memory 217704 kb
Host smart-a10e51a5-5f7c-4ceb-8f39-f3258706361f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241656430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4241656430
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1939702777
Short name T272
Test name
Test status
Simulation time 244690722 ps
CPU time 1.04 seconds
Started Jul 26 07:02:16 PM PDT 24
Finished Jul 26 07:02:17 PM PDT 24
Peak memory 217508 kb
Host smart-c18fb96d-7fc4-489d-8416-c083cf8c4e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939702777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1939702777
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.895946312
Short name T184
Test name
Test status
Simulation time 177739920 ps
CPU time 0.81 seconds
Started Jul 26 07:02:14 PM PDT 24
Finished Jul 26 07:02:15 PM PDT 24
Peak memory 199868 kb
Host smart-81644860-c0b0-4493-b336-4180ccc409db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895946312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.895946312
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1071149796
Short name T346
Test name
Test status
Simulation time 1761870908 ps
CPU time 6.28 seconds
Started Jul 26 07:02:15 PM PDT 24
Finished Jul 26 07:02:21 PM PDT 24
Peak memory 200300 kb
Host smart-7864aa2d-9aa3-4a96-923d-4a5cfbd71f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071149796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1071149796
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.200867724
Short name T203
Test name
Test status
Simulation time 109999622 ps
CPU time 1.03 seconds
Started Jul 26 07:02:29 PM PDT 24
Finished Jul 26 07:02:30 PM PDT 24
Peak memory 200052 kb
Host smart-8dd5399d-ab1b-47b5-b049-460a147d8a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200867724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.200867724
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4260300545
Short name T144
Test name
Test status
Simulation time 201988910 ps
CPU time 1.4 seconds
Started Jul 26 07:02:18 PM PDT 24
Finished Jul 26 07:02:19 PM PDT 24
Peak memory 200356 kb
Host smart-cd0c29fe-4fa4-49e8-ad44-3bde898acdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260300545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4260300545
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1422918560
Short name T521
Test name
Test status
Simulation time 2699306343 ps
CPU time 10.7 seconds
Started Jul 26 07:02:22 PM PDT 24
Finished Jul 26 07:02:33 PM PDT 24
Peak memory 200460 kb
Host smart-baa02388-47cc-403e-a872-fa871536fc17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422918560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1422918560
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2279695642
Short name T415
Test name
Test status
Simulation time 123524717 ps
CPU time 1.54 seconds
Started Jul 26 07:02:29 PM PDT 24
Finished Jul 26 07:02:30 PM PDT 24
Peak memory 200132 kb
Host smart-7b9cfc97-0494-4b45-9d0f-612e81c3d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279695642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2279695642
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3767479552
Short name T268
Test name
Test status
Simulation time 120371148 ps
CPU time 1.07 seconds
Started Jul 26 07:02:29 PM PDT 24
Finished Jul 26 07:02:30 PM PDT 24
Peak memory 200104 kb
Host smart-5db7117c-fd62-4183-ad20-1466ebd0b0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767479552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3767479552
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.802468370
Short name T219
Test name
Test status
Simulation time 84410956 ps
CPU time 0.84 seconds
Started Jul 26 07:02:14 PM PDT 24
Finished Jul 26 07:02:15 PM PDT 24
Peak memory 199944 kb
Host smart-2d183d37-8605-4e2e-8f25-ce433d75f972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802468370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.802468370
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.915218216
Short name T515
Test name
Test status
Simulation time 1915544907 ps
CPU time 7.36 seconds
Started Jul 26 07:02:32 PM PDT 24
Finished Jul 26 07:02:39 PM PDT 24
Peak memory 217432 kb
Host smart-d637b678-929e-41a7-af2f-68cbe93c88b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915218216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.915218216
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1140469052
Short name T56
Test name
Test status
Simulation time 245161787 ps
CPU time 1.08 seconds
Started Jul 26 07:02:27 PM PDT 24
Finished Jul 26 07:02:29 PM PDT 24
Peak memory 217372 kb
Host smart-9fdf5153-1853-4a53-8895-b658178b0e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140469052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1140469052
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.21997684
Short name T246
Test name
Test status
Simulation time 155410902 ps
CPU time 0.89 seconds
Started Jul 26 07:02:21 PM PDT 24
Finished Jul 26 07:02:22 PM PDT 24
Peak memory 199964 kb
Host smart-338a9f6a-6d32-4915-bf2d-9dffdeaab39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21997684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.21997684
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3022413163
Short name T239
Test name
Test status
Simulation time 806745383 ps
CPU time 4.03 seconds
Started Jul 26 07:02:26 PM PDT 24
Finished Jul 26 07:02:30 PM PDT 24
Peak memory 200464 kb
Host smart-f540ebd4-8b11-43bd-b825-c7a0824f176e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022413163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3022413163
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2519220882
Short name T155
Test name
Test status
Simulation time 96160486 ps
CPU time 0.96 seconds
Started Jul 26 07:02:15 PM PDT 24
Finished Jul 26 07:02:16 PM PDT 24
Peak memory 200072 kb
Host smart-2c32de49-133d-41bb-a299-fde58e8df299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519220882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2519220882
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2318384085
Short name T354
Test name
Test status
Simulation time 110286426 ps
CPU time 1.21 seconds
Started Jul 26 07:02:26 PM PDT 24
Finished Jul 26 07:02:28 PM PDT 24
Peak memory 200260 kb
Host smart-5b519ea8-28a5-49fd-9405-a36082627b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318384085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2318384085
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1064985131
Short name T241
Test name
Test status
Simulation time 9745309787 ps
CPU time 35.64 seconds
Started Jul 26 07:02:21 PM PDT 24
Finished Jul 26 07:02:57 PM PDT 24
Peak memory 208608 kb
Host smart-77158865-f470-4358-aff8-254d7555a7ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064985131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1064985131
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2796093657
Short name T535
Test name
Test status
Simulation time 297241737 ps
CPU time 1.98 seconds
Started Jul 26 07:02:16 PM PDT 24
Finished Jul 26 07:02:18 PM PDT 24
Peak memory 208280 kb
Host smart-59c0a24c-f78e-4f84-bacb-98d4855f7709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796093657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2796093657
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.393047418
Short name T269
Test name
Test status
Simulation time 101904461 ps
CPU time 0.85 seconds
Started Jul 26 07:02:31 PM PDT 24
Finished Jul 26 07:02:32 PM PDT 24
Peak memory 200000 kb
Host smart-519229d6-0acb-4b4e-822a-da82f71b0797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393047418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.393047418
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1737600590
Short name T199
Test name
Test status
Simulation time 78943936 ps
CPU time 0.79 seconds
Started Jul 26 07:02:21 PM PDT 24
Finished Jul 26 07:02:22 PM PDT 24
Peak memory 199884 kb
Host smart-499e3536-b39f-43d4-8315-2eea239c6d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737600590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1737600590
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.4087410704
Short name T481
Test name
Test status
Simulation time 1897596476 ps
CPU time 7.21 seconds
Started Jul 26 07:02:15 PM PDT 24
Finished Jul 26 07:02:23 PM PDT 24
Peak memory 221680 kb
Host smart-23ec5799-e596-4485-a6a8-048a2f8e5e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087410704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.4087410704
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3447972526
Short name T368
Test name
Test status
Simulation time 244791804 ps
CPU time 1.03 seconds
Started Jul 26 07:02:13 PM PDT 24
Finished Jul 26 07:02:14 PM PDT 24
Peak memory 217464 kb
Host smart-2592df2e-6ccd-435d-a30f-116ae571fd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447972526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3447972526
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1173644977
Short name T363
Test name
Test status
Simulation time 89990734 ps
CPU time 0.74 seconds
Started Jul 26 07:02:20 PM PDT 24
Finished Jul 26 07:02:21 PM PDT 24
Peak memory 199796 kb
Host smart-9b82e108-d79a-4fab-af2b-7447915fbbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173644977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1173644977
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2555961510
Short name T407
Test name
Test status
Simulation time 1114332207 ps
CPU time 4.4 seconds
Started Jul 26 07:02:24 PM PDT 24
Finished Jul 26 07:02:29 PM PDT 24
Peak memory 200384 kb
Host smart-b81b5744-3f6a-48f0-84d1-e471f8ed34b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555961510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2555961510
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2910740514
Short name T469
Test name
Test status
Simulation time 147867126 ps
CPU time 1.07 seconds
Started Jul 26 07:02:19 PM PDT 24
Finished Jul 26 07:02:20 PM PDT 24
Peak memory 200364 kb
Host smart-27aac83e-fa5f-49af-bb2b-86f72b91a4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910740514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2910740514
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2060306720
Short name T222
Test name
Test status
Simulation time 244405221 ps
CPU time 1.51 seconds
Started Jul 26 07:02:16 PM PDT 24
Finished Jul 26 07:02:18 PM PDT 24
Peak memory 200228 kb
Host smart-9c6880c0-fcc8-4399-a5c7-8efd987d15ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060306720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2060306720
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.4185677546
Short name T530
Test name
Test status
Simulation time 274856472 ps
CPU time 1.78 seconds
Started Jul 26 07:02:22 PM PDT 24
Finished Jul 26 07:02:24 PM PDT 24
Peak memory 200032 kb
Host smart-89365afd-f2db-40c0-97a6-c91c2df1d84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185677546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.4185677546
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.874327598
Short name T30
Test name
Test status
Simulation time 90066868 ps
CPU time 1 seconds
Started Jul 26 07:02:26 PM PDT 24
Finished Jul 26 07:02:27 PM PDT 24
Peak memory 200052 kb
Host smart-99ac751d-836f-4fc1-9ef1-733cd7b0b944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874327598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.874327598
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.4086437163
Short name T371
Test name
Test status
Simulation time 84938651 ps
CPU time 0.86 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:21 PM PDT 24
Peak memory 199708 kb
Host smart-11873541-539d-406d-9c9b-33c98b347e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086437163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4086437163
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1722080923
Short name T66
Test name
Test status
Simulation time 1228575928 ps
CPU time 5.51 seconds
Started Jul 26 07:01:16 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 217484 kb
Host smart-09d52007-699c-4c94-a2a3-9bfc0a399bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722080923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1722080923
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.376012997
Short name T313
Test name
Test status
Simulation time 243946380 ps
CPU time 1.08 seconds
Started Jul 26 07:01:16 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 217408 kb
Host smart-15feabbb-eedc-4db8-9991-0432da81053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376012997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.376012997
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.4229867175
Short name T550
Test name
Test status
Simulation time 209749883 ps
CPU time 0.89 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 199916 kb
Host smart-1eb7acca-391a-494f-ab57-673ec8d2c7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229867175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.4229867175
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1044676069
Short name T307
Test name
Test status
Simulation time 1548039607 ps
CPU time 5.57 seconds
Started Jul 26 07:01:16 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 200296 kb
Host smart-7b4df1c4-d854-4216-93d7-025cb17b9aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044676069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1044676069
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2477269309
Short name T147
Test name
Test status
Simulation time 101951237 ps
CPU time 0.96 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 200136 kb
Host smart-cdba60db-0a19-4e92-9ea9-c5fa73f73edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477269309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2477269309
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2519044641
Short name T321
Test name
Test status
Simulation time 114149448 ps
CPU time 1.17 seconds
Started Jul 26 07:01:09 PM PDT 24
Finished Jul 26 07:01:11 PM PDT 24
Peak memory 200284 kb
Host smart-5e309e89-3447-4ea8-9250-1b925f6e7982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519044641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2519044641
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2872472991
Short name T231
Test name
Test status
Simulation time 11211295468 ps
CPU time 43.92 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:02:03 PM PDT 24
Peak memory 200404 kb
Host smart-8e5bae91-ff90-4d64-8aa1-f93521fa1f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872472991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2872472991
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1314128991
Short name T522
Test name
Test status
Simulation time 305124838 ps
CPU time 2.03 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:01:21 PM PDT 24
Peak memory 208244 kb
Host smart-5d4ff2d7-ca80-4719-8d9c-918b757a481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314128991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1314128991
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.4024584717
Short name T470
Test name
Test status
Simulation time 82066141 ps
CPU time 0.83 seconds
Started Jul 26 07:01:12 PM PDT 24
Finished Jul 26 07:01:13 PM PDT 24
Peak memory 200040 kb
Host smart-15ad0649-7908-4e83-80f2-965aaaa65434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024584717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.4024584717
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1241295708
Short name T152
Test name
Test status
Simulation time 70077752 ps
CPU time 0.82 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 199864 kb
Host smart-f59252c5-a819-4c9f-b0dd-511e5fd61bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241295708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1241295708
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2964263932
Short name T35
Test name
Test status
Simulation time 2368642933 ps
CPU time 8.56 seconds
Started Jul 26 07:01:13 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 217844 kb
Host smart-b1b884fa-5bc2-4979-a46d-20e90e10943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964263932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2964263932
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3440126295
Short name T293
Test name
Test status
Simulation time 244117791 ps
CPU time 1.2 seconds
Started Jul 26 07:01:21 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 217468 kb
Host smart-6de3a738-c162-4abe-8c92-981f540932a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440126295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3440126295
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1314707787
Short name T418
Test name
Test status
Simulation time 80040225 ps
CPU time 0.74 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 199932 kb
Host smart-d8f0bd10-cf52-4b61-8043-4adf504ce492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314707787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1314707787
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3060740947
Short name T257
Test name
Test status
Simulation time 1857592964 ps
CPU time 7.33 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:28 PM PDT 24
Peak memory 200384 kb
Host smart-22973767-7c33-4415-ab21-93f98afd3ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060740947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3060740947
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2243889402
Short name T358
Test name
Test status
Simulation time 181830718 ps
CPU time 1.17 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 200072 kb
Host smart-b98f557c-df85-4b23-8910-26bb2a14bdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243889402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2243889402
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2116384510
Short name T361
Test name
Test status
Simulation time 121105158 ps
CPU time 1.26 seconds
Started Jul 26 07:01:22 PM PDT 24
Finished Jul 26 07:01:24 PM PDT 24
Peak memory 200284 kb
Host smart-fcda5315-6155-4b43-b5f6-99a95442b127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116384510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2116384510
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.533033610
Short name T295
Test name
Test status
Simulation time 11011958041 ps
CPU time 38.04 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:56 PM PDT 24
Peak memory 200364 kb
Host smart-011726f1-cd5c-456d-aef2-90b5bbbcdfa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533033610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.533033610
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3197676666
Short name T487
Test name
Test status
Simulation time 482527788 ps
CPU time 2.61 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 208284 kb
Host smart-5cbe115d-a8e2-4c7b-9e73-e332b7560eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197676666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3197676666
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1445801186
Short name T312
Test name
Test status
Simulation time 128066867 ps
CPU time 1.14 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:01:21 PM PDT 24
Peak memory 200064 kb
Host smart-9b85e64b-3eaa-4cff-b09b-2fad9118383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445801186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1445801186
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1127424440
Short name T478
Test name
Test status
Simulation time 75242764 ps
CPU time 0.8 seconds
Started Jul 26 07:01:27 PM PDT 24
Finished Jul 26 07:01:28 PM PDT 24
Peak memory 199876 kb
Host smart-d1cc05fe-c9cb-4b38-9a3a-3e60ef1b0e6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127424440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1127424440
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1061102950
Short name T517
Test name
Test status
Simulation time 2362291314 ps
CPU time 8.46 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:26 PM PDT 24
Peak memory 221680 kb
Host smart-6448f54c-d8f1-4125-ba0b-fe51b8287c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061102950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1061102950
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.408481060
Short name T391
Test name
Test status
Simulation time 245362131 ps
CPU time 1.06 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 217484 kb
Host smart-0d9b7611-1a82-461e-909f-ba875c656399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408481060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.408481060
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2683161370
Short name T422
Test name
Test status
Simulation time 157117930 ps
CPU time 0.8 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 199888 kb
Host smart-bcb297e1-d7a8-439b-98b0-2966053c366d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683161370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2683161370
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2842710836
Short name T402
Test name
Test status
Simulation time 1295753600 ps
CPU time 4.87 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:23 PM PDT 24
Peak memory 200400 kb
Host smart-bd6ca34f-0d48-4090-be0a-df45f89126e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842710836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2842710836
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2819880699
Short name T301
Test name
Test status
Simulation time 148083519 ps
CPU time 1.24 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:01:20 PM PDT 24
Peak memory 200028 kb
Host smart-cfc37d96-376f-42c1-b418-e286f0ea668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819880699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2819880699
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.485629893
Short name T401
Test name
Test status
Simulation time 122776202 ps
CPU time 1.18 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 200232 kb
Host smart-8e5460bc-d07b-4af8-a416-57059f382508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485629893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.485629893
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3860955983
Short name T229
Test name
Test status
Simulation time 4169066193 ps
CPU time 18.19 seconds
Started Jul 26 07:01:15 PM PDT 24
Finished Jul 26 07:01:33 PM PDT 24
Peak memory 208584 kb
Host smart-7755ad84-8a6d-43fe-81df-76f7440cc9a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860955983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3860955983
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2619378164
Short name T28
Test name
Test status
Simulation time 277610123 ps
CPU time 1.98 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:20 PM PDT 24
Peak memory 200156 kb
Host smart-2fc399f7-2712-46ff-9680-9a8dbea02b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619378164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2619378164
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2702916371
Short name T139
Test name
Test status
Simulation time 161438821 ps
CPU time 1.08 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 200048 kb
Host smart-c15b1e44-67ce-4f8a-b14e-c380667b0c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702916371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2702916371
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1357232334
Short name T79
Test name
Test status
Simulation time 61829073 ps
CPU time 0.75 seconds
Started Jul 26 07:01:16 PM PDT 24
Finished Jul 26 07:01:17 PM PDT 24
Peak memory 199844 kb
Host smart-acd2ee80-66fa-4983-bae1-bb6445566dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357232334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1357232334
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3606844864
Short name T539
Test name
Test status
Simulation time 2366680518 ps
CPU time 9.47 seconds
Started Jul 26 07:01:21 PM PDT 24
Finished Jul 26 07:01:31 PM PDT 24
Peak memory 221744 kb
Host smart-642f5a37-ba70-4bfa-8064-f281ad897cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606844864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3606844864
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1896074898
Short name T366
Test name
Test status
Simulation time 243823163 ps
CPU time 1.12 seconds
Started Jul 26 07:01:14 PM PDT 24
Finished Jul 26 07:01:15 PM PDT 24
Peak memory 217328 kb
Host smart-9e19127e-b4b5-4c4e-9277-4d6102fe5d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896074898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1896074898
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2412684719
Short name T24
Test name
Test status
Simulation time 209663573 ps
CPU time 0.86 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 199884 kb
Host smart-5cf98941-dccc-4d2f-af21-7449edfcd6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412684719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2412684719
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1040325999
Short name T270
Test name
Test status
Simulation time 1038503132 ps
CPU time 5.01 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 200384 kb
Host smart-98154b3b-c926-48b2-9aa0-5f63fa5cf52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040325999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1040325999
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4015279611
Short name T273
Test name
Test status
Simulation time 158661895 ps
CPU time 1.18 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 200024 kb
Host smart-310a3859-9a16-4a1f-ab95-6d408930a9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015279611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4015279611
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.640841334
Short name T352
Test name
Test status
Simulation time 253083102 ps
CPU time 1.61 seconds
Started Jul 26 07:01:10 PM PDT 24
Finished Jul 26 07:01:12 PM PDT 24
Peak memory 200252 kb
Host smart-302bafc8-bbcc-4436-962d-b5dc264f8a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640841334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.640841334
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1242790193
Short name T129
Test name
Test status
Simulation time 5574026919 ps
CPU time 18.99 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:01:38 PM PDT 24
Peak memory 200404 kb
Host smart-711af015-08e8-4246-8686-1833e78b29f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242790193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1242790193
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3378570350
Short name T250
Test name
Test status
Simulation time 451666760 ps
CPU time 2.46 seconds
Started Jul 26 07:01:16 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 200104 kb
Host smart-ddb03418-2bf3-467f-b55a-819da834c28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378570350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3378570350
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.317473545
Short name T414
Test name
Test status
Simulation time 68656423 ps
CPU time 0.8 seconds
Started Jul 26 07:01:24 PM PDT 24
Finished Jul 26 07:01:25 PM PDT 24
Peak memory 200076 kb
Host smart-fd20eebd-3d83-464c-b549-826fd703b6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317473545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.317473545
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2927053187
Short name T260
Test name
Test status
Simulation time 61786922 ps
CPU time 0.76 seconds
Started Jul 26 07:01:29 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 199888 kb
Host smart-966c7adc-d7ef-4834-9ba1-c4236b7b3ae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927053187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2927053187
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2890771642
Short name T351
Test name
Test status
Simulation time 1222616757 ps
CPU time 6.09 seconds
Started Jul 26 07:01:16 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 217768 kb
Host smart-a7f7ad3a-c872-4f44-81ac-5e4a2373da78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890771642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2890771642
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1337434566
Short name T83
Test name
Test status
Simulation time 246499580 ps
CPU time 1.03 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:22 PM PDT 24
Peak memory 217516 kb
Host smart-a9d7897a-3443-4885-ab0c-45672ae6a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337434566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1337434566
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.8103552
Short name T22
Test name
Test status
Simulation time 97155632 ps
CPU time 0.76 seconds
Started Jul 26 07:01:18 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 199892 kb
Host smart-ae0070b4-1292-4726-a312-a147f474a5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8103552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.8103552
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1328828500
Short name T218
Test name
Test status
Simulation time 1322954720 ps
CPU time 4.74 seconds
Started Jul 26 07:01:21 PM PDT 24
Finished Jul 26 07:01:27 PM PDT 24
Peak memory 200336 kb
Host smart-b84cfc91-ef22-42a9-b930-431baf8941e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328828500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1328828500
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2024193267
Short name T474
Test name
Test status
Simulation time 174482949 ps
CPU time 1.11 seconds
Started Jul 26 07:01:14 PM PDT 24
Finished Jul 26 07:01:16 PM PDT 24
Peak memory 200016 kb
Host smart-2a62f5dc-4133-4d91-acbc-2e5def73848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024193267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2024193267
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.900952019
Short name T59
Test name
Test status
Simulation time 194704181 ps
CPU time 1.28 seconds
Started Jul 26 07:01:19 PM PDT 24
Finished Jul 26 07:01:20 PM PDT 24
Peak memory 200276 kb
Host smart-2ca1f655-7797-44cf-8d65-979c69e7921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900952019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.900952019
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3285102417
Short name T378
Test name
Test status
Simulation time 156989977 ps
CPU time 1.02 seconds
Started Jul 26 07:01:17 PM PDT 24
Finished Jul 26 07:01:18 PM PDT 24
Peak memory 199852 kb
Host smart-78c63fcb-114f-46ef-afc6-3737e184b2e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285102417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3285102417
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4111766810
Short name T217
Test name
Test status
Simulation time 278867571 ps
CPU time 1.85 seconds
Started Jul 26 07:01:21 PM PDT 24
Finished Jul 26 07:01:23 PM PDT 24
Peak memory 200040 kb
Host smart-86f50f92-1f20-43c0-80d8-21e3bf88568f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111766810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4111766810
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3589598394
Short name T265
Test name
Test status
Simulation time 140068823 ps
CPU time 1.24 seconds
Started Jul 26 07:01:20 PM PDT 24
Finished Jul 26 07:01:21 PM PDT 24
Peak memory 200080 kb
Host smart-a5538fca-2037-4796-b10d-5d1eea46539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589598394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3589598394
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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