Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8539

1

T2

66

T3

72

T4

33

auto[1]

11333

1

T2

49

T3

53

T4

21

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6116	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6663	1			T1	1		T2	32		T3	47
reset_info_cp[2]	3112	1			T2	17		T3	19		T4	7
reset_info_cp[4]	4017	1			T2	38		T3	25		T4	13
reset_info_cp[8]	121	1			T3	1		T8	1		T10	1
reset_info_cp[16]	119	1			T2	1		T8	2		T13	2
reset_info_cp[32]	107	1			T14	1		T57	1		T82	2
reset_info_cp[64]	114	1			T5	1		T8	1		T40	1
reset_info_cp[128]	123	1			T3	1		T4	1		T8	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3221	1			T2	13		T3	25		T4	11
reset_info_cp[1]	auto[1]	2822	1			T2	18		T3	21		T4	9
reset_info_cp[2]	auto[0]	999	1			T2	10		T3	14		T4	5
reset_info_cp[2]	auto[1]	2113	1			T2	7		T3	5		T4	2
reset_info_cp[4]	auto[0]	1496	1			T2	24		T3	13		T4	8
reset_info_cp[4]	auto[1]	2521	1			T2	14		T3	12		T4	5
reset_info_cp[8]	auto[0]	50	1			T3	1		T8	1		T14	1
reset_info_cp[8]	auto[1]	71	1			T10	1		T12	1		T60	2
reset_info_cp[16]	auto[0]	49	1			T2	1		T8	2		T13	2
reset_info_cp[16]	auto[1]	70	1			T27	1		T28	1		T45	2
reset_info_cp[32]	auto[0]	42	1			T14	1		T57	1		T82	2
reset_info_cp[32]	auto[1]	65	1			T86	2		T87	1		T91	2
reset_info_cp[64]	auto[0]	54	1			T40	1		T42	3		T44	1
reset_info_cp[64]	auto[1]	60	1			T5	1		T8	1		T27	1
reset_info_cp[128]	auto[0]	52	1			T3	1		T8	1		T14	2
reset_info_cp[128]	auto[1]	71	1			T4	1		T8	1		T10	1