Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8581

1

T2

73

T3

70

T4

27

auto[1]

11291

1

T2

42

T3

55

T4

27

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6116	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6663	1			T1	1		T2	32		T3	47
reset_info_cp[2]	3112	1			T2	17		T3	19		T4	7
reset_info_cp[4]	4017	1			T2	38		T3	25		T4	13
reset_info_cp[8]	121	1			T3	1		T8	1		T10	1
reset_info_cp[16]	119	1			T2	1		T8	2		T13	2
reset_info_cp[32]	107	1			T14	1		T57	1		T82	2
reset_info_cp[64]	114	1			T5	1		T8	1		T40	1
reset_info_cp[128]	123	1			T3	1		T4	1		T8	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3198	1			T2	19		T3	23		T4	8
reset_info_cp[1]	auto[1]	2845	1			T2	12		T3	23		T4	12
reset_info_cp[2]	auto[0]	1024	1			T2	11		T3	8		T4	5
reset_info_cp[2]	auto[1]	2088	1			T2	6		T3	11		T4	2
reset_info_cp[4]	auto[0]	1490	1			T2	19		T3	16		T4	6
reset_info_cp[4]	auto[1]	2527	1			T2	19		T3	9		T4	7
reset_info_cp[8]	auto[0]	46	1			T3	1		T14	1		T42	2
reset_info_cp[8]	auto[1]	75	1			T8	1		T10	1		T12	1
reset_info_cp[16]	auto[0]	53	1			T8	2		T14	2		T40	2
reset_info_cp[16]	auto[1]	66	1			T2	1		T13	2		T49	1
reset_info_cp[32]	auto[0]	47	1			T14	1		T57	1		T82	2
reset_info_cp[32]	auto[1]	60	1			T86	3		T91	1		T92	1
reset_info_cp[64]	auto[0]	51	1			T40	1		T42	3		T44	1
reset_info_cp[64]	auto[1]	63	1			T5	1		T8	1		T27	1
reset_info_cp[128]	auto[0]	49	1			T14	2		T82	1		T87	1
reset_info_cp[128]	auto[1]	74	1			T3	1		T4	1		T8	2