Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T542 /workspace/coverage/default/5.rstmgr_stress_all.560506536 Jul 27 05:58:44 PM PDT 24 Jul 27 05:58:45 PM PDT 24 91359625 ps
T543 /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.197895967 Jul 27 05:59:33 PM PDT 24 Jul 27 05:59:34 PM PDT 24 239121104 ps
T544 /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3218977362 Jul 27 05:59:21 PM PDT 24 Jul 27 05:59:23 PM PDT 24 140913804 ps
T545 /workspace/coverage/default/45.rstmgr_alert_test.3770998530 Jul 27 05:59:45 PM PDT 24 Jul 27 05:59:46 PM PDT 24 68787809 ps
T546 /workspace/coverage/default/34.rstmgr_stress_all.3589139797 Jul 27 05:59:20 PM PDT 24 Jul 27 05:59:31 PM PDT 24 2322839229 ps
T64 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1682373531 Jul 27 05:58:18 PM PDT 24 Jul 27 05:58:21 PM PDT 24 894796544 ps
T65 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2396885794 Jul 27 05:58:34 PM PDT 24 Jul 27 05:58:36 PM PDT 24 237481086 ps
T66 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4037512134 Jul 27 05:58:16 PM PDT 24 Jul 27 05:58:17 PM PDT 24 62663293 ps
T106 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3505741656 Jul 27 05:58:48 PM PDT 24 Jul 27 05:58:49 PM PDT 24 134997698 ps
T107 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2174018992 Jul 27 05:58:25 PM PDT 24 Jul 27 05:58:27 PM PDT 24 121148324 ps
T67 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1371562560 Jul 27 05:58:27 PM PDT 24 Jul 27 05:58:28 PM PDT 24 140374865 ps
T132 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2701662641 Jul 27 05:58:08 PM PDT 24 Jul 27 05:58:16 PM PDT 24 1569493793 ps
T547 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2973027446 Jul 27 05:58:11 PM PDT 24 Jul 27 05:58:13 PM PDT 24 250957263 ps
T68 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.631262638 Jul 27 05:58:11 PM PDT 24 Jul 27 05:58:13 PM PDT 24 425027158 ps
T69 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2483869175 Jul 27 05:58:22 PM PDT 24 Jul 27 05:58:24 PM PDT 24 210361612 ps
T70 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3989759175 Jul 27 05:58:16 PM PDT 24 Jul 27 05:58:18 PM PDT 24 107114316 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1242492344 Jul 27 05:58:11 PM PDT 24 Jul 27 05:58:12 PM PDT 24 92122845 ps
T71 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.527950054 Jul 27 05:58:34 PM PDT 24 Jul 27 05:58:36 PM PDT 24 178276591 ps
T108 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1714283224 Jul 27 05:58:15 PM PDT 24 Jul 27 05:58:16 PM PDT 24 75906013 ps
T72 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.935649621 Jul 27 05:58:21 PM PDT 24 Jul 27 05:58:23 PM PDT 24 407657655 ps
T109 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3622412460 Jul 27 05:58:13 PM PDT 24 Jul 27 05:58:14 PM PDT 24 74865062 ps
T97 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2740248255 Jul 27 05:58:19 PM PDT 24 Jul 27 05:58:21 PM PDT 24 490825052 ps
T93 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.602960756 Jul 27 05:58:15 PM PDT 24 Jul 27 05:58:17 PM PDT 24 260068842 ps
T110 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1740601204 Jul 27 05:58:16 PM PDT 24 Jul 27 05:58:17 PM PDT 24 58573862 ps
T94 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.570300732 Jul 27 05:58:15 PM PDT 24 Jul 27 05:58:16 PM PDT 24 99532675 ps
T98 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.803305735 Jul 27 05:58:55 PM PDT 24 Jul 27 05:58:57 PM PDT 24 494668876 ps
T111 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.701662021 Jul 27 05:58:14 PM PDT 24 Jul 27 05:58:16 PM PDT 24 287038877 ps
T549 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.547889720 Jul 27 05:58:30 PM PDT 24 Jul 27 05:58:31 PM PDT 24 73648996 ps
T95 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.524323376 Jul 27 05:58:21 PM PDT 24 Jul 27 05:58:22 PM PDT 24 183115739 ps
T96 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3077511498 Jul 27 05:58:22 PM PDT 24 Jul 27 05:58:25 PM PDT 24 393279939 ps
T130 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3993193418 Jul 27 05:58:13 PM PDT 24 Jul 27 05:58:15 PM PDT 24 442532618 ps
T99 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.951655101 Jul 27 05:58:16 PM PDT 24 Jul 27 05:58:18 PM PDT 24 175653249 ps
T100 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2780036657 Jul 27 05:58:24 PM PDT 24 Jul 27 05:58:25 PM PDT 24 159870492 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.946671810 Jul 27 05:58:09 PM PDT 24 Jul 27 05:58:10 PM PDT 24 100490013 ps
T551 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1049075762 Jul 27 05:58:13 PM PDT 24 Jul 27 05:58:14 PM PDT 24 108029586 ps
T123 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2783952305 Jul 27 05:58:40 PM PDT 24 Jul 27 05:58:43 PM PDT 24 800244902 ps
T552 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2639670128 Jul 27 05:58:09 PM PDT 24 Jul 27 05:58:15 PM PDT 24 491536271 ps
T101 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1890112291 Jul 27 05:58:22 PM PDT 24 Jul 27 05:58:24 PM PDT 24 227078771 ps
T102 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.297925175 Jul 27 05:58:20 PM PDT 24 Jul 27 05:58:21 PM PDT 24 119067173 ps
T112 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4058248058 Jul 27 05:58:27 PM PDT 24 Jul 27 05:58:28 PM PDT 24 69487055 ps
T113 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.434043081 Jul 27 05:58:17 PM PDT 24 Jul 27 05:58:18 PM PDT 24 82325823 ps
T553 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.444952375 Jul 27 05:58:08 PM PDT 24 Jul 27 05:58:11 PM PDT 24 269399637 ps
T121 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1258702921 Jul 27 05:58:06 PM PDT 24 Jul 27 05:58:08 PM PDT 24 473692950 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4144044401 Jul 27 05:58:26 PM PDT 24 Jul 27 05:58:27 PM PDT 24 95656204 ps
T555 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2180579774 Jul 27 05:58:07 PM PDT 24 Jul 27 05:58:08 PM PDT 24 125706015 ps
T124 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3016485954 Jul 27 05:58:16 PM PDT 24 Jul 27 05:58:20 PM PDT 24 904582268 ps
T556 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.609127506 Jul 27 05:58:25 PM PDT 24 Jul 27 05:58:26 PM PDT 24 102117403 ps
T114 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.186550169 Jul 27 05:58:39 PM PDT 24 Jul 27 05:58:41 PM PDT 24 231959011 ps
T557 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4015362200 Jul 27 05:58:22 PM PDT 24 Jul 27 05:58:23 PM PDT 24 283905379 ps
T558 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.325919516 Jul 27 05:58:46 PM PDT 24 Jul 27 05:58:48 PM PDT 24 509748301 ps
T559 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2656424352 Jul 27 05:58:18 PM PDT 24 Jul 27 05:58:20 PM PDT 24 181245471 ps
T115 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.772037844 Jul 27 05:58:19 PM PDT 24 Jul 27 05:58:23 PM PDT 24 423918083 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3002727091 Jul 27 05:58:07 PM PDT 24 Jul 27 05:58:08 PM PDT 24 70372824 ps
T116 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2561419074 Jul 27 05:58:12 PM PDT 24 Jul 27 05:58:14 PM PDT 24 118247756 ps
T561 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3781049724 Jul 27 05:58:16 PM PDT 24 Jul 27 05:58:18 PM PDT 24 208322896 ps
T562 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1080099765 Jul 27 05:58:05 PM PDT 24 Jul 27 05:58:06 PM PDT 24 84911364 ps
T563 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.400288133 Jul 27 05:58:28 PM PDT 24 Jul 27 05:58:29 PM PDT 24 116605480 ps
T564 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3439858224 Jul 27 05:58:19 PM PDT 24 Jul 27 05:58:20 PM PDT 24 102277735 ps
T117 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1360466708 Jul 27 05:58:24 PM PDT 24 Jul 27 05:58:26 PM PDT 24 461042144 ps
T565 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.103002973 Jul 27 05:58:27 PM PDT 24 Jul 27 05:58:28 PM PDT 24 112818385 ps
T566 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2994834370 Jul 27 05:58:22 PM PDT 24 Jul 27 05:58:23 PM PDT 24 89538340 ps
T567 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1908864572 Jul 27 05:58:39 PM PDT 24 Jul 27 05:58:40 PM PDT 24 125990098 ps
T568 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3664562698 Jul 27 05:58:12 PM PDT 24 Jul 27 05:58:14 PM PDT 24 257565875 ps
T569 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1474186774 Jul 27 05:58:17 PM PDT 24 Jul 27 05:58:19 PM PDT 24 482279600 ps
T570 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2810125151 Jul 27 05:58:23 PM PDT 24 Jul 27 05:58:25 PM PDT 24 204659874 ps
T571 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3691014222 Jul 27 05:58:34 PM PDT 24 Jul 27 05:58:35 PM PDT 24 78108506 ps
T118 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1590371237 Jul 27 05:58:13 PM PDT 24 Jul 27 05:58:16 PM PDT 24 359575905 ps
T572 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2935052733 Jul 27 05:58:14 PM PDT 24 Jul 27 05:58:16 PM PDT 24 525741455 ps
T573 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2055281924 Jul 27 05:58:19 PM PDT 24 Jul 27 05:58:21 PM PDT 24 263410410 ps
T122 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1882123812 Jul 27 05:58:09 PM PDT 24 Jul 27 05:58:10 PM PDT 24 425113045 ps
T574 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.575507844 Jul 27 05:58:13 PM PDT 24 Jul 27 05:58:14 PM PDT 24 105366027 ps
T119 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2332963780 Jul 27 05:58:15 PM PDT 24 Jul 27 05:58:17 PM PDT 24 487202680 ps
T575 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3521315232 Jul 27 05:58:11 PM PDT 24 Jul 27 05:58:12 PM PDT 24 59156607 ps
T576 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2873554665 Jul 27 05:58:16 PM PDT 24 Jul 27 05:58:19 PM PDT 24 176233359 ps
T577 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.124661661 Jul 27 05:58:18 PM PDT 24 Jul 27 05:58:20 PM PDT 24 136491088 ps
T578 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3569679363 Jul 27 05:58:11 PM PDT 24 Jul 27 05:58:12 PM PDT 24 104859147 ps
T579 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4289019351 Jul 27 05:58:26 PM PDT 24 Jul 27 05:58:28 PM PDT 24 244948040 ps
T131 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2555404098 Jul 27 05:58:24 PM PDT 24 Jul 27 05:58:26 PM PDT 24 496415416 ps
T580 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3894930502 Jul 27 05:58:13 PM PDT 24 Jul 27 05:58:16 PM PDT 24 412280681 ps
T581 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3675491990 Jul 27 05:58:34 PM PDT 24 Jul 27 05:58:36 PM PDT 24 464414954 ps
T582 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1126344625 Jul 27 05:58:21 PM PDT 24 Jul 27 05:58:21 PM PDT 24 58361334 ps
T583 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3066481745 Jul 27 05:58:20 PM PDT 24 Jul 27 05:58:21 PM PDT 24 135116101 ps
T584 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3934197689 Jul 27 05:58:20 PM PDT 24 Jul 27 05:58:21 PM PDT 24 66157391 ps
T585 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1926292797 Jul 27 05:58:20 PM PDT 24 Jul 27 05:58:22 PM PDT 24 123706853 ps
T120 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3802603965 Jul 27 05:58:18 PM PDT 24 Jul 27 05:58:20 PM PDT 24 482916292 ps
T586 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2842111156 Jul 27 05:58:12 PM PDT 24 Jul 27 05:58:13 PM PDT 24 86450184 ps
T587 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4080016340 Jul 27 05:58:43 PM PDT 24 Jul 27 05:58:45 PM PDT 24 156996990 ps
T588 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2352099509 Jul 27 05:58:19 PM PDT 24 Jul 27 05:58:20 PM PDT 24 76573054 ps
T589 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3349855868 Jul 27 05:58:13 PM PDT 24 Jul 27 05:58:14 PM PDT 24 190698385 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2046985076 Jul 27 05:58:15 PM PDT 24 Jul 27 05:58:16 PM PDT 24 90039293 ps
T591 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3872022562 Jul 27 05:58:18 PM PDT 24 Jul 27 05:58:20 PM PDT 24 126038608 ps
T592 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3502740694 Jul 27 05:58:24 PM PDT 24 Jul 27 05:58:26 PM PDT 24 190857177 ps
T593 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4104200853 Jul 27 05:58:40 PM PDT 24 Jul 27 05:58:41 PM PDT 24 87237788 ps
T594 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.958401152 Jul 27 05:58:16 PM PDT 24 Jul 27 05:58:19 PM PDT 24 147689998 ps
T595 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.472793749 Jul 27 05:58:21 PM PDT 24 Jul 27 05:58:22 PM PDT 24 66247090 ps
T596 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2823350621 Jul 27 05:58:16 PM PDT 24 Jul 27 05:58:18 PM PDT 24 178365037 ps
T597 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1433801755 Jul 27 05:58:27 PM PDT 24 Jul 27 05:58:31 PM PDT 24 548110673 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4226539323 Jul 27 05:58:11 PM PDT 24 Jul 27 05:58:14 PM PDT 24 348911116 ps
T599 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2818593012 Jul 27 05:58:14 PM PDT 24 Jul 27 05:58:15 PM PDT 24 151707094 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3545551276 Jul 27 05:58:14 PM PDT 24 Jul 27 05:58:18 PM PDT 24 276240547 ps
T601 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2352058183 Jul 27 05:58:07 PM PDT 24 Jul 27 05:58:08 PM PDT 24 98397150 ps
T602 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.845159610 Jul 27 05:58:23 PM PDT 24 Jul 27 05:58:25 PM PDT 24 422869716 ps
T603 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2334713911 Jul 27 05:58:08 PM PDT 24 Jul 27 05:58:14 PM PDT 24 1172699998 ps
T604 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.565825346 Jul 27 05:58:38 PM PDT 24 Jul 27 05:58:39 PM PDT 24 117619623 ps
T605 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2837422935 Jul 27 05:58:07 PM PDT 24 Jul 27 05:58:08 PM PDT 24 192080539 ps
T606 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3300228173 Jul 27 05:58:28 PM PDT 24 Jul 27 05:58:31 PM PDT 24 807069954 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2332621979 Jul 27 05:58:12 PM PDT 24 Jul 27 05:58:14 PM PDT 24 237112577 ps
T608 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3412084030 Jul 27 05:58:18 PM PDT 24 Jul 27 05:58:20 PM PDT 24 319116877 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.723303172 Jul 27 05:58:07 PM PDT 24 Jul 27 05:58:10 PM PDT 24 169620097 ps
T610 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1062055721 Jul 27 05:58:13 PM PDT 24 Jul 27 05:58:14 PM PDT 24 63854826 ps
T611 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1003398213 Jul 27 05:58:38 PM PDT 24 Jul 27 05:58:39 PM PDT 24 56165815 ps
T612 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4259902202 Jul 27 05:58:18 PM PDT 24 Jul 27 05:58:20 PM PDT 24 196441944 ps
T613 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3663571826 Jul 27 05:58:07 PM PDT 24 Jul 27 05:58:09 PM PDT 24 230950051 ps
T614 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1746725660 Jul 27 05:58:37 PM PDT 24 Jul 27 05:58:39 PM PDT 24 324366829 ps
T615 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1403841685 Jul 27 05:58:06 PM PDT 24 Jul 27 05:58:07 PM PDT 24 91915606 ps
T616 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3282591755 Jul 27 05:58:14 PM PDT 24 Jul 27 05:58:17 PM PDT 24 292987440 ps
T617 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2376293084 Jul 27 05:58:20 PM PDT 24 Jul 27 05:58:21 PM PDT 24 203983914 ps
T618 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4050265491 Jul 27 05:58:19 PM PDT 24 Jul 27 05:58:22 PM PDT 24 152285766 ps
T619 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.276484859 Jul 27 05:58:26 PM PDT 24 Jul 27 05:58:27 PM PDT 24 81106400 ps
T620 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1922051647 Jul 27 05:58:19 PM PDT 24 Jul 27 05:58:20 PM PDT 24 152957988 ps

Test location /workspace/coverage/default/43.rstmgr_stress_all.3335585800
Short name T8
Test name
Test status
Simulation time 4236654712 ps
CPU time 15.39 seconds
Started Jul 27 05:59:39 PM PDT 24
Finished Jul 27 05:59:55 PM PDT 24
Peak memory 208668 kb
Host smart-308d4ccc-a1d7-44c7-af6b-7895c15c4771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335585800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3335585800
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3392387418
Short name T63
Test name
Test status
Simulation time 391833639 ps
CPU time 2.51 seconds
Started Jul 27 05:59:23 PM PDT 24
Finished Jul 27 05:59:25 PM PDT 24
Peak memory 200132 kb
Host smart-d743ccf9-3a3f-4419-9551-1747c994aaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392387418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3392387418
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.527950054
Short name T71
Test name
Test status
Simulation time 178276591 ps
CPU time 1.8 seconds
Started Jul 27 05:58:34 PM PDT 24
Finished Jul 27 05:58:36 PM PDT 24
Peak memory 208208 kb
Host smart-31ab2fb1-7ead-4776-bbc0-a88f797cc752
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527950054 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.527950054
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.88661262
Short name T48
Test name
Test status
Simulation time 16513001331 ps
CPU time 30.93 seconds
Started Jul 27 05:58:29 PM PDT 24
Finished Jul 27 05:59:00 PM PDT 24
Peak memory 217672 kb
Host smart-c0c80d40-6bfb-42c2-9ca8-923ffbb3cb0a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88661262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.88661262
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.728853366
Short name T12
Test name
Test status
Simulation time 1224798805 ps
CPU time 5.95 seconds
Started Jul 27 05:58:49 PM PDT 24
Finished Jul 27 05:58:55 PM PDT 24
Peak memory 221776 kb
Host smart-02e49db6-6926-42d1-886d-1a32e0616b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728853366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.728853366
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1682373531
Short name T64
Test name
Test status
Simulation time 894796544 ps
CPU time 3.07 seconds
Started Jul 27 05:58:18 PM PDT 24
Finished Jul 27 05:58:21 PM PDT 24
Peak memory 200052 kb
Host smart-7087ab33-ac82-484e-af16-bae7ab423bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682373531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1682373531
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1692679955
Short name T92
Test name
Test status
Simulation time 7748214021 ps
CPU time 32.93 seconds
Started Jul 27 05:58:50 PM PDT 24
Finished Jul 27 05:59:23 PM PDT 24
Peak memory 200384 kb
Host smart-53f5e652-9f66-41d1-b530-ed67c85d216d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692679955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1692679955
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2755161407
Short name T45
Test name
Test status
Simulation time 1899828940 ps
CPU time 7.21 seconds
Started Jul 27 05:59:17 PM PDT 24
Finished Jul 27 05:59:25 PM PDT 24
Peak memory 217596 kb
Host smart-c0c4d153-afe6-4957-8f13-2b09c361614b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755161407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2755161407
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1292984423
Short name T154
Test name
Test status
Simulation time 98067740 ps
CPU time 0.97 seconds
Started Jul 27 05:59:02 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 200100 kb
Host smart-52dc287a-949d-4fc7-8fca-fda36b524376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292984423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1292984423
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2609284454
Short name T153
Test name
Test status
Simulation time 81452801 ps
CPU time 0.8 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 199920 kb
Host smart-e3e7cec3-5225-47e3-8e25-773a662af09e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609284454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2609284454
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3300228173
Short name T606
Test name
Test status
Simulation time 807069954 ps
CPU time 2.99 seconds
Started Jul 27 05:58:28 PM PDT 24
Finished Jul 27 05:58:31 PM PDT 24
Peak memory 200060 kb
Host smart-25968395-d01e-4fb8-8419-ce7def75b2a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300228173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3300228173
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4080016340
Short name T587
Test name
Test status
Simulation time 156996990 ps
CPU time 2.09 seconds
Started Jul 27 05:58:43 PM PDT 24
Finished Jul 27 05:58:45 PM PDT 24
Peak memory 208184 kb
Host smart-345ac720-b52d-4a6a-8948-2bc3fea380c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080016340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4080016340
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3916472359
Short name T128
Test name
Test status
Simulation time 2045047611 ps
CPU time 8.18 seconds
Started Jul 27 05:59:18 PM PDT 24
Finished Jul 27 05:59:26 PM PDT 24
Peak memory 200352 kb
Host smart-e321cc46-abce-4883-9b7b-8cb1f5527088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916472359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3916472359
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1180349295
Short name T53
Test name
Test status
Simulation time 1895710040 ps
CPU time 7.13 seconds
Started Jul 27 05:58:34 PM PDT 24
Finished Jul 27 05:58:42 PM PDT 24
Peak memory 217340 kb
Host smart-ff38616c-db0d-45a1-a98c-1420f4ba4adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180349295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1180349295
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.845159610
Short name T602
Test name
Test status
Simulation time 422869716 ps
CPU time 1.82 seconds
Started Jul 27 05:58:23 PM PDT 24
Finished Jul 27 05:58:25 PM PDT 24
Peak memory 200136 kb
Host smart-20eee9e4-81c4-4b63-a924-fc7a1257ecc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845159610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.845159610
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.892176999
Short name T57
Test name
Test status
Simulation time 216288164 ps
CPU time 1.34 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:58:55 PM PDT 24
Peak memory 200140 kb
Host smart-f82dd6bf-8bed-4783-beab-7e891b6b13ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892176999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.892176999
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.803305735
Short name T98
Test name
Test status
Simulation time 494668876 ps
CPU time 1.83 seconds
Started Jul 27 05:58:55 PM PDT 24
Finished Jul 27 05:58:57 PM PDT 24
Peak memory 199780 kb
Host smart-fa1fed9e-5a35-4887-9fdf-c75e0ba64ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803305735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.803305735
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3622412460
Short name T109
Test name
Test status
Simulation time 74865062 ps
CPU time 0.85 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 199756 kb
Host smart-6f1e2167-c157-46a6-a966-2b86841f29dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622412460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3622412460
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.652221487
Short name T17
Test name
Test status
Simulation time 87784152 ps
CPU time 0.75 seconds
Started Jul 27 05:58:31 PM PDT 24
Finished Jul 27 05:58:32 PM PDT 24
Peak memory 199936 kb
Host smart-07c19c81-feb9-4106-ba53-dbf6f8a721c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652221487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.652221487
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1589524713
Short name T105
Test name
Test status
Simulation time 1440032419 ps
CPU time 5.58 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:54 PM PDT 24
Peak memory 200440 kb
Host smart-e97dd7bb-9c35-40a8-8d19-ce5cbfb34506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589524713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1589524713
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4226539323
Short name T598
Test name
Test status
Simulation time 348911116 ps
CPU time 2.36 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 208180 kb
Host smart-0dff11ae-e1be-40e3-b7f6-8ac16aa1d74a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226539323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
226539323
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.444952375
Short name T553
Test name
Test status
Simulation time 269399637 ps
CPU time 3.3 seconds
Started Jul 27 05:58:08 PM PDT 24
Finished Jul 27 05:58:11 PM PDT 24
Peak memory 200076 kb
Host smart-8f2668a3-ba52-404a-884f-b51798a1dbe4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444952375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.444952375
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.946671810
Short name T550
Test name
Test status
Simulation time 100490013 ps
CPU time 0.83 seconds
Started Jul 27 05:58:09 PM PDT 24
Finished Jul 27 05:58:10 PM PDT 24
Peak memory 199760 kb
Host smart-d9f5d15f-a2b6-46f8-866f-9f30353958e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946671810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.946671810
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.575507844
Short name T574
Test name
Test status
Simulation time 105366027 ps
CPU time 0.9 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 199836 kb
Host smart-dbcc997c-3977-45cd-a325-ff76b19c8e16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575507844 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.575507844
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3664562698
Short name T568
Test name
Test status
Simulation time 257565875 ps
CPU time 1.54 seconds
Started Jul 27 05:58:12 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 208232 kb
Host smart-1fe53b54-fac8-45e7-8317-bb4ee88faa06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664562698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3664562698
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3663571826
Short name T613
Test name
Test status
Simulation time 230950051 ps
CPU time 1.63 seconds
Started Jul 27 05:58:07 PM PDT 24
Finished Jul 27 05:58:09 PM PDT 24
Peak memory 199976 kb
Host smart-a281f165-6b4d-4359-b089-60641154bee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663571826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3663571826
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2935052733
Short name T572
Test name
Test status
Simulation time 525741455 ps
CPU time 2 seconds
Started Jul 27 05:58:14 PM PDT 24
Finished Jul 27 05:58:16 PM PDT 24
Peak memory 200016 kb
Host smart-6402e4cd-709a-4d0c-96e8-7e0f0ed061a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935052733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2935052733
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3569679363
Short name T578
Test name
Test status
Simulation time 104859147 ps
CPU time 1.34 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:12 PM PDT 24
Peak memory 199988 kb
Host smart-453bbe2c-bfac-4769-b777-888e58e50ab9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569679363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
569679363
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3545551276
Short name T600
Test name
Test status
Simulation time 276240547 ps
CPU time 3.3 seconds
Started Jul 27 05:58:14 PM PDT 24
Finished Jul 27 05:58:18 PM PDT 24
Peak memory 199980 kb
Host smart-25681afb-c608-4818-a5cf-a361ea6bb31a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545551276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
545551276
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2352058183
Short name T601
Test name
Test status
Simulation time 98397150 ps
CPU time 0.9 seconds
Started Jul 27 05:58:07 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 199844 kb
Host smart-fad06d6f-7c26-4f20-b1b5-c6b0e18a9072
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352058183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
352058183
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3349855868
Short name T589
Test name
Test status
Simulation time 190698385 ps
CPU time 1.24 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 208124 kb
Host smart-f44125f8-f634-48b9-a839-bd75a71d06fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349855868 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3349855868
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4144044401
Short name T554
Test name
Test status
Simulation time 95656204 ps
CPU time 0.87 seconds
Started Jul 27 05:58:26 PM PDT 24
Finished Jul 27 05:58:27 PM PDT 24
Peak memory 199776 kb
Host smart-bf0eeae0-df39-410f-901b-5d46d600e68d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144044401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.4144044401
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3502740694
Short name T592
Test name
Test status
Simulation time 190857177 ps
CPU time 1.42 seconds
Started Jul 27 05:58:24 PM PDT 24
Finished Jul 27 05:58:26 PM PDT 24
Peak memory 199960 kb
Host smart-22c31e9b-45cd-4926-9770-200769cadb46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502740694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3502740694
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.602960756
Short name T93
Test name
Test status
Simulation time 260068842 ps
CPU time 2.03 seconds
Started Jul 27 05:58:15 PM PDT 24
Finished Jul 27 05:58:17 PM PDT 24
Peak memory 216384 kb
Host smart-92a3c4a8-78f0-4005-8c22-13e092ddd0a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602960756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.602960756
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.631262638
Short name T68
Test name
Test status
Simulation time 425027158 ps
CPU time 1.85 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 200148 kb
Host smart-a960a1d7-a573-41ec-bb44-e87e8bf5d4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631262638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
631262638
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2780036657
Short name T100
Test name
Test status
Simulation time 159870492 ps
CPU time 1.55 seconds
Started Jul 27 05:58:24 PM PDT 24
Finished Jul 27 05:58:25 PM PDT 24
Peak memory 208368 kb
Host smart-d63d8091-d9a4-4743-8a7a-89170a92b5c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780036657 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2780036657
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4104200853
Short name T593
Test name
Test status
Simulation time 87237788 ps
CPU time 0.89 seconds
Started Jul 27 05:58:40 PM PDT 24
Finished Jul 27 05:58:41 PM PDT 24
Peak memory 199768 kb
Host smart-6968d13a-ddb9-42bc-99c2-b37a1d6ab6e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104200853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4104200853
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.103002973
Short name T565
Test name
Test status
Simulation time 112818385 ps
CPU time 0.97 seconds
Started Jul 27 05:58:27 PM PDT 24
Finished Jul 27 05:58:28 PM PDT 24
Peak memory 199928 kb
Host smart-aa885730-76d3-451e-88b6-3914ce0bb59c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103002973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.103002973
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1590371237
Short name T118
Test name
Test status
Simulation time 359575905 ps
CPU time 2.6 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:16 PM PDT 24
Peak memory 208176 kb
Host smart-e5983740-a3f7-4bc1-8591-d1c7c190c379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590371237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1590371237
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1474186774
Short name T569
Test name
Test status
Simulation time 482279600 ps
CPU time 1.86 seconds
Started Jul 27 05:58:17 PM PDT 24
Finished Jul 27 05:58:19 PM PDT 24
Peak memory 200096 kb
Host smart-bee2b230-adab-4bc9-89af-5a747b621e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474186774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1474186774
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1371562560
Short name T67
Test name
Test status
Simulation time 140374865 ps
CPU time 1.09 seconds
Started Jul 27 05:58:27 PM PDT 24
Finished Jul 27 05:58:28 PM PDT 24
Peak memory 208276 kb
Host smart-1fd40623-befc-49de-8ab5-5c4c8dbbbce1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371562560 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1371562560
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1740601204
Short name T110
Test name
Test status
Simulation time 58573862 ps
CPU time 0.86 seconds
Started Jul 27 05:58:16 PM PDT 24
Finished Jul 27 05:58:17 PM PDT 24
Peak memory 199860 kb
Host smart-9853ef1c-4702-4b97-a049-f2b9fe7991d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740601204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1740601204
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.434043081
Short name T113
Test name
Test status
Simulation time 82325823 ps
CPU time 1.05 seconds
Started Jul 27 05:58:17 PM PDT 24
Finished Jul 27 05:58:18 PM PDT 24
Peak memory 199916 kb
Host smart-31c5b240-815b-4896-a70f-7bb6bd17e6ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434043081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.434043081
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1746725660
Short name T614
Test name
Test status
Simulation time 324366829 ps
CPU time 2.3 seconds
Started Jul 27 05:58:37 PM PDT 24
Finished Jul 27 05:58:39 PM PDT 24
Peak memory 208196 kb
Host smart-1231707c-8382-45f6-befa-4a27e19e20cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746725660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1746725660
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3675491990
Short name T581
Test name
Test status
Simulation time 464414954 ps
CPU time 1.81 seconds
Started Jul 27 05:58:34 PM PDT 24
Finished Jul 27 05:58:36 PM PDT 24
Peak memory 200008 kb
Host smart-4efaa28b-72f1-4fff-b423-d473f7c5c0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675491990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3675491990
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.565825346
Short name T604
Test name
Test status
Simulation time 117619623 ps
CPU time 0.96 seconds
Started Jul 27 05:58:38 PM PDT 24
Finished Jul 27 05:58:39 PM PDT 24
Peak memory 199936 kb
Host smart-76a6a924-f251-4e7c-ac5e-0791f2d31305
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565825346 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.565825346
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4037512134
Short name T66
Test name
Test status
Simulation time 62663293 ps
CPU time 0.79 seconds
Started Jul 27 05:58:16 PM PDT 24
Finished Jul 27 05:58:17 PM PDT 24
Peak memory 199712 kb
Host smart-3e649006-d507-4db8-91ad-9bc574e1cd7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037512134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.4037512134
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.701662021
Short name T111
Test name
Test status
Simulation time 287038877 ps
CPU time 1.68 seconds
Started Jul 27 05:58:14 PM PDT 24
Finished Jul 27 05:58:16 PM PDT 24
Peak memory 200000 kb
Host smart-b9b090ab-da71-46c9-b092-a51933136d9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701662021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.701662021
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2055281924
Short name T573
Test name
Test status
Simulation time 263410410 ps
CPU time 1.93 seconds
Started Jul 27 05:58:19 PM PDT 24
Finished Jul 27 05:58:21 PM PDT 24
Peak memory 216120 kb
Host smart-147b7014-b32f-421a-b7ae-834c66b7c334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055281924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2055281924
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3802603965
Short name T120
Test name
Test status
Simulation time 482916292 ps
CPU time 1.92 seconds
Started Jul 27 05:58:18 PM PDT 24
Finished Jul 27 05:58:20 PM PDT 24
Peak memory 200044 kb
Host smart-47a2d452-fdbb-4369-8242-34499e49f17e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802603965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3802603965
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1922051647
Short name T620
Test name
Test status
Simulation time 152957988 ps
CPU time 1.37 seconds
Started Jul 27 05:58:19 PM PDT 24
Finished Jul 27 05:58:20 PM PDT 24
Peak memory 208328 kb
Host smart-50cc64e9-6d21-448d-ad03-3fa028fa8205
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922051647 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1922051647
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3691014222
Short name T571
Test name
Test status
Simulation time 78108506 ps
CPU time 0.76 seconds
Started Jul 27 05:58:34 PM PDT 24
Finished Jul 27 05:58:35 PM PDT 24
Peak memory 199832 kb
Host smart-481766b9-dc52-4838-a6cb-5ffc3059eabf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691014222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3691014222
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1926292797
Short name T585
Test name
Test status
Simulation time 123706853 ps
CPU time 1.05 seconds
Started Jul 27 05:58:20 PM PDT 24
Finished Jul 27 05:58:22 PM PDT 24
Peak memory 199904 kb
Host smart-c347bedf-c323-4919-b9c1-4f927d0a9ef8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926292797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1926292797
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.772037844
Short name T115
Test name
Test status
Simulation time 423918083 ps
CPU time 3.16 seconds
Started Jul 27 05:58:19 PM PDT 24
Finished Jul 27 05:58:23 PM PDT 24
Peak memory 212360 kb
Host smart-8bd1530f-6e1a-40d7-b0c8-b3476a4c9bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772037844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.772037844
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.524323376
Short name T95
Test name
Test status
Simulation time 183115739 ps
CPU time 1.75 seconds
Started Jul 27 05:58:21 PM PDT 24
Finished Jul 27 05:58:22 PM PDT 24
Peak memory 208364 kb
Host smart-a88f526a-3bfa-4601-8ab7-1ab2aa56c90f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524323376 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.524323376
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.472793749
Short name T595
Test name
Test status
Simulation time 66247090 ps
CPU time 0.85 seconds
Started Jul 27 05:58:21 PM PDT 24
Finished Jul 27 05:58:22 PM PDT 24
Peak memory 199864 kb
Host smart-c9c56683-c90f-4039-8f4f-92b69b3fab08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472793749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.472793749
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4015362200
Short name T557
Test name
Test status
Simulation time 283905379 ps
CPU time 1.64 seconds
Started Jul 27 05:58:22 PM PDT 24
Finished Jul 27 05:58:23 PM PDT 24
Peak memory 200016 kb
Host smart-62e8734d-5244-48c1-bc6a-bbf6b3f3d8e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015362200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.4015362200
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2783952305
Short name T123
Test name
Test status
Simulation time 800244902 ps
CPU time 3 seconds
Started Jul 27 05:58:40 PM PDT 24
Finished Jul 27 05:58:43 PM PDT 24
Peak memory 199976 kb
Host smart-f5367d41-e501-41e8-a1bb-fbf68b757a27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783952305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2783952305
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2376293084
Short name T617
Test name
Test status
Simulation time 203983914 ps
CPU time 1.25 seconds
Started Jul 27 05:58:20 PM PDT 24
Finished Jul 27 05:58:21 PM PDT 24
Peak memory 208176 kb
Host smart-ce4dd11f-dff1-4b3f-bce1-2cf83681f0c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376293084 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2376293084
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4058248058
Short name T112
Test name
Test status
Simulation time 69487055 ps
CPU time 0.85 seconds
Started Jul 27 05:58:27 PM PDT 24
Finished Jul 27 05:58:28 PM PDT 24
Peak memory 199784 kb
Host smart-93ef4de1-2564-4339-a760-29dab54e20a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058248058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.4058248058
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3872022562
Short name T591
Test name
Test status
Simulation time 126038608 ps
CPU time 1.13 seconds
Started Jul 27 05:58:18 PM PDT 24
Finished Jul 27 05:58:20 PM PDT 24
Peak memory 199916 kb
Host smart-788e4cb4-cbb6-4b35-9316-feb5f490e12f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872022562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3872022562
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2656424352
Short name T559
Test name
Test status
Simulation time 181245471 ps
CPU time 1.62 seconds
Started Jul 27 05:58:18 PM PDT 24
Finished Jul 27 05:58:20 PM PDT 24
Peak memory 199948 kb
Host smart-6ecc80bb-9fd3-4803-aa40-4fbe5ab95bed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656424352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2656424352
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1890112291
Short name T101
Test name
Test status
Simulation time 227078771 ps
CPU time 1.5 seconds
Started Jul 27 05:58:22 PM PDT 24
Finished Jul 27 05:58:24 PM PDT 24
Peak memory 208372 kb
Host smart-6bfad3ce-74de-4215-814d-0ecf74afbdc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890112291 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1890112291
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2994834370
Short name T566
Test name
Test status
Simulation time 89538340 ps
CPU time 0.89 seconds
Started Jul 27 05:58:22 PM PDT 24
Finished Jul 27 05:58:23 PM PDT 24
Peak memory 199792 kb
Host smart-78d66866-57e3-4556-accf-7c0a8c7c24b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994834370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2994834370
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3066481745
Short name T583
Test name
Test status
Simulation time 135116101 ps
CPU time 1.13 seconds
Started Jul 27 05:58:20 PM PDT 24
Finished Jul 27 05:58:21 PM PDT 24
Peak memory 199920 kb
Host smart-adbc9d07-6292-405f-ac5d-8715a36b33fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066481745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3066481745
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4050265491
Short name T618
Test name
Test status
Simulation time 152285766 ps
CPU time 2.19 seconds
Started Jul 27 05:58:19 PM PDT 24
Finished Jul 27 05:58:22 PM PDT 24
Peak memory 208212 kb
Host smart-501cc4ca-22c0-46db-8e6d-5dc08c06ce45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050265491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4050265491
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.325919516
Short name T558
Test name
Test status
Simulation time 509748301 ps
CPU time 1.87 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:58:48 PM PDT 24
Peak memory 200144 kb
Host smart-790a74e6-dd1e-4bac-9a26-f2ab1ab9243b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325919516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.325919516
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.609127506
Short name T556
Test name
Test status
Simulation time 102117403 ps
CPU time 0.94 seconds
Started Jul 27 05:58:25 PM PDT 24
Finished Jul 27 05:58:26 PM PDT 24
Peak memory 208116 kb
Host smart-46408957-368b-479a-af2c-6ffae759497e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609127506 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.609127506
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2352099509
Short name T588
Test name
Test status
Simulation time 76573054 ps
CPU time 0.87 seconds
Started Jul 27 05:58:19 PM PDT 24
Finished Jul 27 05:58:20 PM PDT 24
Peak memory 199768 kb
Host smart-b4750085-9bc2-4de8-acaa-d8fbfbb036a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352099509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2352099509
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2396885794
Short name T65
Test name
Test status
Simulation time 237481086 ps
CPU time 1.57 seconds
Started Jul 27 05:58:34 PM PDT 24
Finished Jul 27 05:58:36 PM PDT 24
Peak memory 200096 kb
Host smart-3e814e1e-2ef3-4a45-8972-ea166a148ea8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396885794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2396885794
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2483869175
Short name T69
Test name
Test status
Simulation time 210361612 ps
CPU time 1.94 seconds
Started Jul 27 05:58:22 PM PDT 24
Finished Jul 27 05:58:24 PM PDT 24
Peak memory 208128 kb
Host smart-29157ff0-baed-4a2d-8dec-a9428945db1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483869175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2483869175
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.297925175
Short name T102
Test name
Test status
Simulation time 119067173 ps
CPU time 1.01 seconds
Started Jul 27 05:58:20 PM PDT 24
Finished Jul 27 05:58:21 PM PDT 24
Peak memory 199980 kb
Host smart-c03fedf1-b2c5-4ee3-b37f-0f2b0caa9ec3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297925175 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.297925175
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.547889720
Short name T549
Test name
Test status
Simulation time 73648996 ps
CPU time 0.76 seconds
Started Jul 27 05:58:30 PM PDT 24
Finished Jul 27 05:58:31 PM PDT 24
Peak memory 199768 kb
Host smart-b57ff40b-e61f-4e0b-89c0-a542a0fac5cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547889720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.547889720
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.124661661
Short name T577
Test name
Test status
Simulation time 136491088 ps
CPU time 1.12 seconds
Started Jul 27 05:58:18 PM PDT 24
Finished Jul 27 05:58:20 PM PDT 24
Peak memory 199904 kb
Host smart-c241df7c-5c1c-44e4-ad62-deea38c68d5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124661661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.124661661
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4289019351
Short name T579
Test name
Test status
Simulation time 244948040 ps
CPU time 1.64 seconds
Started Jul 27 05:58:26 PM PDT 24
Finished Jul 27 05:58:28 PM PDT 24
Peak memory 208376 kb
Host smart-66266f4a-fb81-4f59-8ed7-d3aa1ecb65d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289019351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.4289019351
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.935649621
Short name T72
Test name
Test status
Simulation time 407657655 ps
CPU time 1.73 seconds
Started Jul 27 05:58:21 PM PDT 24
Finished Jul 27 05:58:23 PM PDT 24
Peak memory 200004 kb
Host smart-5bdeffbd-f2c6-4893-b11c-4709b1565d09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935649621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.935649621
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2810125151
Short name T570
Test name
Test status
Simulation time 204659874 ps
CPU time 1.34 seconds
Started Jul 27 05:58:23 PM PDT 24
Finished Jul 27 05:58:25 PM PDT 24
Peak memory 208300 kb
Host smart-9f93d9c8-5106-4eca-bbea-c874d6d1b837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810125151 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2810125151
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1126344625
Short name T582
Test name
Test status
Simulation time 58361334 ps
CPU time 0.76 seconds
Started Jul 27 05:58:21 PM PDT 24
Finished Jul 27 05:58:21 PM PDT 24
Peak memory 199864 kb
Host smart-28a26a3c-1a53-4329-af40-c9644c5d990d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126344625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1126344625
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3505741656
Short name T106
Test name
Test status
Simulation time 134997698 ps
CPU time 1.28 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 200116 kb
Host smart-ad374474-3bc7-4b8d-9526-d539e674b552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505741656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3505741656
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3077511498
Short name T96
Test name
Test status
Simulation time 393279939 ps
CPU time 2.76 seconds
Started Jul 27 05:58:22 PM PDT 24
Finished Jul 27 05:58:25 PM PDT 24
Peak memory 208156 kb
Host smart-ed589e9d-7b5f-499c-b3cc-b9e8a5e3920e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077511498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3077511498
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2555404098
Short name T131
Test name
Test status
Simulation time 496415416 ps
CPU time 1.93 seconds
Started Jul 27 05:58:24 PM PDT 24
Finished Jul 27 05:58:26 PM PDT 24
Peak memory 200044 kb
Host smart-417fe966-4fb3-49a0-a56a-017db3ab0a25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555404098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2555404098
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3894930502
Short name T580
Test name
Test status
Simulation time 412280681 ps
CPU time 2.54 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:16 PM PDT 24
Peak memory 199944 kb
Host smart-67cb3c05-bc50-431d-8331-330920853060
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894930502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
894930502
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2334713911
Short name T603
Test name
Test status
Simulation time 1172699998 ps
CPU time 5.44 seconds
Started Jul 27 05:58:08 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 199996 kb
Host smart-7afeb880-84a1-4bd6-94a6-15541bd52be4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334713911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
334713911
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1242492344
Short name T548
Test name
Test status
Simulation time 92122845 ps
CPU time 0.81 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:12 PM PDT 24
Peak memory 199868 kb
Host smart-59c9aa81-e35e-48c0-a6d0-f9bbc6e868f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242492344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
242492344
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.951655101
Short name T99
Test name
Test status
Simulation time 175653249 ps
CPU time 1.18 seconds
Started Jul 27 05:58:16 PM PDT 24
Finished Jul 27 05:58:18 PM PDT 24
Peak memory 200012 kb
Host smart-2a0d2064-3ddf-4085-accb-3b90bb29b4fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951655101 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.951655101
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3002727091
Short name T560
Test name
Test status
Simulation time 70372824 ps
CPU time 0.89 seconds
Started Jul 27 05:58:07 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 199856 kb
Host smart-e668cd57-6ce7-4eaf-a3e7-41450cf581eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002727091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3002727091
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1080099765
Short name T562
Test name
Test status
Simulation time 84911364 ps
CPU time 1.09 seconds
Started Jul 27 05:58:05 PM PDT 24
Finished Jul 27 05:58:06 PM PDT 24
Peak memory 199856 kb
Host smart-1e9553df-db9b-4117-b71a-abb8e3ce7ca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080099765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1080099765
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.958401152
Short name T594
Test name
Test status
Simulation time 147689998 ps
CPU time 2 seconds
Started Jul 27 05:58:16 PM PDT 24
Finished Jul 27 05:58:19 PM PDT 24
Peak memory 208152 kb
Host smart-a4a54bd3-a81a-4bb1-a2cd-b206b793892f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958401152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.958401152
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1258702921
Short name T121
Test name
Test status
Simulation time 473692950 ps
CPU time 1.84 seconds
Started Jul 27 05:58:06 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 200124 kb
Host smart-2cf0ec52-276d-4d2e-b0ca-c1e5542bc330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258702921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1258702921
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2973027446
Short name T547
Test name
Test status
Simulation time 250957263 ps
CPU time 1.79 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 199964 kb
Host smart-de7216df-b1d7-41e5-9ecb-86da42aede6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973027446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
973027446
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2639670128
Short name T552
Test name
Test status
Simulation time 491536271 ps
CPU time 6.15 seconds
Started Jul 27 05:58:09 PM PDT 24
Finished Jul 27 05:58:15 PM PDT 24
Peak memory 199988 kb
Host smart-7921ad70-1eef-4ede-a277-b78df1ba3ae3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639670128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
639670128
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1049075762
Short name T551
Test name
Test status
Simulation time 108029586 ps
CPU time 0.82 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 199816 kb
Host smart-59e1b052-f1cf-42d5-910d-bd0bda6b799b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049075762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
049075762
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2180579774
Short name T555
Test name
Test status
Simulation time 125706015 ps
CPU time 1.04 seconds
Started Jul 27 05:58:07 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 208116 kb
Host smart-8d554d34-a70b-4846-a810-eb8316aca863
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180579774 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2180579774
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3934197689
Short name T584
Test name
Test status
Simulation time 66157391 ps
CPU time 0.74 seconds
Started Jul 27 05:58:20 PM PDT 24
Finished Jul 27 05:58:21 PM PDT 24
Peak memory 199760 kb
Host smart-89c0d618-7772-493e-b6fc-b5ea2bb7d176
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934197689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3934197689
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2837422935
Short name T605
Test name
Test status
Simulation time 192080539 ps
CPU time 1.43 seconds
Started Jul 27 05:58:07 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 200060 kb
Host smart-52c21bf5-9bec-4d87-b3d4-a0e740865d3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837422935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2837422935
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.723303172
Short name T609
Test name
Test status
Simulation time 169620097 ps
CPU time 2.42 seconds
Started Jul 27 05:58:07 PM PDT 24
Finished Jul 27 05:58:10 PM PDT 24
Peak memory 208156 kb
Host smart-b56c446d-5424-48d4-8f6c-d8aefdc44955
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723303172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.723303172
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3016485954
Short name T124
Test name
Test status
Simulation time 904582268 ps
CPU time 3.33 seconds
Started Jul 27 05:58:16 PM PDT 24
Finished Jul 27 05:58:20 PM PDT 24
Peak memory 200132 kb
Host smart-7bbde329-a967-4d02-9edd-1d22be76b6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016485954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3016485954
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3781049724
Short name T561
Test name
Test status
Simulation time 208322896 ps
CPU time 1.52 seconds
Started Jul 27 05:58:16 PM PDT 24
Finished Jul 27 05:58:18 PM PDT 24
Peak memory 200032 kb
Host smart-4f05ad43-574c-4c68-a967-21b1055c37a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781049724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
781049724
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2701662641
Short name T132
Test name
Test status
Simulation time 1569493793 ps
CPU time 8.12 seconds
Started Jul 27 05:58:08 PM PDT 24
Finished Jul 27 05:58:16 PM PDT 24
Peak memory 199952 kb
Host smart-4f77b504-fa37-41ce-bf2c-cb709982dd6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701662641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
701662641
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2842111156
Short name T586
Test name
Test status
Simulation time 86450184 ps
CPU time 0.82 seconds
Started Jul 27 05:58:12 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 199864 kb
Host smart-a9a66a88-bf4d-49b5-8e15-02cfbdd947a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842111156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
842111156
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.570300732
Short name T94
Test name
Test status
Simulation time 99532675 ps
CPU time 0.93 seconds
Started Jul 27 05:58:15 PM PDT 24
Finished Jul 27 05:58:16 PM PDT 24
Peak memory 199916 kb
Host smart-df0df657-744d-4ede-ad71-884030496562
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570300732 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.570300732
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1403841685
Short name T615
Test name
Test status
Simulation time 91915606 ps
CPU time 0.89 seconds
Started Jul 27 05:58:06 PM PDT 24
Finished Jul 27 05:58:07 PM PDT 24
Peak memory 199840 kb
Host smart-5857a302-8aca-4724-949f-6a698c337313
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403841685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1403841685
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2046985076
Short name T590
Test name
Test status
Simulation time 90039293 ps
CPU time 0.99 seconds
Started Jul 27 05:58:15 PM PDT 24
Finished Jul 27 05:58:16 PM PDT 24
Peak memory 199928 kb
Host smart-54d263d6-1aa3-4bde-84bf-cbb312b8b5e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046985076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2046985076
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3282591755
Short name T616
Test name
Test status
Simulation time 292987440 ps
CPU time 2.2 seconds
Started Jul 27 05:58:14 PM PDT 24
Finished Jul 27 05:58:17 PM PDT 24
Peak memory 216284 kb
Host smart-8354cd5d-7b89-4996-acba-51dd215880c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282591755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3282591755
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1882123812
Short name T122
Test name
Test status
Simulation time 425113045 ps
CPU time 1.73 seconds
Started Jul 27 05:58:09 PM PDT 24
Finished Jul 27 05:58:10 PM PDT 24
Peak memory 200080 kb
Host smart-2d036b68-c80b-4afd-86ed-c3da623e4296
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882123812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1882123812
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1714283224
Short name T108
Test name
Test status
Simulation time 75906013 ps
CPU time 0.86 seconds
Started Jul 27 05:58:15 PM PDT 24
Finished Jul 27 05:58:16 PM PDT 24
Peak memory 199784 kb
Host smart-6e4f9152-474b-426a-abee-c6fc4c64944e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714283224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1714283224
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2818593012
Short name T599
Test name
Test status
Simulation time 151707094 ps
CPU time 1.27 seconds
Started Jul 27 05:58:14 PM PDT 24
Finished Jul 27 05:58:15 PM PDT 24
Peak memory 199860 kb
Host smart-5b6cca11-cbb2-4f7f-808a-45b69d39784f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818593012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2818593012
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3989759175
Short name T70
Test name
Test status
Simulation time 107114316 ps
CPU time 1.48 seconds
Started Jul 27 05:58:16 PM PDT 24
Finished Jul 27 05:58:18 PM PDT 24
Peak memory 208188 kb
Host smart-a7d8d0ff-78d0-4d50-8637-a3c7af8061ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989759175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3989759175
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2332963780
Short name T119
Test name
Test status
Simulation time 487202680 ps
CPU time 1.98 seconds
Started Jul 27 05:58:15 PM PDT 24
Finished Jul 27 05:58:17 PM PDT 24
Peak memory 200140 kb
Host smart-b21cb59e-1f84-4463-b28c-0acbdfe93aec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332963780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2332963780
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.400288133
Short name T563
Test name
Test status
Simulation time 116605480 ps
CPU time 0.97 seconds
Started Jul 27 05:58:28 PM PDT 24
Finished Jul 27 05:58:29 PM PDT 24
Peak memory 199956 kb
Host smart-4989d50b-5452-4c0f-95bb-9dcf1a4dcd19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400288133 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.400288133
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3521315232
Short name T575
Test name
Test status
Simulation time 59156607 ps
CPU time 0.79 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:12 PM PDT 24
Peak memory 199844 kb
Host smart-93012801-1725-4680-8ce7-b91f19edf9af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521315232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3521315232
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1908864572
Short name T567
Test name
Test status
Simulation time 125990098 ps
CPU time 1.08 seconds
Started Jul 27 05:58:39 PM PDT 24
Finished Jul 27 05:58:40 PM PDT 24
Peak memory 199872 kb
Host smart-15d7bcd0-433e-4acc-b8da-aa613239c1c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908864572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1908864572
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1433801755
Short name T597
Test name
Test status
Simulation time 548110673 ps
CPU time 3.62 seconds
Started Jul 27 05:58:27 PM PDT 24
Finished Jul 27 05:58:31 PM PDT 24
Peak memory 208100 kb
Host smart-79f1efed-6004-4317-8df9-dfec73ca1856
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433801755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1433801755
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2823350621
Short name T596
Test name
Test status
Simulation time 178365037 ps
CPU time 1.73 seconds
Started Jul 27 05:58:16 PM PDT 24
Finished Jul 27 05:58:18 PM PDT 24
Peak memory 208328 kb
Host smart-58017cfa-fdb6-4e1f-8965-09cfd783ebf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823350621 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2823350621
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1003398213
Short name T611
Test name
Test status
Simulation time 56165815 ps
CPU time 0.77 seconds
Started Jul 27 05:58:38 PM PDT 24
Finished Jul 27 05:58:39 PM PDT 24
Peak memory 199688 kb
Host smart-bad819b6-f601-4628-9cb9-5067aeced305
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003398213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1003398213
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2332621979
Short name T607
Test name
Test status
Simulation time 237112577 ps
CPU time 1.54 seconds
Started Jul 27 05:58:12 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 200048 kb
Host smart-b43fa060-445f-428c-81e3-d0a30b08f2e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332621979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2332621979
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2561419074
Short name T116
Test name
Test status
Simulation time 118247756 ps
CPU time 1.68 seconds
Started Jul 27 05:58:12 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 208256 kb
Host smart-37257568-4e2e-485d-bd12-244b882dbcfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561419074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2561419074
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3993193418
Short name T130
Test name
Test status
Simulation time 442532618 ps
CPU time 1.81 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:15 PM PDT 24
Peak memory 200088 kb
Host smart-2bb5046c-9db7-405e-ba20-2a5be92f38b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993193418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3993193418
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4259902202
Short name T612
Test name
Test status
Simulation time 196441944 ps
CPU time 1.92 seconds
Started Jul 27 05:58:18 PM PDT 24
Finished Jul 27 05:58:20 PM PDT 24
Peak memory 208356 kb
Host smart-1564a47d-e854-48a6-8668-14ab59de19cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259902202 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.4259902202
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.276484859
Short name T619
Test name
Test status
Simulation time 81106400 ps
CPU time 0.86 seconds
Started Jul 27 05:58:26 PM PDT 24
Finished Jul 27 05:58:27 PM PDT 24
Peak memory 199708 kb
Host smart-541c7cf6-b830-4c63-bb9b-f99e34f22506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276484859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.276484859
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2174018992
Short name T107
Test name
Test status
Simulation time 121148324 ps
CPU time 1.3 seconds
Started Jul 27 05:58:25 PM PDT 24
Finished Jul 27 05:58:27 PM PDT 24
Peak memory 200028 kb
Host smart-9cc20946-ee9f-4638-b7cf-8105f774445f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174018992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2174018992
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3412084030
Short name T608
Test name
Test status
Simulation time 319116877 ps
CPU time 2.49 seconds
Started Jul 27 05:58:18 PM PDT 24
Finished Jul 27 05:58:20 PM PDT 24
Peak memory 208112 kb
Host smart-6207d611-a385-4a74-8112-35784c99eb1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412084030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3412084030
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2740248255
Short name T97
Test name
Test status
Simulation time 490825052 ps
CPU time 2 seconds
Started Jul 27 05:58:19 PM PDT 24
Finished Jul 27 05:58:21 PM PDT 24
Peak memory 200036 kb
Host smart-8dcfba0f-76f5-4b08-b1f0-2728223413dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740248255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2740248255
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3439858224
Short name T564
Test name
Test status
Simulation time 102277735 ps
CPU time 1 seconds
Started Jul 27 05:58:19 PM PDT 24
Finished Jul 27 05:58:20 PM PDT 24
Peak memory 208464 kb
Host smart-3d964bd5-d0f8-4957-9eea-08ff370ad5ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439858224 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3439858224
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1062055721
Short name T610
Test name
Test status
Simulation time 63854826 ps
CPU time 0.76 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 199744 kb
Host smart-24bf74fb-e7d0-4d94-b13b-709b1a129cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062055721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1062055721
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.186550169
Short name T114
Test name
Test status
Simulation time 231959011 ps
CPU time 1.56 seconds
Started Jul 27 05:58:39 PM PDT 24
Finished Jul 27 05:58:41 PM PDT 24
Peak memory 200060 kb
Host smart-bd7721fa-db9f-42cb-82f5-1a6884685386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186550169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.186550169
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2873554665
Short name T576
Test name
Test status
Simulation time 176233359 ps
CPU time 2.5 seconds
Started Jul 27 05:58:16 PM PDT 24
Finished Jul 27 05:58:19 PM PDT 24
Peak memory 208244 kb
Host smart-748c2135-e3d0-4c37-b7ba-affd793e5815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873554665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2873554665
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1360466708
Short name T117
Test name
Test status
Simulation time 461042144 ps
CPU time 2.12 seconds
Started Jul 27 05:58:24 PM PDT 24
Finished Jul 27 05:58:26 PM PDT 24
Peak memory 200104 kb
Host smart-2fd40d25-8e30-4594-b02b-a6c40841d260
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360466708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1360466708
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.333252239
Short name T347
Test name
Test status
Simulation time 74446685 ps
CPU time 0.82 seconds
Started Jul 27 05:58:38 PM PDT 24
Finished Jul 27 05:58:39 PM PDT 24
Peak memory 199884 kb
Host smart-e8491377-5d7b-4497-be59-be025b7bdccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333252239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.333252239
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4103718147
Short name T80
Test name
Test status
Simulation time 243408315 ps
CPU time 1.19 seconds
Started Jul 27 05:58:22 PM PDT 24
Finished Jul 27 05:58:23 PM PDT 24
Peak memory 217464 kb
Host smart-eeea819a-f7ba-4fa6-a896-6fe2da4f6d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103718147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4103718147
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.798514290
Short name T268
Test name
Test status
Simulation time 978752653 ps
CPU time 4.57 seconds
Started Jul 27 05:58:40 PM PDT 24
Finished Jul 27 05:58:45 PM PDT 24
Peak memory 200348 kb
Host smart-f748e45f-ffd3-436f-a259-177d4d6711eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798514290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.798514290
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2223339981
Short name T79
Test name
Test status
Simulation time 16512005826 ps
CPU time 31.21 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:59:28 PM PDT 24
Peak memory 217224 kb
Host smart-213c7389-c109-4b57-be84-d25d28aeec8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223339981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2223339981
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1263677105
Short name T300
Test name
Test status
Simulation time 105528828 ps
CPU time 1.13 seconds
Started Jul 27 05:58:30 PM PDT 24
Finished Jul 27 05:58:31 PM PDT 24
Peak memory 200092 kb
Host smart-03253949-0046-4c17-a7a0-764a89d2187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263677105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1263677105
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1693012683
Short name T522
Test name
Test status
Simulation time 111279823 ps
CPU time 1.18 seconds
Started Jul 27 05:58:36 PM PDT 24
Finished Jul 27 05:58:37 PM PDT 24
Peak memory 200312 kb
Host smart-8b50b462-0d87-494d-881e-9f4a27bddf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693012683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1693012683
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2740012205
Short name T527
Test name
Test status
Simulation time 12445376942 ps
CPU time 43.14 seconds
Started Jul 27 05:58:19 PM PDT 24
Finished Jul 27 05:59:02 PM PDT 24
Peak memory 208716 kb
Host smart-e3b7bf84-4278-4f80-9053-78c7df5979b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740012205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2740012205
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2821504371
Short name T511
Test name
Test status
Simulation time 272200286 ps
CPU time 1.99 seconds
Started Jul 27 05:58:23 PM PDT 24
Finished Jul 27 05:58:25 PM PDT 24
Peak memory 200348 kb
Host smart-c44604ca-32b4-496c-be3f-69efe46198da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821504371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2821504371
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1358017316
Short name T204
Test name
Test status
Simulation time 117108025 ps
CPU time 0.98 seconds
Started Jul 27 05:58:38 PM PDT 24
Finished Jul 27 05:58:39 PM PDT 24
Peak memory 200060 kb
Host smart-95a12f73-5729-47e9-8a09-a250bb6e7682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358017316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1358017316
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.601686326
Short name T411
Test name
Test status
Simulation time 61403885 ps
CPU time 0.73 seconds
Started Jul 27 05:58:34 PM PDT 24
Finished Jul 27 05:58:35 PM PDT 24
Peak memory 199924 kb
Host smart-5c89b188-992c-40d5-86cf-504080cf3cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601686326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.601686326
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3658120680
Short name T364
Test name
Test status
Simulation time 2361342796 ps
CPU time 8.9 seconds
Started Jul 27 05:58:43 PM PDT 24
Finished Jul 27 05:58:52 PM PDT 24
Peak memory 221832 kb
Host smart-30174357-2c5d-4885-9c4d-4745362b032c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658120680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3658120680
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4134537182
Short name T525
Test name
Test status
Simulation time 244831286 ps
CPU time 1.09 seconds
Started Jul 27 05:58:29 PM PDT 24
Finished Jul 27 05:58:30 PM PDT 24
Peak memory 217512 kb
Host smart-1299b734-25e8-4f0d-ad2d-c93a15386927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134537182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4134537182
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1561688301
Short name T425
Test name
Test status
Simulation time 187070287 ps
CPU time 0.86 seconds
Started Jul 27 05:58:35 PM PDT 24
Finished Jul 27 05:58:36 PM PDT 24
Peak memory 199836 kb
Host smart-b6abe3ee-ee80-407a-8d95-2dc5f61bbefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561688301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1561688301
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.986238510
Short name T230
Test name
Test status
Simulation time 789835933 ps
CPU time 4.22 seconds
Started Jul 27 05:58:22 PM PDT 24
Finished Jul 27 05:58:26 PM PDT 24
Peak memory 200360 kb
Host smart-3f2d959f-f341-494c-b386-73d03401b651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986238510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.986238510
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3445961533
Short name T78
Test name
Test status
Simulation time 8289306841 ps
CPU time 13.41 seconds
Started Jul 27 05:58:37 PM PDT 24
Finished Jul 27 05:58:51 PM PDT 24
Peak memory 217572 kb
Host smart-8dc63c4e-3607-47a2-8ccc-9c4b0ed77213
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445961533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3445961533
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2527559551
Short name T469
Test name
Test status
Simulation time 179780213 ps
CPU time 1.15 seconds
Started Jul 27 05:58:30 PM PDT 24
Finished Jul 27 05:58:31 PM PDT 24
Peak memory 200080 kb
Host smart-d6d5b587-32bc-462b-a50f-03e79493236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527559551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2527559551
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3191714498
Short name T184
Test name
Test status
Simulation time 123830624 ps
CPU time 1.25 seconds
Started Jul 27 05:58:23 PM PDT 24
Finished Jul 27 05:58:25 PM PDT 24
Peak memory 200336 kb
Host smart-92333016-bb95-4145-abce-50e54457b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191714498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3191714498
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1991887294
Short name T91
Test name
Test status
Simulation time 2630798590 ps
CPU time 11.85 seconds
Started Jul 27 05:58:33 PM PDT 24
Finished Jul 27 05:58:44 PM PDT 24
Peak memory 208580 kb
Host smart-ec5a6ea8-6c3d-4c08-a052-e505881262df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991887294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1991887294
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2723131446
Short name T494
Test name
Test status
Simulation time 487443564 ps
CPU time 2.67 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 208320 kb
Host smart-df107956-515d-4edf-8f2e-5d58b3d77557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723131446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2723131446
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3800065131
Short name T474
Test name
Test status
Simulation time 167286424 ps
CPU time 1.22 seconds
Started Jul 27 05:58:28 PM PDT 24
Finished Jul 27 05:58:29 PM PDT 24
Peak memory 200152 kb
Host smart-03609690-ae88-44e6-a49f-20f9742ec8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800065131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3800065131
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1844441079
Short name T395
Test name
Test status
Simulation time 77817493 ps
CPU time 0.8 seconds
Started Jul 27 05:58:54 PM PDT 24
Finished Jul 27 05:58:54 PM PDT 24
Peak memory 199932 kb
Host smart-f3421838-431e-4f62-b419-ff8019ac45a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844441079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1844441079
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3316953055
Short name T58
Test name
Test status
Simulation time 1221698412 ps
CPU time 5.92 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:14 PM PDT 24
Peak memory 217752 kb
Host smart-43e095f3-0e3d-4624-a406-4acda9f52d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316953055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3316953055
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.446583814
Short name T327
Test name
Test status
Simulation time 244070487 ps
CPU time 1.1 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 217476 kb
Host smart-6e4dbfe9-cd78-42e4-94c4-c719414af058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446583814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.446583814
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2502007772
Short name T20
Test name
Test status
Simulation time 119914007 ps
CPU time 0.77 seconds
Started Jul 27 05:58:55 PM PDT 24
Finished Jul 27 05:58:56 PM PDT 24
Peak memory 199876 kb
Host smart-5a341cc9-4d36-4683-9609-e7e8733b2a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502007772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2502007772
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2742329338
Short name T375
Test name
Test status
Simulation time 1716546692 ps
CPU time 6.74 seconds
Started Jul 27 05:59:01 PM PDT 24
Finished Jul 27 05:59:08 PM PDT 24
Peak memory 200396 kb
Host smart-6f9f52fa-643c-44ba-ad67-bd54e5c498af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742329338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2742329338
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1603680723
Short name T213
Test name
Test status
Simulation time 186030885 ps
CPU time 1.2 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:58:58 PM PDT 24
Peak memory 200120 kb
Host smart-11ff9a16-7844-4a9c-94a5-992da70019a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603680723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1603680723
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1267641090
Short name T164
Test name
Test status
Simulation time 115832862 ps
CPU time 1.19 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:58:48 PM PDT 24
Peak memory 200184 kb
Host smart-52e98ba0-3e75-4258-97ab-1eb2db93cf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267641090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1267641090
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.609958574
Short name T221
Test name
Test status
Simulation time 13168001679 ps
CPU time 45.69 seconds
Started Jul 27 05:58:57 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 208704 kb
Host smart-05050ece-6ba9-4e9c-8abf-132345d284c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609958574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.609958574
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2179067622
Short name T90
Test name
Test status
Simulation time 130482831 ps
CPU time 1.52 seconds
Started Jul 27 05:58:45 PM PDT 24
Finished Jul 27 05:58:47 PM PDT 24
Peak memory 200188 kb
Host smart-32de6009-425c-40a7-a2ec-6c5100ae582a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179067622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2179067622
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2330675845
Short name T371
Test name
Test status
Simulation time 139734660 ps
CPU time 1.16 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:58:57 PM PDT 24
Peak memory 200312 kb
Host smart-334465d1-29e3-42d9-a094-5c14a11a7214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330675845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2330675845
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3304155274
Short name T402
Test name
Test status
Simulation time 245071625 ps
CPU time 1.06 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 218372 kb
Host smart-9e15b944-2549-41e5-9758-516eb26188ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304155274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3304155274
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.412115902
Short name T275
Test name
Test status
Simulation time 94526049 ps
CPU time 0.76 seconds
Started Jul 27 05:59:06 PM PDT 24
Finished Jul 27 05:59:07 PM PDT 24
Peak memory 199916 kb
Host smart-0cf36761-b1ea-4fd4-b8e2-631790cdf864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412115902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.412115902
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1400923693
Short name T449
Test name
Test status
Simulation time 177988746 ps
CPU time 1.19 seconds
Started Jul 27 05:59:01 PM PDT 24
Finished Jul 27 05:59:02 PM PDT 24
Peak memory 200016 kb
Host smart-f7160b84-fa7c-49e8-a0f1-90ec1a2d6f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400923693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1400923693
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3761547463
Short name T5
Test name
Test status
Simulation time 127744206 ps
CPU time 1.25 seconds
Started Jul 27 05:58:54 PM PDT 24
Finished Jul 27 05:58:55 PM PDT 24
Peak memory 200384 kb
Host smart-01d01d45-6321-4700-aaed-19c586d234ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761547463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3761547463
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2574281570
Short name T479
Test name
Test status
Simulation time 648785533 ps
CPU time 3.13 seconds
Started Jul 27 05:58:49 PM PDT 24
Finished Jul 27 05:58:52 PM PDT 24
Peak memory 200364 kb
Host smart-f62bb46c-20f5-4a8b-ad7b-3df5e4b5bb19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574281570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2574281570
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.745823093
Short name T193
Test name
Test status
Simulation time 364622688 ps
CPU time 2.28 seconds
Started Jul 27 05:59:01 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 200092 kb
Host smart-42c554a1-2212-4fdf-a756-334bc9148382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745823093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.745823093
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3929376926
Short name T224
Test name
Test status
Simulation time 139162572 ps
CPU time 1.12 seconds
Started Jul 27 05:59:03 PM PDT 24
Finished Jul 27 05:59:05 PM PDT 24
Peak memory 200092 kb
Host smart-3129e2be-a9e8-48f3-a699-ed33563dfe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929376926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3929376926
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.85433031
Short name T388
Test name
Test status
Simulation time 61957901 ps
CPU time 0.75 seconds
Started Jul 27 05:58:47 PM PDT 24
Finished Jul 27 05:58:48 PM PDT 24
Peak memory 199912 kb
Host smart-593df060-f39f-4c3a-bbce-c9848242a0b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85433031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.85433031
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2004125997
Short name T508
Test name
Test status
Simulation time 2352921045 ps
CPU time 8.34 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:56 PM PDT 24
Peak memory 217804 kb
Host smart-af2df034-6194-4b59-91ba-1631a6a3a6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004125997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2004125997
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1533296893
Short name T369
Test name
Test status
Simulation time 244742507 ps
CPU time 1.06 seconds
Started Jul 27 05:58:47 PM PDT 24
Finished Jul 27 05:58:48 PM PDT 24
Peak memory 217372 kb
Host smart-f740fbed-8638-42a8-8f7a-b444931bdf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533296893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1533296893
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1435652661
Short name T518
Test name
Test status
Simulation time 91855126 ps
CPU time 0.7 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:58:54 PM PDT 24
Peak memory 199948 kb
Host smart-3b8c2d58-2311-4faf-92dc-939e8977498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435652661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1435652661
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1226030273
Short name T316
Test name
Test status
Simulation time 1986671333 ps
CPU time 7.95 seconds
Started Jul 27 05:58:55 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 200408 kb
Host smart-80e5408c-a0e2-4837-917c-4f49941922c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226030273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1226030273
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2403085751
Short name T307
Test name
Test status
Simulation time 169124300 ps
CPU time 1.2 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:58:47 PM PDT 24
Peak memory 200112 kb
Host smart-0038da03-03ad-466f-8cf9-e5878b287aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403085751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2403085751
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.4094697704
Short name T227
Test name
Test status
Simulation time 197033082 ps
CPU time 1.36 seconds
Started Jul 27 05:58:59 PM PDT 24
Finished Jul 27 05:59:00 PM PDT 24
Peak memory 200300 kb
Host smart-6f256739-7629-40cb-a0b3-4bbb5136a36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094697704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.4094697704
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2105701838
Short name T238
Test name
Test status
Simulation time 4628361223 ps
CPU time 17.52 seconds
Started Jul 27 05:58:59 PM PDT 24
Finished Jul 27 05:59:16 PM PDT 24
Peak memory 208508 kb
Host smart-26a63158-1235-46f9-a118-ec4c1d1357aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105701838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2105701838
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1412525867
Short name T169
Test name
Test status
Simulation time 122872632 ps
CPU time 1.55 seconds
Started Jul 27 05:58:47 PM PDT 24
Finished Jul 27 05:58:48 PM PDT 24
Peak memory 200108 kb
Host smart-4bcc7bbc-7cbb-43bb-953c-7db08432a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412525867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1412525867
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.555854826
Short name T407
Test name
Test status
Simulation time 236903914 ps
CPU time 1.54 seconds
Started Jul 27 05:58:49 PM PDT 24
Finished Jul 27 05:58:51 PM PDT 24
Peak memory 200132 kb
Host smart-3d3f76c4-3b40-42f2-8a4c-1c1a17452e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555854826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.555854826
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1496963047
Short name T486
Test name
Test status
Simulation time 73989426 ps
CPU time 0.81 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 199904 kb
Host smart-cc7eb69e-939f-429e-be62-4c6f7d379e30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496963047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1496963047
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3035584966
Short name T312
Test name
Test status
Simulation time 1233285415 ps
CPU time 5.56 seconds
Started Jul 27 05:58:52 PM PDT 24
Finished Jul 27 05:58:58 PM PDT 24
Peak memory 221708 kb
Host smart-c18bbd22-7d6f-4592-b7d8-1b013b0e1ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035584966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3035584966
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2283451635
Short name T305
Test name
Test status
Simulation time 249357882 ps
CPU time 1.06 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 217532 kb
Host smart-819acc17-293d-46d5-8554-620d972a72e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283451635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2283451635
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1211212241
Short name T441
Test name
Test status
Simulation time 83957280 ps
CPU time 0.72 seconds
Started Jul 27 05:58:55 PM PDT 24
Finished Jul 27 05:58:56 PM PDT 24
Peak memory 199900 kb
Host smart-d7ef2328-093e-45fa-bf55-b0baa03caa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211212241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1211212241
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.338708240
Short name T283
Test name
Test status
Simulation time 1190533939 ps
CPU time 4.89 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:58:58 PM PDT 24
Peak memory 200392 kb
Host smart-fd1e4dac-887e-42eb-b481-d0db44f58de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338708240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.338708240
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2080374378
Short name T336
Test name
Test status
Simulation time 150149453 ps
CPU time 1.16 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 200132 kb
Host smart-7e1921af-1365-458c-bfd2-a25ec582dde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080374378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2080374378
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1751801988
Short name T426
Test name
Test status
Simulation time 120828165 ps
CPU time 1.25 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:50 PM PDT 24
Peak memory 200376 kb
Host smart-6bccd8f8-2552-44ab-80f5-cc433f3df227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751801988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1751801988
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1035453646
Short name T459
Test name
Test status
Simulation time 15309105022 ps
CPU time 60.99 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:59:47 PM PDT 24
Peak memory 200468 kb
Host smart-7c308036-ebb8-4fe2-b442-e5b6203a1b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035453646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1035453646
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2363928967
Short name T422
Test name
Test status
Simulation time 408738077 ps
CPU time 2.29 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:50 PM PDT 24
Peak memory 200120 kb
Host smart-c7a575ad-3f7c-4d90-a814-2833c1d871c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363928967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2363928967
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3523095507
Short name T163
Test name
Test status
Simulation time 88909718 ps
CPU time 0.88 seconds
Started Jul 27 05:58:49 PM PDT 24
Finished Jul 27 05:58:50 PM PDT 24
Peak memory 200140 kb
Host smart-078017d0-30a9-47c9-bbb7-ff7c2d36814b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523095507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3523095507
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.638557131
Short name T243
Test name
Test status
Simulation time 79946833 ps
CPU time 0.84 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 199792 kb
Host smart-f1005daf-6c05-4959-9219-8f30f73288dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638557131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.638557131
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.650490096
Short name T321
Test name
Test status
Simulation time 1893954551 ps
CPU time 6.97 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 217756 kb
Host smart-194dbe97-d549-4826-9c02-e331347ab415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650490096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.650490096
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.765801280
Short name T540
Test name
Test status
Simulation time 244614234 ps
CPU time 1.02 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:58:47 PM PDT 24
Peak memory 217464 kb
Host smart-ec2640af-d20f-43c6-a840-5d648ed93f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765801280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.765801280
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3202084055
Short name T417
Test name
Test status
Simulation time 163040142 ps
CPU time 0.88 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:05 PM PDT 24
Peak memory 199876 kb
Host smart-0451dab8-88b6-4efc-a5bd-f479890ebab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202084055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3202084055
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.431607142
Short name T248
Test name
Test status
Simulation time 1432546151 ps
CPU time 5.56 seconds
Started Jul 27 05:58:42 PM PDT 24
Finished Jul 27 05:58:47 PM PDT 24
Peak memory 200408 kb
Host smart-e4990d2d-d826-4eaf-b0b0-1c415ea6da48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431607142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.431607142
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1806103839
Short name T208
Test name
Test status
Simulation time 146581342 ps
CPU time 1.15 seconds
Started Jul 27 05:58:47 PM PDT 24
Finished Jul 27 05:58:48 PM PDT 24
Peak memory 200128 kb
Host smart-8f5bb2bd-a4a9-480b-b14a-1afbc8debd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806103839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1806103839
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1234261011
Short name T463
Test name
Test status
Simulation time 204647910 ps
CPU time 1.34 seconds
Started Jul 27 05:58:54 PM PDT 24
Finished Jul 27 05:58:55 PM PDT 24
Peak memory 200284 kb
Host smart-17e2cd98-67b8-461c-946a-25e8cf35ac92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234261011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1234261011
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2250345153
Short name T2
Test name
Test status
Simulation time 2827883400 ps
CPU time 10.63 seconds
Started Jul 27 05:58:41 PM PDT 24
Finished Jul 27 05:58:52 PM PDT 24
Peak memory 200472 kb
Host smart-191ac8b5-1444-49eb-9f58-8a0c67b1c53a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250345153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2250345153
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2028678838
Short name T383
Test name
Test status
Simulation time 139326155 ps
CPU time 1.7 seconds
Started Jul 27 05:58:59 PM PDT 24
Finished Jul 27 05:59:01 PM PDT 24
Peak memory 200176 kb
Host smart-03d137fb-8e0e-4daa-8195-36f81ae54d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028678838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2028678838
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2365708487
Short name T44
Test name
Test status
Simulation time 72286273 ps
CPU time 0.78 seconds
Started Jul 27 05:58:51 PM PDT 24
Finished Jul 27 05:58:52 PM PDT 24
Peak memory 200128 kb
Host smart-730e35ee-ed8c-425b-9ef5-3f09b984a183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365708487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2365708487
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3899767144
Short name T75
Test name
Test status
Simulation time 66313287 ps
CPU time 0.75 seconds
Started Jul 27 05:58:52 PM PDT 24
Finished Jul 27 05:58:53 PM PDT 24
Peak memory 199936 kb
Host smart-8e15cb54-6119-44d6-a4c0-3db8610e9310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899767144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3899767144
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1357145368
Short name T452
Test name
Test status
Simulation time 2358126155 ps
CPU time 8.59 seconds
Started Jul 27 05:58:59 PM PDT 24
Finished Jul 27 05:59:07 PM PDT 24
Peak memory 217952 kb
Host smart-91d2dff0-d5e3-422a-90dd-379e9be2d9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357145368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1357145368
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.480236579
Short name T366
Test name
Test status
Simulation time 244204753 ps
CPU time 1.07 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:58:54 PM PDT 24
Peak memory 217464 kb
Host smart-3bdb8c1b-de21-4320-8ab8-ed38b27f7876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480236579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.480236579
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2881623371
Short name T296
Test name
Test status
Simulation time 117322236 ps
CPU time 0.79 seconds
Started Jul 27 05:58:50 PM PDT 24
Finished Jul 27 05:58:50 PM PDT 24
Peak memory 199944 kb
Host smart-69d3a032-bd5e-44af-aaf6-0536333e19a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881623371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2881623371
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2198812163
Short name T277
Test name
Test status
Simulation time 892330439 ps
CPU time 4.62 seconds
Started Jul 27 05:58:50 PM PDT 24
Finished Jul 27 05:58:55 PM PDT 24
Peak memory 200396 kb
Host smart-148a060e-a3d8-4b89-9490-3ac7f7044dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198812163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2198812163
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.869551621
Short name T478
Test name
Test status
Simulation time 121605975 ps
CPU time 1.23 seconds
Started Jul 27 05:58:47 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 200384 kb
Host smart-688c5378-5abe-4ba0-88f9-93f4ace7c1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869551621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.869551621
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2797170229
Short name T60
Test name
Test status
Simulation time 8544096143 ps
CPU time 27.78 seconds
Started Jul 27 05:58:51 PM PDT 24
Finished Jul 27 05:59:19 PM PDT 24
Peak memory 209452 kb
Host smart-265fa837-2039-48ca-ba56-9db005438167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797170229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2797170229
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3704681088
Short name T497
Test name
Test status
Simulation time 298992145 ps
CPU time 2.11 seconds
Started Jul 27 05:58:49 PM PDT 24
Finished Jul 27 05:58:52 PM PDT 24
Peak memory 208384 kb
Host smart-2f18d25c-fa5f-48fc-8949-8c16ed917924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704681088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3704681088
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3058020455
Short name T195
Test name
Test status
Simulation time 130875066 ps
CPU time 1.04 seconds
Started Jul 27 05:58:49 PM PDT 24
Finished Jul 27 05:58:50 PM PDT 24
Peak memory 200140 kb
Host smart-20626fd2-dad8-4544-885a-8cc9a8e03e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058020455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3058020455
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1922189013
Short name T338
Test name
Test status
Simulation time 96408743 ps
CPU time 0.86 seconds
Started Jul 27 05:58:55 PM PDT 24
Finished Jul 27 05:58:56 PM PDT 24
Peak memory 199916 kb
Host smart-be8b1c58-d34d-4e7f-8533-9f92702cb286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922189013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1922189013
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.365494874
Short name T34
Test name
Test status
Simulation time 1897134869 ps
CPU time 7.3 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:56 PM PDT 24
Peak memory 221704 kb
Host smart-8551955f-8a08-4062-8a93-c22b19bef457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365494874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.365494874
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3600233727
Short name T134
Test name
Test status
Simulation time 244816963 ps
CPU time 1.07 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:06 PM PDT 24
Peak memory 217412 kb
Host smart-ceb9fa1d-1f23-4678-a210-948ad023d6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600233727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3600233727
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3057083468
Short name T24
Test name
Test status
Simulation time 111534298 ps
CPU time 0.81 seconds
Started Jul 27 05:58:50 PM PDT 24
Finished Jul 27 05:58:51 PM PDT 24
Peak memory 199952 kb
Host smart-44ff47e1-32d9-46b1-85b2-20eb1b3873ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057083468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3057083468
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1445091431
Short name T475
Test name
Test status
Simulation time 1734794160 ps
CPU time 6.85 seconds
Started Jul 27 05:59:10 PM PDT 24
Finished Jul 27 05:59:17 PM PDT 24
Peak memory 200376 kb
Host smart-90693d37-0353-4c61-94f8-638f97ca962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445091431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1445091431
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3957178392
Short name T541
Test name
Test status
Simulation time 92449218 ps
CPU time 0.94 seconds
Started Jul 27 05:58:51 PM PDT 24
Finished Jul 27 05:58:52 PM PDT 24
Peak memory 200060 kb
Host smart-c4173dd6-7163-4745-8588-fa43949c4b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957178392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3957178392
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3153518565
Short name T504
Test name
Test status
Simulation time 235698553 ps
CPU time 1.42 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 200300 kb
Host smart-b26a0212-0530-4652-a859-43811ac18eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153518565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3153518565
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2208434632
Short name T453
Test name
Test status
Simulation time 3111811352 ps
CPU time 14.4 seconds
Started Jul 27 05:58:59 PM PDT 24
Finished Jul 27 05:59:13 PM PDT 24
Peak memory 208652 kb
Host smart-9b182b4c-6d66-4ac5-bb78-c1c2b652fdbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208434632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2208434632
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3357164364
Short name T454
Test name
Test status
Simulation time 151538035 ps
CPU time 1.83 seconds
Started Jul 27 05:58:55 PM PDT 24
Finished Jul 27 05:58:57 PM PDT 24
Peak memory 200116 kb
Host smart-362d4d84-c7c0-4491-88d1-3830299a660c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357164364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3357164364
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3328869862
Short name T220
Test name
Test status
Simulation time 254659356 ps
CPU time 1.64 seconds
Started Jul 27 05:59:02 PM PDT 24
Finished Jul 27 05:59:04 PM PDT 24
Peak memory 200340 kb
Host smart-f0e0d318-2067-4b2e-bfd8-c43c0661498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328869862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3328869862
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3220254082
Short name T196
Test name
Test status
Simulation time 76109877 ps
CPU time 0.76 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:58:57 PM PDT 24
Peak memory 199932 kb
Host smart-bea5c448-734e-4b22-8b81-dd25098899d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220254082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3220254082
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1229905682
Short name T386
Test name
Test status
Simulation time 1889171606 ps
CPU time 6.91 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 217768 kb
Host smart-8015af83-cc33-4c58-b592-74b8b133b153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229905682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1229905682
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3436252940
Short name T198
Test name
Test status
Simulation time 244958769 ps
CPU time 1.21 seconds
Started Jul 27 05:59:03 PM PDT 24
Finished Jul 27 05:59:04 PM PDT 24
Peak memory 217444 kb
Host smart-269c88bb-e4d5-4f38-b901-665dee545d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436252940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3436252940
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2078606661
Short name T377
Test name
Test status
Simulation time 179665906 ps
CPU time 0.95 seconds
Started Jul 27 05:59:00 PM PDT 24
Finished Jul 27 05:59:01 PM PDT 24
Peak memory 199864 kb
Host smart-c8217a75-ce3f-4215-823b-d1623cb913be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078606661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2078606661
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1420550553
Short name T448
Test name
Test status
Simulation time 925779330 ps
CPU time 4.22 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:11 PM PDT 24
Peak memory 200440 kb
Host smart-b8a4adba-5127-4500-8a01-eacc5dc1401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420550553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1420550553
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3671763983
Short name T419
Test name
Test status
Simulation time 111536043 ps
CPU time 1.01 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:08 PM PDT 24
Peak memory 200044 kb
Host smart-e4c353c2-7350-487a-9478-363dd891f84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671763983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3671763983
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3097630968
Short name T282
Test name
Test status
Simulation time 247652636 ps
CPU time 1.59 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:06 PM PDT 24
Peak memory 200316 kb
Host smart-2afc651a-8532-4bfd-aa2b-99d6a97433fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097630968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3097630968
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1233582716
Short name T461
Test name
Test status
Simulation time 5595707187 ps
CPU time 21.19 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:59:14 PM PDT 24
Peak memory 209568 kb
Host smart-d2881f9f-e75a-4cb5-8ff2-da37bfaa9a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233582716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1233582716
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.533380976
Short name T471
Test name
Test status
Simulation time 120281213 ps
CPU time 1.65 seconds
Started Jul 27 05:58:58 PM PDT 24
Finished Jul 27 05:59:00 PM PDT 24
Peak memory 208316 kb
Host smart-7676f40c-2789-4a58-a01c-19fcc9f252f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533380976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.533380976
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2577536191
Short name T501
Test name
Test status
Simulation time 73486107 ps
CPU time 0.87 seconds
Started Jul 27 05:58:55 PM PDT 24
Finished Jul 27 05:58:56 PM PDT 24
Peak memory 200040 kb
Host smart-e1c03995-cdf9-4c14-a077-beee5ced1233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577536191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2577536191
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.165465774
Short name T538
Test name
Test status
Simulation time 57521773 ps
CPU time 0.71 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:58:54 PM PDT 24
Peak memory 199928 kb
Host smart-88a7fc6b-3979-41c5-b66c-ef810a4a1a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165465774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.165465774
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.194429852
Short name T298
Test name
Test status
Simulation time 1230132702 ps
CPU time 5.7 seconds
Started Jul 27 05:58:52 PM PDT 24
Finished Jul 27 05:58:58 PM PDT 24
Peak memory 217764 kb
Host smart-65c54012-47b9-474b-9e8a-cf5ad0f19603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194429852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.194429852
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1319091148
Short name T7
Test name
Test status
Simulation time 244533561 ps
CPU time 1.16 seconds
Started Jul 27 05:59:02 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 217496 kb
Host smart-8c2ae74d-f928-4d98-9c13-1256bc3a579a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319091148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1319091148
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2869148398
Short name T205
Test name
Test status
Simulation time 231829435 ps
CPU time 0.9 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:05 PM PDT 24
Peak memory 199916 kb
Host smart-1002bc13-eda9-4b4f-96f6-37b8d692c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869148398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2869148398
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1519679823
Short name T239
Test name
Test status
Simulation time 1547334397 ps
CPU time 6.31 seconds
Started Jul 27 05:59:06 PM PDT 24
Finished Jul 27 05:59:12 PM PDT 24
Peak memory 200368 kb
Host smart-b021e7c0-5f28-4ecd-863f-1c2ba779ef51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519679823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1519679823
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.886057690
Short name T203
Test name
Test status
Simulation time 109486383 ps
CPU time 1.01 seconds
Started Jul 27 05:58:57 PM PDT 24
Finished Jul 27 05:58:59 PM PDT 24
Peak memory 200164 kb
Host smart-9ba27128-ef20-4fb7-9a73-4ab83a956694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886057690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.886057690
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1363866146
Short name T526
Test name
Test status
Simulation time 195707560 ps
CPU time 1.36 seconds
Started Jul 27 05:59:00 PM PDT 24
Finished Jul 27 05:59:02 PM PDT 24
Peak memory 200280 kb
Host smart-a477231e-2d51-4fae-841f-1d5e8aca5650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363866146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1363866146
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3910921238
Short name T87
Test name
Test status
Simulation time 6590416056 ps
CPU time 23.31 seconds
Started Jul 27 05:59:01 PM PDT 24
Finished Jul 27 05:59:24 PM PDT 24
Peak memory 200488 kb
Host smart-de7fc6d6-2b3c-457d-9e6f-0bba912bfcf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910921238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3910921238
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3745405298
Short name T216
Test name
Test status
Simulation time 311069654 ps
CPU time 2.03 seconds
Started Jul 27 05:58:59 PM PDT 24
Finished Jul 27 05:59:01 PM PDT 24
Peak memory 199996 kb
Host smart-fa6b309b-f247-44f4-9675-9747ccafc837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745405298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3745405298
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3275860294
Short name T524
Test name
Test status
Simulation time 162040712 ps
CPU time 1.1 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:58:55 PM PDT 24
Peak memory 200144 kb
Host smart-9dcf2724-d26c-47e0-8991-6e12ae4cdc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275860294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3275860294
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2907001781
Short name T76
Test name
Test status
Simulation time 83323736 ps
CPU time 0.84 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:58:54 PM PDT 24
Peak memory 199920 kb
Host smart-5472bec6-5865-46f0-8f5e-8a7c45c13d97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907001781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2907001781
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3871841224
Short name T495
Test name
Test status
Simulation time 1892928641 ps
CPU time 7.42 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 221728 kb
Host smart-6a18c8a2-4ce7-4c12-8bd5-d49a13a2f039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871841224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3871841224
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3286525361
Short name T149
Test name
Test status
Simulation time 244113907 ps
CPU time 1.17 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:58:58 PM PDT 24
Peak memory 217472 kb
Host smart-a90b3cb0-e96d-4c41-aed5-b7e81f1b1a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286525361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3286525361
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2631759896
Short name T320
Test name
Test status
Simulation time 186814050 ps
CPU time 0.94 seconds
Started Jul 27 05:59:01 PM PDT 24
Finished Jul 27 05:59:02 PM PDT 24
Peak memory 199948 kb
Host smart-ecf14eca-27cf-44fb-9e13-bf8ced46ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631759896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2631759896
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1950501134
Short name T214
Test name
Test status
Simulation time 2210372941 ps
CPU time 7.53 seconds
Started Jul 27 05:58:51 PM PDT 24
Finished Jul 27 05:58:59 PM PDT 24
Peak memory 200396 kb
Host smart-f2c29118-8a9a-4278-9d3e-a4787cb08ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950501134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1950501134
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2359196164
Short name T255
Test name
Test status
Simulation time 138941548 ps
CPU time 1.19 seconds
Started Jul 27 05:59:03 PM PDT 24
Finished Jul 27 05:59:04 PM PDT 24
Peak memory 200076 kb
Host smart-0ad94de0-51e1-4153-bf14-a90ede8e2057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359196164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2359196164
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3419304068
Short name T468
Test name
Test status
Simulation time 194483996 ps
CPU time 1.32 seconds
Started Jul 27 05:58:51 PM PDT 24
Finished Jul 27 05:58:53 PM PDT 24
Peak memory 200324 kb
Host smart-1589e362-468c-4072-8795-9da50b087b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419304068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3419304068
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1916849489
Short name T503
Test name
Test status
Simulation time 863491432 ps
CPU time 3.52 seconds
Started Jul 27 05:58:50 PM PDT 24
Finished Jul 27 05:58:53 PM PDT 24
Peak memory 200272 kb
Host smart-084a0f92-8d4e-43b7-87c1-ac4f6240f420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916849489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1916849489
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.754676778
Short name T480
Test name
Test status
Simulation time 141114873 ps
CPU time 1.7 seconds
Started Jul 27 05:58:58 PM PDT 24
Finished Jul 27 05:59:00 PM PDT 24
Peak memory 200144 kb
Host smart-8e02a119-046b-4cfa-b9a2-d107f684ce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754676778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.754676778
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1459837024
Short name T359
Test name
Test status
Simulation time 72703804 ps
CPU time 0.79 seconds
Started Jul 27 05:58:29 PM PDT 24
Finished Jul 27 05:58:30 PM PDT 24
Peak memory 199928 kb
Host smart-d81ffcd6-4c57-4511-a2c4-526de484f187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459837024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1459837024
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3909616552
Short name T431
Test name
Test status
Simulation time 1889580108 ps
CPU time 7.05 seconds
Started Jul 27 05:58:39 PM PDT 24
Finished Jul 27 05:58:46 PM PDT 24
Peak memory 221764 kb
Host smart-5134f6dc-ef66-4ba6-b6b8-6806212e0e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909616552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3909616552
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3089266917
Short name T278
Test name
Test status
Simulation time 244750302 ps
CPU time 1.11 seconds
Started Jul 27 05:58:35 PM PDT 24
Finished Jul 27 05:58:36 PM PDT 24
Peak memory 217396 kb
Host smart-731ff906-de69-493f-9f12-6e8b1836ad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089266917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3089266917
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2806057032
Short name T420
Test name
Test status
Simulation time 190191200 ps
CPU time 0.86 seconds
Started Jul 27 05:58:29 PM PDT 24
Finished Jul 27 05:58:30 PM PDT 24
Peak memory 199940 kb
Host smart-655aec29-bed9-4536-8669-7068e2e8c9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806057032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2806057032
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.4244252109
Short name T242
Test name
Test status
Simulation time 833081438 ps
CPU time 4.21 seconds
Started Jul 27 05:58:29 PM PDT 24
Finished Jul 27 05:58:34 PM PDT 24
Peak memory 200368 kb
Host smart-bdefd8c1-f710-4338-b06b-d873780b1359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244252109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.4244252109
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1643124151
Short name T74
Test name
Test status
Simulation time 8564968704 ps
CPU time 15.11 seconds
Started Jul 27 05:58:34 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 217104 kb
Host smart-f9d1df98-d494-4428-8ebb-bf23250569c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643124151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1643124151
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1875209824
Short name T378
Test name
Test status
Simulation time 146871379 ps
CPU time 1.17 seconds
Started Jul 27 05:58:28 PM PDT 24
Finished Jul 27 05:58:29 PM PDT 24
Peak memory 200032 kb
Host smart-010ae8b4-a84a-4a98-ad52-1ac37dd6c04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875209824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1875209824
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.834274441
Short name T343
Test name
Test status
Simulation time 199242289 ps
CPU time 1.42 seconds
Started Jul 27 05:58:35 PM PDT 24
Finished Jul 27 05:58:37 PM PDT 24
Peak memory 200336 kb
Host smart-4c6f05a3-484b-4004-9e1c-ba3d7d0660e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834274441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.834274441
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3498210052
Short name T215
Test name
Test status
Simulation time 7360704683 ps
CPU time 24.33 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:59:10 PM PDT 24
Peak memory 208640 kb
Host smart-8439053d-154f-455e-834a-cfa66705310f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498210052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3498210052
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1271249449
Short name T353
Test name
Test status
Simulation time 434823521 ps
CPU time 2.43 seconds
Started Jul 27 05:58:28 PM PDT 24
Finished Jul 27 05:58:31 PM PDT 24
Peak memory 208384 kb
Host smart-41efdc80-eea8-4488-8abe-52459cbfbbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271249449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1271249449
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3474921240
Short name T365
Test name
Test status
Simulation time 131082793 ps
CPU time 1.05 seconds
Started Jul 27 05:58:36 PM PDT 24
Finished Jul 27 05:58:37 PM PDT 24
Peak memory 200128 kb
Host smart-add6371e-0dc2-4ba9-ae6e-f8f016099977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474921240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3474921240
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.99382031
Short name T516
Test name
Test status
Simulation time 70282484 ps
CPU time 0.83 seconds
Started Jul 27 05:59:01 PM PDT 24
Finished Jul 27 05:59:02 PM PDT 24
Peak memory 199880 kb
Host smart-053cfdf8-67c7-4f1d-a863-24cbdaa7707a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99382031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.99382031
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1296930426
Short name T498
Test name
Test status
Simulation time 1223796160 ps
CPU time 6.23 seconds
Started Jul 27 05:58:55 PM PDT 24
Finished Jul 27 05:59:01 PM PDT 24
Peak memory 217756 kb
Host smart-f1b9795e-f3fe-45ae-a62c-d680f5961684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296930426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1296930426
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.4020916285
Short name T502
Test name
Test status
Simulation time 244367402 ps
CPU time 1.1 seconds
Started Jul 27 05:58:54 PM PDT 24
Finished Jul 27 05:58:55 PM PDT 24
Peak memory 217472 kb
Host smart-9234401d-98a4-415f-ad9a-cad502872b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020916285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.4020916285
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1256415690
Short name T254
Test name
Test status
Simulation time 83647375 ps
CPU time 0.73 seconds
Started Jul 27 05:58:58 PM PDT 24
Finished Jul 27 05:58:59 PM PDT 24
Peak memory 199948 kb
Host smart-90246a3c-545a-45eb-a094-86c11758c8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256415690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1256415690
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2165748266
Short name T482
Test name
Test status
Simulation time 864904962 ps
CPU time 4.04 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:59:00 PM PDT 24
Peak memory 200444 kb
Host smart-df790195-1e3d-4c3f-bb32-1006a2674c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165748266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2165748266
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.908382316
Short name T269
Test name
Test status
Simulation time 99439371 ps
CPU time 1.01 seconds
Started Jul 27 05:58:58 PM PDT 24
Finished Jul 27 05:58:59 PM PDT 24
Peak memory 200040 kb
Host smart-fe68d127-1e22-4728-b266-53b41b4e5fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908382316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.908382316
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1452693078
Short name T244
Test name
Test status
Simulation time 197499010 ps
CPU time 1.37 seconds
Started Jul 27 05:58:52 PM PDT 24
Finished Jul 27 05:58:54 PM PDT 24
Peak memory 200324 kb
Host smart-aaf9a3b8-7c44-4ffc-9f11-b2da404e5044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452693078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1452693078
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3831812657
Short name T223
Test name
Test status
Simulation time 12420589709 ps
CPU time 46.05 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:50 PM PDT 24
Peak memory 200452 kb
Host smart-290b9a72-8b03-4117-9d19-ed8e3d9a06bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831812657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3831812657
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3618925687
Short name T443
Test name
Test status
Simulation time 295237525 ps
CPU time 1.88 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:58:55 PM PDT 24
Peak memory 200140 kb
Host smart-7d65e864-72ed-4bfa-9f6b-7ab62c37f0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618925687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3618925687
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2552618656
Short name T328
Test name
Test status
Simulation time 86871474 ps
CPU time 0.93 seconds
Started Jul 27 05:58:57 PM PDT 24
Finished Jul 27 05:58:58 PM PDT 24
Peak memory 200132 kb
Host smart-f64ade76-a753-4b13-93c6-a10094374d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552618656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2552618656
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2890303213
Short name T168
Test name
Test status
Simulation time 61037760 ps
CPU time 0.69 seconds
Started Jul 27 05:58:58 PM PDT 24
Finished Jul 27 05:58:59 PM PDT 24
Peak memory 199936 kb
Host smart-a808891a-b3ae-45c9-abb6-e91b3872b877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890303213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2890303213
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2796621098
Short name T462
Test name
Test status
Simulation time 2178420903 ps
CPU time 7.87 seconds
Started Jul 27 05:59:06 PM PDT 24
Finished Jul 27 05:59:14 PM PDT 24
Peak memory 229972 kb
Host smart-3b37065d-8863-49e3-88de-0d10b0770575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796621098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2796621098
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1200979923
Short name T317
Test name
Test status
Simulation time 244779449 ps
CPU time 1.03 seconds
Started Jul 27 05:59:10 PM PDT 24
Finished Jul 27 05:59:12 PM PDT 24
Peak memory 217436 kb
Host smart-d1bbe1cb-26c4-4a7c-bd76-83ba739e53e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200979923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1200979923
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1370528366
Short name T432
Test name
Test status
Simulation time 82532039 ps
CPU time 0.75 seconds
Started Jul 27 05:59:06 PM PDT 24
Finished Jul 27 05:59:07 PM PDT 24
Peak memory 199952 kb
Host smart-6b4a186a-ee16-4b91-a773-ac8e5d87d2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370528366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1370528366
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.944501617
Short name T438
Test name
Test status
Simulation time 819990863 ps
CPU time 4.4 seconds
Started Jul 27 05:59:02 PM PDT 24
Finished Jul 27 05:59:07 PM PDT 24
Peak memory 200404 kb
Host smart-f5c6ceb5-add8-40c8-9026-00d8a130dadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944501617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.944501617
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.858338544
Short name T29
Test name
Test status
Simulation time 180290584 ps
CPU time 1.19 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:08 PM PDT 24
Peak memory 200132 kb
Host smart-3e3af706-e862-4b02-8d96-182e6d75baaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858338544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.858338544
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.314926452
Short name T293
Test name
Test status
Simulation time 223190638 ps
CPU time 1.47 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:08 PM PDT 24
Peak memory 200308 kb
Host smart-f70bd8c2-6d2d-4158-b458-54b2082207f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314926452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.314926452
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2988343012
Short name T250
Test name
Test status
Simulation time 8133464842 ps
CPU time 25.74 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:30 PM PDT 24
Peak memory 208668 kb
Host smart-14b830c2-0a2d-4dd8-a94d-c9f41b0b43b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988343012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2988343012
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2828637069
Short name T89
Test name
Test status
Simulation time 126120968 ps
CPU time 1.58 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:07 PM PDT 24
Peak memory 200092 kb
Host smart-238276dd-5136-4865-9863-1ac5052f2673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828637069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2828637069
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.4293576915
Short name T514
Test name
Test status
Simulation time 94406214 ps
CPU time 0.93 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:06 PM PDT 24
Peak memory 200144 kb
Host smart-fb6764b5-b7c3-414a-89b1-38f878e8866f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293576915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.4293576915
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.358994708
Short name T450
Test name
Test status
Simulation time 75567197 ps
CPU time 0.78 seconds
Started Jul 27 05:59:02 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 200004 kb
Host smart-580d9f79-842b-448c-96e2-cc9ef5c505ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358994708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.358994708
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2214821275
Short name T333
Test name
Test status
Simulation time 1889373023 ps
CPU time 7.97 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:14 PM PDT 24
Peak memory 217748 kb
Host smart-6818234c-bbf8-4252-aac4-78dfde53d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214821275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2214821275
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.831837851
Short name T143
Test name
Test status
Simulation time 244445321 ps
CPU time 1.07 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:08 PM PDT 24
Peak memory 217548 kb
Host smart-43567d42-9450-44ae-983c-9d5f22cc63ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831837851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.831837851
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1431513269
Short name T15
Test name
Test status
Simulation time 195407884 ps
CPU time 0.95 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:06 PM PDT 24
Peak memory 199916 kb
Host smart-fc8c9b71-9bdc-45e9-b9da-b3dff9cb485e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431513269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1431513269
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2315799352
Short name T289
Test name
Test status
Simulation time 1455416225 ps
CPU time 5.44 seconds
Started Jul 27 05:58:57 PM PDT 24
Finished Jul 27 05:59:02 PM PDT 24
Peak memory 200344 kb
Host smart-e48a3404-8795-42c6-94dd-07b4e5773f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315799352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2315799352
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.851504468
Short name T247
Test name
Test status
Simulation time 98203158 ps
CPU time 1.02 seconds
Started Jul 27 05:59:15 PM PDT 24
Finished Jul 27 05:59:16 PM PDT 24
Peak memory 200128 kb
Host smart-f4942adf-59b0-4f89-97d1-4dd3a14c99a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851504468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.851504468
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3508943825
Short name T138
Test name
Test status
Simulation time 119444439 ps
CPU time 1.21 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:06 PM PDT 24
Peak memory 200304 kb
Host smart-dd04d669-a6ff-4922-97e0-d31951ac7a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508943825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3508943825
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.534600326
Short name T436
Test name
Test status
Simulation time 14132472860 ps
CPU time 48.95 seconds
Started Jul 27 05:59:11 PM PDT 24
Finished Jul 27 06:00:00 PM PDT 24
Peak memory 208648 kb
Host smart-a264ecdf-34e8-494f-b66f-3697c124d10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534600326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.534600326
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2443701093
Short name T191
Test name
Test status
Simulation time 361542023 ps
CPU time 2.09 seconds
Started Jul 27 05:59:10 PM PDT 24
Finished Jul 27 05:59:12 PM PDT 24
Peak memory 200132 kb
Host smart-1e142786-3c39-45b5-b25e-fd9b7ef09b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443701093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2443701093
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1170489890
Short name T260
Test name
Test status
Simulation time 101108769 ps
CPU time 0.93 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:08 PM PDT 24
Peak memory 200132 kb
Host smart-d537aa1b-0323-4a2e-bde5-538c344e5599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170489890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1170489890
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3706975323
Short name T533
Test name
Test status
Simulation time 89983380 ps
CPU time 0.8 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:05 PM PDT 24
Peak memory 199860 kb
Host smart-9fad0325-0c4c-4d70-96ee-4239e932c3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706975323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3706975323
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3407924301
Short name T332
Test name
Test status
Simulation time 1890208903 ps
CPU time 7.29 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:12 PM PDT 24
Peak memory 217548 kb
Host smart-565101e8-c980-45c0-8f19-afc4f1be057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407924301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3407924301
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.910646456
Short name T43
Test name
Test status
Simulation time 244166837 ps
CPU time 1.16 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 217448 kb
Host smart-c2bc3d3b-a543-427a-8b0c-c668a08cdd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910646456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.910646456
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2098194622
Short name T21
Test name
Test status
Simulation time 101204565 ps
CPU time 0.77 seconds
Started Jul 27 05:59:09 PM PDT 24
Finished Jul 27 05:59:10 PM PDT 24
Peak memory 199920 kb
Host smart-c540412c-7833-498c-a5d8-a2e7f02827c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098194622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2098194622
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.599276129
Short name T125
Test name
Test status
Simulation time 1446997241 ps
CPU time 6.34 seconds
Started Jul 27 05:58:55 PM PDT 24
Finished Jul 27 05:59:01 PM PDT 24
Peak memory 200432 kb
Host smart-74629211-3f7e-4025-bac4-cde8e0d946f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599276129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.599276129
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1530622708
Short name T485
Test name
Test status
Simulation time 103951556 ps
CPU time 1.02 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:05 PM PDT 24
Peak memory 200048 kb
Host smart-667c12b8-1643-46bf-badc-3dab0d59d71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530622708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1530622708
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1603028797
Short name T148
Test name
Test status
Simulation time 122899140 ps
CPU time 1.23 seconds
Started Jul 27 05:59:02 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 200228 kb
Host smart-bed232ca-abfc-4293-af13-aa8f6c6303c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603028797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1603028797
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1341581573
Short name T219
Test name
Test status
Simulation time 3985318129 ps
CPU time 15.02 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:23 PM PDT 24
Peak memory 200500 kb
Host smart-82f99432-c319-47c2-ab77-c81e955c4f7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341581573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1341581573
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2833434186
Short name T406
Test name
Test status
Simulation time 366498122 ps
CPU time 2.46 seconds
Started Jul 27 05:59:06 PM PDT 24
Finished Jul 27 05:59:08 PM PDT 24
Peak memory 200144 kb
Host smart-073a8437-a9be-4645-ab85-40a59765c364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833434186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2833434186
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1241270608
Short name T162
Test name
Test status
Simulation time 179488672 ps
CPU time 1.09 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:06 PM PDT 24
Peak memory 200112 kb
Host smart-67cc7974-488a-4530-bb4f-9a53e5579026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241270608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1241270608
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3492856862
Short name T155
Test name
Test status
Simulation time 69075158 ps
CPU time 0.73 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:06 PM PDT 24
Peak memory 199916 kb
Host smart-699c290b-f10c-4084-a92c-5007bac95362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492856862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3492856862
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3103081127
Short name T46
Test name
Test status
Simulation time 2369930867 ps
CPU time 8.48 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:13 PM PDT 24
Peak memory 217788 kb
Host smart-f50f1259-0c21-4f6b-a317-3301ef7ebd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103081127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3103081127
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1345170411
Short name T235
Test name
Test status
Simulation time 244659335 ps
CPU time 1.03 seconds
Started Jul 27 05:59:03 PM PDT 24
Finished Jul 27 05:59:04 PM PDT 24
Peak memory 217520 kb
Host smart-3f95aabb-8db8-4008-93b6-18d8e23bc9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345170411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1345170411
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3419933868
Short name T18
Test name
Test status
Simulation time 159317663 ps
CPU time 0.85 seconds
Started Jul 27 05:59:06 PM PDT 24
Finished Jul 27 05:59:07 PM PDT 24
Peak memory 200020 kb
Host smart-19fd52f4-29b9-461c-a400-f3ac92d1f2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419933868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3419933868
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.290041934
Short name T246
Test name
Test status
Simulation time 1752383752 ps
CPU time 6.7 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:10 PM PDT 24
Peak memory 200424 kb
Host smart-86c8f011-4e0c-41eb-a865-2e8d3a29e984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290041934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.290041934
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3227223362
Short name T175
Test name
Test status
Simulation time 157285133 ps
CPU time 1.1 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:06 PM PDT 24
Peak memory 199996 kb
Host smart-6eef87c4-8bbb-4650-935b-abd0f266b465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227223362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3227223362
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3682622126
Short name T274
Test name
Test status
Simulation time 124704063 ps
CPU time 1.16 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:10 PM PDT 24
Peak memory 200340 kb
Host smart-feaf4dd7-a81f-4e98-8d87-75525a282ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682622126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3682622126
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.205325736
Short name T237
Test name
Test status
Simulation time 3347348962 ps
CPU time 15.83 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:24 PM PDT 24
Peak memory 208588 kb
Host smart-c1cd41ed-23e2-4e95-9184-f051da7d36b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205325736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.205325736
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.626039321
Short name T264
Test name
Test status
Simulation time 120905029 ps
CPU time 1.51 seconds
Started Jul 27 05:59:01 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 200100 kb
Host smart-9db4474f-6f5b-4218-abdd-b2ee3658d8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626039321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.626039321
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1695509075
Short name T290
Test name
Test status
Simulation time 125450463 ps
CPU time 0.96 seconds
Started Jul 27 05:58:57 PM PDT 24
Finished Jul 27 05:58:58 PM PDT 24
Peak memory 200128 kb
Host smart-2e117c48-8ce8-44bc-817c-d81b011fca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695509075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1695509075
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.790432847
Short name T435
Test name
Test status
Simulation time 72448668 ps
CPU time 0.8 seconds
Started Jul 27 05:59:01 PM PDT 24
Finished Jul 27 05:59:02 PM PDT 24
Peak memory 199896 kb
Host smart-e884ca36-0de4-4552-9c1b-2a9b2857b0d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790432847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.790432847
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1941184863
Short name T445
Test name
Test status
Simulation time 2362052458 ps
CPU time 9.03 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:17 PM PDT 24
Peak memory 217844 kb
Host smart-4850e445-a261-48bc-ae5c-db24cc79c38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941184863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1941184863
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3677856124
Short name T423
Test name
Test status
Simulation time 244823564 ps
CPU time 1.04 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 217472 kb
Host smart-28e5249b-cab8-4c82-8593-ba2fcff9618b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677856124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3677856124
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2170020545
Short name T23
Test name
Test status
Simulation time 112361721 ps
CPU time 0.78 seconds
Started Jul 27 05:59:01 PM PDT 24
Finished Jul 27 05:59:01 PM PDT 24
Peak memory 199932 kb
Host smart-25164f45-c639-4464-afd3-63381220a086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170020545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2170020545
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2516198566
Short name T349
Test name
Test status
Simulation time 1660802821 ps
CPU time 6.88 seconds
Started Jul 27 05:59:02 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 200420 kb
Host smart-63c099b7-0c07-4437-9d4c-32c7c139999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516198566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2516198566
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.699745378
Short name T496
Test name
Test status
Simulation time 108146998 ps
CPU time 1 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:58:57 PM PDT 24
Peak memory 200128 kb
Host smart-a4e748d8-45d5-44d6-8ed7-40c78de734bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699745378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.699745378
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1249879530
Short name T284
Test name
Test status
Simulation time 122023638 ps
CPU time 1.32 seconds
Started Jul 27 05:59:01 PM PDT 24
Finished Jul 27 05:59:02 PM PDT 24
Peak memory 200336 kb
Host smart-347f62f3-b1a8-4137-af60-5b2c5018a284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249879530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1249879530
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2459831935
Short name T483
Test name
Test status
Simulation time 3923861682 ps
CPU time 14.46 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:23 PM PDT 24
Peak memory 208564 kb
Host smart-c91787b8-0f74-485f-a8a0-aec5e95999df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459831935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2459831935
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1615427498
Short name T85
Test name
Test status
Simulation time 265860293 ps
CPU time 1.81 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:58:58 PM PDT 24
Peak memory 200080 kb
Host smart-9f208787-5107-430f-9fcd-bf9815eaa8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615427498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1615427498
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1526194927
Short name T133
Test name
Test status
Simulation time 213481280 ps
CPU time 1.29 seconds
Started Jul 27 05:59:06 PM PDT 24
Finished Jul 27 05:59:08 PM PDT 24
Peak memory 199988 kb
Host smart-2ad9dc5e-65e7-4ffe-910d-3d2ba8ce3011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526194927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1526194927
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1156731379
Short name T470
Test name
Test status
Simulation time 75696572 ps
CPU time 0.8 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 199856 kb
Host smart-52963659-3813-4d3d-8e86-b1a3e4f30bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156731379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1156731379
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2951682339
Short name T404
Test name
Test status
Simulation time 2377719343 ps
CPU time 7.71 seconds
Started Jul 27 05:59:06 PM PDT 24
Finished Jul 27 05:59:14 PM PDT 24
Peak memory 217904 kb
Host smart-7f746a9a-694d-4fc7-bc3a-0902c1805ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951682339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2951682339
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3288531541
Short name T83
Test name
Test status
Simulation time 243736307 ps
CPU time 1.08 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:07 PM PDT 24
Peak memory 217500 kb
Host smart-3b3f6bc2-8965-405a-9e83-de25289e59b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288531541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3288531541
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.4143685937
Short name T429
Test name
Test status
Simulation time 122191795 ps
CPU time 0.79 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 199940 kb
Host smart-3b9ef393-ffb7-4f1a-8949-612f96f287e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143685937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.4143685937
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1719651522
Short name T271
Test name
Test status
Simulation time 1927923143 ps
CPU time 6.8 seconds
Started Jul 27 05:59:09 PM PDT 24
Finished Jul 27 05:59:16 PM PDT 24
Peak memory 200604 kb
Host smart-992d7de6-a57e-470e-aec1-b36fb5b2c257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719651522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1719651522
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2135846967
Short name T398
Test name
Test status
Simulation time 144456493 ps
CPU time 1.1 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:26 PM PDT 24
Peak memory 200120 kb
Host smart-e2bf7fe5-e979-4e06-bd30-9bcf2a9bc3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135846967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2135846967
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.993468711
Short name T222
Test name
Test status
Simulation time 192278546 ps
CPU time 1.41 seconds
Started Jul 27 05:59:12 PM PDT 24
Finished Jul 27 05:59:13 PM PDT 24
Peak memory 200340 kb
Host smart-990fed26-9e05-424e-86e7-ae27b402892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993468711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.993468711
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1253951297
Short name T473
Test name
Test status
Simulation time 15757243281 ps
CPU time 58.4 seconds
Started Jul 27 05:59:10 PM PDT 24
Finished Jul 27 06:00:09 PM PDT 24
Peak memory 200512 kb
Host smart-1959301b-140c-4bed-93f4-84444900de45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253951297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1253951297
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.4089891636
Short name T424
Test name
Test status
Simulation time 357111746 ps
CPU time 2.22 seconds
Started Jul 27 05:59:13 PM PDT 24
Finished Jul 27 05:59:15 PM PDT 24
Peak memory 200192 kb
Host smart-40d80c46-752c-4fe0-a4eb-bc2f94b423f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089891636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4089891636
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.897292924
Short name T529
Test name
Test status
Simulation time 204400061 ps
CPU time 1.29 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:10 PM PDT 24
Peak memory 200096 kb
Host smart-c204d95e-bb01-44d5-b6b7-0d8b2fee4e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897292924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.897292924
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1260067645
Short name T323
Test name
Test status
Simulation time 67864061 ps
CPU time 0.8 seconds
Started Jul 27 05:59:12 PM PDT 24
Finished Jul 27 05:59:13 PM PDT 24
Peak memory 199892 kb
Host smart-3b3f58ed-8b3c-4aaf-8d38-d832c461fc9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260067645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1260067645
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.4248647602
Short name T54
Test name
Test status
Simulation time 1216161756 ps
CPU time 5.19 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:10 PM PDT 24
Peak memory 217500 kb
Host smart-ca7b684b-ead6-48f6-9d0c-182f94bf4e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248647602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.4248647602
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3474687010
Short name T1
Test name
Test status
Simulation time 243416121 ps
CPU time 1.17 seconds
Started Jul 27 05:59:12 PM PDT 24
Finished Jul 27 05:59:14 PM PDT 24
Peak memory 217472 kb
Host smart-7d4be812-efd1-4796-ab9a-1ae6738b4e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474687010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3474687010
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.151857979
Short name T357
Test name
Test status
Simulation time 228372525 ps
CPU time 1.02 seconds
Started Jul 27 05:59:09 PM PDT 24
Finished Jul 27 05:59:10 PM PDT 24
Peak memory 199876 kb
Host smart-b60d7f39-31ad-4bb8-8bfe-3c461b53e78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151857979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.151857979
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3554931130
Short name T26
Test name
Test status
Simulation time 1507465759 ps
CPU time 5.99 seconds
Started Jul 27 05:59:09 PM PDT 24
Finished Jul 27 05:59:15 PM PDT 24
Peak memory 200444 kb
Host smart-3ee61411-671b-4751-86bc-3263d31b241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554931130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3554931130
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2905274726
Short name T152
Test name
Test status
Simulation time 171939812 ps
CPU time 1.16 seconds
Started Jul 27 05:59:13 PM PDT 24
Finished Jul 27 05:59:15 PM PDT 24
Peak memory 200192 kb
Host smart-534c5993-3c99-48c1-8dcf-36ccab75310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905274726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2905274726
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.259478080
Short name T270
Test name
Test status
Simulation time 115411355 ps
CPU time 1.2 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 200292 kb
Host smart-e702797c-4b3d-4fc2-8707-b0a870ea7f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259478080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.259478080
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3000942748
Short name T519
Test name
Test status
Simulation time 7407221362 ps
CPU time 34.1 seconds
Started Jul 27 05:59:02 PM PDT 24
Finished Jul 27 05:59:37 PM PDT 24
Peak memory 208656 kb
Host smart-ecd9de36-1fdf-450f-80a9-fbef01ccaa6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000942748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3000942748
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.440475772
Short name T233
Test name
Test status
Simulation time 543652936 ps
CPU time 2.65 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:07 PM PDT 24
Peak memory 200140 kb
Host smart-317fe0a3-9adf-40d9-9517-1f3087761f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440475772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.440475772
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2651675604
Short name T348
Test name
Test status
Simulation time 85663843 ps
CPU time 0.87 seconds
Started Jul 27 05:59:06 PM PDT 24
Finished Jul 27 05:59:07 PM PDT 24
Peak memory 200108 kb
Host smart-01bfc2b7-0539-4c3e-a184-c1bd6fb4d833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651675604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2651675604
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1822305280
Short name T212
Test name
Test status
Simulation time 80371140 ps
CPU time 0.79 seconds
Started Jul 27 05:59:19 PM PDT 24
Finished Jul 27 05:59:20 PM PDT 24
Peak memory 199912 kb
Host smart-4ef061ca-d36b-467e-9c2c-1dd516aeafa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822305280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1822305280
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2437733261
Short name T25
Test name
Test status
Simulation time 1896830406 ps
CPU time 7.64 seconds
Started Jul 27 05:59:04 PM PDT 24
Finished Jul 27 05:59:12 PM PDT 24
Peak memory 217504 kb
Host smart-d5c2be54-96c6-46d7-8c76-ee7c234cd0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437733261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2437733261
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3639740567
Short name T313
Test name
Test status
Simulation time 244659741 ps
CPU time 1.08 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 217524 kb
Host smart-bacd230e-06c0-4f72-aa59-b4da84799cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639740567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3639740567
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.118355753
Short name T476
Test name
Test status
Simulation time 76954157 ps
CPU time 0.8 seconds
Started Jul 27 05:59:13 PM PDT 24
Finished Jul 27 05:59:14 PM PDT 24
Peak memory 199944 kb
Host smart-90e26064-356c-449d-a913-de7003d4d61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118355753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.118355753
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.691299468
Short name T493
Test name
Test status
Simulation time 1027332682 ps
CPU time 5.31 seconds
Started Jul 27 05:59:15 PM PDT 24
Finished Jul 27 05:59:20 PM PDT 24
Peak memory 200408 kb
Host smart-4f01650e-d7bd-47e5-ab6a-d703ea342730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691299468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.691299468
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3374135142
Short name T403
Test name
Test status
Simulation time 109572438 ps
CPU time 1.03 seconds
Started Jul 27 05:59:05 PM PDT 24
Finished Jul 27 05:59:06 PM PDT 24
Peak memory 200104 kb
Host smart-c0980979-7000-415f-a7e1-aa2142813e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374135142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3374135142
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2293203992
Short name T207
Test name
Test status
Simulation time 119324371 ps
CPU time 1.2 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 200300 kb
Host smart-46b00698-7d3a-47a1-9683-9cc578d8321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293203992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2293203992
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2782291723
Short name T167
Test name
Test status
Simulation time 3069050953 ps
CPU time 13.96 seconds
Started Jul 27 05:59:12 PM PDT 24
Finished Jul 27 05:59:26 PM PDT 24
Peak memory 200460 kb
Host smart-30820d31-2bf7-42aa-899e-2efd13a450e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782291723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2782291723
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1728395644
Short name T390
Test name
Test status
Simulation time 270404848 ps
CPU time 1.86 seconds
Started Jul 27 05:59:07 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 200104 kb
Host smart-1f1907c0-e50c-4511-9786-c55dd3077c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728395644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1728395644
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.585510493
Short name T136
Test name
Test status
Simulation time 68079355 ps
CPU time 0.79 seconds
Started Jul 27 05:59:09 PM PDT 24
Finished Jul 27 05:59:10 PM PDT 24
Peak memory 200064 kb
Host smart-1a14c598-27a6-45e6-a44c-d48f556ff88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585510493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.585510493
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3115934777
Short name T394
Test name
Test status
Simulation time 77776686 ps
CPU time 0.89 seconds
Started Jul 27 05:59:08 PM PDT 24
Finished Jul 27 05:59:09 PM PDT 24
Peak memory 199932 kb
Host smart-66778687-0897-45cd-87ea-78c1f936e81d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115934777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3115934777
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.339000600
Short name T218
Test name
Test status
Simulation time 243498429 ps
CPU time 1.13 seconds
Started Jul 27 05:59:14 PM PDT 24
Finished Jul 27 05:59:15 PM PDT 24
Peak memory 217340 kb
Host smart-95068c91-ed03-4948-9eed-ddc824660d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339000600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.339000600
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.437579480
Short name T286
Test name
Test status
Simulation time 159248126 ps
CPU time 0.83 seconds
Started Jul 27 05:59:14 PM PDT 24
Finished Jul 27 05:59:15 PM PDT 24
Peak memory 199972 kb
Host smart-a282c18d-5e29-4d7f-8759-0d31be94a4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437579480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.437579480
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2636461686
Short name T49
Test name
Test status
Simulation time 891286647 ps
CPU time 4.73 seconds
Started Jul 27 05:59:15 PM PDT 24
Finished Jul 27 05:59:20 PM PDT 24
Peak memory 200396 kb
Host smart-1a8c431a-bf98-4ead-8d45-52c385fdf5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636461686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2636461686
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1810041171
Short name T139
Test name
Test status
Simulation time 104776857 ps
CPU time 1.01 seconds
Started Jul 27 05:59:10 PM PDT 24
Finished Jul 27 05:59:11 PM PDT 24
Peak memory 200072 kb
Host smart-68be9d6e-5e01-4570-9b79-a81aa25eec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810041171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1810041171
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.906209032
Short name T156
Test name
Test status
Simulation time 109915461 ps
CPU time 1.21 seconds
Started Jul 27 05:59:20 PM PDT 24
Finished Jul 27 05:59:21 PM PDT 24
Peak memory 200320 kb
Host smart-5b8455fd-de3e-4b94-8ceb-53ac4be8b5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906209032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.906209032
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1663290385
Short name T539
Test name
Test status
Simulation time 4037595354 ps
CPU time 17.73 seconds
Started Jul 27 05:59:13 PM PDT 24
Finished Jul 27 05:59:31 PM PDT 24
Peak memory 200372 kb
Host smart-d4cedbd6-29e0-49fc-8f8e-0eaddfdcd315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663290385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1663290385
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.349308515
Short name T253
Test name
Test status
Simulation time 385818770 ps
CPU time 2.12 seconds
Started Jul 27 05:59:11 PM PDT 24
Finished Jul 27 05:59:14 PM PDT 24
Peak memory 200136 kb
Host smart-3df77dc8-1c54-4a24-8303-475cfb771434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349308515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.349308515
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3942496147
Short name T141
Test name
Test status
Simulation time 76999132 ps
CPU time 0.81 seconds
Started Jul 27 05:59:13 PM PDT 24
Finished Jul 27 05:59:14 PM PDT 24
Peak memory 200204 kb
Host smart-636eefb4-5758-413c-88e5-91a4f2cd6ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942496147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3942496147
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3626780775
Short name T228
Test name
Test status
Simulation time 63695475 ps
CPU time 0.77 seconds
Started Jul 27 05:58:37 PM PDT 24
Finished Jul 27 05:58:38 PM PDT 24
Peak memory 199932 kb
Host smart-81d905c2-c69a-4ac9-a060-ead2a068d8d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626780775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3626780775
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1049042565
Short name T32
Test name
Test status
Simulation time 2357383257 ps
CPU time 7.9 seconds
Started Jul 27 05:58:34 PM PDT 24
Finished Jul 27 05:58:42 PM PDT 24
Peak memory 221812 kb
Host smart-93110baf-d614-4c3b-bb1b-d0e3953bc05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049042565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1049042565
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.985615898
Short name T182
Test name
Test status
Simulation time 243494655 ps
CPU time 1.09 seconds
Started Jul 27 05:58:41 PM PDT 24
Finished Jul 27 05:58:42 PM PDT 24
Peak memory 217408 kb
Host smart-3e3119de-a9cb-4893-bdd0-9587a4f7b9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985615898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.985615898
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2236182336
Short name T427
Test name
Test status
Simulation time 123735458 ps
CPU time 0.8 seconds
Started Jul 27 05:58:43 PM PDT 24
Finished Jul 27 05:58:44 PM PDT 24
Peak memory 199892 kb
Host smart-da1eec0f-b6b6-4f9f-81b2-73b00861fbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236182336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2236182336
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1284284779
Short name T231
Test name
Test status
Simulation time 1817536860 ps
CPU time 7.21 seconds
Started Jul 27 05:58:33 PM PDT 24
Finished Jul 27 05:58:40 PM PDT 24
Peak memory 200604 kb
Host smart-98210a3c-200e-4622-9cb7-137390aa43c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284284779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1284284779
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1721597843
Short name T280
Test name
Test status
Simulation time 192581503 ps
CPU time 1.21 seconds
Started Jul 27 05:58:30 PM PDT 24
Finished Jul 27 05:58:31 PM PDT 24
Peak memory 200080 kb
Host smart-452cd319-1066-47ef-946d-91f47d315963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721597843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1721597843
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1823858944
Short name T437
Test name
Test status
Simulation time 199083192 ps
CPU time 1.39 seconds
Started Jul 27 05:58:30 PM PDT 24
Finished Jul 27 05:58:32 PM PDT 24
Peak memory 200288 kb
Host smart-134bc0f9-7c7e-4785-ae70-2b555431724b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823858944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1823858944
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.4283111431
Short name T344
Test name
Test status
Simulation time 6505298366 ps
CPU time 22.9 seconds
Started Jul 27 05:58:35 PM PDT 24
Finished Jul 27 05:58:58 PM PDT 24
Peak memory 208660 kb
Host smart-20ee0594-7c26-4dcb-9a18-dc5921570cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283111431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.4283111431
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1106842541
Short name T234
Test name
Test status
Simulation time 451787860 ps
CPU time 2.43 seconds
Started Jul 27 05:58:37 PM PDT 24
Finished Jul 27 05:58:39 PM PDT 24
Peak memory 200108 kb
Host smart-4b6b5ce5-885f-4782-b826-db3f5c732ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106842541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1106842541
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1704867452
Short name T392
Test name
Test status
Simulation time 148905215 ps
CPU time 1.25 seconds
Started Jul 27 05:58:42 PM PDT 24
Finished Jul 27 05:58:43 PM PDT 24
Peak memory 200112 kb
Host smart-d4342c62-2b3d-40d5-a520-311e57d64371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704867452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1704867452
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.715696653
Short name T324
Test name
Test status
Simulation time 72314976 ps
CPU time 0.78 seconds
Started Jul 27 05:59:33 PM PDT 24
Finished Jul 27 05:59:34 PM PDT 24
Peak memory 199856 kb
Host smart-21857dd6-d374-421a-8be0-83f26b04f9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715696653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.715696653
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.647531052
Short name T342
Test name
Test status
Simulation time 1883416839 ps
CPU time 6.94 seconds
Started Jul 27 05:59:17 PM PDT 24
Finished Jul 27 05:59:24 PM PDT 24
Peak memory 217736 kb
Host smart-cde3fa49-fcfb-42c3-9a7c-76619a2797a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647531052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.647531052
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2183315461
Short name T251
Test name
Test status
Simulation time 243403685 ps
CPU time 1.12 seconds
Started Jul 27 05:59:15 PM PDT 24
Finished Jul 27 05:59:16 PM PDT 24
Peak memory 217472 kb
Host smart-a5868a77-b4f5-45dd-9d87-2c53115de839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183315461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2183315461
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1978117875
Short name T19
Test name
Test status
Simulation time 76659432 ps
CPU time 0.72 seconds
Started Jul 27 05:59:15 PM PDT 24
Finished Jul 27 05:59:16 PM PDT 24
Peak memory 199848 kb
Host smart-834a4e10-b0c2-48ce-8c3e-1ce9a57df925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978117875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1978117875
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2157497429
Short name T84
Test name
Test status
Simulation time 1448574682 ps
CPU time 5.64 seconds
Started Jul 27 05:59:13 PM PDT 24
Finished Jul 27 05:59:19 PM PDT 24
Peak memory 200372 kb
Host smart-5d48e156-0365-4bde-b4ee-96451628aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157497429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2157497429
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3018643871
Short name T356
Test name
Test status
Simulation time 156860259 ps
CPU time 1.15 seconds
Started Jul 27 05:59:20 PM PDT 24
Finished Jul 27 05:59:21 PM PDT 24
Peak memory 200124 kb
Host smart-b46a98f6-5a86-4b52-9e85-7e0c31af043c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018643871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3018643871
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.965977818
Short name T536
Test name
Test status
Simulation time 114529355 ps
CPU time 1.16 seconds
Started Jul 27 05:59:20 PM PDT 24
Finished Jul 27 05:59:22 PM PDT 24
Peak memory 200336 kb
Host smart-8e39c258-c2f6-4134-928e-d388e3e6b869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965977818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.965977818
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3576359942
Short name T159
Test name
Test status
Simulation time 4226889919 ps
CPU time 15.89 seconds
Started Jul 27 05:59:19 PM PDT 24
Finished Jul 27 05:59:35 PM PDT 24
Peak memory 200440 kb
Host smart-e5bb64d7-0728-45fe-9447-2d9b3512744e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576359942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3576359942
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3001372244
Short name T537
Test name
Test status
Simulation time 354816200 ps
CPU time 2.2 seconds
Started Jul 27 05:59:10 PM PDT 24
Finished Jul 27 05:59:12 PM PDT 24
Peak memory 200092 kb
Host smart-4abee59c-bd08-45d4-a786-ca5bf84429b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001372244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3001372244
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.633123831
Short name T232
Test name
Test status
Simulation time 254940425 ps
CPU time 1.31 seconds
Started Jul 27 05:59:20 PM PDT 24
Finished Jul 27 05:59:21 PM PDT 24
Peak memory 200120 kb
Host smart-fb8cb6fa-f489-4686-9968-42ac79500f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633123831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.633123831
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1818551046
Short name T294
Test name
Test status
Simulation time 75856453 ps
CPU time 0.77 seconds
Started Jul 27 05:59:26 PM PDT 24
Finished Jul 27 05:59:26 PM PDT 24
Peak memory 199892 kb
Host smart-ad0441c9-432c-4be5-9342-7b6e3c25afde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818551046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1818551046
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2881184170
Short name T507
Test name
Test status
Simulation time 1227549660 ps
CPU time 5.34 seconds
Started Jul 27 05:59:28 PM PDT 24
Finished Jul 27 05:59:33 PM PDT 24
Peak memory 221772 kb
Host smart-d1df830f-6844-4bc4-9f0c-298811543f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881184170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2881184170
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2395394354
Short name T302
Test name
Test status
Simulation time 243777267 ps
CPU time 1.07 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:27 PM PDT 24
Peak memory 217436 kb
Host smart-6dc34752-c15c-43aa-a81f-d67bb7c994aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395394354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2395394354
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3945841662
Short name T512
Test name
Test status
Simulation time 204105775 ps
CPU time 0.87 seconds
Started Jul 27 05:59:19 PM PDT 24
Finished Jul 27 05:59:20 PM PDT 24
Peak memory 199940 kb
Host smart-9c660754-af74-4eaa-ad50-39783eb0ee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945841662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3945841662
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2256319476
Short name T160
Test name
Test status
Simulation time 1379959140 ps
CPU time 5.41 seconds
Started Jul 27 05:59:21 PM PDT 24
Finished Jul 27 05:59:27 PM PDT 24
Peak memory 200392 kb
Host smart-b9dfdb57-abd0-49c3-87ee-e03ecdc70fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256319476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2256319476
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.580697399
Short name T491
Test name
Test status
Simulation time 107954389 ps
CPU time 1.03 seconds
Started Jul 27 05:59:27 PM PDT 24
Finished Jul 27 05:59:28 PM PDT 24
Peak memory 200132 kb
Host smart-c689fb9b-b2e6-48b2-a2d7-37596b2119be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580697399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.580697399
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2757834437
Short name T61
Test name
Test status
Simulation time 118981053 ps
CPU time 1.16 seconds
Started Jul 27 05:59:16 PM PDT 24
Finished Jul 27 05:59:17 PM PDT 24
Peak memory 200196 kb
Host smart-75dd9859-1831-41f5-99fe-5222cf958af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757834437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2757834437
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1417646229
Short name T301
Test name
Test status
Simulation time 5277899776 ps
CPU time 20.69 seconds
Started Jul 27 05:59:22 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 200472 kb
Host smart-3831f460-0f01-48a1-84c5-dc3c90544527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417646229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1417646229
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2869510224
Short name T199
Test name
Test status
Simulation time 538610585 ps
CPU time 2.64 seconds
Started Jul 27 05:59:40 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 200092 kb
Host smart-f008436d-d554-4745-9c08-00575a3d7f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869510224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2869510224
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3127966811
Short name T396
Test name
Test status
Simulation time 137785317 ps
CPU time 1 seconds
Started Jul 27 05:59:21 PM PDT 24
Finished Jul 27 05:59:23 PM PDT 24
Peak memory 200140 kb
Host smart-675b9d0b-0d0f-4150-8807-0e6fc49c7448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127966811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3127966811
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3887661734
Short name T352
Test name
Test status
Simulation time 67453324 ps
CPU time 0.83 seconds
Started Jul 27 05:59:17 PM PDT 24
Finished Jul 27 05:59:18 PM PDT 24
Peak memory 199864 kb
Host smart-f9b5e407-d99e-4c9a-90ac-38244fc983ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887661734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3887661734
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1116226028
Short name T306
Test name
Test status
Simulation time 1903001012 ps
CPU time 7.43 seconds
Started Jul 27 05:59:23 PM PDT 24
Finished Jul 27 05:59:30 PM PDT 24
Peak memory 217536 kb
Host smart-34c9319a-3c18-4897-9309-1daae67bb7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116226028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1116226028
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.856372143
Short name T259
Test name
Test status
Simulation time 243983668 ps
CPU time 1.1 seconds
Started Jul 27 05:59:22 PM PDT 24
Finished Jul 27 05:59:24 PM PDT 24
Peak memory 217500 kb
Host smart-c1e6e0bb-0c95-4b98-b6ce-5088e4ed904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856372143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.856372143
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3487732682
Short name T337
Test name
Test status
Simulation time 176665441 ps
CPU time 0.91 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:26 PM PDT 24
Peak memory 199944 kb
Host smart-3a5bbb39-9a7b-4f33-ae47-317ad81641f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487732682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3487732682
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.512931020
Short name T318
Test name
Test status
Simulation time 106231768 ps
CPU time 0.98 seconds
Started Jul 27 05:59:26 PM PDT 24
Finished Jul 27 05:59:27 PM PDT 24
Peak memory 200156 kb
Host smart-11d2919c-32aa-4b10-b095-798cd09c6f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512931020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.512931020
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2062890625
Short name T147
Test name
Test status
Simulation time 126624691 ps
CPU time 1.19 seconds
Started Jul 27 05:59:36 PM PDT 24
Finished Jul 27 05:59:38 PM PDT 24
Peak memory 200224 kb
Host smart-fdc86cdc-31f4-401f-84fe-23f5c8722cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062890625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2062890625
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1858878878
Short name T281
Test name
Test status
Simulation time 3438435665 ps
CPU time 14.99 seconds
Started Jul 27 05:59:26 PM PDT 24
Finished Jul 27 05:59:41 PM PDT 24
Peak memory 200476 kb
Host smart-926e3eab-1f83-416d-aff3-25f5da9fc5ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858878878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1858878878
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.806377891
Short name T451
Test name
Test status
Simulation time 149866054 ps
CPU time 1.78 seconds
Started Jul 27 05:59:18 PM PDT 24
Finished Jul 27 05:59:20 PM PDT 24
Peak memory 200092 kb
Host smart-d3815f7b-4606-4d94-96df-622dffc115b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806377891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.806377891
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1014679384
Short name T467
Test name
Test status
Simulation time 219745278 ps
CPU time 1.27 seconds
Started Jul 27 05:59:21 PM PDT 24
Finished Jul 27 05:59:23 PM PDT 24
Peak memory 200040 kb
Host smart-94de09f5-3534-4449-bd09-61b8180ad4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014679384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1014679384
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2402783919
Short name T322
Test name
Test status
Simulation time 63360571 ps
CPU time 0.74 seconds
Started Jul 27 05:59:24 PM PDT 24
Finished Jul 27 05:59:25 PM PDT 24
Peak memory 199928 kb
Host smart-ebda7b3f-3a44-4420-be00-c25515d77926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402783919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2402783919
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3739937820
Short name T401
Test name
Test status
Simulation time 1894093660 ps
CPU time 7.43 seconds
Started Jul 27 05:59:20 PM PDT 24
Finished Jul 27 05:59:27 PM PDT 24
Peak memory 217704 kb
Host smart-07afe222-460a-4d99-b3b7-426998af0761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739937820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3739937820
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.577114402
Short name T56
Test name
Test status
Simulation time 244948153 ps
CPU time 1.08 seconds
Started Jul 27 05:59:23 PM PDT 24
Finished Jul 27 05:59:24 PM PDT 24
Peak memory 217416 kb
Host smart-7d574431-3c62-4ea5-ab6f-71fba7aa2347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577114402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.577114402
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1624484128
Short name T202
Test name
Test status
Simulation time 125238368 ps
CPU time 0.8 seconds
Started Jul 27 05:59:22 PM PDT 24
Finished Jul 27 05:59:23 PM PDT 24
Peak memory 199848 kb
Host smart-afc3f07c-6914-4581-bc7a-89ec7775862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624484128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1624484128
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3895351131
Short name T81
Test name
Test status
Simulation time 1515161173 ps
CPU time 6.12 seconds
Started Jul 27 05:59:18 PM PDT 24
Finished Jul 27 05:59:25 PM PDT 24
Peak memory 200444 kb
Host smart-ca091894-c09f-4733-877e-255a4d1aa179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895351131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3895351131
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3933655553
Short name T170
Test name
Test status
Simulation time 150948996 ps
CPU time 1.09 seconds
Started Jul 27 05:59:17 PM PDT 24
Finished Jul 27 05:59:19 PM PDT 24
Peak memory 200128 kb
Host smart-a5f926e5-8a30-4044-851b-f781c8891ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933655553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3933655553
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2414916366
Short name T226
Test name
Test status
Simulation time 122532354 ps
CPU time 1.25 seconds
Started Jul 27 05:59:23 PM PDT 24
Finished Jul 27 05:59:24 PM PDT 24
Peak memory 200376 kb
Host smart-3cb5637e-7f5f-4fb7-a43e-48b8d159983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414916366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2414916366
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1525404058
Short name T292
Test name
Test status
Simulation time 3087094664 ps
CPU time 13.73 seconds
Started Jul 27 05:59:17 PM PDT 24
Finished Jul 27 05:59:30 PM PDT 24
Peak memory 200456 kb
Host smart-877e0fb5-d7d1-44b2-933f-c8e827a15758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525404058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1525404058
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2785243170
Short name T433
Test name
Test status
Simulation time 108078194 ps
CPU time 1.45 seconds
Started Jul 27 05:59:16 PM PDT 24
Finished Jul 27 05:59:18 PM PDT 24
Peak memory 200096 kb
Host smart-5b0fbaa6-cab2-4799-b592-594dd75c6f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785243170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2785243170
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2542898618
Short name T487
Test name
Test status
Simulation time 239284955 ps
CPU time 1.35 seconds
Started Jul 27 05:59:23 PM PDT 24
Finished Jul 27 05:59:25 PM PDT 24
Peak memory 200140 kb
Host smart-2310295d-d7d1-4793-a11c-44a49ed8a87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542898618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2542898618
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.731636672
Short name T165
Test name
Test status
Simulation time 66151067 ps
CPU time 0.75 seconds
Started Jul 27 05:59:17 PM PDT 24
Finished Jul 27 05:59:18 PM PDT 24
Peak memory 199972 kb
Host smart-e41bd207-c177-4bb5-a72f-13f22887217e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731636672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.731636672
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3389047025
Short name T515
Test name
Test status
Simulation time 1224578343 ps
CPU time 6.01 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:31 PM PDT 24
Peak memory 217752 kb
Host smart-6e045b96-3047-4221-b749-7c2a6539599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389047025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3389047025
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2536279076
Short name T189
Test name
Test status
Simulation time 245482105 ps
CPU time 1.07 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:27 PM PDT 24
Peak memory 217436 kb
Host smart-f2a5d3c8-d33c-4ede-a702-91efdf103ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536279076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2536279076
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.650289505
Short name T314
Test name
Test status
Simulation time 124288292 ps
CPU time 0.81 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:26 PM PDT 24
Peak memory 199896 kb
Host smart-d2c8b68c-d789-4e20-91b2-fcb054c484ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650289505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.650289505
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.454956887
Short name T370
Test name
Test status
Simulation time 1526883327 ps
CPU time 5.63 seconds
Started Jul 27 05:59:24 PM PDT 24
Finished Jul 27 05:59:30 PM PDT 24
Peak memory 200608 kb
Host smart-1af5f8ce-cd6c-439e-bbe0-27de06010090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454956887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.454956887
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.300725905
Short name T145
Test name
Test status
Simulation time 105774440 ps
CPU time 1 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:27 PM PDT 24
Peak memory 199972 kb
Host smart-73b03578-1c2b-400d-93a7-9be641a07149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300725905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.300725905
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.882233550
Short name T31
Test name
Test status
Simulation time 192822939 ps
CPU time 1.4 seconds
Started Jul 27 05:59:16 PM PDT 24
Finished Jul 27 05:59:17 PM PDT 24
Peak memory 200272 kb
Host smart-4e346284-48ff-4738-a062-ddb204630d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882233550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.882233550
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3589139797
Short name T546
Test name
Test status
Simulation time 2322839229 ps
CPU time 10.81 seconds
Started Jul 27 05:59:20 PM PDT 24
Finished Jul 27 05:59:31 PM PDT 24
Peak memory 208652 kb
Host smart-340198bd-f287-4866-8b32-53caa38fb101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589139797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3589139797
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3416986719
Short name T181
Test name
Test status
Simulation time 151733422 ps
CPU time 1.91 seconds
Started Jul 27 05:59:17 PM PDT 24
Finished Jul 27 05:59:19 PM PDT 24
Peak memory 200012 kb
Host smart-0614696d-f9ef-4cc5-8a3a-2e50ed83d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416986719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3416986719
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1272030156
Short name T42
Test name
Test status
Simulation time 163107002 ps
CPU time 1.24 seconds
Started Jul 27 05:59:22 PM PDT 24
Finished Jul 27 05:59:23 PM PDT 24
Peak memory 200344 kb
Host smart-ddf39a3a-5ba7-43b4-9230-0482c8f5df87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272030156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1272030156
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3651449840
Short name T382
Test name
Test status
Simulation time 53663638 ps
CPU time 0.73 seconds
Started Jul 27 05:59:33 PM PDT 24
Finished Jul 27 05:59:34 PM PDT 24
Peak memory 199896 kb
Host smart-637de401-d014-47b2-af13-3aca6bd55573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651449840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3651449840
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.15213542
Short name T35
Test name
Test status
Simulation time 1230743934 ps
CPU time 5.51 seconds
Started Jul 27 05:59:26 PM PDT 24
Finished Jul 27 05:59:32 PM PDT 24
Peak memory 217848 kb
Host smart-a9bf558a-1ebc-400f-a720-0b7f7f2b23bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15213542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.15213542
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3592681320
Short name T265
Test name
Test status
Simulation time 244247288 ps
CPU time 1.03 seconds
Started Jul 27 05:59:16 PM PDT 24
Finished Jul 27 05:59:17 PM PDT 24
Peak memory 217440 kb
Host smart-b25871ed-0342-472d-8202-e366ba30d5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592681320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3592681320
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3148112035
Short name T245
Test name
Test status
Simulation time 199202774 ps
CPU time 0.92 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:27 PM PDT 24
Peak memory 199820 kb
Host smart-34ab350c-ea16-4d0c-918c-cca0073d7fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148112035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3148112035
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1288974076
Short name T151
Test name
Test status
Simulation time 1661511994 ps
CPU time 6.11 seconds
Started Jul 27 05:59:19 PM PDT 24
Finished Jul 27 05:59:25 PM PDT 24
Peak memory 200604 kb
Host smart-b5d1b797-1651-491a-a096-386d2919190b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288974076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1288974076
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2277387317
Short name T509
Test name
Test status
Simulation time 102570875 ps
CPU time 1.04 seconds
Started Jul 27 05:59:20 PM PDT 24
Finished Jul 27 05:59:21 PM PDT 24
Peak memory 200120 kb
Host smart-545b6471-efb0-43ca-b271-5a301b131d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277387317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2277387317
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2014897752
Short name T399
Test name
Test status
Simulation time 248495978 ps
CPU time 1.45 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:27 PM PDT 24
Peak memory 200300 kb
Host smart-e27fbedb-dfdc-4330-8cc5-9fafe9a3523a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014897752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2014897752
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1285660315
Short name T240
Test name
Test status
Simulation time 6820453464 ps
CPU time 24.43 seconds
Started Jul 27 05:59:40 PM PDT 24
Finished Jul 27 06:00:04 PM PDT 24
Peak memory 200652 kb
Host smart-6d158f84-ebe3-4205-acea-82755c90c381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285660315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1285660315
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1262092599
Short name T465
Test name
Test status
Simulation time 356499015 ps
CPU time 2.53 seconds
Started Jul 27 05:59:15 PM PDT 24
Finished Jul 27 05:59:18 PM PDT 24
Peak memory 200168 kb
Host smart-ca613347-ce62-4e84-b633-7a29f0fcecce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262092599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1262092599
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3629516020
Short name T408
Test name
Test status
Simulation time 102980374 ps
CPU time 0.94 seconds
Started Jul 27 05:59:16 PM PDT 24
Finished Jul 27 05:59:18 PM PDT 24
Peak memory 200080 kb
Host smart-70cb2f3a-ba98-4086-bac5-0529a60ecec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629516020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3629516020
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.88465069
Short name T263
Test name
Test status
Simulation time 72994022 ps
CPU time 0.77 seconds
Started Jul 27 05:59:43 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 199892 kb
Host smart-57903025-e177-47d2-9a58-b5080ca66e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88465069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.88465069
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4049842325
Short name T346
Test name
Test status
Simulation time 1224794575 ps
CPU time 5.55 seconds
Started Jul 27 05:59:34 PM PDT 24
Finished Jul 27 05:59:40 PM PDT 24
Peak memory 217564 kb
Host smart-af9fdcb6-b43b-47fa-8b2b-9008ed57ec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049842325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4049842325
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1816599180
Short name T309
Test name
Test status
Simulation time 245568109 ps
CPU time 1.07 seconds
Started Jul 27 05:59:28 PM PDT 24
Finished Jul 27 05:59:29 PM PDT 24
Peak memory 217476 kb
Host smart-0c9aaf68-0ee2-48dd-ab5c-4a98e80237f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816599180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1816599180
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1077822890
Short name T362
Test name
Test status
Simulation time 137814511 ps
CPU time 0.89 seconds
Started Jul 27 05:59:38 PM PDT 24
Finished Jul 27 05:59:39 PM PDT 24
Peak memory 199944 kb
Host smart-ca3150a2-83ed-4286-b1ff-4273730cd383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077822890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1077822890
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.72245257
Short name T104
Test name
Test status
Simulation time 745629196 ps
CPU time 3.66 seconds
Started Jul 27 05:59:22 PM PDT 24
Finished Jul 27 05:59:25 PM PDT 24
Peak memory 200400 kb
Host smart-49c390c8-ea66-44dc-9b2a-a4ac5fa6a617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72245257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.72245257
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2757994937
Short name T142
Test name
Test status
Simulation time 113277438 ps
CPU time 1.02 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 200096 kb
Host smart-dcbd72f8-801d-469b-88c6-900256dfed7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757994937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2757994937
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3759642517
Short name T330
Test name
Test status
Simulation time 244700635 ps
CPU time 1.39 seconds
Started Jul 27 05:59:32 PM PDT 24
Finished Jul 27 05:59:33 PM PDT 24
Peak memory 200328 kb
Host smart-575d81fc-edd2-4ce0-af91-61cf88d6aff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759642517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3759642517
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.478569322
Short name T416
Test name
Test status
Simulation time 8553525070 ps
CPU time 31.68 seconds
Started Jul 27 05:59:29 PM PDT 24
Finished Jul 27 06:00:01 PM PDT 24
Peak memory 200336 kb
Host smart-48e98fbf-dbeb-4686-bf92-85056eb098da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478569322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.478569322
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.553200986
Short name T413
Test name
Test status
Simulation time 463819772 ps
CPU time 2.79 seconds
Started Jul 27 05:59:28 PM PDT 24
Finished Jul 27 05:59:31 PM PDT 24
Peak memory 200052 kb
Host smart-67d88ae4-bf41-4f81-9b53-90995395baac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553200986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.553200986
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3425446301
Short name T319
Test name
Test status
Simulation time 83814586 ps
CPU time 0.78 seconds
Started Jul 27 05:59:28 PM PDT 24
Finished Jul 27 05:59:29 PM PDT 24
Peak memory 200144 kb
Host smart-802e9655-68d5-4009-b5a7-2824b3546efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425446301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3425446301
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.294575260
Short name T225
Test name
Test status
Simulation time 75662384 ps
CPU time 0.81 seconds
Started Jul 27 05:59:28 PM PDT 24
Finished Jul 27 05:59:29 PM PDT 24
Peak memory 199908 kb
Host smart-ff32e4c0-4ecb-460d-854a-9ceb7d384dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294575260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.294575260
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3089955670
Short name T37
Test name
Test status
Simulation time 1890218123 ps
CPU time 7.23 seconds
Started Jul 27 05:59:29 PM PDT 24
Finished Jul 27 05:59:37 PM PDT 24
Peak memory 217536 kb
Host smart-4972f58e-741c-47d0-90cf-0b3767395d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089955670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3089955670
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2775417228
Short name T484
Test name
Test status
Simulation time 245742142 ps
CPU time 1.04 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:27 PM PDT 24
Peak memory 217500 kb
Host smart-628b3b05-2dfc-43ea-be6d-50ef58ff611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775417228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2775417228
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3353358258
Short name T341
Test name
Test status
Simulation time 197078393 ps
CPU time 1.04 seconds
Started Jul 27 05:59:24 PM PDT 24
Finished Jul 27 05:59:25 PM PDT 24
Peak memory 199948 kb
Host smart-d2278aff-59bb-4516-a9e8-c398c7d1cb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353358258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3353358258
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.569214663
Short name T466
Test name
Test status
Simulation time 1520049046 ps
CPU time 6.27 seconds
Started Jul 27 05:59:25 PM PDT 24
Finished Jul 27 05:59:31 PM PDT 24
Peak memory 200440 kb
Host smart-c51b9b4a-3651-43fb-8e3d-b3e2a781538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569214663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.569214663
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3218977362
Short name T544
Test name
Test status
Simulation time 140913804 ps
CPU time 1.12 seconds
Started Jul 27 05:59:21 PM PDT 24
Finished Jul 27 05:59:23 PM PDT 24
Peak memory 200116 kb
Host smart-e40df414-b4ce-4626-9932-da8f1871d064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218977362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3218977362
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2365881788
Short name T368
Test name
Test status
Simulation time 203998159 ps
CPU time 1.32 seconds
Started Jul 27 05:59:27 PM PDT 24
Finished Jul 27 05:59:28 PM PDT 24
Peak memory 200316 kb
Host smart-ec2a23a8-25e1-4650-b074-559c4b410446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365881788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2365881788
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3251734127
Short name T88
Test name
Test status
Simulation time 329662593 ps
CPU time 1.77 seconds
Started Jul 27 05:59:37 PM PDT 24
Finished Jul 27 05:59:39 PM PDT 24
Peak memory 200268 kb
Host smart-545036a3-8b4d-46d1-a5db-1a4b37e6560d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251734127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3251734127
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.4125258072
Short name T140
Test name
Test status
Simulation time 221078026 ps
CPU time 1.29 seconds
Started Jul 27 05:59:27 PM PDT 24
Finished Jul 27 05:59:28 PM PDT 24
Peak memory 200008 kb
Host smart-6299bebc-b9bb-4e51-86df-3e5cb6d78b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125258072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.4125258072
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3851133982
Short name T299
Test name
Test status
Simulation time 85024416 ps
CPU time 0.82 seconds
Started Jul 27 05:59:27 PM PDT 24
Finished Jul 27 05:59:28 PM PDT 24
Peak memory 199936 kb
Host smart-82b3f642-5a7f-482a-ab51-d2d534fdcc1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851133982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3851133982
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.845609326
Short name T532
Test name
Test status
Simulation time 1228949322 ps
CPU time 6.08 seconds
Started Jul 27 05:59:29 PM PDT 24
Finished Jul 27 05:59:36 PM PDT 24
Peak memory 217820 kb
Host smart-2ec082db-b0fc-4500-9555-f9a49940470f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845609326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.845609326
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.870411708
Short name T418
Test name
Test status
Simulation time 243539515 ps
CPU time 1.07 seconds
Started Jul 27 05:59:41 PM PDT 24
Finished Jul 27 05:59:42 PM PDT 24
Peak memory 217472 kb
Host smart-731e5072-2643-494c-bece-fa1ccf71d5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870411708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.870411708
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3702963731
Short name T273
Test name
Test status
Simulation time 238787522 ps
CPU time 1.01 seconds
Started Jul 27 05:59:32 PM PDT 24
Finished Jul 27 05:59:34 PM PDT 24
Peak memory 199940 kb
Host smart-4b971020-1fbf-4e59-bb0d-a8cf2d37dd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702963731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3702963731
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1078221862
Short name T103
Test name
Test status
Simulation time 1978590615 ps
CPU time 6.97 seconds
Started Jul 27 05:59:33 PM PDT 24
Finished Jul 27 05:59:40 PM PDT 24
Peak memory 200472 kb
Host smart-115d1177-adf8-4bfb-887b-b970f878fb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078221862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1078221862
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.654212485
Short name T499
Test name
Test status
Simulation time 173403328 ps
CPU time 1.23 seconds
Started Jul 27 05:59:38 PM PDT 24
Finished Jul 27 05:59:39 PM PDT 24
Peak memory 200116 kb
Host smart-8b2860b2-b801-4070-8f82-3702f9da7fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654212485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.654212485
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1734362551
Short name T387
Test name
Test status
Simulation time 124025631 ps
CPU time 1.3 seconds
Started Jul 27 05:59:27 PM PDT 24
Finished Jul 27 05:59:29 PM PDT 24
Peak memory 200300 kb
Host smart-f663bb23-9c68-4ada-9ed1-8408ebd03377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734362551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1734362551
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3801467161
Short name T267
Test name
Test status
Simulation time 2860057167 ps
CPU time 11.42 seconds
Started Jul 27 05:59:26 PM PDT 24
Finished Jul 27 05:59:38 PM PDT 24
Peak memory 208536 kb
Host smart-343c5d0d-c4e2-4bdb-8fdf-0b464b1d4f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801467161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3801467161
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1099387170
Short name T272
Test name
Test status
Simulation time 498742868 ps
CPU time 2.52 seconds
Started Jul 27 05:59:32 PM PDT 24
Finished Jul 27 05:59:35 PM PDT 24
Peak memory 200152 kb
Host smart-c2b3febe-0899-4649-9702-110ee2240692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099387170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1099387170
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.563122723
Short name T14
Test name
Test status
Simulation time 148898306 ps
CPU time 1.19 seconds
Started Jul 27 05:59:36 PM PDT 24
Finished Jul 27 05:59:37 PM PDT 24
Peak memory 200172 kb
Host smart-00e21c54-4ee8-4fe4-bc69-683685584210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563122723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.563122723
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.259482774
Short name T252
Test name
Test status
Simulation time 80537568 ps
CPU time 0.85 seconds
Started Jul 27 05:59:41 PM PDT 24
Finished Jul 27 05:59:42 PM PDT 24
Peak memory 199936 kb
Host smart-a633b3f9-6f33-4fdd-9848-c705b8c29f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259482774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.259482774
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1782715115
Short name T10
Test name
Test status
Simulation time 1890803767 ps
CPU time 7.97 seconds
Started Jul 27 05:59:27 PM PDT 24
Finished Jul 27 05:59:35 PM PDT 24
Peak memory 217416 kb
Host smart-a6dccb3d-077e-4aa2-afb8-d4c383209faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782715115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1782715115
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2357016887
Short name T361
Test name
Test status
Simulation time 243571535 ps
CPU time 1.1 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 217440 kb
Host smart-9f0a6fd2-cb6c-4248-84a7-a6ac9a8e62a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357016887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2357016887
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3303721044
Short name T22
Test name
Test status
Simulation time 180373757 ps
CPU time 0.84 seconds
Started Jul 27 05:59:24 PM PDT 24
Finished Jul 27 05:59:25 PM PDT 24
Peak memory 200152 kb
Host smart-0db4aa74-64e9-462b-8e9a-8b7408025a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303721044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3303721044
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3239852140
Short name T157
Test name
Test status
Simulation time 875545610 ps
CPU time 4.46 seconds
Started Jul 27 05:59:28 PM PDT 24
Finished Jul 27 05:59:32 PM PDT 24
Peak memory 200344 kb
Host smart-f0d46531-e4ac-44c4-93b2-47516846152f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239852140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3239852140
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.4020802176
Short name T201
Test name
Test status
Simulation time 144998794 ps
CPU time 1.16 seconds
Started Jul 27 05:59:38 PM PDT 24
Finished Jul 27 05:59:41 PM PDT 24
Peak memory 200124 kb
Host smart-51280324-e4d6-4ca6-8f86-4545116b841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020802176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.4020802176
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.971083458
Short name T458
Test name
Test status
Simulation time 120828173 ps
CPU time 1.14 seconds
Started Jul 27 05:59:40 PM PDT 24
Finished Jul 27 05:59:41 PM PDT 24
Peak memory 200352 kb
Host smart-2c9eb57c-5c9b-4433-99d0-cae27584237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971083458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.971083458
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.58116376
Short name T355
Test name
Test status
Simulation time 4115306074 ps
CPU time 15.08 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:58 PM PDT 24
Peak memory 200440 kb
Host smart-bba4aa79-850d-4989-9adf-32a69f9dbbcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58116376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.58116376
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3465515908
Short name T410
Test name
Test status
Simulation time 340165923 ps
CPU time 2.26 seconds
Started Jul 27 05:59:30 PM PDT 24
Finished Jul 27 05:59:32 PM PDT 24
Peak memory 208336 kb
Host smart-6b72ba04-ae16-4fdf-b53b-8661991c6d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465515908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3465515908
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.197895967
Short name T543
Test name
Test status
Simulation time 239121104 ps
CPU time 1.33 seconds
Started Jul 27 05:59:33 PM PDT 24
Finished Jul 27 05:59:34 PM PDT 24
Peak memory 200100 kb
Host smart-bf6d9602-1c80-4381-96f6-45d47f4f15d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197895967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.197895967
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4098986086
Short name T528
Test name
Test status
Simulation time 88941745 ps
CPU time 0.85 seconds
Started Jul 27 05:58:42 PM PDT 24
Finished Jul 27 05:58:43 PM PDT 24
Peak memory 199900 kb
Host smart-bb5ee60d-1df0-4f4a-a048-9aab02fbe249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098986086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4098986086
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2670260358
Short name T38
Test name
Test status
Simulation time 1226201206 ps
CPU time 5.89 seconds
Started Jul 27 05:58:45 PM PDT 24
Finished Jul 27 05:58:51 PM PDT 24
Peak memory 217844 kb
Host smart-1b68a897-e611-4542-837e-45d97d8ce9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670260358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2670260358
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2250807
Short name T197
Test name
Test status
Simulation time 244447436 ps
CPU time 1.14 seconds
Started Jul 27 05:58:28 PM PDT 24
Finished Jul 27 05:58:29 PM PDT 24
Peak memory 217472 kb
Host smart-f16a56da-6605-4e97-b9ff-52f9a44b7af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2250807
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.4025762333
Short name T391
Test name
Test status
Simulation time 125125083 ps
CPU time 0.77 seconds
Started Jul 27 05:58:38 PM PDT 24
Finished Jul 27 05:58:39 PM PDT 24
Peak memory 199900 kb
Host smart-61d0c733-e1ad-4ff1-be23-36abcbe91182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025762333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.4025762333
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.39420812
Short name T291
Test name
Test status
Simulation time 1531755686 ps
CPU time 6.32 seconds
Started Jul 27 05:58:30 PM PDT 24
Finished Jul 27 05:58:36 PM PDT 24
Peak memory 200428 kb
Host smart-be903a50-06f7-4a9b-b8c0-a385a31e7fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39420812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.39420812
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.680213836
Short name T73
Test name
Test status
Simulation time 16540336128 ps
CPU time 24.94 seconds
Started Jul 27 05:58:29 PM PDT 24
Finished Jul 27 05:58:54 PM PDT 24
Peak memory 217512 kb
Host smart-4f776c51-2c9b-4895-8390-b03265dd5ad9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680213836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.680213836
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1758850636
Short name T421
Test name
Test status
Simulation time 154075058 ps
CPU time 1.11 seconds
Started Jul 27 05:58:45 PM PDT 24
Finished Jul 27 05:58:46 PM PDT 24
Peak memory 200080 kb
Host smart-ff66f458-a18d-4d11-b4f5-71a40da2bebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758850636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1758850636
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.993621425
Short name T345
Test name
Test status
Simulation time 198195846 ps
CPU time 1.35 seconds
Started Jul 27 05:58:33 PM PDT 24
Finished Jul 27 05:58:34 PM PDT 24
Peak memory 200540 kb
Host smart-0f81037a-bd40-4d86-b99c-c471dc360e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993621425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.993621425
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3214103397
Short name T86
Test name
Test status
Simulation time 8343937947 ps
CPU time 29.96 seconds
Started Jul 27 05:58:33 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 208708 kb
Host smart-21cbc064-6d19-41c6-bf24-47285d75c8b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214103397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3214103397
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1572157116
Short name T434
Test name
Test status
Simulation time 135112315 ps
CPU time 1.83 seconds
Started Jul 27 05:58:35 PM PDT 24
Finished Jul 27 05:58:37 PM PDT 24
Peak memory 200144 kb
Host smart-659a3923-ea9f-407c-92a8-07e2abdfa703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572157116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1572157116
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.190492238
Short name T379
Test name
Test status
Simulation time 219608136 ps
CPU time 1.31 seconds
Started Jul 27 05:58:44 PM PDT 24
Finished Jul 27 05:58:45 PM PDT 24
Peak memory 200132 kb
Host smart-5cfda7f4-1eec-451e-972a-fc5ce6966333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190492238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.190492238
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1558050363
Short name T258
Test name
Test status
Simulation time 54354797 ps
CPU time 0.72 seconds
Started Jul 27 05:59:33 PM PDT 24
Finished Jul 27 05:59:34 PM PDT 24
Peak memory 199932 kb
Host smart-4520cb63-4dca-4aa5-b644-dcf97087db73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558050363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1558050363
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3491598409
Short name T33
Test name
Test status
Simulation time 2350426501 ps
CPU time 8.34 seconds
Started Jul 27 05:59:48 PM PDT 24
Finished Jul 27 05:59:56 PM PDT 24
Peak memory 217916 kb
Host smart-4f355484-83c4-4a78-b68f-82542fcdc377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491598409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3491598409
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2853019065
Short name T372
Test name
Test status
Simulation time 245488640 ps
CPU time 1.05 seconds
Started Jul 27 05:59:39 PM PDT 24
Finished Jul 27 05:59:40 PM PDT 24
Peak memory 217404 kb
Host smart-0bda73b0-cadb-4922-a16d-fa047a9b5eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853019065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2853019065
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2995297957
Short name T256
Test name
Test status
Simulation time 96870211 ps
CPU time 0.74 seconds
Started Jul 27 05:59:45 PM PDT 24
Finished Jul 27 05:59:46 PM PDT 24
Peak memory 199912 kb
Host smart-9151438a-77e5-45e0-80e0-630f008779ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995297957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2995297957
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1016767994
Short name T127
Test name
Test status
Simulation time 1551876320 ps
CPU time 5.49 seconds
Started Jul 27 05:59:44 PM PDT 24
Finished Jul 27 05:59:50 PM PDT 24
Peak memory 200472 kb
Host smart-102f64ba-811d-41b8-b593-7efbbcc91e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016767994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1016767994
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.786032597
Short name T457
Test name
Test status
Simulation time 178280741 ps
CPU time 1.16 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 200128 kb
Host smart-7b67c8ab-a110-4f23-ac99-5adbdaa1d34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786032597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.786032597
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3848115896
Short name T520
Test name
Test status
Simulation time 109030179 ps
CPU time 1.2 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 200232 kb
Host smart-b2154b47-81f2-4c60-ad9c-48ccb67a8d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848115896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3848115896
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.932209184
Short name T257
Test name
Test status
Simulation time 7848387805 ps
CPU time 27.08 seconds
Started Jul 27 05:59:35 PM PDT 24
Finished Jul 27 06:00:02 PM PDT 24
Peak memory 216788 kb
Host smart-c549cabf-72b2-4224-8be8-80167682da4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932209184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.932209184
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.866211416
Short name T144
Test name
Test status
Simulation time 336410170 ps
CPU time 2.13 seconds
Started Jul 27 05:59:53 PM PDT 24
Finished Jul 27 05:59:55 PM PDT 24
Peak memory 208340 kb
Host smart-ec5eea47-a365-4e30-bb0f-00570477f0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866211416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.866211416
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2494722389
Short name T187
Test name
Test status
Simulation time 119026317 ps
CPU time 1 seconds
Started Jul 27 05:59:41 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 200040 kb
Host smart-d0f254ae-3cde-40e4-b94b-5160641d3d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494722389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2494722389
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.877937505
Short name T166
Test name
Test status
Simulation time 60187988 ps
CPU time 0.74 seconds
Started Jul 27 05:59:43 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 199912 kb
Host smart-deb7c713-fe6a-474c-a9c4-c79149105c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877937505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.877937505
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.4089042447
Short name T513
Test name
Test status
Simulation time 1881911048 ps
CPU time 7.07 seconds
Started Jul 27 05:59:39 PM PDT 24
Finished Jul 27 05:59:47 PM PDT 24
Peak memory 217768 kb
Host smart-91f0024e-e633-4cfa-8fbf-350b749697a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089042447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.4089042447
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3107788752
Short name T297
Test name
Test status
Simulation time 244904121 ps
CPU time 1.08 seconds
Started Jul 27 05:59:43 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 217440 kb
Host smart-2ff0c269-0acd-4300-b461-d8f0eb7d4105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107788752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3107788752
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4129885961
Short name T447
Test name
Test status
Simulation time 188870536 ps
CPU time 0.87 seconds
Started Jul 27 05:59:49 PM PDT 24
Finished Jul 27 05:59:50 PM PDT 24
Peak memory 199876 kb
Host smart-df4e6d78-33bd-4bb3-9c72-cad5cca19733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129885961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4129885961
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3246193718
Short name T472
Test name
Test status
Simulation time 1464917644 ps
CPU time 5.45 seconds
Started Jul 27 05:59:44 PM PDT 24
Finished Jul 27 05:59:50 PM PDT 24
Peak memory 200448 kb
Host smart-23257b38-14c7-4390-9fc2-af42b2057ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246193718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3246193718
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3317505091
Short name T161
Test name
Test status
Simulation time 99909136 ps
CPU time 1 seconds
Started Jul 27 05:59:55 PM PDT 24
Finished Jul 27 05:59:56 PM PDT 24
Peak memory 200104 kb
Host smart-8d48636e-2f80-451c-9a7d-7871fdfb8fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317505091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3317505091
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2875253435
Short name T266
Test name
Test status
Simulation time 120988375 ps
CPU time 1.23 seconds
Started Jul 27 05:59:39 PM PDT 24
Finished Jul 27 05:59:41 PM PDT 24
Peak memory 200184 kb
Host smart-a7d07d87-7d20-4792-aa7d-b64d6cbcb0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875253435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2875253435
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2575334006
Short name T334
Test name
Test status
Simulation time 6424080028 ps
CPU time 25.41 seconds
Started Jul 27 05:59:38 PM PDT 24
Finished Jul 27 06:00:03 PM PDT 24
Peak memory 200432 kb
Host smart-c003dbf0-6ed6-4487-b649-41e8c1b91c1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575334006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2575334006
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1492087166
Short name T492
Test name
Test status
Simulation time 330917193 ps
CPU time 2.12 seconds
Started Jul 27 05:59:59 PM PDT 24
Finished Jul 27 06:00:01 PM PDT 24
Peak memory 208416 kb
Host smart-05efb03f-6de4-48d4-bdeb-226e10615caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492087166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1492087166
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3336729769
Short name T523
Test name
Test status
Simulation time 162855598 ps
CPU time 1.1 seconds
Started Jul 27 05:59:52 PM PDT 24
Finished Jul 27 05:59:54 PM PDT 24
Peak memory 200112 kb
Host smart-d62d2c2b-c3fa-4e72-b0b4-3c0eced190c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336729769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3336729769
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2030779399
Short name T380
Test name
Test status
Simulation time 70399523 ps
CPU time 0.72 seconds
Started Jul 27 05:59:50 PM PDT 24
Finished Jul 27 05:59:50 PM PDT 24
Peak memory 199932 kb
Host smart-ab2c2779-1828-4c1e-815c-441e268be2a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030779399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2030779399
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1935399267
Short name T51
Test name
Test status
Simulation time 2343931212 ps
CPU time 8.8 seconds
Started Jul 27 05:59:40 PM PDT 24
Finished Jul 27 05:59:49 PM PDT 24
Peak memory 221764 kb
Host smart-a8936854-29a7-4ba1-b9c6-2260d2602767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935399267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1935399267
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.481008277
Short name T430
Test name
Test status
Simulation time 243948803 ps
CPU time 1.14 seconds
Started Jul 27 05:59:53 PM PDT 24
Finished Jul 27 05:59:55 PM PDT 24
Peak memory 217492 kb
Host smart-e92244df-0d03-403c-bf9c-4abe696abf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481008277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.481008277
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3371071886
Short name T16
Test name
Test status
Simulation time 92787661 ps
CPU time 0.77 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 199940 kb
Host smart-187b2c7b-33be-4cd6-9eb9-0715cbdaca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371071886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3371071886
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2247854551
Short name T409
Test name
Test status
Simulation time 1029744495 ps
CPU time 5.03 seconds
Started Jul 27 05:59:37 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 200448 kb
Host smart-37898fb1-8f66-443d-9543-cec72fc63224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247854551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2247854551
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.4288940039
Short name T506
Test name
Test status
Simulation time 156745786 ps
CPU time 1.1 seconds
Started Jul 27 05:59:40 PM PDT 24
Finished Jul 27 05:59:41 PM PDT 24
Peak memory 200128 kb
Host smart-10a828fb-f064-46cd-add6-5ccb7aeb3730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288940039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.4288940039
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.665000820
Short name T354
Test name
Test status
Simulation time 194615129 ps
CPU time 1.39 seconds
Started Jul 27 05:59:44 PM PDT 24
Finished Jul 27 05:59:45 PM PDT 24
Peak memory 200292 kb
Host smart-9e62abe5-cac8-4182-8995-3680a113bad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665000820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.665000820
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2437278858
Short name T178
Test name
Test status
Simulation time 2202343554 ps
CPU time 8.71 seconds
Started Jul 27 05:59:47 PM PDT 24
Finished Jul 27 05:59:56 PM PDT 24
Peak memory 200324 kb
Host smart-3e440964-0ed6-4971-98a8-54bcf31777d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437278858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2437278858
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2541728118
Short name T261
Test name
Test status
Simulation time 140696589 ps
CPU time 1.8 seconds
Started Jul 27 05:59:43 PM PDT 24
Finished Jul 27 05:59:45 PM PDT 24
Peak memory 200144 kb
Host smart-641e76b1-433f-4f82-849f-3eb9f629388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541728118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2541728118
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2386292243
Short name T40
Test name
Test status
Simulation time 243997974 ps
CPU time 1.4 seconds
Started Jul 27 05:59:39 PM PDT 24
Finished Jul 27 05:59:41 PM PDT 24
Peak memory 200144 kb
Host smart-168aac85-53a1-4c61-8f6f-95fd2792edb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386292243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2386292243
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2168700321
Short name T186
Test name
Test status
Simulation time 76784644 ps
CPU time 0.8 seconds
Started Jul 27 05:59:38 PM PDT 24
Finished Jul 27 05:59:39 PM PDT 24
Peak memory 199932 kb
Host smart-822c4d69-3826-4755-b70c-a806cf6d2778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168700321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2168700321
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2203351868
Short name T39
Test name
Test status
Simulation time 1240919416 ps
CPU time 5.97 seconds
Started Jul 27 05:59:38 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 216704 kb
Host smart-faaf4bb1-f96f-4156-b729-a28787901cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203351868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2203351868
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.505050647
Short name T446
Test name
Test status
Simulation time 244328165 ps
CPU time 1.1 seconds
Started Jul 27 05:59:35 PM PDT 24
Finished Jul 27 05:59:36 PM PDT 24
Peak memory 217492 kb
Host smart-c27bfe8d-3ce3-4a42-aa54-17efd0a967e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505050647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.505050647
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.55168199
Short name T490
Test name
Test status
Simulation time 148984694 ps
CPU time 0.83 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 199864 kb
Host smart-4193a10e-667d-4c38-9a49-af5594d759a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55168199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.55168199
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1872732126
Short name T455
Test name
Test status
Simulation time 1459171468 ps
CPU time 5.81 seconds
Started Jul 27 05:59:51 PM PDT 24
Finished Jul 27 05:59:57 PM PDT 24
Peak memory 200404 kb
Host smart-fac18108-5ff9-46fd-8496-50f9f8bd70b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872732126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1872732126
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.509756846
Short name T326
Test name
Test status
Simulation time 143780722 ps
CPU time 1.11 seconds
Started Jul 27 05:59:56 PM PDT 24
Finished Jul 27 05:59:57 PM PDT 24
Peak memory 200044 kb
Host smart-71dee756-699b-483e-9ecd-543aa6471d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509756846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.509756846
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2624871208
Short name T192
Test name
Test status
Simulation time 113869416 ps
CPU time 1.18 seconds
Started Jul 27 05:59:53 PM PDT 24
Finished Jul 27 05:59:55 PM PDT 24
Peak memory 200316 kb
Host smart-1a674a54-84dd-437c-b98f-9948cc169ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624871208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2624871208
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3065677158
Short name T190
Test name
Test status
Simulation time 372243174 ps
CPU time 2.12 seconds
Started Jul 27 05:59:46 PM PDT 24
Finished Jul 27 05:59:48 PM PDT 24
Peak memory 200048 kb
Host smart-e01e3213-1ef7-4302-a0f0-5e54cf97a811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065677158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3065677158
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2340405957
Short name T521
Test name
Test status
Simulation time 93613792 ps
CPU time 0.95 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 200164 kb
Host smart-a475da6a-b035-4cb1-8809-c75b008c3d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340405957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2340405957
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1869315533
Short name T236
Test name
Test status
Simulation time 70698766 ps
CPU time 0.81 seconds
Started Jul 27 05:59:34 PM PDT 24
Finished Jul 27 05:59:35 PM PDT 24
Peak memory 199932 kb
Host smart-087afa0d-d6a6-463e-9f00-c939ecd87c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869315533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1869315533
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.348916504
Short name T47
Test name
Test status
Simulation time 1880337883 ps
CPU time 6.88 seconds
Started Jul 27 05:59:53 PM PDT 24
Finished Jul 27 05:59:59 PM PDT 24
Peak memory 221724 kb
Host smart-032d1dce-6648-4321-a46b-773206a33a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348916504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.348916504
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.571511764
Short name T50
Test name
Test status
Simulation time 243860736 ps
CPU time 1.06 seconds
Started Jul 27 05:59:44 PM PDT 24
Finished Jul 27 05:59:45 PM PDT 24
Peak memory 217492 kb
Host smart-68190206-6bd5-4740-a4a1-db5867b8be3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571511764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.571511764
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3961679178
Short name T439
Test name
Test status
Simulation time 158239435 ps
CPU time 0.89 seconds
Started Jul 27 05:59:59 PM PDT 24
Finished Jul 27 06:00:01 PM PDT 24
Peak memory 199920 kb
Host smart-45485d21-eca6-465b-b2ea-93ffc38900b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961679178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3961679178
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2052769144
Short name T28
Test name
Test status
Simulation time 1929631331 ps
CPU time 7.59 seconds
Started Jul 27 05:59:33 PM PDT 24
Finished Jul 27 05:59:40 PM PDT 24
Peak memory 200332 kb
Host smart-4f2b99f1-0e2f-4ba5-831c-e80b2f8ab1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052769144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2052769144
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2257054887
Short name T510
Test name
Test status
Simulation time 106207821 ps
CPU time 1.04 seconds
Started Jul 27 05:59:53 PM PDT 24
Finished Jul 27 05:59:55 PM PDT 24
Peak memory 200056 kb
Host smart-5d84292d-6b24-4af5-937f-254988e6f28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257054887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2257054887
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.733582186
Short name T400
Test name
Test status
Simulation time 202987552 ps
CPU time 1.5 seconds
Started Jul 27 05:59:40 PM PDT 24
Finished Jul 27 05:59:42 PM PDT 24
Peak memory 200340 kb
Host smart-36717c51-5866-41b6-993b-9075823d5022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733582186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.733582186
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3488124439
Short name T373
Test name
Test status
Simulation time 1349007636 ps
CPU time 6.87 seconds
Started Jul 27 05:59:40 PM PDT 24
Finished Jul 27 05:59:47 PM PDT 24
Peak memory 216756 kb
Host smart-8dac4949-498b-4704-9e81-0ec023347039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488124439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3488124439
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1215044119
Short name T384
Test name
Test status
Simulation time 109149784 ps
CPU time 1.43 seconds
Started Jul 27 05:59:45 PM PDT 24
Finished Jul 27 05:59:47 PM PDT 24
Peak memory 200108 kb
Host smart-0a4a0484-2d47-41b7-8d48-95a9efcf86df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215044119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1215044119
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3362760227
Short name T177
Test name
Test status
Simulation time 130943740 ps
CPU time 1.04 seconds
Started Jul 27 05:59:48 PM PDT 24
Finished Jul 27 05:59:49 PM PDT 24
Peak memory 200108 kb
Host smart-f7beda17-2904-43da-bf0e-b523497e84b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362760227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3362760227
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3770998530
Short name T545
Test name
Test status
Simulation time 68787809 ps
CPU time 0.78 seconds
Started Jul 27 05:59:45 PM PDT 24
Finished Jul 27 05:59:46 PM PDT 24
Peak memory 199928 kb
Host smart-ae5d3fdc-da21-428b-9d50-5fa8c83525f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770998530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3770998530
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2411645486
Short name T531
Test name
Test status
Simulation time 1875339595 ps
CPU time 7.3 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:49 PM PDT 24
Peak memory 216840 kb
Host smart-e369931e-a983-445f-b32d-7f027ab68635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411645486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2411645486
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2552301318
Short name T183
Test name
Test status
Simulation time 244662163 ps
CPU time 1.09 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 217460 kb
Host smart-b091af54-88db-4f16-a8b0-2dd01f5b1754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552301318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2552301318
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1021319613
Short name T350
Test name
Test status
Simulation time 106282461 ps
CPU time 0.77 seconds
Started Jul 27 05:59:44 PM PDT 24
Finished Jul 27 05:59:45 PM PDT 24
Peak memory 199932 kb
Host smart-c2459be5-31a4-4e9a-a475-b872dad560d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021319613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1021319613
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3958674515
Short name T126
Test name
Test status
Simulation time 1877178373 ps
CPU time 6.38 seconds
Started Jul 27 05:59:41 PM PDT 24
Finished Jul 27 05:59:47 PM PDT 24
Peak memory 200448 kb
Host smart-c1e720b2-b87b-47b1-a83d-811ce5451a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958674515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3958674515
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1716703624
Short name T135
Test name
Test status
Simulation time 153162125 ps
CPU time 1.1 seconds
Started Jul 27 05:59:54 PM PDT 24
Finished Jul 27 05:59:55 PM PDT 24
Peak memory 199972 kb
Host smart-9bc088ad-f512-4043-a5d1-05491949f8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716703624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1716703624
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1725864253
Short name T171
Test name
Test status
Simulation time 128121079 ps
CPU time 1.19 seconds
Started Jul 27 05:59:44 PM PDT 24
Finished Jul 27 05:59:45 PM PDT 24
Peak memory 200448 kb
Host smart-d9313dba-2079-41ed-b9d7-9a3a658a1a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725864253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1725864253
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2831565933
Short name T285
Test name
Test status
Simulation time 3870060457 ps
CPU time 15.49 seconds
Started Jul 27 05:59:45 PM PDT 24
Finished Jul 27 06:00:01 PM PDT 24
Peak memory 200408 kb
Host smart-14c3bbf1-03a7-4886-aabd-1908fffcd140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831565933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2831565933
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3341681350
Short name T393
Test name
Test status
Simulation time 120742354 ps
CPU time 1.57 seconds
Started Jul 27 05:59:57 PM PDT 24
Finished Jul 27 05:59:58 PM PDT 24
Peak memory 200116 kb
Host smart-a851f10d-d0e9-413a-b815-f98575a78d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341681350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3341681350
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1963792463
Short name T488
Test name
Test status
Simulation time 128578066 ps
CPU time 1.04 seconds
Started Jul 27 05:59:59 PM PDT 24
Finished Jul 27 06:00:00 PM PDT 24
Peak memory 200132 kb
Host smart-824b2ecf-125f-48df-927b-2cd5c67c186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963792463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1963792463
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3678706867
Short name T381
Test name
Test status
Simulation time 90113152 ps
CPU time 0.82 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 199928 kb
Host smart-36bca420-cbdb-43a8-84cc-baaf9d36eec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678706867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3678706867
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.902541040
Short name T325
Test name
Test status
Simulation time 1233490541 ps
CPU time 5.53 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:48 PM PDT 24
Peak memory 217800 kb
Host smart-58ccf41a-fc49-443d-81f7-ca45452b7fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902541040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.902541040
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3619151731
Short name T414
Test name
Test status
Simulation time 244732513 ps
CPU time 1.05 seconds
Started Jul 27 05:59:41 PM PDT 24
Finished Jul 27 05:59:42 PM PDT 24
Peak memory 217448 kb
Host smart-dcba3176-0f24-4def-bda6-917019d06045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619151731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3619151731
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1975252791
Short name T363
Test name
Test status
Simulation time 167827570 ps
CPU time 0.87 seconds
Started Jul 27 05:59:59 PM PDT 24
Finished Jul 27 06:00:00 PM PDT 24
Peak memory 199876 kb
Host smart-a86465b2-b34d-4bdb-b722-3376ba64963b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975252791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1975252791
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1072575963
Short name T360
Test name
Test status
Simulation time 756529331 ps
CPU time 4.23 seconds
Started Jul 27 05:59:52 PM PDT 24
Finished Jul 27 05:59:57 PM PDT 24
Peak memory 200320 kb
Host smart-c897c14e-a64a-41b9-b4bf-2a2a476cc9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072575963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1072575963
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.4121585160
Short name T442
Test name
Test status
Simulation time 171733394 ps
CPU time 1.17 seconds
Started Jul 27 05:59:50 PM PDT 24
Finished Jul 27 05:59:52 PM PDT 24
Peak memory 200076 kb
Host smart-48256b12-d0c9-47a8-a946-f2bdec8e828b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121585160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.4121585160
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2601280487
Short name T276
Test name
Test status
Simulation time 248367870 ps
CPU time 1.45 seconds
Started Jul 27 05:59:44 PM PDT 24
Finished Jul 27 05:59:45 PM PDT 24
Peak memory 200284 kb
Host smart-62164071-6d83-4c74-8f19-80cdad800183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601280487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2601280487
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3965838787
Short name T428
Test name
Test status
Simulation time 5426619380 ps
CPU time 24.22 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 06:00:06 PM PDT 24
Peak memory 200340 kb
Host smart-edfe6f4b-fd32-4c11-a909-888f605dbf16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965838787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3965838787
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1913344125
Short name T340
Test name
Test status
Simulation time 129321688 ps
CPU time 1.62 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 208324 kb
Host smart-19bf3040-78e9-40b3-83b7-76b9bc3c4119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913344125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1913344125
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1649754190
Short name T412
Test name
Test status
Simulation time 118449131 ps
CPU time 1.03 seconds
Started Jul 27 05:59:46 PM PDT 24
Finished Jul 27 05:59:52 PM PDT 24
Peak memory 200128 kb
Host smart-12890f29-6af2-4d68-a30b-129ad87ce01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649754190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1649754190
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3268338708
Short name T173
Test name
Test status
Simulation time 70230185 ps
CPU time 0.77 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 199928 kb
Host smart-756b856a-1449-4092-ac59-5fea048f68ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268338708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3268338708
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1136931263
Short name T59
Test name
Test status
Simulation time 1891378823 ps
CPU time 7.32 seconds
Started Jul 27 05:59:41 PM PDT 24
Finished Jul 27 05:59:49 PM PDT 24
Peak memory 217772 kb
Host smart-6f470c6c-b687-43cf-a58f-90e9ed6e2785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136931263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1136931263
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.528349680
Short name T6
Test name
Test status
Simulation time 244873812 ps
CPU time 1.02 seconds
Started Jul 27 05:59:39 PM PDT 24
Finished Jul 27 05:59:40 PM PDT 24
Peak memory 217524 kb
Host smart-6018dfd0-c9a7-4d54-b12f-d39664f96fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528349680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.528349680
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.4222295994
Short name T456
Test name
Test status
Simulation time 149658723 ps
CPU time 0.82 seconds
Started Jul 27 05:59:49 PM PDT 24
Finished Jul 27 05:59:50 PM PDT 24
Peak memory 200020 kb
Host smart-76fdfa0c-c9ca-460b-a1a1-d6a058186ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222295994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4222295994
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.588483736
Short name T460
Test name
Test status
Simulation time 957947313 ps
CPU time 4.94 seconds
Started Jul 27 05:59:54 PM PDT 24
Finished Jul 27 05:59:59 PM PDT 24
Peak memory 200324 kb
Host smart-2900c485-4cc5-4780-aa33-5911b597cef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588483736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.588483736
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1391370997
Short name T209
Test name
Test status
Simulation time 94109793 ps
CPU time 1.01 seconds
Started Jul 27 05:59:50 PM PDT 24
Finished Jul 27 05:59:52 PM PDT 24
Peak memory 200068 kb
Host smart-fb4ab540-b5cc-456d-9420-8f863ed08d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391370997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1391370997
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2724452010
Short name T174
Test name
Test status
Simulation time 122234760 ps
CPU time 1.19 seconds
Started Jul 27 05:59:46 PM PDT 24
Finished Jul 27 05:59:47 PM PDT 24
Peak memory 200204 kb
Host smart-89089b74-e522-4abd-9bdf-bb38eb4d62f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724452010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2724452010
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1557759443
Short name T176
Test name
Test status
Simulation time 6416202034 ps
CPU time 28.35 seconds
Started Jul 27 05:59:45 PM PDT 24
Finished Jul 27 06:00:13 PM PDT 24
Peak memory 208668 kb
Host smart-3ce81300-a84d-48d4-8685-bea98d616093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557759443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1557759443
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.320350039
Short name T310
Test name
Test status
Simulation time 395118911 ps
CPU time 2.32 seconds
Started Jul 27 05:59:43 PM PDT 24
Finished Jul 27 05:59:45 PM PDT 24
Peak memory 200080 kb
Host smart-ad647a0b-b684-4028-8f0e-ad9d60266c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320350039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.320350039
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1329493719
Short name T287
Test name
Test status
Simulation time 106951995 ps
CPU time 0.92 seconds
Started Jul 27 05:59:39 PM PDT 24
Finished Jul 27 05:59:41 PM PDT 24
Peak memory 200044 kb
Host smart-d3e0003e-3fdb-4422-85f7-a1053520b481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329493719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1329493719
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.214069293
Short name T331
Test name
Test status
Simulation time 72944731 ps
CPU time 0.75 seconds
Started Jul 27 06:00:00 PM PDT 24
Finished Jul 27 06:00:01 PM PDT 24
Peak memory 199924 kb
Host smart-f70cf313-5cf5-4bc3-b3a1-6053ce1845f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214069293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.214069293
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3935313765
Short name T308
Test name
Test status
Simulation time 1235742953 ps
CPU time 5.37 seconds
Started Jul 27 05:59:47 PM PDT 24
Finished Jul 27 05:59:53 PM PDT 24
Peak memory 217420 kb
Host smart-6a8fa35a-7748-4471-98df-d0c5a2ae1f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935313765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3935313765
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3559291749
Short name T304
Test name
Test status
Simulation time 243732126 ps
CPU time 1.12 seconds
Started Jul 27 05:59:47 PM PDT 24
Finished Jul 27 05:59:48 PM PDT 24
Peak memory 217596 kb
Host smart-a0b24768-615f-49c1-afed-a299ec2b4c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559291749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3559291749
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1824989847
Short name T200
Test name
Test status
Simulation time 175083015 ps
CPU time 0.84 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:43 PM PDT 24
Peak memory 199936 kb
Host smart-b424b161-21b1-44ac-b4ff-402dad68ac24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824989847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1824989847
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2466617357
Short name T405
Test name
Test status
Simulation time 1559533417 ps
CPU time 6.24 seconds
Started Jul 27 05:59:46 PM PDT 24
Finished Jul 27 05:59:52 PM PDT 24
Peak memory 200400 kb
Host smart-656a35cd-784d-4d15-a819-f4df5de81fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466617357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2466617357
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1609677416
Short name T41
Test name
Test status
Simulation time 146954148 ps
CPU time 1.1 seconds
Started Jul 27 05:59:45 PM PDT 24
Finished Jul 27 05:59:46 PM PDT 24
Peak memory 200128 kb
Host smart-fc1ce295-1af2-4f24-9520-e152f821d7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609677416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1609677416
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3665564624
Short name T211
Test name
Test status
Simulation time 115620239 ps
CPU time 1.17 seconds
Started Jul 27 05:59:45 PM PDT 24
Finished Jul 27 05:59:46 PM PDT 24
Peak memory 200336 kb
Host smart-dec296a9-37bf-463b-aeba-9c61c124cb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665564624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3665564624
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3787375951
Short name T3
Test name
Test status
Simulation time 2106630053 ps
CPU time 8.77 seconds
Started Jul 27 05:59:51 PM PDT 24
Finished Jul 27 06:00:00 PM PDT 24
Peak memory 208608 kb
Host smart-2290aa73-3b74-4bf4-b5cd-87eea48aa257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787375951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3787375951
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.337312172
Short name T129
Test name
Test status
Simulation time 536693537 ps
CPU time 2.82 seconds
Started Jul 27 05:59:44 PM PDT 24
Finished Jul 27 05:59:47 PM PDT 24
Peak memory 199992 kb
Host smart-5ad1f009-46db-4290-9004-3c7bdf3a2dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337312172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.337312172
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1135344235
Short name T389
Test name
Test status
Simulation time 226458513 ps
CPU time 1.51 seconds
Started Jul 27 05:59:40 PM PDT 24
Finished Jul 27 05:59:41 PM PDT 24
Peak memory 200108 kb
Host smart-58b44bc2-b7f0-4157-97a4-5275dc398775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135344235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1135344235
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.4258042031
Short name T77
Test name
Test status
Simulation time 71239385 ps
CPU time 0.78 seconds
Started Jul 27 05:59:41 PM PDT 24
Finished Jul 27 05:59:42 PM PDT 24
Peak memory 199880 kb
Host smart-90d951c6-4db6-44a5-af2e-2660abf508e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258042031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4258042031
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.89437138
Short name T27
Test name
Test status
Simulation time 1231592219 ps
CPU time 5.61 seconds
Started Jul 27 05:59:47 PM PDT 24
Finished Jul 27 05:59:53 PM PDT 24
Peak memory 217768 kb
Host smart-7bbee0b0-f305-419d-bb6b-349a5be13876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89437138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.89437138
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3083455369
Short name T505
Test name
Test status
Simulation time 244776565 ps
CPU time 1.05 seconds
Started Jul 27 05:59:57 PM PDT 24
Finished Jul 27 05:59:58 PM PDT 24
Peak memory 217440 kb
Host smart-6c721c9c-edb2-46e4-ba0f-02fe76a5059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083455369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3083455369
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.24988137
Short name T530
Test name
Test status
Simulation time 149195939 ps
CPU time 0.83 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 199936 kb
Host smart-b7a563a9-8a32-41aa-b673-dc297db56e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24988137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.24988137
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2365444596
Short name T4
Test name
Test status
Simulation time 930080095 ps
CPU time 4.49 seconds
Started Jul 27 05:59:42 PM PDT 24
Finished Jul 27 05:59:47 PM PDT 24
Peak memory 200248 kb
Host smart-31de2d9a-de7f-4591-9ebb-84e2a89b012e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365444596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2365444596
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1949297946
Short name T11
Test name
Test status
Simulation time 144665676 ps
CPU time 1.09 seconds
Started Jul 27 06:00:00 PM PDT 24
Finished Jul 27 06:00:02 PM PDT 24
Peak memory 200044 kb
Host smart-ef089e58-b616-437d-940f-d3c2be0c69b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949297946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1949297946
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.4158026690
Short name T351
Test name
Test status
Simulation time 202072914 ps
CPU time 1.36 seconds
Started Jul 27 05:59:49 PM PDT 24
Finished Jul 27 05:59:50 PM PDT 24
Peak memory 200200 kb
Host smart-35274ce8-3ed1-420f-9f85-00adfccb3baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158026690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.4158026690
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.201557267
Short name T535
Test name
Test status
Simulation time 11109951580 ps
CPU time 40.55 seconds
Started Jul 27 05:59:41 PM PDT 24
Finished Jul 27 06:00:22 PM PDT 24
Peak memory 216860 kb
Host smart-23a301fd-78ad-46c3-8acc-d2eaa3bb34ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201557267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.201557267
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2724903566
Short name T185
Test name
Test status
Simulation time 274207937 ps
CPU time 1.87 seconds
Started Jul 27 05:59:43 PM PDT 24
Finished Jul 27 05:59:45 PM PDT 24
Peak memory 200120 kb
Host smart-b1f1009e-e827-4810-9ea1-22b5c1f61cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724903566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2724903566
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3679015908
Short name T339
Test name
Test status
Simulation time 161161637 ps
CPU time 1.27 seconds
Started Jul 27 05:59:43 PM PDT 24
Finished Jul 27 05:59:44 PM PDT 24
Peak memory 200344 kb
Host smart-3a66c516-d33b-4032-862e-ec85f6d17d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679015908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3679015908
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.27034716
Short name T158
Test name
Test status
Simulation time 80575676 ps
CPU time 0.81 seconds
Started Jul 27 05:58:37 PM PDT 24
Finished Jul 27 05:58:38 PM PDT 24
Peak memory 199956 kb
Host smart-7190cb39-74ac-4311-b627-1a28597dd0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27034716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.27034716
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1713709780
Short name T52
Test name
Test status
Simulation time 2180136130 ps
CPU time 7.81 seconds
Started Jul 27 05:58:38 PM PDT 24
Finished Jul 27 05:58:46 PM PDT 24
Peak memory 221748 kb
Host smart-21b4093f-f6f4-431c-a2ad-1e1f625df32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713709780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1713709780
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2326682184
Short name T367
Test name
Test status
Simulation time 243830338 ps
CPU time 1.03 seconds
Started Jul 27 05:58:44 PM PDT 24
Finished Jul 27 05:58:45 PM PDT 24
Peak memory 217464 kb
Host smart-434aa283-9c58-49d4-af8a-84187c32364f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326682184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2326682184
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.205435224
Short name T415
Test name
Test status
Simulation time 137861026 ps
CPU time 0.8 seconds
Started Jul 27 05:58:35 PM PDT 24
Finished Jul 27 05:58:36 PM PDT 24
Peak memory 199952 kb
Host smart-a385d953-7ee9-4713-91bf-11da18ba4e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205435224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.205435224
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2794976418
Short name T210
Test name
Test status
Simulation time 1326419571 ps
CPU time 5.28 seconds
Started Jul 27 05:58:47 PM PDT 24
Finished Jul 27 05:58:52 PM PDT 24
Peak memory 200264 kb
Host smart-b5e96810-54d7-4e12-a67f-c0132c7f665e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794976418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2794976418
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1040848884
Short name T146
Test name
Test status
Simulation time 99664719 ps
CPU time 0.98 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:58:57 PM PDT 24
Peak memory 200120 kb
Host smart-547e1da8-f730-46e1-bb68-37618d8ca519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040848884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1040848884
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3124349856
Short name T500
Test name
Test status
Simulation time 122824537 ps
CPU time 1.22 seconds
Started Jul 27 05:58:57 PM PDT 24
Finished Jul 27 05:58:58 PM PDT 24
Peak memory 200272 kb
Host smart-cf1ad320-6a6b-4c05-9ff7-095d4e7e915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124349856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3124349856
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.560506536
Short name T542
Test name
Test status
Simulation time 91359625 ps
CPU time 0.92 seconds
Started Jul 27 05:58:44 PM PDT 24
Finished Jul 27 05:58:45 PM PDT 24
Peak memory 199944 kb
Host smart-f091746e-494f-4852-8e35-c5cc58937587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560506536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.560506536
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.4049759580
Short name T9
Test name
Test status
Simulation time 432702591 ps
CPU time 2.31 seconds
Started Jul 27 05:58:35 PM PDT 24
Finished Jul 27 05:58:38 PM PDT 24
Peak memory 208336 kb
Host smart-44e02184-5973-4847-8554-084aa37e6191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049759580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.4049759580
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.4025096547
Short name T229
Test name
Test status
Simulation time 165858631 ps
CPU time 1.1 seconds
Started Jul 27 05:58:36 PM PDT 24
Finished Jul 27 05:58:37 PM PDT 24
Peak memory 200088 kb
Host smart-0878702e-33ec-4852-a9a2-03c327cdd42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025096547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.4025096547
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2158305933
Short name T295
Test name
Test status
Simulation time 57898057 ps
CPU time 0.75 seconds
Started Jul 27 05:58:42 PM PDT 24
Finished Jul 27 05:58:43 PM PDT 24
Peak memory 199800 kb
Host smart-b5f7864c-1bbe-42e5-917d-406dc5c672ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158305933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2158305933
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.725357021
Short name T315
Test name
Test status
Simulation time 1222582390 ps
CPU time 5.78 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:58:59 PM PDT 24
Peak memory 217832 kb
Host smart-3bbbb427-d233-48c9-a6c5-ca2c3c070231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725357021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.725357021
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1076421702
Short name T217
Test name
Test status
Simulation time 248038294 ps
CPU time 1.03 seconds
Started Jul 27 05:58:55 PM PDT 24
Finished Jul 27 05:58:56 PM PDT 24
Peak memory 217172 kb
Host smart-e9bf54a6-4dd3-433e-b529-af310befda1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076421702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1076421702
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3080299573
Short name T385
Test name
Test status
Simulation time 97564891 ps
CPU time 0.82 seconds
Started Jul 27 05:58:53 PM PDT 24
Finished Jul 27 05:58:54 PM PDT 24
Peak memory 199868 kb
Host smart-6e3c8501-9777-4c94-9973-4544373a2c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080299573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3080299573
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2857287672
Short name T30
Test name
Test status
Simulation time 796995535 ps
CPU time 4.33 seconds
Started Jul 27 05:58:51 PM PDT 24
Finished Jul 27 05:58:55 PM PDT 24
Peak memory 200432 kb
Host smart-640bfbe1-2320-403e-a408-eb32c38394e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857287672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2857287672
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2003345233
Short name T188
Test name
Test status
Simulation time 109663217 ps
CPU time 1.08 seconds
Started Jul 27 05:58:37 PM PDT 24
Finished Jul 27 05:58:39 PM PDT 24
Peak memory 200068 kb
Host smart-e958e7da-1c85-420b-a2f3-2b9602c95598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003345233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2003345233
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1409547289
Short name T376
Test name
Test status
Simulation time 198448990 ps
CPU time 1.35 seconds
Started Jul 27 05:59:02 PM PDT 24
Finished Jul 27 05:59:03 PM PDT 24
Peak memory 200300 kb
Host smart-0080eee6-5438-4625-9e72-9eb52d44d634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409547289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1409547289
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2566826960
Short name T172
Test name
Test status
Simulation time 973418661 ps
CPU time 4.61 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:58:51 PM PDT 24
Peak memory 200316 kb
Host smart-5285e3ab-8adb-4475-99eb-8431b1ac6c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566826960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2566826960
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1924332970
Short name T335
Test name
Test status
Simulation time 119157498 ps
CPU time 1.54 seconds
Started Jul 27 05:58:35 PM PDT 24
Finished Jul 27 05:58:36 PM PDT 24
Peak memory 200132 kb
Host smart-deb09d09-26f3-4eca-84c7-7f13638442e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924332970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1924332970
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1657267667
Short name T150
Test name
Test status
Simulation time 145871167 ps
CPU time 1.21 seconds
Started Jul 27 05:58:38 PM PDT 24
Finished Jul 27 05:58:39 PM PDT 24
Peak memory 200128 kb
Host smart-e5ee8e39-db07-45a4-920f-d00d37357f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657267667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1657267667
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2502562146
Short name T440
Test name
Test status
Simulation time 54661331 ps
CPU time 0.71 seconds
Started Jul 27 05:58:49 PM PDT 24
Finished Jul 27 05:58:49 PM PDT 24
Peak memory 200004 kb
Host smart-6504b134-8f8f-4896-bd17-3db46b491789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502562146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2502562146
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3149594227
Short name T55
Test name
Test status
Simulation time 1230169178 ps
CPU time 5.36 seconds
Started Jul 27 05:58:38 PM PDT 24
Finished Jul 27 05:58:44 PM PDT 24
Peak memory 220828 kb
Host smart-e3aca014-d4ae-4678-80d5-64d6285bfd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149594227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3149594227
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3501467708
Short name T206
Test name
Test status
Simulation time 249153770 ps
CPU time 1.03 seconds
Started Jul 27 05:58:37 PM PDT 24
Finished Jul 27 05:58:38 PM PDT 24
Peak memory 217500 kb
Host smart-b675ae65-cf35-440b-bc28-0b27a097ebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501467708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3501467708
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3707157698
Short name T489
Test name
Test status
Simulation time 214200032 ps
CPU time 0.9 seconds
Started Jul 27 05:58:39 PM PDT 24
Finished Jul 27 05:58:40 PM PDT 24
Peak memory 199944 kb
Host smart-c92d4b6f-3b5a-4486-98d2-5bb7dce88408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707157698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3707157698
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3681591004
Short name T311
Test name
Test status
Simulation time 1654337194 ps
CPU time 6.26 seconds
Started Jul 27 05:58:37 PM PDT 24
Finished Jul 27 05:58:44 PM PDT 24
Peak memory 200648 kb
Host smart-4b63c48a-64bd-410d-9581-3890c0e4d4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681591004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3681591004
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3544639736
Short name T288
Test name
Test status
Simulation time 148784981 ps
CPU time 1.13 seconds
Started Jul 27 05:58:51 PM PDT 24
Finished Jul 27 05:58:53 PM PDT 24
Peak memory 200068 kb
Host smart-871f33b2-fdf7-4e38-a776-d27aca990305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544639736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3544639736
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4078634414
Short name T517
Test name
Test status
Simulation time 250164266 ps
CPU time 1.6 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:58:48 PM PDT 24
Peak memory 200204 kb
Host smart-d7fba148-79c6-4331-8446-6a0889fef326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078634414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4078634414
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.771369171
Short name T397
Test name
Test status
Simulation time 155066244 ps
CPU time 1.9 seconds
Started Jul 27 05:58:45 PM PDT 24
Finished Jul 27 05:58:47 PM PDT 24
Peak memory 200112 kb
Host smart-b8222a13-dbb6-49a5-aab2-0699d082406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771369171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.771369171
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.638495679
Short name T534
Test name
Test status
Simulation time 193708385 ps
CPU time 1.2 seconds
Started Jul 27 05:58:37 PM PDT 24
Finished Jul 27 05:58:38 PM PDT 24
Peak memory 200148 kb
Host smart-b0515e7e-b75f-4f40-a3ee-da7a006addb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638495679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.638495679
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3527042683
Short name T279
Test name
Test status
Simulation time 80706262 ps
CPU time 0.8 seconds
Started Jul 27 05:58:33 PM PDT 24
Finished Jul 27 05:58:34 PM PDT 24
Peak memory 199908 kb
Host smart-96cf2a70-e2a0-40d0-95fd-79e86bd9bc8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527042683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3527042683
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2057859941
Short name T444
Test name
Test status
Simulation time 1241033125 ps
CPU time 5.78 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:58:52 PM PDT 24
Peak memory 217784 kb
Host smart-4fe341a8-1ac5-45f0-8edc-8ecdd95fd42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057859941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2057859941
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1281158036
Short name T303
Test name
Test status
Simulation time 244746635 ps
CPU time 1.09 seconds
Started Jul 27 05:58:39 PM PDT 24
Finished Jul 27 05:58:40 PM PDT 24
Peak memory 217472 kb
Host smart-71de8b31-53d8-43b7-b4f8-2c9db2f09c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281158036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1281158036
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2413862566
Short name T329
Test name
Test status
Simulation time 84495400 ps
CPU time 0.76 seconds
Started Jul 27 05:58:35 PM PDT 24
Finished Jul 27 05:58:36 PM PDT 24
Peak memory 199948 kb
Host smart-dcee108b-3704-47c0-9edb-910da2e63ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413862566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2413862566
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2412112569
Short name T137
Test name
Test status
Simulation time 1267954299 ps
CPU time 5.07 seconds
Started Jul 27 05:58:49 PM PDT 24
Finished Jul 27 05:58:54 PM PDT 24
Peak memory 200516 kb
Host smart-7f6fdb68-1886-4ea3-971f-383f0202758c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412112569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2412112569
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.501620665
Short name T481
Test name
Test status
Simulation time 157911592 ps
CPU time 1.13 seconds
Started Jul 27 05:58:51 PM PDT 24
Finished Jul 27 05:58:52 PM PDT 24
Peak memory 200076 kb
Host smart-21a696b3-501b-43ba-b300-edb4bb75d7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501620665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.501620665
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3073647976
Short name T241
Test name
Test status
Simulation time 120776880 ps
CPU time 1.2 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:58:48 PM PDT 24
Peak memory 200328 kb
Host smart-c9e48637-41ad-401f-a1f3-8202a0ac8bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073647976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3073647976
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4090518809
Short name T249
Test name
Test status
Simulation time 8713051570 ps
CPU time 31.91 seconds
Started Jul 27 05:58:45 PM PDT 24
Finished Jul 27 05:59:17 PM PDT 24
Peak memory 208640 kb
Host smart-4034dd99-69ea-4f01-bf11-807313218441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090518809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4090518809
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1122798610
Short name T62
Test name
Test status
Simulation time 278499840 ps
CPU time 1.9 seconds
Started Jul 27 05:58:36 PM PDT 24
Finished Jul 27 05:58:38 PM PDT 24
Peak memory 200140 kb
Host smart-70267de0-88ca-4dc7-9c03-7d24fe34ddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122798610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1122798610
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3933077253
Short name T194
Test name
Test status
Simulation time 80660179 ps
CPU time 0.92 seconds
Started Jul 27 05:58:36 PM PDT 24
Finished Jul 27 05:58:37 PM PDT 24
Peak memory 200040 kb
Host smart-9ee2ade2-6fa4-48b8-8d88-ca034385799a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933077253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3933077253
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1135209879
Short name T464
Test name
Test status
Simulation time 72197773 ps
CPU time 0.77 seconds
Started Jul 27 05:58:56 PM PDT 24
Finished Jul 27 05:58:57 PM PDT 24
Peak memory 199840 kb
Host smart-4daa32a9-6a2a-41c3-aa14-d3cdad0c7550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135209879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1135209879
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4171858083
Short name T36
Test name
Test status
Simulation time 1218466766 ps
CPU time 5.53 seconds
Started Jul 27 05:58:48 PM PDT 24
Finished Jul 27 05:58:53 PM PDT 24
Peak memory 217372 kb
Host smart-e2a88230-78da-4504-a26b-c3f425a778c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171858083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4171858083
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.389147896
Short name T358
Test name
Test status
Simulation time 244321696 ps
CPU time 1.1 seconds
Started Jul 27 05:58:36 PM PDT 24
Finished Jul 27 05:58:37 PM PDT 24
Peak memory 217744 kb
Host smart-e5de084a-8ef1-4bc7-a13a-458d87a443eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389147896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.389147896
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1256754100
Short name T477
Test name
Test status
Simulation time 147781571 ps
CPU time 0.89 seconds
Started Jul 27 05:58:50 PM PDT 24
Finished Jul 27 05:58:51 PM PDT 24
Peak memory 199868 kb
Host smart-680f4d15-ff1f-4f07-8924-82e96bd1e830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256754100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1256754100
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2576972605
Short name T13
Test name
Test status
Simulation time 968949445 ps
CPU time 5.27 seconds
Started Jul 27 05:58:36 PM PDT 24
Finished Jul 27 05:58:42 PM PDT 24
Peak memory 200400 kb
Host smart-b35437d4-1241-4fa6-b926-0451e0afd36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576972605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2576972605
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2920417504
Short name T180
Test name
Test status
Simulation time 104707552 ps
CPU time 1.04 seconds
Started Jul 27 05:58:59 PM PDT 24
Finished Jul 27 05:59:00 PM PDT 24
Peak memory 200080 kb
Host smart-c20ebc8a-c9ba-4d68-9ff4-c2d5dcb0b831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920417504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2920417504
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3032165832
Short name T262
Test name
Test status
Simulation time 126332126 ps
CPU time 1.29 seconds
Started Jul 27 05:58:37 PM PDT 24
Finished Jul 27 05:58:39 PM PDT 24
Peak memory 200276 kb
Host smart-ae778f7a-0490-4e3c-87be-8dfcb8a936c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032165832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3032165832
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1228861381
Short name T374
Test name
Test status
Simulation time 4679607964 ps
CPU time 16.69 seconds
Started Jul 27 05:58:51 PM PDT 24
Finished Jul 27 05:59:08 PM PDT 24
Peak memory 208736 kb
Host smart-c4558042-782e-47a9-a64a-27457d03242e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228861381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1228861381
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1571002375
Short name T179
Test name
Test status
Simulation time 315953866 ps
CPU time 2.32 seconds
Started Jul 27 05:58:44 PM PDT 24
Finished Jul 27 05:58:47 PM PDT 24
Peak memory 200108 kb
Host smart-99344abf-76bd-4c7e-b75e-a031b7a2abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571002375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1571002375
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2717883817
Short name T82
Test name
Test status
Simulation time 234334039 ps
CPU time 1.47 seconds
Started Jul 27 05:58:46 PM PDT 24
Finished Jul 27 05:58:47 PM PDT 24
Peak memory 200004 kb
Host smart-565916db-10da-4b3e-bff5-e1695ac85e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717883817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2717883817
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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