Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8970

1

T2

14

T5

19

T6

18

auto[1]

11661

1

T1

4

T2

1

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6292	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6946	1			T1	2		T2	1		T3	1
reset_info_cp[2]	3158	1			T1	1		T4	1		T8	1
reset_info_cp[4]	4268	1			T1	1		T4	1		T8	1
reset_info_cp[8]	126	1			T2	1		T5	2		T20	1
reset_info_cp[16]	122	1			T2	2		T5	1		T6	1
reset_info_cp[32]	115	1			T6	1		T96	3		T135	1
reset_info_cp[64]	118	1			T5	1		T6	3		T12	1
reset_info_cp[128]	106	1			T1	1		T2	1		T5	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3381	1			T20	14		T21	6		T90	12
reset_info_cp[1]	auto[1]	2945	1			T1	1		T4	1		T8	1
reset_info_cp[2]	auto[0]	1046	1			T20	2		T21	6		T90	3
reset_info_cp[2]	auto[1]	2112	1			T1	1		T4	1		T8	1
reset_info_cp[4]	auto[0]	1616	1			T20	9		T21	8		T90	5
reset_info_cp[4]	auto[1]	2652	1			T1	1		T4	1		T8	1
reset_info_cp[8]	auto[0]	61	1			T2	1		T5	2		T20	1
reset_info_cp[8]	auto[1]	65	1			T108	1		T111	2		T26	1
reset_info_cp[16]	auto[0]	46	1			T2	2		T5	1		T6	1
reset_info_cp[16]	auto[1]	76	1			T23	1		T96	2		T130	1
reset_info_cp[32]	auto[0]	44	1			T6	1		T96	1		T135	1
reset_info_cp[32]	auto[1]	71	1			T96	2		T136	1		T40	1
reset_info_cp[64]	auto[0]	51	1			T5	1		T6	3		T12	1
reset_info_cp[64]	auto[1]	67	1			T20	1		T23	1		T36	1
reset_info_cp[128]	auto[0]	46	1			T2	1		T5	1		T6	1
reset_info_cp[128]	auto[1]	60	1			T1	1		T6	1		T90	1