Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T533 /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.670022731 Jul 28 05:17:32 PM PDT 24 Jul 28 05:17:33 PM PDT 24 243691382 ps
T534 /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.144931033 Jul 28 05:17:35 PM PDT 24 Jul 28 05:17:41 PM PDT 24 1229332383 ps
T535 /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2857963155 Jul 28 05:16:56 PM PDT 24 Jul 28 05:16:57 PM PDT 24 160444160 ps
T536 /workspace/coverage/default/2.rstmgr_alert_test.948245008 Jul 28 05:16:25 PM PDT 24 Jul 28 05:16:26 PM PDT 24 56609403 ps
T537 /workspace/coverage/default/33.rstmgr_alert_test.2248378696 Jul 28 05:17:13 PM PDT 24 Jul 28 05:17:13 PM PDT 24 79654976 ps
T64 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.350212337 Jul 28 05:17:43 PM PDT 24 Jul 28 05:17:44 PM PDT 24 101829163 ps
T65 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4201423617 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:53 PM PDT 24 116817813 ps
T66 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1753891522 Jul 28 05:17:48 PM PDT 24 Jul 28 05:17:49 PM PDT 24 151450004 ps
T71 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.731985991 Jul 28 05:17:48 PM PDT 24 Jul 28 05:17:50 PM PDT 24 137122138 ps
T67 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3943544151 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:54 PM PDT 24 425154473 ps
T69 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.892049523 Jul 28 05:17:41 PM PDT 24 Jul 28 05:17:47 PM PDT 24 53733468 ps
T68 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3547973478 Jul 28 05:17:47 PM PDT 24 Jul 28 05:17:49 PM PDT 24 172322348 ps
T123 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1100473995 Jul 28 05:17:56 PM PDT 24 Jul 28 05:17:57 PM PDT 24 74148232 ps
T100 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.369525850 Jul 28 05:17:42 PM PDT 24 Jul 28 05:17:44 PM PDT 24 471734480 ps
T72 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.697039256 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:56 PM PDT 24 939704404 ps
T538 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.545173185 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:59 PM PDT 24 492575196 ps
T539 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2307802304 Jul 28 05:17:55 PM PDT 24 Jul 28 05:17:56 PM PDT 24 90701649 ps
T115 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4060920526 Jul 28 05:17:54 PM PDT 24 Jul 28 05:17:56 PM PDT 24 237495858 ps
T101 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1765104855 Jul 28 05:17:47 PM PDT 24 Jul 28 05:17:50 PM PDT 24 369500362 ps
T73 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2019640583 Jul 28 05:17:38 PM PDT 24 Jul 28 05:17:42 PM PDT 24 487946173 ps
T102 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4090617581 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:53 PM PDT 24 196750243 ps
T103 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.222489709 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:55 PM PDT 24 202373763 ps
T540 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1920411730 Jul 28 05:17:42 PM PDT 24 Jul 28 05:17:43 PM PDT 24 88870943 ps
T104 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3902753327 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:57 PM PDT 24 921541324 ps
T541 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.384439452 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:53 PM PDT 24 146987504 ps
T105 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2893165509 Jul 28 05:17:43 PM PDT 24 Jul 28 05:17:47 PM PDT 24 934701871 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3268499522 Jul 28 05:17:35 PM PDT 24 Jul 28 05:17:38 PM PDT 24 350915806 ps
T116 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2542957481 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:54 PM PDT 24 67830762 ps
T127 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4088753580 Jul 28 05:17:57 PM PDT 24 Jul 28 05:17:59 PM PDT 24 460529687 ps
T106 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.389365206 Jul 28 05:18:01 PM PDT 24 Jul 28 05:18:03 PM PDT 24 201662747 ps
T117 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3958924013 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:53 PM PDT 24 86446736 ps
T118 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.637128934 Jul 28 05:17:46 PM PDT 24 Jul 28 05:17:48 PM PDT 24 127576533 ps
T119 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.639863124 Jul 28 05:17:38 PM PDT 24 Jul 28 05:17:39 PM PDT 24 126783119 ps
T543 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.190050460 Jul 28 05:18:11 PM PDT 24 Jul 28 05:18:12 PM PDT 24 62855217 ps
T126 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4004053341 Jul 28 05:18:00 PM PDT 24 Jul 28 05:18:02 PM PDT 24 435483543 ps
T120 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.229117662 Jul 28 05:18:05 PM PDT 24 Jul 28 05:18:07 PM PDT 24 238407558 ps
T544 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2347046286 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:55 PM PDT 24 432580450 ps
T121 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3214291336 Jul 28 05:18:02 PM PDT 24 Jul 28 05:18:03 PM PDT 24 126734823 ps
T545 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.299981697 Jul 28 05:17:50 PM PDT 24 Jul 28 05:17:53 PM PDT 24 825153859 ps
T546 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.379441161 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:53 PM PDT 24 171618294 ps
T547 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3677891254 Jul 28 05:17:47 PM PDT 24 Jul 28 05:17:50 PM PDT 24 920415620 ps
T122 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1335919431 Jul 28 05:18:09 PM PDT 24 Jul 28 05:18:11 PM PDT 24 262741363 ps
T548 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1163180861 Jul 28 05:17:46 PM PDT 24 Jul 28 05:17:48 PM PDT 24 216284575 ps
T549 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1137309492 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:54 PM PDT 24 466501418 ps
T550 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2779067629 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:53 PM PDT 24 184826100 ps
T551 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1397045979 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:56 PM PDT 24 480995967 ps
T552 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1307950767 Jul 28 05:18:16 PM PDT 24 Jul 28 05:18:17 PM PDT 24 131328516 ps
T553 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2911021798 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:53 PM PDT 24 126414785 ps
T554 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4010758526 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:52 PM PDT 24 93034326 ps
T555 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4060410409 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:53 PM PDT 24 195567228 ps
T556 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2107118156 Jul 28 05:17:57 PM PDT 24 Jul 28 05:17:58 PM PDT 24 134657978 ps
T557 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2940020839 Jul 28 05:18:01 PM PDT 24 Jul 28 05:18:03 PM PDT 24 272659317 ps
T558 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.537618669 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:02 PM PDT 24 466241150 ps
T559 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3426886852 Jul 28 05:17:44 PM PDT 24 Jul 28 05:17:46 PM PDT 24 158833193 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.178966844 Jul 28 05:17:55 PM PDT 24 Jul 28 05:17:57 PM PDT 24 142396952 ps
T561 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3924083851 Jul 28 05:17:39 PM PDT 24 Jul 28 05:17:44 PM PDT 24 1169336993 ps
T562 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2523073489 Jul 28 05:17:50 PM PDT 24 Jul 28 05:17:52 PM PDT 24 222989280 ps
T563 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1200116758 Jul 28 05:18:01 PM PDT 24 Jul 28 05:18:02 PM PDT 24 138945393 ps
T564 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3267303626 Jul 28 05:18:12 PM PDT 24 Jul 28 05:18:13 PM PDT 24 65938341 ps
T565 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2271683274 Jul 28 05:17:57 PM PDT 24 Jul 28 05:17:59 PM PDT 24 150455229 ps
T132 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1945165827 Jul 28 05:18:00 PM PDT 24 Jul 28 05:18:02 PM PDT 24 502871941 ps
T566 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1842131342 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:53 PM PDT 24 261911194 ps
T567 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1472231211 Jul 28 05:18:11 PM PDT 24 Jul 28 05:18:13 PM PDT 24 147902689 ps
T568 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.418344735 Jul 28 05:17:58 PM PDT 24 Jul 28 05:18:00 PM PDT 24 473501148 ps
T569 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1697675803 Jul 28 05:17:46 PM PDT 24 Jul 28 05:17:48 PM PDT 24 164867134 ps
T570 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1043192786 Jul 28 05:17:39 PM PDT 24 Jul 28 05:17:40 PM PDT 24 71608414 ps
T571 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2878515715 Jul 28 05:17:45 PM PDT 24 Jul 28 05:17:46 PM PDT 24 81358181 ps
T133 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1334262758 Jul 28 05:17:50 PM PDT 24 Jul 28 05:17:52 PM PDT 24 495781979 ps
T572 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3682725884 Jul 28 05:17:48 PM PDT 24 Jul 28 05:17:49 PM PDT 24 172982460 ps
T134 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.290392870 Jul 28 05:18:09 PM PDT 24 Jul 28 05:18:12 PM PDT 24 865997617 ps
T573 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.336305801 Jul 28 05:17:41 PM PDT 24 Jul 28 05:17:42 PM PDT 24 145865504 ps
T574 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.317766879 Jul 28 05:18:04 PM PDT 24 Jul 28 05:18:06 PM PDT 24 231940547 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.892346882 Jul 28 05:17:50 PM PDT 24 Jul 28 05:17:58 PM PDT 24 1534666147 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1543999381 Jul 28 05:17:36 PM PDT 24 Jul 28 05:17:37 PM PDT 24 93325838 ps
T577 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.285088765 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:55 PM PDT 24 175236223 ps
T578 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2435634734 Jul 28 05:18:03 PM PDT 24 Jul 28 05:18:04 PM PDT 24 56034232 ps
T579 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.228086480 Jul 28 05:17:36 PM PDT 24 Jul 28 05:17:42 PM PDT 24 86946188 ps
T580 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2404051382 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:52 PM PDT 24 154445874 ps
T581 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2594370216 Jul 28 05:18:03 PM PDT 24 Jul 28 05:18:04 PM PDT 24 79189247 ps
T582 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2794719048 Jul 28 05:17:37 PM PDT 24 Jul 28 05:17:38 PM PDT 24 62040730 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.476427505 Jul 28 05:17:43 PM PDT 24 Jul 28 05:17:44 PM PDT 24 200652086 ps
T584 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.620610515 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:59 PM PDT 24 154651751 ps
T585 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.578562984 Jul 28 05:17:45 PM PDT 24 Jul 28 05:17:47 PM PDT 24 143790971 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2730964776 Jul 28 05:17:45 PM PDT 24 Jul 28 05:17:46 PM PDT 24 80990548 ps
T587 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.862281820 Jul 28 05:17:57 PM PDT 24 Jul 28 05:17:58 PM PDT 24 64041151 ps
T588 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3720001411 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:01 PM PDT 24 183191541 ps
T589 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4158876641 Jul 28 05:17:32 PM PDT 24 Jul 28 05:17:33 PM PDT 24 108705238 ps
T590 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1685601165 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:54 PM PDT 24 203398057 ps
T591 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3753765976 Jul 28 05:17:54 PM PDT 24 Jul 28 05:17:56 PM PDT 24 136272703 ps
T592 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1166487060 Jul 28 05:18:02 PM PDT 24 Jul 28 05:18:04 PM PDT 24 478293913 ps
T593 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.355431703 Jul 28 05:17:48 PM PDT 24 Jul 28 05:17:50 PM PDT 24 264583092 ps
T594 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.699164446 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:54 PM PDT 24 69706474 ps
T595 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3217213795 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:54 PM PDT 24 222026365 ps
T596 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1730588636 Jul 28 05:17:50 PM PDT 24 Jul 28 05:17:52 PM PDT 24 355902809 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.868608095 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:55 PM PDT 24 269203867 ps
T598 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1976664699 Jul 28 05:17:55 PM PDT 24 Jul 28 05:18:01 PM PDT 24 217498557 ps
T599 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3550238029 Jul 28 05:17:47 PM PDT 24 Jul 28 05:17:53 PM PDT 24 79071126 ps
T600 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1861932803 Jul 28 05:17:58 PM PDT 24 Jul 28 05:18:04 PM PDT 24 221784747 ps
T601 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4256118728 Jul 28 05:17:47 PM PDT 24 Jul 28 05:17:49 PM PDT 24 123583366 ps
T602 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3023051636 Jul 28 05:17:36 PM PDT 24 Jul 28 05:17:40 PM PDT 24 619787262 ps
T603 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3563558753 Jul 28 05:17:49 PM PDT 24 Jul 28 05:17:51 PM PDT 24 168819858 ps
T604 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3195707969 Jul 28 05:17:42 PM PDT 24 Jul 28 05:17:43 PM PDT 24 87247970 ps
T605 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1556310202 Jul 28 05:17:43 PM PDT 24 Jul 28 05:17:44 PM PDT 24 86825668 ps
T606 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2030185918 Jul 28 05:17:43 PM PDT 24 Jul 28 05:17:45 PM PDT 24 467918309 ps
T607 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2430599970 Jul 28 05:17:50 PM PDT 24 Jul 28 05:17:52 PM PDT 24 270910689 ps
T608 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.368591596 Jul 28 05:17:54 PM PDT 24 Jul 28 05:17:57 PM PDT 24 916209656 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1143876229 Jul 28 05:17:43 PM PDT 24 Jul 28 05:17:45 PM PDT 24 132149498 ps
T610 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1858368646 Jul 28 05:18:04 PM PDT 24 Jul 28 05:18:05 PM PDT 24 81412973 ps
T611 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2899681289 Jul 28 05:17:49 PM PDT 24 Jul 28 05:17:55 PM PDT 24 1177047652 ps
T612 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3155090047 Jul 28 05:17:49 PM PDT 24 Jul 28 05:17:51 PM PDT 24 190539930 ps
T613 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1894970733 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:53 PM PDT 24 62574388 ps
T614 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2887125231 Jul 28 05:17:44 PM PDT 24 Jul 28 05:17:46 PM PDT 24 110367688 ps
T615 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2912009417 Jul 28 05:18:01 PM PDT 24 Jul 28 05:18:02 PM PDT 24 79071714 ps
T616 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1292055409 Jul 28 05:17:57 PM PDT 24 Jul 28 05:17:57 PM PDT 24 80203049 ps
T124 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.925210127 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:54 PM PDT 24 495403342 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1862161913 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:54 PM PDT 24 187908708 ps
T618 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.800139048 Jul 28 05:17:49 PM PDT 24 Jul 28 05:17:52 PM PDT 24 833294404 ps
T619 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1083863816 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:55 PM PDT 24 266649046 ps
T125 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.723862694 Jul 28 05:18:02 PM PDT 24 Jul 28 05:18:05 PM PDT 24 799873429 ps
T620 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2157080230 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:59 PM PDT 24 152110112 ps

Test location /workspace/coverage/default/1.rstmgr_smoke.3650961602
Short name T8
Test name
Test status
Simulation time 123108330 ps
CPU time 1.18 seconds
Started Jul 28 05:16:38 PM PDT 24
Finished Jul 28 05:16:40 PM PDT 24
Peak memory 200280 kb
Host smart-34749deb-a636-425c-92b6-99a233705c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650961602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3650961602
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.333705363
Short name T62
Test name
Test status
Simulation time 126314241 ps
CPU time 1.54 seconds
Started Jul 28 05:17:09 PM PDT 24
Finished Jul 28 05:17:11 PM PDT 24
Peak memory 208200 kb
Host smart-c94ae6f5-57c2-4e57-be07-59ae470bb506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333705363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.333705363
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3315417826
Short name T6
Test name
Test status
Simulation time 168038820 ps
CPU time 1.37 seconds
Started Jul 28 05:17:20 PM PDT 24
Finished Jul 28 05:17:21 PM PDT 24
Peak memory 200528 kb
Host smart-f74a01df-d9cb-46c6-9fc5-99f6401026e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315417826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3315417826
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3547973478
Short name T68
Test name
Test status
Simulation time 172322348 ps
CPU time 1.67 seconds
Started Jul 28 05:17:47 PM PDT 24
Finished Jul 28 05:17:49 PM PDT 24
Peak memory 208344 kb
Host smart-508c6f31-9a07-4ce3-901a-a965961369dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547973478 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3547973478
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1867596695
Short name T36
Test name
Test status
Simulation time 11370249012 ps
CPU time 35.22 seconds
Started Jul 28 05:17:13 PM PDT 24
Finished Jul 28 05:17:48 PM PDT 24
Peak memory 208852 kb
Host smart-15d73b26-bdf8-45d8-8ab7-46b603bca687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867596695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1867596695
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.4032021398
Short name T75
Test name
Test status
Simulation time 8290387151 ps
CPU time 13.85 seconds
Started Jul 28 05:16:44 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 217244 kb
Host smart-4f571724-9ebe-453f-9502-2e46b88f5b53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032021398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.4032021398
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3734289813
Short name T23
Test name
Test status
Simulation time 1237247659 ps
CPU time 5.79 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:13 PM PDT 24
Peak memory 221680 kb
Host smart-bb6d7c9b-db98-440f-b23e-1dbfb29a0c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734289813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3734289813
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3902753327
Short name T104
Test name
Test status
Simulation time 921541324 ps
CPU time 3.23 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:57 PM PDT 24
Peak memory 200004 kb
Host smart-b87da672-2872-48d6-baf4-a5958cabd78f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902753327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3902753327
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.777205408
Short name T111
Test name
Test status
Simulation time 8527274710 ps
CPU time 39.66 seconds
Started Jul 28 05:16:48 PM PDT 24
Finished Jul 28 05:17:27 PM PDT 24
Peak memory 200328 kb
Host smart-7abe994b-6262-4f34-8280-2d7a2ac0ec7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777205408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.777205408
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3650849510
Short name T79
Test name
Test status
Simulation time 82032531 ps
CPU time 0.85 seconds
Started Jul 28 05:16:37 PM PDT 24
Finished Jul 28 05:16:38 PM PDT 24
Peak memory 199876 kb
Host smart-4a18becd-cb23-433d-98ac-39475b1385ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650849510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3650849510
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1807988316
Short name T142
Test name
Test status
Simulation time 99704738 ps
CPU time 0.96 seconds
Started Jul 28 05:16:55 PM PDT 24
Finished Jul 28 05:16:56 PM PDT 24
Peak memory 200024 kb
Host smart-72271265-34de-4ec5-a264-bfbbb860f99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807988316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1807988316
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4090617581
Short name T102
Test name
Test status
Simulation time 196750243 ps
CPU time 2.05 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 208220 kb
Host smart-6ed43f8b-db28-44eb-9f79-d5c3b34231eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090617581 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4090617581
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1773495164
Short name T42
Test name
Test status
Simulation time 1900000363 ps
CPU time 6.77 seconds
Started Jul 28 05:17:34 PM PDT 24
Finished Jul 28 05:17:41 PM PDT 24
Peak memory 217728 kb
Host smart-1cd4fc0f-01f9-4c86-80ad-79fdc0b8eda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773495164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1773495164
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3915681224
Short name T3
Test name
Test status
Simulation time 97702706 ps
CPU time 0.76 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:08 PM PDT 24
Peak memory 199888 kb
Host smart-b2f1f552-d824-4351-840d-b11980b86b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915681224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3915681224
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2700826774
Short name T31
Test name
Test status
Simulation time 2349014723 ps
CPU time 7.83 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 221792 kb
Host smart-30d7b112-c6c0-4a71-95c6-fc57c36ee5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700826774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2700826774
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.229117662
Short name T120
Test name
Test status
Simulation time 238407558 ps
CPU time 1.55 seconds
Started Jul 28 05:18:05 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 199984 kb
Host smart-48334a0b-82c3-41c0-a099-21bad8d0fde0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229117662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.229117662
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.194007985
Short name T138
Test name
Test status
Simulation time 244916955 ps
CPU time 1.04 seconds
Started Jul 28 05:16:38 PM PDT 24
Finished Jul 28 05:16:39 PM PDT 24
Peak memory 217356 kb
Host smart-a29b6900-7210-4fff-9066-8090b9b34e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194007985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.194007985
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1334262758
Short name T133
Test name
Test status
Simulation time 495781979 ps
CPU time 2.04 seconds
Started Jul 28 05:17:50 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 199980 kb
Host smart-8b55116b-6bb9-4dac-85cc-ed7a257289e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334262758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1334262758
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.723862694
Short name T125
Test name
Test status
Simulation time 799873429 ps
CPU time 2.8 seconds
Started Jul 28 05:18:02 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 199952 kb
Host smart-442276c0-ae4b-4055-b9e2-ed33663d179a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723862694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.723862694
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4088753580
Short name T127
Test name
Test status
Simulation time 460529687 ps
CPU time 1.95 seconds
Started Jul 28 05:17:57 PM PDT 24
Finished Jul 28 05:17:59 PM PDT 24
Peak memory 200056 kb
Host smart-e3aa2305-a187-48a1-ac4d-777dc82524fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088753580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.4088753580
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1163180861
Short name T548
Test name
Test status
Simulation time 216284575 ps
CPU time 1.59 seconds
Started Jul 28 05:17:46 PM PDT 24
Finished Jul 28 05:17:48 PM PDT 24
Peak memory 199852 kb
Host smart-91c313ef-5346-43c7-a4f3-53b3ce34c542
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163180861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
163180861
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2899681289
Short name T611
Test name
Test status
Simulation time 1177047652 ps
CPU time 5.42 seconds
Started Jul 28 05:17:49 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 200160 kb
Host smart-1f8d4b22-2aa4-428e-9e37-450cf2eaf16d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899681289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
899681289
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3195707969
Short name T604
Test name
Test status
Simulation time 87247970 ps
CPU time 0.76 seconds
Started Jul 28 05:17:42 PM PDT 24
Finished Jul 28 05:17:43 PM PDT 24
Peak memory 199724 kb
Host smart-21f04b60-3258-4b40-95d3-1eec6181e5dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195707969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
195707969
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1697675803
Short name T569
Test name
Test status
Simulation time 164867134 ps
CPU time 1.65 seconds
Started Jul 28 05:17:46 PM PDT 24
Finished Jul 28 05:17:48 PM PDT 24
Peak memory 208248 kb
Host smart-a7c3bcdd-48ff-4e4b-b3f6-684ff0e0a2d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697675803 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1697675803
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.228086480
Short name T579
Test name
Test status
Simulation time 86946188 ps
CPU time 0.9 seconds
Started Jul 28 05:17:36 PM PDT 24
Finished Jul 28 05:17:42 PM PDT 24
Peak memory 199768 kb
Host smart-985c17ea-3bc2-429f-bc1c-8ebb267130e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228086480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.228086480
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2730964776
Short name T586
Test name
Test status
Simulation time 80990548 ps
CPU time 1 seconds
Started Jul 28 05:17:45 PM PDT 24
Finished Jul 28 05:17:46 PM PDT 24
Peak memory 199836 kb
Host smart-8db75426-abf8-4bbf-abad-43ee3bed830b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730964776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2730964776
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3023051636
Short name T602
Test name
Test status
Simulation time 619787262 ps
CPU time 3.8 seconds
Started Jul 28 05:17:36 PM PDT 24
Finished Jul 28 05:17:40 PM PDT 24
Peak memory 208048 kb
Host smart-8b0ef0ee-bca9-4250-abb5-9509f094c63d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023051636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3023051636
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.355431703
Short name T593
Test name
Test status
Simulation time 264583092 ps
CPU time 1.75 seconds
Started Jul 28 05:17:48 PM PDT 24
Finished Jul 28 05:17:50 PM PDT 24
Peak memory 199820 kb
Host smart-6668515e-5c63-4179-99e8-cb030f221659
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355431703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.355431703
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.892346882
Short name T575
Test name
Test status
Simulation time 1534666147 ps
CPU time 8.18 seconds
Started Jul 28 05:17:50 PM PDT 24
Finished Jul 28 05:17:58 PM PDT 24
Peak memory 199948 kb
Host smart-dde38918-5ebf-41d9-8cf4-5be0a4bcde4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892346882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.892346882
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1543999381
Short name T576
Test name
Test status
Simulation time 93325838 ps
CPU time 0.81 seconds
Started Jul 28 05:17:36 PM PDT 24
Finished Jul 28 05:17:37 PM PDT 24
Peak memory 199796 kb
Host smart-290e14ca-72a7-4804-8b46-0fb22125bce6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543999381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
543999381
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2911021798
Short name T553
Test name
Test status
Simulation time 126414785 ps
CPU time 0.95 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 199908 kb
Host smart-12a573b0-0c29-4dd3-959f-9fce45caa01c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911021798 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2911021798
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1043192786
Short name T570
Test name
Test status
Simulation time 71608414 ps
CPU time 0.81 seconds
Started Jul 28 05:17:39 PM PDT 24
Finished Jul 28 05:17:40 PM PDT 24
Peak memory 200032 kb
Host smart-d7cef4a7-a36b-48fe-bee7-4502a9380997
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043192786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1043192786
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1976664699
Short name T598
Test name
Test status
Simulation time 217498557 ps
CPU time 1.49 seconds
Started Jul 28 05:17:55 PM PDT 24
Finished Jul 28 05:18:01 PM PDT 24
Peak memory 199960 kb
Host smart-988b5084-20ce-48d5-9f0d-6f2af4721480
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976664699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1976664699
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.178966844
Short name T560
Test name
Test status
Simulation time 142396952 ps
CPU time 1.97 seconds
Started Jul 28 05:17:55 PM PDT 24
Finished Jul 28 05:17:57 PM PDT 24
Peak memory 211344 kb
Host smart-34880f3c-b48a-4826-855a-028802a0467b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178966844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.178966844
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.369525850
Short name T100
Test name
Test status
Simulation time 471734480 ps
CPU time 1.86 seconds
Started Jul 28 05:17:42 PM PDT 24
Finished Jul 28 05:17:44 PM PDT 24
Peak memory 200072 kb
Host smart-900a033d-668f-4db5-a756-10c96991a578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369525850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
369525850
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2779067629
Short name T550
Test name
Test status
Simulation time 184826100 ps
CPU time 1.66 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 212780 kb
Host smart-d9dadc35-5e63-4b77-b6ac-8ca1c1dad23a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779067629 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2779067629
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.190050460
Short name T543
Test name
Test status
Simulation time 62855217 ps
CPU time 0.73 seconds
Started Jul 28 05:18:11 PM PDT 24
Finished Jul 28 05:18:12 PM PDT 24
Peak memory 199788 kb
Host smart-49fa7fad-f365-45ce-8231-cdf662b75e73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190050460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.190050460
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2107118156
Short name T556
Test name
Test status
Simulation time 134657978 ps
CPU time 1.04 seconds
Started Jul 28 05:17:57 PM PDT 24
Finished Jul 28 05:17:58 PM PDT 24
Peak memory 199852 kb
Host smart-eb729f68-42bb-4a58-ac2b-01b503bf4e22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107118156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2107118156
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1397045979
Short name T551
Test name
Test status
Simulation time 480995967 ps
CPU time 3.58 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 208132 kb
Host smart-69378e7f-5150-4c31-8275-26f6873ee51c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397045979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1397045979
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.299981697
Short name T545
Test name
Test status
Simulation time 825153859 ps
CPU time 2.68 seconds
Started Jul 28 05:17:50 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 200064 kb
Host smart-2d1e47c4-f35b-40f7-aca8-1df1fd77d5a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299981697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.299981697
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.862281820
Short name T587
Test name
Test status
Simulation time 64041151 ps
CPU time 0.76 seconds
Started Jul 28 05:17:57 PM PDT 24
Finished Jul 28 05:17:58 PM PDT 24
Peak memory 199840 kb
Host smart-a5047403-e58d-46be-b3ec-958f23922bfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862281820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.862281820
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1730588636
Short name T596
Test name
Test status
Simulation time 355902809 ps
CPU time 2.38 seconds
Started Jul 28 05:17:50 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 211876 kb
Host smart-3a0589a9-e11e-4d72-960a-539144589305
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730588636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1730588636
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1137309492
Short name T549
Test name
Test status
Simulation time 466501418 ps
CPU time 1.86 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 200044 kb
Host smart-57531354-f4a8-43f5-a473-1354690edbfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137309492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1137309492
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1685601165
Short name T590
Test name
Test status
Simulation time 203398057 ps
CPU time 1.31 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 208144 kb
Host smart-fd503fea-6edd-4ba8-88ac-e6d2972ed0fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685601165 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1685601165
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.699164446
Short name T594
Test name
Test status
Simulation time 69706474 ps
CPU time 0.79 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 199732 kb
Host smart-6b37dfa0-a8c0-4c3b-b6dc-9ca03013d01e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699164446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.699164446
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4060920526
Short name T115
Test name
Test status
Simulation time 237495858 ps
CPU time 1.49 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 199936 kb
Host smart-481aac6c-005b-4a3a-92c8-dd4940d94dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060920526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4060920526
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.537618669
Short name T558
Test name
Test status
Simulation time 466241150 ps
CPU time 2.95 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:02 PM PDT 24
Peak memory 208148 kb
Host smart-a77ae8d7-4595-4042-a2a9-55c20839fea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537618669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.537618669
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.800139048
Short name T618
Test name
Test status
Simulation time 833294404 ps
CPU time 2.81 seconds
Started Jul 28 05:17:49 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 200064 kb
Host smart-5da19281-62ba-4b75-88f4-ee37813c87f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800139048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.800139048
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.336305801
Short name T573
Test name
Test status
Simulation time 145865504 ps
CPU time 1.21 seconds
Started Jul 28 05:17:41 PM PDT 24
Finished Jul 28 05:17:42 PM PDT 24
Peak memory 208120 kb
Host smart-4e987d76-dcc9-483a-8dfc-cb9d80d24f8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336305801 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.336305801
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2307802304
Short name T539
Test name
Test status
Simulation time 90701649 ps
CPU time 0.9 seconds
Started Jul 28 05:17:55 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 199828 kb
Host smart-5a281232-c922-4dbd-a85a-2bf72be27aa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307802304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2307802304
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1842131342
Short name T566
Test name
Test status
Simulation time 261911194 ps
CPU time 1.54 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 200008 kb
Host smart-7a385ee2-763b-4dc2-af2a-32155c83d57d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842131342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1842131342
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2430599970
Short name T607
Test name
Test status
Simulation time 270910689 ps
CPU time 1.93 seconds
Started Jul 28 05:17:50 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 208160 kb
Host smart-1e56b5b5-c837-48a5-8d5b-d5363f9b242b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430599970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2430599970
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2030185918
Short name T606
Test name
Test status
Simulation time 467918309 ps
CPU time 1.8 seconds
Started Jul 28 05:17:43 PM PDT 24
Finished Jul 28 05:17:45 PM PDT 24
Peak memory 200056 kb
Host smart-39477c39-342e-46f6-8743-3c9cc7a40a58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030185918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2030185918
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.379441161
Short name T546
Test name
Test status
Simulation time 171618294 ps
CPU time 1.14 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 199912 kb
Host smart-e58bf2a8-09a4-4230-b682-ea3acfc63170
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379441161 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.379441161
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3958924013
Short name T117
Test name
Test status
Simulation time 86446736 ps
CPU time 0.9 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 199756 kb
Host smart-370d346b-ab49-43cb-8258-f8482f69a986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958924013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3958924013
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2157080230
Short name T620
Test name
Test status
Simulation time 152110112 ps
CPU time 1.13 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:59 PM PDT 24
Peak memory 199856 kb
Host smart-9d93048c-db5d-42ef-a1f6-847960b601f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157080230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2157080230
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.620610515
Short name T584
Test name
Test status
Simulation time 154651751 ps
CPU time 2.2 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:59 PM PDT 24
Peak memory 216196 kb
Host smart-9ff055af-9512-4028-a1cf-bb28dee1c380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620610515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.620610515
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3943544151
Short name T67
Test name
Test status
Simulation time 425154473 ps
CPU time 1.93 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 200056 kb
Host smart-d074eb5d-6744-4d2f-9da9-03f6eb05ce2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943544151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3943544151
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4201423617
Short name T65
Test name
Test status
Simulation time 116817813 ps
CPU time 1.2 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 208136 kb
Host smart-dae56a2b-57cd-4491-a411-7a3c57dda98e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201423617 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.4201423617
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3267303626
Short name T564
Test name
Test status
Simulation time 65938341 ps
CPU time 0.77 seconds
Started Jul 28 05:18:12 PM PDT 24
Finished Jul 28 05:18:13 PM PDT 24
Peak memory 199788 kb
Host smart-b8fbb369-51be-4ce5-ac40-98e01bdfdad9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267303626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3267303626
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2404051382
Short name T580
Test name
Test status
Simulation time 154445874 ps
CPU time 1.12 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 199828 kb
Host smart-30b186d7-d465-4d69-9d38-f85fd7ed3c1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404051382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2404051382
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1765104855
Short name T101
Test name
Test status
Simulation time 369500362 ps
CPU time 2.37 seconds
Started Jul 28 05:17:47 PM PDT 24
Finished Jul 28 05:17:50 PM PDT 24
Peak memory 216160 kb
Host smart-beac0e93-0da2-4d5c-b22c-0753670663c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765104855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1765104855
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1166487060
Short name T592
Test name
Test status
Simulation time 478293913 ps
CPU time 1.83 seconds
Started Jul 28 05:18:02 PM PDT 24
Finished Jul 28 05:18:04 PM PDT 24
Peak memory 200068 kb
Host smart-dfc42ec8-720e-4569-a797-c4c2d17ab6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166487060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1166487060
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3720001411
Short name T588
Test name
Test status
Simulation time 183191541 ps
CPU time 1.7 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:01 PM PDT 24
Peak memory 208324 kb
Host smart-a8dfd0c9-df8e-4f7b-aa11-b3379369e2b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720001411 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3720001411
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1894970733
Short name T613
Test name
Test status
Simulation time 62574388 ps
CPU time 0.8 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 199844 kb
Host smart-b8b7a869-e0f6-40a7-842d-2e1a903ae5cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894970733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1894970733
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3214291336
Short name T121
Test name
Test status
Simulation time 126734823 ps
CPU time 1.05 seconds
Started Jul 28 05:18:02 PM PDT 24
Finished Jul 28 05:18:03 PM PDT 24
Peak memory 199860 kb
Host smart-e4a83689-2eb9-4854-aa68-0ce6889e3ea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214291336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3214291336
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.317766879
Short name T574
Test name
Test status
Simulation time 231940547 ps
CPU time 1.69 seconds
Started Jul 28 05:18:04 PM PDT 24
Finished Jul 28 05:18:06 PM PDT 24
Peak memory 199840 kb
Host smart-3383a76f-b890-40c2-a6b0-df78f25b15ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317766879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.317766879
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4004053341
Short name T126
Test name
Test status
Simulation time 435483543 ps
CPU time 2 seconds
Started Jul 28 05:18:00 PM PDT 24
Finished Jul 28 05:18:02 PM PDT 24
Peak memory 200012 kb
Host smart-13da1ddd-ec07-430b-884d-97cf3d362931
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004053341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.4004053341
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4060410409
Short name T555
Test name
Test status
Simulation time 195567228 ps
CPU time 1.3 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 208128 kb
Host smart-ec667511-a7d0-43ac-bdd8-45040482b2d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060410409 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.4060410409
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1100473995
Short name T123
Test name
Test status
Simulation time 74148232 ps
CPU time 0.83 seconds
Started Jul 28 05:17:56 PM PDT 24
Finished Jul 28 05:17:57 PM PDT 24
Peak memory 200024 kb
Host smart-e5daaeab-3fcc-4f85-ab09-c42c212139a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100473995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1100473995
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.637128934
Short name T118
Test name
Test status
Simulation time 127576533 ps
CPU time 1.25 seconds
Started Jul 28 05:17:46 PM PDT 24
Finished Jul 28 05:17:48 PM PDT 24
Peak memory 200044 kb
Host smart-81190462-01c0-49a2-a536-7a70b8790cd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637128934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.637128934
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.578562984
Short name T585
Test name
Test status
Simulation time 143790971 ps
CPU time 1.93 seconds
Started Jul 28 05:17:45 PM PDT 24
Finished Jul 28 05:17:47 PM PDT 24
Peak memory 208184 kb
Host smart-bcda8c39-9c4e-4ad1-b7a9-13972b95fe5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578562984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.578562984
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.290392870
Short name T134
Test name
Test status
Simulation time 865997617 ps
CPU time 2.91 seconds
Started Jul 28 05:18:09 PM PDT 24
Finished Jul 28 05:18:12 PM PDT 24
Peak memory 200080 kb
Host smart-d2282323-4095-457f-a447-af09a2aaea2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290392870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.290392870
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3155090047
Short name T612
Test name
Test status
Simulation time 190539930 ps
CPU time 1.22 seconds
Started Jul 28 05:17:49 PM PDT 24
Finished Jul 28 05:17:51 PM PDT 24
Peak memory 199948 kb
Host smart-62aba8bc-b7f1-4070-b6b6-1f22cc7391e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155090047 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3155090047
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3550238029
Short name T599
Test name
Test status
Simulation time 79071126 ps
CPU time 0.81 seconds
Started Jul 28 05:17:47 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 199744 kb
Host smart-742492d6-10aa-47e6-8ec6-ada890526401
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550238029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3550238029
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1335919431
Short name T122
Test name
Test status
Simulation time 262741363 ps
CPU time 1.48 seconds
Started Jul 28 05:18:09 PM PDT 24
Finished Jul 28 05:18:11 PM PDT 24
Peak memory 200012 kb
Host smart-edadb6d1-928d-4bbd-96c3-deff2988f629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335919431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1335919431
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.389365206
Short name T106
Test name
Test status
Simulation time 201662747 ps
CPU time 1.48 seconds
Started Jul 28 05:18:01 PM PDT 24
Finished Jul 28 05:18:03 PM PDT 24
Peak memory 199912 kb
Host smart-166e8b76-63ac-4adf-beed-bd608ae58d09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389365206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.389365206
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2912009417
Short name T615
Test name
Test status
Simulation time 79071714 ps
CPU time 0.85 seconds
Started Jul 28 05:18:01 PM PDT 24
Finished Jul 28 05:18:02 PM PDT 24
Peak memory 199824 kb
Host smart-da91826c-9a1a-4af5-836d-4c326908ce0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912009417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2912009417
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2940020839
Short name T557
Test name
Test status
Simulation time 272659317 ps
CPU time 1.59 seconds
Started Jul 28 05:18:01 PM PDT 24
Finished Jul 28 05:18:03 PM PDT 24
Peak memory 200196 kb
Host smart-c79698ef-0955-4dd1-8ede-ba347b3b5114
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940020839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2940020839
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.222489709
Short name T103
Test name
Test status
Simulation time 202373763 ps
CPU time 2.73 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 216232 kb
Host smart-63817f31-8ad3-44ba-9462-c7f41b112f04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222489709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.222489709
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3268499522
Short name T542
Test name
Test status
Simulation time 350915806 ps
CPU time 2.57 seconds
Started Jul 28 05:17:35 PM PDT 24
Finished Jul 28 05:17:38 PM PDT 24
Peak memory 199912 kb
Host smart-003aa92d-cdff-485d-a367-cb775045c2c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268499522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
268499522
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3924083851
Short name T561
Test name
Test status
Simulation time 1169336993 ps
CPU time 5.12 seconds
Started Jul 28 05:17:39 PM PDT 24
Finished Jul 28 05:17:44 PM PDT 24
Peak memory 199924 kb
Host smart-4a5fab36-f41d-4cd4-8f98-bd0e180ba3fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924083851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
924083851
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1920411730
Short name T540
Test name
Test status
Simulation time 88870943 ps
CPU time 0.84 seconds
Started Jul 28 05:17:42 PM PDT 24
Finished Jul 28 05:17:43 PM PDT 24
Peak memory 200024 kb
Host smart-f6c73e5e-0e3d-4135-9573-ad5ebb9adeb5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920411730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
920411730
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.476427505
Short name T583
Test name
Test status
Simulation time 200652086 ps
CPU time 1.27 seconds
Started Jul 28 05:17:43 PM PDT 24
Finished Jul 28 05:17:44 PM PDT 24
Peak memory 208096 kb
Host smart-9e872fee-0889-45e9-9bc6-632e52a46250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476427505 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.476427505
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1858368646
Short name T610
Test name
Test status
Simulation time 81412973 ps
CPU time 0.86 seconds
Started Jul 28 05:18:04 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 199764 kb
Host smart-b7e1a809-6181-4a4e-b7dd-6ae5e7e9f332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858368646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1858368646
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.639863124
Short name T119
Test name
Test status
Simulation time 126783119 ps
CPU time 1.11 seconds
Started Jul 28 05:17:38 PM PDT 24
Finished Jul 28 05:17:39 PM PDT 24
Peak memory 199856 kb
Host smart-e4232453-9905-4809-9f6e-7a24a551f2e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639863124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.639863124
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2523073489
Short name T562
Test name
Test status
Simulation time 222989280 ps
CPU time 1.85 seconds
Started Jul 28 05:17:50 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 208156 kb
Host smart-d4036479-f719-4a48-845e-45d7bc37ec0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523073489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2523073489
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.350212337
Short name T64
Test name
Test status
Simulation time 101829163 ps
CPU time 1.26 seconds
Started Jul 28 05:17:43 PM PDT 24
Finished Jul 28 05:17:44 PM PDT 24
Peak memory 200036 kb
Host smart-bb6e2d18-20b6-4923-939c-25bf47356b3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350212337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.350212337
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.545173185
Short name T538
Test name
Test status
Simulation time 492575196 ps
CPU time 5.89 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:59 PM PDT 24
Peak memory 199936 kb
Host smart-4ad625b5-58c6-4848-ab74-01ee4e64f47d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545173185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.545173185
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4158876641
Short name T589
Test name
Test status
Simulation time 108705238 ps
CPU time 0.85 seconds
Started Jul 28 05:17:32 PM PDT 24
Finished Jul 28 05:17:33 PM PDT 24
Peak memory 199776 kb
Host smart-051b0ee7-7a55-40ed-88d8-ff53b59975c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158876641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4
158876641
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1862161913
Short name T617
Test name
Test status
Simulation time 187908708 ps
CPU time 1.28 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 208080 kb
Host smart-327fecdb-5d24-4ed9-8868-f0f4e7d5ce7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862161913 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1862161913
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.892049523
Short name T69
Test name
Test status
Simulation time 53733468 ps
CPU time 0.74 seconds
Started Jul 28 05:17:41 PM PDT 24
Finished Jul 28 05:17:47 PM PDT 24
Peak memory 199756 kb
Host smart-2682787d-e4c9-43f6-9144-444102944846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892049523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.892049523
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2594370216
Short name T581
Test name
Test status
Simulation time 79189247 ps
CPU time 0.99 seconds
Started Jul 28 05:18:03 PM PDT 24
Finished Jul 28 05:18:04 PM PDT 24
Peak memory 199896 kb
Host smart-35ff8743-0635-40f0-8fa2-03fa820c3e50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594370216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2594370216
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1143876229
Short name T609
Test name
Test status
Simulation time 132149498 ps
CPU time 1.74 seconds
Started Jul 28 05:17:43 PM PDT 24
Finished Jul 28 05:17:45 PM PDT 24
Peak memory 211572 kb
Host smart-0431b1bc-d933-4167-83ef-9424914c5565
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143876229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1143876229
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.418344735
Short name T568
Test name
Test status
Simulation time 473501148 ps
CPU time 1.85 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:18:00 PM PDT 24
Peak memory 200004 kb
Host smart-4da2511e-7bd8-4873-bc00-56f0ab58ecd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418344735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
418344735
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2347046286
Short name T544
Test name
Test status
Simulation time 432580450 ps
CPU time 2.58 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 208208 kb
Host smart-0c237f8f-f8fc-4889-bae9-7e5f893e01de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347046286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
347046286
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.868608095
Short name T597
Test name
Test status
Simulation time 269203867 ps
CPU time 3.08 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 199836 kb
Host smart-242316d9-3de5-450b-97bb-30029e6c4d53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868608095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.868608095
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.384439452
Short name T541
Test name
Test status
Simulation time 146987504 ps
CPU time 0.96 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 199840 kb
Host smart-a078db8c-acad-41b1-8cb3-a9f7973b9d82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384439452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.384439452
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3563558753
Short name T603
Test name
Test status
Simulation time 168819858 ps
CPU time 1.53 seconds
Started Jul 28 05:17:49 PM PDT 24
Finished Jul 28 05:17:51 PM PDT 24
Peak memory 208188 kb
Host smart-ce9662a4-770f-4d69-8c5a-e2668838825b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563558753 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3563558753
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1556310202
Short name T605
Test name
Test status
Simulation time 86825668 ps
CPU time 0.84 seconds
Started Jul 28 05:17:43 PM PDT 24
Finished Jul 28 05:17:44 PM PDT 24
Peak memory 199804 kb
Host smart-8f6043a2-2d58-4ea6-91ce-d1f9142d2710
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556310202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1556310202
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1753891522
Short name T66
Test name
Test status
Simulation time 151450004 ps
CPU time 1.11 seconds
Started Jul 28 05:17:48 PM PDT 24
Finished Jul 28 05:17:49 PM PDT 24
Peak memory 199796 kb
Host smart-94441cc8-9bb4-4168-b781-71c9ac30c4f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753891522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1753891522
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2887125231
Short name T614
Test name
Test status
Simulation time 110367688 ps
CPU time 1.53 seconds
Started Jul 28 05:17:44 PM PDT 24
Finished Jul 28 05:17:46 PM PDT 24
Peak memory 210336 kb
Host smart-2b4a7f75-3f7d-456e-bfcb-c4513eb11416
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887125231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2887125231
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3677891254
Short name T547
Test name
Test status
Simulation time 920415620 ps
CPU time 3.48 seconds
Started Jul 28 05:17:47 PM PDT 24
Finished Jul 28 05:17:50 PM PDT 24
Peak memory 200008 kb
Host smart-e8441e0e-a27f-417a-b91a-8d175ee232c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677891254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3677891254
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4256118728
Short name T601
Test name
Test status
Simulation time 123583366 ps
CPU time 1.38 seconds
Started Jul 28 05:17:47 PM PDT 24
Finished Jul 28 05:17:49 PM PDT 24
Peak memory 208284 kb
Host smart-4c49c54c-b44c-4c6c-bee8-2ba521a657d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256118728 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.4256118728
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2542957481
Short name T116
Test name
Test status
Simulation time 67830762 ps
CPU time 0.77 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 199736 kb
Host smart-2d8f9b3a-af6a-4603-96af-957719b48cba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542957481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2542957481
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1200116758
Short name T563
Test name
Test status
Simulation time 138945393 ps
CPU time 1.4 seconds
Started Jul 28 05:18:01 PM PDT 24
Finished Jul 28 05:18:02 PM PDT 24
Peak memory 200000 kb
Host smart-e63afab0-1af1-4239-96c5-7a2b385a543d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200116758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1200116758
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.285088765
Short name T577
Test name
Test status
Simulation time 175236223 ps
CPU time 2.41 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 208168 kb
Host smart-9220a6cc-0e35-4785-ab70-7ff3c19549be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285088765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.285088765
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.925210127
Short name T124
Test name
Test status
Simulation time 495403342 ps
CPU time 2.12 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 199888 kb
Host smart-9751a325-deae-44cd-8aca-cec981095987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925210127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
925210127
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3682725884
Short name T572
Test name
Test status
Simulation time 172982460 ps
CPU time 1.12 seconds
Started Jul 28 05:17:48 PM PDT 24
Finished Jul 28 05:17:49 PM PDT 24
Peak memory 199860 kb
Host smart-06c105e8-1708-49fe-ad84-019fd37a6a19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682725884 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3682725884
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1292055409
Short name T616
Test name
Test status
Simulation time 80203049 ps
CPU time 0.85 seconds
Started Jul 28 05:17:57 PM PDT 24
Finished Jul 28 05:17:57 PM PDT 24
Peak memory 199804 kb
Host smart-b33b9a14-6e6e-4b85-89e3-b3ae9625ab35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292055409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1292055409
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1083863816
Short name T619
Test name
Test status
Simulation time 266649046 ps
CPU time 1.63 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 200008 kb
Host smart-9029f07f-c110-429d-832f-b17251636fa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083863816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1083863816
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2271683274
Short name T565
Test name
Test status
Simulation time 150455229 ps
CPU time 1.93 seconds
Started Jul 28 05:17:57 PM PDT 24
Finished Jul 28 05:17:59 PM PDT 24
Peak memory 208072 kb
Host smart-a31b7be9-72c0-452f-84bb-e870b0f85cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271683274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2271683274
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.368591596
Short name T608
Test name
Test status
Simulation time 916209656 ps
CPU time 3.34 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:57 PM PDT 24
Peak memory 200012 kb
Host smart-130c9da0-ac68-4476-9bdb-a33671fccbae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368591596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
368591596
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4010758526
Short name T554
Test name
Test status
Simulation time 93034326 ps
CPU time 0.91 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 199728 kb
Host smart-a27aaa80-4433-4f2b-9426-726c1eb7fb57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010758526 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4010758526
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2435634734
Short name T578
Test name
Test status
Simulation time 56034232 ps
CPU time 0.74 seconds
Started Jul 28 05:18:03 PM PDT 24
Finished Jul 28 05:18:04 PM PDT 24
Peak memory 199788 kb
Host smart-2b12d38a-2ce2-44a5-a04e-dc9ac1199848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435634734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2435634734
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3217213795
Short name T595
Test name
Test status
Simulation time 222026365 ps
CPU time 1.58 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 200056 kb
Host smart-c5e84a73-4de7-4319-b8d2-e725ad3fc9a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217213795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3217213795
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.731985991
Short name T71
Test name
Test status
Simulation time 137122138 ps
CPU time 1.9 seconds
Started Jul 28 05:17:48 PM PDT 24
Finished Jul 28 05:17:50 PM PDT 24
Peak memory 208104 kb
Host smart-97cd792d-6d72-4f66-a77d-52d5a6a8eff2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731985991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.731985991
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.697039256
Short name T72
Test name
Test status
Simulation time 939704404 ps
CPU time 3.09 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 200016 kb
Host smart-c9e63152-ad07-405b-83d2-6017737374a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697039256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
697039256
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1861932803
Short name T600
Test name
Test status
Simulation time 221784747 ps
CPU time 1.51 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:18:04 PM PDT 24
Peak memory 208108 kb
Host smart-7a8a30cc-24f4-4e33-8ca2-b09b03ec375c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861932803 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1861932803
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2794719048
Short name T582
Test name
Test status
Simulation time 62040730 ps
CPU time 0.81 seconds
Started Jul 28 05:17:37 PM PDT 24
Finished Jul 28 05:17:38 PM PDT 24
Peak memory 199796 kb
Host smart-40425d6e-4320-4822-80e3-0e38d22ca12a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794719048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2794719048
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3426886852
Short name T559
Test name
Test status
Simulation time 158833193 ps
CPU time 1.21 seconds
Started Jul 28 05:17:44 PM PDT 24
Finished Jul 28 05:17:46 PM PDT 24
Peak memory 199820 kb
Host smart-d8c997a5-7506-4ef5-a234-056f11698006
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426886852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3426886852
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3753765976
Short name T591
Test name
Test status
Simulation time 136272703 ps
CPU time 1.95 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 208076 kb
Host smart-ff27d78e-162b-4f79-be6b-3a425063cb60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753765976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3753765976
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2893165509
Short name T105
Test name
Test status
Simulation time 934701871 ps
CPU time 3.28 seconds
Started Jul 28 05:17:43 PM PDT 24
Finished Jul 28 05:17:47 PM PDT 24
Peak memory 199972 kb
Host smart-170a2626-6b10-42df-b710-4f5c5b6ec544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893165509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2893165509
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1472231211
Short name T567
Test name
Test status
Simulation time 147902689 ps
CPU time 1.24 seconds
Started Jul 28 05:18:11 PM PDT 24
Finished Jul 28 05:18:13 PM PDT 24
Peak memory 208108 kb
Host smart-d603e3f1-2c14-4d24-bfce-0dd586c0777c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472231211 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1472231211
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2878515715
Short name T571
Test name
Test status
Simulation time 81358181 ps
CPU time 0.87 seconds
Started Jul 28 05:17:45 PM PDT 24
Finished Jul 28 05:17:46 PM PDT 24
Peak memory 199800 kb
Host smart-ca2d972c-7111-4a65-81c4-ca4050691c2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878515715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2878515715
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1307950767
Short name T552
Test name
Test status
Simulation time 131328516 ps
CPU time 1.12 seconds
Started Jul 28 05:18:16 PM PDT 24
Finished Jul 28 05:18:17 PM PDT 24
Peak memory 199820 kb
Host smart-62d225d8-d896-4523-9d40-7a6c6eb001e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307950767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1307950767
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2019640583
Short name T73
Test name
Test status
Simulation time 487946173 ps
CPU time 3.66 seconds
Started Jul 28 05:17:38 PM PDT 24
Finished Jul 28 05:17:42 PM PDT 24
Peak memory 208124 kb
Host smart-2f47b1af-320b-442e-80f6-5104ea55dd87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019640583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2019640583
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1945165827
Short name T132
Test name
Test status
Simulation time 502871941 ps
CPU time 2.09 seconds
Started Jul 28 05:18:00 PM PDT 24
Finished Jul 28 05:18:02 PM PDT 24
Peak memory 200016 kb
Host smart-31e6b107-83c3-4eeb-89ae-898f7ebdaa1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945165827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1945165827
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3949715786
Short name T486
Test name
Test status
Simulation time 69160652 ps
CPU time 0.76 seconds
Started Jul 28 05:16:34 PM PDT 24
Finished Jul 28 05:16:35 PM PDT 24
Peak memory 199800 kb
Host smart-6255a636-48a6-4809-b0d6-83d65ad88ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949715786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3949715786
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3101870
Short name T324
Test name
Test status
Simulation time 2369296957 ps
CPU time 8.07 seconds
Started Jul 28 05:16:33 PM PDT 24
Finished Jul 28 05:16:41 PM PDT 24
Peak memory 217768 kb
Host smart-e22af5b0-6ba5-4750-8b6d-b45d9b7fd7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3101870
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1707034302
Short name T317
Test name
Test status
Simulation time 243741451 ps
CPU time 1.11 seconds
Started Jul 28 05:16:25 PM PDT 24
Finished Jul 28 05:16:26 PM PDT 24
Peak memory 217416 kb
Host smart-82efc638-7a73-42d7-ad2e-1fb14d748aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707034302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1707034302
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2532341495
Short name T298
Test name
Test status
Simulation time 83914010 ps
CPU time 0.76 seconds
Started Jul 28 05:16:26 PM PDT 24
Finished Jul 28 05:16:27 PM PDT 24
Peak memory 199868 kb
Host smart-bdf98391-560b-4250-a270-50960ca663ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532341495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2532341495
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.471021144
Short name T187
Test name
Test status
Simulation time 1180911047 ps
CPU time 5.22 seconds
Started Jul 28 05:16:30 PM PDT 24
Finished Jul 28 05:16:35 PM PDT 24
Peak memory 200248 kb
Host smart-9aa2ee50-5148-456a-9430-376d7cf444d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471021144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.471021144
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.4252590630
Short name T77
Test name
Test status
Simulation time 8310436711 ps
CPU time 13.62 seconds
Started Jul 28 05:16:32 PM PDT 24
Finished Jul 28 05:16:45 PM PDT 24
Peak memory 217584 kb
Host smart-bb622ee6-046c-4129-9cd5-b9e0edd66b67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252590630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4252590630
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1043741099
Short name T277
Test name
Test status
Simulation time 109124323 ps
CPU time 0.98 seconds
Started Jul 28 05:16:40 PM PDT 24
Finished Jul 28 05:16:42 PM PDT 24
Peak memory 199944 kb
Host smart-7dd9f4b3-673e-412b-93e7-b8d256fbba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043741099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1043741099
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.4194911553
Short name T390
Test name
Test status
Simulation time 202941865 ps
CPU time 1.45 seconds
Started Jul 28 05:16:36 PM PDT 24
Finished Jul 28 05:16:37 PM PDT 24
Peak memory 200304 kb
Host smart-7c320afe-5bb8-41eb-b12e-dc5d78a47be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194911553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.4194911553
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1127797203
Short name T97
Test name
Test status
Simulation time 2154748703 ps
CPU time 7.6 seconds
Started Jul 28 05:16:48 PM PDT 24
Finished Jul 28 05:16:56 PM PDT 24
Peak memory 200332 kb
Host smart-937471d0-4acc-43cc-82a8-4ca28ec336f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127797203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1127797203
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.4208195592
Short name T248
Test name
Test status
Simulation time 124541209 ps
CPU time 1.5 seconds
Started Jul 28 05:16:42 PM PDT 24
Finished Jul 28 05:16:44 PM PDT 24
Peak memory 200056 kb
Host smart-ba09df58-5d93-4162-bf14-33a0c5da3360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208195592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.4208195592
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1373288161
Short name T445
Test name
Test status
Simulation time 176580501 ps
CPU time 1.11 seconds
Started Jul 28 05:16:46 PM PDT 24
Finished Jul 28 05:16:47 PM PDT 24
Peak memory 200052 kb
Host smart-0c9ad777-059d-4b81-9040-3050777786f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373288161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1373288161
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2718732546
Short name T477
Test name
Test status
Simulation time 63992642 ps
CPU time 0.78 seconds
Started Jul 28 05:16:26 PM PDT 24
Finished Jul 28 05:16:27 PM PDT 24
Peak memory 199824 kb
Host smart-0dae58de-1376-4844-b48b-21b84f562c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718732546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2718732546
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2686413074
Short name T27
Test name
Test status
Simulation time 1222287363 ps
CPU time 5.18 seconds
Started Jul 28 05:16:34 PM PDT 24
Finished Jul 28 05:16:39 PM PDT 24
Peak memory 217764 kb
Host smart-ce408b27-74f0-44de-9975-4a6dc1952b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686413074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2686413074
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2447101526
Short name T282
Test name
Test status
Simulation time 244664773 ps
CPU time 1.07 seconds
Started Jul 28 05:16:24 PM PDT 24
Finished Jul 28 05:16:25 PM PDT 24
Peak memory 217356 kb
Host smart-8e0c2aa3-b162-42eb-b932-5f890e2910a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447101526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2447101526
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2862285526
Short name T323
Test name
Test status
Simulation time 178776678 ps
CPU time 0.91 seconds
Started Jul 28 05:16:42 PM PDT 24
Finished Jul 28 05:16:43 PM PDT 24
Peak memory 199796 kb
Host smart-4b26d503-2cfd-4985-9532-0ac975adff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862285526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2862285526
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2799744181
Short name T194
Test name
Test status
Simulation time 1706703034 ps
CPU time 6.58 seconds
Started Jul 28 05:16:41 PM PDT 24
Finished Jul 28 05:16:48 PM PDT 24
Peak memory 200260 kb
Host smart-2bb778a3-9b10-47b9-8cdb-ef3a6e5d4485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799744181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2799744181
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1429405559
Short name T76
Test name
Test status
Simulation time 16515952422 ps
CPU time 25.76 seconds
Started Jul 28 05:16:31 PM PDT 24
Finished Jul 28 05:16:57 PM PDT 24
Peak memory 218144 kb
Host smart-b242b655-f184-4c3f-934f-c46ce829574a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429405559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1429405559
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2547251903
Short name T172
Test name
Test status
Simulation time 180203583 ps
CPU time 1.26 seconds
Started Jul 28 05:16:38 PM PDT 24
Finished Jul 28 05:16:39 PM PDT 24
Peak memory 199988 kb
Host smart-09429e98-b7a2-42f0-bc88-5b7a90d91850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547251903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2547251903
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2750971387
Short name T431
Test name
Test status
Simulation time 12364257053 ps
CPU time 40.86 seconds
Started Jul 28 05:16:33 PM PDT 24
Finished Jul 28 05:17:14 PM PDT 24
Peak memory 208496 kb
Host smart-6baea9e6-c1c2-4e1b-864e-fbc7aedf26d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750971387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2750971387
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3801806434
Short name T63
Test name
Test status
Simulation time 347578200 ps
CPU time 2.24 seconds
Started Jul 28 05:16:29 PM PDT 24
Finished Jul 28 05:16:36 PM PDT 24
Peak memory 200296 kb
Host smart-634ceb44-8601-4c10-b7a0-2b0d7959bdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801806434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3801806434
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2405787318
Short name T2
Test name
Test status
Simulation time 200652571 ps
CPU time 1.28 seconds
Started Jul 28 05:16:27 PM PDT 24
Finished Jul 28 05:16:29 PM PDT 24
Peak memory 200060 kb
Host smart-f9352eda-a878-4ce7-b1b1-2d71acae685b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405787318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2405787318
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.4233264028
Short name T453
Test name
Test status
Simulation time 79786331 ps
CPU time 0.77 seconds
Started Jul 28 05:16:47 PM PDT 24
Finished Jul 28 05:16:48 PM PDT 24
Peak memory 199904 kb
Host smart-b90a58cc-1290-4d20-9968-c1d3bba3023e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233264028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.4233264028
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1548052805
Short name T420
Test name
Test status
Simulation time 1888303422 ps
CPU time 7.01 seconds
Started Jul 28 05:16:34 PM PDT 24
Finished Jul 28 05:16:42 PM PDT 24
Peak memory 217728 kb
Host smart-638daeb7-a187-4287-b42b-22e15ef367cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548052805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1548052805
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1373863165
Short name T265
Test name
Test status
Simulation time 244452273 ps
CPU time 1.08 seconds
Started Jul 28 05:16:34 PM PDT 24
Finished Jul 28 05:16:36 PM PDT 24
Peak memory 217432 kb
Host smart-5aaea520-24cd-4436-bde4-81311b6e7691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373863165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1373863165
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3784186835
Short name T338
Test name
Test status
Simulation time 172828397 ps
CPU time 0.87 seconds
Started Jul 28 05:16:38 PM PDT 24
Finished Jul 28 05:16:39 PM PDT 24
Peak memory 199836 kb
Host smart-1655a1e6-fb18-4b0b-8f17-c104885ce6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784186835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3784186835
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1598470217
Short name T473
Test name
Test status
Simulation time 881458555 ps
CPU time 4.36 seconds
Started Jul 28 05:16:37 PM PDT 24
Finished Jul 28 05:16:41 PM PDT 24
Peak memory 200284 kb
Host smart-b1393cd4-7c66-4d09-b635-1786770ff2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598470217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1598470217
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3451877312
Short name T269
Test name
Test status
Simulation time 144659608 ps
CPU time 1.04 seconds
Started Jul 28 05:16:41 PM PDT 24
Finished Jul 28 05:16:42 PM PDT 24
Peak memory 200044 kb
Host smart-ee0fcbaf-937f-4abb-b2ed-13e3b70a0a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451877312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3451877312
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1277457175
Short name T368
Test name
Test status
Simulation time 189651580 ps
CPU time 1.35 seconds
Started Jul 28 05:16:49 PM PDT 24
Finished Jul 28 05:16:50 PM PDT 24
Peak memory 200204 kb
Host smart-680d81f9-ce7a-4b4a-aaa6-255953169005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277457175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1277457175
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2924973315
Short name T280
Test name
Test status
Simulation time 11013782203 ps
CPU time 34.6 seconds
Started Jul 28 05:16:35 PM PDT 24
Finished Jul 28 05:17:10 PM PDT 24
Peak memory 200320 kb
Host smart-17bbd1b8-b301-477f-ab50-d87dc8df51da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924973315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2924973315
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1902560503
Short name T281
Test name
Test status
Simulation time 494746862 ps
CPU time 2.53 seconds
Started Jul 28 05:16:42 PM PDT 24
Finished Jul 28 05:16:45 PM PDT 24
Peak memory 200172 kb
Host smart-9b035d86-bbe1-40bb-8806-cecf5ba728b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902560503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1902560503
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.269992605
Short name T136
Test name
Test status
Simulation time 171415807 ps
CPU time 1.18 seconds
Started Jul 28 05:16:43 PM PDT 24
Finished Jul 28 05:16:44 PM PDT 24
Peak memory 200056 kb
Host smart-b1d396b0-7b90-4a40-ad6b-894638842080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269992605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.269992605
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3817238899
Short name T32
Test name
Test status
Simulation time 2353710956 ps
CPU time 8.1 seconds
Started Jul 28 05:16:40 PM PDT 24
Finished Jul 28 05:16:48 PM PDT 24
Peak memory 217792 kb
Host smart-f7667199-c1da-4aec-bdfe-03f625cc72c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817238899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3817238899
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2486958482
Short name T14
Test name
Test status
Simulation time 193865885 ps
CPU time 0.97 seconds
Started Jul 28 05:16:43 PM PDT 24
Finished Jul 28 05:16:44 PM PDT 24
Peak memory 199836 kb
Host smart-34d8b424-8ff6-45c5-b0a5-41160876a900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486958482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2486958482
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1801292043
Short name T38
Test name
Test status
Simulation time 1698746732 ps
CPU time 6.01 seconds
Started Jul 28 05:16:51 PM PDT 24
Finished Jul 28 05:16:57 PM PDT 24
Peak memory 200336 kb
Host smart-0c2c9de3-3da1-48e1-a10f-0064041399c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801292043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1801292043
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.158743650
Short name T428
Test name
Test status
Simulation time 170275158 ps
CPU time 1.13 seconds
Started Jul 28 05:16:37 PM PDT 24
Finished Jul 28 05:16:38 PM PDT 24
Peak memory 200080 kb
Host smart-56eb7fa3-1d04-40f8-a5af-9e60482a61cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158743650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.158743650
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3004132949
Short name T366
Test name
Test status
Simulation time 187411754 ps
CPU time 1.33 seconds
Started Jul 28 05:16:57 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 200220 kb
Host smart-a3742ac3-5c17-4784-a8f2-3bbe1df7e6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004132949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3004132949
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1938929025
Short name T302
Test name
Test status
Simulation time 365987815 ps
CPU time 2.1 seconds
Started Jul 28 05:16:41 PM PDT 24
Finished Jul 28 05:16:44 PM PDT 24
Peak memory 208204 kb
Host smart-9396dc7c-6bf6-41e1-9f1a-fd0984408671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938929025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1938929025
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2706842617
Short name T483
Test name
Test status
Simulation time 272790488 ps
CPU time 1.47 seconds
Started Jul 28 05:16:46 PM PDT 24
Finished Jul 28 05:16:48 PM PDT 24
Peak memory 200088 kb
Host smart-3b92487f-5590-4609-8722-05c66b26a44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706842617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2706842617
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4206427708
Short name T481
Test name
Test status
Simulation time 114999276 ps
CPU time 0.86 seconds
Started Jul 28 05:16:45 PM PDT 24
Finished Jul 28 05:16:46 PM PDT 24
Peak memory 199884 kb
Host smart-8eeabb02-7308-49dd-8a59-2186e40aaeca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206427708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4206427708
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2155022150
Short name T459
Test name
Test status
Simulation time 1217125708 ps
CPU time 6.04 seconds
Started Jul 28 05:16:35 PM PDT 24
Finished Jul 28 05:16:41 PM PDT 24
Peak memory 221660 kb
Host smart-9d1e0448-d39f-435e-bfab-ef63a90df13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155022150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2155022150
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.657316918
Short name T515
Test name
Test status
Simulation time 243780297 ps
CPU time 1.04 seconds
Started Jul 28 05:16:49 PM PDT 24
Finished Jul 28 05:16:50 PM PDT 24
Peak memory 217416 kb
Host smart-dbfca1f1-8cad-409e-a175-9c8556c069f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657316918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.657316918
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2883681375
Short name T257
Test name
Test status
Simulation time 161450334 ps
CPU time 0.88 seconds
Started Jul 28 05:16:41 PM PDT 24
Finished Jul 28 05:16:43 PM PDT 24
Peak memory 199908 kb
Host smart-aa98de2f-ceb4-4b57-9358-23c643c74720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883681375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2883681375
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2767340008
Short name T131
Test name
Test status
Simulation time 1214703129 ps
CPU time 5.39 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 200272 kb
Host smart-b618abf4-f785-4f2e-af67-5a15f64d658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767340008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2767340008
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3781461568
Short name T91
Test name
Test status
Simulation time 174906268 ps
CPU time 1.17 seconds
Started Jul 28 05:16:47 PM PDT 24
Finished Jul 28 05:16:48 PM PDT 24
Peak memory 199968 kb
Host smart-b250710f-2a60-4c95-8873-9870528e2a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781461568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3781461568
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1006334873
Short name T152
Test name
Test status
Simulation time 122073615 ps
CPU time 1.15 seconds
Started Jul 28 05:16:37 PM PDT 24
Finished Jul 28 05:16:38 PM PDT 24
Peak memory 200280 kb
Host smart-00f3eafe-c503-4727-b771-62338936fb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006334873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1006334873
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2790524214
Short name T96
Test name
Test status
Simulation time 3666734436 ps
CPU time 16.2 seconds
Started Jul 28 05:16:46 PM PDT 24
Finished Jul 28 05:17:03 PM PDT 24
Peak memory 200276 kb
Host smart-81bfe33d-f1d8-4b53-9865-3db5bcae4ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790524214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2790524214
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.4146146033
Short name T470
Test name
Test status
Simulation time 433199265 ps
CPU time 2.24 seconds
Started Jul 28 05:16:57 PM PDT 24
Finished Jul 28 05:16:59 PM PDT 24
Peak memory 208284 kb
Host smart-c6716478-ce70-4d0e-9abd-6d1ebc64b421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146146033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.4146146033
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2634855359
Short name T284
Test name
Test status
Simulation time 170458640 ps
CPU time 1.28 seconds
Started Jul 28 05:17:08 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 200280 kb
Host smart-54fbd265-d4c5-4987-9cd5-5402e3d61306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634855359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2634855359
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2551004663
Short name T184
Test name
Test status
Simulation time 112027141 ps
CPU time 0.86 seconds
Started Jul 28 05:16:44 PM PDT 24
Finished Jul 28 05:16:45 PM PDT 24
Peak memory 199820 kb
Host smart-9a2e8254-3746-4772-a6a6-fb78777ed234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551004663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2551004663
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.101791447
Short name T313
Test name
Test status
Simulation time 1874705861 ps
CPU time 7.86 seconds
Started Jul 28 05:16:36 PM PDT 24
Finished Jul 28 05:16:44 PM PDT 24
Peak memory 217784 kb
Host smart-a1ea2231-dd7a-4369-8e66-a0e763048210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101791447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.101791447
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.4117791535
Short name T401
Test name
Test status
Simulation time 244038607 ps
CPU time 1.03 seconds
Started Jul 28 05:16:50 PM PDT 24
Finished Jul 28 05:16:51 PM PDT 24
Peak memory 217364 kb
Host smart-8bd41e27-750f-4c41-9ad6-c9993b8dd850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117791535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.4117791535
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1013289178
Short name T375
Test name
Test status
Simulation time 163821848 ps
CPU time 0.83 seconds
Started Jul 28 05:16:50 PM PDT 24
Finished Jul 28 05:16:51 PM PDT 24
Peak memory 199896 kb
Host smart-dca857b9-f1dd-4826-b174-c939365d40df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013289178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1013289178
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3400834296
Short name T495
Test name
Test status
Simulation time 1660879220 ps
CPU time 5.98 seconds
Started Jul 28 05:16:40 PM PDT 24
Finished Jul 28 05:16:46 PM PDT 24
Peak memory 200308 kb
Host smart-44ca391c-8878-4ab6-bbb5-ba6964e3d86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400834296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3400834296
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4278945049
Short name T183
Test name
Test status
Simulation time 155489586 ps
CPU time 1.09 seconds
Started Jul 28 05:16:44 PM PDT 24
Finished Jul 28 05:16:45 PM PDT 24
Peak memory 200068 kb
Host smart-23b53ae3-00ae-453c-a976-1456eb8baaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278945049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4278945049
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3460098508
Short name T237
Test name
Test status
Simulation time 119397270 ps
CPU time 1.16 seconds
Started Jul 28 05:16:37 PM PDT 24
Finished Jul 28 05:16:38 PM PDT 24
Peak memory 200216 kb
Host smart-4818bbae-3e6b-4363-8d40-f19d1f6d3523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460098508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3460098508
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2641726635
Short name T160
Test name
Test status
Simulation time 705668444 ps
CPU time 3.85 seconds
Started Jul 28 05:16:45 PM PDT 24
Finished Jul 28 05:16:49 PM PDT 24
Peak memory 200388 kb
Host smart-83fcfc20-1e2a-46fe-b79f-598b7a1901fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641726635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2641726635
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1908526900
Short name T251
Test name
Test status
Simulation time 337369109 ps
CPU time 2.01 seconds
Started Jul 28 05:16:38 PM PDT 24
Finished Jul 28 05:16:40 PM PDT 24
Peak memory 200076 kb
Host smart-3a4f851d-0c7d-4bb7-bb1f-694838c2e588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908526900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1908526900
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1222975076
Short name T233
Test name
Test status
Simulation time 231615870 ps
CPU time 1.57 seconds
Started Jul 28 05:16:50 PM PDT 24
Finished Jul 28 05:16:52 PM PDT 24
Peak memory 200272 kb
Host smart-25349153-63d2-4913-948b-0adc45e83dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222975076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1222975076
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1068704128
Short name T272
Test name
Test status
Simulation time 82444072 ps
CPU time 0.76 seconds
Started Jul 28 05:16:53 PM PDT 24
Finished Jul 28 05:16:54 PM PDT 24
Peak memory 199808 kb
Host smart-d1b1846a-d3f6-42fb-80f4-c24a7c41f586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068704128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1068704128
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2383568732
Short name T424
Test name
Test status
Simulation time 1897970939 ps
CPU time 6.83 seconds
Started Jul 28 05:16:41 PM PDT 24
Finished Jul 28 05:16:48 PM PDT 24
Peak memory 220712 kb
Host smart-7f8d0239-e190-4707-8f8a-1039d8d7b7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383568732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2383568732
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.65030864
Short name T9
Test name
Test status
Simulation time 244954191 ps
CPU time 1.12 seconds
Started Jul 28 05:16:39 PM PDT 24
Finished Jul 28 05:16:40 PM PDT 24
Peak memory 217372 kb
Host smart-7828618e-b046-4ad6-a5d8-d6fe8e532536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65030864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.65030864
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1416694708
Short name T19
Test name
Test status
Simulation time 161649417 ps
CPU time 0.88 seconds
Started Jul 28 05:16:34 PM PDT 24
Finished Jul 28 05:16:35 PM PDT 24
Peak memory 199932 kb
Host smart-8d2bad1c-cb40-4948-bd62-8c179186680c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416694708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1416694708
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.434001645
Short name T412
Test name
Test status
Simulation time 1634582587 ps
CPU time 6.54 seconds
Started Jul 28 05:16:40 PM PDT 24
Finished Jul 28 05:16:47 PM PDT 24
Peak memory 200268 kb
Host smart-e0fb1983-bf28-408f-b5be-66f6f553678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434001645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.434001645
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2121933163
Short name T162
Test name
Test status
Simulation time 177897448 ps
CPU time 1.17 seconds
Started Jul 28 05:16:52 PM PDT 24
Finished Jul 28 05:16:53 PM PDT 24
Peak memory 200072 kb
Host smart-e34ef3c4-aab7-4422-8d0c-8abc5a2b02d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121933163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2121933163
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2245411348
Short name T383
Test name
Test status
Simulation time 206239162 ps
CPU time 1.52 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 200280 kb
Host smart-7a998dea-caa6-4653-9a91-34fec53544fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245411348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2245411348
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1383113192
Short name T398
Test name
Test status
Simulation time 2041337306 ps
CPU time 7.76 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:07 PM PDT 24
Peak memory 200316 kb
Host smart-73f9e526-ef45-47d8-a349-444b93d523da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383113192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1383113192
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3481073909
Short name T258
Test name
Test status
Simulation time 132873019 ps
CPU time 1.79 seconds
Started Jul 28 05:16:42 PM PDT 24
Finished Jul 28 05:16:44 PM PDT 24
Peak memory 200116 kb
Host smart-36af5261-5e51-43a1-ad2d-0183979c7a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481073909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3481073909
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3774974950
Short name T460
Test name
Test status
Simulation time 145067855 ps
CPU time 1.08 seconds
Started Jul 28 05:17:02 PM PDT 24
Finished Jul 28 05:17:04 PM PDT 24
Peak memory 199952 kb
Host smart-1b099c73-6ee4-4c02-b16f-df4e610817ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774974950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3774974950
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.601572028
Short name T87
Test name
Test status
Simulation time 69746274 ps
CPU time 0.8 seconds
Started Jul 28 05:17:14 PM PDT 24
Finished Jul 28 05:17:15 PM PDT 24
Peak memory 199876 kb
Host smart-6144f678-2814-49d0-b896-2c359712db40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601572028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.601572028
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2296472089
Short name T213
Test name
Test status
Simulation time 244659391 ps
CPU time 1.05 seconds
Started Jul 28 05:17:02 PM PDT 24
Finished Jul 28 05:17:03 PM PDT 24
Peak memory 217420 kb
Host smart-25188f5e-19c0-4f4b-90e1-66075b67bfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296472089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2296472089
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3559917884
Short name T451
Test name
Test status
Simulation time 118162252 ps
CPU time 0.83 seconds
Started Jul 28 05:16:50 PM PDT 24
Finished Jul 28 05:16:51 PM PDT 24
Peak memory 199864 kb
Host smart-9bbc30c8-faac-40df-a780-6614aee9fbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559917884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3559917884
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2630374830
Short name T354
Test name
Test status
Simulation time 948073436 ps
CPU time 4.78 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:10 PM PDT 24
Peak memory 200312 kb
Host smart-29fa1848-8629-4f07-87e4-f2f91f2a67c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630374830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2630374830
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.620513926
Short name T35
Test name
Test status
Simulation time 155574090 ps
CPU time 1.2 seconds
Started Jul 28 05:16:54 PM PDT 24
Finished Jul 28 05:16:55 PM PDT 24
Peak memory 200072 kb
Host smart-ae234639-c86b-4b19-b9fc-edbbf9c654d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620513926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.620513926
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3822938337
Short name T491
Test name
Test status
Simulation time 121702792 ps
CPU time 1.18 seconds
Started Jul 28 05:16:58 PM PDT 24
Finished Jul 28 05:16:59 PM PDT 24
Peak memory 200280 kb
Host smart-fac4b17a-b64b-42af-bb55-fb7c45765a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822938337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3822938337
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3606586673
Short name T252
Test name
Test status
Simulation time 9157231358 ps
CPU time 32.13 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:37 PM PDT 24
Peak memory 200300 kb
Host smart-7b87c718-6f00-490e-8d29-6a7a65e11603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606586673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3606586673
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1742583669
Short name T155
Test name
Test status
Simulation time 130750082 ps
CPU time 1.61 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:03 PM PDT 24
Peak memory 208524 kb
Host smart-4725d1a3-5685-4930-86e5-cb9d2a7056f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742583669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1742583669
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1954990119
Short name T391
Test name
Test status
Simulation time 84987706 ps
CPU time 0.84 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:16:57 PM PDT 24
Peak memory 200064 kb
Host smart-bfa117da-0e4d-4013-8b1f-9c484ff0cb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954990119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1954990119
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3662355119
Short name T51
Test name
Test status
Simulation time 61195694 ps
CPU time 0.74 seconds
Started Jul 28 05:16:53 PM PDT 24
Finished Jul 28 05:16:54 PM PDT 24
Peak memory 199788 kb
Host smart-71fdce2b-66ce-4a22-999f-f67495e9fbd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662355119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3662355119
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1792770182
Short name T361
Test name
Test status
Simulation time 1891011557 ps
CPU time 7.85 seconds
Started Jul 28 05:16:51 PM PDT 24
Finished Jul 28 05:16:59 PM PDT 24
Peak memory 217916 kb
Host smart-15263e28-ab44-451f-bc09-0f94da20ebb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792770182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1792770182
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.940328784
Short name T517
Test name
Test status
Simulation time 243914585 ps
CPU time 1.11 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:16:57 PM PDT 24
Peak memory 217468 kb
Host smart-dab7601e-0f13-4cd9-a685-115fe4bf585d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940328784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.940328784
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2633286792
Short name T348
Test name
Test status
Simulation time 151202432 ps
CPU time 0.84 seconds
Started Jul 28 05:16:51 PM PDT 24
Finished Jul 28 05:16:52 PM PDT 24
Peak memory 199744 kb
Host smart-7d12f2fa-9848-4b3d-9ec6-43b643afcd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633286792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2633286792
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3421968301
Short name T20
Test name
Test status
Simulation time 1015072369 ps
CPU time 4.61 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 200364 kb
Host smart-3d9510ac-b593-476d-bd55-ed98ceff652e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421968301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3421968301
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1000758801
Short name T226
Test name
Test status
Simulation time 102624415 ps
CPU time 0.99 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:05 PM PDT 24
Peak memory 200064 kb
Host smart-cecd0933-9ea8-453c-9d06-c157382be47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000758801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1000758801
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3129558097
Short name T433
Test name
Test status
Simulation time 200656272 ps
CPU time 1.35 seconds
Started Jul 28 05:16:58 PM PDT 24
Finished Jul 28 05:17:00 PM PDT 24
Peak memory 200276 kb
Host smart-c44bcc80-6570-4ab7-8ca9-f570f236b5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129558097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3129558097
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.4294462145
Short name T166
Test name
Test status
Simulation time 9931488457 ps
CPU time 35.91 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:35 PM PDT 24
Peak memory 200328 kb
Host smart-f5415ed1-b28d-4043-af2d-a2d2646c24c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294462145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.4294462145
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4187822843
Short name T351
Test name
Test status
Simulation time 542039527 ps
CPU time 2.84 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:08 PM PDT 24
Peak memory 200060 kb
Host smart-96a0d2b7-0c69-491b-ad3d-dec1a9699162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187822843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4187822843
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1350819251
Short name T312
Test name
Test status
Simulation time 133910198 ps
CPU time 1.16 seconds
Started Jul 28 05:16:51 PM PDT 24
Finished Jul 28 05:16:52 PM PDT 24
Peak memory 200092 kb
Host smart-bc86c26d-3db4-4451-9e36-b5323ea48f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350819251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1350819251
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1320205367
Short name T89
Test name
Test status
Simulation time 72372251 ps
CPU time 0.8 seconds
Started Jul 28 05:16:58 PM PDT 24
Finished Jul 28 05:16:59 PM PDT 24
Peak memory 199816 kb
Host smart-18d2a49e-c6f5-489d-9a6d-7a6f83442d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320205367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1320205367
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.92384835
Short name T492
Test name
Test status
Simulation time 1227913363 ps
CPU time 5.63 seconds
Started Jul 28 05:16:52 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 216792 kb
Host smart-f36813e2-b008-4710-9b26-3045e6b346e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92384835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.92384835
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.934355230
Short name T52
Test name
Test status
Simulation time 244901297 ps
CPU time 1.12 seconds
Started Jul 28 05:16:57 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 217432 kb
Host smart-da32f76d-d604-4c7b-8800-cc294064ed81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934355230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.934355230
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.324653968
Short name T169
Test name
Test status
Simulation time 114987754 ps
CPU time 0.82 seconds
Started Jul 28 05:16:51 PM PDT 24
Finished Jul 28 05:16:52 PM PDT 24
Peak memory 199896 kb
Host smart-54e7a324-144d-4c73-82f6-0a9d3d800354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324653968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.324653968
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.199204651
Short name T48
Test name
Test status
Simulation time 738498979 ps
CPU time 3.88 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:03 PM PDT 24
Peak memory 200332 kb
Host smart-4aaaec18-29c0-4aac-bced-75ed5c0bcc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199204651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.199204651
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3146252911
Short name T437
Test name
Test status
Simulation time 100866557 ps
CPU time 1.03 seconds
Started Jul 28 05:16:49 PM PDT 24
Finished Jul 28 05:16:50 PM PDT 24
Peak memory 200072 kb
Host smart-4be23c8f-496f-4f96-aa86-0eff71c8b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146252911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3146252911
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.564316129
Short name T181
Test name
Test status
Simulation time 204951414 ps
CPU time 1.5 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 200216 kb
Host smart-f7baba75-ffde-4bd9-8897-69aa74741772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564316129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.564316129
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1899109361
Short name T335
Test name
Test status
Simulation time 1424831170 ps
CPU time 5.49 seconds
Started Jul 28 05:16:54 PM PDT 24
Finished Jul 28 05:17:00 PM PDT 24
Peak memory 200284 kb
Host smart-7a0273e0-8173-412b-83e5-692dcb5e97be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899109361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1899109361
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3074405051
Short name T441
Test name
Test status
Simulation time 377567087 ps
CPU time 2.38 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:04 PM PDT 24
Peak memory 200100 kb
Host smart-443c1704-485d-4272-a4b2-fca88eadf505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074405051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3074405051
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2769799782
Short name T430
Test name
Test status
Simulation time 106533922 ps
CPU time 0.87 seconds
Started Jul 28 05:16:55 PM PDT 24
Finished Jul 28 05:16:56 PM PDT 24
Peak memory 200004 kb
Host smart-cf97fba6-d303-40dc-bf98-565efc7d013a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769799782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2769799782
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3731156331
Short name T319
Test name
Test status
Simulation time 67563649 ps
CPU time 0.76 seconds
Started Jul 28 05:16:50 PM PDT 24
Finished Jul 28 05:16:51 PM PDT 24
Peak memory 199848 kb
Host smart-a9de66ab-b6a5-4f44-a516-e738a623fa3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731156331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3731156331
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2403456358
Short name T434
Test name
Test status
Simulation time 1221076004 ps
CPU time 5.28 seconds
Started Jul 28 05:16:53 PM PDT 24
Finished Jul 28 05:16:59 PM PDT 24
Peak memory 217768 kb
Host smart-e4e80f4c-55df-4db3-a61d-6f7630b26a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403456358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2403456358
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2378559047
Short name T98
Test name
Test status
Simulation time 245491057 ps
CPU time 1.05 seconds
Started Jul 28 05:16:52 PM PDT 24
Finished Jul 28 05:16:53 PM PDT 24
Peak memory 217404 kb
Host smart-419ba0a9-7f67-4dee-8772-4bf76553bc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378559047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2378559047
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2104358660
Short name T381
Test name
Test status
Simulation time 161944234 ps
CPU time 0.89 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 199896 kb
Host smart-670023f9-b950-42e4-95bf-82f44a9bf1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104358660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2104358660
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2035108011
Short name T109
Test name
Test status
Simulation time 1631087469 ps
CPU time 6.24 seconds
Started Jul 28 05:16:48 PM PDT 24
Finished Jul 28 05:16:54 PM PDT 24
Peak memory 200352 kb
Host smart-df6afdb6-d069-4c60-ac0d-2e227c830451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035108011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2035108011
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.405658979
Short name T231
Test name
Test status
Simulation time 112827537 ps
CPU time 0.98 seconds
Started Jul 28 05:16:57 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 200048 kb
Host smart-2ea9586d-9fe9-4084-ac42-6e3826bec8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405658979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.405658979
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.477696388
Short name T436
Test name
Test status
Simulation time 199371035 ps
CPU time 1.46 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:03 PM PDT 24
Peak memory 200292 kb
Host smart-b5e18bd1-3b14-4387-a525-2279119b5598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477696388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.477696388
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2957989871
Short name T240
Test name
Test status
Simulation time 13549099271 ps
CPU time 45.92 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:51 PM PDT 24
Peak memory 200380 kb
Host smart-5e26a2fc-224a-47d0-9e70-507ff6fc4ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957989871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2957989871
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.81360602
Short name T347
Test name
Test status
Simulation time 308944126 ps
CPU time 2.02 seconds
Started Jul 28 05:17:00 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 208260 kb
Host smart-dcf6de3f-4c7c-493e-ae9a-3fc66100e209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81360602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.81360602
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.881616094
Short name T474
Test name
Test status
Simulation time 108234911 ps
CPU time 1.01 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:07 PM PDT 24
Peak memory 199988 kb
Host smart-33579965-c4ee-499a-a2b3-32b84c679e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881616094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.881616094
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1123395516
Short name T504
Test name
Test status
Simulation time 58028895 ps
CPU time 0.73 seconds
Started Jul 28 05:16:54 PM PDT 24
Finished Jul 28 05:16:54 PM PDT 24
Peak memory 199808 kb
Host smart-e2dabc11-2161-4060-8baf-ef61c50af7a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123395516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1123395516
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2224986945
Short name T55
Test name
Test status
Simulation time 1898124476 ps
CPU time 6.73 seconds
Started Jul 28 05:16:57 PM PDT 24
Finished Jul 28 05:17:04 PM PDT 24
Peak memory 221620 kb
Host smart-74fcab73-1f0f-4143-b1f3-5ee33e6da598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224986945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2224986945
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1134262015
Short name T500
Test name
Test status
Simulation time 244483336 ps
CPU time 1.22 seconds
Started Jul 28 05:16:50 PM PDT 24
Finished Jul 28 05:16:51 PM PDT 24
Peak memory 217416 kb
Host smart-c8391f5b-0b6b-4119-b6f3-46a100063928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134262015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1134262015
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.276287159
Short name T191
Test name
Test status
Simulation time 200939964 ps
CPU time 0.89 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:16:57 PM PDT 24
Peak memory 200092 kb
Host smart-64795f93-2dc6-4921-94a7-24ca394c44c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276287159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.276287159
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.452838482
Short name T373
Test name
Test status
Simulation time 1896678445 ps
CPU time 7.21 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:11 PM PDT 24
Peak memory 200352 kb
Host smart-54998957-fde8-4ecf-ac70-8ca801aa229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452838482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.452838482
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.904005465
Short name T22
Test name
Test status
Simulation time 255110132 ps
CPU time 1.51 seconds
Started Jul 28 05:16:55 PM PDT 24
Finished Jul 28 05:16:56 PM PDT 24
Peak memory 200288 kb
Host smart-f95229ae-8382-4498-a9d3-8a758975c84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904005465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.904005465
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3204573723
Short name T384
Test name
Test status
Simulation time 482282593 ps
CPU time 3.11 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:03 PM PDT 24
Peak memory 200252 kb
Host smart-bfef9172-2055-4447-b431-812113e23ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204573723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3204573723
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1382250441
Short name T511
Test name
Test status
Simulation time 354872256 ps
CPU time 2.43 seconds
Started Jul 28 05:17:06 PM PDT 24
Finished Jul 28 05:17:13 PM PDT 24
Peak memory 200104 kb
Host smart-e40d0bbe-6e39-4457-9379-58626f73cb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382250441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1382250441
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2857963155
Short name T535
Test name
Test status
Simulation time 160444160 ps
CPU time 1.28 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:16:57 PM PDT 24
Peak memory 200276 kb
Host smart-5ddea11b-34df-47b0-9744-ec3b5530b976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857963155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2857963155
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.948245008
Short name T536
Test name
Test status
Simulation time 56609403 ps
CPU time 0.74 seconds
Started Jul 28 05:16:25 PM PDT 24
Finished Jul 28 05:16:26 PM PDT 24
Peak memory 199784 kb
Host smart-5d8236e4-31bc-4546-b164-ff27ff5b4768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948245008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.948245008
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1441949006
Short name T262
Test name
Test status
Simulation time 1222918210 ps
CPU time 5.41 seconds
Started Jul 28 05:16:29 PM PDT 24
Finished Jul 28 05:16:34 PM PDT 24
Peak memory 221652 kb
Host smart-e8c7a5fa-a652-4a38-bd1f-f284ea8d720c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441949006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1441949006
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.100584648
Short name T10
Test name
Test status
Simulation time 244200766 ps
CPU time 1.08 seconds
Started Jul 28 05:16:44 PM PDT 24
Finished Jul 28 05:16:45 PM PDT 24
Peak memory 217444 kb
Host smart-93d37250-a5f4-48b6-ac09-1501b9238f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100584648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.100584648
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2092656997
Short name T501
Test name
Test status
Simulation time 83402901 ps
CPU time 0.74 seconds
Started Jul 28 05:16:27 PM PDT 24
Finished Jul 28 05:16:28 PM PDT 24
Peak memory 199892 kb
Host smart-a42f9677-946f-45fe-b57e-105cbb27f5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092656997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2092656997
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2651113487
Short name T175
Test name
Test status
Simulation time 923458956 ps
CPU time 4.75 seconds
Started Jul 28 05:16:32 PM PDT 24
Finished Jul 28 05:16:37 PM PDT 24
Peak memory 200284 kb
Host smart-5d5f4339-690a-4d82-8486-3b85e14aec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651113487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2651113487
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.483453505
Short name T80
Test name
Test status
Simulation time 16587703533 ps
CPU time 25.24 seconds
Started Jul 28 05:16:40 PM PDT 24
Finished Jul 28 05:17:06 PM PDT 24
Peak memory 217280 kb
Host smart-57836336-5729-4e4b-a2a8-9355dad75619
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483453505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.483453505
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3584219036
Short name T386
Test name
Test status
Simulation time 145241841 ps
CPU time 1.1 seconds
Started Jul 28 05:16:29 PM PDT 24
Finished Jul 28 05:16:30 PM PDT 24
Peak memory 200080 kb
Host smart-4005a075-1089-44bc-b478-cb27f2077c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584219036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3584219036
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.4266431843
Short name T377
Test name
Test status
Simulation time 250991803 ps
CPU time 1.43 seconds
Started Jul 28 05:16:27 PM PDT 24
Finished Jul 28 05:16:29 PM PDT 24
Peak memory 200264 kb
Host smart-5232c50a-d6be-4e16-a150-a195483dbbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266431843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4266431843
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3934357844
Short name T222
Test name
Test status
Simulation time 6636418530 ps
CPU time 25.06 seconds
Started Jul 28 05:16:33 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 200616 kb
Host smart-ee21be7b-02cf-407f-a17f-6b97ee6b48a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934357844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3934357844
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3335863961
Short name T455
Test name
Test status
Simulation time 260942162 ps
CPU time 1.88 seconds
Started Jul 28 05:16:29 PM PDT 24
Finished Jul 28 05:16:30 PM PDT 24
Peak memory 200096 kb
Host smart-eef9c9e6-0399-4296-a451-113038c9f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335863961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3335863961
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1566796283
Short name T527
Test name
Test status
Simulation time 91413191 ps
CPU time 0.88 seconds
Started Jul 28 05:16:28 PM PDT 24
Finished Jul 28 05:16:29 PM PDT 24
Peak memory 200024 kb
Host smart-2d9b8744-02d7-4e9f-8fe0-1aa8d6b6bec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566796283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1566796283
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.4261863889
Short name T287
Test name
Test status
Simulation time 83565445 ps
CPU time 0.92 seconds
Started Jul 28 05:16:55 PM PDT 24
Finished Jul 28 05:16:56 PM PDT 24
Peak memory 199864 kb
Host smart-8ab29a64-f4e1-4077-a07d-6170cddefdf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261863889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.4261863889
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3470352850
Short name T30
Test name
Test status
Simulation time 1227754806 ps
CPU time 5.48 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 217716 kb
Host smart-0bf4e1d6-f4af-4635-855e-173e5185f076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470352850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3470352850
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2897493991
Short name T163
Test name
Test status
Simulation time 243939783 ps
CPU time 1.06 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:05 PM PDT 24
Peak memory 217444 kb
Host smart-440c20a1-2506-4f0c-9a22-3286997cac6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897493991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2897493991
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1351457195
Short name T254
Test name
Test status
Simulation time 223875901 ps
CPU time 1.01 seconds
Started Jul 28 05:17:00 PM PDT 24
Finished Jul 28 05:17:01 PM PDT 24
Peak memory 199868 kb
Host smart-0d8e79d4-a9e8-4921-8f8d-a815e8e52600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351457195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1351457195
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3724083302
Short name T110
Test name
Test status
Simulation time 1032157275 ps
CPU time 4.83 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:15 PM PDT 24
Peak memory 200340 kb
Host smart-26a97f6e-bd9e-49cb-bc54-a3441d1794cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724083302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3724083302
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3363407867
Short name T88
Test name
Test status
Simulation time 168566244 ps
CPU time 1.16 seconds
Started Jul 28 05:17:25 PM PDT 24
Finished Jul 28 05:17:26 PM PDT 24
Peak memory 200044 kb
Host smart-7215f361-fea9-41e7-9551-466447f9f9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363407867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3363407867
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2888534074
Short name T507
Test name
Test status
Simulation time 257525021 ps
CPU time 1.47 seconds
Started Jul 28 05:17:03 PM PDT 24
Finished Jul 28 05:17:04 PM PDT 24
Peak memory 200272 kb
Host smart-c076f4e7-2624-4fa8-8914-73f7001c2ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888534074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2888534074
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.283080493
Short name T498
Test name
Test status
Simulation time 2299921703 ps
CPU time 8.87 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:08 PM PDT 24
Peak memory 200440 kb
Host smart-7c8f9541-77d9-400b-9e96-d2896e265ce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283080493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.283080493
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3517805483
Short name T33
Test name
Test status
Simulation time 400942348 ps
CPU time 2.06 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 200032 kb
Host smart-3e730562-f81d-4c9f-9189-6316c8e33a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517805483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3517805483
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.4006793194
Short name T446
Test name
Test status
Simulation time 160413299 ps
CPU time 1.35 seconds
Started Jul 28 05:16:55 PM PDT 24
Finished Jul 28 05:16:56 PM PDT 24
Peak memory 200276 kb
Host smart-c9af9562-2bee-42d4-a09b-307457ea4f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006793194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.4006793194
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3032243659
Short name T215
Test name
Test status
Simulation time 69579884 ps
CPU time 0.72 seconds
Started Jul 28 05:16:52 PM PDT 24
Finished Jul 28 05:16:53 PM PDT 24
Peak memory 199892 kb
Host smart-2990d0ab-0cf5-4f81-85eb-cacf2d21604e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032243659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3032243659
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2506083698
Short name T362
Test name
Test status
Simulation time 1885132571 ps
CPU time 6.84 seconds
Started Jul 28 05:17:02 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 217716 kb
Host smart-c0a5f988-640a-4fff-883a-8dc1061acf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506083698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2506083698
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2097303212
Short name T74
Test name
Test status
Simulation time 244195136 ps
CPU time 1.08 seconds
Started Jul 28 05:16:58 PM PDT 24
Finished Jul 28 05:16:59 PM PDT 24
Peak memory 217368 kb
Host smart-b344deaa-b189-4e6e-9b6f-a4fc1b9fa5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097303212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2097303212
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1814390898
Short name T524
Test name
Test status
Simulation time 157953315 ps
CPU time 0.91 seconds
Started Jul 28 05:16:51 PM PDT 24
Finished Jul 28 05:16:52 PM PDT 24
Peak memory 199796 kb
Host smart-610b5042-b5a6-4466-b9e4-2d0f33b772f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814390898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1814390898
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1712341952
Short name T239
Test name
Test status
Simulation time 1454455191 ps
CPU time 5.15 seconds
Started Jul 28 05:17:09 PM PDT 24
Finished Jul 28 05:17:19 PM PDT 24
Peak memory 200348 kb
Host smart-962dd959-cb62-40e7-8656-04fd0df11f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712341952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1712341952
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3225240025
Short name T478
Test name
Test status
Simulation time 102948167 ps
CPU time 0.98 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:00 PM PDT 24
Peak memory 200064 kb
Host smart-cb30041c-ef37-4fcb-9adb-d31bc110e7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225240025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3225240025
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3904215367
Short name T427
Test name
Test status
Simulation time 109151776 ps
CPU time 1.24 seconds
Started Jul 28 05:16:57 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 200308 kb
Host smart-7e28b0d6-f46c-4b42-aad5-efe98ccd33f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904215367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3904215367
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2226488532
Short name T458
Test name
Test status
Simulation time 3613138413 ps
CPU time 14.73 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:19 PM PDT 24
Peak memory 200380 kb
Host smart-72c388c7-5ec2-47f6-aedc-d1b4db3a089b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226488532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2226488532
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.764436737
Short name T144
Test name
Test status
Simulation time 304119474 ps
CPU time 2.09 seconds
Started Jul 28 05:17:03 PM PDT 24
Finished Jul 28 05:17:05 PM PDT 24
Peak memory 208272 kb
Host smart-e254151a-6589-44d1-9768-ed070a898dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764436737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.764436737
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1585032710
Short name T5
Test name
Test status
Simulation time 170982658 ps
CPU time 1.29 seconds
Started Jul 28 05:17:03 PM PDT 24
Finished Jul 28 05:17:04 PM PDT 24
Peak memory 200320 kb
Host smart-0172579f-c1ec-47b4-84bc-683345a2e1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585032710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1585032710
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.985397291
Short name T332
Test name
Test status
Simulation time 68229852 ps
CPU time 0.81 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:16:57 PM PDT 24
Peak memory 199824 kb
Host smart-90e0cd5d-3c9c-480d-bfd4-c1b08f7fd003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985397291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.985397291
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3312804843
Short name T53
Test name
Test status
Simulation time 1219962026 ps
CPU time 5.32 seconds
Started Jul 28 05:17:02 PM PDT 24
Finished Jul 28 05:17:08 PM PDT 24
Peak memory 221700 kb
Host smart-70fa9915-7e06-4c56-8cd9-5fd01402c6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312804843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3312804843
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2512010133
Short name T472
Test name
Test status
Simulation time 243953682 ps
CPU time 1.1 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 217432 kb
Host smart-d8e4b990-73b9-492f-a9dc-d295ec0fff23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512010133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2512010133
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3724178086
Short name T294
Test name
Test status
Simulation time 120830285 ps
CPU time 0.81 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:00 PM PDT 24
Peak memory 199792 kb
Host smart-e7e9ff2a-1672-4ba9-b057-32b82ab00231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724178086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3724178086
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.847511814
Short name T190
Test name
Test status
Simulation time 1724166527 ps
CPU time 6.43 seconds
Started Jul 28 05:17:08 PM PDT 24
Finished Jul 28 05:17:14 PM PDT 24
Peak memory 200344 kb
Host smart-f4340a22-e9f2-49f8-87cd-fca6c56c07b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847511814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.847511814
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4107661359
Short name T369
Test name
Test status
Simulation time 104531172 ps
CPU time 0.94 seconds
Started Jul 28 05:17:09 PM PDT 24
Finished Jul 28 05:17:11 PM PDT 24
Peak memory 200056 kb
Host smart-92d4c099-d967-48b4-9ec0-f1676a374901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107661359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.4107661359
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.141066436
Short name T374
Test name
Test status
Simulation time 191578186 ps
CPU time 1.41 seconds
Started Jul 28 05:16:57 PM PDT 24
Finished Jul 28 05:16:59 PM PDT 24
Peak memory 200136 kb
Host smart-4a589a00-1ee3-48fa-92eb-5fee3c847072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141066436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.141066436
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1970585163
Short name T333
Test name
Test status
Simulation time 4086778591 ps
CPU time 19.89 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:18 PM PDT 24
Peak memory 200356 kb
Host smart-ab6270f8-a95c-49c5-96e8-7f29a505d884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970585163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1970585163
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2235470837
Short name T409
Test name
Test status
Simulation time 119988525 ps
CPU time 1.57 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 200144 kb
Host smart-4ffe3dd2-437f-448b-999d-5b7313b48ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235470837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2235470837
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.147215991
Short name T12
Test name
Test status
Simulation time 233693834 ps
CPU time 1.41 seconds
Started Jul 28 05:17:06 PM PDT 24
Finished Jul 28 05:17:12 PM PDT 24
Peak memory 200096 kb
Host smart-d9380cb6-4dcd-4d91-8446-1d2999af15ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147215991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.147215991
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1284567437
Short name T388
Test name
Test status
Simulation time 58238418 ps
CPU time 0.73 seconds
Started Jul 28 05:16:53 PM PDT 24
Finished Jul 28 05:16:54 PM PDT 24
Peak memory 199864 kb
Host smart-4630e1fd-fa3f-4882-8573-2278a76c3317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284567437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1284567437
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1711114847
Short name T210
Test name
Test status
Simulation time 246079012 ps
CPU time 1.06 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:06 PM PDT 24
Peak memory 217416 kb
Host smart-2e104418-b4dd-4d9f-8d33-1a197a886ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711114847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1711114847
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3164616587
Short name T452
Test name
Test status
Simulation time 182402958 ps
CPU time 0.83 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:00 PM PDT 24
Peak memory 199884 kb
Host smart-062952b3-bae0-48f7-8894-e473d5ddb63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164616587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3164616587
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1323762333
Short name T339
Test name
Test status
Simulation time 1947873815 ps
CPU time 7.52 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:07 PM PDT 24
Peak memory 200364 kb
Host smart-a4e79766-75da-4987-93ce-6e5e7a24b8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323762333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1323762333
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3340082735
Short name T359
Test name
Test status
Simulation time 105319384 ps
CPU time 1.01 seconds
Started Jul 28 05:16:57 PM PDT 24
Finished Jul 28 05:16:58 PM PDT 24
Peak memory 200332 kb
Host smart-ea3044d5-762f-4b73-b6de-57a434d7936b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340082735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3340082735
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.881516746
Short name T167
Test name
Test status
Simulation time 259196226 ps
CPU time 1.51 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:06 PM PDT 24
Peak memory 200088 kb
Host smart-d3a318e7-f858-4a66-8ebe-331983add891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881516746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.881516746
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.4221283223
Short name T201
Test name
Test status
Simulation time 1819842746 ps
CPU time 7.2 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 200416 kb
Host smart-3e1cb3d6-6d92-468c-a2c7-91abeea4c9e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221283223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.4221283223
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.962586021
Short name T217
Test name
Test status
Simulation time 431864965 ps
CPU time 2.26 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:07 PM PDT 24
Peak memory 208276 kb
Host smart-622be032-c9a7-4413-b109-dc1ce019947f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962586021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.962586021
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2319461626
Short name T352
Test name
Test status
Simulation time 111731168 ps
CPU time 0.99 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:00 PM PDT 24
Peak memory 200044 kb
Host smart-d4eba932-b4cf-40ec-8184-186dc8866198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319461626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2319461626
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1492586823
Short name T236
Test name
Test status
Simulation time 62110245 ps
CPU time 0.73 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 199868 kb
Host smart-057f7b2b-4c03-4a7e-b808-465a02b77b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492586823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1492586823
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1051747482
Short name T499
Test name
Test status
Simulation time 1217373401 ps
CPU time 5.31 seconds
Started Jul 28 05:16:57 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 217404 kb
Host smart-34cd8ae6-ba57-40d5-889f-ccbe6f126a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051747482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1051747482
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1080023271
Short name T34
Test name
Test status
Simulation time 244749364 ps
CPU time 1.07 seconds
Started Jul 28 05:16:58 PM PDT 24
Finished Jul 28 05:16:59 PM PDT 24
Peak memory 217388 kb
Host smart-0fb1cd19-13a7-47e2-a6bf-0f791a585512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080023271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1080023271
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2084554565
Short name T392
Test name
Test status
Simulation time 201690591 ps
CPU time 0.9 seconds
Started Jul 28 05:16:58 PM PDT 24
Finished Jul 28 05:16:59 PM PDT 24
Peak memory 199828 kb
Host smart-c7edff9a-78df-4eaf-9228-9150cf3143e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084554565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2084554565
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.370053388
Short name T522
Test name
Test status
Simulation time 2093973055 ps
CPU time 7.15 seconds
Started Jul 28 05:17:09 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 200364 kb
Host smart-e806f330-a150-44c7-bb70-2a2a5667578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370053388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.370053388
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1170861568
Short name T259
Test name
Test status
Simulation time 185147643 ps
CPU time 1.2 seconds
Started Jul 28 05:17:00 PM PDT 24
Finished Jul 28 05:17:01 PM PDT 24
Peak memory 200032 kb
Host smart-c43302a4-0df1-47a1-8f53-1e4db7e5ad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170861568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1170861568
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1672236667
Short name T211
Test name
Test status
Simulation time 118915573 ps
CPU time 1.14 seconds
Started Jul 28 05:17:06 PM PDT 24
Finished Jul 28 05:17:07 PM PDT 24
Peak memory 200284 kb
Host smart-9d82e031-9ca6-425f-ac30-b53a8cb5c37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672236667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1672236667
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3868817774
Short name T156
Test name
Test status
Simulation time 3853064814 ps
CPU time 18.05 seconds
Started Jul 28 05:16:58 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 208648 kb
Host smart-fcd0e20e-c7c9-42fc-96c6-48e0ec08d257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868817774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3868817774
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3231788374
Short name T203
Test name
Test status
Simulation time 122914384 ps
CPU time 1.46 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 200072 kb
Host smart-78c9142f-ad29-4bbb-b70d-892a52384414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231788374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3231788374
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2829808831
Short name T532
Test name
Test status
Simulation time 137374645 ps
CPU time 1.09 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:16:57 PM PDT 24
Peak memory 200064 kb
Host smart-3e74c642-f4f5-44f0-a541-ba7a1b55720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829808831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2829808831
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2364586884
Short name T357
Test name
Test status
Simulation time 93318050 ps
CPU time 0.86 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:06 PM PDT 24
Peak memory 199892 kb
Host smart-f61614a1-7ae2-46f4-b335-be7c96c46bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364586884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2364586884
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3146978894
Short name T435
Test name
Test status
Simulation time 1901347066 ps
CPU time 6.88 seconds
Started Jul 28 05:17:03 PM PDT 24
Finished Jul 28 05:17:10 PM PDT 24
Peak memory 221740 kb
Host smart-7be47d78-8e5b-4d77-9fd2-fc8aef1ed542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146978894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3146978894
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1306691504
Short name T83
Test name
Test status
Simulation time 243741557 ps
CPU time 1.01 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:05 PM PDT 24
Peak memory 217412 kb
Host smart-6dd48eb2-eedd-442b-b5c3-5c6121ad0ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306691504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1306691504
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1453665265
Short name T16
Test name
Test status
Simulation time 235776140 ps
CPU time 0.93 seconds
Started Jul 28 05:16:54 PM PDT 24
Finished Jul 28 05:16:55 PM PDT 24
Peak memory 199812 kb
Host smart-4c7125ae-73b3-477d-84af-c0e668622b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453665265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1453665265
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2449774426
Short name T130
Test name
Test status
Simulation time 1012210141 ps
CPU time 4.96 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:17:01 PM PDT 24
Peak memory 200348 kb
Host smart-8a0cefe7-b279-40ac-92b3-84a7b9f3980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449774426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2449774426
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3182858837
Short name T456
Test name
Test status
Simulation time 167857904 ps
CPU time 1.16 seconds
Started Jul 28 05:17:08 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 200064 kb
Host smart-2bc3936f-b2ec-43ab-8c49-c1c44a62680c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182858837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3182858837
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2286404311
Short name T318
Test name
Test status
Simulation time 116112770 ps
CPU time 1.16 seconds
Started Jul 28 05:16:55 PM PDT 24
Finished Jul 28 05:16:56 PM PDT 24
Peak memory 200328 kb
Host smart-87984b41-fdf7-4721-873e-d27c2f120f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286404311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2286404311
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1825136794
Short name T225
Test name
Test status
Simulation time 9334151304 ps
CPU time 34.3 seconds
Started Jul 28 05:17:10 PM PDT 24
Finished Jul 28 05:17:45 PM PDT 24
Peak memory 200328 kb
Host smart-ac876696-1d3e-4bb1-bc50-d9414a7df431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825136794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1825136794
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1993867446
Short name T99
Test name
Test status
Simulation time 133952387 ps
CPU time 1.69 seconds
Started Jul 28 05:17:08 PM PDT 24
Finished Jul 28 05:17:10 PM PDT 24
Peak memory 200076 kb
Host smart-5359411c-e0d1-40c1-8663-94dbeeec3d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993867446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1993867446
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.157316200
Short name T189
Test name
Test status
Simulation time 167289589 ps
CPU time 1.11 seconds
Started Jul 28 05:16:55 PM PDT 24
Finished Jul 28 05:16:57 PM PDT 24
Peak memory 200096 kb
Host smart-f98df86c-98ef-423c-8d18-4fc02a43a123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157316200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.157316200
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1174731588
Short name T193
Test name
Test status
Simulation time 81874057 ps
CPU time 0.75 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:05 PM PDT 24
Peak memory 199916 kb
Host smart-e98f61ee-ee14-4590-a615-be2e76a87082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174731588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1174731588
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.4244138035
Short name T503
Test name
Test status
Simulation time 1232994177 ps
CPU time 5.5 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:11 PM PDT 24
Peak memory 221528 kb
Host smart-605aba90-0a00-4b12-8200-9d8818d9c188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244138035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.4244138035
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1177387374
Short name T261
Test name
Test status
Simulation time 243830293 ps
CPU time 1.08 seconds
Started Jul 28 05:17:17 PM PDT 24
Finished Jul 28 05:17:19 PM PDT 24
Peak memory 217464 kb
Host smart-8c07c708-2f10-44ce-865f-d049e0d329f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177387374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1177387374
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3958628571
Short name T266
Test name
Test status
Simulation time 187410037 ps
CPU time 0.9 seconds
Started Jul 28 05:17:00 PM PDT 24
Finished Jul 28 05:17:01 PM PDT 24
Peak memory 199872 kb
Host smart-17ac695d-2836-4dd7-ba4b-0ddf3d4e5da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958628571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3958628571
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1165722409
Short name T21
Test name
Test status
Simulation time 597986004 ps
CPU time 3.45 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:17:00 PM PDT 24
Peak memory 200236 kb
Host smart-1ccaf0c6-faba-4029-bf68-df63b29ba9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165722409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1165722409
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3424382316
Short name T86
Test name
Test status
Simulation time 173944510 ps
CPU time 1.21 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:12 PM PDT 24
Peak memory 200060 kb
Host smart-07e095ec-ffa6-426c-b615-ae01d1ce12df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424382316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3424382316
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.146734436
Short name T395
Test name
Test status
Simulation time 123488831 ps
CPU time 1.22 seconds
Started Jul 28 05:16:55 PM PDT 24
Finished Jul 28 05:16:56 PM PDT 24
Peak memory 200304 kb
Host smart-51be5768-4313-43e3-ac49-d176fe5779af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146734436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.146734436
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1938573770
Short name T209
Test name
Test status
Simulation time 7194830825 ps
CPU time 24.94 seconds
Started Jul 28 05:17:00 PM PDT 24
Finished Jul 28 05:17:25 PM PDT 24
Peak memory 210572 kb
Host smart-b4300cdf-1fbc-45f2-b31c-531065b76ecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938573770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1938573770
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.722277914
Short name T461
Test name
Test status
Simulation time 379500975 ps
CPU time 2.38 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 200064 kb
Host smart-08cd7795-79fb-4084-92c4-2f5b919b3e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722277914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.722277914
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3337748165
Short name T146
Test name
Test status
Simulation time 97705507 ps
CPU time 0.89 seconds
Started Jul 28 05:17:00 PM PDT 24
Finished Jul 28 05:17:01 PM PDT 24
Peak memory 200092 kb
Host smart-abbe7d88-35cf-4b20-8f05-c9229813a416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337748165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3337748165
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.714870340
Short name T151
Test name
Test status
Simulation time 87856563 ps
CPU time 0.81 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:12 PM PDT 24
Peak memory 199780 kb
Host smart-198adfc6-5bda-4783-b3d9-3688897ede15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714870340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.714870340
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.619751176
Short name T364
Test name
Test status
Simulation time 2175836978 ps
CPU time 7.97 seconds
Started Jul 28 05:17:17 PM PDT 24
Finished Jul 28 05:17:30 PM PDT 24
Peak memory 217076 kb
Host smart-f01d48e0-bab5-443c-805d-77b5bbeaf04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619751176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.619751176
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2766031957
Short name T519
Test name
Test status
Simulation time 244148529 ps
CPU time 1.12 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 217468 kb
Host smart-045b5926-1502-4560-8d79-0646f42f7d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766031957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2766031957
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.889632020
Short name T497
Test name
Test status
Simulation time 114982344 ps
CPU time 0.74 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:06 PM PDT 24
Peak memory 199884 kb
Host smart-dde0b3c7-e491-4791-b6bf-c211382816a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889632020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.889632020
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2776474199
Short name T355
Test name
Test status
Simulation time 1101208869 ps
CPU time 5.09 seconds
Started Jul 28 05:17:00 PM PDT 24
Finished Jul 28 05:17:06 PM PDT 24
Peak memory 200328 kb
Host smart-5ae14628-9636-4d12-b3fc-8fa1b50c71b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776474199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2776474199
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1188937894
Short name T321
Test name
Test status
Simulation time 107440575 ps
CPU time 0.98 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:06 PM PDT 24
Peak memory 200076 kb
Host smart-ca6871a2-da56-4f38-8989-06c9382fc27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188937894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1188937894
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1800285652
Short name T267
Test name
Test status
Simulation time 110491186 ps
CPU time 1.14 seconds
Started Jul 28 05:17:08 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 200268 kb
Host smart-8a85a908-3d54-469b-8c21-09c57af1b8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800285652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1800285652
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1770409864
Short name T197
Test name
Test status
Simulation time 3264010252 ps
CPU time 15.5 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:15 PM PDT 24
Peak memory 200392 kb
Host smart-7dcc3136-fe3e-4297-a315-eccbfa81591f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770409864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1770409864
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1801542702
Short name T396
Test name
Test status
Simulation time 127948029 ps
CPU time 1.58 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:05 PM PDT 24
Peak memory 208300 kb
Host smart-2f18a2a0-8fb9-4caf-8785-2b1d15376874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801542702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1801542702
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2132628381
Short name T214
Test name
Test status
Simulation time 108373744 ps
CPU time 1.01 seconds
Started Jul 28 05:17:09 PM PDT 24
Finished Jul 28 05:17:10 PM PDT 24
Peak memory 200112 kb
Host smart-96ce008f-020a-4c3e-ba9e-34cd7f798237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132628381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2132628381
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.235369331
Short name T454
Test name
Test status
Simulation time 78992884 ps
CPU time 0.83 seconds
Started Jul 28 05:17:10 PM PDT 24
Finished Jul 28 05:17:11 PM PDT 24
Peak memory 199904 kb
Host smart-a21940bc-b55f-4767-8134-5e732e69fb86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235369331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.235369331
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2888855059
Short name T283
Test name
Test status
Simulation time 2365469335 ps
CPU time 8.55 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:20 PM PDT 24
Peak memory 217036 kb
Host smart-40cb135a-978b-4e5b-b342-8d160bb2f2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888855059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2888855059
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3888863474
Short name T186
Test name
Test status
Simulation time 244901847 ps
CPU time 1.11 seconds
Started Jul 28 05:17:10 PM PDT 24
Finished Jul 28 05:17:12 PM PDT 24
Peak memory 217504 kb
Host smart-2322c795-73fb-4417-9e41-fa23f0779bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888863474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3888863474
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3134365754
Short name T415
Test name
Test status
Simulation time 1856540835 ps
CPU time 7.58 seconds
Started Jul 28 05:17:10 PM PDT 24
Finished Jul 28 05:17:17 PM PDT 24
Peak memory 200328 kb
Host smart-91572a2a-f1c4-425c-b0d8-a2ec8471323d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134365754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3134365754
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1515500133
Short name T44
Test name
Test status
Simulation time 170116422 ps
CPU time 1.17 seconds
Started Jul 28 05:17:13 PM PDT 24
Finished Jul 28 05:17:14 PM PDT 24
Peak memory 200024 kb
Host smart-0a4dd396-8f69-40a6-8b50-51ec97b41960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515500133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1515500133
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1540379007
Short name T188
Test name
Test status
Simulation time 116821272 ps
CPU time 1.13 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:05 PM PDT 24
Peak memory 200256 kb
Host smart-e0589f89-5ef1-48cf-82a6-8c598e27ca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540379007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1540379007
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3201390629
Short name T493
Test name
Test status
Simulation time 4244185211 ps
CPU time 18.33 seconds
Started Jul 28 05:17:08 PM PDT 24
Finished Jul 28 05:17:26 PM PDT 24
Peak memory 208760 kb
Host smart-5966cbcf-f4cc-435b-9170-37a744d6d69d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201390629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3201390629
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.4190791267
Short name T411
Test name
Test status
Simulation time 122328723 ps
CPU time 1.56 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 200096 kb
Host smart-588c18fa-1334-449d-bc85-d8daba0ace70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190791267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.4190791267
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.773800987
Short name T149
Test name
Test status
Simulation time 165440366 ps
CPU time 1.31 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:07 PM PDT 24
Peak memory 200292 kb
Host smart-947ab3ba-ee38-47ff-91f6-7d86f9a41033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773800987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.773800987
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2594342430
Short name T78
Test name
Test status
Simulation time 67816449 ps
CPU time 0.76 seconds
Started Jul 28 05:17:04 PM PDT 24
Finished Jul 28 05:17:04 PM PDT 24
Peak memory 199856 kb
Host smart-f8e1e347-d44f-4eca-ade6-099e3af51881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594342430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2594342430
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3858279321
Short name T26
Test name
Test status
Simulation time 1890968531 ps
CPU time 6.84 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:18 PM PDT 24
Peak memory 221732 kb
Host smart-d692c8be-2c25-4399-ab79-610b38fb9c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858279321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3858279321
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2773970000
Short name T208
Test name
Test status
Simulation time 244660441 ps
CPU time 1.09 seconds
Started Jul 28 05:17:08 PM PDT 24
Finished Jul 28 05:17:10 PM PDT 24
Peak memory 217400 kb
Host smart-189c6f49-a23e-4d11-9913-7bb322929e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773970000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2773970000
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3040350816
Short name T244
Test name
Test status
Simulation time 143151920 ps
CPU time 0.88 seconds
Started Jul 28 05:17:01 PM PDT 24
Finished Jul 28 05:17:02 PM PDT 24
Peak memory 199700 kb
Host smart-5bc55594-4b8f-4cdb-94db-8cde98730202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040350816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3040350816
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3049856702
Short name T168
Test name
Test status
Simulation time 1303799908 ps
CPU time 5.1 seconds
Started Jul 28 05:17:14 PM PDT 24
Finished Jul 28 05:17:19 PM PDT 24
Peak memory 200380 kb
Host smart-c2e5916d-4eb9-466d-8e0d-c7057fbf6c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049856702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3049856702
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4167292613
Short name T418
Test name
Test status
Simulation time 106525574 ps
CPU time 1 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 200056 kb
Host smart-7e42ae51-8f31-44e4-b168-3adeacbe2ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167292613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4167292613
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.632961585
Short name T480
Test name
Test status
Simulation time 112991938 ps
CPU time 1.19 seconds
Started Jul 28 05:17:03 PM PDT 24
Finished Jul 28 05:17:04 PM PDT 24
Peak memory 200208 kb
Host smart-25818a8e-f479-4ca7-9364-d024996a2005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632961585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.632961585
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3278922923
Short name T356
Test name
Test status
Simulation time 4000929102 ps
CPU time 16.74 seconds
Started Jul 28 05:17:06 PM PDT 24
Finished Jul 28 05:17:23 PM PDT 24
Peak memory 200384 kb
Host smart-1244f832-5244-4794-a24b-81a5ab28ec14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278922923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3278922923
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3096000555
Short name T94
Test name
Test status
Simulation time 478744873 ps
CPU time 2.44 seconds
Started Jul 28 05:17:19 PM PDT 24
Finished Jul 28 05:17:21 PM PDT 24
Peak memory 199984 kb
Host smart-cccb68b5-4c0d-4f57-908d-eb914c38ee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096000555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3096000555
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1601633106
Short name T471
Test name
Test status
Simulation time 233747293 ps
CPU time 1.44 seconds
Started Jul 28 05:17:08 PM PDT 24
Finished Jul 28 05:17:10 PM PDT 24
Peak memory 200008 kb
Host smart-8dbf723a-5fd7-4716-be1e-bd8fa0ceed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601633106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1601633106
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3813724292
Short name T82
Test name
Test status
Simulation time 68948764 ps
CPU time 0.73 seconds
Started Jul 28 05:16:40 PM PDT 24
Finished Jul 28 05:16:41 PM PDT 24
Peak memory 199908 kb
Host smart-a20d8838-7e11-43fc-ab89-3cf1a92237bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813724292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3813724292
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3324138422
Short name T28
Test name
Test status
Simulation time 2162175457 ps
CPU time 7.87 seconds
Started Jul 28 05:16:44 PM PDT 24
Finished Jul 28 05:16:52 PM PDT 24
Peak memory 217832 kb
Host smart-23015697-ce4a-4396-960a-bfab577af7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324138422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3324138422
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2115041639
Short name T306
Test name
Test status
Simulation time 243945970 ps
CPU time 1.08 seconds
Started Jul 28 05:16:29 PM PDT 24
Finished Jul 28 05:16:30 PM PDT 24
Peak memory 217364 kb
Host smart-963a3b2c-0d44-4cc4-b106-fe2bd9a9f8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115041639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2115041639
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.894922299
Short name T165
Test name
Test status
Simulation time 199856213 ps
CPU time 0.92 seconds
Started Jul 28 05:16:36 PM PDT 24
Finished Jul 28 05:16:37 PM PDT 24
Peak memory 199660 kb
Host smart-6b8e68c1-f53b-478b-a36e-09ec5ebd5767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894922299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.894922299
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2784526571
Short name T514
Test name
Test status
Simulation time 1192871794 ps
CPU time 4.65 seconds
Started Jul 28 05:16:26 PM PDT 24
Finished Jul 28 05:16:31 PM PDT 24
Peak memory 200348 kb
Host smart-320a5ca0-e898-4554-a046-6d94884acd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784526571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2784526571
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3430335091
Short name T4
Test name
Test status
Simulation time 181485566 ps
CPU time 1.16 seconds
Started Jul 28 05:16:28 PM PDT 24
Finished Jul 28 05:16:30 PM PDT 24
Peak memory 200020 kb
Host smart-3b7b1e22-eddb-4331-969f-b520be273232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430335091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3430335091
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.4224065107
Short name T289
Test name
Test status
Simulation time 189776225 ps
CPU time 1.37 seconds
Started Jul 28 05:16:39 PM PDT 24
Finished Jul 28 05:16:41 PM PDT 24
Peak memory 200304 kb
Host smart-f7142b25-9818-423e-a922-6b0610c8ce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224065107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.4224065107
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1165611040
Short name T310
Test name
Test status
Simulation time 2236668221 ps
CPU time 9.26 seconds
Started Jul 28 05:16:29 PM PDT 24
Finished Jul 28 05:16:39 PM PDT 24
Peak memory 200616 kb
Host smart-cfe9befe-54cf-4c76-8bb4-ad4416314b26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165611040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1165611040
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1112428469
Short name T228
Test name
Test status
Simulation time 120274836 ps
CPU time 1.52 seconds
Started Jul 28 05:16:29 PM PDT 24
Finished Jul 28 05:16:31 PM PDT 24
Peak memory 200112 kb
Host smart-6e6dc240-c9a2-41ad-aaeb-7ef03af5c469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112428469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1112428469
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1080617883
Short name T523
Test name
Test status
Simulation time 256874766 ps
CPU time 1.41 seconds
Started Jul 28 05:16:44 PM PDT 24
Finished Jul 28 05:16:45 PM PDT 24
Peak memory 200304 kb
Host smart-b141902d-4f4f-46cb-8667-3ea7483e05ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080617883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1080617883
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3614004662
Short name T422
Test name
Test status
Simulation time 80622713 ps
CPU time 0.83 seconds
Started Jul 28 05:17:02 PM PDT 24
Finished Jul 28 05:17:03 PM PDT 24
Peak memory 199756 kb
Host smart-f96841bc-ca66-4421-9584-9e8c0124ef0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614004662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3614004662
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3605719824
Short name T307
Test name
Test status
Simulation time 2322504564 ps
CPU time 7.64 seconds
Started Jul 28 05:17:16 PM PDT 24
Finished Jul 28 05:17:24 PM PDT 24
Peak memory 221476 kb
Host smart-a0680f3f-9b02-45e4-a308-cd5fe6d5b174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605719824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3605719824
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2596645232
Short name T145
Test name
Test status
Simulation time 254083014 ps
CPU time 1.03 seconds
Started Jul 28 05:17:14 PM PDT 24
Finished Jul 28 05:17:15 PM PDT 24
Peak memory 217476 kb
Host smart-e2cec87f-6767-47ca-80e3-bc176523e38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596645232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2596645232
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2835138779
Short name T7
Test name
Test status
Simulation time 214575409 ps
CPU time 0.91 seconds
Started Jul 28 05:17:16 PM PDT 24
Finished Jul 28 05:17:17 PM PDT 24
Peak memory 199820 kb
Host smart-57fadbc9-4be5-4550-a64d-f8acdfe10e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835138779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2835138779
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1500741501
Short name T107
Test name
Test status
Simulation time 942657717 ps
CPU time 4.56 seconds
Started Jul 28 05:17:12 PM PDT 24
Finished Jul 28 05:17:17 PM PDT 24
Peak memory 200336 kb
Host smart-886c4333-f7d9-4430-89ed-923520d43008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500741501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1500741501
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1397770238
Short name T315
Test name
Test status
Simulation time 152412695 ps
CPU time 1.14 seconds
Started Jul 28 05:17:13 PM PDT 24
Finished Jul 28 05:17:14 PM PDT 24
Peak memory 200084 kb
Host smart-448ea4b9-2a12-41f9-bc74-735ec22db4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397770238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1397770238
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.208615671
Short name T246
Test name
Test status
Simulation time 112406593 ps
CPU time 1.18 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:08 PM PDT 24
Peak memory 200348 kb
Host smart-d144e871-856f-40a6-b901-08d2cde86106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208615671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.208615671
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.826651669
Short name T112
Test name
Test status
Simulation time 10510194851 ps
CPU time 35.16 seconds
Started Jul 28 05:16:59 PM PDT 24
Finished Jul 28 05:17:34 PM PDT 24
Peak memory 209412 kb
Host smart-8c55f12d-a38f-4ed0-8983-d5796183b130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826651669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.826651669
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2847498504
Short name T506
Test name
Test status
Simulation time 331486746 ps
CPU time 2.02 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:13 PM PDT 24
Peak memory 200012 kb
Host smart-b0a2fc7c-8135-4c26-b8d2-d7d25453f8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847498504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2847498504
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.758150921
Short name T216
Test name
Test status
Simulation time 287578668 ps
CPU time 1.46 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:07 PM PDT 24
Peak memory 200192 kb
Host smart-10838be3-aa9e-4962-8e87-1398a3ec4f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758150921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.758150921
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2984051738
Short name T154
Test name
Test status
Simulation time 72156936 ps
CPU time 0.75 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:08 PM PDT 24
Peak memory 199872 kb
Host smart-36d06752-a2f3-4a87-a15a-507b8e3fbe7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984051738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2984051738
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1027481086
Short name T60
Test name
Test status
Simulation time 1226752209 ps
CPU time 5.31 seconds
Started Jul 28 05:17:10 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 217684 kb
Host smart-7bf2075f-4902-4588-8281-a987f69acefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027481086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1027481086
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3869624516
Short name T464
Test name
Test status
Simulation time 244621720 ps
CPU time 1.16 seconds
Started Jul 28 05:17:14 PM PDT 24
Finished Jul 28 05:17:21 PM PDT 24
Peak memory 217420 kb
Host smart-bb019ee7-b53d-405b-a580-53b734adc754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869624516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3869624516
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.124932579
Short name T278
Test name
Test status
Simulation time 189738111 ps
CPU time 0.88 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:06 PM PDT 24
Peak memory 199872 kb
Host smart-effc092a-7689-4a6a-86b2-49dbb93d36ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124932579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.124932579
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2834777018
Short name T360
Test name
Test status
Simulation time 880036520 ps
CPU time 4.39 seconds
Started Jul 28 05:17:05 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 200200 kb
Host smart-910b08e1-18a9-4713-9768-ab224951ac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834777018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2834777018
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.662507133
Short name T419
Test name
Test status
Simulation time 161611141 ps
CPU time 1.15 seconds
Started Jul 28 05:17:14 PM PDT 24
Finished Jul 28 05:17:15 PM PDT 24
Peak memory 200024 kb
Host smart-5162978f-21b0-4c64-abac-bebc7273d2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662507133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.662507133
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.608863714
Short name T487
Test name
Test status
Simulation time 190190139 ps
CPU time 1.4 seconds
Started Jul 28 05:17:09 PM PDT 24
Finished Jul 28 05:17:11 PM PDT 24
Peak memory 200304 kb
Host smart-23b9afda-a9dc-479d-a9c0-3aa0e43e232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608863714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.608863714
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.4010670580
Short name T174
Test name
Test status
Simulation time 2815306894 ps
CPU time 10.63 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:18 PM PDT 24
Peak memory 200428 kb
Host smart-acf6d57c-cf4d-4aec-929c-fa523e49d7d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010670580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4010670580
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3745885902
Short name T450
Test name
Test status
Simulation time 132992512 ps
CPU time 1.73 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:13 PM PDT 24
Peak memory 199980 kb
Host smart-6aefe857-478e-4984-967c-937529cfc875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745885902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3745885902
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3969040136
Short name T274
Test name
Test status
Simulation time 105075196 ps
CPU time 0.86 seconds
Started Jul 28 05:17:08 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 200080 kb
Host smart-378af56c-47f9-4c67-9c67-1f6ac6ffd5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969040136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3969040136
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1951020427
Short name T230
Test name
Test status
Simulation time 54402200 ps
CPU time 0.71 seconds
Started Jul 28 05:17:09 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 199792 kb
Host smart-fcc85f34-263e-4f2a-9651-38e2c86b55d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951020427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1951020427
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3272789502
Short name T512
Test name
Test status
Simulation time 1232041910 ps
CPU time 5.23 seconds
Started Jul 28 05:17:09 PM PDT 24
Finished Jul 28 05:17:15 PM PDT 24
Peak memory 217708 kb
Host smart-449a6faa-4e8f-4f83-a12b-090ea862de51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272789502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3272789502
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1448599381
Short name T37
Test name
Test status
Simulation time 243787977 ps
CPU time 1.04 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:12 PM PDT 24
Peak memory 217276 kb
Host smart-8c9bb6e6-ee03-42b2-8d9d-002f70f1fff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448599381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1448599381
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1076852772
Short name T232
Test name
Test status
Simulation time 191441598 ps
CPU time 0.85 seconds
Started Jul 28 05:17:28 PM PDT 24
Finished Jul 28 05:17:29 PM PDT 24
Peak memory 199864 kb
Host smart-d1c6d974-e915-405b-a65b-e8df81bf84bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076852772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1076852772
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1291618643
Short name T147
Test name
Test status
Simulation time 906171825 ps
CPU time 5 seconds
Started Jul 28 05:17:17 PM PDT 24
Finished Jul 28 05:17:22 PM PDT 24
Peak memory 200256 kb
Host smart-93d75a8b-a15a-4753-bb7e-8c64acd994d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291618643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1291618643
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3589755174
Short name T1
Test name
Test status
Simulation time 135493211 ps
CPU time 1.04 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:08 PM PDT 24
Peak memory 200332 kb
Host smart-7f415c58-6881-4563-811b-4a14b5fb679b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589755174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3589755174
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2159917772
Short name T331
Test name
Test status
Simulation time 113355191 ps
CPU time 1.17 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:12 PM PDT 24
Peak memory 200192 kb
Host smart-13759c1e-a245-44fd-a445-d9b9423f1076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159917772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2159917772
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1210091437
Short name T84
Test name
Test status
Simulation time 6952092167 ps
CPU time 25.31 seconds
Started Jul 28 05:17:20 PM PDT 24
Finished Jul 28 05:17:45 PM PDT 24
Peak memory 208512 kb
Host smart-36fb8052-ec19-47ce-9b88-15c36e8935e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210091437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1210091437
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2108391763
Short name T253
Test name
Test status
Simulation time 138914931 ps
CPU time 1.7 seconds
Started Jul 28 05:17:25 PM PDT 24
Finished Jul 28 05:17:27 PM PDT 24
Peak memory 200040 kb
Host smart-497d0d2c-7fd8-43f0-8712-d724a28c1ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108391763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2108391763
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3171836118
Short name T423
Test name
Test status
Simulation time 168833566 ps
CPU time 1.31 seconds
Started Jul 28 05:17:32 PM PDT 24
Finished Jul 28 05:17:34 PM PDT 24
Peak memory 200284 kb
Host smart-103378c3-e65c-4bd6-b9f5-ea41194fac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171836118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3171836118
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2248378696
Short name T537
Test name
Test status
Simulation time 79654976 ps
CPU time 0.82 seconds
Started Jul 28 05:17:13 PM PDT 24
Finished Jul 28 05:17:13 PM PDT 24
Peak memory 199856 kb
Host smart-7c671e58-4d07-4086-974b-a2d98d0da91c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248378696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2248378696
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2811704193
Short name T56
Test name
Test status
Simulation time 2361382089 ps
CPU time 8.46 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 221748 kb
Host smart-69a7d1e5-efea-4009-a582-73407eddd5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811704193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2811704193
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2094388973
Short name T405
Test name
Test status
Simulation time 243653109 ps
CPU time 1.14 seconds
Started Jul 28 05:17:12 PM PDT 24
Finished Jul 28 05:17:13 PM PDT 24
Peak memory 217356 kb
Host smart-df01f28e-8c4f-409b-8ac0-8766709cc831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094388973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2094388973
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3268755180
Short name T447
Test name
Test status
Simulation time 183117071 ps
CPU time 0.84 seconds
Started Jul 28 05:17:15 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 199804 kb
Host smart-0b15fb9b-bb4b-427f-8f41-90d5d9ffc604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268755180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3268755180
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.14688288
Short name T379
Test name
Test status
Simulation time 1213121799 ps
CPU time 4.99 seconds
Started Jul 28 05:17:29 PM PDT 24
Finished Jul 28 05:17:34 PM PDT 24
Peak memory 200400 kb
Host smart-da7c342a-090b-45e1-bddb-8627eacdaacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14688288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.14688288
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.31605886
Short name T286
Test name
Test status
Simulation time 103355348 ps
CPU time 1.09 seconds
Started Jul 28 05:17:17 PM PDT 24
Finished Jul 28 05:17:18 PM PDT 24
Peak memory 199984 kb
Host smart-34dfc730-2ecf-435d-bd8c-fc8841316284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31605886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.31605886
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2149478762
Short name T205
Test name
Test status
Simulation time 121654594 ps
CPU time 1.25 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:36 PM PDT 24
Peak memory 200248 kb
Host smart-b9305c9c-ccd9-44be-9bb6-882b2856576e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149478762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2149478762
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3391965604
Short name T402
Test name
Test status
Simulation time 3161964451 ps
CPU time 13.77 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:21 PM PDT 24
Peak memory 200416 kb
Host smart-a0d1a5f3-5305-4808-8688-396d6d792465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391965604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3391965604
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1970364813
Short name T378
Test name
Test status
Simulation time 516282108 ps
CPU time 2.66 seconds
Started Jul 28 05:17:09 PM PDT 24
Finished Jul 28 05:17:12 PM PDT 24
Peak memory 200008 kb
Host smart-3f95ff0e-be84-491e-ab49-cd79eef15a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970364813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1970364813
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.4129819772
Short name T416
Test name
Test status
Simulation time 92439215 ps
CPU time 0.88 seconds
Started Jul 28 05:17:19 PM PDT 24
Finished Jul 28 05:17:20 PM PDT 24
Peak memory 200008 kb
Host smart-a5df2edb-77f3-4f45-afe9-54aba200cfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129819772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.4129819772
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2358314297
Short name T238
Test name
Test status
Simulation time 68988499 ps
CPU time 0.8 seconds
Started Jul 28 05:17:17 PM PDT 24
Finished Jul 28 05:17:18 PM PDT 24
Peak memory 199864 kb
Host smart-50382631-f777-4d21-ba89-17c603c1ed44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358314297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2358314297
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1122716449
Short name T61
Test name
Test status
Simulation time 2161213037 ps
CPU time 7.94 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:24 PM PDT 24
Peak memory 217680 kb
Host smart-2bf45ace-0d00-478d-a002-bec3ea471fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122716449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1122716449
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1523990627
Short name T247
Test name
Test status
Simulation time 244234453 ps
CPU time 1.05 seconds
Started Jul 28 05:17:13 PM PDT 24
Finished Jul 28 05:17:14 PM PDT 24
Peak memory 217496 kb
Host smart-345af362-8b8b-4786-88a0-fa2c93b950e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523990627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1523990627
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.4293091575
Short name T196
Test name
Test status
Simulation time 109235307 ps
CPU time 0.78 seconds
Started Jul 28 05:17:10 PM PDT 24
Finished Jul 28 05:17:11 PM PDT 24
Peak memory 199816 kb
Host smart-d031eff5-47f4-4067-a7ce-0c8eeffd3cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293091575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.4293091575
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2171985998
Short name T295
Test name
Test status
Simulation time 970172198 ps
CPU time 4.88 seconds
Started Jul 28 05:17:27 PM PDT 24
Finished Jul 28 05:17:32 PM PDT 24
Peak memory 200328 kb
Host smart-2c648ac0-7fd0-40ea-84bb-6ee929b21f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171985998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2171985998
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.4009987215
Short name T153
Test name
Test status
Simulation time 102531790 ps
CPU time 1.04 seconds
Started Jul 28 05:17:02 PM PDT 24
Finished Jul 28 05:17:03 PM PDT 24
Peak memory 200060 kb
Host smart-9abcdfdf-3e80-4b9f-a4ab-81afa822c8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009987215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.4009987215
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2551207656
Short name T358
Test name
Test status
Simulation time 124195098 ps
CPU time 1.19 seconds
Started Jul 28 05:17:18 PM PDT 24
Finished Jul 28 05:17:20 PM PDT 24
Peak memory 200344 kb
Host smart-a7a6e279-9548-4ef7-a831-ab0b73b4026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551207656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2551207656
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.571586231
Short name T270
Test name
Test status
Simulation time 128282022 ps
CPU time 0.94 seconds
Started Jul 28 05:17:19 PM PDT 24
Finished Jul 28 05:17:20 PM PDT 24
Peak memory 200080 kb
Host smart-5faf75fe-26fc-4e81-9dbf-b9b341cd517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571586231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.571586231
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2029088398
Short name T221
Test name
Test status
Simulation time 66610657 ps
CPU time 0.75 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:31 PM PDT 24
Peak memory 199860 kb
Host smart-23a40441-4835-4df5-ab58-b62b365bd772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029088398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2029088398
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1506931466
Short name T393
Test name
Test status
Simulation time 2366126815 ps
CPU time 8 seconds
Started Jul 28 05:17:12 PM PDT 24
Finished Jul 28 05:17:20 PM PDT 24
Peak memory 221740 kb
Host smart-d3bcb5ae-eccd-448d-bbde-bb6d677d7207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506931466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1506931466
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2297526125
Short name T407
Test name
Test status
Simulation time 244692875 ps
CPU time 1.11 seconds
Started Jul 28 05:17:15 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 217408 kb
Host smart-67c8d738-720d-4731-8362-c40ec6559088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297526125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2297526125
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2874175815
Short name T11
Test name
Test status
Simulation time 95619128 ps
CPU time 0.78 seconds
Started Jul 28 05:17:20 PM PDT 24
Finished Jul 28 05:17:21 PM PDT 24
Peak memory 199896 kb
Host smart-e1d2aa13-3c67-4039-ac95-390c487ac143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874175815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2874175815
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1653203556
Short name T468
Test name
Test status
Simulation time 2025754390 ps
CPU time 8.12 seconds
Started Jul 28 05:17:06 PM PDT 24
Finished Jul 28 05:17:15 PM PDT 24
Peak memory 200288 kb
Host smart-798795ea-94c0-4230-9b9f-4d315deb91e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653203556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1653203556
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3824865906
Short name T290
Test name
Test status
Simulation time 111280608 ps
CPU time 1.05 seconds
Started Jul 28 05:17:20 PM PDT 24
Finished Jul 28 05:17:22 PM PDT 24
Peak memory 200072 kb
Host smart-39c093e0-17e8-4f12-8e74-0d0c4c8d656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824865906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3824865906
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2350310672
Short name T399
Test name
Test status
Simulation time 251493868 ps
CPU time 1.54 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:13 PM PDT 24
Peak memory 200284 kb
Host smart-d6649c2f-ec23-4821-bf50-0efaed985c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350310672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2350310672
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3936006702
Short name T192
Test name
Test status
Simulation time 9222604661 ps
CPU time 33.17 seconds
Started Jul 28 05:17:21 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 208516 kb
Host smart-c5131b61-6429-484d-a162-df35668f93e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936006702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3936006702
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2742343331
Short name T403
Test name
Test status
Simulation time 145112517 ps
CPU time 1.84 seconds
Started Jul 28 05:17:14 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 200012 kb
Host smart-261fd1f8-40fb-4db9-bf1a-d32a279b8582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742343331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2742343331
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1947763965
Short name T303
Test name
Test status
Simulation time 167024397 ps
CPU time 1.29 seconds
Started Jul 28 05:17:18 PM PDT 24
Finished Jul 28 05:17:19 PM PDT 24
Peak memory 200236 kb
Host smart-a7d3d68e-33b8-4632-b816-162ea47078b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947763965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1947763965
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.876310599
Short name T241
Test name
Test status
Simulation time 87290914 ps
CPU time 0.79 seconds
Started Jul 28 05:17:16 PM PDT 24
Finished Jul 28 05:17:17 PM PDT 24
Peak memory 199880 kb
Host smart-ac47d7db-f52c-43e8-a5cd-181cf0511e4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876310599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.876310599
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1959511045
Short name T301
Test name
Test status
Simulation time 1229506102 ps
CPU time 5.29 seconds
Started Jul 28 05:17:20 PM PDT 24
Finished Jul 28 05:17:26 PM PDT 24
Peak memory 217900 kb
Host smart-acdb7ac8-e240-43fd-a2dd-037dfaa81748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959511045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1959511045
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2178194832
Short name T224
Test name
Test status
Simulation time 243526922 ps
CPU time 1.08 seconds
Started Jul 28 05:17:19 PM PDT 24
Finished Jul 28 05:17:20 PM PDT 24
Peak memory 217416 kb
Host smart-87ff8cde-5b52-4c1f-a666-e6fae00a8e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178194832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2178194832
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1148604438
Short name T343
Test name
Test status
Simulation time 147458483 ps
CPU time 0.78 seconds
Started Jul 28 05:17:15 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 199904 kb
Host smart-5e2a68e1-e201-4c24-b0e7-98e4e734c986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148604438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1148604438
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.744493097
Short name T479
Test name
Test status
Simulation time 2050954641 ps
CPU time 7.85 seconds
Started Jul 28 05:17:15 PM PDT 24
Finished Jul 28 05:17:23 PM PDT 24
Peak memory 200332 kb
Host smart-cdeef24b-7dc9-41f9-b239-258453d2a812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744493097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.744493097
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2837086633
Short name T207
Test name
Test status
Simulation time 176107253 ps
CPU time 1.2 seconds
Started Jul 28 05:17:20 PM PDT 24
Finished Jul 28 05:17:21 PM PDT 24
Peak memory 200092 kb
Host smart-d3117c3a-2060-40bb-967a-3e298c56d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837086633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2837086633
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.311219410
Short name T327
Test name
Test status
Simulation time 109160350 ps
CPU time 1.18 seconds
Started Jul 28 05:17:25 PM PDT 24
Finished Jul 28 05:17:27 PM PDT 24
Peak memory 200252 kb
Host smart-cec0404d-9a00-496d-9b57-8c672f4cbcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311219410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.311219410
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.265839619
Short name T158
Test name
Test status
Simulation time 7532127935 ps
CPU time 27.73 seconds
Started Jul 28 05:17:11 PM PDT 24
Finished Jul 28 05:17:39 PM PDT 24
Peak memory 216760 kb
Host smart-89cd2494-c1f7-4337-90bb-7eeba5ff34f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265839619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.265839619
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2068599110
Short name T143
Test name
Test status
Simulation time 273242537 ps
CPU time 1.85 seconds
Started Jul 28 05:17:28 PM PDT 24
Finished Jul 28 05:17:29 PM PDT 24
Peak memory 200032 kb
Host smart-bf5039bc-a5a5-4589-ab50-ace15d834570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068599110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2068599110
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3617247929
Short name T171
Test name
Test status
Simulation time 238818894 ps
CPU time 1.45 seconds
Started Jul 28 05:17:14 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 200252 kb
Host smart-52bfa640-f99a-44ec-b19c-a50ff83995b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617247929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3617247929
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3493900816
Short name T195
Test name
Test status
Simulation time 61207773 ps
CPU time 0.75 seconds
Started Jul 28 05:17:17 PM PDT 24
Finished Jul 28 05:17:18 PM PDT 24
Peak memory 199860 kb
Host smart-1510f1e7-0885-4ddc-93fa-d92a3ca05d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493900816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3493900816
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.144931033
Short name T534
Test name
Test status
Simulation time 1229332383 ps
CPU time 5.42 seconds
Started Jul 28 05:17:35 PM PDT 24
Finished Jul 28 05:17:41 PM PDT 24
Peak memory 217736 kb
Host smart-66c12ffd-edb9-454e-af24-09f97b3fb6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144931033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.144931033
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3280161709
Short name T297
Test name
Test status
Simulation time 243576830 ps
CPU time 1.11 seconds
Started Jul 28 05:17:25 PM PDT 24
Finished Jul 28 05:17:26 PM PDT 24
Peak memory 217492 kb
Host smart-2ca13d3f-4bca-4013-8bde-ccfb5c662973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280161709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3280161709
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3344874087
Short name T249
Test name
Test status
Simulation time 162780290 ps
CPU time 0.83 seconds
Started Jul 28 05:17:29 PM PDT 24
Finished Jul 28 05:17:30 PM PDT 24
Peak memory 199816 kb
Host smart-24d64414-0b89-46e2-89ff-704248c944c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344874087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3344874087
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2254873731
Short name T525
Test name
Test status
Simulation time 1339709044 ps
CPU time 5.37 seconds
Started Jul 28 05:17:14 PM PDT 24
Finished Jul 28 05:17:19 PM PDT 24
Peak memory 200324 kb
Host smart-ca44df0f-e185-4568-9bc9-f377e7a203b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254873731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2254873731
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.583946362
Short name T223
Test name
Test status
Simulation time 102692026 ps
CPU time 1.06 seconds
Started Jul 28 05:17:21 PM PDT 24
Finished Jul 28 05:17:22 PM PDT 24
Peak memory 200060 kb
Host smart-804f0477-344d-48a2-9b73-585c6fa729fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583946362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.583946362
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1891894938
Short name T70
Test name
Test status
Simulation time 227909188 ps
CPU time 1.44 seconds
Started Jul 28 05:17:21 PM PDT 24
Finished Jul 28 05:17:22 PM PDT 24
Peak memory 200252 kb
Host smart-21811a82-de68-4c99-8e15-d16fa02b33d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891894938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1891894938
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.339720990
Short name T439
Test name
Test status
Simulation time 118819011 ps
CPU time 1.01 seconds
Started Jul 28 05:17:20 PM PDT 24
Finished Jul 28 05:17:21 PM PDT 24
Peak memory 200060 kb
Host smart-ecd91255-3396-4fab-b69c-d6539016a9ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339720990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.339720990
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3211681494
Short name T502
Test name
Test status
Simulation time 349362706 ps
CPU time 2 seconds
Started Jul 28 05:17:23 PM PDT 24
Finished Jul 28 05:17:25 PM PDT 24
Peak memory 200100 kb
Host smart-ced5f2ff-5931-4eba-bbc8-755329ae7fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211681494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3211681494
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3730198740
Short name T438
Test name
Test status
Simulation time 98950279 ps
CPU time 0.88 seconds
Started Jul 28 05:17:27 PM PDT 24
Finished Jul 28 05:17:28 PM PDT 24
Peak memory 200036 kb
Host smart-554e49c1-9ca5-4045-a299-1520d2ac2ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730198740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3730198740
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3131160341
Short name T494
Test name
Test status
Simulation time 69204998 ps
CPU time 0.77 seconds
Started Jul 28 05:17:35 PM PDT 24
Finished Jul 28 05:17:36 PM PDT 24
Peak memory 199892 kb
Host smart-a13eb3fe-d821-4f61-b720-831289128b4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131160341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3131160341
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1890992985
Short name T57
Test name
Test status
Simulation time 1885544148 ps
CPU time 7.07 seconds
Started Jul 28 05:17:16 PM PDT 24
Finished Jul 28 05:17:23 PM PDT 24
Peak memory 217784 kb
Host smart-03dbb0bf-cb0c-491f-ac8f-361c5348d20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890992985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1890992985
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2341545737
Short name T526
Test name
Test status
Simulation time 243582993 ps
CPU time 1.13 seconds
Started Jul 28 05:17:35 PM PDT 24
Finished Jul 28 05:17:36 PM PDT 24
Peak memory 217420 kb
Host smart-223a96f7-6d05-44c1-873c-05d0aacef82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341545737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2341545737
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3154880190
Short name T346
Test name
Test status
Simulation time 89151205 ps
CPU time 0.75 seconds
Started Jul 28 05:17:18 PM PDT 24
Finished Jul 28 05:17:19 PM PDT 24
Peak memory 199840 kb
Host smart-630d5696-54a2-43dd-89c6-dffaa6300bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154880190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3154880190
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2385061269
Short name T482
Test name
Test status
Simulation time 1702167293 ps
CPU time 6.66 seconds
Started Jul 28 05:17:18 PM PDT 24
Finished Jul 28 05:17:25 PM PDT 24
Peak memory 200392 kb
Host smart-a7afa611-f6e1-4571-a0ca-e753b1f26e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385061269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2385061269
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3658037434
Short name T426
Test name
Test status
Simulation time 103321256 ps
CPU time 0.97 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:08 PM PDT 24
Peak memory 200020 kb
Host smart-9c5b507e-69ca-4b90-b2d6-252685e77d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658037434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3658037434
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3755934667
Short name T256
Test name
Test status
Simulation time 200452403 ps
CPU time 1.46 seconds
Started Jul 28 05:17:10 PM PDT 24
Finished Jul 28 05:17:12 PM PDT 24
Peak memory 200256 kb
Host smart-aec30446-9df9-4938-a419-767bd5eed63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755934667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3755934667
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3190442834
Short name T177
Test name
Test status
Simulation time 12833964256 ps
CPU time 41.79 seconds
Started Jul 28 05:17:07 PM PDT 24
Finished Jul 28 05:17:48 PM PDT 24
Peak memory 200396 kb
Host smart-ac09f4ac-3591-4ccc-b79f-bd9b6e22df59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190442834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3190442834
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2575452671
Short name T382
Test name
Test status
Simulation time 328076925 ps
CPU time 1.98 seconds
Started Jul 28 05:17:19 PM PDT 24
Finished Jul 28 05:17:21 PM PDT 24
Peak memory 200020 kb
Host smart-55632bcf-38fe-45f7-bbcc-28ea48045b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575452671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2575452671
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1777435798
Short name T371
Test name
Test status
Simulation time 81355727 ps
CPU time 0.83 seconds
Started Jul 28 05:17:20 PM PDT 24
Finished Jul 28 05:17:21 PM PDT 24
Peak memory 199992 kb
Host smart-e2880f59-9aa1-4d38-af36-4475eedcdc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777435798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1777435798
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.37424158
Short name T448
Test name
Test status
Simulation time 76566295 ps
CPU time 0.87 seconds
Started Jul 28 05:17:28 PM PDT 24
Finished Jul 28 05:17:29 PM PDT 24
Peak memory 199816 kb
Host smart-0b5c3a2e-0fc7-4bbf-abc5-2bee9372764c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37424158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.37424158
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1405381481
Short name T334
Test name
Test status
Simulation time 1230133483 ps
CPU time 5.52 seconds
Started Jul 28 05:17:21 PM PDT 24
Finished Jul 28 05:17:27 PM PDT 24
Peak memory 216812 kb
Host smart-f2c03a83-038e-46cb-a35c-45e7850e9752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405381481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1405381481
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2031375981
Short name T164
Test name
Test status
Simulation time 244414243 ps
CPU time 0.99 seconds
Started Jul 28 05:17:18 PM PDT 24
Finished Jul 28 05:17:19 PM PDT 24
Peak memory 217408 kb
Host smart-385b3841-d8ad-4fe4-913f-4d292b146279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031375981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2031375981
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1956198702
Short name T13
Test name
Test status
Simulation time 166779642 ps
CPU time 0.86 seconds
Started Jul 28 05:17:38 PM PDT 24
Finished Jul 28 05:17:39 PM PDT 24
Peak memory 199892 kb
Host smart-7931e454-5210-45cd-ae2b-d8507b2aa5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956198702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1956198702
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2151655390
Short name T387
Test name
Test status
Simulation time 776378708 ps
CPU time 3.99 seconds
Started Jul 28 05:17:27 PM PDT 24
Finished Jul 28 05:17:31 PM PDT 24
Peak memory 200592 kb
Host smart-b4612c2b-30f0-4b43-a191-a900e43d6693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151655390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2151655390
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2593867100
Short name T39
Test name
Test status
Simulation time 179611237 ps
CPU time 1.25 seconds
Started Jul 28 05:17:15 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 199988 kb
Host smart-e0015830-a21c-46bd-b3b0-2a516c950e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593867100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2593867100
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1164051507
Short name T367
Test name
Test status
Simulation time 194779155 ps
CPU time 1.35 seconds
Started Jul 28 05:17:18 PM PDT 24
Finished Jul 28 05:17:19 PM PDT 24
Peak memory 200256 kb
Host smart-36e11fea-f0e3-44a3-ba7d-e609c8445d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164051507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1164051507
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.36266725
Short name T173
Test name
Test status
Simulation time 8927137178 ps
CPU time 29.93 seconds
Started Jul 28 05:17:29 PM PDT 24
Finished Jul 28 05:17:59 PM PDT 24
Peak memory 200392 kb
Host smart-facefa85-7afd-48d3-8ff4-667cf88b41f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36266725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.36266725
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2164994102
Short name T92
Test name
Test status
Simulation time 290330339 ps
CPU time 2.06 seconds
Started Jul 28 05:17:32 PM PDT 24
Finished Jul 28 05:17:34 PM PDT 24
Peak memory 208244 kb
Host smart-2455284c-812c-4c6b-9a13-2d7081672454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164994102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2164994102
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1245350782
Short name T263
Test name
Test status
Simulation time 119451975 ps
CPU time 0.98 seconds
Started Jul 28 05:17:19 PM PDT 24
Finished Jul 28 05:17:20 PM PDT 24
Peak memory 200092 kb
Host smart-8fa8a495-e33c-4637-84c4-93b148ed2aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245350782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1245350782
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2457796559
Short name T469
Test name
Test status
Simulation time 61494604 ps
CPU time 0.73 seconds
Started Jul 28 05:16:30 PM PDT 24
Finished Jul 28 05:16:31 PM PDT 24
Peak memory 199884 kb
Host smart-8ea48262-174e-4430-ab3d-c2049c2ff2dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457796559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2457796559
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3012310046
Short name T292
Test name
Test status
Simulation time 2176622345 ps
CPU time 7.33 seconds
Started Jul 28 05:16:36 PM PDT 24
Finished Jul 28 05:16:43 PM PDT 24
Peak memory 221692 kb
Host smart-45e46f4a-5d39-4b41-9bcb-705188540a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012310046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3012310046
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2861516727
Short name T300
Test name
Test status
Simulation time 243865006 ps
CPU time 1.14 seconds
Started Jul 28 05:16:54 PM PDT 24
Finished Jul 28 05:16:55 PM PDT 24
Peak memory 217432 kb
Host smart-d9dc14bd-2aa8-439b-b1f5-dad6bb5d3d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861516727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2861516727
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2895338348
Short name T85
Test name
Test status
Simulation time 174457042 ps
CPU time 0.9 seconds
Started Jul 28 05:16:28 PM PDT 24
Finished Jul 28 05:16:29 PM PDT 24
Peak memory 199876 kb
Host smart-c3458633-2ed7-4425-90d2-08ab4e187fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895338348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2895338348
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3499573756
Short name T90
Test name
Test status
Simulation time 1107323366 ps
CPU time 5.4 seconds
Started Jul 28 05:16:40 PM PDT 24
Finished Jul 28 05:16:46 PM PDT 24
Peak memory 200208 kb
Host smart-81f8b864-9ace-4a06-bc1b-53dc12887da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499573756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3499573756
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.741713481
Short name T81
Test name
Test status
Simulation time 16853622602 ps
CPU time 24.34 seconds
Started Jul 28 05:16:31 PM PDT 24
Finished Jul 28 05:16:55 PM PDT 24
Peak memory 217208 kb
Host smart-e09637b2-672c-4011-9d9c-63c518a93356
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741713481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.741713481
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1995302072
Short name T466
Test name
Test status
Simulation time 96704775 ps
CPU time 1 seconds
Started Jul 28 05:16:36 PM PDT 24
Finished Jul 28 05:16:37 PM PDT 24
Peak memory 200056 kb
Host smart-4e8c3e17-f3c5-48ab-bb63-5a4896078728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995302072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1995302072
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3705294536
Short name T330
Test name
Test status
Simulation time 200525417 ps
CPU time 1.36 seconds
Started Jul 28 05:16:48 PM PDT 24
Finished Jul 28 05:16:49 PM PDT 24
Peak memory 200300 kb
Host smart-35b5cffe-094d-4a81-80a3-83b8b9f98eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705294536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3705294536
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.724293592
Short name T113
Test name
Test status
Simulation time 20211855841 ps
CPU time 74.24 seconds
Started Jul 28 05:16:34 PM PDT 24
Finished Jul 28 05:17:49 PM PDT 24
Peak memory 200648 kb
Host smart-992c6563-95b6-44b3-91b1-badd80d7f978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724293592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.724293592
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.580025389
Short name T329
Test name
Test status
Simulation time 389198296 ps
CPU time 2.07 seconds
Started Jul 28 05:16:44 PM PDT 24
Finished Jul 28 05:16:47 PM PDT 24
Peak memory 200108 kb
Host smart-0e2eb4f9-35fb-4396-ba26-951263ee0c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580025389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.580025389
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2188808809
Short name T220
Test name
Test status
Simulation time 82493600 ps
CPU time 0.89 seconds
Started Jul 28 05:16:49 PM PDT 24
Finished Jul 28 05:16:50 PM PDT 24
Peak memory 200104 kb
Host smart-2133ca6d-cce9-4542-a390-a5993bd4870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188808809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2188808809
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3459611846
Short name T406
Test name
Test status
Simulation time 157939287 ps
CPU time 0.94 seconds
Started Jul 28 05:17:22 PM PDT 24
Finished Jul 28 05:17:23 PM PDT 24
Peak memory 199880 kb
Host smart-d04e90e8-9c72-4fee-9530-9d1c4597f9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459611846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3459611846
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1588257508
Short name T25
Test name
Test status
Simulation time 1887636241 ps
CPU time 7.05 seconds
Started Jul 28 05:17:37 PM PDT 24
Finished Jul 28 05:17:44 PM PDT 24
Peak memory 216700 kb
Host smart-7308168f-09c5-45c0-83ae-3aef3981af26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588257508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1588257508
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3577513671
Short name T462
Test name
Test status
Simulation time 245079366 ps
CPU time 1.11 seconds
Started Jul 28 05:17:32 PM PDT 24
Finished Jul 28 05:17:33 PM PDT 24
Peak memory 217336 kb
Host smart-22287dca-ec48-4d60-8de5-4be7202ad066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577513671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3577513671
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1766343040
Short name T508
Test name
Test status
Simulation time 172991507 ps
CPU time 0.87 seconds
Started Jul 28 05:17:31 PM PDT 24
Finished Jul 28 05:17:32 PM PDT 24
Peak memory 199860 kb
Host smart-2d2ccad9-1759-437d-b423-e904b120a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766343040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1766343040
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3368081686
Short name T442
Test name
Test status
Simulation time 1636127065 ps
CPU time 5.72 seconds
Started Jul 28 05:17:22 PM PDT 24
Finished Jul 28 05:17:28 PM PDT 24
Peak memory 200396 kb
Host smart-11f0deca-92ed-4b3d-bbff-a3dd15ca3e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368081686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3368081686
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1693923288
Short name T440
Test name
Test status
Simulation time 110026727 ps
CPU time 1.01 seconds
Started Jul 28 05:17:29 PM PDT 24
Finished Jul 28 05:17:30 PM PDT 24
Peak memory 199980 kb
Host smart-3b6a3486-b822-4937-9210-c06263a66fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693923288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1693923288
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3278349564
Short name T199
Test name
Test status
Simulation time 193583881 ps
CPU time 1.33 seconds
Started Jul 28 05:17:35 PM PDT 24
Finished Jul 28 05:17:37 PM PDT 24
Peak memory 200304 kb
Host smart-1055b6fa-a00f-4876-901d-f7ee06a6e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278349564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3278349564
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.216068991
Short name T291
Test name
Test status
Simulation time 6863044521 ps
CPU time 25.78 seconds
Started Jul 28 05:17:20 PM PDT 24
Finished Jul 28 05:17:46 PM PDT 24
Peak memory 200660 kb
Host smart-6cd05182-1b3d-4a79-be4a-51149251d380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216068991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.216068991
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.910053521
Short name T93
Test name
Test status
Simulation time 120995559 ps
CPU time 1.57 seconds
Started Jul 28 05:17:37 PM PDT 24
Finished Jul 28 05:17:39 PM PDT 24
Peak memory 200136 kb
Host smart-c4418a49-8cc8-4d0d-81d3-2a5838aa2ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910053521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.910053521
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3550969932
Short name T212
Test name
Test status
Simulation time 97106189 ps
CPU time 0.85 seconds
Started Jul 28 05:17:31 PM PDT 24
Finished Jul 28 05:17:32 PM PDT 24
Peak memory 200008 kb
Host smart-f32e041a-8e5d-443f-ba60-96d2658c4b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550969932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3550969932
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.225736062
Short name T305
Test name
Test status
Simulation time 62982987 ps
CPU time 0.78 seconds
Started Jul 28 05:17:31 PM PDT 24
Finished Jul 28 05:17:32 PM PDT 24
Peak memory 199884 kb
Host smart-c068697b-698f-4262-b596-44d2b9608b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225736062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.225736062
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2992872812
Short name T24
Test name
Test status
Simulation time 1233664077 ps
CPU time 5.58 seconds
Started Jul 28 05:17:28 PM PDT 24
Finished Jul 28 05:17:34 PM PDT 24
Peak memory 217752 kb
Host smart-87402b05-d4ee-45bf-b9c4-92d3d11016d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992872812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2992872812
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.22366129
Short name T531
Test name
Test status
Simulation time 244276106 ps
CPU time 1.05 seconds
Started Jul 28 05:17:29 PM PDT 24
Finished Jul 28 05:17:30 PM PDT 24
Peak memory 217408 kb
Host smart-63c838f8-54ca-4759-8eb3-af2af359e84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22366129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.22366129
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4120837948
Short name T260
Test name
Test status
Simulation time 103196426 ps
CPU time 0.84 seconds
Started Jul 28 05:17:28 PM PDT 24
Finished Jul 28 05:17:29 PM PDT 24
Peak memory 199752 kb
Host smart-783e0c4e-11de-47bf-929e-a2d69a6eab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120837948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4120837948
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3807316732
Short name T444
Test name
Test status
Simulation time 1668750007 ps
CPU time 6.18 seconds
Started Jul 28 05:17:24 PM PDT 24
Finished Jul 28 05:17:30 PM PDT 24
Peak memory 200316 kb
Host smart-a48d9281-5664-4026-858d-261c9e6489ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807316732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3807316732
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1096252839
Short name T43
Test name
Test status
Simulation time 177663834 ps
CPU time 1.26 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:58 PM PDT 24
Peak memory 200084 kb
Host smart-d8e45215-ec57-48a2-8f7c-b4664e8d77fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096252839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1096252839
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2099586183
Short name T255
Test name
Test status
Simulation time 195071861 ps
CPU time 1.42 seconds
Started Jul 28 05:17:34 PM PDT 24
Finished Jul 28 05:17:35 PM PDT 24
Peak memory 200272 kb
Host smart-a48e7835-8a34-40a1-899f-71e8aab900e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099586183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2099586183
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1398506493
Short name T180
Test name
Test status
Simulation time 6687758913 ps
CPU time 30.61 seconds
Started Jul 28 05:17:34 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 208636 kb
Host smart-37ff177d-98fc-4e0b-be72-c71e9e2859e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398506493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1398506493
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2778663037
Short name T179
Test name
Test status
Simulation time 415414513 ps
CPU time 2.31 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:33 PM PDT 24
Peak memory 208256 kb
Host smart-f38de8ee-8971-4345-a949-3b314a45a2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778663037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2778663037
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1108405616
Short name T376
Test name
Test status
Simulation time 140028405 ps
CPU time 0.99 seconds
Started Jul 28 05:17:33 PM PDT 24
Finished Jul 28 05:17:35 PM PDT 24
Peak memory 200056 kb
Host smart-52236daa-e9bc-410e-be22-934df865e489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108405616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1108405616
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2493171843
Short name T314
Test name
Test status
Simulation time 66951407 ps
CPU time 0.72 seconds
Started Jul 28 05:17:34 PM PDT 24
Finished Jul 28 05:17:35 PM PDT 24
Peak memory 199880 kb
Host smart-e9b0fea6-afec-4c72-bc36-6554df8960a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493171843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2493171843
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2522651140
Short name T293
Test name
Test status
Simulation time 244614031 ps
CPU time 1.02 seconds
Started Jul 28 05:17:25 PM PDT 24
Finished Jul 28 05:17:26 PM PDT 24
Peak memory 217412 kb
Host smart-b16e34ba-0753-4251-80f6-97b6c77298e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522651140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2522651140
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.810047186
Short name T413
Test name
Test status
Simulation time 95157549 ps
CPU time 0.74 seconds
Started Jul 28 05:17:19 PM PDT 24
Finished Jul 28 05:17:20 PM PDT 24
Peak memory 199884 kb
Host smart-6701be7d-db67-4322-b2cd-416799f382ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810047186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.810047186
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3490090564
Short name T50
Test name
Test status
Simulation time 865877832 ps
CPU time 4.21 seconds
Started Jul 28 05:17:34 PM PDT 24
Finished Jul 28 05:17:38 PM PDT 24
Peak memory 200384 kb
Host smart-16ecfe93-f149-42e8-9e24-b2f464b1d58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490090564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3490090564
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2666599041
Short name T322
Test name
Test status
Simulation time 140236271 ps
CPU time 1.15 seconds
Started Jul 28 05:17:22 PM PDT 24
Finished Jul 28 05:17:23 PM PDT 24
Peak memory 200076 kb
Host smart-70ccdc4e-9803-4ba7-9cdd-abbe42826686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666599041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2666599041
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1330698650
Short name T363
Test name
Test status
Simulation time 112948177 ps
CPU time 1.19 seconds
Started Jul 28 05:17:22 PM PDT 24
Finished Jul 28 05:17:23 PM PDT 24
Peak memory 200332 kb
Host smart-1c519895-2b6c-4b2a-836a-06fdd6b55012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330698650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1330698650
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3636479489
Short name T308
Test name
Test status
Simulation time 3386347225 ps
CPU time 12.4 seconds
Started Jul 28 05:17:32 PM PDT 24
Finished Jul 28 05:17:45 PM PDT 24
Peak memory 208580 kb
Host smart-3905bea5-264b-4c8e-8a38-963f9e306830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636479489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3636479489
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1722943894
Short name T516
Test name
Test status
Simulation time 144333345 ps
CPU time 1.68 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:32 PM PDT 24
Peak memory 199992 kb
Host smart-450be67a-86d8-4755-b14a-b292133fdccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722943894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1722943894
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2774408365
Short name T157
Test name
Test status
Simulation time 92194066 ps
CPU time 0.93 seconds
Started Jul 28 05:17:35 PM PDT 24
Finished Jul 28 05:17:36 PM PDT 24
Peak memory 199992 kb
Host smart-4f931dbe-f75c-48b2-b4d8-60d4154dcc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774408365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2774408365
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.521467509
Short name T490
Test name
Test status
Simulation time 70363101 ps
CPU time 0.76 seconds
Started Jul 28 05:17:35 PM PDT 24
Finished Jul 28 05:17:36 PM PDT 24
Peak memory 199828 kb
Host smart-862825e4-d1f8-4ccb-8a40-4189fb6bdd7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521467509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.521467509
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.389583564
Short name T489
Test name
Test status
Simulation time 2165999956 ps
CPU time 7.44 seconds
Started Jul 28 05:17:35 PM PDT 24
Finished Jul 28 05:17:47 PM PDT 24
Peak memory 221652 kb
Host smart-d9429fb0-fb60-43ed-a673-00a79638fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389583564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.389583564
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.670022731
Short name T533
Test name
Test status
Simulation time 243691382 ps
CPU time 1.04 seconds
Started Jul 28 05:17:32 PM PDT 24
Finished Jul 28 05:17:33 PM PDT 24
Peak memory 217396 kb
Host smart-4cd84ced-882e-48a8-a8d2-c399b22c5010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670022731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.670022731
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3568034131
Short name T17
Test name
Test status
Simulation time 179775045 ps
CPU time 0.86 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:31 PM PDT 24
Peak memory 199876 kb
Host smart-e8b45429-737e-4f41-ad25-022086794335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568034131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3568034131
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3654435390
Short name T425
Test name
Test status
Simulation time 2054919323 ps
CPU time 7.21 seconds
Started Jul 28 05:17:44 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 200320 kb
Host smart-84ac36c3-d2be-42dc-8d5a-da5216b3d125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654435390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3654435390
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3706166385
Short name T344
Test name
Test status
Simulation time 157322767 ps
CPU time 1.12 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:31 PM PDT 24
Peak memory 200064 kb
Host smart-3ac16a79-afd6-41a4-b34d-9dc7ef56f8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706166385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3706166385
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1943587353
Short name T380
Test name
Test status
Simulation time 208195009 ps
CPU time 1.36 seconds
Started Jul 28 05:17:31 PM PDT 24
Finished Jul 28 05:17:32 PM PDT 24
Peak memory 200268 kb
Host smart-cc3c5454-9e28-4164-bb47-11769c79b41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943587353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1943587353
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1619405077
Short name T389
Test name
Test status
Simulation time 4391729595 ps
CPU time 21.55 seconds
Started Jul 28 05:17:34 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 208620 kb
Host smart-f80a09ee-f513-4878-b457-3dae7491b2e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619405077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1619405077
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.285447066
Short name T285
Test name
Test status
Simulation time 116313800 ps
CPU time 1.45 seconds
Started Jul 28 05:17:35 PM PDT 24
Finished Jul 28 05:17:36 PM PDT 24
Peak memory 199996 kb
Host smart-bab3f7f5-384d-425a-b60b-8eba5d85f6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285447066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.285447066
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1914095301
Short name T288
Test name
Test status
Simulation time 97993391 ps
CPU time 0.86 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:31 PM PDT 24
Peak memory 200124 kb
Host smart-4c9436a1-edca-4d06-ba0d-331bcead40e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914095301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1914095301
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3933200912
Short name T273
Test name
Test status
Simulation time 68614487 ps
CPU time 0.76 seconds
Started Jul 28 05:17:32 PM PDT 24
Finished Jul 28 05:17:33 PM PDT 24
Peak memory 199912 kb
Host smart-022ab3c2-406c-4725-ba2f-53c0707fce42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933200912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3933200912
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2235162797
Short name T421
Test name
Test status
Simulation time 1235168222 ps
CPU time 5.79 seconds
Started Jul 28 05:17:42 PM PDT 24
Finished Jul 28 05:17:48 PM PDT 24
Peak memory 217632 kb
Host smart-9d973980-eeb2-4bd9-a926-4937a0657cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235162797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2235162797
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2428904845
Short name T250
Test name
Test status
Simulation time 244745394 ps
CPU time 1.01 seconds
Started Jul 28 05:17:34 PM PDT 24
Finished Jul 28 05:17:36 PM PDT 24
Peak memory 217484 kb
Host smart-3744e7d5-badc-49c3-b666-a9b788c868df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428904845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2428904845
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1332948486
Short name T414
Test name
Test status
Simulation time 97492816 ps
CPU time 0.83 seconds
Started Jul 28 05:17:37 PM PDT 24
Finished Jul 28 05:17:38 PM PDT 24
Peak memory 199888 kb
Host smart-ed270afe-9bf1-4f69-8f7d-689bb550fa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332948486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1332948486
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.902350193
Short name T275
Test name
Test status
Simulation time 893917674 ps
CPU time 4.59 seconds
Started Jul 28 05:17:32 PM PDT 24
Finished Jul 28 05:17:37 PM PDT 24
Peak memory 200216 kb
Host smart-8f9a8710-e23e-48e4-ac47-b0ea891c3a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902350193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.902350193
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.483335115
Short name T204
Test name
Test status
Simulation time 159985768 ps
CPU time 1.1 seconds
Started Jul 28 05:17:29 PM PDT 24
Finished Jul 28 05:17:30 PM PDT 24
Peak memory 200020 kb
Host smart-c23763c4-1738-47c4-bc1f-bd871db97661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483335115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.483335115
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2079085065
Short name T465
Test name
Test status
Simulation time 195703245 ps
CPU time 1.33 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:32 PM PDT 24
Peak memory 200264 kb
Host smart-c9561110-7645-4f4e-881e-d8c63f34f002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079085065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2079085065
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1598066500
Short name T202
Test name
Test status
Simulation time 3881273078 ps
CPU time 13.16 seconds
Started Jul 28 05:17:38 PM PDT 24
Finished Jul 28 05:17:51 PM PDT 24
Peak memory 200416 kb
Host smart-146d6c7b-9392-46da-9429-b8d12d72982a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598066500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1598066500
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.765840215
Short name T530
Test name
Test status
Simulation time 426994454 ps
CPU time 2.28 seconds
Started Jul 28 05:17:33 PM PDT 24
Finished Jul 28 05:17:35 PM PDT 24
Peak memory 208312 kb
Host smart-b5ed43d2-50ed-472b-b5b2-7cb03465b853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765840215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.765840215
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2812523635
Short name T417
Test name
Test status
Simulation time 111609186 ps
CPU time 1.08 seconds
Started Jul 28 05:17:36 PM PDT 24
Finished Jul 28 05:17:37 PM PDT 24
Peak memory 200080 kb
Host smart-afff0ed1-70b5-49eb-b618-9f0537019cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812523635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2812523635
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3749674560
Short name T276
Test name
Test status
Simulation time 57370290 ps
CPU time 0.71 seconds
Started Jul 28 05:17:41 PM PDT 24
Finished Jul 28 05:17:41 PM PDT 24
Peak memory 199904 kb
Host smart-522cf083-5f6b-4d17-b09f-95b9054bad25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749674560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3749674560
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2775346164
Short name T54
Test name
Test status
Simulation time 1239572505 ps
CPU time 5.31 seconds
Started Jul 28 05:17:38 PM PDT 24
Finished Jul 28 05:17:44 PM PDT 24
Peak memory 217712 kb
Host smart-a8b25bea-1fda-4b86-be41-afc32bcf24ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775346164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2775346164
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3804314143
Short name T505
Test name
Test status
Simulation time 245989242 ps
CPU time 1.03 seconds
Started Jul 28 05:17:27 PM PDT 24
Finished Jul 28 05:17:28 PM PDT 24
Peak memory 217508 kb
Host smart-354a1bfd-9f1e-46ca-82bd-9eb186aaaef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804314143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3804314143
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3414844855
Short name T316
Test name
Test status
Simulation time 108739173 ps
CPU time 0.78 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:31 PM PDT 24
Peak memory 199864 kb
Host smart-6d73a5be-9b27-42df-85f4-6c7dd0fd84ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414844855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3414844855
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1491317995
Short name T227
Test name
Test status
Simulation time 1544248808 ps
CPU time 5.74 seconds
Started Jul 28 05:17:36 PM PDT 24
Finished Jul 28 05:17:42 PM PDT 24
Peak memory 200260 kb
Host smart-41e7f440-6669-4ad6-a1ee-1854a462aa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491317995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1491317995
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1994125333
Short name T229
Test name
Test status
Simulation time 166859071 ps
CPU time 1.23 seconds
Started Jul 28 05:17:32 PM PDT 24
Finished Jul 28 05:17:33 PM PDT 24
Peak memory 200304 kb
Host smart-b30c9939-fa40-4521-9929-dbecc5141838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994125333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1994125333
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.811767400
Short name T140
Test name
Test status
Simulation time 208149270 ps
CPU time 1.38 seconds
Started Jul 28 05:17:20 PM PDT 24
Finished Jul 28 05:17:21 PM PDT 24
Peak memory 200288 kb
Host smart-8962f448-5972-4513-9467-3dc6893ff41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811767400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.811767400
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.101632926
Short name T350
Test name
Test status
Simulation time 8256227087 ps
CPU time 30.07 seconds
Started Jul 28 05:17:38 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 208592 kb
Host smart-a7258a03-d82d-47ad-adb1-2daa67ce08f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101632926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.101632926
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3802136384
Short name T521
Test name
Test status
Simulation time 114738872 ps
CPU time 1.43 seconds
Started Jul 28 05:17:40 PM PDT 24
Finished Jul 28 05:17:41 PM PDT 24
Peak memory 200100 kb
Host smart-3cc4212a-1156-4a00-b222-3ea2cb3b7d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802136384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3802136384
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3512014847
Short name T299
Test name
Test status
Simulation time 149748847 ps
CPU time 1.03 seconds
Started Jul 28 05:17:19 PM PDT 24
Finished Jul 28 05:17:20 PM PDT 24
Peak memory 200072 kb
Host smart-47f3b3d0-6cec-49a0-9589-a905419b2fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512014847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3512014847
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1749631839
Short name T457
Test name
Test status
Simulation time 71483593 ps
CPU time 0.77 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:31 PM PDT 24
Peak memory 199860 kb
Host smart-848160a1-e49d-4078-9471-c37316c54b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749631839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1749631839
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2561828544
Short name T518
Test name
Test status
Simulation time 2351135088 ps
CPU time 7.71 seconds
Started Jul 28 05:17:31 PM PDT 24
Finished Jul 28 05:17:39 PM PDT 24
Peak memory 217792 kb
Host smart-773f3db7-2803-4ca4-b933-df0d5f4b0e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561828544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2561828544
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3184730474
Short name T349
Test name
Test status
Simulation time 244611651 ps
CPU time 1.06 seconds
Started Jul 28 05:17:28 PM PDT 24
Finished Jul 28 05:17:29 PM PDT 24
Peak memory 217476 kb
Host smart-742aca3b-389e-4a20-9d8d-b65a57c52787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184730474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3184730474
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2230422197
Short name T340
Test name
Test status
Simulation time 75451082 ps
CPU time 0.74 seconds
Started Jul 28 05:17:34 PM PDT 24
Finished Jul 28 05:17:35 PM PDT 24
Peak memory 199888 kb
Host smart-85cfb66e-8763-42d7-8111-03dd54cea188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230422197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2230422197
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.201093811
Short name T400
Test name
Test status
Simulation time 1935958664 ps
CPU time 7.05 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:59 PM PDT 24
Peak memory 200328 kb
Host smart-60b154ba-e613-41c6-a343-136db33181d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201093811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.201093811
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2985868573
Short name T271
Test name
Test status
Simulation time 106439165 ps
CPU time 0.97 seconds
Started Jul 28 05:17:33 PM PDT 24
Finished Jul 28 05:17:34 PM PDT 24
Peak memory 200072 kb
Host smart-c689ba7e-dfb9-40e0-8c82-d8db062d5376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985868573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2985868573
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1160084595
Short name T372
Test name
Test status
Simulation time 190790937 ps
CPU time 1.48 seconds
Started Jul 28 05:17:36 PM PDT 24
Finished Jul 28 05:17:38 PM PDT 24
Peak memory 200224 kb
Host smart-dcc78c65-3bdc-4cee-9e04-c6510c1351f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160084595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1160084595
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3557458157
Short name T429
Test name
Test status
Simulation time 711279657 ps
CPU time 2.98 seconds
Started Jul 28 05:17:40 PM PDT 24
Finished Jul 28 05:17:43 PM PDT 24
Peak memory 200228 kb
Host smart-727c2b01-fbe7-492f-8261-850e8f303e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557458157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3557458157
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1117396064
Short name T46
Test name
Test status
Simulation time 113036748 ps
CPU time 1.4 seconds
Started Jul 28 05:17:31 PM PDT 24
Finished Jul 28 05:17:33 PM PDT 24
Peak memory 200024 kb
Host smart-60f30c43-c784-4845-b103-a724bf4317ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117396064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1117396064
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3712829270
Short name T234
Test name
Test status
Simulation time 63189921 ps
CPU time 0.74 seconds
Started Jul 28 05:17:24 PM PDT 24
Finished Jul 28 05:17:25 PM PDT 24
Peak memory 199856 kb
Host smart-b2f2a26f-c1ea-4919-94e0-12d4fe3b08ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712829270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3712829270
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3196508720
Short name T58
Test name
Test status
Simulation time 2357101252 ps
CPU time 7.92 seconds
Started Jul 28 05:17:21 PM PDT 24
Finished Jul 28 05:17:29 PM PDT 24
Peak memory 217852 kb
Host smart-a94badc0-8fc9-4388-973b-1753e2c9eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196508720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3196508720
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.923474020
Short name T159
Test name
Test status
Simulation time 245289247 ps
CPU time 1.08 seconds
Started Jul 28 05:17:34 PM PDT 24
Finished Jul 28 05:17:36 PM PDT 24
Peak memory 217436 kb
Host smart-64037e3d-5b2a-4bfb-bdc3-cad35fc76d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923474020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.923474020
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.900331573
Short name T408
Test name
Test status
Simulation time 95440036 ps
CPU time 0.78 seconds
Started Jul 28 05:17:34 PM PDT 24
Finished Jul 28 05:17:35 PM PDT 24
Peak memory 199888 kb
Host smart-b4f4075d-bc9e-48bb-9116-ec25e6aa43db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900331573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.900331573
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3092588975
Short name T394
Test name
Test status
Simulation time 1013406459 ps
CPU time 4.8 seconds
Started Jul 28 05:17:46 PM PDT 24
Finished Jul 28 05:17:51 PM PDT 24
Peak memory 200348 kb
Host smart-a35db90c-068b-442c-8271-f91450023284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092588975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3092588975
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3502477099
Short name T345
Test name
Test status
Simulation time 143124039 ps
CPU time 1.1 seconds
Started Jul 28 05:17:25 PM PDT 24
Finished Jul 28 05:17:26 PM PDT 24
Peak memory 200072 kb
Host smart-c4911eee-d506-487d-aedc-d937a7f17e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502477099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3502477099
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2475608623
Short name T337
Test name
Test status
Simulation time 245939940 ps
CPU time 1.55 seconds
Started Jul 28 05:17:37 PM PDT 24
Finished Jul 28 05:17:39 PM PDT 24
Peak memory 200276 kb
Host smart-6acddee3-0077-473a-9e64-a40debe90972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475608623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2475608623
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3029235992
Short name T185
Test name
Test status
Simulation time 12876416266 ps
CPU time 45.83 seconds
Started Jul 28 05:17:39 PM PDT 24
Finished Jul 28 05:18:25 PM PDT 24
Peak memory 208552 kb
Host smart-597a9bd3-b3b1-47a0-b3ba-8c3ac47c827c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029235992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3029235992
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.68499076
Short name T513
Test name
Test status
Simulation time 438418266 ps
CPU time 2.4 seconds
Started Jul 28 05:17:30 PM PDT 24
Finished Jul 28 05:17:33 PM PDT 24
Peak memory 200072 kb
Host smart-41fef281-bab5-4c41-901a-0a73ce89842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68499076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.68499076
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.532685675
Short name T264
Test name
Test status
Simulation time 171482639 ps
CPU time 1.23 seconds
Started Jul 28 05:17:31 PM PDT 24
Finished Jul 28 05:17:32 PM PDT 24
Peak memory 199996 kb
Host smart-f49cb682-86ed-45c2-a237-3adfb290667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532685675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.532685675
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1104442103
Short name T385
Test name
Test status
Simulation time 62990541 ps
CPU time 0.72 seconds
Started Jul 28 05:17:38 PM PDT 24
Finished Jul 28 05:17:38 PM PDT 24
Peak memory 199800 kb
Host smart-0292f7f0-85db-42c6-8b4f-dc65a1980ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104442103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1104442103
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.298093574
Short name T59
Test name
Test status
Simulation time 1877035973 ps
CPU time 6.55 seconds
Started Jul 28 05:17:39 PM PDT 24
Finished Jul 28 05:17:45 PM PDT 24
Peak memory 217780 kb
Host smart-88ed8348-f97c-4780-8326-fb8be85dcb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298093574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.298093574
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2174369543
Short name T235
Test name
Test status
Simulation time 244287999 ps
CPU time 1.18 seconds
Started Jul 28 05:17:33 PM PDT 24
Finished Jul 28 05:17:34 PM PDT 24
Peak memory 217420 kb
Host smart-7c2a7860-9ee1-4dc8-a6ff-dd9843c2ce7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174369543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2174369543
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3176015910
Short name T449
Test name
Test status
Simulation time 167815054 ps
CPU time 0.88 seconds
Started Jul 28 05:17:33 PM PDT 24
Finished Jul 28 05:17:34 PM PDT 24
Peak memory 199796 kb
Host smart-1be804bc-267c-4df2-907f-7282d194f991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176015910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3176015910
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2788480213
Short name T108
Test name
Test status
Simulation time 1916429783 ps
CPU time 6.85 seconds
Started Jul 28 05:17:38 PM PDT 24
Finished Jul 28 05:17:45 PM PDT 24
Peak memory 200344 kb
Host smart-576a933c-5e3b-45e2-af25-b92520af5d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788480213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2788480213
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3815916515
Short name T304
Test name
Test status
Simulation time 187950098 ps
CPU time 1.25 seconds
Started Jul 28 05:17:24 PM PDT 24
Finished Jul 28 05:17:26 PM PDT 24
Peak memory 200080 kb
Host smart-2a8d501c-bb24-4cb1-8176-383785a0e505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815916515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3815916515
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3360829685
Short name T182
Test name
Test status
Simulation time 117855811 ps
CPU time 1.21 seconds
Started Jul 28 05:17:35 PM PDT 24
Finished Jul 28 05:17:37 PM PDT 24
Peak memory 200324 kb
Host smart-e3e0d2c0-6f98-438a-93b0-5ee4f2516230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360829685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3360829685
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2782025619
Short name T161
Test name
Test status
Simulation time 1051839530 ps
CPU time 5.18 seconds
Started Jul 28 05:17:37 PM PDT 24
Finished Jul 28 05:17:42 PM PDT 24
Peak memory 208536 kb
Host smart-4109f729-d830-4ec9-82f3-d204e21ae202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782025619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2782025619
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4259835432
Short name T170
Test name
Test status
Simulation time 361451217 ps
CPU time 2.01 seconds
Started Jul 28 05:17:33 PM PDT 24
Finished Jul 28 05:17:35 PM PDT 24
Peak memory 200084 kb
Host smart-012cbae2-36fc-427c-a7ce-77ab73bf4c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259835432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4259835432
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2666183323
Short name T135
Test name
Test status
Simulation time 101939086 ps
CPU time 1.01 seconds
Started Jul 28 05:17:44 PM PDT 24
Finished Jul 28 05:17:46 PM PDT 24
Peak memory 200064 kb
Host smart-bdfadf6a-0183-4877-a19b-c06375794b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666183323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2666183323
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.4174825661
Short name T45
Test name
Test status
Simulation time 65907607 ps
CPU time 0.81 seconds
Started Jul 28 05:17:36 PM PDT 24
Finished Jul 28 05:17:37 PM PDT 24
Peak memory 199824 kb
Host smart-a25ee13b-0329-4cd4-b668-dba801556eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174825661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4174825661
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2848135157
Short name T41
Test name
Test status
Simulation time 1886130511 ps
CPU time 7.7 seconds
Started Jul 28 05:17:27 PM PDT 24
Finished Jul 28 05:17:34 PM PDT 24
Peak memory 217672 kb
Host smart-3003c8e0-12fe-4cb7-bc06-24322728d179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848135157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2848135157
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3124713865
Short name T404
Test name
Test status
Simulation time 244231699 ps
CPU time 1.1 seconds
Started Jul 28 05:17:37 PM PDT 24
Finished Jul 28 05:17:38 PM PDT 24
Peak memory 217404 kb
Host smart-83395881-c2b0-4271-9052-c4e4cd2f8f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124713865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3124713865
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2825426158
Short name T365
Test name
Test status
Simulation time 98154816 ps
CPU time 0.76 seconds
Started Jul 28 05:17:27 PM PDT 24
Finished Jul 28 05:17:28 PM PDT 24
Peak memory 199868 kb
Host smart-7f797884-bf47-4083-a5b4-e3011fa4791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825426158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2825426158
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1779797680
Short name T206
Test name
Test status
Simulation time 1447287512 ps
CPU time 5.74 seconds
Started Jul 28 05:17:36 PM PDT 24
Finished Jul 28 05:17:42 PM PDT 24
Peak memory 200256 kb
Host smart-d69da3c0-5e89-41eb-bb4e-d74586109ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779797680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1779797680
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1830038228
Short name T49
Test name
Test status
Simulation time 97369593 ps
CPU time 0.96 seconds
Started Jul 28 05:17:42 PM PDT 24
Finished Jul 28 05:17:43 PM PDT 24
Peak memory 199984 kb
Host smart-4c4cad47-8b3d-4661-a65a-6e7f8023b63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830038228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1830038228
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2538010506
Short name T150
Test name
Test status
Simulation time 122576882 ps
CPU time 1.21 seconds
Started Jul 28 05:17:37 PM PDT 24
Finished Jul 28 05:17:39 PM PDT 24
Peak memory 200188 kb
Host smart-0cb9f7ce-1352-41a9-a2a2-dc09688dcf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538010506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2538010506
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2617444006
Short name T410
Test name
Test status
Simulation time 7045287192 ps
CPU time 28.87 seconds
Started Jul 28 05:17:39 PM PDT 24
Finished Jul 28 05:18:08 PM PDT 24
Peak memory 208572 kb
Host smart-624f7671-89bc-4e60-896e-4911a2cc4d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617444006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2617444006
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2976657730
Short name T95
Test name
Test status
Simulation time 253363406 ps
CPU time 1.68 seconds
Started Jul 28 05:17:25 PM PDT 24
Finished Jul 28 05:17:27 PM PDT 24
Peak memory 200060 kb
Host smart-ffc48061-25d2-4414-9f93-9fa9bf1ead5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976657730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2976657730
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.538921918
Short name T326
Test name
Test status
Simulation time 76022335 ps
CPU time 0.79 seconds
Started Jul 28 05:17:27 PM PDT 24
Finished Jul 28 05:17:28 PM PDT 24
Peak memory 200020 kb
Host smart-dd2e71d0-6666-4055-abc5-daab180769f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538921918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.538921918
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1271500709
Short name T129
Test name
Test status
Simulation time 94113099 ps
CPU time 0.84 seconds
Started Jul 28 05:16:42 PM PDT 24
Finished Jul 28 05:16:43 PM PDT 24
Peak memory 199860 kb
Host smart-647d4ceb-8075-47b2-b40c-238dcd2709d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271500709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1271500709
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.177789503
Short name T496
Test name
Test status
Simulation time 1883505643 ps
CPU time 7.14 seconds
Started Jul 28 05:16:34 PM PDT 24
Finished Jul 28 05:16:42 PM PDT 24
Peak memory 217728 kb
Host smart-5fbba5bf-a188-4d47-8bce-788e981b48c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177789503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.177789503
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3779468635
Short name T137
Test name
Test status
Simulation time 244157104 ps
CPU time 1.08 seconds
Started Jul 28 05:16:38 PM PDT 24
Finished Jul 28 05:16:39 PM PDT 24
Peak memory 217476 kb
Host smart-aee71ab6-1e84-4d9e-afbe-9453c2a195e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779468635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3779468635
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.745999899
Short name T443
Test name
Test status
Simulation time 211692155 ps
CPU time 0.91 seconds
Started Jul 28 05:16:33 PM PDT 24
Finished Jul 28 05:16:34 PM PDT 24
Peak memory 199884 kb
Host smart-c27630ed-cacc-4919-a2f6-15d00c4db800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745999899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.745999899
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1963480373
Short name T476
Test name
Test status
Simulation time 1711298190 ps
CPU time 6.28 seconds
Started Jul 28 05:16:53 PM PDT 24
Finished Jul 28 05:16:59 PM PDT 24
Peak memory 200360 kb
Host smart-b6654f46-5f2e-4480-9c6e-ba4fa81c884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963480373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1963480373
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.604521310
Short name T176
Test name
Test status
Simulation time 146576852 ps
CPU time 1.14 seconds
Started Jul 28 05:16:40 PM PDT 24
Finished Jul 28 05:16:42 PM PDT 24
Peak memory 200096 kb
Host smart-a55ae963-5ccb-4e27-8b63-c8c2178a3c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604521310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.604521310
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.569127976
Short name T47
Test name
Test status
Simulation time 255250331 ps
CPU time 1.51 seconds
Started Jul 28 05:16:42 PM PDT 24
Finished Jul 28 05:16:44 PM PDT 24
Peak memory 200280 kb
Host smart-68adcd38-e923-4aed-bbe9-187060e68b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569127976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.569127976
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1979341460
Short name T309
Test name
Test status
Simulation time 5082696759 ps
CPU time 20.88 seconds
Started Jul 28 05:16:32 PM PDT 24
Finished Jul 28 05:16:53 PM PDT 24
Peak memory 200332 kb
Host smart-522ace2b-d733-4612-a620-eb065280ddab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979341460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1979341460
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.33327069
Short name T245
Test name
Test status
Simulation time 137989672 ps
CPU time 1.64 seconds
Started Jul 28 05:16:40 PM PDT 24
Finished Jul 28 05:16:42 PM PDT 24
Peak memory 200084 kb
Host smart-d8dd5635-aa5b-4896-885f-7fc489b8a39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33327069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.33327069
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.25460708
Short name T370
Test name
Test status
Simulation time 131075573 ps
CPU time 1.03 seconds
Started Jul 28 05:16:35 PM PDT 24
Finished Jul 28 05:16:37 PM PDT 24
Peak memory 200060 kb
Host smart-5af31c5f-5caf-4109-b160-2c8f0d57b0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25460708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.25460708
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3195963369
Short name T200
Test name
Test status
Simulation time 66783729 ps
CPU time 0.76 seconds
Started Jul 28 05:16:35 PM PDT 24
Finished Jul 28 05:16:36 PM PDT 24
Peak memory 199892 kb
Host smart-0c863c5c-fc0e-4eb9-b76d-54341d33e5f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195963369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3195963369
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1207405328
Short name T268
Test name
Test status
Simulation time 2182183177 ps
CPU time 8.43 seconds
Started Jul 28 05:16:39 PM PDT 24
Finished Jul 28 05:16:48 PM PDT 24
Peak memory 217696 kb
Host smart-d60a850a-7693-44b3-ab46-a7782a208b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207405328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1207405328
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3227082097
Short name T485
Test name
Test status
Simulation time 245366055 ps
CPU time 1.13 seconds
Started Jul 28 05:16:36 PM PDT 24
Finished Jul 28 05:16:37 PM PDT 24
Peak memory 217416 kb
Host smart-b4c5f5c3-2959-471a-9c57-7fe88f3cd371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227082097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3227082097
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2638921183
Short name T15
Test name
Test status
Simulation time 227986539 ps
CPU time 0.9 seconds
Started Jul 28 05:16:39 PM PDT 24
Finished Jul 28 05:16:40 PM PDT 24
Peak memory 199784 kb
Host smart-11114b4e-7891-4318-aec9-6495449036df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638921183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2638921183
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3224379544
Short name T296
Test name
Test status
Simulation time 1116083320 ps
CPU time 4.85 seconds
Started Jul 28 05:16:43 PM PDT 24
Finished Jul 28 05:16:48 PM PDT 24
Peak memory 200340 kb
Host smart-ff7e3a7d-57fc-4d54-865e-3b88f5d275a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224379544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3224379544
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3378948454
Short name T463
Test name
Test status
Simulation time 148200191 ps
CPU time 1.14 seconds
Started Jul 28 05:16:39 PM PDT 24
Finished Jul 28 05:16:40 PM PDT 24
Peak memory 199956 kb
Host smart-0265c4c9-4a85-494a-85af-85ddf8a956c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378948454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3378948454
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1782984951
Short name T528
Test name
Test status
Simulation time 116361738 ps
CPU time 1.22 seconds
Started Jul 28 05:16:44 PM PDT 24
Finished Jul 28 05:16:46 PM PDT 24
Peak memory 200276 kb
Host smart-a2cfc47a-3612-4f8e-a610-4b86fb386a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782984951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1782984951
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1260312034
Short name T336
Test name
Test status
Simulation time 9725990026 ps
CPU time 37.01 seconds
Started Jul 28 05:16:36 PM PDT 24
Finished Jul 28 05:17:13 PM PDT 24
Peak memory 200420 kb
Host smart-626bb2f8-0aa8-466d-bcb8-31a2312d39f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260312034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1260312034
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1466408155
Short name T484
Test name
Test status
Simulation time 124243494 ps
CPU time 1.59 seconds
Started Jul 28 05:16:41 PM PDT 24
Finished Jul 28 05:16:43 PM PDT 24
Peak memory 208208 kb
Host smart-f8ac2143-4da6-4e6e-8e92-c7dd433d4558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466408155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1466408155
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.604405764
Short name T218
Test name
Test status
Simulation time 135999968 ps
CPU time 1.19 seconds
Started Jul 28 05:16:37 PM PDT 24
Finished Jul 28 05:16:38 PM PDT 24
Peak memory 200028 kb
Host smart-b876e470-edd7-4c7a-9532-a6e19d0ed361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604405764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.604405764
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1322943791
Short name T510
Test name
Test status
Simulation time 61122895 ps
CPU time 0.77 seconds
Started Jul 28 05:16:41 PM PDT 24
Finished Jul 28 05:16:42 PM PDT 24
Peak memory 199880 kb
Host smart-889a158a-1da7-4859-b156-64dc35622a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322943791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1322943791
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3100833409
Short name T29
Test name
Test status
Simulation time 2341132447 ps
CPU time 8.67 seconds
Started Jul 28 05:16:32 PM PDT 24
Finished Jul 28 05:16:41 PM PDT 24
Peak memory 221624 kb
Host smart-a8708e01-aea9-4983-90fb-25f2f3e4a58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100833409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3100833409
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1890786384
Short name T475
Test name
Test status
Simulation time 244235086 ps
CPU time 1.1 seconds
Started Jul 28 05:16:42 PM PDT 24
Finished Jul 28 05:16:43 PM PDT 24
Peak memory 217292 kb
Host smart-a8e2fda5-220f-47f2-a989-7c6455436f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890786384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1890786384
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2827209022
Short name T342
Test name
Test status
Simulation time 155323665 ps
CPU time 0.81 seconds
Started Jul 28 05:16:33 PM PDT 24
Finished Jul 28 05:16:34 PM PDT 24
Peak memory 199876 kb
Host smart-47f466fe-9bd1-4e75-95a2-e06fb9176023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827209022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2827209022
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.80856904
Short name T114
Test name
Test status
Simulation time 1825971099 ps
CPU time 7.09 seconds
Started Jul 28 05:16:35 PM PDT 24
Finished Jul 28 05:16:42 PM PDT 24
Peak memory 200296 kb
Host smart-d5ffdd7e-5d60-4c60-b697-8a61c15d58ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80856904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.80856904
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1544876517
Short name T509
Test name
Test status
Simulation time 116198295 ps
CPU time 0.99 seconds
Started Jul 28 05:16:50 PM PDT 24
Finished Jul 28 05:16:51 PM PDT 24
Peak memory 200096 kb
Host smart-81cfd78e-b795-4990-a744-62cb3bbf6125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544876517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1544876517
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.720863990
Short name T488
Test name
Test status
Simulation time 197203276 ps
CPU time 1.42 seconds
Started Jul 28 05:16:38 PM PDT 24
Finished Jul 28 05:16:40 PM PDT 24
Peak memory 200320 kb
Host smart-db2ff2d7-ef20-41af-b423-d85a60f55b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720863990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.720863990
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3663918931
Short name T467
Test name
Test status
Simulation time 10229661617 ps
CPU time 36.72 seconds
Started Jul 28 05:16:41 PM PDT 24
Finished Jul 28 05:17:18 PM PDT 24
Peak memory 208560 kb
Host smart-68150502-f06e-4cb6-9ec4-3558a1428834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663918931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3663918931
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3231950466
Short name T139
Test name
Test status
Simulation time 313909210 ps
CPU time 2.2 seconds
Started Jul 28 05:16:51 PM PDT 24
Finished Jul 28 05:16:53 PM PDT 24
Peak memory 208360 kb
Host smart-ac3dd2a4-f057-4aa7-843c-bb18237ed378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231950466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3231950466
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3711457354
Short name T529
Test name
Test status
Simulation time 125155520 ps
CPU time 0.94 seconds
Started Jul 28 05:16:43 PM PDT 24
Finished Jul 28 05:16:44 PM PDT 24
Peak memory 200052 kb
Host smart-01b1685d-593f-4e16-81fd-a3deb389967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711457354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3711457354
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1773046434
Short name T198
Test name
Test status
Simulation time 69363231 ps
CPU time 0.78 seconds
Started Jul 28 05:16:34 PM PDT 24
Finished Jul 28 05:16:35 PM PDT 24
Peak memory 199780 kb
Host smart-8756fd1f-0fd8-4204-9033-861017e118d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773046434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1773046434
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.125346687
Short name T311
Test name
Test status
Simulation time 1216865508 ps
CPU time 5.48 seconds
Started Jul 28 05:16:39 PM PDT 24
Finished Jul 28 05:16:45 PM PDT 24
Peak memory 217704 kb
Host smart-000dd60a-742b-4f52-b6a9-015525a2c5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125346687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.125346687
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2489414882
Short name T148
Test name
Test status
Simulation time 245407801 ps
CPU time 1.07 seconds
Started Jul 28 05:16:37 PM PDT 24
Finished Jul 28 05:16:38 PM PDT 24
Peak memory 217416 kb
Host smart-d22ecbe0-96dc-4a54-8c58-e42a3ab3769b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489414882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2489414882
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1598008855
Short name T328
Test name
Test status
Simulation time 122688917 ps
CPU time 0.81 seconds
Started Jul 28 05:16:34 PM PDT 24
Finished Jul 28 05:16:35 PM PDT 24
Peak memory 199884 kb
Host smart-d3759405-231e-40e0-b8c5-a183ffd89045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598008855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1598008855
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2083408170
Short name T320
Test name
Test status
Simulation time 1468412280 ps
CPU time 5.52 seconds
Started Jul 28 05:16:36 PM PDT 24
Finished Jul 28 05:16:41 PM PDT 24
Peak memory 200360 kb
Host smart-a37311ce-cb40-4afd-8ce1-55eddf642ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083408170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2083408170
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1990332143
Short name T279
Test name
Test status
Simulation time 180486715 ps
CPU time 1.16 seconds
Started Jul 28 05:16:39 PM PDT 24
Finished Jul 28 05:16:41 PM PDT 24
Peak memory 200076 kb
Host smart-5b8a6c91-7d36-4a65-953f-465d23cb7c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990332143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1990332143
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3508950589
Short name T341
Test name
Test status
Simulation time 220830412 ps
CPU time 1.42 seconds
Started Jul 28 05:16:33 PM PDT 24
Finished Jul 28 05:16:35 PM PDT 24
Peak memory 200284 kb
Host smart-264458f0-4000-4fb0-9f72-0936f0edb71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508950589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3508950589
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1778661359
Short name T128
Test name
Test status
Simulation time 14592227168 ps
CPU time 45.21 seconds
Started Jul 28 05:16:40 PM PDT 24
Finished Jul 28 05:17:26 PM PDT 24
Peak memory 200412 kb
Host smart-717caed3-1abf-4729-9643-fbc5460edaaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778661359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1778661359
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1337296121
Short name T397
Test name
Test status
Simulation time 360443766 ps
CPU time 2.29 seconds
Started Jul 28 05:16:38 PM PDT 24
Finished Jul 28 05:16:41 PM PDT 24
Peak memory 200128 kb
Host smart-5ebf7b8e-2973-46d3-9473-5d290aa0083b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337296121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1337296121
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1936077470
Short name T432
Test name
Test status
Simulation time 150909814 ps
CPU time 1.15 seconds
Started Jul 28 05:16:51 PM PDT 24
Finished Jul 28 05:16:52 PM PDT 24
Peak memory 200216 kb
Host smart-7f78a39e-e005-43a9-9b97-4fc3dc0e6161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936077470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1936077470
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2578749113
Short name T219
Test name
Test status
Simulation time 62076272 ps
CPU time 0.76 seconds
Started Jul 28 05:16:38 PM PDT 24
Finished Jul 28 05:16:39 PM PDT 24
Peak memory 199872 kb
Host smart-bee0aaa3-80da-4089-a4fb-6c8fc41ad6c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578749113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2578749113
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3835871471
Short name T40
Test name
Test status
Simulation time 2186621946 ps
CPU time 8.04 seconds
Started Jul 28 05:16:39 PM PDT 24
Finished Jul 28 05:16:47 PM PDT 24
Peak memory 221664 kb
Host smart-1503b7fc-c4d0-47b8-ab80-4c7802962589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835871471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3835871471
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2331503590
Short name T243
Test name
Test status
Simulation time 244485282 ps
CPU time 1.06 seconds
Started Jul 28 05:16:38 PM PDT 24
Finished Jul 28 05:16:39 PM PDT 24
Peak memory 217392 kb
Host smart-875195e5-9018-4b40-8d75-bd7455848cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331503590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2331503590
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1621989474
Short name T18
Test name
Test status
Simulation time 148195653 ps
CPU time 0.88 seconds
Started Jul 28 05:16:34 PM PDT 24
Finished Jul 28 05:16:35 PM PDT 24
Peak memory 200148 kb
Host smart-bc5c8a96-06f9-492d-88b8-ce101cfac8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621989474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1621989474
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.4215135817
Short name T242
Test name
Test status
Simulation time 694826766 ps
CPU time 4.05 seconds
Started Jul 28 05:16:35 PM PDT 24
Finished Jul 28 05:16:40 PM PDT 24
Peak memory 200588 kb
Host smart-ed1473f0-5faf-45ea-b3ac-214d1fe71e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215135817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.4215135817
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.269776838
Short name T520
Test name
Test status
Simulation time 168446191 ps
CPU time 1.14 seconds
Started Jul 28 05:16:37 PM PDT 24
Finished Jul 28 05:16:38 PM PDT 24
Peak memory 200028 kb
Host smart-d7015fef-c093-4f76-82a4-ba717b58d707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269776838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.269776838
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.409764127
Short name T141
Test name
Test status
Simulation time 127492337 ps
CPU time 1.16 seconds
Started Jul 28 05:16:56 PM PDT 24
Finished Jul 28 05:16:57 PM PDT 24
Peak memory 200324 kb
Host smart-bb0fba4e-f295-4c19-8cbd-9de64e43c5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409764127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.409764127
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1960012761
Short name T353
Test name
Test status
Simulation time 4107320664 ps
CPU time 16.26 seconds
Started Jul 28 05:16:45 PM PDT 24
Finished Jul 28 05:17:01 PM PDT 24
Peak memory 200408 kb
Host smart-ea0e9e99-46ae-4672-a4b1-707842fa9f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960012761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1960012761
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2176869908
Short name T178
Test name
Test status
Simulation time 369865704 ps
CPU time 2.08 seconds
Started Jul 28 05:16:43 PM PDT 24
Finished Jul 28 05:16:50 PM PDT 24
Peak memory 200080 kb
Host smart-22fcfc1e-eda2-44f9-8962-b444e597dedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176869908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2176869908
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1407074971
Short name T325
Test name
Test status
Simulation time 86999792 ps
CPU time 0.83 seconds
Started Jul 28 05:16:33 PM PDT 24
Finished Jul 28 05:16:34 PM PDT 24
Peak memory 199976 kb
Host smart-705b5e51-f401-4910-8640-5951769970de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407074971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1407074971
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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