Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8902

1

T1

39

T3

22

T4

313

auto[1]

11853

1

T1

25

T3

79

T4

317

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6375	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	7034	1			T1	26		T2	1		T3	27
reset_info_cp[2]	3212	1			T1	8		T3	13		T4	90
reset_info_cp[4]	4158	1			T1	17		T3	16		T4	133
reset_info_cp[8]	110	1			T3	3		T4	4		T6	1
reset_info_cp[16]	117	1			T4	6		T9	1		T37	1
reset_info_cp[32]	113	1			T4	2		T9	1		T39	2
reset_info_cp[64]	134	1			T3	2		T4	2		T9	1
reset_info_cp[128]	122	1			T4	4		T9	2		T37	3

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3352	1			T1	13		T3	22		T4	97
reset_info_cp[1]	auto[1]	3062	1			T1	12		T3	4		T4	124
reset_info_cp[2]	auto[0]	1069	1			T1	4		T4	40		T9	20
reset_info_cp[2]	auto[1]	2143	1			T1	4		T3	13		T4	50
reset_info_cp[4]	auto[0]	1475	1			T1	12		T4	64		T9	36
reset_info_cp[4]	auto[1]	2683	1			T1	5		T3	16		T4	69
reset_info_cp[8]	auto[0]	43	1			T4	3		T6	1		T74	1
reset_info_cp[8]	auto[1]	67	1			T3	3		T4	1		T9	1
reset_info_cp[16]	auto[0]	40	1			T4	2		T9	1		T74	1
reset_info_cp[16]	auto[1]	77	1			T4	4		T37	1		T24	1
reset_info_cp[32]	auto[0]	58	1			T4	2		T75	1		T76	1
reset_info_cp[32]	auto[1]	55	1			T9	1		T39	2		T25	1
reset_info_cp[64]	auto[0]	58	1			T4	1		T9	1		T23	1
reset_info_cp[64]	auto[1]	76	1			T3	2		T4	1		T25	2
reset_info_cp[128]	auto[0]	39	1			T4	1		T76	1		T79	1
reset_info_cp[128]	auto[1]	83	1			T4	3		T9	2		T37	3