Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T534 /workspace/coverage/default/17.rstmgr_sw_rst.4014050767 Jul 30 04:57:17 PM PDT 24 Jul 30 04:57:19 PM PDT 24 342702695 ps
T535 /workspace/coverage/default/13.rstmgr_por_stretcher.2248652605 Jul 30 04:56:55 PM PDT 24 Jul 30 04:56:56 PM PDT 24 166197470 ps
T536 /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1459022961 Jul 30 04:58:36 PM PDT 24 Jul 30 04:58:37 PM PDT 24 98691464 ps
T537 /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.860960233 Jul 30 04:58:02 PM PDT 24 Jul 30 04:58:03 PM PDT 24 244524182 ps
T538 /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1142801706 Jul 30 04:58:36 PM PDT 24 Jul 30 04:58:38 PM PDT 24 244125219 ps
T53 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3787999122 Jul 30 04:48:49 PM PDT 24 Jul 30 04:48:51 PM PDT 24 303414905 ps
T49 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.217638728 Jul 30 04:48:30 PM PDT 24 Jul 30 04:48:31 PM PDT 24 70249100 ps
T50 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1424144778 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:30 PM PDT 24 244826240 ps
T51 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1036858290 Jul 30 04:48:36 PM PDT 24 Jul 30 04:48:38 PM PDT 24 160606554 ps
T52 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3933238787 Jul 30 04:48:47 PM PDT 24 Jul 30 04:48:48 PM PDT 24 91749025 ps
T54 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2890265042 Jul 30 04:48:34 PM PDT 24 Jul 30 04:48:35 PM PDT 24 159823127 ps
T85 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3186164823 Jul 30 04:48:35 PM PDT 24 Jul 30 04:48:35 PM PDT 24 57582843 ps
T77 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.317904306 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:21 PM PDT 24 82082949 ps
T61 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3090245060 Jul 30 04:48:49 PM PDT 24 Jul 30 04:48:51 PM PDT 24 207900263 ps
T55 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.932834190 Jul 30 04:48:30 PM PDT 24 Jul 30 04:48:33 PM PDT 24 878130934 ps
T66 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2344231901 Jul 30 04:48:43 PM PDT 24 Jul 30 04:48:45 PM PDT 24 128453547 ps
T56 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.101292550 Jul 30 04:48:24 PM PDT 24 Jul 30 04:48:27 PM PDT 24 763625455 ps
T539 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3264021625 Jul 30 04:48:38 PM PDT 24 Jul 30 04:48:48 PM PDT 24 1983138819 ps
T540 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3567995775 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:23 PM PDT 24 276486075 ps
T541 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.606535889 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:21 PM PDT 24 76241003 ps
T67 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2896408170 Jul 30 04:48:40 PM PDT 24 Jul 30 04:48:43 PM PDT 24 769086503 ps
T542 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.693058360 Jul 30 04:48:31 PM PDT 24 Jul 30 04:48:32 PM PDT 24 113870640 ps
T68 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3527471372 Jul 30 04:48:26 PM PDT 24 Jul 30 04:48:29 PM PDT 24 217653095 ps
T86 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.219921747 Jul 30 04:48:49 PM PDT 24 Jul 30 04:48:50 PM PDT 24 67939460 ps
T69 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4099583379 Jul 30 04:48:46 PM PDT 24 Jul 30 04:48:48 PM PDT 24 263866904 ps
T70 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1794565817 Jul 30 04:48:42 PM PDT 24 Jul 30 04:48:46 PM PDT 24 926089651 ps
T543 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2652009716 Jul 30 04:48:22 PM PDT 24 Jul 30 04:48:24 PM PDT 24 99448929 ps
T71 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2510158641 Jul 30 04:48:31 PM PDT 24 Jul 30 04:48:33 PM PDT 24 471960752 ps
T72 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3790738956 Jul 30 04:48:32 PM PDT 24 Jul 30 04:48:34 PM PDT 24 470079696 ps
T97 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3664584574 Jul 30 04:48:34 PM PDT 24 Jul 30 04:48:37 PM PDT 24 401537701 ps
T544 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.203162801 Jul 30 04:48:53 PM PDT 24 Jul 30 04:48:55 PM PDT 24 298076803 ps
T87 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1392120023 Jul 30 04:48:43 PM PDT 24 Jul 30 04:48:44 PM PDT 24 71480762 ps
T545 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1070328022 Jul 30 04:48:34 PM PDT 24 Jul 30 04:48:35 PM PDT 24 120694078 ps
T546 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3519822343 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:30 PM PDT 24 107951614 ps
T547 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.614788555 Jul 30 04:48:45 PM PDT 24 Jul 30 04:48:47 PM PDT 24 126874391 ps
T548 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2885068144 Jul 30 04:48:46 PM PDT 24 Jul 30 04:48:47 PM PDT 24 142232853 ps
T88 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.301507354 Jul 30 04:48:32 PM PDT 24 Jul 30 04:48:33 PM PDT 24 79207135 ps
T95 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1163397162 Jul 30 04:48:35 PM PDT 24 Jul 30 04:48:38 PM PDT 24 875907654 ps
T549 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1349774424 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:26 PM PDT 24 124907340 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4093734697 Jul 30 04:48:17 PM PDT 24 Jul 30 04:48:20 PM PDT 24 414915244 ps
T551 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1154634651 Jul 30 04:48:35 PM PDT 24 Jul 30 04:48:36 PM PDT 24 201156392 ps
T552 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1256166165 Jul 30 04:48:42 PM PDT 24 Jul 30 04:48:44 PM PDT 24 252195315 ps
T553 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2788082437 Jul 30 04:48:36 PM PDT 24 Jul 30 04:48:38 PM PDT 24 182957534 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2039221069 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:22 PM PDT 24 72326682 ps
T89 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.759031945 Jul 30 04:48:54 PM PDT 24 Jul 30 04:48:55 PM PDT 24 82491957 ps
T94 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2588756360 Jul 30 04:48:35 PM PDT 24 Jul 30 04:48:38 PM PDT 24 818876648 ps
T555 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.548248538 Jul 30 04:48:32 PM PDT 24 Jul 30 04:48:33 PM PDT 24 105369821 ps
T556 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.636697168 Jul 30 04:48:40 PM PDT 24 Jul 30 04:48:48 PM PDT 24 1537131934 ps
T110 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1224298010 Jul 30 04:48:51 PM PDT 24 Jul 30 04:48:53 PM PDT 24 470037150 ps
T90 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2795689933 Jul 30 04:48:37 PM PDT 24 Jul 30 04:48:38 PM PDT 24 75492778 ps
T557 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2766878352 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:25 PM PDT 24 461708827 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1330251674 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:27 PM PDT 24 201441121 ps
T111 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1749592893 Jul 30 04:48:52 PM PDT 24 Jul 30 04:48:54 PM PDT 24 479609161 ps
T559 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3735336983 Jul 30 04:48:37 PM PDT 24 Jul 30 04:48:38 PM PDT 24 155119434 ps
T560 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1195176757 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:23 PM PDT 24 117324610 ps
T561 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2376717583 Jul 30 04:48:47 PM PDT 24 Jul 30 04:48:48 PM PDT 24 121233579 ps
T562 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.672697145 Jul 30 04:48:41 PM PDT 24 Jul 30 04:48:44 PM PDT 24 485783400 ps
T563 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1975423444 Jul 30 04:48:58 PM PDT 24 Jul 30 04:49:00 PM PDT 24 96572019 ps
T91 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2441351918 Jul 30 04:48:39 PM PDT 24 Jul 30 04:48:40 PM PDT 24 69910504 ps
T564 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.980245675 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:32 PM PDT 24 466281605 ps
T565 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2712790040 Jul 30 04:48:17 PM PDT 24 Jul 30 04:48:19 PM PDT 24 120165769 ps
T566 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1923429628 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:29 PM PDT 24 83606591 ps
T567 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1486289518 Jul 30 04:48:41 PM PDT 24 Jul 30 04:48:44 PM PDT 24 595905915 ps
T568 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2494519028 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:30 PM PDT 24 62414076 ps
T92 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3680735485 Jul 30 04:48:37 PM PDT 24 Jul 30 04:48:39 PM PDT 24 469500338 ps
T109 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.711989990 Jul 30 04:48:37 PM PDT 24 Jul 30 04:48:40 PM PDT 24 480905655 ps
T569 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3897769392 Jul 30 04:48:32 PM PDT 24 Jul 30 04:48:33 PM PDT 24 93249639 ps
T570 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1031378937 Jul 30 04:48:19 PM PDT 24 Jul 30 04:48:21 PM PDT 24 248702864 ps
T571 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1846996443 Jul 30 04:48:35 PM PDT 24 Jul 30 04:48:37 PM PDT 24 100361771 ps
T572 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2990941182 Jul 30 04:48:34 PM PDT 24 Jul 30 04:48:35 PM PDT 24 65914348 ps
T573 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4227052731 Jul 30 04:48:47 PM PDT 24 Jul 30 04:48:50 PM PDT 24 305151357 ps
T574 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4236350746 Jul 30 04:48:41 PM PDT 24 Jul 30 04:48:43 PM PDT 24 312541630 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1732936253 Jul 30 04:48:30 PM PDT 24 Jul 30 04:48:31 PM PDT 24 82689558 ps
T576 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3252180026 Jul 30 04:48:38 PM PDT 24 Jul 30 04:48:39 PM PDT 24 65910018 ps
T577 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.140992422 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:22 PM PDT 24 128983584 ps
T578 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.713842536 Jul 30 04:48:17 PM PDT 24 Jul 30 04:48:19 PM PDT 24 258648226 ps
T579 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2809476842 Jul 30 04:48:31 PM PDT 24 Jul 30 04:48:32 PM PDT 24 77318574 ps
T580 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.153127614 Jul 30 04:48:32 PM PDT 24 Jul 30 04:48:33 PM PDT 24 133326801 ps
T581 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2914318381 Jul 30 04:48:41 PM PDT 24 Jul 30 04:48:43 PM PDT 24 162081992 ps
T582 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1963365737 Jul 30 04:48:47 PM PDT 24 Jul 30 04:48:48 PM PDT 24 83661672 ps
T583 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1904037102 Jul 30 04:48:39 PM PDT 24 Jul 30 04:48:41 PM PDT 24 250776721 ps
T584 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1201790098 Jul 30 04:48:34 PM PDT 24 Jul 30 04:48:35 PM PDT 24 109030882 ps
T96 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2069892506 Jul 30 04:48:31 PM PDT 24 Jul 30 04:48:34 PM PDT 24 775028925 ps
T585 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3651213003 Jul 30 04:48:18 PM PDT 24 Jul 30 04:48:20 PM PDT 24 228946270 ps
T586 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2107833600 Jul 30 04:48:44 PM PDT 24 Jul 30 04:48:45 PM PDT 24 64813993 ps
T587 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.14085900 Jul 30 04:48:41 PM PDT 24 Jul 30 04:48:42 PM PDT 24 79319703 ps
T588 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3741814066 Jul 30 04:48:43 PM PDT 24 Jul 30 04:48:45 PM PDT 24 103784105 ps
T589 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3005603392 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:31 PM PDT 24 794039556 ps
T590 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3552522435 Jul 30 04:48:46 PM PDT 24 Jul 30 04:48:48 PM PDT 24 113866134 ps
T591 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2560004087 Jul 30 04:48:54 PM PDT 24 Jul 30 04:48:56 PM PDT 24 233081197 ps
T592 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1906093085 Jul 30 04:48:51 PM PDT 24 Jul 30 04:48:52 PM PDT 24 245489287 ps
T593 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.709661266 Jul 30 04:48:51 PM PDT 24 Jul 30 04:48:53 PM PDT 24 321857619 ps
T594 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.342111332 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:24 PM PDT 24 424239026 ps
T595 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4192079685 Jul 30 04:48:18 PM PDT 24 Jul 30 04:48:19 PM PDT 24 98289570 ps
T596 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2352362924 Jul 30 04:48:42 PM PDT 24 Jul 30 04:48:42 PM PDT 24 63612087 ps
T597 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3144007796 Jul 30 04:48:32 PM PDT 24 Jul 30 04:48:34 PM PDT 24 130999737 ps
T598 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2240771808 Jul 30 04:48:17 PM PDT 24 Jul 30 04:48:18 PM PDT 24 148535103 ps
T599 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.48374740 Jul 30 04:48:39 PM PDT 24 Jul 30 04:48:45 PM PDT 24 491906460 ps
T600 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2545392725 Jul 30 04:48:54 PM PDT 24 Jul 30 04:48:56 PM PDT 24 157321429 ps
T601 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1708820334 Jul 30 04:48:35 PM PDT 24 Jul 30 04:48:38 PM PDT 24 304457586 ps
T602 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.452586766 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:22 PM PDT 24 138905591 ps
T603 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4176064665 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:37 PM PDT 24 1553591751 ps
T604 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2099893197 Jul 30 04:48:57 PM PDT 24 Jul 30 04:49:00 PM PDT 24 784912065 ps
T605 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2565177037 Jul 30 04:48:44 PM PDT 24 Jul 30 04:48:45 PM PDT 24 127113225 ps
T606 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1851596876 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:26 PM PDT 24 89282908 ps
T93 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.775672590 Jul 30 04:48:48 PM PDT 24 Jul 30 04:48:50 PM PDT 24 471580974 ps
T607 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2298454212 Jul 30 04:48:54 PM PDT 24 Jul 30 04:48:55 PM PDT 24 76624430 ps
T608 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1644285269 Jul 30 04:48:31 PM PDT 24 Jul 30 04:48:32 PM PDT 24 67939774 ps
T609 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1118309153 Jul 30 04:48:45 PM PDT 24 Jul 30 04:48:49 PM PDT 24 1013989403 ps
T610 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.687733019 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:29 PM PDT 24 104829066 ps
T611 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2442305086 Jul 30 04:48:53 PM PDT 24 Jul 30 04:48:54 PM PDT 24 94441851 ps
T612 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.723003421 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:30 PM PDT 24 152400167 ps
T613 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3044851754 Jul 30 04:48:34 PM PDT 24 Jul 30 04:48:37 PM PDT 24 794286100 ps
T614 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.63085046 Jul 30 04:48:32 PM PDT 24 Jul 30 04:48:33 PM PDT 24 145325650 ps
T615 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1925359348 Jul 30 04:48:26 PM PDT 24 Jul 30 04:48:28 PM PDT 24 168942317 ps
T616 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3755838659 Jul 30 04:48:25 PM PDT 24 Jul 30 04:48:29 PM PDT 24 542127130 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2381514922 Jul 30 04:48:25 PM PDT 24 Jul 30 04:48:26 PM PDT 24 86700314 ps
T618 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2611075403 Jul 30 04:48:45 PM PDT 24 Jul 30 04:48:46 PM PDT 24 134273050 ps
T619 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2355095505 Jul 30 04:48:44 PM PDT 24 Jul 30 04:48:46 PM PDT 24 276283267 ps
T620 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3564991112 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:31 PM PDT 24 200278840 ps

Test location /workspace/coverage/default/23.rstmgr_stress_all.171869404
Short name T4
Test name
Test status
Simulation time 17122209894 ps
CPU time 70.54 seconds
Started Jul 30 04:57:46 PM PDT 24
Finished Jul 30 04:58:57 PM PDT 24
Peak memory 208748 kb
Host smart-6769364f-19ad-4052-99e3-15caec0029cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171869404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.171869404
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2711385232
Short name T48
Test name
Test status
Simulation time 493241141 ps
CPU time 2.66 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:49 PM PDT 24
Peak memory 200256 kb
Host smart-a77b6270-91b1-49b9-9978-f926cf40be2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711385232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2711385232
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2344231901
Short name T66
Test name
Test status
Simulation time 128453547 ps
CPU time 1.42 seconds
Started Jul 30 04:48:43 PM PDT 24
Finished Jul 30 04:48:45 PM PDT 24
Peak memory 208280 kb
Host smart-1f5fb0e0-be8b-4ea5-879c-d41b800112ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344231901 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2344231901
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.4046602743
Short name T2
Test name
Test status
Simulation time 16518837122 ps
CPU time 31.17 seconds
Started Jul 30 04:55:35 PM PDT 24
Finished Jul 30 04:56:06 PM PDT 24
Peak memory 217360 kb
Host smart-e98bdb84-bc2e-4834-af42-088331a4401d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046602743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4046602743
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.633666348
Short name T25
Test name
Test status
Simulation time 1892680831 ps
CPU time 6.92 seconds
Started Jul 30 04:57:50 PM PDT 24
Finished Jul 30 04:57:57 PM PDT 24
Peak memory 217652 kb
Host smart-dcfd7ef1-e5d6-4424-9d70-9ea90998d63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633666348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.633666348
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1794565817
Short name T70
Test name
Test status
Simulation time 926089651 ps
CPU time 3.18 seconds
Started Jul 30 04:48:42 PM PDT 24
Finished Jul 30 04:48:46 PM PDT 24
Peak memory 200128 kb
Host smart-45bfafeb-df41-4c0b-84ce-221b86ebd4af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794565817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1794565817
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1505110544
Short name T117
Test name
Test status
Simulation time 91690386 ps
CPU time 0.83 seconds
Started Jul 30 04:56:03 PM PDT 24
Finished Jul 30 04:56:04 PM PDT 24
Peak memory 199980 kb
Host smart-1ea5aa36-fe49-4695-bd32-aecb65185f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505110544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1505110544
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.4136921584
Short name T126
Test name
Test status
Simulation time 111572731 ps
CPU time 1.06 seconds
Started Jul 30 04:57:24 PM PDT 24
Finished Jul 30 04:57:25 PM PDT 24
Peak memory 200312 kb
Host smart-23f14c18-d40b-47a7-9e20-7631c040daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136921584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.4136921584
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3787999122
Short name T53
Test name
Test status
Simulation time 303414905 ps
CPU time 2.32 seconds
Started Jul 30 04:48:49 PM PDT 24
Finished Jul 30 04:48:51 PM PDT 24
Peak memory 216176 kb
Host smart-428e643c-707e-4586-83de-d77c50b5177e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787999122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3787999122
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1077609673
Short name T26
Test name
Test status
Simulation time 1897623730 ps
CPU time 8.16 seconds
Started Jul 30 04:58:27 PM PDT 24
Finished Jul 30 04:58:35 PM PDT 24
Peak memory 217676 kb
Host smart-e898204c-f8ca-4e55-afc5-4546a362cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077609673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1077609673
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3186164823
Short name T85
Test name
Test status
Simulation time 57582843 ps
CPU time 0.76 seconds
Started Jul 30 04:48:35 PM PDT 24
Finished Jul 30 04:48:35 PM PDT 24
Peak memory 199884 kb
Host smart-945a32f5-3652-4478-b2bd-9c68b7ae3fb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186164823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3186164823
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2021749580
Short name T79
Test name
Test status
Simulation time 10076030340 ps
CPU time 35.06 seconds
Started Jul 30 04:57:01 PM PDT 24
Finished Jul 30 04:57:36 PM PDT 24
Peak memory 200508 kb
Host smart-7e76e622-5dbf-4334-bc05-65c607d81787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021749580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2021749580
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.685395109
Short name T35
Test name
Test status
Simulation time 1888803830 ps
CPU time 7.47 seconds
Started Jul 30 04:57:57 PM PDT 24
Finished Jul 30 04:58:04 PM PDT 24
Peak memory 217636 kb
Host smart-ab36681e-ca6b-4513-8e81-68ff4f03a6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685395109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.685395109
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3230604690
Short name T105
Test name
Test status
Simulation time 199910390 ps
CPU time 1.23 seconds
Started Jul 30 04:56:56 PM PDT 24
Finished Jul 30 04:56:57 PM PDT 24
Peak memory 200236 kb
Host smart-8d88e39e-3da5-4bc3-904c-23b05c1f1dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230604690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3230604690
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.775672590
Short name T93
Test name
Test status
Simulation time 471580974 ps
CPU time 2.09 seconds
Started Jul 30 04:48:48 PM PDT 24
Finished Jul 30 04:48:50 PM PDT 24
Peak memory 200000 kb
Host smart-3b128a2a-7d28-40e3-8adc-09683bc4aa8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775672590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.775672590
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2151214434
Short name T19
Test name
Test status
Simulation time 141037353 ps
CPU time 0.83 seconds
Started Jul 30 04:55:33 PM PDT 24
Finished Jul 30 04:55:34 PM PDT 24
Peak memory 199980 kb
Host smart-37c46d68-5a44-4615-b1c0-06d572d01bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151214434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2151214434
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.938053579
Short name T44
Test name
Test status
Simulation time 155122016 ps
CPU time 1.89 seconds
Started Jul 30 04:57:05 PM PDT 24
Finished Jul 30 04:57:07 PM PDT 24
Peak memory 200068 kb
Host smart-1f1ed724-d671-406c-beea-aa869ce5521e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938053579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.938053579
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.713842536
Short name T578
Test name
Test status
Simulation time 258648226 ps
CPU time 1.72 seconds
Started Jul 30 04:48:17 PM PDT 24
Finished Jul 30 04:48:19 PM PDT 24
Peak memory 208208 kb
Host smart-4446a4de-3459-43dd-a655-6e352aaa2cb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713842536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.713842536
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3567995775
Short name T540
Test name
Test status
Simulation time 276486075 ps
CPU time 3 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:23 PM PDT 24
Peak memory 200044 kb
Host smart-9bd2bb4a-6eaf-4c5e-b37d-e40e701b4abb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567995775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
567995775
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3933238787
Short name T52
Test name
Test status
Simulation time 91749025 ps
CPU time 0.8 seconds
Started Jul 30 04:48:47 PM PDT 24
Finished Jul 30 04:48:48 PM PDT 24
Peak memory 199888 kb
Host smart-a52bec42-8754-4f2d-a58f-e3184513a210
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933238787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
933238787
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2712790040
Short name T565
Test name
Test status
Simulation time 120165769 ps
CPU time 1.04 seconds
Started Jul 30 04:48:17 PM PDT 24
Finished Jul 30 04:48:19 PM PDT 24
Peak memory 199904 kb
Host smart-0d24f609-9067-4ee5-b966-90a42c526076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712790040 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2712790040
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3252180026
Short name T576
Test name
Test status
Simulation time 65910018 ps
CPU time 0.9 seconds
Started Jul 30 04:48:38 PM PDT 24
Finished Jul 30 04:48:39 PM PDT 24
Peak memory 199884 kb
Host smart-00758688-3cb3-4d2a-9b25-ebfd02372457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252180026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3252180026
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1031378937
Short name T570
Test name
Test status
Simulation time 248702864 ps
CPU time 1.61 seconds
Started Jul 30 04:48:19 PM PDT 24
Finished Jul 30 04:48:21 PM PDT 24
Peak memory 200020 kb
Host smart-cd1d273e-8cda-4cd8-9d2a-c12cb1a992f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031378937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1031378937
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4093734697
Short name T550
Test name
Test status
Simulation time 414915244 ps
CPU time 2.89 seconds
Started Jul 30 04:48:17 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 211712 kb
Host smart-2984e621-7d7e-44ab-b4e9-5dd8cac2e895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093734697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.4093734697
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2510158641
Short name T71
Test name
Test status
Simulation time 471960752 ps
CPU time 1.83 seconds
Started Jul 30 04:48:31 PM PDT 24
Finished Jul 30 04:48:33 PM PDT 24
Peak memory 200040 kb
Host smart-fb18ae30-11b0-4f2f-8c2d-9987e2f8e050
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510158641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2510158641
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.693058360
Short name T542
Test name
Test status
Simulation time 113870640 ps
CPU time 1.4 seconds
Started Jul 30 04:48:31 PM PDT 24
Finished Jul 30 04:48:32 PM PDT 24
Peak memory 200000 kb
Host smart-f010011a-d8c1-41b1-bdc4-b0d90b5b3a9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693058360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.693058360
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3264021625
Short name T539
Test name
Test status
Simulation time 1983138819 ps
CPU time 10.04 seconds
Started Jul 30 04:48:38 PM PDT 24
Finished Jul 30 04:48:48 PM PDT 24
Peak memory 199912 kb
Host smart-3d5addf1-b80f-46a2-bff6-5c4ab039f081
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264021625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
264021625
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.723003421
Short name T612
Test name
Test status
Simulation time 152400167 ps
CPU time 1.03 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 199952 kb
Host smart-aaf77e16-7a43-4a59-ac0c-b5d4ca7d4b63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723003421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.723003421
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1925359348
Short name T615
Test name
Test status
Simulation time 168942317 ps
CPU time 1.5 seconds
Started Jul 30 04:48:26 PM PDT 24
Finished Jul 30 04:48:28 PM PDT 24
Peak memory 208272 kb
Host smart-004019f6-3ab9-4b80-9283-13721c77a06d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925359348 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1925359348
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2039221069
Short name T554
Test name
Test status
Simulation time 72326682 ps
CPU time 0.77 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:22 PM PDT 24
Peak memory 199768 kb
Host smart-64bb3aa1-82cb-4aa0-ac01-a8ff939833cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039221069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2039221069
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1732936253
Short name T575
Test name
Test status
Simulation time 82689558 ps
CPU time 0.94 seconds
Started Jul 30 04:48:30 PM PDT 24
Finished Jul 30 04:48:31 PM PDT 24
Peak memory 199916 kb
Host smart-be3bbd02-889f-4fe6-a62e-64132b9191da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732936253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1732936253
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.980245675
Short name T564
Test name
Test status
Simulation time 466281605 ps
CPU time 3.12 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:32 PM PDT 24
Peak memory 208244 kb
Host smart-39df065c-f158-4a30-8d16-2f89e8bbc7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980245675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.980245675
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3790738956
Short name T72
Test name
Test status
Simulation time 470079696 ps
CPU time 1.9 seconds
Started Jul 30 04:48:32 PM PDT 24
Finished Jul 30 04:48:34 PM PDT 24
Peak memory 200112 kb
Host smart-a735f057-4add-41f3-8357-45a609769b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790738956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3790738956
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.548248538
Short name T555
Test name
Test status
Simulation time 105369821 ps
CPU time 1.1 seconds
Started Jul 30 04:48:32 PM PDT 24
Finished Jul 30 04:48:33 PM PDT 24
Peak memory 208176 kb
Host smart-f39e153d-13e9-42ba-b24e-2ba1785af179
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548248538 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.548248538
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3741814066
Short name T588
Test name
Test status
Simulation time 103784105 ps
CPU time 1.24 seconds
Started Jul 30 04:48:43 PM PDT 24
Finished Jul 30 04:48:45 PM PDT 24
Peak memory 200052 kb
Host smart-68866866-82f6-47b4-8e02-4fe567813ad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741814066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3741814066
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.709661266
Short name T593
Test name
Test status
Simulation time 321857619 ps
CPU time 2.35 seconds
Started Jul 30 04:48:51 PM PDT 24
Finished Jul 30 04:48:53 PM PDT 24
Peak memory 208188 kb
Host smart-e23417b8-01db-4ae3-a35f-930beff9d8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709661266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.709661266
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2069892506
Short name T96
Test name
Test status
Simulation time 775028925 ps
CPU time 2.74 seconds
Started Jul 30 04:48:31 PM PDT 24
Finished Jul 30 04:48:34 PM PDT 24
Peak memory 200132 kb
Host smart-155555dc-4ebe-4248-9cad-07bce4af0ebc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069892506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2069892506
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2611075403
Short name T618
Test name
Test status
Simulation time 134273050 ps
CPU time 1.41 seconds
Started Jul 30 04:48:45 PM PDT 24
Finished Jul 30 04:48:46 PM PDT 24
Peak memory 208344 kb
Host smart-a435c8d8-758d-4a4f-a891-c811f8eca9af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611075403 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2611075403
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2990941182
Short name T572
Test name
Test status
Simulation time 65914348 ps
CPU time 0.77 seconds
Started Jul 30 04:48:34 PM PDT 24
Finished Jul 30 04:48:35 PM PDT 24
Peak memory 199904 kb
Host smart-d8964c73-674c-482e-a003-71b845343134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990941182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2990941182
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1963365737
Short name T582
Test name
Test status
Simulation time 83661672 ps
CPU time 1.05 seconds
Started Jul 30 04:48:47 PM PDT 24
Finished Jul 30 04:48:48 PM PDT 24
Peak memory 200052 kb
Host smart-3cdafa37-3a44-46b6-b0c7-d9d66ea756ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963365737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1963365737
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3527471372
Short name T68
Test name
Test status
Simulation time 217653095 ps
CPU time 3.32 seconds
Started Jul 30 04:48:26 PM PDT 24
Finished Jul 30 04:48:29 PM PDT 24
Peak memory 208120 kb
Host smart-f6bbf354-1c34-4923-99a3-be910ef7f36c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527471372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3527471372
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3680735485
Short name T92
Test name
Test status
Simulation time 469500338 ps
CPU time 2.13 seconds
Started Jul 30 04:48:37 PM PDT 24
Finished Jul 30 04:48:39 PM PDT 24
Peak memory 200128 kb
Host smart-ce5febbf-3348-47c4-bd4a-59b08c6e5b42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680735485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3680735485
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2376717583
Short name T561
Test name
Test status
Simulation time 121233579 ps
CPU time 1.46 seconds
Started Jul 30 04:48:47 PM PDT 24
Finished Jul 30 04:48:48 PM PDT 24
Peak memory 208308 kb
Host smart-a006dd6c-5080-4f38-af98-0a501b560acc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376717583 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2376717583
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3897769392
Short name T569
Test name
Test status
Simulation time 93249639 ps
CPU time 0.87 seconds
Started Jul 30 04:48:32 PM PDT 24
Finished Jul 30 04:48:33 PM PDT 24
Peak memory 199908 kb
Host smart-991706be-a894-49e9-93a4-003b58d0e180
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897769392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3897769392
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1904037102
Short name T583
Test name
Test status
Simulation time 250776721 ps
CPU time 1.6 seconds
Started Jul 30 04:48:39 PM PDT 24
Finished Jul 30 04:48:41 PM PDT 24
Peak memory 200028 kb
Host smart-522eb0f8-3211-4432-8723-f2eb56ace7d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904037102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1904037102
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3664584574
Short name T97
Test name
Test status
Simulation time 401537701 ps
CPU time 2.71 seconds
Started Jul 30 04:48:34 PM PDT 24
Finished Jul 30 04:48:37 PM PDT 24
Peak memory 208140 kb
Host smart-2a9e6d7c-229b-4615-8379-89c85a56259d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664584574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3664584574
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.711989990
Short name T109
Test name
Test status
Simulation time 480905655 ps
CPU time 2.12 seconds
Started Jul 30 04:48:37 PM PDT 24
Finished Jul 30 04:48:40 PM PDT 24
Peak memory 200140 kb
Host smart-ebea6dd3-62ef-4e56-8eb3-4cd47f3f905e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711989990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.711989990
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.614788555
Short name T547
Test name
Test status
Simulation time 126874391 ps
CPU time 1.45 seconds
Started Jul 30 04:48:45 PM PDT 24
Finished Jul 30 04:48:47 PM PDT 24
Peak memory 208252 kb
Host smart-d50451a2-d305-4f93-bf23-008fd35d6992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614788555 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.614788555
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.219921747
Short name T86
Test name
Test status
Simulation time 67939460 ps
CPU time 0.79 seconds
Started Jul 30 04:48:49 PM PDT 24
Finished Jul 30 04:48:50 PM PDT 24
Peak memory 199920 kb
Host smart-e034c12f-3cee-442b-8a92-dbece015e66f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219921747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.219921747
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.759031945
Short name T89
Test name
Test status
Simulation time 82491957 ps
CPU time 0.96 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:48:55 PM PDT 24
Peak memory 200004 kb
Host smart-8dca91c2-fa3f-4cf1-85be-7f6eab11616c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759031945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.759031945
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2890265042
Short name T54
Test name
Test status
Simulation time 159823127 ps
CPU time 1.39 seconds
Started Jul 30 04:48:34 PM PDT 24
Finished Jul 30 04:48:35 PM PDT 24
Peak memory 199940 kb
Host smart-a189a581-35dc-4d1b-9d30-27a82d3b37c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890265042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2890265042
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2885068144
Short name T548
Test name
Test status
Simulation time 142232853 ps
CPU time 1.14 seconds
Started Jul 30 04:48:46 PM PDT 24
Finished Jul 30 04:48:47 PM PDT 24
Peak memory 208180 kb
Host smart-329a4276-710a-46a2-b76d-8cdd74561df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885068144 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2885068144
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2809476842
Short name T579
Test name
Test status
Simulation time 77318574 ps
CPU time 0.84 seconds
Started Jul 30 04:48:31 PM PDT 24
Finished Jul 30 04:48:32 PM PDT 24
Peak memory 199856 kb
Host smart-de7a1338-2f40-4684-945c-1b16ebd796de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809476842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2809476842
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2545392725
Short name T600
Test name
Test status
Simulation time 157321429 ps
CPU time 1.34 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:48:56 PM PDT 24
Peak memory 200000 kb
Host smart-7c020e01-8dff-4712-b6f6-9a1caf96bb9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545392725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2545392725
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.672697145
Short name T562
Test name
Test status
Simulation time 485783400 ps
CPU time 3.52 seconds
Started Jul 30 04:48:41 PM PDT 24
Finished Jul 30 04:48:44 PM PDT 24
Peak memory 211292 kb
Host smart-ff0220a0-3c90-4011-8729-d009911db0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672697145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.672697145
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2099893197
Short name T604
Test name
Test status
Simulation time 784912065 ps
CPU time 2.83 seconds
Started Jul 30 04:48:57 PM PDT 24
Finished Jul 30 04:49:00 PM PDT 24
Peak memory 200148 kb
Host smart-416dbfeb-ff75-47fb-ae75-d9f7a6314427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099893197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2099893197
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1036858290
Short name T51
Test name
Test status
Simulation time 160606554 ps
CPU time 1.12 seconds
Started Jul 30 04:48:36 PM PDT 24
Finished Jul 30 04:48:38 PM PDT 24
Peak memory 199972 kb
Host smart-f06aaaae-1400-4248-8076-8253c848ef30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036858290 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1036858290
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2441351918
Short name T91
Test name
Test status
Simulation time 69910504 ps
CPU time 0.8 seconds
Started Jul 30 04:48:39 PM PDT 24
Finished Jul 30 04:48:40 PM PDT 24
Peak memory 199800 kb
Host smart-7a1333bc-e202-4260-9481-6a5efbfd3ec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441351918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2441351918
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2560004087
Short name T591
Test name
Test status
Simulation time 233081197 ps
CPU time 1.61 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:48:56 PM PDT 24
Peak memory 200064 kb
Host smart-afff02ab-6c81-4fef-827c-5f5313865fbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560004087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2560004087
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4227052731
Short name T573
Test name
Test status
Simulation time 305151357 ps
CPU time 2.45 seconds
Started Jul 30 04:48:47 PM PDT 24
Finished Jul 30 04:48:50 PM PDT 24
Peak memory 208240 kb
Host smart-ae51b11d-8a3f-45cd-8785-b338acf44d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227052731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4227052731
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1486289518
Short name T567
Test name
Test status
Simulation time 595905915 ps
CPU time 2.03 seconds
Started Jul 30 04:48:41 PM PDT 24
Finished Jul 30 04:48:44 PM PDT 24
Peak memory 200080 kb
Host smart-6504767d-e2a4-48cf-9eb7-d7a660e4a892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486289518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1486289518
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.153127614
Short name T580
Test name
Test status
Simulation time 133326801 ps
CPU time 1.09 seconds
Started Jul 30 04:48:32 PM PDT 24
Finished Jul 30 04:48:33 PM PDT 24
Peak memory 200560 kb
Host smart-06223f2a-d7e2-4646-b383-63ba60b907b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153127614 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.153127614
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2107833600
Short name T586
Test name
Test status
Simulation time 64813993 ps
CPU time 0.76 seconds
Started Jul 30 04:48:44 PM PDT 24
Finished Jul 30 04:48:45 PM PDT 24
Peak memory 199872 kb
Host smart-52928c19-a47c-4c80-b88b-c9aa1eb236fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107833600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2107833600
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1392120023
Short name T87
Test name
Test status
Simulation time 71480762 ps
CPU time 0.94 seconds
Started Jul 30 04:48:43 PM PDT 24
Finished Jul 30 04:48:44 PM PDT 24
Peak memory 199988 kb
Host smart-c5b56b7a-08ac-4f4f-9606-3a2280bee106
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392120023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1392120023
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1749592893
Short name T111
Test name
Test status
Simulation time 479609161 ps
CPU time 1.92 seconds
Started Jul 30 04:48:52 PM PDT 24
Finished Jul 30 04:48:54 PM PDT 24
Peak memory 200112 kb
Host smart-74d1fcb8-d920-4fe5-b14e-2d1c8a2282db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749592893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1749592893
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1846996443
Short name T571
Test name
Test status
Simulation time 100361771 ps
CPU time 0.99 seconds
Started Jul 30 04:48:35 PM PDT 24
Finished Jul 30 04:48:37 PM PDT 24
Peak memory 200044 kb
Host smart-11a9fdae-2dd5-4814-8738-8e14db3810b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846996443 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1846996443
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2352362924
Short name T596
Test name
Test status
Simulation time 63612087 ps
CPU time 0.73 seconds
Started Jul 30 04:48:42 PM PDT 24
Finished Jul 30 04:48:42 PM PDT 24
Peak memory 199908 kb
Host smart-41304f9b-733f-473d-9337-5606df4d87f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352362924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2352362924
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1906093085
Short name T592
Test name
Test status
Simulation time 245489287 ps
CPU time 1.58 seconds
Started Jul 30 04:48:51 PM PDT 24
Finished Jul 30 04:48:52 PM PDT 24
Peak memory 200088 kb
Host smart-41ac9769-4554-4a71-8abf-2734bee8707a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906093085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1906093085
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4236350746
Short name T574
Test name
Test status
Simulation time 312541630 ps
CPU time 2.59 seconds
Started Jul 30 04:48:41 PM PDT 24
Finished Jul 30 04:48:43 PM PDT 24
Peak memory 211400 kb
Host smart-730f327a-9cb5-47ea-b7b9-e8e7943d8b28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236350746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4236350746
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1163397162
Short name T95
Test name
Test status
Simulation time 875907654 ps
CPU time 3.28 seconds
Started Jul 30 04:48:35 PM PDT 24
Finished Jul 30 04:48:38 PM PDT 24
Peak memory 200112 kb
Host smart-7066be3b-9fbf-480e-9651-4f8d7c064969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163397162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1163397162
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3090245060
Short name T61
Test name
Test status
Simulation time 207900263 ps
CPU time 1.3 seconds
Started Jul 30 04:48:49 PM PDT 24
Finished Jul 30 04:48:51 PM PDT 24
Peak memory 208248 kb
Host smart-658fdea6-9e5b-40e0-9a85-755dc28ecf54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090245060 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3090245060
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2442305086
Short name T611
Test name
Test status
Simulation time 94441851 ps
CPU time 0.87 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:48:54 PM PDT 24
Peak memory 199924 kb
Host smart-a6df5d4f-5ef1-4cf3-8b6d-679d49e36b19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442305086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2442305086
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2914318381
Short name T581
Test name
Test status
Simulation time 162081992 ps
CPU time 1.22 seconds
Started Jul 30 04:48:41 PM PDT 24
Finished Jul 30 04:48:43 PM PDT 24
Peak memory 200008 kb
Host smart-8f77fd17-c8d5-47d3-8485-474e0b7c3e03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914318381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2914318381
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.203162801
Short name T544
Test name
Test status
Simulation time 298076803 ps
CPU time 2.33 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:48:55 PM PDT 24
Peak memory 208180 kb
Host smart-4deae338-326a-4c73-80a4-dcf0ef98ec5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203162801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.203162801
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1224298010
Short name T110
Test name
Test status
Simulation time 470037150 ps
CPU time 1.89 seconds
Started Jul 30 04:48:51 PM PDT 24
Finished Jul 30 04:48:53 PM PDT 24
Peak memory 200128 kb
Host smart-c64e0c7f-10d9-446f-8eef-4e28d2e9f470
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224298010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1224298010
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2788082437
Short name T553
Test name
Test status
Simulation time 182957534 ps
CPU time 1.27 seconds
Started Jul 30 04:48:36 PM PDT 24
Finished Jul 30 04:48:38 PM PDT 24
Peak memory 208216 kb
Host smart-40423835-89a5-4ed6-b29d-23090426d55d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788082437 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2788082437
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2298454212
Short name T607
Test name
Test status
Simulation time 76624430 ps
CPU time 0.84 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:48:55 PM PDT 24
Peak memory 199908 kb
Host smart-562b1800-7b6b-41d1-96f1-dc406166a5dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298454212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2298454212
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.14085900
Short name T587
Test name
Test status
Simulation time 79319703 ps
CPU time 0.97 seconds
Started Jul 30 04:48:41 PM PDT 24
Finished Jul 30 04:48:42 PM PDT 24
Peak memory 199960 kb
Host smart-418b85d2-89a3-4d69-93c9-f8b17a2caf5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14085900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sam
e_csr_outstanding.14085900
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2355095505
Short name T619
Test name
Test status
Simulation time 276283267 ps
CPU time 2.25 seconds
Started Jul 30 04:48:44 PM PDT 24
Finished Jul 30 04:48:46 PM PDT 24
Peak memory 199976 kb
Host smart-74663fe9-08c3-444b-b4a9-6e5b7602d777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355095505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2355095505
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1330251674
Short name T558
Test name
Test status
Simulation time 201441121 ps
CPU time 1.59 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:27 PM PDT 24
Peak memory 199932 kb
Host smart-2d2a5bdc-f285-4883-b585-fba42215a2e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330251674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
330251674
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.48374740
Short name T599
Test name
Test status
Simulation time 491906460 ps
CPU time 6.5 seconds
Started Jul 30 04:48:39 PM PDT 24
Finished Jul 30 04:48:45 PM PDT 24
Peak memory 199880 kb
Host smart-36bbe863-29b8-4267-aefe-0dbf1228c1b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48374740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.48374740
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3519822343
Short name T546
Test name
Test status
Simulation time 107951614 ps
CPU time 0.88 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 199920 kb
Host smart-6d5f8c17-6e53-43cd-bc96-e698b379fa9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519822343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
519822343
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3564991112
Short name T620
Test name
Test status
Simulation time 200278840 ps
CPU time 1.85 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:31 PM PDT 24
Peak memory 208228 kb
Host smart-219f914b-1c99-4b11-a662-28fab046480a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564991112 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3564991112
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1851596876
Short name T606
Test name
Test status
Simulation time 89282908 ps
CPU time 0.98 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:26 PM PDT 24
Peak memory 199776 kb
Host smart-6285b862-1fa5-4560-ad0c-31f42e6462f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851596876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1851596876
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3144007796
Short name T597
Test name
Test status
Simulation time 130999737 ps
CPU time 1.3 seconds
Started Jul 30 04:48:32 PM PDT 24
Finished Jul 30 04:48:34 PM PDT 24
Peak memory 200032 kb
Host smart-fb946090-9e16-4323-8cda-b7aa51cb551e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144007796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3144007796
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1975423444
Short name T563
Test name
Test status
Simulation time 96572019 ps
CPU time 1.38 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:00 PM PDT 24
Peak memory 200020 kb
Host smart-f8424ed9-00b7-4562-a40d-d926b629bc60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975423444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1975423444
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3044851754
Short name T613
Test name
Test status
Simulation time 794286100 ps
CPU time 3.18 seconds
Started Jul 30 04:48:34 PM PDT 24
Finished Jul 30 04:48:37 PM PDT 24
Peak memory 200004 kb
Host smart-d584ea4f-fbfb-42a1-bbc0-b52a156fac3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044851754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3044851754
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3651213003
Short name T585
Test name
Test status
Simulation time 228946270 ps
CPU time 1.67 seconds
Started Jul 30 04:48:18 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 199852 kb
Host smart-d7bf4fdf-791c-438d-8c0d-9f5f6e5e9e3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651213003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
651213003
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4176064665
Short name T603
Test name
Test status
Simulation time 1553591751 ps
CPU time 7.86 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:37 PM PDT 24
Peak memory 199976 kb
Host smart-33f281c7-c88c-45e0-939b-c9d323b65b79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176064665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.4
176064665
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2240771808
Short name T598
Test name
Test status
Simulation time 148535103 ps
CPU time 1.01 seconds
Started Jul 30 04:48:17 PM PDT 24
Finished Jul 30 04:48:18 PM PDT 24
Peak memory 199912 kb
Host smart-1e9dfd81-920f-4e62-862b-e5068b6d0d30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240771808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
240771808
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1154634651
Short name T551
Test name
Test status
Simulation time 201156392 ps
CPU time 1.27 seconds
Started Jul 30 04:48:35 PM PDT 24
Finished Jul 30 04:48:36 PM PDT 24
Peak memory 208260 kb
Host smart-44ee4245-186e-4536-ba84-405af42eb5bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154634651 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1154634651
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.606535889
Short name T541
Test name
Test status
Simulation time 76241003 ps
CPU time 0.77 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:21 PM PDT 24
Peak memory 199876 kb
Host smart-5e8b888b-3187-4ad1-b653-2e437a46de37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606535889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.606535889
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2381514922
Short name T617
Test name
Test status
Simulation time 86700314 ps
CPU time 0.96 seconds
Started Jul 30 04:48:25 PM PDT 24
Finished Jul 30 04:48:26 PM PDT 24
Peak memory 199828 kb
Host smart-bfb63764-0f2e-4c75-9adb-aff1a9a4e9d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381514922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2381514922
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4192079685
Short name T595
Test name
Test status
Simulation time 98289570 ps
CPU time 1.4 seconds
Started Jul 30 04:48:18 PM PDT 24
Finished Jul 30 04:48:19 PM PDT 24
Peak memory 210556 kb
Host smart-5050c6b2-037e-42c4-9203-55687fe33afb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192079685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.4192079685
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.932834190
Short name T55
Test name
Test status
Simulation time 878130934 ps
CPU time 2.88 seconds
Started Jul 30 04:48:30 PM PDT 24
Finished Jul 30 04:48:33 PM PDT 24
Peak memory 200104 kb
Host smart-a72da5f7-9d8f-445f-9cfb-9415c3fc5fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932834190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
932834190
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2652009716
Short name T543
Test name
Test status
Simulation time 99448929 ps
CPU time 1.28 seconds
Started Jul 30 04:48:22 PM PDT 24
Finished Jul 30 04:48:24 PM PDT 24
Peak memory 199904 kb
Host smart-6fb66f6b-4769-4003-9d59-a1bfd2d13a4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652009716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
652009716
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.636697168
Short name T556
Test name
Test status
Simulation time 1537131934 ps
CPU time 8.13 seconds
Started Jul 30 04:48:40 PM PDT 24
Finished Jul 30 04:48:48 PM PDT 24
Peak memory 200068 kb
Host smart-2a1e2810-c741-4f4e-9a1a-9051daf31504
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636697168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.636697168
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1195176757
Short name T560
Test name
Test status
Simulation time 117324610 ps
CPU time 0.87 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:23 PM PDT 24
Peak memory 199944 kb
Host smart-dc43559b-d695-4f2f-a357-0b1c20a8187d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195176757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
195176757
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.63085046
Short name T614
Test name
Test status
Simulation time 145325650 ps
CPU time 1.19 seconds
Started Jul 30 04:48:32 PM PDT 24
Finished Jul 30 04:48:33 PM PDT 24
Peak memory 208156 kb
Host smart-fa874c00-eec5-496f-b238-ca38e36a7cbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63085046 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.63085046
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.217638728
Short name T49
Test name
Test status
Simulation time 70249100 ps
CPU time 0.78 seconds
Started Jul 30 04:48:30 PM PDT 24
Finished Jul 30 04:48:31 PM PDT 24
Peak memory 199756 kb
Host smart-1240b049-7f53-4ded-8452-e5457c773be7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217638728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.217638728
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1201790098
Short name T584
Test name
Test status
Simulation time 109030882 ps
CPU time 1.31 seconds
Started Jul 30 04:48:34 PM PDT 24
Finished Jul 30 04:48:35 PM PDT 24
Peak memory 200052 kb
Host smart-f704c583-bf17-4875-9024-f6b027928dba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201790098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1201790098
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2766878352
Short name T557
Test name
Test status
Simulation time 461708827 ps
CPU time 3.09 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:25 PM PDT 24
Peak memory 216368 kb
Host smart-fc13fd81-8502-4783-879d-185a027e42b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766878352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2766878352
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2588756360
Short name T94
Test name
Test status
Simulation time 818876648 ps
CPU time 2.67 seconds
Started Jul 30 04:48:35 PM PDT 24
Finished Jul 30 04:48:38 PM PDT 24
Peak memory 200020 kb
Host smart-db824ed7-a27b-42e7-aa3b-7eeedba63b22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588756360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2588756360
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1349774424
Short name T549
Test name
Test status
Simulation time 124907340 ps
CPU time 1.03 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:26 PM PDT 24
Peak memory 200052 kb
Host smart-3cc2ed5b-9d03-4a15-aad0-5ce1a516fcdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349774424 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1349774424
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.317904306
Short name T77
Test name
Test status
Simulation time 82082949 ps
CPU time 0.82 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:21 PM PDT 24
Peak memory 199852 kb
Host smart-08de6a79-7277-4544-9fa8-b5baf560ccf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317904306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.317904306
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1424144778
Short name T50
Test name
Test status
Simulation time 244826240 ps
CPU time 1.52 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 200012 kb
Host smart-8f0279d4-952b-4040-94b5-786d5f149326
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424144778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1424144778
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1256166165
Short name T552
Test name
Test status
Simulation time 252195315 ps
CPU time 2.1 seconds
Started Jul 30 04:48:42 PM PDT 24
Finished Jul 30 04:48:44 PM PDT 24
Peak memory 208204 kb
Host smart-d6b71991-8f34-44ee-8bb9-93c430fc27fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256166165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1256166165
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.342111332
Short name T594
Test name
Test status
Simulation time 424239026 ps
CPU time 1.9 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:24 PM PDT 24
Peak memory 200080 kb
Host smart-3d4cea8f-e950-42b4-b879-b2e6588c601b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342111332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
342111332
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1644285269
Short name T608
Test name
Test status
Simulation time 67939774 ps
CPU time 0.78 seconds
Started Jul 30 04:48:31 PM PDT 24
Finished Jul 30 04:48:32 PM PDT 24
Peak memory 199800 kb
Host smart-8dc192ec-2f1e-4ec6-a685-77822d2e905e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644285269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1644285269
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.687733019
Short name T610
Test name
Test status
Simulation time 104829066 ps
CPU time 1.2 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:29 PM PDT 24
Peak memory 200060 kb
Host smart-7e3c2cbd-e47a-4df3-9aad-3a9b3278e607
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687733019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.687733019
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4099583379
Short name T69
Test name
Test status
Simulation time 263866904 ps
CPU time 2.26 seconds
Started Jul 30 04:48:46 PM PDT 24
Finished Jul 30 04:48:48 PM PDT 24
Peak memory 211660 kb
Host smart-372804b7-6d45-4038-b28f-3ef11e077c83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099583379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4099583379
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.101292550
Short name T56
Test name
Test status
Simulation time 763625455 ps
CPU time 2.92 seconds
Started Jul 30 04:48:24 PM PDT 24
Finished Jul 30 04:48:27 PM PDT 24
Peak memory 200008 kb
Host smart-700a4bc5-f7e8-401a-aef5-40d78264332b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101292550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
101292550
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.140992422
Short name T577
Test name
Test status
Simulation time 128983584 ps
CPU time 1.42 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:22 PM PDT 24
Peak memory 208340 kb
Host smart-17ca5658-85e5-40dc-8706-7da5d8296e45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140992422 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.140992422
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2795689933
Short name T90
Test name
Test status
Simulation time 75492778 ps
CPU time 0.84 seconds
Started Jul 30 04:48:37 PM PDT 24
Finished Jul 30 04:48:38 PM PDT 24
Peak memory 199896 kb
Host smart-c33e9dc8-c59a-416a-8ab8-db932cced2e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795689933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2795689933
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.452586766
Short name T602
Test name
Test status
Simulation time 138905591 ps
CPU time 1.49 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:22 PM PDT 24
Peak memory 200000 kb
Host smart-32c5c656-0a98-4d94-82f3-d9d834bcebc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452586766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.452586766
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3735336983
Short name T559
Test name
Test status
Simulation time 155119434 ps
CPU time 1.43 seconds
Started Jul 30 04:48:37 PM PDT 24
Finished Jul 30 04:48:38 PM PDT 24
Peak memory 199876 kb
Host smart-a6653798-ba93-4af2-885b-c1b53bb861bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735336983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3735336983
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3005603392
Short name T589
Test name
Test status
Simulation time 794039556 ps
CPU time 2.89 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:31 PM PDT 24
Peak memory 200008 kb
Host smart-867a7c96-602e-4136-8b89-4d6c33d25322
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005603392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3005603392
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1070328022
Short name T545
Test name
Test status
Simulation time 120694078 ps
CPU time 1.04 seconds
Started Jul 30 04:48:34 PM PDT 24
Finished Jul 30 04:48:35 PM PDT 24
Peak memory 199900 kb
Host smart-6c853ce6-ae60-4948-b190-e4263aaa7693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070328022 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1070328022
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1923429628
Short name T566
Test name
Test status
Simulation time 83606591 ps
CPU time 0.85 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:29 PM PDT 24
Peak memory 199912 kb
Host smart-32bf7ca5-05b3-4169-8fde-f2721beed207
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923429628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1923429628
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.301507354
Short name T88
Test name
Test status
Simulation time 79207135 ps
CPU time 0.99 seconds
Started Jul 30 04:48:32 PM PDT 24
Finished Jul 30 04:48:33 PM PDT 24
Peak memory 199960 kb
Host smart-82905a67-42aa-42c6-87a9-35a8f60df81a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301507354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.301507354
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1708820334
Short name T601
Test name
Test status
Simulation time 304457586 ps
CPU time 2.3 seconds
Started Jul 30 04:48:35 PM PDT 24
Finished Jul 30 04:48:38 PM PDT 24
Peak memory 199952 kb
Host smart-53f9037d-fcbc-46f8-bb31-b66ea7aebb47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708820334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1708820334
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1118309153
Short name T609
Test name
Test status
Simulation time 1013989403 ps
CPU time 3.31 seconds
Started Jul 30 04:48:45 PM PDT 24
Finished Jul 30 04:48:49 PM PDT 24
Peak memory 200084 kb
Host smart-e5079371-402f-4e7f-969f-70147a02adb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118309153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1118309153
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3552522435
Short name T590
Test name
Test status
Simulation time 113866134 ps
CPU time 1.27 seconds
Started Jul 30 04:48:46 PM PDT 24
Finished Jul 30 04:48:48 PM PDT 24
Peak memory 208224 kb
Host smart-d5fbc823-071a-40af-93bc-93a938136619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552522435 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3552522435
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2494519028
Short name T568
Test name
Test status
Simulation time 62414076 ps
CPU time 0.75 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 199832 kb
Host smart-407b1036-4acd-48a7-9392-c053228b5215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494519028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2494519028
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2565177037
Short name T605
Test name
Test status
Simulation time 127113225 ps
CPU time 1.23 seconds
Started Jul 30 04:48:44 PM PDT 24
Finished Jul 30 04:48:45 PM PDT 24
Peak memory 199880 kb
Host smart-df66787a-5ac0-44cc-9403-5e9142556bdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565177037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2565177037
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3755838659
Short name T616
Test name
Test status
Simulation time 542127130 ps
CPU time 3.51 seconds
Started Jul 30 04:48:25 PM PDT 24
Finished Jul 30 04:48:29 PM PDT 24
Peak memory 199972 kb
Host smart-d982f042-3cb7-404d-9249-5c5488d44b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755838659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3755838659
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2896408170
Short name T67
Test name
Test status
Simulation time 769086503 ps
CPU time 3.01 seconds
Started Jul 30 04:48:40 PM PDT 24
Finished Jul 30 04:48:43 PM PDT 24
Peak memory 200008 kb
Host smart-af9cba92-2f75-43a1-bb02-24a8d06966df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896408170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2896408170
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.4174757025
Short name T449
Test name
Test status
Simulation time 74413848 ps
CPU time 0.8 seconds
Started Jul 30 04:55:34 PM PDT 24
Finished Jul 30 04:55:34 PM PDT 24
Peak memory 200012 kb
Host smart-b9ca3377-39cd-44f8-9d26-388110fb9735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174757025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4174757025
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2722049950
Short name T27
Test name
Test status
Simulation time 1884967067 ps
CPU time 8.32 seconds
Started Jul 30 04:55:34 PM PDT 24
Finished Jul 30 04:55:42 PM PDT 24
Peak memory 217320 kb
Host smart-5aa487fb-09b3-43d1-923f-164c340bac6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722049950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2722049950
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3246182975
Short name T530
Test name
Test status
Simulation time 244985777 ps
CPU time 1.16 seconds
Started Jul 30 04:55:35 PM PDT 24
Finished Jul 30 04:55:37 PM PDT 24
Peak memory 217324 kb
Host smart-c97e484a-9afe-479b-a320-1efbd9751aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246182975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3246182975
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.343300006
Short name T270
Test name
Test status
Simulation time 1669791282 ps
CPU time 6.63 seconds
Started Jul 30 04:55:31 PM PDT 24
Finished Jul 30 04:55:38 PM PDT 24
Peak memory 200432 kb
Host smart-82dc1f7f-1dde-4bcc-9fb2-f67942ea0c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343300006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.343300006
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1638219284
Short name T337
Test name
Test status
Simulation time 156611554 ps
CPU time 1.19 seconds
Started Jul 30 04:55:33 PM PDT 24
Finished Jul 30 04:55:34 PM PDT 24
Peak memory 200168 kb
Host smart-dc0ec86f-50d8-4d9c-b00f-8110813b95df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638219284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1638219284
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3516587186
Short name T463
Test name
Test status
Simulation time 206608248 ps
CPU time 1.32 seconds
Started Jul 30 04:55:27 PM PDT 24
Finished Jul 30 04:55:28 PM PDT 24
Peak memory 200300 kb
Host smart-7add0841-00d6-4e64-8219-b2bd6f158903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516587186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3516587186
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3086693339
Short name T273
Test name
Test status
Simulation time 8560390823 ps
CPU time 34.69 seconds
Started Jul 30 04:55:35 PM PDT 24
Finished Jul 30 04:56:10 PM PDT 24
Peak memory 200488 kb
Host smart-10a0d79c-0ad7-4fa4-9a88-3810472e42a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086693339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3086693339
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3375058835
Short name T314
Test name
Test status
Simulation time 278157584 ps
CPU time 1.96 seconds
Started Jul 30 04:55:34 PM PDT 24
Finished Jul 30 04:55:36 PM PDT 24
Peak memory 200164 kb
Host smart-87bf14b3-f202-4769-91d6-9e34ec5ca3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375058835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3375058835
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3397870353
Short name T188
Test name
Test status
Simulation time 198441684 ps
CPU time 1.3 seconds
Started Jul 30 04:55:31 PM PDT 24
Finished Jul 30 04:55:32 PM PDT 24
Peak memory 200116 kb
Host smart-777d8e76-efbf-4f4d-a134-d883d01b24b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397870353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3397870353
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1012328390
Short name T230
Test name
Test status
Simulation time 69203128 ps
CPU time 0.8 seconds
Started Jul 30 04:55:52 PM PDT 24
Finished Jul 30 04:55:53 PM PDT 24
Peak memory 200068 kb
Host smart-c06cdf3f-d1ad-4906-851f-becfed5e8792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012328390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1012328390
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2214949573
Short name T30
Test name
Test status
Simulation time 1220758605 ps
CPU time 5.4 seconds
Started Jul 30 04:55:43 PM PDT 24
Finished Jul 30 04:55:49 PM PDT 24
Peak memory 216768 kb
Host smart-84bec910-371d-488c-ad1c-2ee42fbe13f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214949573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2214949573
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4269676187
Short name T331
Test name
Test status
Simulation time 244576639 ps
CPU time 1.15 seconds
Started Jul 30 04:55:47 PM PDT 24
Finished Jul 30 04:55:48 PM PDT 24
Peak memory 217376 kb
Host smart-7439c279-7d63-40a8-aeb1-a7245fbd3f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269676187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4269676187
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3057975725
Short name T220
Test name
Test status
Simulation time 149737966 ps
CPU time 0.82 seconds
Started Jul 30 04:55:42 PM PDT 24
Finished Jul 30 04:55:43 PM PDT 24
Peak memory 199980 kb
Host smart-a4ad3d84-d8dd-4a59-b94b-13acda505f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057975725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3057975725
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3575539548
Short name T142
Test name
Test status
Simulation time 1100327430 ps
CPU time 5.4 seconds
Started Jul 30 04:55:43 PM PDT 24
Finished Jul 30 04:55:48 PM PDT 24
Peak memory 200320 kb
Host smart-16ae0f05-9962-476e-a125-3a02f70a5ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575539548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3575539548
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3163606780
Short name T58
Test name
Test status
Simulation time 16523951229 ps
CPU time 32.09 seconds
Started Jul 30 04:55:52 PM PDT 24
Finished Jul 30 04:56:25 PM PDT 24
Peak memory 217104 kb
Host smart-48f19279-7fa3-4969-9a52-8499d0766cea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163606780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3163606780
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3186942609
Short name T179
Test name
Test status
Simulation time 190076427 ps
CPU time 1.21 seconds
Started Jul 30 04:55:43 PM PDT 24
Finished Jul 30 04:55:44 PM PDT 24
Peak memory 200184 kb
Host smart-d964c9b7-b7e2-4a7d-a202-2b3f8910ff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186942609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3186942609
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3042073021
Short name T471
Test name
Test status
Simulation time 118497717 ps
CPU time 1.22 seconds
Started Jul 30 04:55:38 PM PDT 24
Finished Jul 30 04:55:40 PM PDT 24
Peak memory 200300 kb
Host smart-2c3b5b25-9770-400b-9ae5-88105ccd7c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042073021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3042073021
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3770314417
Short name T83
Test name
Test status
Simulation time 7664056641 ps
CPU time 29.15 seconds
Started Jul 30 04:55:51 PM PDT 24
Finished Jul 30 04:56:20 PM PDT 24
Peak memory 208664 kb
Host smart-a438de6f-35d9-448b-a025-8f3204b0ebdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770314417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3770314417
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1205036940
Short name T241
Test name
Test status
Simulation time 364742261 ps
CPU time 2.09 seconds
Started Jul 30 04:55:42 PM PDT 24
Finished Jul 30 04:55:44 PM PDT 24
Peak memory 200200 kb
Host smart-68ae4d92-e240-42ea-be54-18185d2823be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205036940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1205036940
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.4038535457
Short name T336
Test name
Test status
Simulation time 260541133 ps
CPU time 1.45 seconds
Started Jul 30 04:55:43 PM PDT 24
Finished Jul 30 04:55:45 PM PDT 24
Peak memory 200148 kb
Host smart-28ed393c-0088-4af9-a401-bed1781930fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038535457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.4038535457
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2397728262
Short name T200
Test name
Test status
Simulation time 74911237 ps
CPU time 0.83 seconds
Started Jul 30 04:56:47 PM PDT 24
Finished Jul 30 04:56:48 PM PDT 24
Peak memory 200020 kb
Host smart-824bbfcb-f83e-4fb6-b499-9322dac9ea2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397728262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2397728262
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2330478663
Short name T504
Test name
Test status
Simulation time 1218997173 ps
CPU time 5.36 seconds
Started Jul 30 04:56:43 PM PDT 24
Finished Jul 30 04:56:49 PM PDT 24
Peak memory 217504 kb
Host smart-3544a79a-32e8-42e3-8404-e5fb5bd4b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330478663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2330478663
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2994092196
Short name T511
Test name
Test status
Simulation time 245319240 ps
CPU time 1.08 seconds
Started Jul 30 04:56:46 PM PDT 24
Finished Jul 30 04:56:47 PM PDT 24
Peak memory 217312 kb
Host smart-dbaf738e-cd0d-4eae-b6dc-95f6f444d0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994092196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2994092196
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2136642651
Short name T523
Test name
Test status
Simulation time 82566769 ps
CPU time 0.76 seconds
Started Jul 30 04:56:42 PM PDT 24
Finished Jul 30 04:56:43 PM PDT 24
Peak memory 200096 kb
Host smart-84969b0d-5387-4d54-9612-9ccd1a98c1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136642651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2136642651
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3263215289
Short name T234
Test name
Test status
Simulation time 785581600 ps
CPU time 3.96 seconds
Started Jul 30 04:56:45 PM PDT 24
Finished Jul 30 04:56:49 PM PDT 24
Peak memory 200460 kb
Host smart-b8635da8-40cc-444e-8662-02a1a4bd9b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263215289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3263215289
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2663936189
Short name T233
Test name
Test status
Simulation time 98870316 ps
CPU time 1.04 seconds
Started Jul 30 04:56:42 PM PDT 24
Finished Jul 30 04:56:43 PM PDT 24
Peak memory 200324 kb
Host smart-0b0fe607-c52d-4967-99c7-f76931d0def8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663936189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2663936189
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1689732120
Short name T377
Test name
Test status
Simulation time 248745695 ps
CPU time 1.53 seconds
Started Jul 30 04:56:47 PM PDT 24
Finished Jul 30 04:56:49 PM PDT 24
Peak memory 200408 kb
Host smart-2de3a811-6dcb-42ad-8641-502bcad31b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689732120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1689732120
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3609288369
Short name T292
Test name
Test status
Simulation time 14789936467 ps
CPU time 49.24 seconds
Started Jul 30 04:56:48 PM PDT 24
Finished Jul 30 04:57:37 PM PDT 24
Peak memory 200488 kb
Host smart-24392ec1-63f3-43e5-baba-df3737dfd733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609288369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3609288369
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3503081511
Short name T517
Test name
Test status
Simulation time 128940336 ps
CPU time 1.44 seconds
Started Jul 30 04:56:47 PM PDT 24
Finished Jul 30 04:56:48 PM PDT 24
Peak memory 200220 kb
Host smart-64104d96-be36-4a6d-9eb3-4cd5bb00feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503081511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3503081511
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1920753258
Short name T386
Test name
Test status
Simulation time 244279884 ps
CPU time 1.33 seconds
Started Jul 30 04:56:45 PM PDT 24
Finished Jul 30 04:56:47 PM PDT 24
Peak memory 200272 kb
Host smart-996cf4cb-9a9e-4147-b856-6ae0b84ab989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920753258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1920753258
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1455400643
Short name T120
Test name
Test status
Simulation time 72229996 ps
CPU time 0.72 seconds
Started Jul 30 04:56:50 PM PDT 24
Finished Jul 30 04:56:51 PM PDT 24
Peak memory 200032 kb
Host smart-141ca4f5-6b0c-4dce-ad1e-a2e96cb83f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455400643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1455400643
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1039755974
Short name T24
Test name
Test status
Simulation time 1902081025 ps
CPU time 7.77 seconds
Started Jul 30 04:56:51 PM PDT 24
Finished Jul 30 04:56:59 PM PDT 24
Peak memory 221648 kb
Host smart-c094209e-3179-4849-bc40-a69dfafcbaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039755974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1039755974
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.4203264289
Short name T204
Test name
Test status
Simulation time 243899109 ps
CPU time 1.16 seconds
Started Jul 30 04:56:50 PM PDT 24
Finished Jul 30 04:56:51 PM PDT 24
Peak memory 217452 kb
Host smart-f0fce378-a075-408f-9361-e62de299fcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203264289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.4203264289
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3208645701
Short name T193
Test name
Test status
Simulation time 173992002 ps
CPU time 0.87 seconds
Started Jul 30 04:56:49 PM PDT 24
Finished Jul 30 04:56:50 PM PDT 24
Peak memory 200024 kb
Host smart-08d84105-228e-4a85-aaec-59a3a18f5223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208645701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3208645701
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.722799728
Short name T173
Test name
Test status
Simulation time 907244555 ps
CPU time 4.54 seconds
Started Jul 30 04:56:47 PM PDT 24
Finished Jul 30 04:56:52 PM PDT 24
Peak memory 200320 kb
Host smart-8be22829-92fb-4ac5-b584-ec94e47dcfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722799728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.722799728
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3458182895
Short name T262
Test name
Test status
Simulation time 180742323 ps
CPU time 1.19 seconds
Started Jul 30 04:56:51 PM PDT 24
Finished Jul 30 04:56:52 PM PDT 24
Peak memory 200124 kb
Host smart-c78d8a9e-de48-433a-9531-07d9e3ed9ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458182895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3458182895
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.364912379
Short name T443
Test name
Test status
Simulation time 249398752 ps
CPU time 1.56 seconds
Started Jul 30 04:56:46 PM PDT 24
Finished Jul 30 04:56:48 PM PDT 24
Peak memory 200376 kb
Host smart-022066d6-44e8-4149-9bd3-a36726938067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364912379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.364912379
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.780736165
Short name T304
Test name
Test status
Simulation time 2831251854 ps
CPU time 11.7 seconds
Started Jul 30 04:56:54 PM PDT 24
Finished Jul 30 04:57:05 PM PDT 24
Peak memory 200528 kb
Host smart-89969e87-b76e-47d4-a6e3-52ebdd5beb41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780736165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.780736165
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3080991584
Short name T287
Test name
Test status
Simulation time 328455638 ps
CPU time 2.09 seconds
Started Jul 30 04:56:53 PM PDT 24
Finished Jul 30 04:56:55 PM PDT 24
Peak memory 200216 kb
Host smart-f4f6f07c-7fe8-4a7a-9a49-3992fe478a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080991584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3080991584
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2688572684
Short name T341
Test name
Test status
Simulation time 128111710 ps
CPU time 0.94 seconds
Started Jul 30 04:56:47 PM PDT 24
Finished Jul 30 04:56:48 PM PDT 24
Peak memory 200216 kb
Host smart-62c80a1d-d6fe-463e-8acd-896f80f08aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688572684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2688572684
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2105199842
Short name T332
Test name
Test status
Simulation time 74580938 ps
CPU time 0.77 seconds
Started Jul 30 04:56:57 PM PDT 24
Finished Jul 30 04:56:58 PM PDT 24
Peak memory 199996 kb
Host smart-f83dbf64-e630-49a4-a7cb-94c918d1bd45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105199842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2105199842
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3817372345
Short name T353
Test name
Test status
Simulation time 1226661074 ps
CPU time 5.68 seconds
Started Jul 30 04:56:58 PM PDT 24
Finished Jul 30 04:57:04 PM PDT 24
Peak memory 229788 kb
Host smart-ae1443eb-1396-4462-9b7a-96e36dcc0e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817372345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3817372345
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1693322184
Short name T344
Test name
Test status
Simulation time 243196887 ps
CPU time 1.16 seconds
Started Jul 30 04:56:58 PM PDT 24
Finished Jul 30 04:56:59 PM PDT 24
Peak memory 217352 kb
Host smart-37be0a75-7eac-4f61-beed-9d6775326763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693322184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1693322184
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3470464755
Short name T497
Test name
Test status
Simulation time 115822400 ps
CPU time 0.79 seconds
Started Jul 30 04:56:53 PM PDT 24
Finished Jul 30 04:56:54 PM PDT 24
Peak memory 199976 kb
Host smart-cb0612d3-ba70-420e-8827-ac90d60fe908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470464755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3470464755
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2285448337
Short name T380
Test name
Test status
Simulation time 1093113193 ps
CPU time 5.26 seconds
Started Jul 30 04:56:55 PM PDT 24
Finished Jul 30 04:57:00 PM PDT 24
Peak memory 200476 kb
Host smart-04e54e1b-2083-4977-88a0-b898e15a9180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285448337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2285448337
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2162253481
Short name T128
Test name
Test status
Simulation time 142069586 ps
CPU time 1.13 seconds
Started Jul 30 04:56:57 PM PDT 24
Finished Jul 30 04:56:58 PM PDT 24
Peak memory 200288 kb
Host smart-95cbbc49-fad6-40a1-92d8-adb379f00948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162253481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2162253481
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1743462518
Short name T108
Test name
Test status
Simulation time 259195742 ps
CPU time 1.55 seconds
Started Jul 30 04:56:54 PM PDT 24
Finished Jul 30 04:56:56 PM PDT 24
Peak memory 200364 kb
Host smart-692bb40f-870b-4267-9ea6-d5f7a65d2baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743462518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1743462518
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3871185001
Short name T339
Test name
Test status
Simulation time 6273586926 ps
CPU time 29.61 seconds
Started Jul 30 04:56:56 PM PDT 24
Finished Jul 30 04:57:25 PM PDT 24
Peak memory 200460 kb
Host smart-10f449b8-6312-4b44-a8eb-4c37f43a61e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871185001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3871185001
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2257971823
Short name T160
Test name
Test status
Simulation time 326742241 ps
CPU time 2.12 seconds
Started Jul 30 04:56:57 PM PDT 24
Finished Jul 30 04:56:59 PM PDT 24
Peak memory 200216 kb
Host smart-630ed57a-d088-4dfa-93a1-93b44e8ded84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257971823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2257971823
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.948538120
Short name T440
Test name
Test status
Simulation time 70538963 ps
CPU time 0.78 seconds
Started Jul 30 04:57:00 PM PDT 24
Finished Jul 30 04:57:01 PM PDT 24
Peak memory 199936 kb
Host smart-c91e0343-d3a2-4217-b5a3-7a4c69272b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948538120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.948538120
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.584576758
Short name T282
Test name
Test status
Simulation time 1234794548 ps
CPU time 5.81 seconds
Started Jul 30 04:57:01 PM PDT 24
Finished Jul 30 04:57:07 PM PDT 24
Peak memory 221572 kb
Host smart-0526048e-9fbe-4250-994a-4f2fb37555c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584576758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.584576758
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.619614331
Short name T402
Test name
Test status
Simulation time 244996176 ps
CPU time 1.1 seconds
Started Jul 30 04:57:00 PM PDT 24
Finished Jul 30 04:57:02 PM PDT 24
Peak memory 217340 kb
Host smart-d61e2f2b-6268-4e30-8800-4e50c455537b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619614331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.619614331
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2248652605
Short name T535
Test name
Test status
Simulation time 166197470 ps
CPU time 0.87 seconds
Started Jul 30 04:56:55 PM PDT 24
Finished Jul 30 04:56:56 PM PDT 24
Peak memory 200012 kb
Host smart-2df863cd-bced-4445-93d3-da1dc48df029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248652605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2248652605
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1990929153
Short name T444
Test name
Test status
Simulation time 1520968553 ps
CPU time 6.2 seconds
Started Jul 30 04:56:59 PM PDT 24
Finished Jul 30 04:57:06 PM PDT 24
Peak memory 200468 kb
Host smart-332b35f4-e342-4de4-8ad6-b28723d57f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990929153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1990929153
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3187166303
Short name T437
Test name
Test status
Simulation time 104654260 ps
CPU time 1.12 seconds
Started Jul 30 04:57:01 PM PDT 24
Finished Jul 30 04:57:03 PM PDT 24
Peak memory 200128 kb
Host smart-0133b67b-25f6-4a69-ab38-d93dcc1b6636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187166303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3187166303
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2498084074
Short name T237
Test name
Test status
Simulation time 191570032 ps
CPU time 1.41 seconds
Started Jul 30 04:56:56 PM PDT 24
Finished Jul 30 04:56:57 PM PDT 24
Peak memory 200280 kb
Host smart-d81c4e1e-18e2-4210-b797-5ceed12196ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498084074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2498084074
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.4161149934
Short name T501
Test name
Test status
Simulation time 129702493 ps
CPU time 1.58 seconds
Started Jul 30 04:56:59 PM PDT 24
Finished Jul 30 04:57:01 PM PDT 24
Peak memory 208360 kb
Host smart-57e46aa2-decc-43ac-baa9-b03333cdb872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161149934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.4161149934
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3346984931
Short name T183
Test name
Test status
Simulation time 223107682 ps
CPU time 1.45 seconds
Started Jul 30 04:57:00 PM PDT 24
Finished Jul 30 04:57:01 PM PDT 24
Peak memory 200216 kb
Host smart-7938866f-45a6-4d09-a721-59d004b37411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346984931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3346984931
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.940150110
Short name T295
Test name
Test status
Simulation time 65029288 ps
CPU time 0.76 seconds
Started Jul 30 04:57:06 PM PDT 24
Finished Jul 30 04:57:07 PM PDT 24
Peak memory 199992 kb
Host smart-8652e71f-aa4f-4104-b0ff-7e43d085031b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940150110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.940150110
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3722301199
Short name T363
Test name
Test status
Simulation time 2350039661 ps
CPU time 8.42 seconds
Started Jul 30 04:57:06 PM PDT 24
Finished Jul 30 04:57:15 PM PDT 24
Peak memory 229856 kb
Host smart-77e300a9-3c73-4e65-a00a-ce7b2f972eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722301199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3722301199
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3740942434
Short name T263
Test name
Test status
Simulation time 243534149 ps
CPU time 1.15 seconds
Started Jul 30 04:57:06 PM PDT 24
Finished Jul 30 04:57:07 PM PDT 24
Peak memory 217408 kb
Host smart-be4abdc5-232f-4be4-b733-8b49f5a8e92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740942434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3740942434
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.902587491
Short name T172
Test name
Test status
Simulation time 120189809 ps
CPU time 0.81 seconds
Started Jul 30 04:57:00 PM PDT 24
Finished Jul 30 04:57:01 PM PDT 24
Peak memory 200056 kb
Host smart-f92963fb-a869-4e6f-a4b4-97e296279d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902587491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.902587491
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3776674942
Short name T268
Test name
Test status
Simulation time 1347384893 ps
CPU time 5.49 seconds
Started Jul 30 04:57:00 PM PDT 24
Finished Jul 30 04:57:06 PM PDT 24
Peak memory 200416 kb
Host smart-c093e96d-fe82-4613-9ab7-23ad2de61159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776674942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3776674942
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2957242077
Short name T267
Test name
Test status
Simulation time 111452943 ps
CPU time 1.06 seconds
Started Jul 30 04:57:07 PM PDT 24
Finished Jul 30 04:57:08 PM PDT 24
Peak memory 200272 kb
Host smart-2309c440-aea4-411b-8808-1531b6f5cb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957242077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2957242077
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.807060374
Short name T294
Test name
Test status
Simulation time 121165466 ps
CPU time 1.27 seconds
Started Jul 30 04:57:02 PM PDT 24
Finished Jul 30 04:57:03 PM PDT 24
Peak memory 200400 kb
Host smart-6408eaca-81bf-4597-990c-9c554eeae39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807060374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.807060374
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1503592277
Short name T213
Test name
Test status
Simulation time 9883856949 ps
CPU time 33.76 seconds
Started Jul 30 04:57:08 PM PDT 24
Finished Jul 30 04:57:41 PM PDT 24
Peak memory 208732 kb
Host smart-43d9ceca-da49-4fef-ad4e-48a9e46b29d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503592277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1503592277
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2118365428
Short name T414
Test name
Test status
Simulation time 160322922 ps
CPU time 1.3 seconds
Started Jul 30 04:57:06 PM PDT 24
Finished Jul 30 04:57:08 PM PDT 24
Peak memory 200360 kb
Host smart-83562fd8-9f9a-4e9f-9ed8-1029229d9634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118365428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2118365428
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3835408450
Short name T144
Test name
Test status
Simulation time 60323239 ps
CPU time 0.86 seconds
Started Jul 30 04:57:10 PM PDT 24
Finished Jul 30 04:57:11 PM PDT 24
Peak memory 200080 kb
Host smart-49981c4e-6d74-4294-8f66-68432e9a4ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835408450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3835408450
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.752756405
Short name T178
Test name
Test status
Simulation time 2357390660 ps
CPU time 8.29 seconds
Started Jul 30 04:57:09 PM PDT 24
Finished Jul 30 04:57:17 PM PDT 24
Peak memory 221628 kb
Host smart-1de00b91-0b9e-41f1-a672-0977c09eb964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752756405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.752756405
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2912609186
Short name T65
Test name
Test status
Simulation time 243452197 ps
CPU time 1.21 seconds
Started Jul 30 04:57:10 PM PDT 24
Finished Jul 30 04:57:11 PM PDT 24
Peak memory 217492 kb
Host smart-5bfdfa0c-a921-4431-8805-d5159420b8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912609186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2912609186
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3620003973
Short name T16
Test name
Test status
Simulation time 130198974 ps
CPU time 0.83 seconds
Started Jul 30 04:57:06 PM PDT 24
Finished Jul 30 04:57:07 PM PDT 24
Peak memory 200104 kb
Host smart-49f11f39-8074-4146-8957-2f5bd655c3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620003973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3620003973
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2737922516
Short name T281
Test name
Test status
Simulation time 818420645 ps
CPU time 3.98 seconds
Started Jul 30 04:57:06 PM PDT 24
Finished Jul 30 04:57:10 PM PDT 24
Peak memory 200496 kb
Host smart-371e2465-e074-4a0d-b5c9-744f6a6ba32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737922516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2737922516
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.707710513
Short name T225
Test name
Test status
Simulation time 104491792 ps
CPU time 1.02 seconds
Started Jul 30 04:57:10 PM PDT 24
Finished Jul 30 04:57:11 PM PDT 24
Peak memory 200228 kb
Host smart-67464e29-04aa-46e0-a657-3a8aabc0d210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707710513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.707710513
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.469639286
Short name T403
Test name
Test status
Simulation time 194648721 ps
CPU time 1.52 seconds
Started Jul 30 04:57:07 PM PDT 24
Finished Jul 30 04:57:08 PM PDT 24
Peak memory 200408 kb
Host smart-75f61bc5-723f-4af2-8c14-675515aa3637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469639286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.469639286
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3754631171
Short name T155
Test name
Test status
Simulation time 5674822587 ps
CPU time 20.43 seconds
Started Jul 30 04:57:08 PM PDT 24
Finished Jul 30 04:57:28 PM PDT 24
Peak memory 200476 kb
Host smart-5424cb4b-3ecf-4e04-bbdc-4ff1cd3ae529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754631171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3754631171
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1107508456
Short name T412
Test name
Test status
Simulation time 562071914 ps
CPU time 3.11 seconds
Started Jul 30 04:57:10 PM PDT 24
Finished Jul 30 04:57:13 PM PDT 24
Peak memory 200060 kb
Host smart-59c59673-eac5-4f3e-a575-cbb46b1b4afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107508456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1107508456
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2214669754
Short name T482
Test name
Test status
Simulation time 92318481 ps
CPU time 0.94 seconds
Started Jul 30 04:57:05 PM PDT 24
Finished Jul 30 04:57:06 PM PDT 24
Peak memory 200296 kb
Host smart-2ef8caba-2ab2-4cd5-916a-627f189410fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214669754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2214669754
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3338550327
Short name T533
Test name
Test status
Simulation time 87575198 ps
CPU time 0.85 seconds
Started Jul 30 04:57:14 PM PDT 24
Finished Jul 30 04:57:15 PM PDT 24
Peak memory 200108 kb
Host smart-354ee252-e510-4095-8efd-1898c4a4153b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338550327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3338550327
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1162122217
Short name T343
Test name
Test status
Simulation time 1226200724 ps
CPU time 5.75 seconds
Started Jul 30 04:57:12 PM PDT 24
Finished Jul 30 04:57:18 PM PDT 24
Peak memory 217648 kb
Host smart-a70c53c1-0cad-4e76-8576-e28ad074f53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162122217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1162122217
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4173047763
Short name T484
Test name
Test status
Simulation time 243314596 ps
CPU time 1.06 seconds
Started Jul 30 04:57:14 PM PDT 24
Finished Jul 30 04:57:16 PM PDT 24
Peak memory 217284 kb
Host smart-1bd7ca29-352b-4915-9738-45e8d4b987a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173047763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.4173047763
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.4144134551
Short name T174
Test name
Test status
Simulation time 192074752 ps
CPU time 0.89 seconds
Started Jul 30 04:57:10 PM PDT 24
Finished Jul 30 04:57:11 PM PDT 24
Peak memory 200072 kb
Host smart-5e4f5f9e-2563-401d-b293-724269b0543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144134551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.4144134551
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1008632011
Short name T457
Test name
Test status
Simulation time 834034221 ps
CPU time 4 seconds
Started Jul 30 04:57:15 PM PDT 24
Finished Jul 30 04:57:19 PM PDT 24
Peak memory 200364 kb
Host smart-b8de4f0a-9159-4dcf-badd-c872457a8615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008632011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1008632011
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.99283868
Short name T283
Test name
Test status
Simulation time 107662387 ps
CPU time 1.05 seconds
Started Jul 30 04:57:13 PM PDT 24
Finished Jul 30 04:57:15 PM PDT 24
Peak memory 200252 kb
Host smart-22dcce59-265c-4994-bb39-9661115e0aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99283868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.99283868
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2487577577
Short name T249
Test name
Test status
Simulation time 122941384 ps
CPU time 1.27 seconds
Started Jul 30 04:57:09 PM PDT 24
Finished Jul 30 04:57:10 PM PDT 24
Peak memory 200328 kb
Host smart-4c3648b1-523a-4daf-ad32-73874ad5c4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487577577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2487577577
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.52505805
Short name T143
Test name
Test status
Simulation time 4593154904 ps
CPU time 20.94 seconds
Started Jul 30 04:57:13 PM PDT 24
Finished Jul 30 04:57:34 PM PDT 24
Peak memory 208656 kb
Host smart-de24c9dc-a6b4-43e0-88e7-734093d9d9f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52505805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.52505805
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.949830285
Short name T156
Test name
Test status
Simulation time 146991305 ps
CPU time 1.93 seconds
Started Jul 30 04:57:12 PM PDT 24
Finished Jul 30 04:57:14 PM PDT 24
Peak memory 200216 kb
Host smart-216401b7-5585-4dea-a05c-d235d743b1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949830285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.949830285
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2808491736
Short name T187
Test name
Test status
Simulation time 121814390 ps
CPU time 0.94 seconds
Started Jul 30 04:57:14 PM PDT 24
Finished Jul 30 04:57:15 PM PDT 24
Peak memory 200268 kb
Host smart-f8151ba1-d458-4368-af1c-655d6afe1fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808491736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2808491736
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.694587826
Short name T195
Test name
Test status
Simulation time 65785126 ps
CPU time 0.76 seconds
Started Jul 30 04:57:19 PM PDT 24
Finished Jul 30 04:57:20 PM PDT 24
Peak memory 200080 kb
Host smart-6ddd6e94-64e2-4f94-9b47-404ff108dd09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694587826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.694587826
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.4182971520
Short name T36
Test name
Test status
Simulation time 1231078976 ps
CPU time 5.59 seconds
Started Jul 30 04:57:15 PM PDT 24
Finished Jul 30 04:57:21 PM PDT 24
Peak memory 216732 kb
Host smart-e4030ac7-76f9-45cc-b54a-f86480d54de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182971520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.4182971520
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3047273787
Short name T335
Test name
Test status
Simulation time 244698086 ps
CPU time 1.02 seconds
Started Jul 30 04:57:19 PM PDT 24
Finished Jul 30 04:57:20 PM PDT 24
Peak memory 217480 kb
Host smart-4f96439a-57db-4305-9914-90eea0d7ad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047273787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3047273787
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1664128227
Short name T165
Test name
Test status
Simulation time 186074766 ps
CPU time 0.93 seconds
Started Jul 30 04:57:13 PM PDT 24
Finished Jul 30 04:57:14 PM PDT 24
Peak memory 199988 kb
Host smart-d55640fc-d55b-43cd-b6c6-9042c50f78cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664128227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1664128227
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1114374045
Short name T327
Test name
Test status
Simulation time 1655458845 ps
CPU time 6.63 seconds
Started Jul 30 04:57:19 PM PDT 24
Finished Jul 30 04:57:25 PM PDT 24
Peak memory 200476 kb
Host smart-883896fa-4422-4195-bafb-72deeaba8868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114374045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1114374045
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.664835285
Short name T374
Test name
Test status
Simulation time 97365530 ps
CPU time 1.07 seconds
Started Jul 30 04:57:19 PM PDT 24
Finished Jul 30 04:57:20 PM PDT 24
Peak memory 200208 kb
Host smart-3dc6999c-60e1-41bc-a0ad-f60af694cd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664835285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.664835285
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1761998475
Short name T338
Test name
Test status
Simulation time 251233954 ps
CPU time 1.49 seconds
Started Jul 30 04:57:13 PM PDT 24
Finished Jul 30 04:57:14 PM PDT 24
Peak memory 200264 kb
Host smart-b8db99db-ea51-498b-b66b-a65f4a60adca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761998475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1761998475
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3832865459
Short name T355
Test name
Test status
Simulation time 3036509479 ps
CPU time 12.92 seconds
Started Jul 30 04:57:17 PM PDT 24
Finished Jul 30 04:57:30 PM PDT 24
Peak memory 200456 kb
Host smart-ecabc7c9-e0ca-4c50-b30f-ca8035dd58a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832865459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3832865459
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4014050767
Short name T534
Test name
Test status
Simulation time 342702695 ps
CPU time 2.2 seconds
Started Jul 30 04:57:17 PM PDT 24
Finished Jul 30 04:57:19 PM PDT 24
Peak memory 200256 kb
Host smart-d011f826-b04f-4463-939e-1b1ee7b98574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014050767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4014050767
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.897384003
Short name T381
Test name
Test status
Simulation time 262155064 ps
CPU time 1.46 seconds
Started Jul 30 04:57:18 PM PDT 24
Finished Jul 30 04:57:19 PM PDT 24
Peak memory 200228 kb
Host smart-cbdfc032-fac0-44c3-9fdd-06eb72857fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897384003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.897384003
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1161182085
Short name T404
Test name
Test status
Simulation time 74739820 ps
CPU time 0.77 seconds
Started Jul 30 04:57:23 PM PDT 24
Finished Jul 30 04:57:24 PM PDT 24
Peak memory 200072 kb
Host smart-4ddea3c3-67ba-49fb-b551-33a54ac987c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161182085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1161182085
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2279636346
Short name T41
Test name
Test status
Simulation time 1217247819 ps
CPU time 6.07 seconds
Started Jul 30 04:57:25 PM PDT 24
Finished Jul 30 04:57:31 PM PDT 24
Peak memory 217376 kb
Host smart-97dc51cf-5adc-4a2b-a433-a28101185656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279636346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2279636346
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2405893708
Short name T321
Test name
Test status
Simulation time 243985804 ps
CPU time 1.07 seconds
Started Jul 30 04:57:26 PM PDT 24
Finished Jul 30 04:57:27 PM PDT 24
Peak memory 217432 kb
Host smart-62e8f218-c019-45ad-bf6d-89b75ecf52d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405893708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2405893708
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2316726202
Short name T208
Test name
Test status
Simulation time 101702396 ps
CPU time 0.82 seconds
Started Jul 30 04:57:20 PM PDT 24
Finished Jul 30 04:57:21 PM PDT 24
Peak memory 199976 kb
Host smart-4d2c58d2-79cf-4154-9a53-b719bf64ba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316726202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2316726202
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3024010455
Short name T293
Test name
Test status
Simulation time 1051572323 ps
CPU time 5.15 seconds
Started Jul 30 04:57:16 PM PDT 24
Finished Jul 30 04:57:21 PM PDT 24
Peak memory 200364 kb
Host smart-2125f3c3-9baa-4834-8204-898db6787b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024010455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3024010455
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.291572069
Short name T525
Test name
Test status
Simulation time 235069571 ps
CPU time 1.52 seconds
Started Jul 30 04:57:17 PM PDT 24
Finished Jul 30 04:57:19 PM PDT 24
Peak memory 200296 kb
Host smart-73f133a9-bb31-4ff7-addd-254f5599454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291572069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.291572069
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.4115559616
Short name T222
Test name
Test status
Simulation time 2593583503 ps
CPU time 12.56 seconds
Started Jul 30 04:57:23 PM PDT 24
Finished Jul 30 04:57:35 PM PDT 24
Peak memory 208704 kb
Host smart-fae8eb83-e390-46b6-99a2-d5600f442809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115559616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.4115559616
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3435304359
Short name T246
Test name
Test status
Simulation time 560664550 ps
CPU time 2.85 seconds
Started Jul 30 04:57:25 PM PDT 24
Finished Jul 30 04:57:28 PM PDT 24
Peak memory 200204 kb
Host smart-e92c216e-5339-47cf-a2e3-347720ce2355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435304359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3435304359
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2281583168
Short name T206
Test name
Test status
Simulation time 215025804 ps
CPU time 1.38 seconds
Started Jul 30 04:57:23 PM PDT 24
Finished Jul 30 04:57:25 PM PDT 24
Peak memory 200256 kb
Host smart-ccaf445d-00db-454e-9cdd-5fe6f5d54823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281583168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2281583168
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3195913470
Short name T243
Test name
Test status
Simulation time 78198341 ps
CPU time 0.8 seconds
Started Jul 30 04:57:28 PM PDT 24
Finished Jul 30 04:57:28 PM PDT 24
Peak memory 199996 kb
Host smart-326b835a-d4d8-405a-8b43-bb1dff40472a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195913470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3195913470
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.421516701
Short name T218
Test name
Test status
Simulation time 2174719126 ps
CPU time 8.21 seconds
Started Jul 30 04:57:25 PM PDT 24
Finished Jul 30 04:57:34 PM PDT 24
Peak memory 216924 kb
Host smart-aa14015a-9d29-45b3-b8cc-23a8c7ea791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421516701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.421516701
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.901800780
Short name T330
Test name
Test status
Simulation time 244398880 ps
CPU time 1.18 seconds
Started Jul 30 04:57:27 PM PDT 24
Finished Jul 30 04:57:28 PM PDT 24
Peak memory 217328 kb
Host smart-22eef2c4-ad29-4a0e-82f8-91b974bed2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901800780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.901800780
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3792131531
Short name T227
Test name
Test status
Simulation time 151487264 ps
CPU time 0.84 seconds
Started Jul 30 04:57:28 PM PDT 24
Finished Jul 30 04:57:29 PM PDT 24
Peak memory 200040 kb
Host smart-22879b3e-58b8-42a4-bda7-d190162209b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792131531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3792131531
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2331811424
Short name T410
Test name
Test status
Simulation time 1686837524 ps
CPU time 6.9 seconds
Started Jul 30 04:57:29 PM PDT 24
Finished Jul 30 04:57:36 PM PDT 24
Peak memory 200432 kb
Host smart-4f16b3f8-b37e-417c-87e2-e8ea833b6406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331811424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2331811424
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.154898562
Short name T103
Test name
Test status
Simulation time 94581975 ps
CPU time 1.01 seconds
Started Jul 30 04:57:27 PM PDT 24
Finished Jul 30 04:57:28 PM PDT 24
Peak memory 200276 kb
Host smart-9260abd9-d9e0-4f5f-baee-9538be73634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154898562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.154898562
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3068898216
Short name T147
Test name
Test status
Simulation time 108372261 ps
CPU time 1.15 seconds
Started Jul 30 04:57:23 PM PDT 24
Finished Jul 30 04:57:24 PM PDT 24
Peak memory 200376 kb
Host smart-161db7e8-18af-4dae-9ca2-f4f5a18efb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068898216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3068898216
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3588155406
Short name T223
Test name
Test status
Simulation time 4057728691 ps
CPU time 15.59 seconds
Started Jul 30 04:57:26 PM PDT 24
Finished Jul 30 04:57:42 PM PDT 24
Peak memory 208716 kb
Host smart-3ec70235-6c65-4e71-998c-5d0b7b90aec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588155406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3588155406
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3246883216
Short name T394
Test name
Test status
Simulation time 373624227 ps
CPU time 1.98 seconds
Started Jul 30 04:57:24 PM PDT 24
Finished Jul 30 04:57:26 PM PDT 24
Peak memory 200168 kb
Host smart-462e549e-d47d-4afa-8eee-2a9fc272497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246883216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3246883216
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1412312624
Short name T324
Test name
Test status
Simulation time 147314479 ps
CPU time 1.24 seconds
Started Jul 30 04:57:22 PM PDT 24
Finished Jul 30 04:57:23 PM PDT 24
Peak memory 200520 kb
Host smart-d9541f24-df0f-4d91-8537-1e8a186ee409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412312624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1412312624
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1808350092
Short name T42
Test name
Test status
Simulation time 1230707716 ps
CPU time 5.36 seconds
Started Jul 30 04:55:59 PM PDT 24
Finished Jul 30 04:56:04 PM PDT 24
Peak memory 217400 kb
Host smart-eef10d2e-c5a1-4133-a9eb-d989ffe109f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808350092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1808350092
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.739675280
Short name T130
Test name
Test status
Simulation time 244833440 ps
CPU time 1.11 seconds
Started Jul 30 04:56:01 PM PDT 24
Finished Jul 30 04:56:02 PM PDT 24
Peak memory 217348 kb
Host smart-f73bd4b5-810a-4937-993f-22c57720c99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739675280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.739675280
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2710916668
Short name T15
Test name
Test status
Simulation time 108355993 ps
CPU time 0.81 seconds
Started Jul 30 04:55:51 PM PDT 24
Finished Jul 30 04:55:52 PM PDT 24
Peak memory 199956 kb
Host smart-99b32f43-454a-4af0-83bf-17da236db6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710916668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2710916668
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.995718843
Short name T81
Test name
Test status
Simulation time 1496497429 ps
CPU time 5.51 seconds
Started Jul 30 04:55:56 PM PDT 24
Finished Jul 30 04:56:01 PM PDT 24
Peak memory 200376 kb
Host smart-365d8aba-680f-44af-ae35-9e47a5b66a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995718843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.995718843
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2414107999
Short name T57
Test name
Test status
Simulation time 16551087428 ps
CPU time 27.84 seconds
Started Jul 30 04:56:03 PM PDT 24
Finished Jul 30 04:56:31 PM PDT 24
Peak memory 217108 kb
Host smart-cfbe0214-0fb3-441f-9861-5bb0b1e9804f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414107999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2414107999
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3305724706
Short name T247
Test name
Test status
Simulation time 98366720 ps
CPU time 1.04 seconds
Started Jul 30 04:55:58 PM PDT 24
Finished Jul 30 04:55:59 PM PDT 24
Peak memory 200148 kb
Host smart-b1776e37-0515-4c88-92e5-c021297f7d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305724706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3305724706
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1997652780
Short name T493
Test name
Test status
Simulation time 256030446 ps
CPU time 1.62 seconds
Started Jul 30 04:55:52 PM PDT 24
Finished Jul 30 04:55:53 PM PDT 24
Peak memory 200488 kb
Host smart-b1c63054-1b77-4b80-be26-aba86fed788e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997652780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1997652780
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.476966481
Short name T211
Test name
Test status
Simulation time 8809022996 ps
CPU time 30.56 seconds
Started Jul 30 04:56:00 PM PDT 24
Finished Jul 30 04:56:30 PM PDT 24
Peak memory 208604 kb
Host smart-587e8ed8-fdb3-4ec8-9920-07d07dd5cf83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476966481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.476966481
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1009099349
Short name T106
Test name
Test status
Simulation time 356740300 ps
CPU time 2.42 seconds
Started Jul 30 04:55:54 PM PDT 24
Finished Jul 30 04:55:57 PM PDT 24
Peak memory 200120 kb
Host smart-317cf287-14cb-4bb5-8eed-fa5a57f1cec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009099349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1009099349
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1769704333
Short name T446
Test name
Test status
Simulation time 76453361 ps
CPU time 0.79 seconds
Started Jul 30 04:55:56 PM PDT 24
Finished Jul 30 04:55:57 PM PDT 24
Peak memory 200228 kb
Host smart-c09c8e79-a206-425b-9ae4-03ca8359fb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769704333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1769704333
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.950029961
Short name T515
Test name
Test status
Simulation time 59746678 ps
CPU time 0.76 seconds
Started Jul 30 04:57:31 PM PDT 24
Finished Jul 30 04:57:32 PM PDT 24
Peak memory 200064 kb
Host smart-5ba3535d-e4ad-445d-9818-06275f08924e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950029961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.950029961
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.351906518
Short name T445
Test name
Test status
Simulation time 2176048663 ps
CPU time 7.88 seconds
Started Jul 30 04:57:29 PM PDT 24
Finished Jul 30 04:57:37 PM PDT 24
Peak memory 216980 kb
Host smart-e8a9b304-59ab-42f7-86e0-89bac92d478a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351906518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.351906518
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.333179082
Short name T507
Test name
Test status
Simulation time 244571747 ps
CPU time 1.06 seconds
Started Jul 30 04:57:31 PM PDT 24
Finished Jul 30 04:57:32 PM PDT 24
Peak memory 217492 kb
Host smart-a2a3a1f1-d2dc-4627-b170-a261fb5a516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333179082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.333179082
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3290824657
Short name T364
Test name
Test status
Simulation time 149149456 ps
CPU time 0.89 seconds
Started Jul 30 04:57:31 PM PDT 24
Finished Jul 30 04:57:32 PM PDT 24
Peak memory 200040 kb
Host smart-7e79d409-e3ca-4c8a-9c3d-635601400b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290824657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3290824657
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2814787701
Short name T166
Test name
Test status
Simulation time 799164050 ps
CPU time 3.92 seconds
Started Jul 30 04:57:27 PM PDT 24
Finished Jul 30 04:57:31 PM PDT 24
Peak memory 200512 kb
Host smart-17b013e1-ed7a-47a3-afb6-00fd3fbc055c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814787701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2814787701
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4226799067
Short name T524
Test name
Test status
Simulation time 155694236 ps
CPU time 1.18 seconds
Started Jul 30 04:57:31 PM PDT 24
Finished Jul 30 04:57:32 PM PDT 24
Peak memory 200168 kb
Host smart-d8e72bb2-f8c7-42b0-982d-95ac6aa6db93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226799067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4226799067
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2899988707
Short name T450
Test name
Test status
Simulation time 120483053 ps
CPU time 1.25 seconds
Started Jul 30 04:57:31 PM PDT 24
Finished Jul 30 04:57:33 PM PDT 24
Peak memory 200368 kb
Host smart-3f304c6d-be15-4f3d-8aad-cabe82ecf241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899988707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2899988707
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2834571692
Short name T76
Test name
Test status
Simulation time 5782503483 ps
CPU time 21.28 seconds
Started Jul 30 04:57:32 PM PDT 24
Finished Jul 30 04:57:53 PM PDT 24
Peak memory 200580 kb
Host smart-6d46711a-cd03-4590-ba3e-993f7e923615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834571692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2834571692
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2027617441
Short name T199
Test name
Test status
Simulation time 365290151 ps
CPU time 2.32 seconds
Started Jul 30 04:57:29 PM PDT 24
Finished Jul 30 04:57:31 PM PDT 24
Peak memory 200172 kb
Host smart-28a38935-dd4d-4ed8-a072-af2984021d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027617441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2027617441
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1940105418
Short name T458
Test name
Test status
Simulation time 146688736 ps
CPU time 1.23 seconds
Started Jul 30 04:57:27 PM PDT 24
Finished Jul 30 04:57:28 PM PDT 24
Peak memory 200296 kb
Host smart-6a773162-f1d0-42bd-bf64-b59788e25930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940105418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1940105418
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2287595053
Short name T451
Test name
Test status
Simulation time 72448488 ps
CPU time 0.87 seconds
Started Jul 30 04:57:34 PM PDT 24
Finished Jul 30 04:57:35 PM PDT 24
Peak memory 200048 kb
Host smart-35284dc0-e83f-48d4-abfa-c00521196c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287595053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2287595053
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1764051467
Short name T483
Test name
Test status
Simulation time 1221965755 ps
CPU time 6.43 seconds
Started Jul 30 04:57:40 PM PDT 24
Finished Jul 30 04:57:47 PM PDT 24
Peak memory 217656 kb
Host smart-d89b259e-49b0-4d66-b9aa-5f2df8bb90fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764051467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1764051467
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.4210459069
Short name T506
Test name
Test status
Simulation time 244276030 ps
CPU time 1.12 seconds
Started Jul 30 04:57:39 PM PDT 24
Finished Jul 30 04:57:40 PM PDT 24
Peak memory 217360 kb
Host smart-03711603-edbc-4fbd-8333-7541f5239d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210459069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.4210459069
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.547860171
Short name T499
Test name
Test status
Simulation time 229066744 ps
CPU time 0.93 seconds
Started Jul 30 04:57:31 PM PDT 24
Finished Jul 30 04:57:32 PM PDT 24
Peak memory 199928 kb
Host smart-a8bb668d-0575-4b3e-a121-067e1ecf042d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547860171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.547860171
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1116402980
Short name T503
Test name
Test status
Simulation time 1626759822 ps
CPU time 6.76 seconds
Started Jul 30 04:57:31 PM PDT 24
Finished Jul 30 04:57:38 PM PDT 24
Peak memory 200420 kb
Host smart-d42e37fa-dd4d-4b86-afc4-5bd47d2dbd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116402980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1116402980
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2320803592
Short name T348
Test name
Test status
Simulation time 116453998 ps
CPU time 1.06 seconds
Started Jul 30 04:57:34 PM PDT 24
Finished Jul 30 04:57:35 PM PDT 24
Peak memory 200176 kb
Host smart-402891fb-7da1-4726-ac63-1c96be4312eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320803592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2320803592
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.329621756
Short name T468
Test name
Test status
Simulation time 243950691 ps
CPU time 1.45 seconds
Started Jul 30 04:57:29 PM PDT 24
Finished Jul 30 04:57:31 PM PDT 24
Peak memory 200292 kb
Host smart-3569de20-8dae-4684-b818-623242b0c9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329621756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.329621756
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1929005063
Short name T214
Test name
Test status
Simulation time 6748958918 ps
CPU time 22.44 seconds
Started Jul 30 04:57:39 PM PDT 24
Finished Jul 30 04:58:02 PM PDT 24
Peak memory 208396 kb
Host smart-98018852-6c77-409d-95eb-95eccbf70838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929005063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1929005063
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.108351988
Short name T260
Test name
Test status
Simulation time 372532281 ps
CPU time 2.41 seconds
Started Jul 30 04:57:37 PM PDT 24
Finished Jul 30 04:57:40 PM PDT 24
Peak memory 208328 kb
Host smart-317ff357-8865-4aa6-b3a0-75bd66685b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108351988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.108351988
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1689771354
Short name T299
Test name
Test status
Simulation time 115207445 ps
CPU time 1.04 seconds
Started Jul 30 04:57:37 PM PDT 24
Finished Jul 30 04:57:39 PM PDT 24
Peak memory 200176 kb
Host smart-f9e0de49-3b57-4476-bbff-566a75dda4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689771354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1689771354
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2746671693
Short name T169
Test name
Test status
Simulation time 65364470 ps
CPU time 0.78 seconds
Started Jul 30 04:57:39 PM PDT 24
Finished Jul 30 04:57:40 PM PDT 24
Peak memory 199748 kb
Host smart-eca1f06d-7072-4277-83c0-2eb8c732c70a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746671693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2746671693
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1784977819
Short name T352
Test name
Test status
Simulation time 1231198961 ps
CPU time 5.97 seconds
Started Jul 30 04:57:39 PM PDT 24
Finished Jul 30 04:57:45 PM PDT 24
Peak memory 221564 kb
Host smart-c00d195e-5526-4fa3-adc0-ba9c565df834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784977819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1784977819
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3660761822
Short name T269
Test name
Test status
Simulation time 244280350 ps
CPU time 1.06 seconds
Started Jul 30 04:57:37 PM PDT 24
Finished Jul 30 04:57:39 PM PDT 24
Peak memory 217424 kb
Host smart-04a39987-6c4f-431f-9177-0583fd782408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660761822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3660761822
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.889097683
Short name T435
Test name
Test status
Simulation time 128701200 ps
CPU time 0.8 seconds
Started Jul 30 04:57:35 PM PDT 24
Finished Jul 30 04:57:36 PM PDT 24
Peak memory 200096 kb
Host smart-a3f3a333-db56-43fc-8457-22204cc7ec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889097683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.889097683
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3150528293
Short name T257
Test name
Test status
Simulation time 1041543315 ps
CPU time 5.32 seconds
Started Jul 30 04:57:37 PM PDT 24
Finished Jul 30 04:57:42 PM PDT 24
Peak memory 200484 kb
Host smart-f03f1555-df08-47a7-817c-2c4a3af052f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150528293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3150528293
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3650845985
Short name T342
Test name
Test status
Simulation time 146495709 ps
CPU time 1.16 seconds
Started Jul 30 04:57:37 PM PDT 24
Finished Jul 30 04:57:39 PM PDT 24
Peak memory 200208 kb
Host smart-ec62d79d-1c66-4aa7-8279-7f2b3efafea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650845985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3650845985
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.694421312
Short name T164
Test name
Test status
Simulation time 241242742 ps
CPU time 1.67 seconds
Started Jul 30 04:57:36 PM PDT 24
Finished Jul 30 04:57:37 PM PDT 24
Peak memory 200236 kb
Host smart-70190de3-031f-4478-9004-77a337ae23f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694421312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.694421312
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2189608052
Short name T480
Test name
Test status
Simulation time 14079735112 ps
CPU time 50.25 seconds
Started Jul 30 04:57:40 PM PDT 24
Finished Jul 30 04:58:31 PM PDT 24
Peak memory 207552 kb
Host smart-4789ecae-8599-41b8-9c53-a57408cb9755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189608052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2189608052
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3091325444
Short name T203
Test name
Test status
Simulation time 156036882 ps
CPU time 1.95 seconds
Started Jul 30 04:57:40 PM PDT 24
Finished Jul 30 04:57:42 PM PDT 24
Peak memory 198988 kb
Host smart-044c5e60-e126-4cd9-a04a-f0b64c5bc4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091325444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3091325444
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2155108555
Short name T307
Test name
Test status
Simulation time 157609373 ps
CPU time 1.22 seconds
Started Jul 30 04:57:34 PM PDT 24
Finished Jul 30 04:57:35 PM PDT 24
Peak memory 200376 kb
Host smart-cb9e1da9-324a-40e3-8ead-7462884589dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155108555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2155108555
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2769389071
Short name T453
Test name
Test status
Simulation time 90858698 ps
CPU time 0.92 seconds
Started Jul 30 04:57:42 PM PDT 24
Finished Jul 30 04:57:44 PM PDT 24
Peak memory 199940 kb
Host smart-a08feed1-1392-4541-9e34-656efbd6acee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769389071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2769389071
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.4018881985
Short name T409
Test name
Test status
Simulation time 1897384172 ps
CPU time 7.84 seconds
Started Jul 30 04:57:38 PM PDT 24
Finished Jul 30 04:57:46 PM PDT 24
Peak memory 217484 kb
Host smart-59e92eae-bd5c-443a-b363-2038c040a3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018881985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.4018881985
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3464458495
Short name T454
Test name
Test status
Simulation time 244450089 ps
CPU time 1.13 seconds
Started Jul 30 04:57:38 PM PDT 24
Finished Jul 30 04:57:39 PM PDT 24
Peak memory 217452 kb
Host smart-2b54b8c9-a63f-422d-b1f8-33aceb69db6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464458495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3464458495
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2003925442
Short name T306
Test name
Test status
Simulation time 226282073 ps
CPU time 0.95 seconds
Started Jul 30 04:57:38 PM PDT 24
Finished Jul 30 04:57:39 PM PDT 24
Peak memory 200104 kb
Host smart-5dc137f3-2515-44ab-817b-24af36a4bb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003925442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2003925442
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1908911163
Short name T393
Test name
Test status
Simulation time 1368992144 ps
CPU time 5.97 seconds
Started Jul 30 04:57:41 PM PDT 24
Finished Jul 30 04:57:47 PM PDT 24
Peak memory 200476 kb
Host smart-b104bf0d-0491-4d30-913c-9a9a0eecb25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908911163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1908911163
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2452458701
Short name T177
Test name
Test status
Simulation time 183280471 ps
CPU time 1.23 seconds
Started Jul 30 04:57:41 PM PDT 24
Finished Jul 30 04:57:42 PM PDT 24
Peak memory 200208 kb
Host smart-9894c26d-2f90-449f-8667-ad4691d8c76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452458701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2452458701
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3339164186
Short name T276
Test name
Test status
Simulation time 108529539 ps
CPU time 1.12 seconds
Started Jul 30 04:57:40 PM PDT 24
Finished Jul 30 04:57:42 PM PDT 24
Peak memory 200404 kb
Host smart-c32c3370-d132-400c-b8b5-1671b00828ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339164186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3339164186
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.338184246
Short name T456
Test name
Test status
Simulation time 113037676 ps
CPU time 1.58 seconds
Started Jul 30 04:57:40 PM PDT 24
Finished Jul 30 04:57:42 PM PDT 24
Peak memory 200220 kb
Host smart-3ccd1b0c-2ec9-416f-a9b3-79b73fcc4bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338184246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.338184246
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1986645810
Short name T460
Test name
Test status
Simulation time 222702500 ps
CPU time 1.37 seconds
Started Jul 30 04:57:38 PM PDT 24
Finished Jul 30 04:57:39 PM PDT 24
Peak memory 200180 kb
Host smart-4dd143c2-4f59-4eab-b9df-bdf6766efefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986645810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1986645810
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3464053136
Short name T215
Test name
Test status
Simulation time 58286916 ps
CPU time 0.74 seconds
Started Jul 30 04:57:41 PM PDT 24
Finished Jul 30 04:57:42 PM PDT 24
Peak memory 200068 kb
Host smart-566e5e0e-9c66-4c4d-b559-588c1fe15ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464053136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3464053136
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4052694828
Short name T366
Test name
Test status
Simulation time 1894551530 ps
CPU time 7.12 seconds
Started Jul 30 04:57:46 PM PDT 24
Finished Jul 30 04:57:53 PM PDT 24
Peak memory 217268 kb
Host smart-c2c206eb-114c-4ae0-88c7-107611e3d158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052694828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4052694828
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.810637803
Short name T429
Test name
Test status
Simulation time 245153835 ps
CPU time 1.09 seconds
Started Jul 30 04:57:44 PM PDT 24
Finished Jul 30 04:57:46 PM PDT 24
Peak memory 217388 kb
Host smart-4274a017-a5e8-436d-a0f5-79837e3ba1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810637803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.810637803
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.455976278
Short name T387
Test name
Test status
Simulation time 169445598 ps
CPU time 0.84 seconds
Started Jul 30 04:57:43 PM PDT 24
Finished Jul 30 04:57:44 PM PDT 24
Peak memory 200108 kb
Host smart-adf4ed4d-8cc6-4026-854a-36d5882719df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455976278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.455976278
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2995469800
Short name T415
Test name
Test status
Simulation time 730664839 ps
CPU time 4.07 seconds
Started Jul 30 04:57:44 PM PDT 24
Finished Jul 30 04:57:48 PM PDT 24
Peak memory 200512 kb
Host smart-5fc2cf50-78fd-4bc5-9da3-da57ceca4b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995469800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2995469800
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3810970089
Short name T475
Test name
Test status
Simulation time 149697382 ps
CPU time 1.16 seconds
Started Jul 30 04:57:44 PM PDT 24
Finished Jul 30 04:57:45 PM PDT 24
Peak memory 200276 kb
Host smart-b7fe310d-f542-4066-a0e0-391b7e3b8a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810970089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3810970089
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.890154283
Short name T432
Test name
Test status
Simulation time 192914482 ps
CPU time 1.42 seconds
Started Jul 30 04:57:43 PM PDT 24
Finished Jul 30 04:57:45 PM PDT 24
Peak memory 200460 kb
Host smart-1d5943ed-23f6-4535-ae3a-88fee93dfc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890154283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.890154283
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.230432973
Short name T289
Test name
Test status
Simulation time 2674145277 ps
CPU time 10.48 seconds
Started Jul 30 04:57:44 PM PDT 24
Finished Jul 30 04:57:54 PM PDT 24
Peak memory 208700 kb
Host smart-9962e8b8-fc06-4037-a6b1-5e55166c4d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230432973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.230432973
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1120378967
Short name T258
Test name
Test status
Simulation time 264249993 ps
CPU time 1.73 seconds
Started Jul 30 04:57:43 PM PDT 24
Finished Jul 30 04:57:45 PM PDT 24
Peak memory 200064 kb
Host smart-2d947545-2cbe-47f7-b5eb-d5f3999eb148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120378967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1120378967
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.316806720
Short name T219
Test name
Test status
Simulation time 268581928 ps
CPU time 1.51 seconds
Started Jul 30 04:57:46 PM PDT 24
Finished Jul 30 04:57:47 PM PDT 24
Peak memory 200220 kb
Host smart-5c0574ae-228d-44a5-8279-5ea6d18e6c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316806720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.316806720
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1165643310
Short name T375
Test name
Test status
Simulation time 87159095 ps
CPU time 0.82 seconds
Started Jul 30 04:57:48 PM PDT 24
Finished Jul 30 04:57:49 PM PDT 24
Peak memory 199992 kb
Host smart-ef10fd02-15f4-4253-aeb3-a641a70902f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165643310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1165643310
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3555688191
Short name T259
Test name
Test status
Simulation time 244495255 ps
CPU time 1.09 seconds
Started Jul 30 04:57:48 PM PDT 24
Finished Jul 30 04:57:49 PM PDT 24
Peak memory 217412 kb
Host smart-a268d8d1-57fb-4eb1-9d76-288ff2601235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555688191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3555688191
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2807674536
Short name T168
Test name
Test status
Simulation time 117289997 ps
CPU time 0.82 seconds
Started Jul 30 04:57:47 PM PDT 24
Finished Jul 30 04:57:48 PM PDT 24
Peak memory 200016 kb
Host smart-4c5db93b-cdb8-4b2d-97f2-88792d84aace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807674536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2807674536
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.4135512111
Short name T78
Test name
Test status
Simulation time 829206336 ps
CPU time 4.47 seconds
Started Jul 30 04:57:48 PM PDT 24
Finished Jul 30 04:57:53 PM PDT 24
Peak memory 200460 kb
Host smart-f0ab1996-f384-48eb-bfcb-cda7e5f074c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135512111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.4135512111
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2334818257
Short name T490
Test name
Test status
Simulation time 145488770 ps
CPU time 1.09 seconds
Started Jul 30 04:57:49 PM PDT 24
Finished Jul 30 04:57:50 PM PDT 24
Peak memory 200272 kb
Host smart-97b935b2-0c19-4680-9238-3d757fc0b870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334818257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2334818257
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4006841919
Short name T43
Test name
Test status
Simulation time 108406416 ps
CPU time 1.24 seconds
Started Jul 30 04:57:44 PM PDT 24
Finished Jul 30 04:57:46 PM PDT 24
Peak memory 200264 kb
Host smart-20e06845-af23-4e74-bafe-1b4757ae2dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006841919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4006841919
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3536246089
Short name T22
Test name
Test status
Simulation time 1150206740 ps
CPU time 5.15 seconds
Started Jul 30 04:57:48 PM PDT 24
Finished Jul 30 04:57:53 PM PDT 24
Peak memory 200516 kb
Host smart-35b4f200-cb1b-45a2-8989-4ffa36199b3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536246089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3536246089
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1565729920
Short name T476
Test name
Test status
Simulation time 132651397 ps
CPU time 1.61 seconds
Started Jul 30 04:57:49 PM PDT 24
Finished Jul 30 04:57:51 PM PDT 24
Peak memory 208472 kb
Host smart-b7dd7d60-4d80-44b2-b17c-1632b9b24bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565729920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1565729920
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2738613980
Short name T170
Test name
Test status
Simulation time 159816590 ps
CPU time 1.15 seconds
Started Jul 30 04:57:48 PM PDT 24
Finished Jul 30 04:57:49 PM PDT 24
Peak memory 200296 kb
Host smart-797bbb2f-53ab-4130-92e9-c178ce411169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738613980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2738613980
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.24815030
Short name T60
Test name
Test status
Simulation time 83290394 ps
CPU time 0.84 seconds
Started Jul 30 04:57:55 PM PDT 24
Finished Jul 30 04:57:56 PM PDT 24
Peak memory 200080 kb
Host smart-7ea6bed1-d8b1-49e0-8627-7b335a5bb19c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24815030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.24815030
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2530664130
Short name T526
Test name
Test status
Simulation time 2318755856 ps
CPU time 8.28 seconds
Started Jul 30 04:57:52 PM PDT 24
Finished Jul 30 04:58:01 PM PDT 24
Peak memory 217716 kb
Host smart-b4198d0a-aba3-479e-b0c3-5f43ce2ad4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530664130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2530664130
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1047585149
Short name T261
Test name
Test status
Simulation time 243999619 ps
CPU time 1.08 seconds
Started Jul 30 04:57:51 PM PDT 24
Finished Jul 30 04:57:53 PM PDT 24
Peak memory 217388 kb
Host smart-c4037bba-6f07-4000-b716-fecc47b8e592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047585149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1047585149
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.932677779
Short name T21
Test name
Test status
Simulation time 158694988 ps
CPU time 0.87 seconds
Started Jul 30 04:57:49 PM PDT 24
Finished Jul 30 04:57:50 PM PDT 24
Peak memory 200076 kb
Host smart-9f9fd80a-0528-4998-87da-1520b27842d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932677779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.932677779
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3333629695
Short name T315
Test name
Test status
Simulation time 806252238 ps
CPU time 4.53 seconds
Started Jul 30 04:57:47 PM PDT 24
Finished Jul 30 04:57:52 PM PDT 24
Peak memory 200508 kb
Host smart-bc901b3f-baa7-4dac-8ff9-300315e6050e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333629695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3333629695
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.160574002
Short name T320
Test name
Test status
Simulation time 143731243 ps
CPU time 1.11 seconds
Started Jul 30 04:57:51 PM PDT 24
Finished Jul 30 04:57:53 PM PDT 24
Peak memory 200200 kb
Host smart-da1b644a-9233-4cd8-bc38-a706cd811d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160574002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.160574002
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2840986250
Short name T417
Test name
Test status
Simulation time 124531161 ps
CPU time 1.28 seconds
Started Jul 30 04:57:47 PM PDT 24
Finished Jul 30 04:57:49 PM PDT 24
Peak memory 200428 kb
Host smart-044ea28f-02fa-4bf4-ac0a-ff8564b901b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840986250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2840986250
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.359807053
Short name T396
Test name
Test status
Simulation time 2870257804 ps
CPU time 10.45 seconds
Started Jul 30 04:57:51 PM PDT 24
Finished Jul 30 04:58:01 PM PDT 24
Peak memory 200404 kb
Host smart-788a709c-17de-4a5f-ab71-cdf1ec8a3acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359807053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.359807053
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.4201508711
Short name T349
Test name
Test status
Simulation time 459579401 ps
CPU time 2.56 seconds
Started Jul 30 04:57:54 PM PDT 24
Finished Jul 30 04:57:57 PM PDT 24
Peak memory 200224 kb
Host smart-350c8346-2614-48ef-b899-c01d4e4b5357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201508711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4201508711
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1865768965
Short name T312
Test name
Test status
Simulation time 292782648 ps
CPU time 1.59 seconds
Started Jul 30 04:57:47 PM PDT 24
Finished Jul 30 04:57:49 PM PDT 24
Peak memory 200384 kb
Host smart-f3a71dc6-b56d-4528-8734-ca5a145b9182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865768965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1865768965
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3283025173
Short name T496
Test name
Test status
Simulation time 68494430 ps
CPU time 0.83 seconds
Started Jul 30 04:57:58 PM PDT 24
Finished Jul 30 04:57:59 PM PDT 24
Peak memory 200076 kb
Host smart-7a7746bb-489b-474e-b742-73ef0b259fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283025173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3283025173
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.628430733
Short name T226
Test name
Test status
Simulation time 244193932 ps
CPU time 1.06 seconds
Started Jul 30 04:57:55 PM PDT 24
Finished Jul 30 04:57:56 PM PDT 24
Peak memory 217372 kb
Host smart-18298d1c-facb-48f7-9577-4a0fdbbc5b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628430733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.628430733
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1994552149
Short name T272
Test name
Test status
Simulation time 154779883 ps
CPU time 0.83 seconds
Started Jul 30 04:57:54 PM PDT 24
Finished Jul 30 04:57:55 PM PDT 24
Peak memory 200072 kb
Host smart-dcb3f0b3-4d08-4db3-8a56-3af8c5ed4f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994552149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1994552149
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1289993739
Short name T256
Test name
Test status
Simulation time 750331542 ps
CPU time 4.06 seconds
Started Jul 30 04:57:55 PM PDT 24
Finished Jul 30 04:57:59 PM PDT 24
Peak memory 200436 kb
Host smart-24c11b3c-23e0-420a-b119-7a651fb50dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289993739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1289993739
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3769260603
Short name T527
Test name
Test status
Simulation time 182903037 ps
CPU time 1.21 seconds
Started Jul 30 04:57:57 PM PDT 24
Finished Jul 30 04:57:58 PM PDT 24
Peak memory 200276 kb
Host smart-723f5349-3a63-4d31-8497-20828b96d4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769260603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3769260603
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.862876043
Short name T175
Test name
Test status
Simulation time 194481463 ps
CPU time 1.43 seconds
Started Jul 30 04:57:53 PM PDT 24
Finished Jul 30 04:57:54 PM PDT 24
Peak memory 200400 kb
Host smart-4110f1fe-46ae-40ff-8519-24b79432633f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862876043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.862876043
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3068134721
Short name T478
Test name
Test status
Simulation time 2320716454 ps
CPU time 10.69 seconds
Started Jul 30 04:57:55 PM PDT 24
Finished Jul 30 04:58:06 PM PDT 24
Peak memory 208740 kb
Host smart-74bccb14-61da-4794-9e02-535b9595b311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068134721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3068134721
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3090757262
Short name T244
Test name
Test status
Simulation time 278523139 ps
CPU time 1.89 seconds
Started Jul 30 04:57:58 PM PDT 24
Finished Jul 30 04:58:00 PM PDT 24
Peak memory 200216 kb
Host smart-f3709868-b2a8-4ba5-a5ff-4eb5bf12732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090757262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3090757262
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2474417472
Short name T528
Test name
Test status
Simulation time 254698296 ps
CPU time 1.59 seconds
Started Jul 30 04:57:55 PM PDT 24
Finished Jul 30 04:57:57 PM PDT 24
Peak memory 200268 kb
Host smart-590a3571-cc8d-4659-af3e-ed6b7ffe161f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474417472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2474417472
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2084029714
Short name T228
Test name
Test status
Simulation time 76439115 ps
CPU time 0.78 seconds
Started Jul 30 04:58:02 PM PDT 24
Finished Jul 30 04:58:03 PM PDT 24
Peak memory 200076 kb
Host smart-63d66ee2-f7ce-4772-899d-c955ed49df8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084029714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2084029714
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2554906626
Short name T39
Test name
Test status
Simulation time 1221378426 ps
CPU time 6.07 seconds
Started Jul 30 04:58:00 PM PDT 24
Finished Jul 30 04:58:06 PM PDT 24
Peak memory 221484 kb
Host smart-322ef91d-7073-45c5-b0da-80df7b20435a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554906626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2554906626
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.860960233
Short name T537
Test name
Test status
Simulation time 244524182 ps
CPU time 1.16 seconds
Started Jul 30 04:58:02 PM PDT 24
Finished Jul 30 04:58:03 PM PDT 24
Peak memory 217440 kb
Host smart-dadf32f5-d6ec-4165-be9f-218c677cc5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860960233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.860960233
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.235265581
Short name T18
Test name
Test status
Simulation time 148034519 ps
CPU time 0.84 seconds
Started Jul 30 04:57:55 PM PDT 24
Finished Jul 30 04:57:56 PM PDT 24
Peak memory 199968 kb
Host smart-70b0d515-d591-4e0a-acf0-d428ebc29571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235265581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.235265581
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.203424225
Short name T532
Test name
Test status
Simulation time 804578716 ps
CPU time 4.14 seconds
Started Jul 30 04:57:55 PM PDT 24
Finished Jul 30 04:58:00 PM PDT 24
Peak memory 200476 kb
Host smart-fd825c31-4abb-4f09-92a2-8257b0337b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203424225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.203424225
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.206125427
Short name T508
Test name
Test status
Simulation time 107910956 ps
CPU time 1.04 seconds
Started Jul 30 04:57:56 PM PDT 24
Finished Jul 30 04:57:57 PM PDT 24
Peak memory 200216 kb
Host smart-f2a05369-81fe-4ac0-b31d-20f01170d4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206125427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.206125427
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2566809193
Short name T358
Test name
Test status
Simulation time 125448085 ps
CPU time 1.21 seconds
Started Jul 30 04:57:56 PM PDT 24
Finished Jul 30 04:57:57 PM PDT 24
Peak memory 200440 kb
Host smart-7ffd00df-fd54-4939-820b-31e7db17ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566809193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2566809193
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.266055284
Short name T82
Test name
Test status
Simulation time 5390079922 ps
CPU time 25.86 seconds
Started Jul 30 04:58:01 PM PDT 24
Finished Jul 30 04:58:27 PM PDT 24
Peak memory 200472 kb
Host smart-a36ed875-9e0a-4b0e-8828-59bee1a938bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266055284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.266055284
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3293798951
Short name T302
Test name
Test status
Simulation time 432957152 ps
CPU time 2.47 seconds
Started Jul 30 04:57:58 PM PDT 24
Finished Jul 30 04:58:00 PM PDT 24
Peak memory 208404 kb
Host smart-2ceb11c2-7585-4a65-8aba-ad8348c369cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293798951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3293798951
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1623496822
Short name T23
Test name
Test status
Simulation time 102529213 ps
CPU time 1 seconds
Started Jul 30 04:57:59 PM PDT 24
Finished Jul 30 04:58:00 PM PDT 24
Peak memory 200256 kb
Host smart-43739d02-ff62-468e-b30b-fb1b71329f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623496822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1623496822
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3581287744
Short name T442
Test name
Test status
Simulation time 57775805 ps
CPU time 0.74 seconds
Started Jul 30 04:58:06 PM PDT 24
Finished Jul 30 04:58:07 PM PDT 24
Peak memory 200044 kb
Host smart-7bf45303-d9aa-47c9-b5e6-5176d0c9aeed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581287744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3581287744
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.512199528
Short name T399
Test name
Test status
Simulation time 2155498573 ps
CPU time 9.7 seconds
Started Jul 30 04:58:00 PM PDT 24
Finished Jul 30 04:58:10 PM PDT 24
Peak memory 217628 kb
Host smart-d82ef55b-3637-4d6c-a86d-8336ccc56263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512199528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.512199528
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.4047521386
Short name T319
Test name
Test status
Simulation time 244364275 ps
CPU time 1.1 seconds
Started Jul 30 04:58:01 PM PDT 24
Finished Jul 30 04:58:02 PM PDT 24
Peak memory 217388 kb
Host smart-bf42a4bf-356c-45d4-af11-7c2450a2aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047521386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.4047521386
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2229861935
Short name T210
Test name
Test status
Simulation time 181941895 ps
CPU time 0.88 seconds
Started Jul 30 04:58:02 PM PDT 24
Finished Jul 30 04:58:03 PM PDT 24
Peak memory 200104 kb
Host smart-651e9609-7153-4dfb-bd18-dd9951948d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229861935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2229861935
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.570448921
Short name T378
Test name
Test status
Simulation time 1659424790 ps
CPU time 6.84 seconds
Started Jul 30 04:58:02 PM PDT 24
Finished Jul 30 04:58:09 PM PDT 24
Peak memory 200384 kb
Host smart-6b8b7387-4b4e-43d4-9a87-31f60771007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570448921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.570448921
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1700895347
Short name T405
Test name
Test status
Simulation time 163198782 ps
CPU time 1.19 seconds
Started Jul 30 04:58:01 PM PDT 24
Finished Jul 30 04:58:02 PM PDT 24
Peak memory 200296 kb
Host smart-ed378c4f-b602-4f61-bbbf-5457bd66aed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700895347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1700895347
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2073975404
Short name T491
Test name
Test status
Simulation time 199901758 ps
CPU time 1.38 seconds
Started Jul 30 04:58:00 PM PDT 24
Finished Jul 30 04:58:02 PM PDT 24
Peak memory 200420 kb
Host smart-b36ebf5e-dc1b-4af2-ad17-29ffffed69d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073975404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2073975404
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.808020278
Short name T198
Test name
Test status
Simulation time 2453935398 ps
CPU time 9.46 seconds
Started Jul 30 04:58:11 PM PDT 24
Finished Jul 30 04:58:21 PM PDT 24
Peak memory 209164 kb
Host smart-9ed7e4e5-6080-4697-8c74-b8f11c149919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808020278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.808020278
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.4269479905
Short name T466
Test name
Test status
Simulation time 140943940 ps
CPU time 1.92 seconds
Started Jul 30 04:58:01 PM PDT 24
Finished Jul 30 04:58:03 PM PDT 24
Peak memory 200224 kb
Host smart-cbe0ab8c-79d3-4e5d-b167-7e8bc6e8dd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269479905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.4269479905
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2453621943
Short name T121
Test name
Test status
Simulation time 235701578 ps
CPU time 1.45 seconds
Started Jul 30 04:58:01 PM PDT 24
Finished Jul 30 04:58:03 PM PDT 24
Peak memory 200368 kb
Host smart-280175e2-ed4a-476b-9165-c06d160e7e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453621943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2453621943
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.4288648559
Short name T357
Test name
Test status
Simulation time 70319940 ps
CPU time 0.8 seconds
Started Jul 30 04:56:07 PM PDT 24
Finished Jul 30 04:56:08 PM PDT 24
Peak memory 200092 kb
Host smart-a427a06f-5d12-4208-bf5f-ceca35dd29f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288648559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.4288648559
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1246581339
Short name T513
Test name
Test status
Simulation time 1897249091 ps
CPU time 7.74 seconds
Started Jul 30 04:56:08 PM PDT 24
Finished Jul 30 04:56:16 PM PDT 24
Peak memory 229728 kb
Host smart-82171a8f-36aa-4173-acfb-974277373a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246581339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1246581339
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3073472974
Short name T301
Test name
Test status
Simulation time 251750372 ps
CPU time 1.07 seconds
Started Jul 30 04:56:07 PM PDT 24
Finished Jul 30 04:56:09 PM PDT 24
Peak memory 217356 kb
Host smart-65ec6178-c8d6-4d38-b355-98efe22ae709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073472974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3073472974
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3866896039
Short name T12
Test name
Test status
Simulation time 171450841 ps
CPU time 0.85 seconds
Started Jul 30 04:56:05 PM PDT 24
Finished Jul 30 04:56:06 PM PDT 24
Peak memory 199980 kb
Host smart-df8bb12f-126b-46fe-a74f-730e1e7e8a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866896039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3866896039
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2884703122
Short name T328
Test name
Test status
Simulation time 1851832067 ps
CPU time 6.63 seconds
Started Jul 30 04:56:02 PM PDT 24
Finished Jul 30 04:56:09 PM PDT 24
Peak memory 200400 kb
Host smart-01df87fc-9f2b-4c97-bf40-b4fc0d04cdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884703122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2884703122
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2621940519
Short name T62
Test name
Test status
Simulation time 8276222715 ps
CPU time 13.87 seconds
Started Jul 30 04:56:07 PM PDT 24
Finished Jul 30 04:56:21 PM PDT 24
Peak memory 217192 kb
Host smart-dd1a185e-7b78-4485-ad68-5a9cdc9c386c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621940519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2621940519
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1985581661
Short name T102
Test name
Test status
Simulation time 98120840 ps
CPU time 0.99 seconds
Started Jul 30 04:56:07 PM PDT 24
Finished Jul 30 04:56:08 PM PDT 24
Peak memory 200168 kb
Host smart-eeb52c85-78b1-42c9-b76c-d2c7a74c3520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985581661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1985581661
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1360222699
Short name T498
Test name
Test status
Simulation time 186233651 ps
CPU time 1.37 seconds
Started Jul 30 04:56:05 PM PDT 24
Finished Jul 30 04:56:06 PM PDT 24
Peak memory 200364 kb
Host smart-daa87e82-b305-4838-92fd-4c52d0cb5a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360222699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1360222699
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.202212479
Short name T329
Test name
Test status
Simulation time 19427349283 ps
CPU time 77.27 seconds
Started Jul 30 04:56:07 PM PDT 24
Finished Jul 30 04:57:25 PM PDT 24
Peak memory 208656 kb
Host smart-3897116d-43a1-459e-a755-9fb94e6938bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202212479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.202212479
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2378780936
Short name T140
Test name
Test status
Simulation time 300822150 ps
CPU time 2.14 seconds
Started Jul 30 04:56:08 PM PDT 24
Finished Jul 30 04:56:10 PM PDT 24
Peak memory 208328 kb
Host smart-ea0b1be3-7a70-4247-9b5a-79ad9b42f942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378780936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2378780936
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2892920485
Short name T251
Test name
Test status
Simulation time 113109601 ps
CPU time 1.04 seconds
Started Jul 30 04:56:04 PM PDT 24
Finished Jul 30 04:56:05 PM PDT 24
Peak memory 200220 kb
Host smart-b0694345-61ae-499e-952f-2d70108e8b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892920485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2892920485
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2086728465
Short name T38
Test name
Test status
Simulation time 59992739 ps
CPU time 0.79 seconds
Started Jul 30 04:58:06 PM PDT 24
Finished Jul 30 04:58:06 PM PDT 24
Peak memory 200032 kb
Host smart-c8807c4f-3a31-4b5e-b58c-7fef7db365f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086728465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2086728465
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3710782810
Short name T28
Test name
Test status
Simulation time 1898589154 ps
CPU time 7.44 seconds
Started Jul 30 04:58:04 PM PDT 24
Finished Jul 30 04:58:12 PM PDT 24
Peak memory 221536 kb
Host smart-cd39b29d-cc23-4754-8500-4a90c0a80eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710782810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3710782810
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.163532829
Short name T340
Test name
Test status
Simulation time 244578685 ps
CPU time 1.06 seconds
Started Jul 30 04:58:06 PM PDT 24
Finished Jul 30 04:58:07 PM PDT 24
Peak memory 217352 kb
Host smart-2089ca6e-1aae-4f4e-88a2-d1764e1e4026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163532829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.163532829
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2693858479
Short name T313
Test name
Test status
Simulation time 171375256 ps
CPU time 0.83 seconds
Started Jul 30 04:58:06 PM PDT 24
Finished Jul 30 04:58:07 PM PDT 24
Peak memory 200104 kb
Host smart-d43f5f35-6f5b-4273-a782-70671eb6516c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693858479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2693858479
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1831533165
Short name T271
Test name
Test status
Simulation time 657622673 ps
CPU time 3.7 seconds
Started Jul 30 04:58:08 PM PDT 24
Finished Jul 30 04:58:12 PM PDT 24
Peak memory 200476 kb
Host smart-9c4c052a-0ccc-4359-a0f5-7f386ea38b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831533165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1831533165
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1002488697
Short name T229
Test name
Test status
Simulation time 138956350 ps
CPU time 1.09 seconds
Started Jul 30 04:58:05 PM PDT 24
Finished Jul 30 04:58:06 PM PDT 24
Peak memory 200256 kb
Host smart-0b1d5bf6-cfb7-47ec-91fe-975ef5cd67e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002488697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1002488697
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1677991450
Short name T127
Test name
Test status
Simulation time 242997885 ps
CPU time 1.6 seconds
Started Jul 30 04:58:06 PM PDT 24
Finished Jul 30 04:58:08 PM PDT 24
Peak memory 200424 kb
Host smart-9bbf3c9a-e38e-4d1d-8eeb-8c71e706f6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677991450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1677991450
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3297992088
Short name T98
Test name
Test status
Simulation time 6393201351 ps
CPU time 24.87 seconds
Started Jul 30 04:58:06 PM PDT 24
Finished Jul 30 04:58:31 PM PDT 24
Peak memory 200792 kb
Host smart-1bbb05d1-32ac-4219-bd85-26b02bfc6506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297992088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3297992088
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1186555491
Short name T47
Test name
Test status
Simulation time 297947611 ps
CPU time 2.1 seconds
Started Jul 30 04:58:05 PM PDT 24
Finished Jul 30 04:58:07 PM PDT 24
Peak memory 208360 kb
Host smart-64da8d8d-bb05-4e61-886f-d97e3912dac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186555491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1186555491
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.419624747
Short name T134
Test name
Test status
Simulation time 136022429 ps
CPU time 1 seconds
Started Jul 30 04:58:05 PM PDT 24
Finished Jul 30 04:58:06 PM PDT 24
Peak memory 200292 kb
Host smart-3d7cc68d-c526-423e-90fa-eb803ea1271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419624747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.419624747
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2777096640
Short name T481
Test name
Test status
Simulation time 82027929 ps
CPU time 0.82 seconds
Started Jul 30 04:58:12 PM PDT 24
Finished Jul 30 04:58:13 PM PDT 24
Peak memory 200108 kb
Host smart-b91b506f-a811-4dbb-8905-8b1878b69ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777096640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2777096640
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2997034593
Short name T157
Test name
Test status
Simulation time 1901121009 ps
CPU time 7.36 seconds
Started Jul 30 04:58:10 PM PDT 24
Finished Jul 30 04:58:17 PM PDT 24
Peak memory 217376 kb
Host smart-e41ea970-b27d-4fcd-b1aa-c2fae54204ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997034593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2997034593
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3053497599
Short name T351
Test name
Test status
Simulation time 244239041 ps
CPU time 1.07 seconds
Started Jul 30 04:58:13 PM PDT 24
Finished Jul 30 04:58:14 PM PDT 24
Peak memory 217424 kb
Host smart-cab15a3a-0a4e-4a57-a9ca-834a7f698955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053497599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3053497599
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.468008413
Short name T20
Test name
Test status
Simulation time 138691073 ps
CPU time 0.83 seconds
Started Jul 30 04:58:06 PM PDT 24
Finished Jul 30 04:58:07 PM PDT 24
Peak memory 200084 kb
Host smart-fca37f03-f1d7-45a8-8e52-d03a8adb8967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468008413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.468008413
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2023203329
Short name T427
Test name
Test status
Simulation time 810363288 ps
CPU time 3.93 seconds
Started Jul 30 04:58:08 PM PDT 24
Finished Jul 30 04:58:12 PM PDT 24
Peak memory 200372 kb
Host smart-6b26a1f5-94d4-4b4a-8276-8ffc802bd895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023203329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2023203329
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1849899190
Short name T356
Test name
Test status
Simulation time 148830605 ps
CPU time 1.16 seconds
Started Jul 30 04:58:08 PM PDT 24
Finished Jul 30 04:58:09 PM PDT 24
Peak memory 200196 kb
Host smart-3b2938fa-041f-4332-aaba-be1637e62576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849899190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1849899190
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2221399675
Short name T438
Test name
Test status
Simulation time 197744656 ps
CPU time 1.38 seconds
Started Jul 30 04:58:07 PM PDT 24
Finished Jul 30 04:58:08 PM PDT 24
Peak memory 200452 kb
Host smart-b34cb40e-042b-4a5a-98c7-b14bb67a3ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221399675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2221399675
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.798573022
Short name T285
Test name
Test status
Simulation time 4540743216 ps
CPU time 16.27 seconds
Started Jul 30 04:58:11 PM PDT 24
Finished Jul 30 04:58:27 PM PDT 24
Peak memory 208748 kb
Host smart-70a9f4e4-5019-4008-b1e3-af681cb34968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798573022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.798573022
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1939043068
Short name T406
Test name
Test status
Simulation time 136983492 ps
CPU time 1.82 seconds
Started Jul 30 04:58:13 PM PDT 24
Finished Jul 30 04:58:15 PM PDT 24
Peak memory 200220 kb
Host smart-afae1301-7d45-4003-8930-d68fbf79e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939043068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1939043068
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2585832987
Short name T266
Test name
Test status
Simulation time 88154600 ps
CPU time 0.88 seconds
Started Jul 30 04:58:09 PM PDT 24
Finished Jul 30 04:58:10 PM PDT 24
Peak memory 200140 kb
Host smart-fe896bff-970c-45bf-933f-735f49aa02ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585832987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2585832987
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1499893054
Short name T461
Test name
Test status
Simulation time 79278673 ps
CPU time 0.8 seconds
Started Jul 30 04:58:11 PM PDT 24
Finished Jul 30 04:58:12 PM PDT 24
Peak memory 200072 kb
Host smart-04330cdb-7a7c-434a-aacf-f3ee7d565468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499893054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1499893054
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1639001474
Short name T3
Test name
Test status
Simulation time 1223835806 ps
CPU time 6.01 seconds
Started Jul 30 04:58:11 PM PDT 24
Finished Jul 30 04:58:17 PM PDT 24
Peak memory 217448 kb
Host smart-b0ae0164-6979-4a9b-a134-cc96fbd2b6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639001474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1639001474
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.397055489
Short name T423
Test name
Test status
Simulation time 245167162 ps
CPU time 1.12 seconds
Started Jul 30 04:58:09 PM PDT 24
Finished Jul 30 04:58:11 PM PDT 24
Peak memory 217496 kb
Host smart-2fab0dd8-2c4b-4750-a71e-12251dc8447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397055489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.397055489
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.4072110217
Short name T136
Test name
Test status
Simulation time 89741156 ps
CPU time 0.79 seconds
Started Jul 30 04:58:12 PM PDT 24
Finished Jul 30 04:58:13 PM PDT 24
Peak memory 200040 kb
Host smart-2d053a91-d864-4e28-bcc7-7bb75ec89f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072110217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.4072110217
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3811967968
Short name T407
Test name
Test status
Simulation time 1530256496 ps
CPU time 5.74 seconds
Started Jul 30 04:58:14 PM PDT 24
Finished Jul 30 04:58:20 PM PDT 24
Peak memory 200520 kb
Host smart-78bd2f18-c4d1-4ea4-a1a9-8b4291db36e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811967968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3811967968
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.760456750
Short name T151
Test name
Test status
Simulation time 111282207 ps
CPU time 1.09 seconds
Started Jul 30 04:58:10 PM PDT 24
Finished Jul 30 04:58:11 PM PDT 24
Peak memory 200288 kb
Host smart-c6ce3342-1418-4699-a1a1-4ad1ae754c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760456750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.760456750
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3052710332
Short name T392
Test name
Test status
Simulation time 121820082 ps
CPU time 1.21 seconds
Started Jul 30 04:58:09 PM PDT 24
Finished Jul 30 04:58:10 PM PDT 24
Peak memory 200416 kb
Host smart-047fb381-2674-4775-8755-5fcc4d81c1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052710332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3052710332
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2619447206
Short name T99
Test name
Test status
Simulation time 8631977135 ps
CPU time 28.85 seconds
Started Jul 30 04:58:12 PM PDT 24
Finished Jul 30 04:58:41 PM PDT 24
Peak memory 200540 kb
Host smart-25dd8910-60bd-411c-9b16-e3a3b2f43c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619447206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2619447206
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.830839618
Short name T488
Test name
Test status
Simulation time 331789668 ps
CPU time 2.28 seconds
Started Jul 30 04:58:09 PM PDT 24
Finished Jul 30 04:58:11 PM PDT 24
Peak memory 200252 kb
Host smart-25ea369b-6dfb-43c5-804d-20d0251dce6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830839618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.830839618
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.466661135
Short name T291
Test name
Test status
Simulation time 124992986 ps
CPU time 1.01 seconds
Started Jul 30 04:58:09 PM PDT 24
Finished Jul 30 04:58:11 PM PDT 24
Peak memory 200320 kb
Host smart-d1de144f-e496-4f0a-aee2-ae2ccd6fcfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466661135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.466661135
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.762756324
Short name T465
Test name
Test status
Simulation time 78230806 ps
CPU time 0.89 seconds
Started Jul 30 04:58:15 PM PDT 24
Finished Jul 30 04:58:16 PM PDT 24
Peak memory 200072 kb
Host smart-faf272ac-648e-433f-853a-79788964b3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762756324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.762756324
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3572611871
Short name T277
Test name
Test status
Simulation time 2339802641 ps
CPU time 7.7 seconds
Started Jul 30 04:58:15 PM PDT 24
Finished Jul 30 04:58:23 PM PDT 24
Peak memory 217756 kb
Host smart-17d6f48b-7087-41e0-a4a2-0658368af379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572611871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3572611871
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.219748550
Short name T385
Test name
Test status
Simulation time 244947105 ps
CPU time 1 seconds
Started Jul 30 04:58:17 PM PDT 24
Finished Jul 30 04:58:18 PM PDT 24
Peak memory 217424 kb
Host smart-33f96349-b8ea-4d4a-95dc-0e2d1fe2edbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219748550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.219748550
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.926492845
Short name T5
Test name
Test status
Simulation time 163537843 ps
CPU time 0.88 seconds
Started Jul 30 04:58:14 PM PDT 24
Finished Jul 30 04:58:15 PM PDT 24
Peak memory 200072 kb
Host smart-58ba4ece-9a11-48a1-aa32-7fae037615a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926492845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.926492845
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3663431567
Short name T100
Test name
Test status
Simulation time 1667374114 ps
CPU time 5.89 seconds
Started Jul 30 04:58:14 PM PDT 24
Finished Jul 30 04:58:20 PM PDT 24
Peak memory 200472 kb
Host smart-9b762903-a861-4128-ae0a-91cafeea972e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663431567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3663431567
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3951512992
Short name T45
Test name
Test status
Simulation time 152914482 ps
CPU time 1.2 seconds
Started Jul 30 04:58:12 PM PDT 24
Finished Jul 30 04:58:14 PM PDT 24
Peak memory 200120 kb
Host smart-9ef7f7d6-a37d-4f2a-b12a-200da4510cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951512992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3951512992
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1430691220
Short name T145
Test name
Test status
Simulation time 192080726 ps
CPU time 1.3 seconds
Started Jul 30 04:58:10 PM PDT 24
Finished Jul 30 04:58:11 PM PDT 24
Peak memory 200368 kb
Host smart-c26bae51-df53-4f70-8390-e2c8ec305b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430691220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1430691220
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1267355242
Short name T84
Test name
Test status
Simulation time 3039473525 ps
CPU time 11.83 seconds
Started Jul 30 04:58:13 PM PDT 24
Finished Jul 30 04:58:25 PM PDT 24
Peak memory 200624 kb
Host smart-4e7407e0-d200-4761-95cc-65bbc41cee16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267355242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1267355242
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1568807234
Short name T194
Test name
Test status
Simulation time 326525541 ps
CPU time 2.35 seconds
Started Jul 30 04:58:14 PM PDT 24
Finished Jul 30 04:58:17 PM PDT 24
Peak memory 200236 kb
Host smart-3e1a0237-1b93-4ba1-a356-c4a29882c85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568807234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1568807234
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2930502382
Short name T149
Test name
Test status
Simulation time 93660506 ps
CPU time 0.92 seconds
Started Jul 30 04:58:16 PM PDT 24
Finished Jul 30 04:58:17 PM PDT 24
Peak memory 200224 kb
Host smart-59294546-c171-42cd-a169-fa5076ebcdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930502382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2930502382
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2911045159
Short name T360
Test name
Test status
Simulation time 70155667 ps
CPU time 0.87 seconds
Started Jul 30 04:58:18 PM PDT 24
Finished Jul 30 04:58:19 PM PDT 24
Peak memory 199960 kb
Host smart-c8080e75-e2ee-46db-93db-d5d30988e6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911045159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2911045159
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2852478972
Short name T32
Test name
Test status
Simulation time 1895372432 ps
CPU time 7.46 seconds
Started Jul 30 04:58:13 PM PDT 24
Finished Jul 30 04:58:21 PM PDT 24
Peak memory 217212 kb
Host smart-2f81370e-ba94-4010-9ba9-b6e25a85308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852478972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2852478972
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3852351004
Short name T158
Test name
Test status
Simulation time 244411776 ps
CPU time 1.06 seconds
Started Jul 30 04:58:17 PM PDT 24
Finished Jul 30 04:58:19 PM PDT 24
Peak memory 217444 kb
Host smart-e49fef08-5282-4555-a6bc-d704d046eb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852351004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3852351004
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1440864744
Short name T373
Test name
Test status
Simulation time 124154708 ps
CPU time 0.8 seconds
Started Jul 30 04:58:15 PM PDT 24
Finished Jul 30 04:58:16 PM PDT 24
Peak memory 200096 kb
Host smart-aa8a3f5b-d1e2-4868-9c78-efd1709309a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440864744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1440864744
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2029442111
Short name T73
Test name
Test status
Simulation time 2133374764 ps
CPU time 7.65 seconds
Started Jul 30 04:58:15 PM PDT 24
Finished Jul 30 04:58:23 PM PDT 24
Peak memory 200504 kb
Host smart-64b770e7-fc86-4d51-b1ed-d71fb444aca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029442111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2029442111
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3375400874
Short name T372
Test name
Test status
Simulation time 176664872 ps
CPU time 1.3 seconds
Started Jul 30 04:58:13 PM PDT 24
Finished Jul 30 04:58:15 PM PDT 24
Peak memory 200240 kb
Host smart-39034fa3-7eef-4a76-9f33-7746e0157aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375400874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3375400874
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2350762842
Short name T305
Test name
Test status
Simulation time 193572942 ps
CPU time 1.37 seconds
Started Jul 30 04:58:15 PM PDT 24
Finished Jul 30 04:58:16 PM PDT 24
Peak memory 200384 kb
Host smart-3b577471-4793-4f26-bbf2-7893eefa58da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350762842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2350762842
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.220279140
Short name T379
Test name
Test status
Simulation time 8202767377 ps
CPU time 31.05 seconds
Started Jul 30 04:58:17 PM PDT 24
Finished Jul 30 04:58:48 PM PDT 24
Peak memory 208724 kb
Host smart-68aa52cb-8e5e-456b-89c4-f49d8e203142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220279140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.220279140
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3987629163
Short name T212
Test name
Test status
Simulation time 536992321 ps
CPU time 2.74 seconds
Started Jul 30 04:58:13 PM PDT 24
Finished Jul 30 04:58:16 PM PDT 24
Peak memory 200128 kb
Host smart-a1b7d120-8967-4fb8-9aaf-2a8bab245e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987629163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3987629163
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1167000952
Short name T390
Test name
Test status
Simulation time 159374909 ps
CPU time 1.1 seconds
Started Jul 30 04:58:15 PM PDT 24
Finished Jul 30 04:58:16 PM PDT 24
Peak memory 200140 kb
Host smart-5a709b55-3023-4e52-9095-f73caf14520e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167000952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1167000952
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3605868525
Short name T531
Test name
Test status
Simulation time 71197272 ps
CPU time 0.77 seconds
Started Jul 30 04:58:20 PM PDT 24
Finished Jul 30 04:58:21 PM PDT 24
Peak memory 199992 kb
Host smart-55b0e290-9f2b-4fb2-bef2-01362c771566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605868525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3605868525
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2480484999
Short name T235
Test name
Test status
Simulation time 1886633302 ps
CPU time 7.72 seconds
Started Jul 30 04:58:18 PM PDT 24
Finished Jul 30 04:58:26 PM PDT 24
Peak memory 221588 kb
Host smart-dabf4427-9aaf-4e93-ba00-465f5b515875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480484999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2480484999
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2796146325
Short name T521
Test name
Test status
Simulation time 244314728 ps
CPU time 1.17 seconds
Started Jul 30 04:58:18 PM PDT 24
Finished Jul 30 04:58:19 PM PDT 24
Peak memory 217444 kb
Host smart-869cd1d9-5b7e-42ff-bd44-cf5c26bbb16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796146325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2796146325
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.886331389
Short name T426
Test name
Test status
Simulation time 126363752 ps
CPU time 0.81 seconds
Started Jul 30 04:58:20 PM PDT 24
Finished Jul 30 04:58:21 PM PDT 24
Peak memory 199980 kb
Host smart-cc46eaed-356f-4c50-986b-bce3c8aa604b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886331389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.886331389
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3952355880
Short name T317
Test name
Test status
Simulation time 1379119164 ps
CPU time 5.33 seconds
Started Jul 30 04:58:16 PM PDT 24
Finished Jul 30 04:58:21 PM PDT 24
Peak memory 200388 kb
Host smart-1417c25b-15a4-4954-9522-d1d88ef10893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952355880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3952355880
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3689982592
Short name T191
Test name
Test status
Simulation time 185323139 ps
CPU time 1.23 seconds
Started Jul 30 04:58:18 PM PDT 24
Finished Jul 30 04:58:20 PM PDT 24
Peak memory 200144 kb
Host smart-4cf90930-0b27-4bb3-a8ec-f09f6727e821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689982592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3689982592
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3377063185
Short name T428
Test name
Test status
Simulation time 113285124 ps
CPU time 1.23 seconds
Started Jul 30 04:58:18 PM PDT 24
Finished Jul 30 04:58:19 PM PDT 24
Peak memory 200404 kb
Host smart-1bcbda07-4b99-49c3-ae03-7bff6295fc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377063185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3377063185
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.93346927
Short name T436
Test name
Test status
Simulation time 6571662441 ps
CPU time 22.92 seconds
Started Jul 30 04:58:18 PM PDT 24
Finished Jul 30 04:58:41 PM PDT 24
Peak memory 208752 kb
Host smart-3978b35e-79f9-4927-8bf9-3fc4b5f4a67a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93346927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.93346927
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3052290741
Short name T11
Test name
Test status
Simulation time 128071512 ps
CPU time 1.65 seconds
Started Jul 30 04:58:18 PM PDT 24
Finished Jul 30 04:58:20 PM PDT 24
Peak memory 208244 kb
Host smart-c568fe39-b806-4e59-8a6e-9aca404c992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052290741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3052290741
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3604269514
Short name T132
Test name
Test status
Simulation time 148023397 ps
CPU time 1.05 seconds
Started Jul 30 04:58:18 PM PDT 24
Finished Jul 30 04:58:19 PM PDT 24
Peak memory 200256 kb
Host smart-321fb2f0-50c5-4602-b91a-43262ae4ce2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604269514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3604269514
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1758973982
Short name T231
Test name
Test status
Simulation time 63285725 ps
CPU time 0.76 seconds
Started Jul 30 04:58:23 PM PDT 24
Finished Jul 30 04:58:24 PM PDT 24
Peak memory 200108 kb
Host smart-660ff227-742c-4edc-8679-3fcd85545365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758973982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1758973982
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1068091674
Short name T359
Test name
Test status
Simulation time 2359386783 ps
CPU time 9.39 seconds
Started Jul 30 04:58:25 PM PDT 24
Finished Jul 30 04:58:34 PM PDT 24
Peak memory 217696 kb
Host smart-1c89b06f-6688-4cfb-bbf7-3170e529a979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068091674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1068091674
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1455807513
Short name T474
Test name
Test status
Simulation time 244279470 ps
CPU time 1.1 seconds
Started Jul 30 04:58:25 PM PDT 24
Finished Jul 30 04:58:26 PM PDT 24
Peak memory 217396 kb
Host smart-707fece4-40ce-4bf9-8e16-08544dac5ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455807513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1455807513
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.333360893
Short name T17
Test name
Test status
Simulation time 144707918 ps
CPU time 0.91 seconds
Started Jul 30 04:58:18 PM PDT 24
Finished Jul 30 04:58:19 PM PDT 24
Peak memory 200108 kb
Host smart-e409fb3c-0f03-4297-8b9e-b18779cfd09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333360893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.333360893
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1490158924
Short name T376
Test name
Test status
Simulation time 1662285658 ps
CPU time 6.6 seconds
Started Jul 30 04:58:17 PM PDT 24
Finished Jul 30 04:58:23 PM PDT 24
Peak memory 200484 kb
Host smart-bde1a8ea-62c8-4155-9b99-bd67b8a14d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490158924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1490158924
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.884963221
Short name T252
Test name
Test status
Simulation time 170700514 ps
CPU time 1.21 seconds
Started Jul 30 04:58:24 PM PDT 24
Finished Jul 30 04:58:26 PM PDT 24
Peak memory 200252 kb
Host smart-0a6ebd91-a4fc-4926-b20d-317bf7cf8446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884963221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.884963221
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.149026510
Short name T362
Test name
Test status
Simulation time 208901291 ps
CPU time 1.38 seconds
Started Jul 30 04:58:21 PM PDT 24
Finished Jul 30 04:58:23 PM PDT 24
Peak memory 200364 kb
Host smart-5f37f834-aa12-4add-84a0-d71f0fd0e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149026510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.149026510
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3641857662
Short name T311
Test name
Test status
Simulation time 2245217597 ps
CPU time 11.05 seconds
Started Jul 30 04:58:24 PM PDT 24
Finished Jul 30 04:58:35 PM PDT 24
Peak memory 208712 kb
Host smart-5aeb45c7-151f-4c4b-98a9-19a209ff8d4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641857662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3641857662
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2334183221
Short name T441
Test name
Test status
Simulation time 379823777 ps
CPU time 2.26 seconds
Started Jul 30 04:58:23 PM PDT 24
Finished Jul 30 04:58:25 PM PDT 24
Peak memory 200080 kb
Host smart-bb447c99-963d-4f94-9e5f-6cd1fe139c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334183221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2334183221
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3523623285
Short name T184
Test name
Test status
Simulation time 218071915 ps
CPU time 1.4 seconds
Started Jul 30 04:58:25 PM PDT 24
Finished Jul 30 04:58:27 PM PDT 24
Peak memory 200284 kb
Host smart-0f799ea0-7bee-4e2d-a2d6-2e621d92ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523623285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3523623285
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2633091227
Short name T224
Test name
Test status
Simulation time 70697263 ps
CPU time 0.84 seconds
Started Jul 30 04:58:26 PM PDT 24
Finished Jul 30 04:58:27 PM PDT 24
Peak memory 199852 kb
Host smart-abea5c0e-5367-4e9b-a7be-82b02d9e185f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633091227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2633091227
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.408656984
Short name T31
Test name
Test status
Simulation time 1908744613 ps
CPU time 7.41 seconds
Started Jul 30 04:58:23 PM PDT 24
Finished Jul 30 04:58:30 PM PDT 24
Peak memory 217648 kb
Host smart-a537162d-34d9-43f4-bd5f-fbf0f8ad2fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408656984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.408656984
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3425770054
Short name T310
Test name
Test status
Simulation time 244538932 ps
CPU time 1.17 seconds
Started Jul 30 04:58:22 PM PDT 24
Finished Jul 30 04:58:23 PM PDT 24
Peak memory 217328 kb
Host smart-ee921b8f-c855-4600-95f9-7891cad82a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425770054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3425770054
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1266384280
Short name T197
Test name
Test status
Simulation time 88522646 ps
CPU time 0.8 seconds
Started Jul 30 04:58:26 PM PDT 24
Finished Jul 30 04:58:27 PM PDT 24
Peak memory 200072 kb
Host smart-fab92de7-5b59-495d-b6a4-188f911abc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266384280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1266384280
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3304089806
Short name T388
Test name
Test status
Simulation time 1392662507 ps
CPU time 5.49 seconds
Started Jul 30 04:58:25 PM PDT 24
Finished Jul 30 04:58:31 PM PDT 24
Peak memory 200480 kb
Host smart-1d235144-31bf-41aa-b2d9-394b0874ee73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304089806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3304089806
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3182004793
Short name T365
Test name
Test status
Simulation time 151779293 ps
CPU time 1.21 seconds
Started Jul 30 04:58:26 PM PDT 24
Finished Jul 30 04:58:27 PM PDT 24
Peak memory 200304 kb
Host smart-17c31c54-30c2-405a-884c-e998a8569945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182004793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3182004793
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2681401472
Short name T346
Test name
Test status
Simulation time 224239055 ps
CPU time 1.64 seconds
Started Jul 30 04:58:21 PM PDT 24
Finished Jul 30 04:58:23 PM PDT 24
Peak memory 200352 kb
Host smart-65931506-01e7-4814-8e84-13956ecc03ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681401472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2681401472
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3744706735
Short name T37
Test name
Test status
Simulation time 3723316629 ps
CPU time 19.62 seconds
Started Jul 30 04:58:25 PM PDT 24
Finished Jul 30 04:58:44 PM PDT 24
Peak memory 210536 kb
Host smart-f249a439-4b17-4c33-a8ec-c62ca8246e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744706735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3744706735
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3643195597
Short name T408
Test name
Test status
Simulation time 130037793 ps
CPU time 1.6 seconds
Started Jul 30 04:58:25 PM PDT 24
Finished Jul 30 04:58:27 PM PDT 24
Peak memory 208420 kb
Host smart-0f1c94a6-05ad-400a-b7f4-28eeed622a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643195597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3643195597
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1575675568
Short name T104
Test name
Test status
Simulation time 103695234 ps
CPU time 0.86 seconds
Started Jul 30 04:58:27 PM PDT 24
Finished Jul 30 04:58:28 PM PDT 24
Peak memory 200248 kb
Host smart-34f3ec6b-2058-4032-a4b4-841d590930cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575675568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1575675568
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3617695193
Short name T182
Test name
Test status
Simulation time 71279823 ps
CPU time 0.84 seconds
Started Jul 30 04:58:27 PM PDT 24
Finished Jul 30 04:58:28 PM PDT 24
Peak memory 199908 kb
Host smart-253e44b3-5c9c-4353-a827-3c164efe672c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617695193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3617695193
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3717674380
Short name T472
Test name
Test status
Simulation time 243953301 ps
CPU time 1.07 seconds
Started Jul 30 04:58:26 PM PDT 24
Finished Jul 30 04:58:27 PM PDT 24
Peak memory 217352 kb
Host smart-8d27bdaa-ccee-4c3c-abdf-144149f15d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717674380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3717674380
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3402356584
Short name T265
Test name
Test status
Simulation time 136730861 ps
CPU time 0.82 seconds
Started Jul 30 04:58:27 PM PDT 24
Finished Jul 30 04:58:28 PM PDT 24
Peak memory 200040 kb
Host smart-e58a2dcb-3f19-4385-8a79-36bf73c0d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402356584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3402356584
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.374047474
Short name T421
Test name
Test status
Simulation time 2005930904 ps
CPU time 6.95 seconds
Started Jul 30 04:58:28 PM PDT 24
Finished Jul 30 04:58:35 PM PDT 24
Peak memory 200424 kb
Host smart-bd8e9e38-e2db-4be3-9743-d18ffe5b0c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374047474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.374047474
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.368362559
Short name T459
Test name
Test status
Simulation time 100613515 ps
CPU time 1 seconds
Started Jul 30 04:58:28 PM PDT 24
Finished Jul 30 04:58:29 PM PDT 24
Peak memory 200288 kb
Host smart-613927ee-ea7c-4047-b524-de5bcd8a9089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368362559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.368362559
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1851759704
Short name T397
Test name
Test status
Simulation time 113405731 ps
CPU time 1.25 seconds
Started Jul 30 04:58:26 PM PDT 24
Finished Jul 30 04:58:28 PM PDT 24
Peak memory 200124 kb
Host smart-66874cf8-4a5d-4865-9fab-afd64688cc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851759704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1851759704
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1035921277
Short name T368
Test name
Test status
Simulation time 2888770599 ps
CPU time 12.07 seconds
Started Jul 30 04:58:26 PM PDT 24
Finished Jul 30 04:58:39 PM PDT 24
Peak memory 208752 kb
Host smart-a44c3cc3-af51-4b12-b167-16824fc58b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035921277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1035921277
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2198564832
Short name T192
Test name
Test status
Simulation time 454701676 ps
CPU time 3.04 seconds
Started Jul 30 04:58:26 PM PDT 24
Finished Jul 30 04:58:29 PM PDT 24
Peak memory 200212 kb
Host smart-99daa4a0-0973-4228-a3b5-0a7637e7e72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198564832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2198564832
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.961769952
Short name T275
Test name
Test status
Simulation time 150957953 ps
CPU time 1.25 seconds
Started Jul 30 04:58:25 PM PDT 24
Finished Jul 30 04:58:26 PM PDT 24
Peak memory 200176 kb
Host smart-cc109060-f2e0-47be-8180-261459a434f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961769952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.961769952
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.304064694
Short name T153
Test name
Test status
Simulation time 72534692 ps
CPU time 0.87 seconds
Started Jul 30 04:58:35 PM PDT 24
Finished Jul 30 04:58:36 PM PDT 24
Peak memory 199944 kb
Host smart-6ce2a43b-98f6-4e3a-87e9-d100a949a29f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304064694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.304064694
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.404787659
Short name T334
Test name
Test status
Simulation time 1870925985 ps
CPU time 7.17 seconds
Started Jul 30 04:58:36 PM PDT 24
Finished Jul 30 04:58:44 PM PDT 24
Peak memory 221620 kb
Host smart-52493087-7267-4e19-952e-5bb16eef993f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404787659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.404787659
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1822254741
Short name T232
Test name
Test status
Simulation time 244748818 ps
CPU time 1.07 seconds
Started Jul 30 04:58:33 PM PDT 24
Finished Jul 30 04:58:34 PM PDT 24
Peak memory 217428 kb
Host smart-81cd58e2-4536-4d74-a50d-4fc903496ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822254741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1822254741
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1458539599
Short name T510
Test name
Test status
Simulation time 110451525 ps
CPU time 0.88 seconds
Started Jul 30 04:58:27 PM PDT 24
Finished Jul 30 04:58:28 PM PDT 24
Peak memory 200096 kb
Host smart-2a2943bd-02c0-4616-98f3-7b7c16d386eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458539599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1458539599
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.739425563
Short name T383
Test name
Test status
Simulation time 1502501378 ps
CPU time 6.04 seconds
Started Jul 30 04:58:28 PM PDT 24
Finished Jul 30 04:58:34 PM PDT 24
Peak memory 200516 kb
Host smart-3653d2b9-fd7e-468a-8d6a-e93c5de7fe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739425563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.739425563
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1459022961
Short name T536
Test name
Test status
Simulation time 98691464 ps
CPU time 1.02 seconds
Started Jul 30 04:58:36 PM PDT 24
Finished Jul 30 04:58:37 PM PDT 24
Peak memory 200196 kb
Host smart-b5a8070e-ba45-4466-ae19-d7648663d1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459022961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1459022961
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.40499066
Short name T398
Test name
Test status
Simulation time 111647311 ps
CPU time 1.23 seconds
Started Jul 30 04:58:26 PM PDT 24
Finished Jul 30 04:58:28 PM PDT 24
Peak memory 200412 kb
Host smart-0a8d993a-1d66-40c4-93e4-120073d76138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40499066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.40499066
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.137665085
Short name T464
Test name
Test status
Simulation time 549411663 ps
CPU time 2.93 seconds
Started Jul 30 04:58:33 PM PDT 24
Finished Jul 30 04:58:36 PM PDT 24
Peak memory 200412 kb
Host smart-62cf73e3-185d-4809-8983-9377bb2248b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137665085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.137665085
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.270614160
Short name T137
Test name
Test status
Simulation time 301499249 ps
CPU time 2 seconds
Started Jul 30 04:58:32 PM PDT 24
Finished Jul 30 04:58:34 PM PDT 24
Peak memory 208456 kb
Host smart-475691c3-54f9-4ae2-ab37-97d75be48dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270614160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.270614160
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3570767694
Short name T422
Test name
Test status
Simulation time 223831120 ps
CPU time 1.36 seconds
Started Jul 30 04:58:36 PM PDT 24
Finished Jul 30 04:58:37 PM PDT 24
Peak memory 200208 kb
Host smart-e4300cd8-75a9-486e-a0ef-c30f6cca4d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570767694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3570767694
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.853759607
Short name T430
Test name
Test status
Simulation time 54580062 ps
CPU time 0.73 seconds
Started Jul 30 04:56:11 PM PDT 24
Finished Jul 30 04:56:12 PM PDT 24
Peak memory 200072 kb
Host smart-cb07f9fb-a0bc-421f-8881-5c54202ad044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853759607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.853759607
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1650164284
Short name T29
Test name
Test status
Simulation time 2382387645 ps
CPU time 10.76 seconds
Started Jul 30 04:56:11 PM PDT 24
Finished Jul 30 04:56:22 PM PDT 24
Peak memory 217716 kb
Host smart-01f2d0cf-e492-420e-b61c-6f165eafdf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650164284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1650164284
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3622941327
Short name T148
Test name
Test status
Simulation time 243914181 ps
CPU time 1.16 seconds
Started Jul 30 04:56:11 PM PDT 24
Finished Jul 30 04:56:13 PM PDT 24
Peak memory 217340 kb
Host smart-57972854-8c0d-4795-8489-a98412aa9685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622941327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3622941327
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1378911041
Short name T367
Test name
Test status
Simulation time 211781583 ps
CPU time 1 seconds
Started Jul 30 04:56:09 PM PDT 24
Finished Jul 30 04:56:10 PM PDT 24
Peak memory 200092 kb
Host smart-671d1adb-fa55-4b18-aaad-45fc030ae552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378911041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1378911041
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2084107080
Short name T245
Test name
Test status
Simulation time 1604128566 ps
CPU time 6.11 seconds
Started Jul 30 04:56:07 PM PDT 24
Finished Jul 30 04:56:14 PM PDT 24
Peak memory 200340 kb
Host smart-9f7f7c90-4dee-449a-b034-91e025a92cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084107080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2084107080
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4024764707
Short name T63
Test name
Test status
Simulation time 8419718837 ps
CPU time 13.55 seconds
Started Jul 30 04:56:12 PM PDT 24
Finished Jul 30 04:56:26 PM PDT 24
Peak memory 217084 kb
Host smart-0be6f9de-b69f-4604-88e8-340037538907
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024764707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4024764707
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3442649377
Short name T391
Test name
Test status
Simulation time 179286309 ps
CPU time 1.22 seconds
Started Jul 30 04:56:12 PM PDT 24
Finished Jul 30 04:56:13 PM PDT 24
Peak memory 200124 kb
Host smart-c961d25b-034a-4895-b32d-ca93a3df488f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442649377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3442649377
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3796877156
Short name T125
Test name
Test status
Simulation time 112610496 ps
CPU time 1.18 seconds
Started Jul 30 04:56:07 PM PDT 24
Finished Jul 30 04:56:08 PM PDT 24
Peak memory 200328 kb
Host smart-7d2f6b3b-c2bb-4908-9690-939dfc9bd10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796877156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3796877156
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2429112348
Short name T242
Test name
Test status
Simulation time 6301340813 ps
CPU time 28.43 seconds
Started Jul 30 04:56:13 PM PDT 24
Finished Jul 30 04:56:41 PM PDT 24
Peak memory 200404 kb
Host smart-38fca4fe-870d-44fd-82a5-3143afd39064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429112348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2429112348
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1275005416
Short name T514
Test name
Test status
Simulation time 285124685 ps
CPU time 1.99 seconds
Started Jul 30 04:56:09 PM PDT 24
Finished Jul 30 04:56:11 PM PDT 24
Peak memory 200176 kb
Host smart-294ebdfa-d85d-423b-a8ed-0ad7dfd99166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275005416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1275005416
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.4154661930
Short name T150
Test name
Test status
Simulation time 199749606 ps
CPU time 1.31 seconds
Started Jul 30 04:56:07 PM PDT 24
Finished Jul 30 04:56:08 PM PDT 24
Peak memory 200120 kb
Host smart-3f5b6e28-d593-43c3-9ed9-cecd0d386d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154661930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4154661930
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2754561212
Short name T133
Test name
Test status
Simulation time 96203272 ps
CPU time 0.85 seconds
Started Jul 30 04:58:38 PM PDT 24
Finished Jul 30 04:58:39 PM PDT 24
Peak memory 200080 kb
Host smart-3adb4333-8bd3-4a58-8e2a-f93f141a1927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754561212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2754561212
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.671674989
Short name T284
Test name
Test status
Simulation time 1219336628 ps
CPU time 5.79 seconds
Started Jul 30 04:58:40 PM PDT 24
Finished Jul 30 04:58:46 PM PDT 24
Peak memory 221588 kb
Host smart-01d5edb8-92d6-4fb3-90c8-56f88d4a9abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671674989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.671674989
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1142801706
Short name T538
Test name
Test status
Simulation time 244125219 ps
CPU time 1.04 seconds
Started Jul 30 04:58:36 PM PDT 24
Finished Jul 30 04:58:38 PM PDT 24
Peak memory 217420 kb
Host smart-97cca737-31d0-406e-997e-22cf4742fcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142801706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1142801706
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2386209916
Short name T316
Test name
Test status
Simulation time 96025748 ps
CPU time 0.83 seconds
Started Jul 30 04:58:32 PM PDT 24
Finished Jul 30 04:58:33 PM PDT 24
Peak memory 200040 kb
Host smart-6bb6c3bd-1a95-48d8-8598-9d3c697b4ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386209916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2386209916
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.420071149
Short name T248
Test name
Test status
Simulation time 769695707 ps
CPU time 4.26 seconds
Started Jul 30 04:58:33 PM PDT 24
Finished Jul 30 04:58:37 PM PDT 24
Peak memory 200464 kb
Host smart-a912a015-a3c8-4eef-bf9f-73cf32fbfc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420071149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.420071149
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3071711449
Short name T13
Test name
Test status
Simulation time 142486897 ps
CPU time 1.14 seconds
Started Jul 30 04:58:43 PM PDT 24
Finished Jul 30 04:58:44 PM PDT 24
Peak memory 200248 kb
Host smart-2c64d771-e218-49f7-9851-68edda71f385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071711449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3071711449
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3239655656
Short name T518
Test name
Test status
Simulation time 125026097 ps
CPU time 1.22 seconds
Started Jul 30 04:58:32 PM PDT 24
Finished Jul 30 04:58:33 PM PDT 24
Peak memory 200400 kb
Host smart-e65e3698-2a78-4627-b46a-1780a4154dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239655656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3239655656
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1924103886
Short name T519
Test name
Test status
Simulation time 9522479691 ps
CPU time 36.42 seconds
Started Jul 30 04:58:38 PM PDT 24
Finished Jul 30 04:59:14 PM PDT 24
Peak memory 208716 kb
Host smart-7de9c5e4-761d-4f1f-b023-5293cfb9d41b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924103886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1924103886
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.628388007
Short name T254
Test name
Test status
Simulation time 149248735 ps
CPU time 1.84 seconds
Started Jul 30 04:58:40 PM PDT 24
Finished Jul 30 04:58:42 PM PDT 24
Peak memory 200236 kb
Host smart-382b9732-a983-4767-902f-89b552ac579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628388007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.628388007
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.97998477
Short name T439
Test name
Test status
Simulation time 74155420 ps
CPU time 0.83 seconds
Started Jul 30 04:58:40 PM PDT 24
Finished Jul 30 04:58:41 PM PDT 24
Peak memory 200260 kb
Host smart-fdfaf7f0-3a8b-4d52-a27a-81b72dd2a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97998477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.97998477
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3110257252
Short name T115
Test name
Test status
Simulation time 71830131 ps
CPU time 0.81 seconds
Started Jul 30 04:58:45 PM PDT 24
Finished Jul 30 04:58:46 PM PDT 24
Peak memory 200096 kb
Host smart-9b5d60fb-649b-4a15-8e2e-307b2315e983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110257252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3110257252
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.32721085
Short name T401
Test name
Test status
Simulation time 2345305832 ps
CPU time 8.96 seconds
Started Jul 30 04:58:35 PM PDT 24
Finished Jul 30 04:58:45 PM PDT 24
Peak memory 221756 kb
Host smart-a5bfd3a6-2426-490a-bf8d-34c2caf5f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32721085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.32721085
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4080065421
Short name T189
Test name
Test status
Simulation time 243621527 ps
CPU time 1.15 seconds
Started Jul 30 04:58:39 PM PDT 24
Finished Jul 30 04:58:40 PM PDT 24
Peak memory 217412 kb
Host smart-667ea23a-d6bd-4d59-852f-6d703c6dbe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080065421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4080065421
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3285724931
Short name T529
Test name
Test status
Simulation time 214658329 ps
CPU time 0.91 seconds
Started Jul 30 04:58:38 PM PDT 24
Finished Jul 30 04:58:39 PM PDT 24
Peak memory 200076 kb
Host smart-12c27c08-a9d5-4cb7-8b88-b85d6ca8fc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285724931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3285724931
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2692715373
Short name T202
Test name
Test status
Simulation time 1578956607 ps
CPU time 6.42 seconds
Started Jul 30 04:58:37 PM PDT 24
Finished Jul 30 04:58:44 PM PDT 24
Peak memory 200468 kb
Host smart-dca9ea27-10c9-440f-861a-dd7f2ad3bed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692715373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2692715373
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3731516768
Short name T516
Test name
Test status
Simulation time 184120760 ps
CPU time 1.2 seconds
Started Jul 30 04:58:38 PM PDT 24
Finished Jul 30 04:58:39 PM PDT 24
Peak memory 200288 kb
Host smart-b97a9e85-7450-4e75-8b89-788a4c5d0e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731516768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3731516768
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.755849654
Short name T209
Test name
Test status
Simulation time 114956624 ps
CPU time 1.25 seconds
Started Jul 30 04:58:36 PM PDT 24
Finished Jul 30 04:58:38 PM PDT 24
Peak memory 200436 kb
Host smart-84c05bb7-cccc-42c5-878b-40756a19c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755849654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.755849654
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3114671729
Short name T505
Test name
Test status
Simulation time 3342524719 ps
CPU time 15.26 seconds
Started Jul 30 04:58:36 PM PDT 24
Finished Jul 30 04:58:51 PM PDT 24
Peak memory 200596 kb
Host smart-2c7cf94c-91e4-4e4a-8437-f1511e71a9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114671729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3114671729
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1732448491
Short name T485
Test name
Test status
Simulation time 439905993 ps
CPU time 2.59 seconds
Started Jul 30 04:58:41 PM PDT 24
Finished Jul 30 04:58:44 PM PDT 24
Peak memory 208420 kb
Host smart-a4b2a5ec-9ca2-4bf9-a1a0-152ab537f74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732448491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1732448491
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1572891192
Short name T6
Test name
Test status
Simulation time 223615426 ps
CPU time 1.34 seconds
Started Jul 30 04:58:39 PM PDT 24
Finished Jul 30 04:58:40 PM PDT 24
Peak memory 200216 kb
Host smart-d755e3a8-84bd-4375-9a88-57422af9da57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572891192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1572891192
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1821170919
Short name T322
Test name
Test status
Simulation time 57915995 ps
CPU time 0.79 seconds
Started Jul 30 04:58:45 PM PDT 24
Finished Jul 30 04:58:46 PM PDT 24
Peak memory 199872 kb
Host smart-b2c8cc2e-0d32-47e5-bf28-063520ddee0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821170919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1821170919
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.36008733
Short name T255
Test name
Test status
Simulation time 2158305865 ps
CPU time 8.4 seconds
Started Jul 30 04:58:45 PM PDT 24
Finished Jul 30 04:58:54 PM PDT 24
Peak memory 217592 kb
Host smart-3e18e886-0ecd-4ac1-85c4-c220b1047847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36008733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.36008733
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1057971649
Short name T119
Test name
Test status
Simulation time 245988903 ps
CPU time 1.08 seconds
Started Jul 30 04:58:44 PM PDT 24
Finished Jul 30 04:58:45 PM PDT 24
Peak memory 217424 kb
Host smart-a5536f3c-dd76-4b23-9020-a0629a06b019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057971649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1057971649
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2551231055
Short name T418
Test name
Test status
Simulation time 215744074 ps
CPU time 0.94 seconds
Started Jul 30 04:58:40 PM PDT 24
Finished Jul 30 04:58:41 PM PDT 24
Peak memory 200080 kb
Host smart-d6ed37e0-8e18-42ba-9449-9e12f5a68a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551231055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2551231055
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2234296482
Short name T469
Test name
Test status
Simulation time 1656672114 ps
CPU time 6.37 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:52 PM PDT 24
Peak memory 200424 kb
Host smart-6ee68146-64a1-4412-92ab-3d7a7bc50958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234296482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2234296482
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.600479919
Short name T171
Test name
Test status
Simulation time 181817723 ps
CPU time 1.17 seconds
Started Jul 30 04:58:42 PM PDT 24
Finished Jul 30 04:58:43 PM PDT 24
Peak memory 200272 kb
Host smart-cc6b5028-429d-47ef-ab4a-4e6ea666d068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600479919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.600479919
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.658756320
Short name T161
Test name
Test status
Simulation time 124322172 ps
CPU time 1.23 seconds
Started Jul 30 04:58:40 PM PDT 24
Finished Jul 30 04:58:41 PM PDT 24
Peak memory 200376 kb
Host smart-e940791a-7cc5-4e21-9f0f-f675a3b6b351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658756320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.658756320
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2200074293
Short name T74
Test name
Test status
Simulation time 12487550589 ps
CPU time 42.82 seconds
Started Jul 30 04:58:42 PM PDT 24
Finished Jul 30 04:59:25 PM PDT 24
Peak memory 208780 kb
Host smart-55568a6b-85bf-47a4-a838-626d82a47e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200074293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2200074293
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3562422472
Short name T413
Test name
Test status
Simulation time 135081279 ps
CPU time 1.87 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:48 PM PDT 24
Peak memory 208372 kb
Host smart-8b1e4ce2-156a-439c-b6a8-9f0008ea056a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562422472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3562422472
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4055500176
Short name T152
Test name
Test status
Simulation time 222242442 ps
CPU time 1.3 seconds
Started Jul 30 04:58:40 PM PDT 24
Finished Jul 30 04:58:42 PM PDT 24
Peak memory 200256 kb
Host smart-9f484bc0-003d-4960-8003-4bf9af1997e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055500176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4055500176
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2832413786
Short name T59
Test name
Test status
Simulation time 71818641 ps
CPU time 0.81 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:47 PM PDT 24
Peak memory 200332 kb
Host smart-62cd63b8-0076-4701-ac94-8ae65dbabfd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832413786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2832413786
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3256710604
Short name T40
Test name
Test status
Simulation time 1224797168 ps
CPU time 5.37 seconds
Started Jul 30 04:58:45 PM PDT 24
Finished Jul 30 04:58:50 PM PDT 24
Peak memory 221556 kb
Host smart-52c45132-6516-4ab1-bcbe-2d3b9e0cb6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256710604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3256710604
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1427718448
Short name T389
Test name
Test status
Simulation time 243875673 ps
CPU time 1.04 seconds
Started Jul 30 04:58:41 PM PDT 24
Finished Jul 30 04:58:42 PM PDT 24
Peak memory 217388 kb
Host smart-d36ed75a-dcb4-4a4c-a09d-646e1db7b5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427718448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1427718448
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2841992136
Short name T139
Test name
Test status
Simulation time 158032858 ps
CPU time 0.84 seconds
Started Jul 30 04:58:39 PM PDT 24
Finished Jul 30 04:58:40 PM PDT 24
Peak memory 200016 kb
Host smart-27963d8b-b0ae-47b0-9848-04270d85f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841992136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2841992136
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3464138868
Short name T354
Test name
Test status
Simulation time 1646078888 ps
CPU time 6.54 seconds
Started Jul 30 04:58:41 PM PDT 24
Finished Jul 30 04:58:48 PM PDT 24
Peak memory 200532 kb
Host smart-3258d10e-48f8-43fe-a464-23ad9034c89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464138868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3464138868
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2178743134
Short name T489
Test name
Test status
Simulation time 142908242 ps
CPU time 1.26 seconds
Started Jul 30 04:58:42 PM PDT 24
Finished Jul 30 04:58:44 PM PDT 24
Peak memory 200268 kb
Host smart-074d87df-ca05-4778-9713-9c91287f2fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178743134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2178743134
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3311930031
Short name T286
Test name
Test status
Simulation time 206319772 ps
CPU time 1.4 seconds
Started Jul 30 04:58:45 PM PDT 24
Finished Jul 30 04:58:47 PM PDT 24
Peak memory 200404 kb
Host smart-11dde11c-1921-4218-a454-efd246839241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311930031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3311930031
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1720593243
Short name T185
Test name
Test status
Simulation time 2018126003 ps
CPU time 7.93 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:55 PM PDT 24
Peak memory 200512 kb
Host smart-fa2891af-e74e-4f45-a0a1-cc2e68743417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720593243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1720593243
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.409506529
Short name T46
Test name
Test status
Simulation time 261037112 ps
CPU time 1.84 seconds
Started Jul 30 04:58:40 PM PDT 24
Finished Jul 30 04:58:42 PM PDT 24
Peak memory 200076 kb
Host smart-692d651c-5b19-467c-a84d-0483ab8aa1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409506529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.409506529
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.280700794
Short name T509
Test name
Test status
Simulation time 277023347 ps
CPU time 1.6 seconds
Started Jul 30 04:58:40 PM PDT 24
Finished Jul 30 04:58:42 PM PDT 24
Peak memory 200400 kb
Host smart-f3c2cae0-1aab-44b0-8dea-6a401e424fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280700794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.280700794
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.424858695
Short name T138
Test name
Test status
Simulation time 77610603 ps
CPU time 0.76 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:46 PM PDT 24
Peak memory 200036 kb
Host smart-897a2065-2393-4028-b9b5-db03952699e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424858695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.424858695
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3555911207
Short name T297
Test name
Test status
Simulation time 1883928284 ps
CPU time 7.31 seconds
Started Jul 30 04:58:44 PM PDT 24
Finished Jul 30 04:58:52 PM PDT 24
Peak memory 217676 kb
Host smart-7d16fad9-d519-42e6-844e-57cbd7284ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555911207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3555911207
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.663592127
Short name T308
Test name
Test status
Simulation time 244581112 ps
CPU time 1.06 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:47 PM PDT 24
Peak memory 217424 kb
Host smart-f48f38f5-ef77-4912-83fa-8f0db6b78fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663592127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.663592127
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3810897940
Short name T238
Test name
Test status
Simulation time 99786229 ps
CPU time 0.79 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:47 PM PDT 24
Peak memory 200076 kb
Host smart-ae166843-eac3-4d6a-a679-4114810698c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810897940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3810897940
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2445898430
Short name T131
Test name
Test status
Simulation time 1518705912 ps
CPU time 6.49 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:52 PM PDT 24
Peak memory 200508 kb
Host smart-ad1a2e9e-afa5-4a4e-b827-69d04feec992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445898430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2445898430
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1722828205
Short name T274
Test name
Test status
Simulation time 107611974 ps
CPU time 1.05 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:48 PM PDT 24
Peak memory 200312 kb
Host smart-2595b7f7-905c-4795-8b64-9f74d552b67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722828205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1722828205
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.444834354
Short name T162
Test name
Test status
Simulation time 119030796 ps
CPU time 1.21 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:47 PM PDT 24
Peak memory 200368 kb
Host smart-476cf981-b631-4668-bd14-b1b3999327ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444834354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.444834354
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3611486795
Short name T221
Test name
Test status
Simulation time 3578105127 ps
CPU time 13.2 seconds
Started Jul 30 04:58:48 PM PDT 24
Finished Jul 30 04:59:02 PM PDT 24
Peak memory 200544 kb
Host smart-ceb7f5fb-91cd-4652-ad3e-845fa89c2c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611486795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3611486795
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1788973163
Short name T487
Test name
Test status
Simulation time 137117994 ps
CPU time 1.24 seconds
Started Jul 30 04:58:48 PM PDT 24
Finished Jul 30 04:58:50 PM PDT 24
Peak memory 200244 kb
Host smart-7ae77d1d-ddc3-40cb-8ce4-577ecb9d3228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788973163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1788973163
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2239682240
Short name T400
Test name
Test status
Simulation time 91530654 ps
CPU time 0.84 seconds
Started Jul 30 04:58:49 PM PDT 24
Finished Jul 30 04:58:50 PM PDT 24
Peak memory 199956 kb
Host smart-5f50ae60-f8d5-47e8-85ec-0d18aef10953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239682240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2239682240
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3419638630
Short name T479
Test name
Test status
Simulation time 1220322675 ps
CPU time 5.45 seconds
Started Jul 30 04:58:48 PM PDT 24
Finished Jul 30 04:58:54 PM PDT 24
Peak memory 216924 kb
Host smart-b3c4816b-9a38-4bc9-82e7-4213ab133069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419638630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3419638630
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.666450988
Short name T112
Test name
Test status
Simulation time 245440404 ps
CPU time 1.04 seconds
Started Jul 30 04:58:51 PM PDT 24
Finished Jul 30 04:58:52 PM PDT 24
Peak memory 217488 kb
Host smart-2298e1d1-cd79-448b-9790-16a1d1db7d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666450988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.666450988
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3963634550
Short name T411
Test name
Test status
Simulation time 92113518 ps
CPU time 0.78 seconds
Started Jul 30 04:58:54 PM PDT 24
Finished Jul 30 04:58:55 PM PDT 24
Peak memory 199952 kb
Host smart-b5b4c8e2-62a9-489e-bd91-c96e09c3b79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963634550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3963634550
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2633860577
Short name T279
Test name
Test status
Simulation time 1151738485 ps
CPU time 4.81 seconds
Started Jul 30 04:58:46 PM PDT 24
Finished Jul 30 04:58:51 PM PDT 24
Peak memory 200488 kb
Host smart-d03b5359-0fa9-45b3-bff9-8b2ee2638510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633860577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2633860577
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3952981444
Short name T10
Test name
Test status
Simulation time 170832612 ps
CPU time 1.2 seconds
Started Jul 30 04:58:47 PM PDT 24
Finished Jul 30 04:58:48 PM PDT 24
Peak memory 200280 kb
Host smart-c9a9dc27-6aed-4831-86aa-ad7f4fa9f681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952981444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3952981444
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4258663659
Short name T473
Test name
Test status
Simulation time 250410604 ps
CPU time 1.68 seconds
Started Jul 30 04:58:54 PM PDT 24
Finished Jul 30 04:58:56 PM PDT 24
Peak memory 200284 kb
Host smart-cb214d28-d81d-4f7a-8a1a-63fd7fa82e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258663659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4258663659
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2820101515
Short name T154
Test name
Test status
Simulation time 1936219904 ps
CPU time 9.32 seconds
Started Jul 30 04:58:51 PM PDT 24
Finished Jul 30 04:59:00 PM PDT 24
Peak memory 200400 kb
Host smart-a95369ff-9ed3-47b7-a41d-2d0517a4ffc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820101515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2820101515
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2541724186
Short name T309
Test name
Test status
Simulation time 111913903 ps
CPU time 1.43 seconds
Started Jul 30 04:58:48 PM PDT 24
Finished Jul 30 04:58:50 PM PDT 24
Peak memory 200204 kb
Host smart-7fb453c0-9087-44c3-868b-4891770769e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541724186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2541724186
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3420645779
Short name T333
Test name
Test status
Simulation time 294664774 ps
CPU time 1.74 seconds
Started Jul 30 04:58:45 PM PDT 24
Finished Jul 30 04:58:46 PM PDT 24
Peak memory 200400 kb
Host smart-efc29729-1986-47db-9e14-57488e46391b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420645779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3420645779
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.4221927545
Short name T163
Test name
Test status
Simulation time 57857742 ps
CPU time 0.72 seconds
Started Jul 30 04:58:49 PM PDT 24
Finished Jul 30 04:58:50 PM PDT 24
Peak memory 200080 kb
Host smart-e259179c-919e-44bb-9438-f5e04fcedeb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221927545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.4221927545
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2922592473
Short name T236
Test name
Test status
Simulation time 2368758430 ps
CPU time 9.57 seconds
Started Jul 30 04:58:50 PM PDT 24
Finished Jul 30 04:59:00 PM PDT 24
Peak memory 217668 kb
Host smart-8fd103ec-c351-4755-a00b-b318751da61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922592473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2922592473
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1573310604
Short name T382
Test name
Test status
Simulation time 245815043 ps
CPU time 1.05 seconds
Started Jul 30 04:58:51 PM PDT 24
Finished Jul 30 04:58:52 PM PDT 24
Peak memory 217504 kb
Host smart-e940d31c-5e75-4559-bf5a-ee1b0c7c8614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573310604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1573310604
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2957473765
Short name T159
Test name
Test status
Simulation time 149439118 ps
CPU time 0.92 seconds
Started Jul 30 04:58:58 PM PDT 24
Finished Jul 30 04:58:59 PM PDT 24
Peak memory 199952 kb
Host smart-45f34287-9c34-4fd7-8ff0-366e4d48f2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957473765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2957473765
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.894297323
Short name T124
Test name
Test status
Simulation time 834289781 ps
CPU time 3.95 seconds
Started Jul 30 04:58:50 PM PDT 24
Finished Jul 30 04:58:54 PM PDT 24
Peak memory 200476 kb
Host smart-1629426f-b786-4608-9002-6239152cd8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894297323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.894297323
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.371716556
Short name T186
Test name
Test status
Simulation time 187791862 ps
CPU time 1.18 seconds
Started Jul 30 04:58:48 PM PDT 24
Finished Jul 30 04:58:50 PM PDT 24
Peak memory 200256 kb
Host smart-5aa90220-cd10-4649-8ff0-ef23d357b505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371716556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.371716556
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1687488768
Short name T201
Test name
Test status
Simulation time 192285420 ps
CPU time 1.43 seconds
Started Jul 30 04:58:58 PM PDT 24
Finished Jul 30 04:58:59 PM PDT 24
Peak memory 200324 kb
Host smart-a81c8938-7b2e-452e-be21-8cd512298741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687488768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1687488768
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.4088535362
Short name T502
Test name
Test status
Simulation time 1934124774 ps
CPU time 8.79 seconds
Started Jul 30 04:58:50 PM PDT 24
Finished Jul 30 04:58:58 PM PDT 24
Peak memory 208712 kb
Host smart-bcf9b289-545f-4a3f-81d4-d51b29114e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088535362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4088535362
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1145846356
Short name T190
Test name
Test status
Simulation time 148153440 ps
CPU time 1.89 seconds
Started Jul 30 04:58:49 PM PDT 24
Finished Jul 30 04:58:51 PM PDT 24
Peak memory 200248 kb
Host smart-acc5f903-593e-46ce-b87c-62d508e88ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145846356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1145846356
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2172833178
Short name T122
Test name
Test status
Simulation time 194492500 ps
CPU time 1.28 seconds
Started Jul 30 04:58:54 PM PDT 24
Finished Jul 30 04:58:56 PM PDT 24
Peak memory 200088 kb
Host smart-248a1597-46ef-42c5-8fd4-8b69dc05a32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172833178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2172833178
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.220840054
Short name T180
Test name
Test status
Simulation time 69164968 ps
CPU time 0.81 seconds
Started Jul 30 04:58:55 PM PDT 24
Finished Jul 30 04:58:56 PM PDT 24
Peak memory 200044 kb
Host smart-88069b00-321e-4ee7-9f15-2e8c8808939d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220840054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.220840054
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.4181356468
Short name T350
Test name
Test status
Simulation time 1234156393 ps
CPU time 5.65 seconds
Started Jul 30 04:58:51 PM PDT 24
Finished Jul 30 04:58:57 PM PDT 24
Peak memory 216724 kb
Host smart-504cff69-dccf-4595-87db-7721ea04010d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181356468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4181356468
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3477735691
Short name T492
Test name
Test status
Simulation time 243832206 ps
CPU time 1.17 seconds
Started Jul 30 04:58:57 PM PDT 24
Finished Jul 30 04:58:58 PM PDT 24
Peak memory 217308 kb
Host smart-ad59de3f-c149-4c81-9a68-de660ce6a258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477735691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3477735691
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3376125391
Short name T14
Test name
Test status
Simulation time 97781564 ps
CPU time 0.77 seconds
Started Jul 30 04:58:52 PM PDT 24
Finished Jul 30 04:58:53 PM PDT 24
Peak memory 200024 kb
Host smart-d84c8222-bb35-4aa4-a177-38408cd71ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376125391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3376125391
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1351340755
Short name T75
Test name
Test status
Simulation time 819364178 ps
CPU time 3.78 seconds
Started Jul 30 04:58:58 PM PDT 24
Finished Jul 30 04:59:02 PM PDT 24
Peak memory 200392 kb
Host smart-9923ed56-be29-45b4-9cb5-ebdb69356e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351340755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1351340755
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2775301510
Short name T250
Test name
Test status
Simulation time 151496804 ps
CPU time 1.08 seconds
Started Jul 30 04:58:51 PM PDT 24
Finished Jul 30 04:58:53 PM PDT 24
Peak memory 200268 kb
Host smart-fcd0332f-0a8b-43db-820f-bd3ee75e1651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775301510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2775301510
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1069770275
Short name T135
Test name
Test status
Simulation time 197110590 ps
CPU time 1.47 seconds
Started Jul 30 04:58:48 PM PDT 24
Finished Jul 30 04:58:50 PM PDT 24
Peak memory 200484 kb
Host smart-08c9db61-9559-43ed-9ac0-a4b8406bc593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069770275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1069770275
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1820414728
Short name T298
Test name
Test status
Simulation time 17622664303 ps
CPU time 61.73 seconds
Started Jul 30 04:58:55 PM PDT 24
Finished Jul 30 04:59:57 PM PDT 24
Peak memory 208800 kb
Host smart-42065f74-ac1f-4743-b2b8-84446d826666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820414728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1820414728
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.393630352
Short name T239
Test name
Test status
Simulation time 475956746 ps
CPU time 2.69 seconds
Started Jul 30 04:58:49 PM PDT 24
Finished Jul 30 04:58:52 PM PDT 24
Peak memory 200112 kb
Host smart-d3cca0a2-63ae-48f3-aa30-fa3968549998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393630352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.393630352
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3555638835
Short name T278
Test name
Test status
Simulation time 138319648 ps
CPU time 1.08 seconds
Started Jul 30 04:58:51 PM PDT 24
Finished Jul 30 04:58:52 PM PDT 24
Peak memory 200280 kb
Host smart-a8aef710-100c-4e80-9485-75d53caa3886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555638835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3555638835
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3960273116
Short name T452
Test name
Test status
Simulation time 68526559 ps
CPU time 0.79 seconds
Started Jul 30 04:58:55 PM PDT 24
Finished Jul 30 04:58:56 PM PDT 24
Peak memory 200092 kb
Host smart-1756a7d9-a404-4da3-b3ee-106818384774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960273116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3960273116
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3009847994
Short name T280
Test name
Test status
Simulation time 1884920165 ps
CPU time 7.72 seconds
Started Jul 30 04:58:54 PM PDT 24
Finished Jul 30 04:59:02 PM PDT 24
Peak memory 217660 kb
Host smart-0eea88df-e31d-4ebe-8d23-a86920d189e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009847994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3009847994
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2371545131
Short name T370
Test name
Test status
Simulation time 244120057 ps
CPU time 1.11 seconds
Started Jul 30 04:58:55 PM PDT 24
Finished Jul 30 04:58:56 PM PDT 24
Peak memory 217384 kb
Host smart-d0ca9048-d4a3-4573-ba61-d99beb43fc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371545131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2371545131
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3914620046
Short name T167
Test name
Test status
Simulation time 219941039 ps
CPU time 0.95 seconds
Started Jul 30 04:58:55 PM PDT 24
Finished Jul 30 04:58:56 PM PDT 24
Peak memory 200092 kb
Host smart-598705d8-f122-4151-ba36-20024ae505d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914620046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3914620046
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4156881503
Short name T196
Test name
Test status
Simulation time 848779083 ps
CPU time 4.43 seconds
Started Jul 30 04:58:56 PM PDT 24
Finished Jul 30 04:59:00 PM PDT 24
Peak memory 200432 kb
Host smart-d4f74357-64f7-4811-b241-0ea36e3e3cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156881503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4156881503
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3093979585
Short name T326
Test name
Test status
Simulation time 106905070 ps
CPU time 1.04 seconds
Started Jul 30 04:58:55 PM PDT 24
Finished Jul 30 04:58:56 PM PDT 24
Peak memory 200268 kb
Host smart-5f723c16-2f07-4e39-885f-5d0dac97a42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093979585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3093979585
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.980924668
Short name T129
Test name
Test status
Simulation time 196111308 ps
CPU time 1.39 seconds
Started Jul 30 04:58:55 PM PDT 24
Finished Jul 30 04:58:57 PM PDT 24
Peak memory 200276 kb
Host smart-a8fac3fd-49e2-46ef-928a-7f06da48bef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980924668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.980924668
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2516579843
Short name T9
Test name
Test status
Simulation time 7583846217 ps
CPU time 25.79 seconds
Started Jul 30 04:59:02 PM PDT 24
Finished Jul 30 04:59:27 PM PDT 24
Peak memory 208732 kb
Host smart-a7ff6ce0-848f-44d3-9016-708fc14daa2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516579843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2516579843
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1773310509
Short name T318
Test name
Test status
Simulation time 156234178 ps
CPU time 1.97 seconds
Started Jul 30 04:58:54 PM PDT 24
Finished Jul 30 04:58:56 PM PDT 24
Peak memory 200248 kb
Host smart-741edd5d-fac3-41ab-86ee-28a90c7882dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773310509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1773310509
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3307982143
Short name T477
Test name
Test status
Simulation time 110324054 ps
CPU time 0.96 seconds
Started Jul 30 04:59:00 PM PDT 24
Finished Jul 30 04:59:01 PM PDT 24
Peak memory 200216 kb
Host smart-181d3e03-84e3-4ccf-82de-31b37ef17221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307982143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3307982143
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2645183468
Short name T253
Test name
Test status
Simulation time 103571568 ps
CPU time 0.88 seconds
Started Jul 30 04:58:58 PM PDT 24
Finished Jul 30 04:58:59 PM PDT 24
Peak memory 200076 kb
Host smart-bcb3e4d6-0d22-4e49-a547-7967e59b5872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645183468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2645183468
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3460052084
Short name T470
Test name
Test status
Simulation time 2363348265 ps
CPU time 8.24 seconds
Started Jul 30 04:58:56 PM PDT 24
Finished Jul 30 04:59:04 PM PDT 24
Peak memory 221676 kb
Host smart-e3b28506-cf55-486d-921c-895f531f3c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460052084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3460052084
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1425825199
Short name T420
Test name
Test status
Simulation time 243281323 ps
CPU time 1.21 seconds
Started Jul 30 04:59:02 PM PDT 24
Finished Jul 30 04:59:03 PM PDT 24
Peak memory 217484 kb
Host smart-1f0a5c63-8705-4acd-b82f-96ae7a646564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425825199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1425825199
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3711407085
Short name T217
Test name
Test status
Simulation time 186322256 ps
CPU time 0.89 seconds
Started Jul 30 04:58:56 PM PDT 24
Finished Jul 30 04:58:57 PM PDT 24
Peak memory 200024 kb
Host smart-07b0cdfe-c8d5-480b-be46-b143f2729db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711407085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3711407085
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3977416150
Short name T431
Test name
Test status
Simulation time 1589550323 ps
CPU time 7.15 seconds
Started Jul 30 04:58:54 PM PDT 24
Finished Jul 30 04:59:01 PM PDT 24
Peak memory 200452 kb
Host smart-8c2087d5-388e-4bca-b898-fd85743e3e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977416150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3977416150
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1282187963
Short name T8
Test name
Test status
Simulation time 102906132 ps
CPU time 1.08 seconds
Started Jul 30 04:58:56 PM PDT 24
Finished Jul 30 04:58:57 PM PDT 24
Peak memory 200256 kb
Host smart-53ef83d7-c4df-40ff-8cdf-9567bb8eb408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282187963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1282187963
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3128171327
Short name T101
Test name
Test status
Simulation time 118743569 ps
CPU time 1.24 seconds
Started Jul 30 04:58:54 PM PDT 24
Finished Jul 30 04:58:55 PM PDT 24
Peak memory 200384 kb
Host smart-7fae16ea-e1cb-453a-9fa6-dc2a68ab252e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128171327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3128171327
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1244957369
Short name T288
Test name
Test status
Simulation time 6141503952 ps
CPU time 25.61 seconds
Started Jul 30 04:58:58 PM PDT 24
Finished Jul 30 04:59:23 PM PDT 24
Peak memory 208552 kb
Host smart-5339da78-8f1e-4f77-8fd9-aeb48c8a2ef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244957369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1244957369
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1356656543
Short name T107
Test name
Test status
Simulation time 349489351 ps
CPU time 1.95 seconds
Started Jul 30 04:58:55 PM PDT 24
Finished Jul 30 04:58:57 PM PDT 24
Peak memory 200116 kb
Host smart-e51d822e-87a4-4778-b544-fd0cc8dd288e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356656543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1356656543
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3649084047
Short name T347
Test name
Test status
Simulation time 153240158 ps
CPU time 1.34 seconds
Started Jul 30 04:59:02 PM PDT 24
Finished Jul 30 04:59:03 PM PDT 24
Peak memory 200392 kb
Host smart-cf3edb27-33e0-4a3c-8931-79123e5d417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649084047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3649084047
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3694219473
Short name T384
Test name
Test status
Simulation time 81075581 ps
CPU time 0.88 seconds
Started Jul 30 04:56:19 PM PDT 24
Finished Jul 30 04:56:20 PM PDT 24
Peak memory 199976 kb
Host smart-9234cba3-b241-4a48-a939-3970f2968e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694219473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3694219473
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3411511054
Short name T34
Test name
Test status
Simulation time 1890786397 ps
CPU time 7.67 seconds
Started Jul 30 04:56:21 PM PDT 24
Finished Jul 30 04:56:29 PM PDT 24
Peak memory 221640 kb
Host smart-19ffbc06-23fb-4d91-a980-ae7009db4f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411511054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3411511054
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1373548721
Short name T181
Test name
Test status
Simulation time 243608785 ps
CPU time 1.12 seconds
Started Jul 30 04:56:19 PM PDT 24
Finished Jul 30 04:56:20 PM PDT 24
Peak memory 217356 kb
Host smart-db1844d0-d56f-4e62-9d75-27fde07297f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373548721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1373548721
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2327547042
Short name T455
Test name
Test status
Simulation time 231567670 ps
CPU time 1.01 seconds
Started Jul 30 04:56:15 PM PDT 24
Finished Jul 30 04:56:16 PM PDT 24
Peak memory 200036 kb
Host smart-01ffb6bb-0f80-46ad-9ee2-97a1a2217d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327547042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2327547042
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2759248319
Short name T424
Test name
Test status
Simulation time 793796163 ps
CPU time 4.44 seconds
Started Jul 30 04:56:16 PM PDT 24
Finished Jul 30 04:56:21 PM PDT 24
Peak memory 200436 kb
Host smart-95b0c040-1718-46b4-9ba6-98b4694d7386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759248319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2759248319
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2309023680
Short name T116
Test name
Test status
Simulation time 139284475 ps
CPU time 1.07 seconds
Started Jul 30 04:56:17 PM PDT 24
Finished Jul 30 04:56:19 PM PDT 24
Peak memory 200288 kb
Host smart-85e99a35-ab5e-4fad-b580-9fecb161c0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309023680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2309023680
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.395154695
Short name T520
Test name
Test status
Simulation time 195195329 ps
CPU time 1.35 seconds
Started Jul 30 04:56:16 PM PDT 24
Finished Jul 30 04:56:17 PM PDT 24
Peak memory 200412 kb
Host smart-d1ed98ff-74c0-416b-b2af-16a703dc0350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395154695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.395154695
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.578787256
Short name T80
Test name
Test status
Simulation time 4439268166 ps
CPU time 19.25 seconds
Started Jul 30 04:56:20 PM PDT 24
Finished Jul 30 04:56:40 PM PDT 24
Peak memory 200512 kb
Host smart-1d4e7ba6-c588-4709-bde8-94fab4ebad0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578787256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.578787256
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.608494979
Short name T296
Test name
Test status
Simulation time 550244618 ps
CPU time 2.91 seconds
Started Jul 30 04:56:15 PM PDT 24
Finished Jul 30 04:56:18 PM PDT 24
Peak memory 200160 kb
Host smart-c5492b5d-8ca2-41da-ab77-9d3795614da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608494979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.608494979
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1991821820
Short name T207
Test name
Test status
Simulation time 85873781 ps
CPU time 0.84 seconds
Started Jul 30 04:56:18 PM PDT 24
Finished Jul 30 04:56:19 PM PDT 24
Peak memory 200284 kb
Host smart-5ed4c8de-1e0f-48fe-8f4e-46bab4a5cbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991821820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1991821820
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1443831868
Short name T123
Test name
Test status
Simulation time 73111156 ps
CPU time 0.8 seconds
Started Jul 30 04:56:23 PM PDT 24
Finished Jul 30 04:56:24 PM PDT 24
Peak memory 200084 kb
Host smart-316e95c5-c5c1-4ea6-84d1-81817821df25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443831868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1443831868
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2099307526
Short name T361
Test name
Test status
Simulation time 1229963176 ps
CPU time 5.82 seconds
Started Jul 30 04:56:24 PM PDT 24
Finished Jul 30 04:56:29 PM PDT 24
Peak memory 221492 kb
Host smart-3b020fc8-8f9c-4d67-8911-8adba0075a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099307526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2099307526
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3931887079
Short name T434
Test name
Test status
Simulation time 243953935 ps
CPU time 1.1 seconds
Started Jul 30 04:56:24 PM PDT 24
Finished Jul 30 04:56:25 PM PDT 24
Peak memory 217364 kb
Host smart-c9aeab88-bb76-4eac-a832-08ad91b0abb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931887079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3931887079
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3449986940
Short name T395
Test name
Test status
Simulation time 92023216 ps
CPU time 0.75 seconds
Started Jul 30 04:56:18 PM PDT 24
Finished Jul 30 04:56:19 PM PDT 24
Peak memory 199984 kb
Host smart-2564565f-6fea-42b3-94a3-9a694905f21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449986940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3449986940
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2297210333
Short name T303
Test name
Test status
Simulation time 1398243189 ps
CPU time 5.51 seconds
Started Jul 30 04:56:19 PM PDT 24
Finished Jul 30 04:56:25 PM PDT 24
Peak memory 200384 kb
Host smart-aa27d7dc-398b-4a23-bc0d-9b611c0d6fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297210333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2297210333
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3853784081
Short name T113
Test name
Test status
Simulation time 110912395 ps
CPU time 1.05 seconds
Started Jul 30 04:56:23 PM PDT 24
Finished Jul 30 04:56:25 PM PDT 24
Peak memory 200256 kb
Host smart-68ed12be-d8a8-4310-87c9-fe2eaddd7547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853784081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3853784081
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2001624883
Short name T141
Test name
Test status
Simulation time 190247647 ps
CPU time 1.34 seconds
Started Jul 30 04:56:18 PM PDT 24
Finished Jul 30 04:56:20 PM PDT 24
Peak memory 200312 kb
Host smart-5a231eae-bcd5-4f5b-b841-6883e929c5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001624883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2001624883
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.614768700
Short name T494
Test name
Test status
Simulation time 6467079182 ps
CPU time 27.67 seconds
Started Jul 30 04:56:23 PM PDT 24
Finished Jul 30 04:56:51 PM PDT 24
Peak memory 208708 kb
Host smart-75dab5fa-7a10-4c77-a720-b5bae9ae7441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614768700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.614768700
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1914075375
Short name T264
Test name
Test status
Simulation time 430402342 ps
CPU time 2.65 seconds
Started Jul 30 04:56:20 PM PDT 24
Finished Jul 30 04:56:23 PM PDT 24
Peak memory 200076 kb
Host smart-29f53221-6cb2-4387-99e9-d9a6c71f5975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914075375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1914075375
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2461501917
Short name T425
Test name
Test status
Simulation time 101748419 ps
CPU time 0.9 seconds
Started Jul 30 04:56:20 PM PDT 24
Finished Jul 30 04:56:21 PM PDT 24
Peak memory 200196 kb
Host smart-822110ba-8a05-486e-ab75-75ef3b7a0a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461501917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2461501917
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.4177173577
Short name T216
Test name
Test status
Simulation time 76411382 ps
CPU time 0.82 seconds
Started Jul 30 04:56:34 PM PDT 24
Finished Jul 30 04:56:35 PM PDT 24
Peak memory 199948 kb
Host smart-5d9fdb47-4caa-474b-87f4-fba9d31d106d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177173577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.4177173577
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2742882276
Short name T486
Test name
Test status
Simulation time 1219367963 ps
CPU time 5.61 seconds
Started Jul 30 04:56:34 PM PDT 24
Finished Jul 30 04:56:39 PM PDT 24
Peak memory 217652 kb
Host smart-523dc661-620c-4fdb-9fa5-d8b3aaefebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742882276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2742882276
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1842481678
Short name T345
Test name
Test status
Simulation time 243825629 ps
CPU time 1.09 seconds
Started Jul 30 04:56:30 PM PDT 24
Finished Jul 30 04:56:32 PM PDT 24
Peak memory 217340 kb
Host smart-e61da5a4-37f9-4919-8499-65f272ce5a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842481678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1842481678
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1828415984
Short name T176
Test name
Test status
Simulation time 113983352 ps
CPU time 0.81 seconds
Started Jul 30 04:56:29 PM PDT 24
Finished Jul 30 04:56:30 PM PDT 24
Peak memory 200068 kb
Host smart-c8d81597-582c-4d29-a1d9-343b49604675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828415984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1828415984
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1287816106
Short name T64
Test name
Test status
Simulation time 767536627 ps
CPU time 4.06 seconds
Started Jul 30 04:56:29 PM PDT 24
Finished Jul 30 04:56:34 PM PDT 24
Peak memory 200488 kb
Host smart-1fbca237-d754-463e-9b11-59104a7c0e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287816106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1287816106
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2639973573
Short name T114
Test name
Test status
Simulation time 92373151 ps
CPU time 1.05 seconds
Started Jul 30 04:56:27 PM PDT 24
Finished Jul 30 04:56:28 PM PDT 24
Peak memory 200208 kb
Host smart-527780c1-57ff-4886-8138-f1a638fce2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639973573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2639973573
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4183052995
Short name T467
Test name
Test status
Simulation time 126774769 ps
CPU time 1.26 seconds
Started Jul 30 04:56:29 PM PDT 24
Finished Jul 30 04:56:30 PM PDT 24
Peak memory 200340 kb
Host smart-defd933a-db83-4a2a-afed-6c19a30c1f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183052995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4183052995
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3106333711
Short name T447
Test name
Test status
Simulation time 12525681745 ps
CPU time 48.43 seconds
Started Jul 30 04:56:33 PM PDT 24
Finished Jul 30 04:57:21 PM PDT 24
Peak memory 208780 kb
Host smart-db783818-b06d-4808-847e-5a6cc6475aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106333711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3106333711
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2160495760
Short name T290
Test name
Test status
Simulation time 460068335 ps
CPU time 2.95 seconds
Started Jul 30 04:56:27 PM PDT 24
Finished Jul 30 04:56:31 PM PDT 24
Peak memory 200060 kb
Host smart-bd8912ed-791c-498a-94ef-f351e641053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160495760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2160495760
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1334212216
Short name T118
Test name
Test status
Simulation time 110664649 ps
CPU time 0.96 seconds
Started Jul 30 04:56:29 PM PDT 24
Finished Jul 30 04:56:30 PM PDT 24
Peak memory 200184 kb
Host smart-279c19cf-27c6-412a-bf4a-d98d3428af6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334212216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1334212216
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3040234124
Short name T448
Test name
Test status
Simulation time 78647283 ps
CPU time 0.81 seconds
Started Jul 30 04:56:40 PM PDT 24
Finished Jul 30 04:56:40 PM PDT 24
Peak memory 199988 kb
Host smart-98765af5-f945-413b-9388-46b2bb445da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040234124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3040234124
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.49426962
Short name T33
Test name
Test status
Simulation time 1224716387 ps
CPU time 5.52 seconds
Started Jul 30 04:56:39 PM PDT 24
Finished Jul 30 04:56:45 PM PDT 24
Peak memory 217612 kb
Host smart-bdc9a11f-f9a2-4a23-8bd6-6816bce62d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49426962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.49426962
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2767421816
Short name T146
Test name
Test status
Simulation time 243699626 ps
CPU time 1.08 seconds
Started Jul 30 04:56:39 PM PDT 24
Finished Jul 30 04:56:40 PM PDT 24
Peak memory 217388 kb
Host smart-7bf55aff-6300-42db-9c1b-42b026700f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767421816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2767421816
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.502188974
Short name T433
Test name
Test status
Simulation time 199198369 ps
CPU time 0.88 seconds
Started Jul 30 04:56:31 PM PDT 24
Finished Jul 30 04:56:32 PM PDT 24
Peak memory 199924 kb
Host smart-c1875988-e7c6-446b-9141-877190a87d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502188974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.502188974
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2095808029
Short name T416
Test name
Test status
Simulation time 727410241 ps
CPU time 3.84 seconds
Started Jul 30 04:56:34 PM PDT 24
Finished Jul 30 04:56:38 PM PDT 24
Peak memory 200372 kb
Host smart-d1cc6b76-837c-49ad-9925-06c40d3c68dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095808029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2095808029
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2715060006
Short name T500
Test name
Test status
Simulation time 180990724 ps
CPU time 1.16 seconds
Started Jul 30 04:56:36 PM PDT 24
Finished Jul 30 04:56:37 PM PDT 24
Peak memory 200208 kb
Host smart-24d4818c-058f-453f-9098-ed9e8e3c85ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715060006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2715060006
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.27711517
Short name T323
Test name
Test status
Simulation time 122747080 ps
CPU time 1.22 seconds
Started Jul 30 04:56:34 PM PDT 24
Finished Jul 30 04:56:35 PM PDT 24
Peak memory 200308 kb
Host smart-95a9da65-130f-45e4-80e1-5133d1bfda80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27711517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.27711517
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2880698451
Short name T369
Test name
Test status
Simulation time 10572941254 ps
CPU time 38.71 seconds
Started Jul 30 04:56:39 PM PDT 24
Finished Jul 30 04:57:18 PM PDT 24
Peak memory 216816 kb
Host smart-4514b4f6-b56d-456d-90f4-f50a555e888f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880698451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2880698451
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3735480763
Short name T7
Test name
Test status
Simulation time 256650082 ps
CPU time 1.95 seconds
Started Jul 30 04:56:37 PM PDT 24
Finished Jul 30 04:56:39 PM PDT 24
Peak memory 200120 kb
Host smart-572fb0c7-7b03-48e3-8aa8-80285b27bd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735480763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3735480763
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2727565195
Short name T462
Test name
Test status
Simulation time 113321568 ps
CPU time 1.04 seconds
Started Jul 30 04:56:37 PM PDT 24
Finished Jul 30 04:56:38 PM PDT 24
Peak memory 200228 kb
Host smart-0cb6f674-4883-4a0e-90af-eae77516ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727565195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2727565195
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3718238796
Short name T419
Test name
Test status
Simulation time 63909147 ps
CPU time 0.74 seconds
Started Jul 30 04:56:42 PM PDT 24
Finished Jul 30 04:56:43 PM PDT 24
Peak memory 200032 kb
Host smart-9f25c404-1d97-4e3b-9e4e-e15a377ecd5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718238796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3718238796
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.215947183
Short name T522
Test name
Test status
Simulation time 1226991945 ps
CPU time 5.65 seconds
Started Jul 30 04:56:44 PM PDT 24
Finished Jul 30 04:56:50 PM PDT 24
Peak memory 217292 kb
Host smart-59d0ee5c-50c0-43e8-915f-376b6cfba10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215947183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.215947183
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.4116917240
Short name T205
Test name
Test status
Simulation time 244069199 ps
CPU time 1.18 seconds
Started Jul 30 04:56:44 PM PDT 24
Finished Jul 30 04:56:46 PM PDT 24
Peak memory 217436 kb
Host smart-325d0012-faed-4d9a-88f5-6a5227ed20e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116917240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.4116917240
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1462620469
Short name T371
Test name
Test status
Simulation time 227274582 ps
CPU time 0.95 seconds
Started Jul 30 04:56:41 PM PDT 24
Finished Jul 30 04:56:42 PM PDT 24
Peak memory 200000 kb
Host smart-fa07cfb2-4ca9-4b51-a0e8-758940d3179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462620469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1462620469
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3896315854
Short name T1
Test name
Test status
Simulation time 1745094268 ps
CPU time 7.39 seconds
Started Jul 30 04:56:39 PM PDT 24
Finished Jul 30 04:56:46 PM PDT 24
Peak memory 200524 kb
Host smart-7a7df7da-132b-4f78-a8f0-80d5ae31ddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896315854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3896315854
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2470943905
Short name T325
Test name
Test status
Simulation time 150155605 ps
CPU time 1.14 seconds
Started Jul 30 04:56:43 PM PDT 24
Finished Jul 30 04:56:44 PM PDT 24
Peak memory 200108 kb
Host smart-40a3eb70-2a92-4336-b94a-c3d4f98590bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470943905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2470943905
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.177779110
Short name T300
Test name
Test status
Simulation time 186617914 ps
CPU time 1.44 seconds
Started Jul 30 04:56:40 PM PDT 24
Finished Jul 30 04:56:42 PM PDT 24
Peak memory 200484 kb
Host smart-0590d31d-8f9a-45b8-861c-769f029faf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177779110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.177779110
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3950071976
Short name T240
Test name
Test status
Simulation time 1743468466 ps
CPU time 7.5 seconds
Started Jul 30 04:56:47 PM PDT 24
Finished Jul 30 04:56:55 PM PDT 24
Peak memory 200520 kb
Host smart-e7e54592-b2db-407c-b097-39a6458b90d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950071976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3950071976
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1874954316
Short name T495
Test name
Test status
Simulation time 519078102 ps
CPU time 2.65 seconds
Started Jul 30 04:56:40 PM PDT 24
Finished Jul 30 04:56:43 PM PDT 24
Peak memory 200464 kb
Host smart-d644be87-1184-42f4-b833-2f06b10443fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874954316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1874954316
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2670041521
Short name T512
Test name
Test status
Simulation time 91238337 ps
CPU time 0.95 seconds
Started Jul 30 04:56:41 PM PDT 24
Finished Jul 30 04:56:42 PM PDT 24
Peak memory 200300 kb
Host smart-e4058c09-4a40-4f57-8709-5f187e296a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670041521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2670041521
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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