Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7701

1

T9

75

T10

20

T11

15

auto[1]

10924

1

T1

4

T6

4

T7

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5833	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6274	1			T1	2		T2	1		T3	1
reset_info_cp[2]	2900	1			T1	1		T6	1		T7	1
reset_info_cp[4]	3715	1			T1	1		T6	1		T7	1
reset_info_cp[8]	101	1			T10	1		T46	1		T99	1
reset_info_cp[16]	119	1			T1	1		T9	1		T10	1
reset_info_cp[32]	108	1			T9	1		T10	1		T23	1
reset_info_cp[64]	80	1			T9	1		T10	1		T46	1
reset_info_cp[128]	115	1			T9	3		T46	7		T23	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2997	1			T9	28		T10	20		T21	8
reset_info_cp[1]	auto[1]	2657	1			T1	1		T6	1		T7	1
reset_info_cp[2]	auto[0]	814	1			T9	11		T21	7		T45	7
reset_info_cp[2]	auto[1]	2086	1			T1	1		T6	1		T7	1
reset_info_cp[4]	auto[0]	1298	1			T9	13		T21	4		T45	4
reset_info_cp[4]	auto[1]	2417	1			T1	1		T6	1		T7	1
reset_info_cp[8]	auto[0]	39	1			T46	1		T99	1		T36	1
reset_info_cp[8]	auto[1]	62	1			T10	1		T86	1		T87	1
reset_info_cp[16]	auto[0]	48	1			T22	1		T46	3		T86	2
reset_info_cp[16]	auto[1]	71	1			T1	1		T9	1		T10	1
reset_info_cp[32]	auto[0]	42	1			T86	1		T87	3		T137	1
reset_info_cp[32]	auto[1]	66	1			T9	1		T10	1		T23	1
reset_info_cp[64]	auto[0]	28	1			T86	2		T87	1		T102	1
reset_info_cp[64]	auto[1]	52	1			T9	1		T10	1		T46	1
reset_info_cp[128]	auto[0]	61	1			T9	2		T46	5		T36	1
reset_info_cp[128]	auto[1]	54	1			T9	1		T46	2		T23	1