Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T540 /workspace/coverage/default/8.rstmgr_smoke.2137321203 Jul 31 05:19:52 PM PDT 24 Jul 31 05:19:54 PM PDT 24 202790110 ps
T541 /workspace/coverage/default/13.rstmgr_sw_rst.3437516325 Jul 31 05:19:56 PM PDT 24 Jul 31 05:19:58 PM PDT 24 126368562 ps
T542 /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1879686444 Jul 31 05:19:52 PM PDT 24 Jul 31 05:19:57 PM PDT 24 1231958803 ps
T543 /workspace/coverage/default/8.rstmgr_stress_all.2154915937 Jul 31 05:19:51 PM PDT 24 Jul 31 05:20:09 PM PDT 24 4072358730 ps
T544 /workspace/coverage/default/21.rstmgr_smoke.997163198 Jul 31 05:19:55 PM PDT 24 Jul 31 05:19:57 PM PDT 24 113368370 ps
T58 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.898963266 Jul 31 05:01:35 PM PDT 24 Jul 31 05:01:37 PM PDT 24 56655234 ps
T59 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3464099520 Jul 31 05:00:45 PM PDT 24 Jul 31 05:00:48 PM PDT 24 272899045 ps
T60 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2681440141 Jul 31 05:01:04 PM PDT 24 Jul 31 05:01:05 PM PDT 24 169958382 ps
T61 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4131402007 Jul 31 05:00:55 PM PDT 24 Jul 31 05:00:57 PM PDT 24 421038884 ps
T545 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.586724756 Jul 31 05:01:35 PM PDT 24 Jul 31 05:01:42 PM PDT 24 83440267 ps
T108 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3262883033 Jul 31 05:01:01 PM PDT 24 Jul 31 05:01:03 PM PDT 24 81813617 ps
T109 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.918722688 Jul 31 05:01:09 PM PDT 24 Jul 31 05:01:10 PM PDT 24 68066452 ps
T110 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2379492036 Jul 31 05:00:56 PM PDT 24 Jul 31 05:00:58 PM PDT 24 149359308 ps
T116 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.251699615 Jul 31 05:00:39 PM PDT 24 Jul 31 05:00:40 PM PDT 24 131195444 ps
T64 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.662285249 Jul 31 05:01:08 PM PDT 24 Jul 31 05:01:09 PM PDT 24 178872454 ps
T111 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.425819866 Jul 31 05:01:01 PM PDT 24 Jul 31 05:01:02 PM PDT 24 105457403 ps
T65 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2572454787 Jul 31 05:00:36 PM PDT 24 Jul 31 05:00:37 PM PDT 24 201662093 ps
T66 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.923750339 Jul 31 05:00:41 PM PDT 24 Jul 31 05:00:43 PM PDT 24 230314732 ps
T67 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3637098794 Jul 31 05:00:53 PM PDT 24 Jul 31 05:00:56 PM PDT 24 322745421 ps
T112 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1255228389 Jul 31 05:01:08 PM PDT 24 Jul 31 05:01:10 PM PDT 24 63357425 ps
T113 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3886762092 Jul 31 05:01:11 PM PDT 24 Jul 31 05:01:13 PM PDT 24 231692372 ps
T136 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1899227035 Jul 31 05:00:48 PM PDT 24 Jul 31 05:00:51 PM PDT 24 410284942 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3773847290 Jul 31 05:00:48 PM PDT 24 Jul 31 05:00:49 PM PDT 24 144409854 ps
T547 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3011561173 Jul 31 05:01:01 PM PDT 24 Jul 31 05:01:02 PM PDT 24 89784231 ps
T90 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4245238395 Jul 31 05:01:03 PM PDT 24 Jul 31 05:01:04 PM PDT 24 127320289 ps
T114 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2861562485 Jul 31 05:01:35 PM PDT 24 Jul 31 05:01:42 PM PDT 24 159942860 ps
T115 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2805989998 Jul 31 05:01:14 PM PDT 24 Jul 31 05:01:15 PM PDT 24 90151577 ps
T91 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3740552122 Jul 31 05:00:57 PM PDT 24 Jul 31 05:00:59 PM PDT 24 189443603 ps
T548 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2763800103 Jul 31 05:01:58 PM PDT 24 Jul 31 05:02:00 PM PDT 24 183994297 ps
T92 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1395734692 Jul 31 05:00:47 PM PDT 24 Jul 31 05:00:50 PM PDT 24 899461893 ps
T93 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.991562509 Jul 31 05:01:08 PM PDT 24 Jul 31 05:01:11 PM PDT 24 472203130 ps
T549 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.904522127 Jul 31 05:00:59 PM PDT 24 Jul 31 05:01:00 PM PDT 24 69023044 ps
T550 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.395805758 Jul 31 05:00:43 PM PDT 24 Jul 31 05:00:44 PM PDT 24 132702413 ps
T551 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3570376872 Jul 31 05:00:48 PM PDT 24 Jul 31 05:00:49 PM PDT 24 263079077 ps
T552 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2830886505 Jul 31 05:00:40 PM PDT 24 Jul 31 05:00:46 PM PDT 24 480246237 ps
T553 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3618856428 Jul 31 05:01:06 PM PDT 24 Jul 31 05:01:07 PM PDT 24 74499018 ps
T554 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2282640420 Jul 31 05:00:35 PM PDT 24 Jul 31 05:00:38 PM PDT 24 263906266 ps
T555 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.169725226 Jul 31 05:00:44 PM PDT 24 Jul 31 05:00:45 PM PDT 24 164775920 ps
T94 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4223384650 Jul 31 05:00:48 PM PDT 24 Jul 31 05:00:49 PM PDT 24 103896715 ps
T95 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3940285322 Jul 31 05:00:53 PM PDT 24 Jul 31 05:00:55 PM PDT 24 475501230 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3237214324 Jul 31 05:00:57 PM PDT 24 Jul 31 05:01:00 PM PDT 24 275943088 ps
T96 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2132362152 Jul 31 05:01:09 PM PDT 24 Jul 31 05:01:11 PM PDT 24 141070384 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.180471428 Jul 31 05:00:56 PM PDT 24 Jul 31 05:00:57 PM PDT 24 69939678 ps
T558 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1281299130 Jul 31 05:01:13 PM PDT 24 Jul 31 05:01:15 PM PDT 24 221951364 ps
T97 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3726175700 Jul 31 05:00:53 PM PDT 24 Jul 31 05:00:57 PM PDT 24 411535172 ps
T559 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1135599584 Jul 31 05:00:47 PM PDT 24 Jul 31 05:00:48 PM PDT 24 68416125 ps
T126 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3673102746 Jul 31 05:01:12 PM PDT 24 Jul 31 05:01:15 PM PDT 24 877534521 ps
T121 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3919058783 Jul 31 05:00:53 PM PDT 24 Jul 31 05:00:55 PM PDT 24 474414458 ps
T98 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2268275117 Jul 31 05:01:04 PM PDT 24 Jul 31 05:01:10 PM PDT 24 111858975 ps
T560 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.126884262 Jul 31 05:01:09 PM PDT 24 Jul 31 05:01:10 PM PDT 24 83940855 ps
T561 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2445933136 Jul 31 05:00:39 PM PDT 24 Jul 31 05:00:40 PM PDT 24 179867739 ps
T562 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3881962106 Jul 31 05:01:15 PM PDT 24 Jul 31 05:01:17 PM PDT 24 433774995 ps
T563 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.257345237 Jul 31 05:01:35 PM PDT 24 Jul 31 05:01:37 PM PDT 24 197039398 ps
T564 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1390034605 Jul 31 05:00:57 PM PDT 24 Jul 31 05:00:59 PM PDT 24 559663326 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.982703695 Jul 31 05:00:56 PM PDT 24 Jul 31 05:00:58 PM PDT 24 209786785 ps
T566 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3443214612 Jul 31 05:00:59 PM PDT 24 Jul 31 05:01:01 PM PDT 24 144456323 ps
T127 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.22747685 Jul 31 05:00:55 PM PDT 24 Jul 31 05:00:57 PM PDT 24 422319360 ps
T117 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.584188775 Jul 31 05:00:42 PM PDT 24 Jul 31 05:00:45 PM PDT 24 922695443 ps
T567 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1956613594 Jul 31 05:00:52 PM PDT 24 Jul 31 05:00:53 PM PDT 24 116817750 ps
T568 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3810929828 Jul 31 05:00:47 PM PDT 24 Jul 31 05:00:48 PM PDT 24 194189260 ps
T123 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2556597027 Jul 31 05:01:06 PM PDT 24 Jul 31 05:01:08 PM PDT 24 263826669 ps
T124 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1492239152 Jul 31 05:00:50 PM PDT 24 Jul 31 05:00:52 PM PDT 24 116777125 ps
T569 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3134753526 Jul 31 05:00:41 PM PDT 24 Jul 31 05:00:44 PM PDT 24 397084099 ps
T570 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2786327042 Jul 31 05:00:54 PM PDT 24 Jul 31 05:00:56 PM PDT 24 168123836 ps
T571 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1343934452 Jul 31 05:01:14 PM PDT 24 Jul 31 05:01:15 PM PDT 24 142954238 ps
T572 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3668670800 Jul 31 05:01:04 PM PDT 24 Jul 31 05:01:06 PM PDT 24 200369939 ps
T573 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2895868114 Jul 31 05:00:52 PM PDT 24 Jul 31 05:00:54 PM PDT 24 215833592 ps
T574 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4249852024 Jul 31 05:01:12 PM PDT 24 Jul 31 05:01:14 PM PDT 24 170816702 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2175324540 Jul 31 05:00:34 PM PDT 24 Jul 31 05:00:41 PM PDT 24 227075113 ps
T576 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4006631597 Jul 31 05:00:42 PM PDT 24 Jul 31 05:00:43 PM PDT 24 72914993 ps
T577 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.423528015 Jul 31 05:01:11 PM PDT 24 Jul 31 05:01:12 PM PDT 24 78620763 ps
T125 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3643564923 Jul 31 05:00:51 PM PDT 24 Jul 31 05:00:53 PM PDT 24 128907977 ps
T578 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2182826841 Jul 31 05:00:56 PM PDT 24 Jul 31 05:00:58 PM PDT 24 198489226 ps
T579 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2073876256 Jul 31 05:00:52 PM PDT 24 Jul 31 05:00:53 PM PDT 24 141481279 ps
T119 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1711163615 Jul 31 05:01:14 PM PDT 24 Jul 31 05:01:17 PM PDT 24 812213208 ps
T580 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2046343729 Jul 31 05:00:55 PM PDT 24 Jul 31 05:00:56 PM PDT 24 128912510 ps
T581 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1007672014 Jul 31 05:00:42 PM PDT 24 Jul 31 05:00:43 PM PDT 24 80829836 ps
T582 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1258725403 Jul 31 05:00:55 PM PDT 24 Jul 31 05:00:56 PM PDT 24 200692907 ps
T135 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.131760332 Jul 31 05:00:57 PM PDT 24 Jul 31 05:01:00 PM PDT 24 884871538 ps
T118 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3338871720 Jul 31 05:00:33 PM PDT 24 Jul 31 05:00:36 PM PDT 24 911156477 ps
T583 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2935241824 Jul 31 05:00:53 PM PDT 24 Jul 31 05:00:55 PM PDT 24 408573973 ps
T584 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1667582948 Jul 31 05:00:55 PM PDT 24 Jul 31 05:00:56 PM PDT 24 168525175 ps
T585 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4075863259 Jul 31 05:00:42 PM PDT 24 Jul 31 05:00:43 PM PDT 24 92998606 ps
T586 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2948107994 Jul 31 05:01:03 PM PDT 24 Jul 31 05:01:05 PM PDT 24 305747400 ps
T587 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3413989447 Jul 31 05:01:08 PM PDT 24 Jul 31 05:01:10 PM PDT 24 82781988 ps
T588 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3714628640 Jul 31 05:02:06 PM PDT 24 Jul 31 05:02:08 PM PDT 24 262331827 ps
T589 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1739803305 Jul 31 05:00:42 PM PDT 24 Jul 31 05:00:44 PM PDT 24 206863114 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2195261391 Jul 31 05:00:45 PM PDT 24 Jul 31 05:00:51 PM PDT 24 127857490 ps
T591 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.751720025 Jul 31 05:00:50 PM PDT 24 Jul 31 05:00:53 PM PDT 24 941540088 ps
T592 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1867022637 Jul 31 05:01:00 PM PDT 24 Jul 31 05:01:01 PM PDT 24 73206725 ps
T593 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1626604516 Jul 31 05:00:45 PM PDT 24 Jul 31 05:00:46 PM PDT 24 207408874 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2809163747 Jul 31 05:00:33 PM PDT 24 Jul 31 05:00:36 PM PDT 24 360617581 ps
T595 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.164683689 Jul 31 05:01:13 PM PDT 24 Jul 31 05:01:16 PM PDT 24 798075811 ps
T596 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4278832467 Jul 31 05:00:45 PM PDT 24 Jul 31 05:00:51 PM PDT 24 264411949 ps
T597 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3860613327 Jul 31 05:00:50 PM PDT 24 Jul 31 05:00:51 PM PDT 24 75664477 ps
T598 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4263178792 Jul 31 05:00:46 PM PDT 24 Jul 31 05:00:48 PM PDT 24 237248479 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3028895889 Jul 31 05:00:52 PM PDT 24 Jul 31 05:00:53 PM PDT 24 56943173 ps
T122 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1494209262 Jul 31 05:01:01 PM PDT 24 Jul 31 05:01:04 PM PDT 24 785993636 ps
T600 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1716445622 Jul 31 05:01:05 PM PDT 24 Jul 31 05:01:06 PM PDT 24 117607461 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.72456482 Jul 31 05:00:39 PM PDT 24 Jul 31 05:00:42 PM PDT 24 341784348 ps
T602 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2723969037 Jul 31 05:01:05 PM PDT 24 Jul 31 05:01:08 PM PDT 24 195536032 ps
T603 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.926895630 Jul 31 05:01:06 PM PDT 24 Jul 31 05:01:07 PM PDT 24 81787741 ps
T604 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1833078872 Jul 31 05:01:06 PM PDT 24 Jul 31 05:01:08 PM PDT 24 189320475 ps
T120 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1046243067 Jul 31 05:00:56 PM PDT 24 Jul 31 05:00:59 PM PDT 24 785878557 ps
T605 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3332644982 Jul 31 05:00:54 PM PDT 24 Jul 31 05:00:55 PM PDT 24 74609424 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3003543973 Jul 31 05:01:13 PM PDT 24 Jul 31 05:01:15 PM PDT 24 80654377 ps
T607 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.252406571 Jul 31 05:00:40 PM PDT 24 Jul 31 05:00:41 PM PDT 24 67241079 ps
T608 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2162946246 Jul 31 05:00:54 PM PDT 24 Jul 31 05:00:55 PM PDT 24 203031367 ps
T609 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.655179433 Jul 31 05:00:50 PM PDT 24 Jul 31 05:00:51 PM PDT 24 73651165 ps
T610 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2748842280 Jul 31 05:00:51 PM PDT 24 Jul 31 05:00:54 PM PDT 24 164077318 ps
T611 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3440744891 Jul 31 05:00:46 PM PDT 24 Jul 31 05:00:48 PM PDT 24 118692256 ps
T612 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2646107890 Jul 31 05:00:46 PM PDT 24 Jul 31 05:00:47 PM PDT 24 115829996 ps
T613 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.738064598 Jul 31 05:01:35 PM PDT 24 Jul 31 05:01:38 PM PDT 24 278075897 ps
T614 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3683789170 Jul 31 05:00:40 PM PDT 24 Jul 31 05:00:41 PM PDT 24 158079028 ps
T615 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1869282815 Jul 31 05:00:54 PM PDT 24 Jul 31 05:00:58 PM PDT 24 606196715 ps
T616 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3819619475 Jul 31 05:02:00 PM PDT 24 Jul 31 05:02:02 PM PDT 24 422126266 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.484253614 Jul 31 05:00:57 PM PDT 24 Jul 31 05:00:58 PM PDT 24 99527026 ps
T618 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1730329244 Jul 31 05:00:55 PM PDT 24 Jul 31 05:00:58 PM PDT 24 263569325 ps
T619 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.942648868 Jul 31 05:00:54 PM PDT 24 Jul 31 05:00:55 PM PDT 24 105567942 ps
T620 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4100141859 Jul 31 05:01:28 PM PDT 24 Jul 31 05:01:31 PM PDT 24 817709613 ps

Test location /workspace/coverage/default/33.rstmgr_stress_all.3576247183
Short name T9
Test name
Test status
Simulation time 2672559999 ps
CPU time 12.39 seconds
Started Jul 31 05:20:08 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 208772 kb
Host smart-ec3b9889-9b57-426e-a581-8103cf3f8ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576247183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3576247183
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4242165882
Short name T2
Test name
Test status
Simulation time 496328733 ps
CPU time 2.65 seconds
Started Jul 31 05:19:45 PM PDT 24
Finished Jul 31 05:19:47 PM PDT 24
Peak memory 200228 kb
Host smart-c8319960-3708-4b5f-aa57-3f875f7b4abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242165882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4242165882
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.662285249
Short name T64
Test name
Test status
Simulation time 178872454 ps
CPU time 1.58 seconds
Started Jul 31 05:01:08 PM PDT 24
Finished Jul 31 05:01:09 PM PDT 24
Peak memory 208312 kb
Host smart-287c0d67-31e6-45bc-a8d8-928a9a5178aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662285249 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.662285249
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3891637221
Short name T69
Test name
Test status
Simulation time 8357018199 ps
CPU time 12.74 seconds
Started Jul 31 05:19:30 PM PDT 24
Finished Jul 31 05:19:43 PM PDT 24
Peak memory 217196 kb
Host smart-9baa416b-c69d-4c9d-9723-e0e1b050dd85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891637221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3891637221
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1101853862
Short name T10
Test name
Test status
Simulation time 1221917502 ps
CPU time 5.27 seconds
Started Jul 31 05:20:07 PM PDT 24
Finished Jul 31 05:20:12 PM PDT 24
Peak memory 217792 kb
Host smart-74229780-b23e-4876-8bc7-e60be72dc21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101853862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1101853862
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4131402007
Short name T61
Test name
Test status
Simulation time 421038884 ps
CPU time 1.93 seconds
Started Jul 31 05:00:55 PM PDT 24
Finished Jul 31 05:00:57 PM PDT 24
Peak memory 200088 kb
Host smart-c12cc7a0-6300-4d55-9fc2-a58fbbf02762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131402007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.4131402007
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.37157715
Short name T71
Test name
Test status
Simulation time 70570967 ps
CPU time 0.77 seconds
Started Jul 31 05:19:34 PM PDT 24
Finished Jul 31 05:19:34 PM PDT 24
Peak memory 200140 kb
Host smart-4fc89577-5d88-4066-a88d-5e7b84c6896b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37157715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.37157715
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2248602343
Short name T103
Test name
Test status
Simulation time 5279647835 ps
CPU time 17.24 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 200572 kb
Host smart-224f9a98-ab5d-442a-b9d6-0069abe51315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248602343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2248602343
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3726175700
Short name T97
Test name
Test status
Simulation time 411535172 ps
CPU time 3.15 seconds
Started Jul 31 05:00:53 PM PDT 24
Finished Jul 31 05:00:57 PM PDT 24
Peak memory 208140 kb
Host smart-e9ff9ceb-0cd7-444e-8b15-ec356334812d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726175700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3726175700
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2183574883
Short name T20
Test name
Test status
Simulation time 149499164 ps
CPU time 1.21 seconds
Started Jul 31 05:19:32 PM PDT 24
Finished Jul 31 05:19:33 PM PDT 24
Peak memory 200368 kb
Host smart-f6615a73-1376-4492-badd-50bbb62652ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183574883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2183574883
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2174519659
Short name T26
Test name
Test status
Simulation time 1905542199 ps
CPU time 6.86 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:20:01 PM PDT 24
Peak memory 221732 kb
Host smart-912a9438-9e54-42a8-b5f1-290160971038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174519659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2174519659
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.131760332
Short name T135
Test name
Test status
Simulation time 884871538 ps
CPU time 3.02 seconds
Started Jul 31 05:00:57 PM PDT 24
Finished Jul 31 05:01:00 PM PDT 24
Peak memory 200212 kb
Host smart-6c407186-b7f8-45be-abd2-e85e1a08777a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131760332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
131760332
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.4227754164
Short name T137
Test name
Test status
Simulation time 209123459 ps
CPU time 1.28 seconds
Started Jul 31 05:19:46 PM PDT 24
Finished Jul 31 05:19:47 PM PDT 24
Peak memory 200352 kb
Host smart-c8793aca-c2de-4e28-ba00-514a45e43636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227754164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.4227754164
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1492239152
Short name T124
Test name
Test status
Simulation time 116777125 ps
CPU time 1.64 seconds
Started Jul 31 05:00:50 PM PDT 24
Finished Jul 31 05:00:52 PM PDT 24
Peak memory 208176 kb
Host smart-a977ed39-83cd-4380-be70-84b1f6e5a501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492239152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1492239152
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3262883033
Short name T108
Test name
Test status
Simulation time 81813617 ps
CPU time 1.04 seconds
Started Jul 31 05:01:01 PM PDT 24
Finished Jul 31 05:01:03 PM PDT 24
Peak memory 199988 kb
Host smart-b0798263-96a8-4026-93ee-4c98ac45f7ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262883033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3262883033
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2121369960
Short name T15
Test name
Test status
Simulation time 155206282 ps
CPU time 0.91 seconds
Started Jul 31 05:19:59 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 200128 kb
Host smart-be71ffcb-3a48-4814-8712-515d9d045d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121369960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2121369960
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3558287892
Short name T53
Test name
Test status
Simulation time 1223993880 ps
CPU time 5.39 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:08 PM PDT 24
Peak memory 221652 kb
Host smart-3e74f67b-2514-4bd4-a503-55bcc7bb66aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558287892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3558287892
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3338871720
Short name T118
Test name
Test status
Simulation time 911156477 ps
CPU time 3.03 seconds
Started Jul 31 05:00:33 PM PDT 24
Finished Jul 31 05:00:36 PM PDT 24
Peak memory 199968 kb
Host smart-75d1e5c6-c767-4483-b741-c945a8c061c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338871720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3338871720
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1494209262
Short name T122
Test name
Test status
Simulation time 785993636 ps
CPU time 2.82 seconds
Started Jul 31 05:01:01 PM PDT 24
Finished Jul 31 05:01:04 PM PDT 24
Peak memory 200088 kb
Host smart-2d375806-e1f7-4161-a376-c2584aa20dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494209262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1494209262
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.474105519
Short name T105
Test name
Test status
Simulation time 5122781142 ps
CPU time 22.38 seconds
Started Jul 31 05:19:37 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 208788 kb
Host smart-5696ec05-e698-4929-8890-3b6f1f377b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474105519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.474105519
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4278832467
Short name T596
Test name
Test status
Simulation time 264411949 ps
CPU time 1.68 seconds
Started Jul 31 05:00:45 PM PDT 24
Finished Jul 31 05:00:51 PM PDT 24
Peak memory 199864 kb
Host smart-5d2c79ae-bce6-4bb3-8620-403de4e1c14d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278832467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
278832467
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3464099520
Short name T59
Test name
Test status
Simulation time 272899045 ps
CPU time 3.2 seconds
Started Jul 31 05:00:45 PM PDT 24
Finished Jul 31 05:00:48 PM PDT 24
Peak memory 199972 kb
Host smart-2c1011eb-22dc-4bab-b5bf-1bdd80e4e629
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464099520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
464099520
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4075863259
Short name T585
Test name
Test status
Simulation time 92998606 ps
CPU time 0.8 seconds
Started Jul 31 05:00:42 PM PDT 24
Finished Jul 31 05:00:43 PM PDT 24
Peak memory 199884 kb
Host smart-8ef9e913-fe68-4f62-8285-a160cb331ea3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075863259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.4
075863259
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2572454787
Short name T65
Test name
Test status
Simulation time 201662093 ps
CPU time 1.25 seconds
Started Jul 31 05:00:36 PM PDT 24
Finished Jul 31 05:00:37 PM PDT 24
Peak memory 208144 kb
Host smart-418a2a28-137c-4b1d-b3c8-50ccb89998ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572454787 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2572454787
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3028895889
Short name T599
Test name
Test status
Simulation time 56943173 ps
CPU time 0.74 seconds
Started Jul 31 05:00:52 PM PDT 24
Finished Jul 31 05:00:53 PM PDT 24
Peak memory 199888 kb
Host smart-54eaa40b-ede3-4466-80f9-43e7936158b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028895889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3028895889
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1956613594
Short name T567
Test name
Test status
Simulation time 116817750 ps
CPU time 1.57 seconds
Started Jul 31 05:00:52 PM PDT 24
Finished Jul 31 05:00:53 PM PDT 24
Peak memory 208204 kb
Host smart-e6310c7f-ed5d-4b49-9483-fb975a90c654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956613594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1956613594
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1395734692
Short name T92
Test name
Test status
Simulation time 899461893 ps
CPU time 2.91 seconds
Started Jul 31 05:00:47 PM PDT 24
Finished Jul 31 05:00:50 PM PDT 24
Peak memory 200092 kb
Host smart-2a237584-fd99-4239-9e8a-26cdc449a321
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395734692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1395734692
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2809163747
Short name T594
Test name
Test status
Simulation time 360617581 ps
CPU time 2.55 seconds
Started Jul 31 05:00:33 PM PDT 24
Finished Jul 31 05:00:36 PM PDT 24
Peak memory 208020 kb
Host smart-a0c06d91-3703-439c-8963-97828df7f8eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809163747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
809163747
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3237214324
Short name T556
Test name
Test status
Simulation time 275943088 ps
CPU time 3.12 seconds
Started Jul 31 05:00:57 PM PDT 24
Finished Jul 31 05:01:00 PM PDT 24
Peak memory 199956 kb
Host smart-f787f338-3eb5-4fc9-8a58-0c2fa0792d86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237214324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
237214324
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2073876256
Short name T579
Test name
Test status
Simulation time 141481279 ps
CPU time 0.95 seconds
Started Jul 31 05:00:52 PM PDT 24
Finished Jul 31 05:00:53 PM PDT 24
Peak memory 199884 kb
Host smart-718a6978-02ab-47c3-a477-e8ac1d115215
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073876256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
073876256
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4223384650
Short name T94
Test name
Test status
Simulation time 103896715 ps
CPU time 1 seconds
Started Jul 31 05:00:48 PM PDT 24
Finished Jul 31 05:00:49 PM PDT 24
Peak memory 208152 kb
Host smart-3a0f9343-e2d8-4683-86db-ef64cca5b54c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223384650 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.4223384650
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.252406571
Short name T607
Test name
Test status
Simulation time 67241079 ps
CPU time 0.75 seconds
Started Jul 31 05:00:40 PM PDT 24
Finished Jul 31 05:00:41 PM PDT 24
Peak memory 199956 kb
Host smart-52e50ca8-a87b-4bf5-b8b6-90aeb61ee16a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252406571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.252406571
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2175324540
Short name T575
Test name
Test status
Simulation time 227075113 ps
CPU time 1.54 seconds
Started Jul 31 05:00:34 PM PDT 24
Finished Jul 31 05:00:41 PM PDT 24
Peak memory 199960 kb
Host smart-1ebdf298-a805-4401-b0fc-08009cbc85b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175324540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2175324540
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3683789170
Short name T614
Test name
Test status
Simulation time 158079028 ps
CPU time 1.12 seconds
Started Jul 31 05:00:40 PM PDT 24
Finished Jul 31 05:00:41 PM PDT 24
Peak memory 209340 kb
Host smart-764ed7a1-e8a5-4b38-ae72-fe6ac00cf2ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683789170 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3683789170
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.898963266
Short name T58
Test name
Test status
Simulation time 56655234 ps
CPU time 0.76 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 198144 kb
Host smart-79bfb7d7-78ff-4d35-a319-f72f7fa35af9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898963266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.898963266
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2861562485
Short name T114
Test name
Test status
Simulation time 159942860 ps
CPU time 1.19 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:42 PM PDT 24
Peak memory 198968 kb
Host smart-786f4400-3d4f-495b-9a92-86835e49a1ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861562485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2861562485
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3643564923
Short name T125
Test name
Test status
Simulation time 128907977 ps
CPU time 1.84 seconds
Started Jul 31 05:00:51 PM PDT 24
Finished Jul 31 05:00:53 PM PDT 24
Peak memory 208132 kb
Host smart-5edabe05-29be-4d71-9cfa-d7b4643c02b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643564923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3643564923
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1046243067
Short name T120
Test name
Test status
Simulation time 785878557 ps
CPU time 3.12 seconds
Started Jul 31 05:00:56 PM PDT 24
Finished Jul 31 05:00:59 PM PDT 24
Peak memory 199992 kb
Host smart-db807834-8016-402d-a9a4-0a6d77f69127
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046243067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1046243067
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1258725403
Short name T582
Test name
Test status
Simulation time 200692907 ps
CPU time 1.26 seconds
Started Jul 31 05:00:55 PM PDT 24
Finished Jul 31 05:00:56 PM PDT 24
Peak memory 199944 kb
Host smart-1fe89b63-8bf8-4272-adba-cf9286858a1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258725403 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1258725403
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1135599584
Short name T559
Test name
Test status
Simulation time 68416125 ps
CPU time 0.77 seconds
Started Jul 31 05:00:47 PM PDT 24
Finished Jul 31 05:00:48 PM PDT 24
Peak memory 199856 kb
Host smart-8e4a45ab-d9a6-41d5-8a20-026b5f2655be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135599584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1135599584
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1281299130
Short name T558
Test name
Test status
Simulation time 221951364 ps
CPU time 1.55 seconds
Started Jul 31 05:01:13 PM PDT 24
Finished Jul 31 05:01:15 PM PDT 24
Peak memory 200064 kb
Host smart-a67d3d3d-1fd7-4977-bc68-41b0267feabb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281299130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1281299130
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.738064598
Short name T613
Test name
Test status
Simulation time 278075897 ps
CPU time 2.02 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:38 PM PDT 24
Peak memory 206444 kb
Host smart-23ba935b-bb43-4038-bbcc-41d2bcae36bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738064598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.738064598
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1711163615
Short name T119
Test name
Test status
Simulation time 812213208 ps
CPU time 3.05 seconds
Started Jul 31 05:01:14 PM PDT 24
Finished Jul 31 05:01:17 PM PDT 24
Peak memory 200092 kb
Host smart-2ca379a4-5cc5-4a6f-84da-d17a413c78e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711163615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1711163615
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1833078872
Short name T604
Test name
Test status
Simulation time 189320475 ps
CPU time 1.31 seconds
Started Jul 31 05:01:06 PM PDT 24
Finished Jul 31 05:01:08 PM PDT 24
Peak memory 208236 kb
Host smart-264a9750-40d3-4f61-a34d-ef0a931f2113
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833078872 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1833078872
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.918722688
Short name T109
Test name
Test status
Simulation time 68066452 ps
CPU time 0.76 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 199876 kb
Host smart-478741f4-3f1a-4ed3-a857-f7c5e8ee43a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918722688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.918722688
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1343934452
Short name T571
Test name
Test status
Simulation time 142954238 ps
CPU time 1.35 seconds
Started Jul 31 05:01:14 PM PDT 24
Finished Jul 31 05:01:15 PM PDT 24
Peak memory 200160 kb
Host smart-453aa31a-b2ad-4537-90c3-e8cf1d889edb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343934452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1343934452
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1869282815
Short name T615
Test name
Test status
Simulation time 606196715 ps
CPU time 3.87 seconds
Started Jul 31 05:00:54 PM PDT 24
Finished Jul 31 05:00:58 PM PDT 24
Peak memory 208264 kb
Host smart-93343bdb-310a-41f3-88dc-a2f3e507f5fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869282815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1869282815
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1390034605
Short name T564
Test name
Test status
Simulation time 559663326 ps
CPU time 1.95 seconds
Started Jul 31 05:00:57 PM PDT 24
Finished Jul 31 05:00:59 PM PDT 24
Peak memory 200040 kb
Host smart-2c00821d-24db-4da3-8ab3-0b1c09145d68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390034605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1390034605
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2182826841
Short name T578
Test name
Test status
Simulation time 198489226 ps
CPU time 2.18 seconds
Started Jul 31 05:00:56 PM PDT 24
Finished Jul 31 05:00:58 PM PDT 24
Peak memory 208748 kb
Host smart-e73f6a51-3eff-4140-ab8a-6ed4391cd2a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182826841 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2182826841
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.126884262
Short name T560
Test name
Test status
Simulation time 83940855 ps
CPU time 0.8 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 200004 kb
Host smart-4ef7f83e-658a-454d-9a3b-9198de38d52e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126884262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.126884262
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2046343729
Short name T580
Test name
Test status
Simulation time 128912510 ps
CPU time 1.16 seconds
Started Jul 31 05:00:55 PM PDT 24
Finished Jul 31 05:00:56 PM PDT 24
Peak memory 199964 kb
Host smart-16166e99-72d2-40b5-b971-e75773e5f285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046343729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2046343729
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2556597027
Short name T123
Test name
Test status
Simulation time 263826669 ps
CPU time 1.92 seconds
Started Jul 31 05:01:06 PM PDT 24
Finished Jul 31 05:01:08 PM PDT 24
Peak memory 208144 kb
Host smart-7ae343e6-0901-4315-b2a2-5620206965b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556597027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2556597027
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.164683689
Short name T595
Test name
Test status
Simulation time 798075811 ps
CPU time 2.76 seconds
Started Jul 31 05:01:13 PM PDT 24
Finished Jul 31 05:01:16 PM PDT 24
Peak memory 200056 kb
Host smart-023a63a2-72d6-42d6-926c-26dc43dcaedd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164683689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.164683689
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3740552122
Short name T91
Test name
Test status
Simulation time 189443603 ps
CPU time 1.85 seconds
Started Jul 31 05:00:57 PM PDT 24
Finished Jul 31 05:00:59 PM PDT 24
Peak memory 208392 kb
Host smart-7b14c6df-dcbb-4017-986d-d9dc5dc79a38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740552122 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3740552122
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3413989447
Short name T587
Test name
Test status
Simulation time 82781988 ps
CPU time 0.83 seconds
Started Jul 31 05:01:08 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 199788 kb
Host smart-96f129f5-048b-487c-95af-bc339514db8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413989447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3413989447
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2379492036
Short name T110
Test name
Test status
Simulation time 149359308 ps
CPU time 1.13 seconds
Started Jul 31 05:00:56 PM PDT 24
Finished Jul 31 05:00:58 PM PDT 24
Peak memory 200020 kb
Host smart-f48933bc-6133-4d30-a043-962a0eae4b41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379492036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2379492036
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2948107994
Short name T586
Test name
Test status
Simulation time 305747400 ps
CPU time 2.32 seconds
Started Jul 31 05:01:03 PM PDT 24
Finished Jul 31 05:01:05 PM PDT 24
Peak memory 211824 kb
Host smart-b3705713-2f9a-48be-a37c-3e005d7556d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948107994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2948107994
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3673102746
Short name T126
Test name
Test status
Simulation time 877534521 ps
CPU time 3.14 seconds
Started Jul 31 05:01:12 PM PDT 24
Finished Jul 31 05:01:15 PM PDT 24
Peak memory 200184 kb
Host smart-2e991e2f-a8ca-44c7-a80c-dad259599955
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673102746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3673102746
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4245238395
Short name T90
Test name
Test status
Simulation time 127320289 ps
CPU time 1.22 seconds
Started Jul 31 05:01:03 PM PDT 24
Finished Jul 31 05:01:04 PM PDT 24
Peak memory 208192 kb
Host smart-a34540bd-3ea6-4405-876f-95ea3b3f1c30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245238395 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.4245238395
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3011561173
Short name T547
Test name
Test status
Simulation time 89784231 ps
CPU time 0.9 seconds
Started Jul 31 05:01:01 PM PDT 24
Finished Jul 31 05:01:02 PM PDT 24
Peak memory 199888 kb
Host smart-beb69afb-2fdb-4115-b305-0f847c8bec26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011561173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3011561173
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2805989998
Short name T115
Test name
Test status
Simulation time 90151577 ps
CPU time 1.03 seconds
Started Jul 31 05:01:14 PM PDT 24
Finished Jul 31 05:01:15 PM PDT 24
Peak memory 200028 kb
Host smart-10ff4f6c-210c-4d55-bcf6-8e4b3e556ad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805989998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2805989998
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4263178792
Short name T598
Test name
Test status
Simulation time 237248479 ps
CPU time 1.86 seconds
Started Jul 31 05:00:46 PM PDT 24
Finished Jul 31 05:00:48 PM PDT 24
Peak memory 208176 kb
Host smart-078fef3b-19ff-448f-a219-ad426114e370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263178792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4263178792
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4100141859
Short name T620
Test name
Test status
Simulation time 817709613 ps
CPU time 2.76 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:31 PM PDT 24
Peak memory 200112 kb
Host smart-7844c3fc-dbaf-4051-8d2c-422d76dd1bad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100141859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.4100141859
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3668670800
Short name T572
Test name
Test status
Simulation time 200369939 ps
CPU time 1.31 seconds
Started Jul 31 05:01:04 PM PDT 24
Finished Jul 31 05:01:06 PM PDT 24
Peak memory 208316 kb
Host smart-19489fee-5a57-41d7-ab2e-b08cb2597dfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668670800 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3668670800
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3618856428
Short name T553
Test name
Test status
Simulation time 74499018 ps
CPU time 0.82 seconds
Started Jul 31 05:01:06 PM PDT 24
Finished Jul 31 05:01:07 PM PDT 24
Peak memory 199840 kb
Host smart-8ae1eb8d-06a6-44c6-b7fd-53bbad48bdb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618856428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3618856428
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3003543973
Short name T606
Test name
Test status
Simulation time 80654377 ps
CPU time 1.02 seconds
Started Jul 31 05:01:13 PM PDT 24
Finished Jul 31 05:01:15 PM PDT 24
Peak memory 199968 kb
Host smart-964e5f11-6af1-4412-9295-6412150f63bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003543973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3003543973
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4249852024
Short name T574
Test name
Test status
Simulation time 170816702 ps
CPU time 1.51 seconds
Started Jul 31 05:01:12 PM PDT 24
Finished Jul 31 05:01:14 PM PDT 24
Peak memory 208144 kb
Host smart-bec48834-f1cf-4175-abc9-f748a768993f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249852024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4249852024
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2162946246
Short name T608
Test name
Test status
Simulation time 203031367 ps
CPU time 1.32 seconds
Started Jul 31 05:00:54 PM PDT 24
Finished Jul 31 05:00:55 PM PDT 24
Peak memory 208308 kb
Host smart-4d653ad9-3f1f-473f-aa67-30fcf965d2b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162946246 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2162946246
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.904522127
Short name T549
Test name
Test status
Simulation time 69023044 ps
CPU time 0.8 seconds
Started Jul 31 05:00:59 PM PDT 24
Finished Jul 31 05:01:00 PM PDT 24
Peak memory 199888 kb
Host smart-9b4c80ba-2ce8-463f-84f8-7a7b0d6c0395
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904522127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.904522127
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2895868114
Short name T573
Test name
Test status
Simulation time 215833592 ps
CPU time 1.53 seconds
Started Jul 31 05:00:52 PM PDT 24
Finished Jul 31 05:00:54 PM PDT 24
Peak memory 200024 kb
Host smart-597987c0-5046-4118-a74f-51528541cfa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895868114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2895868114
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2748842280
Short name T610
Test name
Test status
Simulation time 164077318 ps
CPU time 2.36 seconds
Started Jul 31 05:00:51 PM PDT 24
Finished Jul 31 05:00:54 PM PDT 24
Peak memory 208100 kb
Host smart-79895011-665f-4efe-9825-2caaf5acb586
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748842280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2748842280
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2935241824
Short name T583
Test name
Test status
Simulation time 408573973 ps
CPU time 1.81 seconds
Started Jul 31 05:00:53 PM PDT 24
Finished Jul 31 05:00:55 PM PDT 24
Peak memory 200020 kb
Host smart-6eb1617b-2fb4-45c7-bde8-dadaab563c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935241824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2935241824
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3810929828
Short name T568
Test name
Test status
Simulation time 194189260 ps
CPU time 1.29 seconds
Started Jul 31 05:00:47 PM PDT 24
Finished Jul 31 05:00:48 PM PDT 24
Peak memory 208240 kb
Host smart-0d2e8bf6-a0fe-47e2-9c67-b9e429a46c3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810929828 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3810929828
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.655179433
Short name T609
Test name
Test status
Simulation time 73651165 ps
CPU time 0.81 seconds
Started Jul 31 05:00:50 PM PDT 24
Finished Jul 31 05:00:51 PM PDT 24
Peak memory 199796 kb
Host smart-2f81696b-b033-4d9a-80b6-f59f60f06857
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655179433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.655179433
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.425819866
Short name T111
Test name
Test status
Simulation time 105457403 ps
CPU time 1.31 seconds
Started Jul 31 05:01:01 PM PDT 24
Finished Jul 31 05:01:02 PM PDT 24
Peak memory 200100 kb
Host smart-9f2c559d-06e1-467a-924f-69f0f3d19a40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425819866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.425819866
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2132362152
Short name T96
Test name
Test status
Simulation time 141070384 ps
CPU time 1.96 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:11 PM PDT 24
Peak memory 208168 kb
Host smart-da90207c-b1d5-485f-baef-798577519197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132362152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2132362152
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1255228389
Short name T112
Test name
Test status
Simulation time 63357425 ps
CPU time 0.74 seconds
Started Jul 31 05:01:08 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 199744 kb
Host smart-763c1739-4d24-4ade-acef-cc4c603a7cac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255228389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1255228389
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3570376872
Short name T551
Test name
Test status
Simulation time 263079077 ps
CPU time 1.65 seconds
Started Jul 31 05:00:48 PM PDT 24
Finished Jul 31 05:00:49 PM PDT 24
Peak memory 199948 kb
Host smart-9483164b-e2da-45d0-a0bc-42b6890d7d4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570376872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3570376872
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2723969037
Short name T602
Test name
Test status
Simulation time 195536032 ps
CPU time 3.01 seconds
Started Jul 31 05:01:05 PM PDT 24
Finished Jul 31 05:01:08 PM PDT 24
Peak memory 208268 kb
Host smart-531709db-fcd0-40c3-897d-bf3cf9c882ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723969037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2723969037
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3881962106
Short name T562
Test name
Test status
Simulation time 433774995 ps
CPU time 1.79 seconds
Started Jul 31 05:01:15 PM PDT 24
Finished Jul 31 05:01:17 PM PDT 24
Peak memory 200136 kb
Host smart-534b3e9f-8583-4375-b9b3-0c1799cab163
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881962106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3881962106
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1899227035
Short name T136
Test name
Test status
Simulation time 410284942 ps
CPU time 2.4 seconds
Started Jul 31 05:00:48 PM PDT 24
Finished Jul 31 05:00:51 PM PDT 24
Peak memory 200092 kb
Host smart-cfe09db7-2de4-4d7e-90e9-ec6dd38764b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899227035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
899227035
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2830886505
Short name T552
Test name
Test status
Simulation time 480246237 ps
CPU time 5.58 seconds
Started Jul 31 05:00:40 PM PDT 24
Finished Jul 31 05:00:46 PM PDT 24
Peak memory 200032 kb
Host smart-1c461b9c-dc2b-48c8-a487-f411ac6577b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830886505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
830886505
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.251699615
Short name T116
Test name
Test status
Simulation time 131195444 ps
CPU time 0.91 seconds
Started Jul 31 05:00:39 PM PDT 24
Finished Jul 31 05:00:40 PM PDT 24
Peak memory 199896 kb
Host smart-955df45f-f184-4750-9275-03dd8de82b0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251699615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.251699615
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2268275117
Short name T98
Test name
Test status
Simulation time 111858975 ps
CPU time 1.13 seconds
Started Jul 31 05:01:04 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 208216 kb
Host smart-1646e9df-5d4a-4891-afa2-5d9e676fb336
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268275117 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2268275117
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3860613327
Short name T597
Test name
Test status
Simulation time 75664477 ps
CPU time 0.87 seconds
Started Jul 31 05:00:50 PM PDT 24
Finished Jul 31 05:00:51 PM PDT 24
Peak memory 199892 kb
Host smart-69bb5d0e-3403-4c32-bc65-05bc1bfce1ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860613327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3860613327
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.982703695
Short name T565
Test name
Test status
Simulation time 209786785 ps
CPU time 1.4 seconds
Started Jul 31 05:00:56 PM PDT 24
Finished Jul 31 05:00:58 PM PDT 24
Peak memory 199944 kb
Host smart-7ab3a7d2-9ab4-470d-9c47-ec8521ef3d1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982703695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.982703695
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.72456482
Short name T601
Test name
Test status
Simulation time 341784348 ps
CPU time 2.48 seconds
Started Jul 31 05:00:39 PM PDT 24
Finished Jul 31 05:00:42 PM PDT 24
Peak memory 216216 kb
Host smart-0ec816e7-652b-4b79-b319-70d89e88c8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72456482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.72456482
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3940285322
Short name T95
Test name
Test status
Simulation time 475501230 ps
CPU time 1.89 seconds
Started Jul 31 05:00:53 PM PDT 24
Finished Jul 31 05:00:55 PM PDT 24
Peak memory 200104 kb
Host smart-20d81231-e582-446d-90e3-9ee0d5a2b636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940285322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3940285322
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1626604516
Short name T593
Test name
Test status
Simulation time 207408874 ps
CPU time 1.46 seconds
Started Jul 31 05:00:45 PM PDT 24
Finished Jul 31 05:00:46 PM PDT 24
Peak memory 199960 kb
Host smart-94daf2c5-1ea3-4922-a972-ee4f8a74ea9a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626604516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
626604516
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2282640420
Short name T554
Test name
Test status
Simulation time 263906266 ps
CPU time 3.2 seconds
Started Jul 31 05:00:35 PM PDT 24
Finished Jul 31 05:00:38 PM PDT 24
Peak memory 199844 kb
Host smart-9a030445-5de9-4dc9-9ae5-de679e73b571
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282640420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
282640420
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3773847290
Short name T546
Test name
Test status
Simulation time 144409854 ps
CPU time 0.92 seconds
Started Jul 31 05:00:48 PM PDT 24
Finished Jul 31 05:00:49 PM PDT 24
Peak memory 199952 kb
Host smart-4120718b-98a0-45f7-a0d5-c8369d35a5fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773847290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
773847290
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.484253614
Short name T617
Test name
Test status
Simulation time 99527026 ps
CPU time 0.91 seconds
Started Jul 31 05:00:57 PM PDT 24
Finished Jul 31 05:00:58 PM PDT 24
Peak memory 200060 kb
Host smart-4fe89dd8-1140-4e6e-b799-f76eab7fbdff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484253614 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.484253614
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.180471428
Short name T557
Test name
Test status
Simulation time 69939678 ps
CPU time 0.79 seconds
Started Jul 31 05:00:56 PM PDT 24
Finished Jul 31 05:00:57 PM PDT 24
Peak memory 199920 kb
Host smart-9c543d39-5bca-4a3f-b04a-b83a59d01cd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180471428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.180471428
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.926895630
Short name T603
Test name
Test status
Simulation time 81787741 ps
CPU time 0.97 seconds
Started Jul 31 05:01:06 PM PDT 24
Finished Jul 31 05:01:07 PM PDT 24
Peak memory 199920 kb
Host smart-0f2c41ea-5876-4fc8-8177-c09ff03115f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926895630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.926895630
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1739803305
Short name T589
Test name
Test status
Simulation time 206863114 ps
CPU time 1.49 seconds
Started Jul 31 05:00:42 PM PDT 24
Finished Jul 31 05:00:44 PM PDT 24
Peak memory 208176 kb
Host smart-5f516597-d848-4736-b4c5-c7556d4e5059
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739803305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1739803305
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.584188775
Short name T117
Test name
Test status
Simulation time 922695443 ps
CPU time 3.02 seconds
Started Jul 31 05:00:42 PM PDT 24
Finished Jul 31 05:00:45 PM PDT 24
Peak memory 199972 kb
Host smart-c6de4d45-c036-4762-afc4-352888a6c0ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584188775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
584188775
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3134753526
Short name T569
Test name
Test status
Simulation time 397084099 ps
CPU time 2.53 seconds
Started Jul 31 05:00:41 PM PDT 24
Finished Jul 31 05:00:44 PM PDT 24
Peak memory 199900 kb
Host smart-05185dd2-6d94-46e3-adbd-7e1703c4eff7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134753526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
134753526
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1730329244
Short name T618
Test name
Test status
Simulation time 263569325 ps
CPU time 3.28 seconds
Started Jul 31 05:00:55 PM PDT 24
Finished Jul 31 05:00:58 PM PDT 24
Peak memory 200004 kb
Host smart-f52568f6-8226-4fec-ab70-522090a89f2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730329244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
730329244
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2195261391
Short name T590
Test name
Test status
Simulation time 127857490 ps
CPU time 0.91 seconds
Started Jul 31 05:00:45 PM PDT 24
Finished Jul 31 05:00:51 PM PDT 24
Peak memory 199944 kb
Host smart-f1f64101-0243-46fa-a8f7-a0b37b1edaaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195261391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
195261391
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2646107890
Short name T612
Test name
Test status
Simulation time 115829996 ps
CPU time 0.91 seconds
Started Jul 31 05:00:46 PM PDT 24
Finished Jul 31 05:00:47 PM PDT 24
Peak memory 199848 kb
Host smart-c6f59690-5de8-4e56-a7ab-6b1e86f7b401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646107890 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2646107890
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1007672014
Short name T581
Test name
Test status
Simulation time 80829836 ps
CPU time 0.86 seconds
Started Jul 31 05:00:42 PM PDT 24
Finished Jul 31 05:00:43 PM PDT 24
Peak memory 199812 kb
Host smart-41c85ff9-5fac-4ce1-9699-5d1ccb9cee01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007672014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1007672014
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.169725226
Short name T555
Test name
Test status
Simulation time 164775920 ps
CPU time 1.14 seconds
Started Jul 31 05:00:44 PM PDT 24
Finished Jul 31 05:00:45 PM PDT 24
Peak memory 199952 kb
Host smart-59ab82d9-bf9e-44b4-b21a-a8abe07dd4d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169725226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.169725226
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1716445622
Short name T600
Test name
Test status
Simulation time 117607461 ps
CPU time 1.55 seconds
Started Jul 31 05:01:05 PM PDT 24
Finished Jul 31 05:01:06 PM PDT 24
Peak memory 208072 kb
Host smart-46b6e649-95a9-4e1c-bf10-19714e79aceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716445622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1716445622
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3919058783
Short name T121
Test name
Test status
Simulation time 474414458 ps
CPU time 1.92 seconds
Started Jul 31 05:00:53 PM PDT 24
Finished Jul 31 05:00:55 PM PDT 24
Peak memory 200056 kb
Host smart-8efb692d-d8a2-49c7-8f50-bf94d11e5f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919058783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3919058783
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2445933136
Short name T561
Test name
Test status
Simulation time 179867739 ps
CPU time 1.61 seconds
Started Jul 31 05:00:39 PM PDT 24
Finished Jul 31 05:00:40 PM PDT 24
Peak memory 208264 kb
Host smart-db601970-29f3-49e3-94a1-1dfb36583fd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445933136 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2445933136
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3332644982
Short name T605
Test name
Test status
Simulation time 74609424 ps
CPU time 0.78 seconds
Started Jul 31 05:00:54 PM PDT 24
Finished Jul 31 05:00:55 PM PDT 24
Peak memory 199676 kb
Host smart-4c896275-f489-4fa2-bf73-7854596ca893
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332644982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3332644982
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3443214612
Short name T566
Test name
Test status
Simulation time 144456323 ps
CPU time 1.17 seconds
Started Jul 31 05:00:59 PM PDT 24
Finished Jul 31 05:01:01 PM PDT 24
Peak memory 199956 kb
Host smart-810d6a5e-d04c-4eb3-afdd-559aba72fd28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443214612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3443214612
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.751720025
Short name T591
Test name
Test status
Simulation time 941540088 ps
CPU time 3.22 seconds
Started Jul 31 05:00:50 PM PDT 24
Finished Jul 31 05:00:53 PM PDT 24
Peak memory 200120 kb
Host smart-99071fc6-f14a-41b7-adaa-80fb03db3d33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751720025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
751720025
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.942648868
Short name T619
Test name
Test status
Simulation time 105567942 ps
CPU time 0.98 seconds
Started Jul 31 05:00:54 PM PDT 24
Finished Jul 31 05:00:55 PM PDT 24
Peak memory 199960 kb
Host smart-c9e4d1ac-bbd1-4c30-bf1a-4b842d3e3d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942648868 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.942648868
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.423528015
Short name T577
Test name
Test status
Simulation time 78620763 ps
CPU time 0.83 seconds
Started Jul 31 05:01:11 PM PDT 24
Finished Jul 31 05:01:12 PM PDT 24
Peak memory 200120 kb
Host smart-fa215f1e-c1fc-48fb-8f9c-7783b70f34b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423528015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.423528015
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2681440141
Short name T60
Test name
Test status
Simulation time 169958382 ps
CPU time 1.23 seconds
Started Jul 31 05:01:04 PM PDT 24
Finished Jul 31 05:01:05 PM PDT 24
Peak memory 199984 kb
Host smart-5384f878-28df-49fe-a079-9b4810d27184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681440141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2681440141
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3440744891
Short name T611
Test name
Test status
Simulation time 118692256 ps
CPU time 1.64 seconds
Started Jul 31 05:00:46 PM PDT 24
Finished Jul 31 05:00:48 PM PDT 24
Peak memory 208272 kb
Host smart-ed73c98f-e0ae-4182-aa3c-3e13576f87b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440744891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3440744891
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.257345237
Short name T563
Test name
Test status
Simulation time 197039398 ps
CPU time 1.39 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 206676 kb
Host smart-e8573a04-1086-48ca-89be-3be20657c124
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257345237 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.257345237
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4006631597
Short name T576
Test name
Test status
Simulation time 72914993 ps
CPU time 0.81 seconds
Started Jul 31 05:00:42 PM PDT 24
Finished Jul 31 05:00:43 PM PDT 24
Peak memory 199960 kb
Host smart-717ccb0a-479f-445d-a461-6cc471328086
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006631597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4006631597
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2763800103
Short name T548
Test name
Test status
Simulation time 183994297 ps
CPU time 1.34 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:02:00 PM PDT 24
Peak memory 199948 kb
Host smart-d19f90ed-da8e-4a01-a7f8-a3b53a89d8a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763800103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2763800103
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3637098794
Short name T67
Test name
Test status
Simulation time 322745421 ps
CPU time 2.3 seconds
Started Jul 31 05:00:53 PM PDT 24
Finished Jul 31 05:00:56 PM PDT 24
Peak memory 208168 kb
Host smart-b9224ad1-fb31-4dbb-b390-ec8fb73f2323
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637098794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3637098794
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.22747685
Short name T127
Test name
Test status
Simulation time 422319360 ps
CPU time 1.75 seconds
Started Jul 31 05:00:55 PM PDT 24
Finished Jul 31 05:00:57 PM PDT 24
Peak memory 200004 kb
Host smart-bef7ed00-ba73-4294-a7d2-56b94d75080a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22747685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.22747685
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2786327042
Short name T570
Test name
Test status
Simulation time 168123836 ps
CPU time 1.54 seconds
Started Jul 31 05:00:54 PM PDT 24
Finished Jul 31 05:00:56 PM PDT 24
Peak memory 208380 kb
Host smart-47836db4-ee43-4136-b392-01625aeb2ef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786327042 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2786327042
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.586724756
Short name T545
Test name
Test status
Simulation time 83440267 ps
CPU time 0.97 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:42 PM PDT 24
Peak memory 199024 kb
Host smart-7f9fc116-e035-4f32-a916-af954500f627
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586724756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.586724756
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.395805758
Short name T550
Test name
Test status
Simulation time 132702413 ps
CPU time 1.08 seconds
Started Jul 31 05:00:43 PM PDT 24
Finished Jul 31 05:00:44 PM PDT 24
Peak memory 200032 kb
Host smart-e71ba288-4f5c-4e8c-9d8b-6f1772978426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395805758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.395805758
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3714628640
Short name T588
Test name
Test status
Simulation time 262331827 ps
CPU time 1.89 seconds
Started Jul 31 05:02:06 PM PDT 24
Finished Jul 31 05:02:08 PM PDT 24
Peak memory 208144 kb
Host smart-7a4c4846-05a5-4e24-9a3e-d602a7bb5ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714628640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3714628640
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3819619475
Short name T616
Test name
Test status
Simulation time 422126266 ps
CPU time 1.68 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:02:02 PM PDT 24
Peak memory 200000 kb
Host smart-af2da7ad-d5c3-456d-a9dd-5c9e281d2ebc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819619475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3819619475
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1667582948
Short name T584
Test name
Test status
Simulation time 168525175 ps
CPU time 1.45 seconds
Started Jul 31 05:00:55 PM PDT 24
Finished Jul 31 05:00:56 PM PDT 24
Peak memory 208296 kb
Host smart-6c7fafa1-5b9c-40e9-9004-d6c32c7b922f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667582948 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1667582948
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1867022637
Short name T592
Test name
Test status
Simulation time 73206725 ps
CPU time 0.78 seconds
Started Jul 31 05:01:00 PM PDT 24
Finished Jul 31 05:01:01 PM PDT 24
Peak memory 199924 kb
Host smart-4f982e69-4b46-4660-aecb-7a0cad6c0d92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867022637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1867022637
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3886762092
Short name T113
Test name
Test status
Simulation time 231692372 ps
CPU time 1.59 seconds
Started Jul 31 05:01:11 PM PDT 24
Finished Jul 31 05:01:13 PM PDT 24
Peak memory 200072 kb
Host smart-5a557969-8850-484c-9d8b-46ce0ca3bf87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886762092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3886762092
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.923750339
Short name T66
Test name
Test status
Simulation time 230314732 ps
CPU time 1.51 seconds
Started Jul 31 05:00:41 PM PDT 24
Finished Jul 31 05:00:43 PM PDT 24
Peak memory 199840 kb
Host smart-c010d797-7655-4819-827c-90dd935961f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923750339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.923750339
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.991562509
Short name T93
Test name
Test status
Simulation time 472203130 ps
CPU time 1.92 seconds
Started Jul 31 05:01:08 PM PDT 24
Finished Jul 31 05:01:11 PM PDT 24
Peak memory 200112 kb
Host smart-1fa06e51-f485-456a-a467-0e3bae17342a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991562509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
991562509
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2943424462
Short name T393
Test name
Test status
Simulation time 76871319 ps
CPU time 0.84 seconds
Started Jul 31 05:19:40 PM PDT 24
Finished Jul 31 05:19:41 PM PDT 24
Peak memory 200180 kb
Host smart-f0648446-882f-491b-8498-13888b32aeed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943424462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2943424462
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.463095211
Short name T226
Test name
Test status
Simulation time 1890494434 ps
CPU time 6.97 seconds
Started Jul 31 05:19:37 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 217672 kb
Host smart-53e67664-5945-4a4f-8a90-c6dff34587dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463095211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.463095211
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3996761113
Short name T188
Test name
Test status
Simulation time 244111263 ps
CPU time 1.14 seconds
Started Jul 31 05:19:41 PM PDT 24
Finished Jul 31 05:19:42 PM PDT 24
Peak memory 217476 kb
Host smart-3e7e5868-5d84-4ebf-b4f8-dfff15f8a385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996761113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3996761113
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3982725811
Short name T213
Test name
Test status
Simulation time 77078608 ps
CPU time 0.7 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:50 PM PDT 24
Peak memory 200116 kb
Host smart-522b7b5a-5bfd-49ee-a4a2-ae94ef42c2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982725811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3982725811
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2880513097
Short name T196
Test name
Test status
Simulation time 1512043792 ps
CPU time 6.33 seconds
Started Jul 31 05:19:41 PM PDT 24
Finished Jul 31 05:19:47 PM PDT 24
Peak memory 200536 kb
Host smart-babfbf00-1e79-4fcd-8bb2-5af4043d003f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880513097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2880513097
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.666955905
Short name T320
Test name
Test status
Simulation time 254910156 ps
CPU time 1.56 seconds
Started Jul 31 05:19:41 PM PDT 24
Finished Jul 31 05:19:43 PM PDT 24
Peak memory 200460 kb
Host smart-addc2430-d2d8-48dc-a464-b5e1679dba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666955905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.666955905
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.388854684
Short name T242
Test name
Test status
Simulation time 266077652 ps
CPU time 1.95 seconds
Started Jul 31 05:19:38 PM PDT 24
Finished Jul 31 05:19:40 PM PDT 24
Peak memory 200296 kb
Host smart-2692fc13-53f7-48a8-b910-87d56754bd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388854684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.388854684
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1118369017
Short name T298
Test name
Test status
Simulation time 196037491 ps
CPU time 1.2 seconds
Started Jul 31 05:19:37 PM PDT 24
Finished Jul 31 05:19:38 PM PDT 24
Peak memory 200280 kb
Host smart-2e366608-ba2b-43be-adcc-6fc23f8c1de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118369017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1118369017
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1816103645
Short name T246
Test name
Test status
Simulation time 55856305 ps
CPU time 0.73 seconds
Started Jul 31 05:19:37 PM PDT 24
Finished Jul 31 05:19:38 PM PDT 24
Peak memory 200164 kb
Host smart-28a8027e-6d27-4799-8647-32c047e222fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816103645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1816103645
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1908742964
Short name T346
Test name
Test status
Simulation time 2173080912 ps
CPU time 8.3 seconds
Started Jul 31 05:19:32 PM PDT 24
Finished Jul 31 05:19:41 PM PDT 24
Peak memory 221656 kb
Host smart-baf97414-fe7e-4135-9ffe-2459fdcb6752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908742964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1908742964
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2479726369
Short name T291
Test name
Test status
Simulation time 244448912 ps
CPU time 1.1 seconds
Started Jul 31 05:19:38 PM PDT 24
Finished Jul 31 05:19:39 PM PDT 24
Peak memory 217512 kb
Host smart-10b7a5b2-3ebe-4240-a283-7f0c5609559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479726369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2479726369
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.31910501
Short name T256
Test name
Test status
Simulation time 198947111 ps
CPU time 0.91 seconds
Started Jul 31 05:19:30 PM PDT 24
Finished Jul 31 05:19:31 PM PDT 24
Peak memory 200080 kb
Host smart-951c8431-5479-489c-a1a5-721af8dda9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31910501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.31910501
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1033665658
Short name T270
Test name
Test status
Simulation time 865573280 ps
CPU time 4.66 seconds
Started Jul 31 05:19:40 PM PDT 24
Finished Jul 31 05:19:45 PM PDT 24
Peak memory 200484 kb
Host smart-13f08fcb-5925-491b-902b-a4a13836cc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033665658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1033665658
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.4074819857
Short name T68
Test name
Test status
Simulation time 8295648701 ps
CPU time 16.97 seconds
Started Jul 31 05:19:30 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 217252 kb
Host smart-28cd73b6-7ab7-43be-a7e6-4cd5b2768fe1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074819857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4074819857
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3951542740
Short name T337
Test name
Test status
Simulation time 152073051 ps
CPU time 1.1 seconds
Started Jul 31 05:19:45 PM PDT 24
Finished Jul 31 05:19:46 PM PDT 24
Peak memory 200324 kb
Host smart-326b150c-ad6e-49e2-a7d1-3033d9210d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951542740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3951542740
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2822532014
Short name T172
Test name
Test status
Simulation time 125781715 ps
CPU time 1.17 seconds
Started Jul 31 05:19:45 PM PDT 24
Finished Jul 31 05:19:46 PM PDT 24
Peak memory 200472 kb
Host smart-2f6a02a7-fedb-4c1f-af77-27ec7794bef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822532014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2822532014
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3584802102
Short name T216
Test name
Test status
Simulation time 9583640661 ps
CPU time 33.13 seconds
Started Jul 31 05:19:27 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 208812 kb
Host smart-a6a9598c-ed86-4a59-9338-e9d2e6603a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584802102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3584802102
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2801504902
Short name T233
Test name
Test status
Simulation time 440067812 ps
CPU time 2.55 seconds
Started Jul 31 05:19:30 PM PDT 24
Finished Jul 31 05:19:33 PM PDT 24
Peak memory 200300 kb
Host smart-0720dcc9-c06e-4058-86d4-fc79141fb045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801504902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2801504902
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1243826457
Short name T409
Test name
Test status
Simulation time 84113537 ps
CPU time 0.86 seconds
Started Jul 31 05:19:44 PM PDT 24
Finished Jul 31 05:19:45 PM PDT 24
Peak memory 200372 kb
Host smart-f998a2fc-2848-4c8a-936a-3d78f3391a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243826457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1243826457
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2171740674
Short name T520
Test name
Test status
Simulation time 85954623 ps
CPU time 0.85 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:50 PM PDT 24
Peak memory 200172 kb
Host smart-34e2c647-ff92-4147-bc72-83f545938414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171740674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2171740674
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1580629634
Short name T42
Test name
Test status
Simulation time 1233378473 ps
CPU time 5.62 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:20:01 PM PDT 24
Peak memory 217480 kb
Host smart-7a3bc20d-9af6-402c-b91b-31f055c22f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580629634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1580629634
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.961437106
Short name T453
Test name
Test status
Simulation time 246959417 ps
CPU time 1.07 seconds
Started Jul 31 05:20:09 PM PDT 24
Finished Jul 31 05:20:16 PM PDT 24
Peak memory 217492 kb
Host smart-c3770c3a-17c1-428a-9c65-7d8574e14ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961437106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.961437106
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1215308559
Short name T521
Test name
Test status
Simulation time 96690456 ps
CPU time 0.75 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 200108 kb
Host smart-3c287539-1146-442b-8a53-73a4cbab9512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215308559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1215308559
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3893191717
Short name T537
Test name
Test status
Simulation time 1788497673 ps
CPU time 5.89 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 200476 kb
Host smart-1a51446b-68d6-4f89-990a-3b95dffd5967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893191717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3893191717
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3153175467
Short name T314
Test name
Test status
Simulation time 108235084 ps
CPU time 0.95 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 200276 kb
Host smart-6960d0ad-eec7-4328-b03e-276a031d881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153175467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3153175467
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1326233520
Short name T405
Test name
Test status
Simulation time 206237961 ps
CPU time 1.35 seconds
Started Jul 31 05:19:53 PM PDT 24
Finished Jul 31 05:19:54 PM PDT 24
Peak memory 200536 kb
Host smart-8d0c073a-c2e8-4cbe-80ef-122b6f97b7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326233520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1326233520
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1552908492
Short name T100
Test name
Test status
Simulation time 2656668545 ps
CPU time 12.05 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:20:08 PM PDT 24
Peak memory 200544 kb
Host smart-6b49d45d-80bb-415c-9fd4-324a9171ec8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552908492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1552908492
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1518977993
Short name T170
Test name
Test status
Simulation time 533044844 ps
CPU time 2.78 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 200232 kb
Host smart-d906a87a-2364-4e39-93c9-48a81a2a5072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518977993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1518977993
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.4150593102
Short name T203
Test name
Test status
Simulation time 201696776 ps
CPU time 1.33 seconds
Started Jul 31 05:19:48 PM PDT 24
Finished Jul 31 05:19:49 PM PDT 24
Peak memory 200352 kb
Host smart-6b9f5e59-e53d-4e7f-bae6-a33ee1c1b886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150593102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.4150593102
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1215096845
Short name T292
Test name
Test status
Simulation time 69204960 ps
CPU time 0.78 seconds
Started Jul 31 05:19:47 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 200184 kb
Host smart-b1618a7f-af68-4521-8bfc-8bd2828b36e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215096845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1215096845
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1879686444
Short name T542
Test name
Test status
Simulation time 1231958803 ps
CPU time 5.63 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 216744 kb
Host smart-b8264d30-ec8d-442c-9ec8-9013e32c02d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879686444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1879686444
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1393285531
Short name T219
Test name
Test status
Simulation time 244999342 ps
CPU time 1.07 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 217472 kb
Host smart-fa3b95c8-1910-4af0-8cf5-db916a607afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393285531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1393285531
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.4267425534
Short name T159
Test name
Test status
Simulation time 122857407 ps
CPU time 0.78 seconds
Started Jul 31 05:19:45 PM PDT 24
Finished Jul 31 05:19:46 PM PDT 24
Peak memory 200076 kb
Host smart-9a258276-69b0-49a5-97d9-73c788b91c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267425534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.4267425534
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.323876304
Short name T383
Test name
Test status
Simulation time 1052655259 ps
CPU time 5.06 seconds
Started Jul 31 05:19:47 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 200468 kb
Host smart-d09b9b72-d77b-4e1e-a697-79c83de9369c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323876304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.323876304
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.560521080
Short name T463
Test name
Test status
Simulation time 150288548 ps
CPU time 1.08 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 200348 kb
Host smart-3f744c70-7756-4da0-b8be-ea173873c038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560521080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.560521080
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1008254942
Short name T62
Test name
Test status
Simulation time 114240334 ps
CPU time 1.17 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:05 PM PDT 24
Peak memory 200464 kb
Host smart-66b97e08-3f12-44f0-bd52-ee561ea977bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008254942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1008254942
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2125999214
Short name T206
Test name
Test status
Simulation time 3850014408 ps
CPU time 14.07 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:20:05 PM PDT 24
Peak memory 208820 kb
Host smart-68200a97-5139-42c4-a6c3-e8812c176949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125999214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2125999214
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.520090297
Short name T340
Test name
Test status
Simulation time 403538772 ps
CPU time 2.09 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:51 PM PDT 24
Peak memory 208380 kb
Host smart-ea1be3be-9b54-4549-874d-1f647c254ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520090297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.520090297
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.680064465
Short name T11
Test name
Test status
Simulation time 140032162 ps
CPU time 1.16 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:54 PM PDT 24
Peak memory 200492 kb
Host smart-3a27ca68-a83b-40c0-b973-6af1549278ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680064465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.680064465
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.333416071
Short name T286
Test name
Test status
Simulation time 59772923 ps
CPU time 0.72 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200148 kb
Host smart-dc0b8868-6c95-4175-bde3-ea37bae9db38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333416071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.333416071
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3408130391
Short name T321
Test name
Test status
Simulation time 1237210992 ps
CPU time 5.64 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 221612 kb
Host smart-45807efa-b498-4e73-917e-0070d2a86330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408130391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3408130391
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3734237890
Short name T139
Test name
Test status
Simulation time 243989051 ps
CPU time 1.02 seconds
Started Jul 31 05:19:50 PM PDT 24
Finished Jul 31 05:19:51 PM PDT 24
Peak memory 217504 kb
Host smart-b292c43f-503b-435a-9cfb-ed0776980a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734237890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3734237890
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_reset.766864665
Short name T50
Test name
Test status
Simulation time 828152863 ps
CPU time 4.46 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 200492 kb
Host smart-2d65ad13-2430-4632-ae01-556a48c4ec9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766864665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.766864665
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2514969251
Short name T38
Test name
Test status
Simulation time 101365886 ps
CPU time 1.05 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 200368 kb
Host smart-29c33890-2b1a-4ba1-9878-04a08cd2f6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514969251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2514969251
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2124999381
Short name T214
Test name
Test status
Simulation time 262825732 ps
CPU time 1.42 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:50 PM PDT 24
Peak memory 200472 kb
Host smart-3afd9dbf-ed57-43dc-af1b-0ea4fa80c870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124999381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2124999381
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2738975429
Short name T238
Test name
Test status
Simulation time 9307148957 ps
CPU time 34.81 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:35 PM PDT 24
Peak memory 208788 kb
Host smart-f483e7f2-a751-475b-a4d2-24ece00d5e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738975429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2738975429
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2006005121
Short name T376
Test name
Test status
Simulation time 131915073 ps
CPU time 1.57 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:51 PM PDT 24
Peak memory 208476 kb
Host smart-9738fe2d-b3a2-4479-b7c4-4ba6e05c7e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006005121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2006005121
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1016349865
Short name T455
Test name
Test status
Simulation time 277039452 ps
CPU time 1.47 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 200560 kb
Host smart-64e7153b-dd23-4032-8409-5706193b2e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016349865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1016349865
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.971785259
Short name T457
Test name
Test status
Simulation time 57325706 ps
CPU time 0.74 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200096 kb
Host smart-c98f4891-fa80-43b6-89f7-6113c3280ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971785259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.971785259
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1933356197
Short name T297
Test name
Test status
Simulation time 1227212971 ps
CPU time 5.26 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:20:04 PM PDT 24
Peak memory 217404 kb
Host smart-4d5fb722-9989-4b6c-95a2-fa5f789d3445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933356197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1933356197
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1086364075
Short name T515
Test name
Test status
Simulation time 243833990 ps
CPU time 1.13 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 217412 kb
Host smart-72e514fa-16b4-41b7-86e9-546053ab370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086364075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1086364075
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2618389251
Short name T171
Test name
Test status
Simulation time 219067575 ps
CPU time 0.9 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:51 PM PDT 24
Peak memory 200156 kb
Host smart-8c608825-9b0d-43fa-a565-8d87d40da81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618389251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2618389251
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.114031977
Short name T334
Test name
Test status
Simulation time 1104740388 ps
CPU time 5.02 seconds
Started Jul 31 05:20:10 PM PDT 24
Finished Jul 31 05:20:15 PM PDT 24
Peak memory 200536 kb
Host smart-3e31c7a8-6b94-46a0-8999-49f46625178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114031977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.114031977
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.758233355
Short name T241
Test name
Test status
Simulation time 174074430 ps
CPU time 1.17 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:51 PM PDT 24
Peak memory 200332 kb
Host smart-b876d61c-891d-47d9-aa06-01a6eb542ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758233355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.758233355
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3721016534
Short name T479
Test name
Test status
Simulation time 187913127 ps
CPU time 1.3 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:51 PM PDT 24
Peak memory 200448 kb
Host smart-0e504393-5b24-4645-a0ef-c41041f44c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721016534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3721016534
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1401416002
Short name T239
Test name
Test status
Simulation time 1116588696 ps
CPU time 5.15 seconds
Started Jul 31 05:20:09 PM PDT 24
Finished Jul 31 05:20:14 PM PDT 24
Peak memory 200528 kb
Host smart-32c54b7e-de18-4e2a-a3e3-da6f8cc885bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401416002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1401416002
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3437516325
Short name T541
Test name
Test status
Simulation time 126368562 ps
CPU time 1.7 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 208508 kb
Host smart-2f443f19-6fc8-49b9-83be-dcafb8e19148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437516325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3437516325
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1262800645
Short name T150
Test name
Test status
Simulation time 119496624 ps
CPU time 1.05 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 200236 kb
Host smart-3557e089-02ed-48b4-8581-9ef11a5f8794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262800645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1262800645
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.316949667
Short name T145
Test name
Test status
Simulation time 81909152 ps
CPU time 0.83 seconds
Started Jul 31 05:20:20 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 200088 kb
Host smart-acc4b622-8eda-4db9-8bc0-a65f4469edb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316949667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.316949667
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.444309427
Short name T266
Test name
Test status
Simulation time 1878961277 ps
CPU time 6.81 seconds
Started Jul 31 05:19:43 PM PDT 24
Finished Jul 31 05:19:50 PM PDT 24
Peak memory 217744 kb
Host smart-16666ca5-b69f-4b2a-b773-babc7783aa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444309427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.444309427
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3585907293
Short name T528
Test name
Test status
Simulation time 244487624 ps
CPU time 1.09 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 217516 kb
Host smart-cbbedd20-5e38-4368-9f80-109c6a5e3824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585907293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3585907293
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1677798194
Short name T181
Test name
Test status
Simulation time 173855929 ps
CPU time 0.85 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 200040 kb
Host smart-a48da8c3-fa46-4746-abc6-f4ae87ade800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677798194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1677798194
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2578045421
Short name T329
Test name
Test status
Simulation time 1109166022 ps
CPU time 5.24 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:54 PM PDT 24
Peak memory 200576 kb
Host smart-627f618d-97ec-4212-aadc-1f4b174c74d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578045421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2578045421
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3096270027
Short name T421
Test name
Test status
Simulation time 109956945 ps
CPU time 1.06 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200340 kb
Host smart-e1ca3b7e-d234-43f1-9f3f-8baec0e8bb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096270027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3096270027
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3325593600
Short name T168
Test name
Test status
Simulation time 224317307 ps
CPU time 1.48 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200536 kb
Host smart-14e9b5cb-3ede-48eb-b2cf-423b1c1042bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325593600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3325593600
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.586129919
Short name T417
Test name
Test status
Simulation time 1911455673 ps
CPU time 7.45 seconds
Started Jul 31 05:19:50 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 208724 kb
Host smart-6d1a9dce-1a78-4b33-960b-51619a6aaabe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586129919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.586129919
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.518056901
Short name T163
Test name
Test status
Simulation time 447702853 ps
CPU time 2.64 seconds
Started Jul 31 05:19:48 PM PDT 24
Finished Jul 31 05:19:51 PM PDT 24
Peak memory 200272 kb
Host smart-3fb9427c-63f8-464e-8af7-7011520c8eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518056901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.518056901
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.80266183
Short name T209
Test name
Test status
Simulation time 112203359 ps
CPU time 0.97 seconds
Started Jul 31 05:19:48 PM PDT 24
Finished Jul 31 05:19:49 PM PDT 24
Peak memory 200280 kb
Host smart-4eef70b5-4610-4002-aeb6-144f129e13a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80266183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.80266183
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.319328270
Short name T302
Test name
Test status
Simulation time 66777950 ps
CPU time 0.76 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 200144 kb
Host smart-3988f6e8-67c9-464c-954d-e6596ee651af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319328270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.319328270
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.892363816
Short name T399
Test name
Test status
Simulation time 1886087587 ps
CPU time 6.69 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 221292 kb
Host smart-946f0a6a-6b39-49a0-8bbe-6510a2053aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892363816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.892363816
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2450066353
Short name T254
Test name
Test status
Simulation time 243664190 ps
CPU time 1.02 seconds
Started Jul 31 05:20:06 PM PDT 24
Finished Jul 31 05:20:07 PM PDT 24
Peak memory 217532 kb
Host smart-775015a9-4436-45be-a27f-7da164acd805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450066353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2450066353
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3537865399
Short name T478
Test name
Test status
Simulation time 160956218 ps
CPU time 0.9 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 200036 kb
Host smart-edd36f60-010d-4ee1-9a31-6c64c3669398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537865399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3537865399
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3234515059
Short name T368
Test name
Test status
Simulation time 2089795800 ps
CPU time 8.06 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200568 kb
Host smart-64e75a1b-e40a-490d-885a-ba7ead912974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234515059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3234515059
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.844500555
Short name T138
Test name
Test status
Simulation time 104329210 ps
CPU time 1.04 seconds
Started Jul 31 05:20:16 PM PDT 24
Finished Jul 31 05:20:17 PM PDT 24
Peak memory 200328 kb
Host smart-dbf78a50-b862-4b3f-9e38-e4ee7835a1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844500555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.844500555
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1171286125
Short name T63
Test name
Test status
Simulation time 226166732 ps
CPU time 1.51 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200436 kb
Host smart-4b2c567b-08a4-49d2-b256-3f71739573bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171286125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1171286125
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1601512566
Short name T268
Test name
Test status
Simulation time 12324372934 ps
CPU time 39.59 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:20:34 PM PDT 24
Peak memory 208776 kb
Host smart-d7c6a2f6-e72e-4111-88fe-d45aaec17a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601512566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1601512566
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.568207255
Short name T279
Test name
Test status
Simulation time 382453162 ps
CPU time 2.3 seconds
Started Jul 31 05:19:53 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 200244 kb
Host smart-8e34338e-2d62-4293-8db9-02aec1294e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568207255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.568207255
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2807242480
Short name T230
Test name
Test status
Simulation time 168120716 ps
CPU time 1.21 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:20:04 PM PDT 24
Peak memory 200436 kb
Host smart-e77bb313-7ceb-41ba-b259-40b51b108f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807242480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2807242480
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1602650559
Short name T147
Test name
Test status
Simulation time 73652583 ps
CPU time 0.75 seconds
Started Jul 31 05:20:04 PM PDT 24
Finished Jul 31 05:20:05 PM PDT 24
Peak memory 200140 kb
Host smart-e7365406-4469-4986-8823-d597fb4705c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602650559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1602650559
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1229170216
Short name T497
Test name
Test status
Simulation time 244481522 ps
CPU time 1.1 seconds
Started Jul 31 05:19:53 PM PDT 24
Finished Jul 31 05:19:54 PM PDT 24
Peak memory 217540 kb
Host smart-60ff9046-70f0-4b54-a368-26ce60361621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229170216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1229170216
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1425087302
Short name T18
Test name
Test status
Simulation time 123161792 ps
CPU time 0.81 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200096 kb
Host smart-b8e28138-e09e-4e6a-b366-fe6f71015ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425087302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1425087302
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2794111749
Short name T104
Test name
Test status
Simulation time 1937085249 ps
CPU time 7.4 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:20:05 PM PDT 24
Peak memory 200500 kb
Host smart-13cd447f-2a71-4d59-accd-88769db88e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794111749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2794111749
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3387497184
Short name T385
Test name
Test status
Simulation time 97821730 ps
CPU time 0.97 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200496 kb
Host smart-e4ddc94a-d565-4f39-8f53-71bca304172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387497184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3387497184
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3753566433
Short name T440
Test name
Test status
Simulation time 255443818 ps
CPU time 1.5 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 200524 kb
Host smart-8bac740d-e8be-4760-8235-1f68bc3f5156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753566433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3753566433
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1161850779
Short name T102
Test name
Test status
Simulation time 7046179872 ps
CPU time 23.14 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:20:18 PM PDT 24
Peak memory 210076 kb
Host smart-bbe24b8b-be6f-40b3-9155-dd493a618d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161850779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1161850779
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2417224890
Short name T407
Test name
Test status
Simulation time 338869083 ps
CPU time 2.13 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 208504 kb
Host smart-7a9d35b7-4b2b-4c71-9e87-cb8bc7566bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417224890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2417224890
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.576954141
Short name T155
Test name
Test status
Simulation time 272034029 ps
CPU time 1.61 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200328 kb
Host smart-a4823b22-3c2f-4b04-879b-9c95e3b88114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576954141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.576954141
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.399207349
Short name T267
Test name
Test status
Simulation time 56772034 ps
CPU time 0.72 seconds
Started Jul 31 05:19:47 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 200124 kb
Host smart-1dfc2b91-9292-4a9c-973f-c1f2f8050e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399207349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.399207349
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1380276088
Short name T387
Test name
Test status
Simulation time 2367431213 ps
CPU time 7.95 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:20:05 PM PDT 24
Peak memory 221796 kb
Host smart-679c39ae-6891-4bd4-9e8b-f059fc505d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380276088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1380276088
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3203169168
Short name T534
Test name
Test status
Simulation time 244362557 ps
CPU time 1.07 seconds
Started Jul 31 05:20:09 PM PDT 24
Finished Jul 31 05:20:10 PM PDT 24
Peak memory 217468 kb
Host smart-e8442d00-94ba-4306-9349-487fee831104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203169168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3203169168
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3392240636
Short name T525
Test name
Test status
Simulation time 138330071 ps
CPU time 0.81 seconds
Started Jul 31 05:19:42 PM PDT 24
Finished Jul 31 05:19:43 PM PDT 24
Peak memory 199864 kb
Host smart-9018c0e8-e9c7-46c5-b135-340100e50b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392240636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3392240636
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.4037671704
Short name T194
Test name
Test status
Simulation time 789043597 ps
CPU time 3.94 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:20:01 PM PDT 24
Peak memory 200568 kb
Host smart-29ae69e6-40ec-47aa-882f-c8280eff66d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037671704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.4037671704
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1710205717
Short name T430
Test name
Test status
Simulation time 94146563 ps
CPU time 0.97 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200292 kb
Host smart-7671f702-e40f-4e94-a2fe-82f9a5ec7919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710205717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1710205717
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3596165997
Short name T312
Test name
Test status
Simulation time 124109708 ps
CPU time 1.22 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200636 kb
Host smart-4b438670-7894-4bd4-804c-ad568b369966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596165997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3596165997
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.931248770
Short name T428
Test name
Test status
Simulation time 1851339491 ps
CPU time 9.52 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 208760 kb
Host smart-3f39757c-aedb-418c-9b5b-4c1e6d71d8e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931248770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.931248770
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.575909756
Short name T183
Test name
Test status
Simulation time 307982869 ps
CPU time 1.94 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 208476 kb
Host smart-d51c1018-5d6a-4373-bf0c-9634615c6c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575909756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.575909756
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.152101241
Short name T441
Test name
Test status
Simulation time 169407457 ps
CPU time 1.24 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 200468 kb
Host smart-b0f8e725-bc4f-4c50-9f70-0eeca251da90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152101241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.152101241
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3456691196
Short name T243
Test name
Test status
Simulation time 62497280 ps
CPU time 0.72 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 200156 kb
Host smart-22c8cbee-c24c-4519-9cd1-1f7dfa85edc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456691196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3456691196
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3909061715
Short name T43
Test name
Test status
Simulation time 2159623238 ps
CPU time 8.06 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:11 PM PDT 24
Peak memory 217600 kb
Host smart-e35327f4-cfed-4ffb-be66-2f21ddcfd6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909061715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3909061715
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2561714173
Short name T156
Test name
Test status
Simulation time 245491281 ps
CPU time 1.04 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 217420 kb
Host smart-ea84118c-5fa8-497f-a23a-88e175a3e438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561714173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2561714173
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.181678268
Short name T392
Test name
Test status
Simulation time 109073041 ps
CPU time 0.76 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200080 kb
Host smart-826948a5-f3f0-4c63-8a85-0e48600896db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181678268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.181678268
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2550120680
Short name T481
Test name
Test status
Simulation time 840121605 ps
CPU time 4.24 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 200596 kb
Host smart-59149fd8-6896-4157-bfa4-4ed440359919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550120680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2550120680
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3453637354
Short name T388
Test name
Test status
Simulation time 170618148 ps
CPU time 1.1 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200336 kb
Host smart-e4c3f644-7d67-4189-8abc-f3dcebc778eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453637354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3453637354
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2912818033
Short name T425
Test name
Test status
Simulation time 119319632 ps
CPU time 1.14 seconds
Started Jul 31 05:19:59 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 200452 kb
Host smart-72692cd5-4669-432e-bfab-9e3dcd3d3a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912818033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2912818033
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2269442573
Short name T379
Test name
Test status
Simulation time 7757808800 ps
CPU time 31.21 seconds
Started Jul 31 05:19:46 PM PDT 24
Finished Jul 31 05:20:17 PM PDT 24
Peak memory 216724 kb
Host smart-50d723e8-41cb-4bb5-927f-a5f595633ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269442573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2269442573
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2952144054
Short name T74
Test name
Test status
Simulation time 414122662 ps
CPU time 2.14 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 208476 kb
Host smart-9bc4c28f-bb0c-4473-960a-e72ddd2a6feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952144054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2952144054
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1801765632
Short name T316
Test name
Test status
Simulation time 144284354 ps
CPU time 1.16 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 200364 kb
Host smart-0052562b-5414-47eb-b139-e435fa1f9182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801765632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1801765632
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3310799662
Short name T299
Test name
Test status
Simulation time 53745734 ps
CPU time 0.72 seconds
Started Jul 31 05:20:18 PM PDT 24
Finished Jul 31 05:20:19 PM PDT 24
Peak memory 200200 kb
Host smart-2c16c1c8-6e28-43c4-9530-1cc2a1bd9152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310799662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3310799662
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2025804076
Short name T391
Test name
Test status
Simulation time 244693796 ps
CPU time 1.05 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:50 PM PDT 24
Peak memory 217476 kb
Host smart-3d84f94d-a2b3-4f0e-b113-66447ee0121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025804076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2025804076
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2530755561
Short name T427
Test name
Test status
Simulation time 149582435 ps
CPU time 0.82 seconds
Started Jul 31 05:19:59 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 200140 kb
Host smart-b3d96b49-ba75-42a1-b59d-2ebecd315c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530755561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2530755561
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2449097685
Short name T107
Test name
Test status
Simulation time 974546622 ps
CPU time 4.86 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 200544 kb
Host smart-639e4d70-ba3c-407e-b7c9-01fb1961c63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449097685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2449097685
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3497383336
Short name T235
Test name
Test status
Simulation time 157492134 ps
CPU time 1.07 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 200396 kb
Host smart-8436e75f-c6f0-44fe-b5a6-2311073942b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497383336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3497383336
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.4108415090
Short name T218
Test name
Test status
Simulation time 214285310 ps
CPU time 1.4 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200484 kb
Host smart-3df8f99a-b035-4cdf-af0c-6b9f7835a0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108415090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.4108415090
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2727213266
Short name T350
Test name
Test status
Simulation time 546118882 ps
CPU time 2.57 seconds
Started Jul 31 05:20:16 PM PDT 24
Finished Jul 31 05:20:19 PM PDT 24
Peak memory 200532 kb
Host smart-6e9f845f-163c-48f7-b996-09a34bded75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727213266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2727213266
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3339319151
Short name T289
Test name
Test status
Simulation time 141025959 ps
CPU time 1.79 seconds
Started Jul 31 05:20:24 PM PDT 24
Finished Jul 31 05:20:26 PM PDT 24
Peak memory 200280 kb
Host smart-e62fdf6d-f8f0-456d-acbc-4aaddfbb96fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339319151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3339319151
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1256063352
Short name T438
Test name
Test status
Simulation time 96480649 ps
CPU time 0.81 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 200344 kb
Host smart-ffd1fb98-16fd-47d1-8847-b7c69860f247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256063352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1256063352
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1811937292
Short name T44
Test name
Test status
Simulation time 1219591473 ps
CPU time 5.34 seconds
Started Jul 31 05:19:36 PM PDT 24
Finished Jul 31 05:19:42 PM PDT 24
Peak memory 217688 kb
Host smart-02f9f3e9-ba92-4f1e-8aae-da2cdbaf27c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811937292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1811937292
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1323949215
Short name T143
Test name
Test status
Simulation time 243497686 ps
CPU time 1.08 seconds
Started Jul 31 05:19:45 PM PDT 24
Finished Jul 31 05:19:47 PM PDT 24
Peak memory 217488 kb
Host smart-2d02ca52-0b23-4806-afb2-75a14a28aeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323949215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1323949215
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2587190195
Short name T12
Test name
Test status
Simulation time 197230811 ps
CPU time 0.93 seconds
Started Jul 31 05:19:43 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 200128 kb
Host smart-d01f8119-fcac-4618-aead-d55951a0f0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587190195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2587190195
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3341493765
Short name T487
Test name
Test status
Simulation time 1365953779 ps
CPU time 5.32 seconds
Started Jul 31 05:19:34 PM PDT 24
Finished Jul 31 05:19:39 PM PDT 24
Peak memory 200520 kb
Host smart-4c2fe0e7-3154-4729-b203-20ac21b8fbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341493765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3341493765
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3935929486
Short name T73
Test name
Test status
Simulation time 8294564758 ps
CPU time 14.99 seconds
Started Jul 31 05:19:36 PM PDT 24
Finished Jul 31 05:19:51 PM PDT 24
Peak memory 217300 kb
Host smart-7bc35841-3d8a-45e5-9a55-e368f631d32e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935929486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3935929486
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2325848805
Short name T309
Test name
Test status
Simulation time 183736952 ps
CPU time 1.27 seconds
Started Jul 31 05:19:28 PM PDT 24
Finished Jul 31 05:19:30 PM PDT 24
Peak memory 200316 kb
Host smart-f7e96dfb-8d80-4a7b-9b92-27a468d04532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325848805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2325848805
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1792661675
Short name T510
Test name
Test status
Simulation time 258743947 ps
CPU time 1.41 seconds
Started Jul 31 05:19:25 PM PDT 24
Finished Jul 31 05:19:26 PM PDT 24
Peak memory 200508 kb
Host smart-18a4962e-5f50-4110-808f-8f39a8435f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792661675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1792661675
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3685357396
Short name T307
Test name
Test status
Simulation time 1859968050 ps
CPU time 7.18 seconds
Started Jul 31 05:19:37 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 208732 kb
Host smart-3f26a567-4d97-445b-b93d-170ff2fd898c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685357396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3685357396
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.269767803
Short name T56
Test name
Test status
Simulation time 368233115 ps
CPU time 2.28 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:54 PM PDT 24
Peak memory 200292 kb
Host smart-ef500814-5d1a-4f7f-a924-1528a2ef040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269767803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.269767803
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2673850554
Short name T141
Test name
Test status
Simulation time 93815695 ps
CPU time 0.81 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 200344 kb
Host smart-4c191ec8-8cf7-4b39-bbd9-44ec1f2c9a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673850554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2673850554
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3413944101
Short name T472
Test name
Test status
Simulation time 86274435 ps
CPU time 0.79 seconds
Started Jul 31 05:19:59 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 200176 kb
Host smart-b0904f1c-df90-49d3-a713-577f4c1d21f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413944101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3413944101
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3602963026
Short name T490
Test name
Test status
Simulation time 1902845948 ps
CPU time 6.81 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 217768 kb
Host smart-4d54d1d7-9e86-426a-a0d8-25c3a59b772d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602963026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3602963026
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3215466021
Short name T190
Test name
Test status
Simulation time 244824697 ps
CPU time 1.05 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 217468 kb
Host smart-7e1aace0-2e50-4825-9388-82418623dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215466021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3215466021
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1414440423
Short name T199
Test name
Test status
Simulation time 98523994 ps
CPU time 0.8 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200160 kb
Host smart-0712b477-cbcc-4855-b6ea-095635b298fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414440423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1414440423
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3514429111
Short name T179
Test name
Test status
Simulation time 805575107 ps
CPU time 3.84 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 200492 kb
Host smart-a114d0ce-f1b7-4560-8767-da68d216d543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514429111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3514429111
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4222518483
Short name T275
Test name
Test status
Simulation time 156153382 ps
CPU time 1.16 seconds
Started Jul 31 05:20:04 PM PDT 24
Finished Jul 31 05:20:05 PM PDT 24
Peak memory 200348 kb
Host smart-88492086-cb8c-4582-bd2d-1c6b8a9c4e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222518483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4222518483
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1190946650
Short name T369
Test name
Test status
Simulation time 112402855 ps
CPU time 1.15 seconds
Started Jul 31 05:20:19 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 200492 kb
Host smart-ffcb5dfc-7c15-4e26-9bcb-569821ecf0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190946650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1190946650
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2888850195
Short name T192
Test name
Test status
Simulation time 3652140246 ps
CPU time 17.4 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:20:13 PM PDT 24
Peak memory 208844 kb
Host smart-66bd5a97-1e1c-4db5-a6a0-e85d3857a53e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888850195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2888850195
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2936613047
Short name T134
Test name
Test status
Simulation time 352333148 ps
CPU time 1.95 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 200336 kb
Host smart-6241edf0-d409-4d8b-a159-c833208c2116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936613047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2936613047
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1810740851
Short name T384
Test name
Test status
Simulation time 137692764 ps
CPU time 0.96 seconds
Started Jul 31 05:20:01 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 200364 kb
Host smart-d9c0baf8-621f-451b-98e6-31b75b774c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810740851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1810740851
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2154300310
Short name T305
Test name
Test status
Simulation time 85197630 ps
CPU time 0.79 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 200168 kb
Host smart-f5f98707-d097-461c-bef6-a9a3cb588dd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154300310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2154300310
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1466493156
Short name T451
Test name
Test status
Simulation time 1228906101 ps
CPU time 5.8 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 217704 kb
Host smart-47e6ae3e-bf3d-488f-b39d-a8fafff7a5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466493156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1466493156
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.4266612960
Short name T169
Test name
Test status
Simulation time 244917480 ps
CPU time 1.06 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:04 PM PDT 24
Peak memory 217480 kb
Host smart-6dd6ead3-cbc1-4cc2-aca3-0923230fd0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266612960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.4266612960
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2180963551
Short name T249
Test name
Test status
Simulation time 209703791 ps
CPU time 0.97 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 200204 kb
Host smart-85ffab54-740b-4d12-8578-b8f4bbd869d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180963551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2180963551
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.4039950652
Short name T191
Test name
Test status
Simulation time 1570329543 ps
CPU time 5.92 seconds
Started Jul 31 05:20:02 PM PDT 24
Finished Jul 31 05:20:08 PM PDT 24
Peak memory 200440 kb
Host smart-c3d635d6-5c90-431b-886f-26a6dd292aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039950652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.4039950652
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.501522183
Short name T201
Test name
Test status
Simulation time 152618052 ps
CPU time 1.12 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200348 kb
Host smart-7341ccfa-985e-4546-8174-5d6d90f9b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501522183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.501522183
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.997163198
Short name T544
Test name
Test status
Simulation time 113368370 ps
CPU time 1.16 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200516 kb
Host smart-0e0bf0e3-ecd8-49c4-89b0-390d3fdaa850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997163198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.997163198
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.172615087
Short name T401
Test name
Test status
Simulation time 2956177752 ps
CPU time 10.63 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 208864 kb
Host smart-69124c0c-1228-4e00-abda-07886a11a220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172615087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.172615087
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2925465926
Short name T476
Test name
Test status
Simulation time 343898591 ps
CPU time 2.28 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200292 kb
Host smart-dbd0f637-b534-49f6-8288-a9ce73b313b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925465926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2925465926
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1322534110
Short name T176
Test name
Test status
Simulation time 190746278 ps
CPU time 1.15 seconds
Started Jul 31 05:20:08 PM PDT 24
Finished Jul 31 05:20:09 PM PDT 24
Peak memory 200300 kb
Host smart-f0d715b7-be56-4fe5-8006-eb84de921d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322534110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1322534110
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3690733339
Short name T149
Test name
Test status
Simulation time 66988041 ps
CPU time 0.84 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 200164 kb
Host smart-4da26f86-428e-445a-87ed-887b570d0976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690733339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3690733339
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.4027984215
Short name T524
Test name
Test status
Simulation time 1235697953 ps
CPU time 5.24 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 216804 kb
Host smart-e32df2a7-a6a9-4673-8be0-fa28072e6898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027984215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.4027984215
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2722522657
Short name T464
Test name
Test status
Simulation time 243941772 ps
CPU time 1.05 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 217440 kb
Host smart-862b4753-bf7b-44d5-a6be-848928e91227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722522657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2722522657
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.167427719
Short name T439
Test name
Test status
Simulation time 185736878 ps
CPU time 0.87 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 200160 kb
Host smart-56326e7a-c92b-4b75-9bd4-2b0c646feff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167427719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.167427719
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1395182546
Short name T101
Test name
Test status
Simulation time 1779954959 ps
CPU time 6.09 seconds
Started Jul 31 05:19:50 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 200536 kb
Host smart-2c45efcd-7da4-476e-bfb8-697b8689e9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395182546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1395182546
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3116019220
Short name T469
Test name
Test status
Simulation time 141193483 ps
CPU time 1.07 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 200368 kb
Host smart-2dd9a790-7f7f-41ae-a9dd-a4da6b06dfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116019220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3116019220
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1900979042
Short name T480
Test name
Test status
Simulation time 198996843 ps
CPU time 1.35 seconds
Started Jul 31 05:20:13 PM PDT 24
Finished Jul 31 05:20:15 PM PDT 24
Peak memory 200504 kb
Host smart-77e11f8f-9509-4545-9f0b-60679dd64c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900979042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1900979042
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.4076028092
Short name T437
Test name
Test status
Simulation time 207150098 ps
CPU time 1.32 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 200328 kb
Host smart-a9a113dd-e524-44fa-ae2a-3705297d4677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076028092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.4076028092
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.66043678
Short name T133
Test name
Test status
Simulation time 386357755 ps
CPU time 2.19 seconds
Started Jul 31 05:20:01 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 200280 kb
Host smart-c885ec98-a593-465b-9da1-7f6ae08676d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66043678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.66043678
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2991489867
Short name T217
Test name
Test status
Simulation time 90034061 ps
CPU time 0.88 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 200348 kb
Host smart-1935ef83-fc81-4d12-a432-098b6fca3a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991489867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2991489867
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3918448801
Short name T247
Test name
Test status
Simulation time 75956956 ps
CPU time 0.77 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200140 kb
Host smart-d806001e-d293-4c82-819f-a98891190065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918448801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3918448801
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.4213023197
Short name T448
Test name
Test status
Simulation time 1221206988 ps
CPU time 5.23 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:08 PM PDT 24
Peak memory 220900 kb
Host smart-7bb49843-747a-4702-b093-0be663170638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213023197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.4213023197
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1217995278
Short name T152
Test name
Test status
Simulation time 244314975 ps
CPU time 1.06 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 217528 kb
Host smart-ea878cd7-85c9-4ce5-a166-a2fea355719d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217995278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1217995278
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2835160622
Short name T338
Test name
Test status
Simulation time 102664498 ps
CPU time 0.76 seconds
Started Jul 31 05:20:13 PM PDT 24
Finished Jul 31 05:20:14 PM PDT 24
Peak memory 200108 kb
Host smart-e4e792bc-30a7-46f8-b2d1-97cc0ee68900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835160622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2835160622
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3450715660
Short name T261
Test name
Test status
Simulation time 1395461472 ps
CPU time 5.85 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:20:04 PM PDT 24
Peak memory 200608 kb
Host smart-d343a5c1-7620-4df0-a8d3-dcac582e6db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450715660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3450715660
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1080203776
Short name T146
Test name
Test status
Simulation time 170203377 ps
CPU time 1.13 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200348 kb
Host smart-23b4ddcd-bc78-4aed-b2ca-9ef4e30fb30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080203776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1080203776
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2371706603
Short name T530
Test name
Test status
Simulation time 196370017 ps
CPU time 1.32 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:04 PM PDT 24
Peak memory 200388 kb
Host smart-493ea55c-6cd1-4bdc-9354-c1e41edf5b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371706603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2371706603
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.141139988
Short name T317
Test name
Test status
Simulation time 456457290 ps
CPU time 2.39 seconds
Started Jul 31 05:20:16 PM PDT 24
Finished Jul 31 05:20:19 PM PDT 24
Peak memory 200344 kb
Host smart-b6bf15dc-1b41-468c-ae14-2832aa94b86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141139988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.141139988
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3791948068
Short name T436
Test name
Test status
Simulation time 170273286 ps
CPU time 1.17 seconds
Started Jul 31 05:20:01 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 200328 kb
Host smart-542941f8-82d8-4af6-a999-bf7fd113aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791948068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3791948068
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.648627635
Short name T356
Test name
Test status
Simulation time 74164113 ps
CPU time 0.81 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 200168 kb
Host smart-e4a70c7f-9672-44fa-913b-4fe4689ae857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648627635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.648627635
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1897946950
Short name T55
Test name
Test status
Simulation time 2339707080 ps
CPU time 8.42 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 217184 kb
Host smart-bfb80d37-123c-42a2-a4ae-b517105ded7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897946950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1897946950
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2016875692
Short name T372
Test name
Test status
Simulation time 244370966 ps
CPU time 1.05 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:01 PM PDT 24
Peak memory 217528 kb
Host smart-a8587f4b-9479-4488-9fb9-58e789f39fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016875692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2016875692
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3815682563
Short name T5
Test name
Test status
Simulation time 198607249 ps
CPU time 1.07 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 200132 kb
Host smart-45cc3f42-f0e9-475e-b4b6-128a09807c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815682563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3815682563
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2401135050
Short name T488
Test name
Test status
Simulation time 1629496644 ps
CPU time 6.25 seconds
Started Jul 31 05:20:17 PM PDT 24
Finished Jul 31 05:20:23 PM PDT 24
Peak memory 200508 kb
Host smart-feb94b94-124c-43db-bfb3-33b23810d8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401135050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2401135050
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1385050163
Short name T6
Test name
Test status
Simulation time 175081382 ps
CPU time 1.2 seconds
Started Jul 31 05:20:17 PM PDT 24
Finished Jul 31 05:20:18 PM PDT 24
Peak memory 200308 kb
Host smart-565fba6b-5c16-4414-a661-d4880c9bbd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385050163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1385050163
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.46655763
Short name T498
Test name
Test status
Simulation time 244650640 ps
CPU time 1.5 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200248 kb
Host smart-eac9ce12-c9e0-4833-b739-de503937c4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46655763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.46655763
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3025247443
Short name T253
Test name
Test status
Simulation time 3724233854 ps
CPU time 12.43 seconds
Started Jul 31 05:19:59 PM PDT 24
Finished Jul 31 05:20:12 PM PDT 24
Peak memory 200664 kb
Host smart-4666ca8e-deda-420e-8c18-ebe62c4d20e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025247443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3025247443
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2423500735
Short name T205
Test name
Test status
Simulation time 268148052 ps
CPU time 1.84 seconds
Started Jul 31 05:20:10 PM PDT 24
Finished Jul 31 05:20:12 PM PDT 24
Peak memory 200260 kb
Host smart-212341c4-8386-422d-8c31-e6dedbc8cfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423500735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2423500735
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3988612575
Short name T458
Test name
Test status
Simulation time 218734469 ps
CPU time 1.29 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200336 kb
Host smart-e15ff4a3-8113-4432-8129-af4f7336ce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988612575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3988612575
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2623598127
Short name T258
Test name
Test status
Simulation time 71121611 ps
CPU time 0.79 seconds
Started Jul 31 05:20:07 PM PDT 24
Finished Jul 31 05:20:08 PM PDT 24
Peak memory 200168 kb
Host smart-146f2ec5-a184-4a41-bf6d-7b7d55254ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623598127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2623598127
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.316536281
Short name T32
Test name
Test status
Simulation time 2178832429 ps
CPU time 7.45 seconds
Started Jul 31 05:20:06 PM PDT 24
Finished Jul 31 05:20:14 PM PDT 24
Peak memory 217352 kb
Host smart-c19d9511-cdfe-461d-beb1-ce9fb0970898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316536281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.316536281
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2315212246
Short name T290
Test name
Test status
Simulation time 244370000 ps
CPU time 1.05 seconds
Started Jul 31 05:20:02 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 217536 kb
Host smart-e10d7642-93fa-4888-ae30-a6ae4406c155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315212246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2315212246
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3761651300
Short name T348
Test name
Test status
Simulation time 199780675 ps
CPU time 0.95 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:04 PM PDT 24
Peak memory 200104 kb
Host smart-272db01a-594a-4add-8464-08ac57a96262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761651300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3761651300
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.4137690561
Short name T508
Test name
Test status
Simulation time 746825564 ps
CPU time 4.04 seconds
Started Jul 31 05:20:01 PM PDT 24
Finished Jul 31 05:20:06 PM PDT 24
Peak memory 200532 kb
Host smart-b36e8df8-bde4-4bb6-9f23-ccc29fa8bad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137690561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.4137690561
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3152766455
Short name T460
Test name
Test status
Simulation time 149497371 ps
CPU time 1.13 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200348 kb
Host smart-7e246108-896e-4c2f-bb21-6243633cd59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152766455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3152766455
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1992495441
Short name T400
Test name
Test status
Simulation time 107904876 ps
CPU time 1.11 seconds
Started Jul 31 05:20:08 PM PDT 24
Finished Jul 31 05:20:09 PM PDT 24
Peak memory 200524 kb
Host smart-56fcc9f3-0189-4105-bffc-3f982d6d2ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992495441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1992495441
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3382699332
Short name T539
Test name
Test status
Simulation time 2284179737 ps
CPU time 10.63 seconds
Started Jul 31 05:20:04 PM PDT 24
Finished Jul 31 05:20:20 PM PDT 24
Peak memory 200592 kb
Host smart-b6fc8999-329c-440a-b03c-1b7c84fd0d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382699332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3382699332
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2492587987
Short name T343
Test name
Test status
Simulation time 153703165 ps
CPU time 1.87 seconds
Started Jul 31 05:20:23 PM PDT 24
Finished Jul 31 05:20:25 PM PDT 24
Peak memory 200260 kb
Host smart-3d6b7e3c-a904-484e-b029-0628b3fc7c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492587987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2492587987
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.129977827
Short name T374
Test name
Test status
Simulation time 155524429 ps
CPU time 1.15 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 200336 kb
Host smart-62120a58-be8c-494c-afea-cbf160636764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129977827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.129977827
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3882210377
Short name T403
Test name
Test status
Simulation time 97528683 ps
CPU time 0.86 seconds
Started Jul 31 05:20:17 PM PDT 24
Finished Jul 31 05:20:18 PM PDT 24
Peak memory 200136 kb
Host smart-dd1b7a98-e1e8-4e71-9cd6-f4c75bc299fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882210377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3882210377
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.450442121
Short name T30
Test name
Test status
Simulation time 1225241766 ps
CPU time 5.45 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 217360 kb
Host smart-85bd9969-ceb6-4a18-a9cf-a77e54bed78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450442121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.450442121
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.4145296606
Short name T164
Test name
Test status
Simulation time 244832192 ps
CPU time 1.12 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 217436 kb
Host smart-d73e4162-4154-4e75-b105-f8f1d597c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145296606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.4145296606
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2357814779
Short name T162
Test name
Test status
Simulation time 105443816 ps
CPU time 0.79 seconds
Started Jul 31 05:20:27 PM PDT 24
Finished Jul 31 05:20:28 PM PDT 24
Peak memory 200168 kb
Host smart-1dc2cb86-1ec0-48d3-97e7-e2c4d3ba0610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357814779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2357814779
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3360178754
Short name T45
Test name
Test status
Simulation time 1348751254 ps
CPU time 5.11 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 200552 kb
Host smart-be37958f-e9e8-429e-a555-0bdf9d464fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360178754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3360178754
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.667389024
Short name T432
Test name
Test status
Simulation time 152987862 ps
CPU time 1.09 seconds
Started Jul 31 05:20:09 PM PDT 24
Finished Jul 31 05:20:10 PM PDT 24
Peak memory 200276 kb
Host smart-15c611fa-f2d3-44c4-b8c9-6827299e385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667389024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.667389024
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2803872154
Short name T83
Test name
Test status
Simulation time 269751088 ps
CPU time 1.54 seconds
Started Jul 31 05:19:50 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 200476 kb
Host smart-2eec217d-91f6-4444-a319-246c0239d950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803872154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2803872154
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.221201154
Short name T353
Test name
Test status
Simulation time 828737339 ps
CPU time 4.14 seconds
Started Jul 31 05:20:13 PM PDT 24
Finished Jul 31 05:20:17 PM PDT 24
Peak memory 200636 kb
Host smart-3d3ad4c4-b56d-4e1c-9587-13a3dd38db45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221201154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.221201154
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2905368532
Short name T287
Test name
Test status
Simulation time 131699522 ps
CPU time 1.68 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 208508 kb
Host smart-88c2f5d1-f635-469f-b378-90f3287e7f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905368532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2905368532
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2533016780
Short name T251
Test name
Test status
Simulation time 177076832 ps
CPU time 1.28 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 200424 kb
Host smart-78409cd1-65d4-4762-bfbf-187fc4bb6199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533016780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2533016780
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.747292904
Short name T352
Test name
Test status
Simulation time 72236766 ps
CPU time 0.79 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200048 kb
Host smart-99deba9c-c6b3-4f0e-a981-0f03290505eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747292904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.747292904
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.836405708
Short name T523
Test name
Test status
Simulation time 1229126086 ps
CPU time 5.31 seconds
Started Jul 31 05:20:20 PM PDT 24
Finished Jul 31 05:20:26 PM PDT 24
Peak memory 221664 kb
Host smart-28561882-94cd-4058-befb-f4c07c536341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836405708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.836405708
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.4146104949
Short name T236
Test name
Test status
Simulation time 245910570 ps
CPU time 1.07 seconds
Started Jul 31 05:20:15 PM PDT 24
Finished Jul 31 05:20:17 PM PDT 24
Peak memory 217500 kb
Host smart-bb896d35-6366-472b-a1eb-23d58203bbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146104949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.4146104949
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3748008903
Short name T14
Test name
Test status
Simulation time 149820261 ps
CPU time 0.85 seconds
Started Jul 31 05:20:26 PM PDT 24
Finished Jul 31 05:20:27 PM PDT 24
Peak memory 200072 kb
Host smart-1ad98bfe-e7b7-4ef7-9cc6-b9dbf3e6e760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748008903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3748008903
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2535132732
Short name T252
Test name
Test status
Simulation time 998699552 ps
CPU time 5.12 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 200620 kb
Host smart-ff284904-6885-4667-b387-3519e5a5dfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535132732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2535132732
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1523453135
Short name T519
Test name
Test status
Simulation time 147033040 ps
CPU time 1.1 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 200348 kb
Host smart-71623ee4-2987-4e09-949d-542ae57e38ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523453135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1523453135
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1963671880
Short name T354
Test name
Test status
Simulation time 195862312 ps
CPU time 1.28 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200524 kb
Host smart-797c5df1-9f48-453d-9aa5-c6490a66ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963671880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1963671880
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1750126246
Short name T89
Test name
Test status
Simulation time 5855831622 ps
CPU time 25.92 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:20:24 PM PDT 24
Peak memory 208756 kb
Host smart-743e04c3-1f75-4135-a5fa-5ece3c7487ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750126246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1750126246
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2815736449
Short name T351
Test name
Test status
Simulation time 141865722 ps
CPU time 1.82 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200284 kb
Host smart-65784441-a13e-4146-9be3-d00ef324b161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815736449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2815736449
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2854333167
Short name T234
Test name
Test status
Simulation time 229329541 ps
CPU time 1.42 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:04 PM PDT 24
Peak memory 200496 kb
Host smart-182cff84-cf0d-4cb2-a9ba-a615f8834b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854333167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2854333167
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2547368808
Short name T532
Test name
Test status
Simulation time 70037562 ps
CPU time 0.78 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 200164 kb
Host smart-a1411e2b-57aa-4b8a-b16f-d70a94297c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547368808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2547368808
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4056269412
Short name T41
Test name
Test status
Simulation time 1218197241 ps
CPU time 5.3 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:20:01 PM PDT 24
Peak memory 217760 kb
Host smart-79a7c59d-8999-47e1-a738-999fb53862a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056269412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.4056269412
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3457160742
Short name T377
Test name
Test status
Simulation time 244692595 ps
CPU time 1.18 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 217488 kb
Host smart-d1bd904d-eb5a-4c5f-b6ab-d235fb2edb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457160742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3457160742
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1459868380
Short name T484
Test name
Test status
Simulation time 75497266 ps
CPU time 0.76 seconds
Started Jul 31 05:20:16 PM PDT 24
Finished Jul 31 05:20:17 PM PDT 24
Peak memory 200204 kb
Host smart-5405a0fc-e38d-4906-8c4e-11c5d762d21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459868380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1459868380
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2887729500
Short name T373
Test name
Test status
Simulation time 611449817 ps
CPU time 3.28 seconds
Started Jul 31 05:20:13 PM PDT 24
Finished Jul 31 05:20:16 PM PDT 24
Peak memory 200460 kb
Host smart-906b2d23-95b3-45bc-a31e-71d29b29c38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887729500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2887729500
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.749172732
Short name T489
Test name
Test status
Simulation time 101943763 ps
CPU time 0.97 seconds
Started Jul 31 05:20:07 PM PDT 24
Finished Jul 31 05:20:08 PM PDT 24
Peak memory 200308 kb
Host smart-b7154e66-5b37-46f8-a31c-38ec011bd58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749172732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.749172732
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1584358704
Short name T468
Test name
Test status
Simulation time 207481134 ps
CPU time 1.42 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:04 PM PDT 24
Peak memory 200504 kb
Host smart-3ce2cb48-7654-46f4-9022-f4455844fb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584358704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1584358704
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2834804429
Short name T443
Test name
Test status
Simulation time 590211791 ps
CPU time 2.76 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 200376 kb
Host smart-74d6aa87-e4c6-446c-a38e-86b47d8ca600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834804429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2834804429
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.864713513
Short name T57
Test name
Test status
Simulation time 269657182 ps
CPU time 1.69 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200340 kb
Host smart-cc509e05-a75b-4c73-9ca2-f3bb3216f743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864713513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.864713513
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.389678388
Short name T326
Test name
Test status
Simulation time 127146880 ps
CPU time 1.11 seconds
Started Jul 31 05:20:11 PM PDT 24
Finished Jul 31 05:20:12 PM PDT 24
Peak memory 200384 kb
Host smart-6735f40a-0595-4ef4-b61e-8e549f4d4c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389678388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.389678388
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3340727672
Short name T416
Test name
Test status
Simulation time 63241845 ps
CPU time 0.77 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 200120 kb
Host smart-bb489d9f-0643-40e5-90dd-15756c285308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340727672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3340727672
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3348168956
Short name T174
Test name
Test status
Simulation time 244499523 ps
CPU time 1.01 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 217540 kb
Host smart-9247d280-6160-425c-ae53-8825b9a8d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348168956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3348168956
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.590913235
Short name T300
Test name
Test status
Simulation time 235357604 ps
CPU time 0.93 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 200136 kb
Host smart-40b1cee3-cfb4-4be3-bcae-0db8af5de47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590913235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.590913235
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1252173059
Short name T129
Test name
Test status
Simulation time 1485302068 ps
CPU time 5.52 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:06 PM PDT 24
Peak memory 200560 kb
Host smart-47a4e9a5-46c9-41d0-8f0b-8525ba1d1031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252173059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1252173059
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1138074684
Short name T512
Test name
Test status
Simulation time 168022893 ps
CPU time 1.13 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200356 kb
Host smart-6df84a43-127c-44d9-a83e-1bdd8cd1dcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138074684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1138074684
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3126130305
Short name T166
Test name
Test status
Simulation time 129024296 ps
CPU time 1.19 seconds
Started Jul 31 05:20:16 PM PDT 24
Finished Jul 31 05:20:17 PM PDT 24
Peak memory 200440 kb
Host smart-d7a6a331-7e18-4956-8683-2a1aa9032259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126130305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3126130305
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1421693134
Short name T465
Test name
Test status
Simulation time 8757675079 ps
CPU time 35.93 seconds
Started Jul 31 05:20:21 PM PDT 24
Finished Jul 31 05:20:57 PM PDT 24
Peak memory 200536 kb
Host smart-30b993e5-2871-48c2-965f-b94a9481f62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421693134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1421693134
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3228761147
Short name T84
Test name
Test status
Simulation time 367742082 ps
CPU time 2.2 seconds
Started Jul 31 05:20:04 PM PDT 24
Finished Jul 31 05:20:07 PM PDT 24
Peak memory 200248 kb
Host smart-2ff2363e-5531-444a-8acd-06b6539aa6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228761147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3228761147
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3196014461
Short name T406
Test name
Test status
Simulation time 163314177 ps
CPU time 1.21 seconds
Started Jul 31 05:20:07 PM PDT 24
Finished Jul 31 05:20:08 PM PDT 24
Peak memory 200412 kb
Host smart-aa0d5a45-6f11-4742-b034-f9e851d7ecc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196014461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3196014461
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1323239739
Short name T277
Test name
Test status
Simulation time 80821867 ps
CPU time 0.88 seconds
Started Jul 31 05:19:38 PM PDT 24
Finished Jul 31 05:19:39 PM PDT 24
Peak memory 200176 kb
Host smart-f67cc8a4-db95-440c-b42a-395063ef0b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323239739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1323239739
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1295170782
Short name T24
Test name
Test status
Simulation time 2353713028 ps
CPU time 9.05 seconds
Started Jul 31 05:19:44 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 217716 kb
Host smart-eb830b31-f059-4686-98bd-b15a94553fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295170782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1295170782
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.4133014822
Short name T161
Test name
Test status
Simulation time 244525852 ps
CPU time 1.09 seconds
Started Jul 31 05:19:34 PM PDT 24
Finished Jul 31 05:19:35 PM PDT 24
Peak memory 217460 kb
Host smart-28d384a5-33e6-4800-943b-3960871b6558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133014822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.4133014822
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3780194778
Short name T454
Test name
Test status
Simulation time 163904849 ps
CPU time 0.88 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200140 kb
Host smart-d1fc70f0-8ed3-4177-97ab-48e548f61b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780194778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3780194778
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1988629339
Short name T483
Test name
Test status
Simulation time 1195542492 ps
CPU time 5.68 seconds
Started Jul 31 05:19:38 PM PDT 24
Finished Jul 31 05:19:43 PM PDT 24
Peak memory 200476 kb
Host smart-b76bb992-6b5f-4c09-877f-4ecee56d83d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988629339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1988629339
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1953294154
Short name T72
Test name
Test status
Simulation time 8354105916 ps
CPU time 12.44 seconds
Started Jul 31 05:19:36 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 217236 kb
Host smart-639a7d00-e11e-44f5-9a7b-c5344e997196
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953294154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1953294154
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2157439514
Short name T538
Test name
Test status
Simulation time 104869770 ps
CPU time 1.02 seconds
Started Jul 31 05:19:41 PM PDT 24
Finished Jul 31 05:19:42 PM PDT 24
Peak memory 200348 kb
Host smart-3dc51260-ae0f-4f57-ba6b-bbd0288c61a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157439514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2157439514
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1342353229
Short name T336
Test name
Test status
Simulation time 247240573 ps
CPU time 1.44 seconds
Started Jul 31 05:19:38 PM PDT 24
Finished Jul 31 05:19:39 PM PDT 24
Peak memory 200488 kb
Host smart-1868bd4d-2e55-4c0f-ac78-675dc76f2cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342353229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1342353229
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2758023365
Short name T435
Test name
Test status
Simulation time 5089534454 ps
CPU time 18.16 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:20:12 PM PDT 24
Peak memory 208792 kb
Host smart-1b8a5cf3-4a1e-4da6-a896-2575272052bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758023365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2758023365
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.444865684
Short name T81
Test name
Test status
Simulation time 128738117 ps
CPU time 1.67 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:50 PM PDT 24
Peak memory 200300 kb
Host smart-3e0173b9-c107-4cda-82c2-ad4014e813c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444865684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.444865684
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.283455269
Short name T148
Test name
Test status
Simulation time 63485733 ps
CPU time 0.73 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200156 kb
Host smart-558d8cb8-5002-4c53-a4b1-9000f468fd7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283455269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.283455269
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1570355242
Short name T389
Test name
Test status
Simulation time 2357430514 ps
CPU time 8.25 seconds
Started Jul 31 05:20:27 PM PDT 24
Finished Jul 31 05:20:35 PM PDT 24
Peak memory 217896 kb
Host smart-f47c862f-589d-4aaf-89c3-5490c7a0b12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570355242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1570355242
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1256164139
Short name T504
Test name
Test status
Simulation time 244082737 ps
CPU time 1.07 seconds
Started Jul 31 05:20:06 PM PDT 24
Finished Jul 31 05:20:07 PM PDT 24
Peak memory 217560 kb
Host smart-8af703ef-8328-48cb-8d5d-ac306cfba898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256164139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1256164139
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.413850259
Short name T378
Test name
Test status
Simulation time 119445001 ps
CPU time 0.76 seconds
Started Jul 31 05:20:09 PM PDT 24
Finished Jul 31 05:20:10 PM PDT 24
Peak memory 200080 kb
Host smart-4438aea6-72a1-4766-8fb3-423f769552e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413850259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.413850259
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3976731417
Short name T187
Test name
Test status
Simulation time 870328131 ps
CPU time 4.53 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 200496 kb
Host smart-5a2788d7-35b6-4115-a01f-c0a9a5f9442f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976731417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3976731417
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1733733508
Short name T398
Test name
Test status
Simulation time 153000138 ps
CPU time 1.14 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200372 kb
Host smart-38ebad38-b247-4248-873e-d496ffb1b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733733508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1733733508
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2197314436
Short name T419
Test name
Test status
Simulation time 126986452 ps
CPU time 1.15 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 200432 kb
Host smart-cf93d6f2-23ac-4b54-a6c8-756959bbfef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197314436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2197314436
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1525697130
Short name T46
Test name
Test status
Simulation time 8978057274 ps
CPU time 33.06 seconds
Started Jul 31 05:19:59 PM PDT 24
Finished Jul 31 05:20:32 PM PDT 24
Peak memory 208836 kb
Host smart-812a5300-edeb-4af0-b611-0c04c3c79939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525697130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1525697130
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3497024690
Short name T78
Test name
Test status
Simulation time 295284159 ps
CPU time 1.93 seconds
Started Jul 31 05:20:19 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 208408 kb
Host smart-b821600f-1b64-4536-ac3e-3b556e183caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497024690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3497024690
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3031062447
Short name T513
Test name
Test status
Simulation time 61159274 ps
CPU time 0.72 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:01 PM PDT 24
Peak memory 200352 kb
Host smart-2af14706-db38-49cb-8a1a-da1ecb89e010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031062447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3031062447
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3723737518
Short name T303
Test name
Test status
Simulation time 61816026 ps
CPU time 0.74 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 200008 kb
Host smart-88dbbcc0-5211-41c9-8c2b-6ada3d076034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723737518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3723737518
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3906224042
Short name T31
Test name
Test status
Simulation time 1223077633 ps
CPU time 5.87 seconds
Started Jul 31 05:20:24 PM PDT 24
Finished Jul 31 05:20:30 PM PDT 24
Peak memory 216792 kb
Host smart-7f861629-0b94-49a9-8102-53a91749fea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906224042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3906224042
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.155234798
Short name T492
Test name
Test status
Simulation time 246495783 ps
CPU time 1.13 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 217396 kb
Host smart-52323af4-0578-477f-baee-f4a87c585f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155234798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.155234798
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2102984145
Short name T220
Test name
Test status
Simulation time 127532605 ps
CPU time 0.78 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 200104 kb
Host smart-7000b6b6-58ae-4138-afc0-4179c9e9ce01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102984145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2102984145
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1032589859
Short name T99
Test name
Test status
Simulation time 1371622473 ps
CPU time 5.4 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 200560 kb
Host smart-4b71f720-2aa9-4913-b4b4-d0359b7031d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032589859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1032589859
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1697984707
Short name T382
Test name
Test status
Simulation time 105580250 ps
CPU time 1 seconds
Started Jul 31 05:20:20 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 200276 kb
Host smart-885e6fc8-f7da-4190-a08c-d4beefaadec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697984707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1697984707
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2521345097
Short name T7
Test name
Test status
Simulation time 189523434 ps
CPU time 1.31 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 200492 kb
Host smart-17faca5b-a0e4-4b52-a920-5a4b0ae5cfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521345097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2521345097
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.63352671
Short name T324
Test name
Test status
Simulation time 11154413547 ps
CPU time 37.72 seconds
Started Jul 31 05:20:26 PM PDT 24
Finished Jul 31 05:21:04 PM PDT 24
Peak memory 208764 kb
Host smart-e4800660-c64b-4a25-84ab-f886ec3da739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63352671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.63352671
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2867516167
Short name T477
Test name
Test status
Simulation time 389997970 ps
CPU time 2.12 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200140 kb
Host smart-51f53b21-fcc4-4e2a-9821-5c3ac5585a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867516167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2867516167
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.578016308
Short name T175
Test name
Test status
Simulation time 155285099 ps
CPU time 1.03 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:04 PM PDT 24
Peak memory 200256 kb
Host smart-e77862e8-ee6c-415f-aa05-ceabe98c0e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578016308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.578016308
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1827875455
Short name T49
Test name
Test status
Simulation time 60861264 ps
CPU time 0.72 seconds
Started Jul 31 05:19:48 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 200120 kb
Host smart-1db53f46-657b-477c-b033-f013c47a2a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827875455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1827875455
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1863932553
Short name T355
Test name
Test status
Simulation time 2367542192 ps
CPU time 8.04 seconds
Started Jul 31 05:20:11 PM PDT 24
Finished Jul 31 05:20:19 PM PDT 24
Peak memory 221680 kb
Host smart-b2d51f2f-c99f-4404-8edd-0125a4c5937e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863932553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1863932553
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1904319898
Short name T142
Test name
Test status
Simulation time 245118950 ps
CPU time 1.04 seconds
Started Jul 31 05:20:15 PM PDT 24
Finished Jul 31 05:20:16 PM PDT 24
Peak memory 217508 kb
Host smart-136fdbb6-15ba-4e74-af20-845a22d35095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904319898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1904319898
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3762729644
Short name T366
Test name
Test status
Simulation time 174456278 ps
CPU time 0.83 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200172 kb
Host smart-a8a59f05-8316-4c6b-ba26-78513b220c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762729644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3762729644
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2298174502
Short name T367
Test name
Test status
Simulation time 1363323970 ps
CPU time 5.31 seconds
Started Jul 31 05:20:15 PM PDT 24
Finished Jul 31 05:20:20 PM PDT 24
Peak memory 200516 kb
Host smart-878aab88-f370-4320-9ed5-53304707ce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298174502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2298174502
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3768878136
Short name T294
Test name
Test status
Simulation time 107331768 ps
CPU time 0.99 seconds
Started Jul 31 05:20:04 PM PDT 24
Finished Jul 31 05:20:05 PM PDT 24
Peak memory 200312 kb
Host smart-e54f00b5-e443-4a33-a9d4-df01842e1d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768878136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3768878136
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3310578292
Short name T79
Test name
Test status
Simulation time 116823777 ps
CPU time 1.18 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 200476 kb
Host smart-c90db7f4-24bd-40e1-bcf5-a35f4dd0f7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310578292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3310578292
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2582079278
Short name T414
Test name
Test status
Simulation time 5778545111 ps
CPU time 20.92 seconds
Started Jul 31 05:19:59 PM PDT 24
Finished Jul 31 05:20:25 PM PDT 24
Peak memory 200664 kb
Host smart-98255d67-5352-46c9-b41f-06182654e3d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582079278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2582079278
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.193446664
Short name T331
Test name
Test status
Simulation time 277487212 ps
CPU time 1.87 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200296 kb
Host smart-d3262e5e-2bb7-460f-b04f-8e73c9fb56b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193446664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.193446664
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2382154167
Short name T257
Test name
Test status
Simulation time 222207827 ps
CPU time 1.43 seconds
Started Jul 31 05:20:21 PM PDT 24
Finished Jul 31 05:20:23 PM PDT 24
Peak memory 200312 kb
Host smart-794af6c6-a955-455f-80c7-f8389d6b0558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382154167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2382154167
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.4148493319
Short name T263
Test name
Test status
Simulation time 74121440 ps
CPU time 0.77 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 200184 kb
Host smart-a7077348-df7d-412c-ac44-e165348f15f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148493319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.4148493319
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.800918007
Short name T27
Test name
Test status
Simulation time 2152097531 ps
CPU time 7.58 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:20:05 PM PDT 24
Peak memory 216860 kb
Host smart-49e2cd6b-d898-48b5-bf1c-9dd4c696fa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800918007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.800918007
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1051868456
Short name T47
Test name
Test status
Simulation time 244201402 ps
CPU time 1.06 seconds
Started Jul 31 05:20:21 PM PDT 24
Finished Jul 31 05:20:22 PM PDT 24
Peak memory 217432 kb
Host smart-b160964e-edb4-46f3-9d94-718b3d70ebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051868456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1051868456
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.825294056
Short name T522
Test name
Test status
Simulation time 239489921 ps
CPU time 0.98 seconds
Started Jul 31 05:20:18 PM PDT 24
Finished Jul 31 05:20:19 PM PDT 24
Peak memory 200084 kb
Host smart-e6f1d160-698c-4801-9e57-817316dd16ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825294056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.825294056
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2920402284
Short name T182
Test name
Test status
Simulation time 1586127919 ps
CPU time 6.23 seconds
Started Jul 31 05:20:23 PM PDT 24
Finished Jul 31 05:20:30 PM PDT 24
Peak memory 200560 kb
Host smart-9673f8b7-c28e-4d7c-9494-d5698f8ffd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920402284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2920402284
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1776791859
Short name T208
Test name
Test status
Simulation time 103779114 ps
CPU time 0.94 seconds
Started Jul 31 05:20:06 PM PDT 24
Finished Jul 31 05:20:07 PM PDT 24
Peak memory 200324 kb
Host smart-32c29188-fc6e-4a04-857b-b971fba9ed15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776791859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1776791859
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.593460846
Short name T327
Test name
Test status
Simulation time 202151972 ps
CPU time 1.37 seconds
Started Jul 31 05:20:30 PM PDT 24
Finished Jul 31 05:20:32 PM PDT 24
Peak memory 200536 kb
Host smart-de6f0a88-e173-4809-9ae1-5328e7ef4efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593460846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.593460846
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.4220753400
Short name T517
Test name
Test status
Simulation time 331785761 ps
CPU time 2.17 seconds
Started Jul 31 05:20:17 PM PDT 24
Finished Jul 31 05:20:20 PM PDT 24
Peak memory 208504 kb
Host smart-449596fb-33e1-4022-8c2b-053a22e5cdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220753400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.4220753400
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3017899892
Short name T22
Test name
Test status
Simulation time 180779981 ps
CPU time 1.12 seconds
Started Jul 31 05:20:20 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 200332 kb
Host smart-8902b882-50dd-4a20-9345-affb82a27487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017899892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3017899892
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1935542961
Short name T505
Test name
Test status
Simulation time 79323491 ps
CPU time 0.78 seconds
Started Jul 31 05:20:19 PM PDT 24
Finished Jul 31 05:20:20 PM PDT 24
Peak memory 200092 kb
Host smart-9662510c-f95c-431d-8b5d-149e0b8bbf17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935542961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1935542961
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.282675271
Short name T434
Test name
Test status
Simulation time 2173124154 ps
CPU time 7.52 seconds
Started Jul 31 05:20:16 PM PDT 24
Finished Jul 31 05:20:24 PM PDT 24
Peak memory 221760 kb
Host smart-9e523d4c-8b59-4e80-84b8-f8160d989b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282675271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.282675271
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4039421619
Short name T328
Test name
Test status
Simulation time 244121534 ps
CPU time 1.06 seconds
Started Jul 31 05:20:20 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 217532 kb
Host smart-3d92505e-f913-4107-939d-01cd21992f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039421619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4039421619
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1693788256
Short name T319
Test name
Test status
Simulation time 119365448 ps
CPU time 0.77 seconds
Started Jul 31 05:20:19 PM PDT 24
Finished Jul 31 05:20:20 PM PDT 24
Peak memory 200160 kb
Host smart-1e4fe61c-152f-4e46-aaec-859f4ff364df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693788256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1693788256
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.536614665
Short name T345
Test name
Test status
Simulation time 1144047169 ps
CPU time 4.44 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 200532 kb
Host smart-cd8d33c9-a53c-40a1-aaf2-8367dc5fc33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536614665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.536614665
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2861391937
Short name T535
Test name
Test status
Simulation time 166708421 ps
CPU time 1.22 seconds
Started Jul 31 05:20:28 PM PDT 24
Finished Jul 31 05:20:29 PM PDT 24
Peak memory 200272 kb
Host smart-d77d1066-b9c1-40b2-8779-c3a78662c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861391937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2861391937
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3866081262
Short name T276
Test name
Test status
Simulation time 230667226 ps
CPU time 1.36 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:01 PM PDT 24
Peak memory 200408 kb
Host smart-cf2f849d-7803-4b9e-80b2-85b7c1f7843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866081262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3866081262
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1088176598
Short name T527
Test name
Test status
Simulation time 5974786535 ps
CPU time 24.64 seconds
Started Jul 31 05:20:33 PM PDT 24
Finished Jul 31 05:20:57 PM PDT 24
Peak memory 210672 kb
Host smart-1b5675b8-923b-4740-a534-64d727110706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088176598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1088176598
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2450668443
Short name T313
Test name
Test status
Simulation time 472820493 ps
CPU time 2.61 seconds
Started Jul 31 05:20:18 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 208456 kb
Host smart-6fcb4799-64b7-4eea-8670-028fb008792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450668443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2450668443
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.4087349920
Short name T442
Test name
Test status
Simulation time 217899174 ps
CPU time 1.29 seconds
Started Jul 31 05:19:59 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 200348 kb
Host smart-771861a7-1125-4584-abf5-54c80f9ef2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087349920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.4087349920
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.960689012
Short name T315
Test name
Test status
Simulation time 66865946 ps
CPU time 0.71 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200084 kb
Host smart-604f7566-f07d-4901-a0ff-e2662de28b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960689012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.960689012
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.551926134
Short name T494
Test name
Test status
Simulation time 2172831373 ps
CPU time 7.71 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:08 PM PDT 24
Peak memory 221740 kb
Host smart-c6fcd478-df7c-4454-9c92-5d4cde4ede3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551926134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.551926134
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.726267045
Short name T237
Test name
Test status
Simulation time 244360038 ps
CPU time 1.04 seconds
Started Jul 31 05:20:19 PM PDT 24
Finished Jul 31 05:20:20 PM PDT 24
Peak memory 217500 kb
Host smart-b5436508-4e23-4100-bcb4-dfd9266478e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726267045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.726267045
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2352682542
Short name T248
Test name
Test status
Simulation time 210404884 ps
CPU time 0.95 seconds
Started Jul 31 05:20:12 PM PDT 24
Finished Jul 31 05:20:13 PM PDT 24
Peak memory 200172 kb
Host smart-8034ee8a-ede4-4818-ae62-09b25b748125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352682542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2352682542
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2936372563
Short name T128
Test name
Test status
Simulation time 1592717089 ps
CPU time 5.73 seconds
Started Jul 31 05:20:20 PM PDT 24
Finished Jul 31 05:20:26 PM PDT 24
Peak memory 200700 kb
Host smart-11985b5d-7e3f-4b7c-9a76-8d65f8f48f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936372563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2936372563
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3177396820
Short name T280
Test name
Test status
Simulation time 99233819 ps
CPU time 0.97 seconds
Started Jul 31 05:20:02 PM PDT 24
Finished Jul 31 05:20:03 PM PDT 24
Peak memory 200352 kb
Host smart-ab423a32-edb3-4b3b-91fb-5cbfbb9b9019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177396820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3177396820
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.743043029
Short name T293
Test name
Test status
Simulation time 116072673 ps
CPU time 1.16 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200388 kb
Host smart-ba6dec08-c0cb-4cf7-9bf3-b9b8fa7748f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743043029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.743043029
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1899623884
Short name T308
Test name
Test status
Simulation time 1277451965 ps
CPU time 5.89 seconds
Started Jul 31 05:20:22 PM PDT 24
Finished Jul 31 05:20:28 PM PDT 24
Peak memory 208772 kb
Host smart-2c6cb601-fb30-440d-8edf-0a136f1d8666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899623884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1899623884
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2074101011
Short name T274
Test name
Test status
Simulation time 454991133 ps
CPU time 2.51 seconds
Started Jul 31 05:20:10 PM PDT 24
Finished Jul 31 05:20:13 PM PDT 24
Peak memory 200312 kb
Host smart-405cf99a-bc2a-4c81-a247-10d5857e79c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074101011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2074101011
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3807943893
Short name T500
Test name
Test status
Simulation time 62821542 ps
CPU time 0.75 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200360 kb
Host smart-829cd824-085f-48b5-8359-63c066bc4e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807943893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3807943893
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.4113325731
Short name T144
Test name
Test status
Simulation time 81623200 ps
CPU time 0.87 seconds
Started Jul 31 05:20:29 PM PDT 24
Finished Jul 31 05:20:30 PM PDT 24
Peak memory 200136 kb
Host smart-7a273317-28f5-493c-a114-230a679ce337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113325731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.4113325731
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3776387411
Short name T370
Test name
Test status
Simulation time 2354542458 ps
CPU time 8.96 seconds
Started Jul 31 05:20:17 PM PDT 24
Finished Jul 31 05:20:26 PM PDT 24
Peak memory 221736 kb
Host smart-06cfd474-8d2c-4cc9-a6b9-afd9debd3128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776387411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3776387411
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3278647236
Short name T415
Test name
Test status
Simulation time 244156727 ps
CPU time 1.12 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 217540 kb
Host smart-61a1df1d-1b53-4ba2-92fd-ac401adf5e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278647236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3278647236
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2970616369
Short name T371
Test name
Test status
Simulation time 207500214 ps
CPU time 0.9 seconds
Started Jul 31 05:20:25 PM PDT 24
Finished Jul 31 05:20:26 PM PDT 24
Peak memory 200160 kb
Host smart-83c484e5-6813-416e-8169-f26de43e5f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970616369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2970616369
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.146312330
Short name T21
Test name
Test status
Simulation time 716574131 ps
CPU time 3.7 seconds
Started Jul 31 05:20:17 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 200484 kb
Host smart-c81d9bc8-5072-4a34-a52c-050ba4f637a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146312330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.146312330
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2725182633
Short name T423
Test name
Test status
Simulation time 177948712 ps
CPU time 1.13 seconds
Started Jul 31 05:20:00 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 200300 kb
Host smart-ccf78d37-9a25-4a2a-9956-658dbcbdb714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725182633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2725182633
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2621752735
Short name T76
Test name
Test status
Simulation time 205870307 ps
CPU time 1.42 seconds
Started Jul 31 05:20:29 PM PDT 24
Finished Jul 31 05:20:31 PM PDT 24
Peak memory 200460 kb
Host smart-4f1408c4-14d5-476d-b9c8-5f78683b1c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621752735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2621752735
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.599050208
Short name T446
Test name
Test status
Simulation time 4712987351 ps
CPU time 22.45 seconds
Started Jul 31 05:20:19 PM PDT 24
Finished Jul 31 05:20:42 PM PDT 24
Peak memory 208840 kb
Host smart-4d011923-3eec-4023-992f-56451e7ecbc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599050208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.599050208
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3893489071
Short name T167
Test name
Test status
Simulation time 384237799 ps
CPU time 2.32 seconds
Started Jul 31 05:20:09 PM PDT 24
Finished Jul 31 05:20:11 PM PDT 24
Peak memory 200276 kb
Host smart-2347441d-a5e4-46dc-93c2-d2ddddec0333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893489071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3893489071
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1601064545
Short name T335
Test name
Test status
Simulation time 90030348 ps
CPU time 0.82 seconds
Started Jul 31 05:20:28 PM PDT 24
Finished Jul 31 05:20:29 PM PDT 24
Peak memory 200336 kb
Host smart-20853a5a-5f27-4877-acfa-17e85250c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601064545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1601064545
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.16647408
Short name T450
Test name
Test status
Simulation time 66070772 ps
CPU time 0.74 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200156 kb
Host smart-2e68d0b8-61e9-4080-96c9-c32ba3f6773d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16647408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.16647408
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2395092176
Short name T23
Test name
Test status
Simulation time 1228701578 ps
CPU time 5.36 seconds
Started Jul 31 05:20:05 PM PDT 24
Finished Jul 31 05:20:11 PM PDT 24
Peak memory 216780 kb
Host smart-c051e815-5e68-4a6d-a95c-3bacd1e16cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395092176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2395092176
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3611798919
Short name T3
Test name
Test status
Simulation time 244205383 ps
CPU time 1.07 seconds
Started Jul 31 05:20:08 PM PDT 24
Finished Jul 31 05:20:10 PM PDT 24
Peak memory 217552 kb
Host smart-4a769d04-414b-4849-933f-d3940f41b352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611798919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3611798919
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1081407052
Short name T365
Test name
Test status
Simulation time 185567979 ps
CPU time 0.85 seconds
Started Jul 31 05:20:18 PM PDT 24
Finished Jul 31 05:20:19 PM PDT 24
Peak memory 200152 kb
Host smart-55211fb2-7422-4b95-a3ff-344684dc61f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081407052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1081407052
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2561134224
Short name T531
Test name
Test status
Simulation time 765828799 ps
CPU time 3.76 seconds
Started Jul 31 05:20:18 PM PDT 24
Finished Jul 31 05:20:22 PM PDT 24
Peak memory 200564 kb
Host smart-7daffec6-d115-484e-b08f-d00a0059c86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561134224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2561134224
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.142964583
Short name T344
Test name
Test status
Simulation time 105234376 ps
CPU time 1.02 seconds
Started Jul 31 05:20:31 PM PDT 24
Finished Jul 31 05:20:32 PM PDT 24
Peak memory 200352 kb
Host smart-6dfd7052-ce71-469d-837a-60e440837f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142964583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.142964583
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2735619730
Short name T75
Test name
Test status
Simulation time 245331620 ps
CPU time 1.45 seconds
Started Jul 31 05:20:28 PM PDT 24
Finished Jul 31 05:20:29 PM PDT 24
Peak memory 200492 kb
Host smart-277a8161-68f4-4489-bde3-b51933cfc559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735619730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2735619730
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2540504630
Short name T444
Test name
Test status
Simulation time 1422539073 ps
CPU time 6.6 seconds
Started Jul 31 05:20:25 PM PDT 24
Finished Jul 31 05:20:32 PM PDT 24
Peak memory 208764 kb
Host smart-2217dbdf-bd6a-4676-9b75-8a9f4a6beb02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540504630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2540504630
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3577127531
Short name T221
Test name
Test status
Simulation time 515957402 ps
CPU time 2.71 seconds
Started Jul 31 05:20:13 PM PDT 24
Finished Jul 31 05:20:16 PM PDT 24
Peak memory 200280 kb
Host smart-f9c21373-7806-423d-8d08-fc54a9530e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577127531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3577127531
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1250831051
Short name T402
Test name
Test status
Simulation time 79583074 ps
CPU time 0.84 seconds
Started Jul 31 05:20:03 PM PDT 24
Finished Jul 31 05:20:04 PM PDT 24
Peak memory 200316 kb
Host smart-35fdaea4-f3b4-44db-a59b-5d6df0d8104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250831051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1250831051
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1671051441
Short name T333
Test name
Test status
Simulation time 72123809 ps
CPU time 0.76 seconds
Started Jul 31 05:20:23 PM PDT 24
Finished Jul 31 05:20:24 PM PDT 24
Peak memory 199876 kb
Host smart-66960a93-801c-4b6a-bb24-e461daee82d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671051441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1671051441
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4069402768
Short name T332
Test name
Test status
Simulation time 2369550584 ps
CPU time 8.16 seconds
Started Jul 31 05:20:37 PM PDT 24
Finished Jul 31 05:20:45 PM PDT 24
Peak memory 217640 kb
Host smart-edb822c1-6b3d-4ccf-826e-e965f7460f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069402768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4069402768
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2194376945
Short name T37
Test name
Test status
Simulation time 244361832 ps
CPU time 1.07 seconds
Started Jul 31 05:20:36 PM PDT 24
Finished Jul 31 05:20:37 PM PDT 24
Peak memory 217580 kb
Host smart-41c3d808-1a1b-4d17-b5b6-2bc1df1c1856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194376945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2194376945
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3336993031
Short name T386
Test name
Test status
Simulation time 228789775 ps
CPU time 0.94 seconds
Started Jul 31 05:20:36 PM PDT 24
Finished Jul 31 05:20:37 PM PDT 24
Peak memory 200136 kb
Host smart-9f599ce9-43ba-4014-84fb-9f22ef1acf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336993031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3336993031
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.283108378
Short name T526
Test name
Test status
Simulation time 762409408 ps
CPU time 4.23 seconds
Started Jul 31 05:20:33 PM PDT 24
Finished Jul 31 05:20:38 PM PDT 24
Peak memory 200540 kb
Host smart-f9dbbd6a-b5fd-497b-9017-f9f0b9cb7087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283108378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.283108378
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3633410587
Short name T420
Test name
Test status
Simulation time 100276633 ps
CPU time 1.01 seconds
Started Jul 31 05:20:14 PM PDT 24
Finished Jul 31 05:20:16 PM PDT 24
Peak memory 200368 kb
Host smart-4026c20d-f2bc-4d01-8ee8-35a0041ae236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633410587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3633410587
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.457896561
Short name T204
Test name
Test status
Simulation time 187415317 ps
CPU time 1.45 seconds
Started Jul 31 05:20:15 PM PDT 24
Finished Jul 31 05:20:16 PM PDT 24
Peak memory 200376 kb
Host smart-419e6cda-e013-4aee-8d1a-d9cd952ce8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457896561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.457896561
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3657366393
Short name T466
Test name
Test status
Simulation time 896001450 ps
CPU time 4.85 seconds
Started Jul 31 05:20:33 PM PDT 24
Finished Jul 31 05:20:38 PM PDT 24
Peak memory 200476 kb
Host smart-1df9f5b9-f77f-4929-a133-7449c8cc3302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657366393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3657366393
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.283193325
Short name T395
Test name
Test status
Simulation time 120980489 ps
CPU time 1.42 seconds
Started Jul 31 05:20:13 PM PDT 24
Finished Jul 31 05:20:15 PM PDT 24
Peak memory 200264 kb
Host smart-9a9ac310-71b8-49fe-99f5-4e81e2b68272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283193325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.283193325
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3827042462
Short name T227
Test name
Test status
Simulation time 136987080 ps
CPU time 1.01 seconds
Started Jul 31 05:20:32 PM PDT 24
Finished Jul 31 05:20:33 PM PDT 24
Peak memory 200388 kb
Host smart-4086361b-512b-4d4f-9d3d-c4096756e36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827042462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3827042462
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3668579336
Short name T452
Test name
Test status
Simulation time 78610806 ps
CPU time 0.8 seconds
Started Jul 31 05:20:22 PM PDT 24
Finished Jul 31 05:20:23 PM PDT 24
Peak memory 200172 kb
Host smart-e14a4403-6542-43de-92e0-89128ddb5362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668579336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3668579336
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1409811916
Short name T25
Test name
Test status
Simulation time 1899291486 ps
CPU time 7.39 seconds
Started Jul 31 05:20:23 PM PDT 24
Finished Jul 31 05:20:30 PM PDT 24
Peak memory 217752 kb
Host smart-7e758c6b-4037-4a41-8af6-6f6070bee35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409811916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1409811916
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3665303271
Short name T410
Test name
Test status
Simulation time 244746098 ps
CPU time 1.18 seconds
Started Jul 31 05:20:32 PM PDT 24
Finished Jul 31 05:20:33 PM PDT 24
Peak memory 217520 kb
Host smart-ab16df05-b8be-4151-8b89-c3ccdcae9266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665303271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3665303271
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3106998938
Short name T447
Test name
Test status
Simulation time 169522451 ps
CPU time 0.87 seconds
Started Jul 31 05:20:28 PM PDT 24
Finished Jul 31 05:20:29 PM PDT 24
Peak memory 200160 kb
Host smart-d06a4d2c-0b72-493d-8eba-37d77a6c4cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106998938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3106998938
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2197414124
Short name T180
Test name
Test status
Simulation time 1638203096 ps
CPU time 6.17 seconds
Started Jul 31 05:20:30 PM PDT 24
Finished Jul 31 05:20:36 PM PDT 24
Peak memory 200540 kb
Host smart-a636d186-6db7-42b7-9ab0-b194d7d3b02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197414124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2197414124
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1880878245
Short name T212
Test name
Test status
Simulation time 98151707 ps
CPU time 0.92 seconds
Started Jul 31 05:20:20 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 200024 kb
Host smart-92e0c8a5-150c-4a1c-91de-e3ef66fc3405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880878245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1880878245
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1000729551
Short name T359
Test name
Test status
Simulation time 113232242 ps
CPU time 1.16 seconds
Started Jul 31 05:20:27 PM PDT 24
Finished Jul 31 05:20:28 PM PDT 24
Peak memory 200492 kb
Host smart-2e077ae1-6af3-4e34-b350-1a592db5c8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000729551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1000729551
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3981122147
Short name T502
Test name
Test status
Simulation time 4877109906 ps
CPU time 21.01 seconds
Started Jul 31 05:20:41 PM PDT 24
Finished Jul 31 05:21:02 PM PDT 24
Peak memory 209700 kb
Host smart-d3780d3d-9d46-4ab2-8795-51e3c8733900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981122147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3981122147
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2431472608
Short name T207
Test name
Test status
Simulation time 463786496 ps
CPU time 2.73 seconds
Started Jul 31 05:20:36 PM PDT 24
Finished Jul 31 05:20:39 PM PDT 24
Peak memory 200344 kb
Host smart-39c33bfa-d99a-429d-9f39-769c01ec0ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431472608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2431472608
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2465217155
Short name T154
Test name
Test status
Simulation time 207416434 ps
CPU time 1.21 seconds
Started Jul 31 05:20:24 PM PDT 24
Finished Jul 31 05:20:25 PM PDT 24
Peak memory 200372 kb
Host smart-8956adfc-baf2-4b18-b2ec-f9bfd3d47312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465217155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2465217155
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1536008437
Short name T39
Test name
Test status
Simulation time 65400068 ps
CPU time 0.76 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 200160 kb
Host smart-f1e51304-a6d7-41d7-a4a4-f6df8238dc05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536008437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1536008437
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1928295896
Short name T28
Test name
Test status
Simulation time 1226089650 ps
CPU time 5.37 seconds
Started Jul 31 05:19:50 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 217796 kb
Host smart-d93e6c80-659b-4925-bf93-d80715c1d1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928295896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1928295896
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.977545131
Short name T362
Test name
Test status
Simulation time 245414739 ps
CPU time 1.04 seconds
Started Jul 31 05:19:46 PM PDT 24
Finished Jul 31 05:19:47 PM PDT 24
Peak memory 217488 kb
Host smart-df460521-4e41-4349-825e-b36e78722b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977545131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.977545131
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1009451994
Short name T13
Test name
Test status
Simulation time 133534465 ps
CPU time 0.78 seconds
Started Jul 31 05:19:43 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 200148 kb
Host smart-07e388c6-d21d-4edf-84a2-077c2064f72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009451994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1009451994
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.790193878
Short name T516
Test name
Test status
Simulation time 1223197604 ps
CPU time 5.1 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200584 kb
Host smart-ca9014f4-9454-44a2-ae80-13504b9e312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790193878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.790193878
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2346410819
Short name T70
Test name
Test status
Simulation time 8292679568 ps
CPU time 15.55 seconds
Started Jul 31 05:19:40 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 217224 kb
Host smart-78044a40-5dd3-450b-b2e0-afbe061124b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346410819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2346410819
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.517518547
Short name T259
Test name
Test status
Simulation time 94496953 ps
CPU time 1.02 seconds
Started Jul 31 05:19:44 PM PDT 24
Finished Jul 31 05:19:45 PM PDT 24
Peak memory 200336 kb
Host smart-c8709290-051f-4420-89d2-12cfeb41d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517518547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.517518547
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.161229341
Short name T342
Test name
Test status
Simulation time 116914611 ps
CPU time 1.18 seconds
Started Jul 31 05:19:34 PM PDT 24
Finished Jul 31 05:19:36 PM PDT 24
Peak memory 200516 kb
Host smart-47956e2a-f91d-4393-802c-e3c32d92e8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161229341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.161229341
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3279118311
Short name T33
Test name
Test status
Simulation time 382899390 ps
CPU time 1.95 seconds
Started Jul 31 05:19:42 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 200516 kb
Host smart-75c93160-8d38-4b35-98b1-dee7d6d07b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279118311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3279118311
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.804212302
Short name T509
Test name
Test status
Simulation time 130409068 ps
CPU time 1.55 seconds
Started Jul 31 05:19:35 PM PDT 24
Finished Jul 31 05:19:37 PM PDT 24
Peak memory 208492 kb
Host smart-c4d45a6c-3a42-49d6-a8a4-ad3a697d2acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804212302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.804212302
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.283423104
Short name T232
Test name
Test status
Simulation time 223538955 ps
CPU time 1.31 seconds
Started Jul 31 05:19:33 PM PDT 24
Finished Jul 31 05:19:35 PM PDT 24
Peak memory 200268 kb
Host smart-6fa03545-e101-4d24-8554-6ea9712ae6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283423104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.283423104
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.215947555
Short name T426
Test name
Test status
Simulation time 67440220 ps
CPU time 0.76 seconds
Started Jul 31 05:20:19 PM PDT 24
Finished Jul 31 05:20:20 PM PDT 24
Peak memory 200132 kb
Host smart-5c98c50a-c092-48bb-ac78-d580edbd8dfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215947555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.215947555
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.4018285949
Short name T511
Test name
Test status
Simulation time 1900626605 ps
CPU time 7.46 seconds
Started Jul 31 05:20:30 PM PDT 24
Finished Jul 31 05:20:38 PM PDT 24
Peak memory 217024 kb
Host smart-30ecb94d-7270-4047-bbe0-dcb73b8fa39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018285949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.4018285949
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3548744904
Short name T40
Test name
Test status
Simulation time 244652626 ps
CPU time 1.16 seconds
Started Jul 31 05:20:23 PM PDT 24
Finished Jul 31 05:20:24 PM PDT 24
Peak memory 217488 kb
Host smart-303d4e32-eb3c-4bae-9734-385a878ead67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548744904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3548744904
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2891473921
Short name T424
Test name
Test status
Simulation time 181233085 ps
CPU time 0.86 seconds
Started Jul 31 05:20:33 PM PDT 24
Finished Jul 31 05:20:34 PM PDT 24
Peak memory 200128 kb
Host smart-f166e268-5154-487d-9744-14fcdd5222f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891473921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2891473921
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2276815161
Short name T306
Test name
Test status
Simulation time 871947427 ps
CPU time 4.45 seconds
Started Jul 31 05:20:27 PM PDT 24
Finished Jul 31 05:20:32 PM PDT 24
Peak memory 200628 kb
Host smart-2c7839ae-a9f4-41d8-bb1a-3003da6c977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276815161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2276815161
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3305823223
Short name T265
Test name
Test status
Simulation time 166914124 ps
CPU time 1.1 seconds
Started Jul 31 05:20:29 PM PDT 24
Finished Jul 31 05:20:31 PM PDT 24
Peak memory 200352 kb
Host smart-88ea3242-aff3-45a6-bb37-2112a253e572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305823223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3305823223
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2831320451
Short name T223
Test name
Test status
Simulation time 120398274 ps
CPU time 1.27 seconds
Started Jul 31 05:20:24 PM PDT 24
Finished Jul 31 05:20:25 PM PDT 24
Peak memory 200432 kb
Host smart-a3090f21-a8e1-4499-9a10-e158168b42e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831320451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2831320451
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3636441809
Short name T397
Test name
Test status
Simulation time 1173989023 ps
CPU time 5.51 seconds
Started Jul 31 05:20:24 PM PDT 24
Finished Jul 31 05:20:30 PM PDT 24
Peak memory 208756 kb
Host smart-b981fc8b-e533-4979-b482-e035cd5850df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636441809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3636441809
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3422032835
Short name T295
Test name
Test status
Simulation time 388738659 ps
CPU time 2.17 seconds
Started Jul 31 05:20:11 PM PDT 24
Finished Jul 31 05:20:13 PM PDT 24
Peak memory 200324 kb
Host smart-5bfa2908-c86d-48b6-a13d-bf3a9b410c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422032835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3422032835
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.4066048941
Short name T272
Test name
Test status
Simulation time 116992815 ps
CPU time 1.12 seconds
Started Jul 31 05:20:25 PM PDT 24
Finished Jul 31 05:20:26 PM PDT 24
Peak memory 200316 kb
Host smart-6ffde6ee-0b19-40c1-b729-b9cbfad694e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066048941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4066048941
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.737294115
Short name T77
Test name
Test status
Simulation time 67234866 ps
CPU time 0.78 seconds
Started Jul 31 05:20:29 PM PDT 24
Finished Jul 31 05:20:29 PM PDT 24
Peak memory 200148 kb
Host smart-4e9ae4a4-f98e-4802-8272-05bdd611e0eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737294115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.737294115
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3082164399
Short name T52
Test name
Test status
Simulation time 2190414158 ps
CPU time 8.22 seconds
Started Jul 31 05:20:27 PM PDT 24
Finished Jul 31 05:20:35 PM PDT 24
Peak memory 221756 kb
Host smart-11bae591-7662-440b-84ae-36bb596afb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082164399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3082164399
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.171859742
Short name T231
Test name
Test status
Simulation time 244083486 ps
CPU time 1.08 seconds
Started Jul 31 05:20:27 PM PDT 24
Finished Jul 31 05:20:29 PM PDT 24
Peak memory 217544 kb
Host smart-4384e70c-14e8-4a9f-b55a-5a23f908cc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171859742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.171859742
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.746483959
Short name T418
Test name
Test status
Simulation time 204440402 ps
CPU time 0.92 seconds
Started Jul 31 05:20:37 PM PDT 24
Finished Jul 31 05:20:38 PM PDT 24
Peak memory 200128 kb
Host smart-54595288-79cf-4b6f-914c-63ea49da49c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746483959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.746483959
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.744682126
Short name T322
Test name
Test status
Simulation time 1010825780 ps
CPU time 4.94 seconds
Started Jul 31 05:20:28 PM PDT 24
Finished Jul 31 05:20:33 PM PDT 24
Peak memory 200484 kb
Host smart-5bf02d6c-8b28-4433-833d-6eb948f99424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744682126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.744682126
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1382310494
Short name T269
Test name
Test status
Simulation time 174205960 ps
CPU time 1.09 seconds
Started Jul 31 05:20:39 PM PDT 24
Finished Jul 31 05:20:40 PM PDT 24
Peak memory 200300 kb
Host smart-c36bcbec-c155-4bb3-96bb-e3bd559fa397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382310494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1382310494
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3721457679
Short name T48
Test name
Test status
Simulation time 118065158 ps
CPU time 1.15 seconds
Started Jul 31 05:20:30 PM PDT 24
Finished Jul 31 05:20:31 PM PDT 24
Peak memory 200444 kb
Host smart-d92a62fa-8add-415c-a7c7-9b549d94ad2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721457679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3721457679
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.4039465045
Short name T349
Test name
Test status
Simulation time 6089084033 ps
CPU time 26.28 seconds
Started Jul 31 05:20:44 PM PDT 24
Finished Jul 31 05:21:10 PM PDT 24
Peak memory 200592 kb
Host smart-f4b923e2-1e0e-432e-9c7a-691c3f55425b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039465045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4039465045
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3161403083
Short name T215
Test name
Test status
Simulation time 387569456 ps
CPU time 2.26 seconds
Started Jul 31 05:20:22 PM PDT 24
Finished Jul 31 05:20:25 PM PDT 24
Peak memory 200344 kb
Host smart-741bf3c8-a047-4e79-addf-b7fbab644d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161403083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3161403083
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1152986284
Short name T339
Test name
Test status
Simulation time 166362207 ps
CPU time 1.19 seconds
Started Jul 31 05:20:46 PM PDT 24
Finished Jul 31 05:20:48 PM PDT 24
Peak memory 200352 kb
Host smart-f0af1f5e-b256-4ccf-9245-be5885f0c9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152986284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1152986284
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.510343443
Short name T507
Test name
Test status
Simulation time 74438733 ps
CPU time 0.84 seconds
Started Jul 31 05:20:29 PM PDT 24
Finished Jul 31 05:20:30 PM PDT 24
Peak memory 200152 kb
Host smart-d64f9af7-12c6-484d-9d8b-94db1872e202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510343443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.510343443
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3589331309
Short name T364
Test name
Test status
Simulation time 1899796404 ps
CPU time 7.28 seconds
Started Jul 31 05:20:34 PM PDT 24
Finished Jul 31 05:20:42 PM PDT 24
Peak memory 217760 kb
Host smart-943fbc32-76e9-40e0-bb9e-b9998848a774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589331309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3589331309
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3062467305
Short name T296
Test name
Test status
Simulation time 244497258 ps
CPU time 1.07 seconds
Started Jul 31 05:20:41 PM PDT 24
Finished Jul 31 05:20:42 PM PDT 24
Peak memory 217496 kb
Host smart-ae30ba41-b03a-4df0-aea6-ac9fa32fbeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062467305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3062467305
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1375184756
Short name T485
Test name
Test status
Simulation time 108529043 ps
CPU time 0.75 seconds
Started Jul 31 05:20:26 PM PDT 24
Finished Jul 31 05:20:27 PM PDT 24
Peak memory 200040 kb
Host smart-17810d5c-c3de-4020-9845-1179cedaa415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375184756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1375184756
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2688118661
Short name T501
Test name
Test status
Simulation time 831210072 ps
CPU time 4.03 seconds
Started Jul 31 05:20:39 PM PDT 24
Finished Jul 31 05:20:44 PM PDT 24
Peak memory 200592 kb
Host smart-7b51b04e-d216-43d6-8ecd-f6e43ed0761d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688118661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2688118661
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2926264866
Short name T408
Test name
Test status
Simulation time 155111190 ps
CPU time 1.13 seconds
Started Jul 31 05:20:27 PM PDT 24
Finished Jul 31 05:20:28 PM PDT 24
Peak memory 200380 kb
Host smart-9bd6d8f1-6625-4aa0-911f-a88acb767502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926264866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2926264866
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3001141796
Short name T529
Test name
Test status
Simulation time 200578540 ps
CPU time 1.41 seconds
Started Jul 31 05:20:45 PM PDT 24
Finished Jul 31 05:20:46 PM PDT 24
Peak memory 200452 kb
Host smart-729f31a1-f3a4-4789-8a1a-b5b808db92a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001141796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3001141796
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1024553805
Short name T86
Test name
Test status
Simulation time 8217259351 ps
CPU time 26.12 seconds
Started Jul 31 05:20:32 PM PDT 24
Finished Jul 31 05:20:58 PM PDT 24
Peak memory 200660 kb
Host smart-41711644-49ed-4a7c-ba3d-87b2527e7e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024553805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1024553805
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.627916066
Short name T85
Test name
Test status
Simulation time 427083401 ps
CPU time 2.39 seconds
Started Jul 31 05:20:34 PM PDT 24
Finished Jul 31 05:20:37 PM PDT 24
Peak memory 208452 kb
Host smart-78399eb0-28b7-4e1e-9c3f-47cfc740e592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627916066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.627916066
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1381711149
Short name T80
Test name
Test status
Simulation time 94233480 ps
CPU time 0.85 seconds
Started Jul 31 05:20:28 PM PDT 24
Finished Jul 31 05:20:29 PM PDT 24
Peak memory 200292 kb
Host smart-6da0bc76-17b4-4cae-8e79-588395d6dd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381711149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1381711149
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1210386411
Short name T185
Test name
Test status
Simulation time 71247514 ps
CPU time 0.84 seconds
Started Jul 31 05:20:44 PM PDT 24
Finished Jul 31 05:20:45 PM PDT 24
Peak memory 200124 kb
Host smart-25f5b0fa-90df-45cf-8954-1f01dc75d684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210386411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1210386411
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2613293092
Short name T282
Test name
Test status
Simulation time 2344223365 ps
CPU time 9.06 seconds
Started Jul 31 05:20:35 PM PDT 24
Finished Jul 31 05:20:44 PM PDT 24
Peak memory 221824 kb
Host smart-58daaf60-c18c-41e6-83ce-0a67488975db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613293092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2613293092
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3603227724
Short name T278
Test name
Test status
Simulation time 243991558 ps
CPU time 1.18 seconds
Started Jul 31 05:20:38 PM PDT 24
Finished Jul 31 05:20:39 PM PDT 24
Peak memory 217484 kb
Host smart-3bb410a0-7fd7-4b59-808f-d6743007414d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603227724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3603227724
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3216684582
Short name T4
Test name
Test status
Simulation time 165618380 ps
CPU time 0.86 seconds
Started Jul 31 05:20:20 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 200152 kb
Host smart-92eed4b6-e9a3-4964-9024-e76d385505a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216684582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3216684582
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3317689711
Short name T363
Test name
Test status
Simulation time 870046429 ps
CPU time 4.43 seconds
Started Jul 31 05:20:29 PM PDT 24
Finished Jul 31 05:20:33 PM PDT 24
Peak memory 200592 kb
Host smart-c86c2295-1d35-4a7d-9a08-5dbca745ab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317689711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3317689711
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1823621044
Short name T429
Test name
Test status
Simulation time 101568317 ps
CPU time 0.95 seconds
Started Jul 31 05:21:03 PM PDT 24
Finished Jul 31 05:21:09 PM PDT 24
Peak memory 200348 kb
Host smart-b799c3b0-91a6-4750-a878-a0703dce22dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823621044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1823621044
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2012809833
Short name T198
Test name
Test status
Simulation time 250077850 ps
CPU time 1.56 seconds
Started Jul 31 05:20:38 PM PDT 24
Finished Jul 31 05:20:39 PM PDT 24
Peak memory 200444 kb
Host smart-209491b1-503e-42c9-b434-c36df04a18ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012809833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2012809833
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3856194134
Short name T325
Test name
Test status
Simulation time 10596940709 ps
CPU time 35.2 seconds
Started Jul 31 05:20:36 PM PDT 24
Finished Jul 31 05:21:16 PM PDT 24
Peak memory 200504 kb
Host smart-3b4233ba-fd7a-4ece-b232-ab6324c09c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856194134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3856194134
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1483132793
Short name T506
Test name
Test status
Simulation time 158738238 ps
CPU time 1.86 seconds
Started Jul 31 05:20:45 PM PDT 24
Finished Jul 31 05:20:47 PM PDT 24
Peak memory 200256 kb
Host smart-6fe662d6-00d2-495a-9f0d-6732b178bf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483132793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1483132793
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3292765369
Short name T211
Test name
Test status
Simulation time 85772903 ps
CPU time 0.93 seconds
Started Jul 31 05:20:26 PM PDT 24
Finished Jul 31 05:20:27 PM PDT 24
Peak memory 200356 kb
Host smart-ae55f7ce-f1f2-405b-9407-5ee6783ab729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292765369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3292765369
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.694690330
Short name T157
Test name
Test status
Simulation time 62483605 ps
CPU time 0.74 seconds
Started Jul 31 05:20:32 PM PDT 24
Finished Jul 31 05:20:32 PM PDT 24
Peak memory 200124 kb
Host smart-3cc10b0d-0838-4a14-b903-41f9dffc8f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694690330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.694690330
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1840936272
Short name T29
Test name
Test status
Simulation time 2341512268 ps
CPU time 7.75 seconds
Started Jul 31 05:20:42 PM PDT 24
Finished Jul 31 05:20:55 PM PDT 24
Peak memory 221780 kb
Host smart-79cfea9f-c648-4213-85c9-382561c798db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840936272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1840936272
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3501916424
Short name T318
Test name
Test status
Simulation time 244735051 ps
CPU time 1.19 seconds
Started Jul 31 05:20:39 PM PDT 24
Finished Jul 31 05:20:40 PM PDT 24
Peak memory 217636 kb
Host smart-5fa72f6e-bccf-4d19-96ac-cf54003d53f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501916424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3501916424
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.595542853
Short name T17
Test name
Test status
Simulation time 152250261 ps
CPU time 0.83 seconds
Started Jul 31 05:20:45 PM PDT 24
Finished Jul 31 05:20:46 PM PDT 24
Peak memory 200160 kb
Host smart-06e823db-c29f-46d3-ba2e-9ab4c6b3c40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595542853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.595542853
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3859643440
Short name T36
Test name
Test status
Simulation time 1641039884 ps
CPU time 6.04 seconds
Started Jul 31 05:20:45 PM PDT 24
Finished Jul 31 05:20:56 PM PDT 24
Peak memory 200568 kb
Host smart-32cac78f-c2f8-410c-87d1-a7c7883e89a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859643440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3859643440
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1254447773
Short name T486
Test name
Test status
Simulation time 173566291 ps
CPU time 1.2 seconds
Started Jul 31 05:20:28 PM PDT 24
Finished Jul 31 05:20:30 PM PDT 24
Peak memory 200340 kb
Host smart-8444c7d1-156c-436f-8ada-94ff7a6ef07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254447773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1254447773
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2844949182
Short name T536
Test name
Test status
Simulation time 195125484 ps
CPU time 1.42 seconds
Started Jul 31 05:20:36 PM PDT 24
Finished Jul 31 05:20:37 PM PDT 24
Peak memory 200488 kb
Host smart-c1cbf07b-6818-4a2d-a8de-8e331ed24f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844949182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2844949182
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1635932740
Short name T200
Test name
Test status
Simulation time 214693279 ps
CPU time 1.4 seconds
Started Jul 31 05:20:47 PM PDT 24
Finished Jul 31 05:20:49 PM PDT 24
Peak memory 200468 kb
Host smart-2db28d07-8882-4e6a-9be9-ff059d79e42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635932740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1635932740
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2215741731
Short name T222
Test name
Test status
Simulation time 135945424 ps
CPU time 1.63 seconds
Started Jul 31 05:20:32 PM PDT 24
Finished Jul 31 05:20:34 PM PDT 24
Peak memory 200312 kb
Host smart-77c049e8-b538-4802-8dd1-23a50aa8869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215741731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2215741731
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2266997377
Short name T503
Test name
Test status
Simulation time 131408714 ps
CPU time 0.99 seconds
Started Jul 31 05:20:40 PM PDT 24
Finished Jul 31 05:20:42 PM PDT 24
Peak memory 200332 kb
Host smart-5d9b14f0-d46c-42af-969a-a118cdca029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266997377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2266997377
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.226231712
Short name T189
Test name
Test status
Simulation time 84956077 ps
CPU time 0.8 seconds
Started Jul 31 05:20:35 PM PDT 24
Finished Jul 31 05:20:35 PM PDT 24
Peak memory 200180 kb
Host smart-12cbd132-d211-4169-a24e-0ec6fe83bdc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226231712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.226231712
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.205621880
Short name T54
Test name
Test status
Simulation time 1232169211 ps
CPU time 5.77 seconds
Started Jul 31 05:20:44 PM PDT 24
Finished Jul 31 05:20:50 PM PDT 24
Peak memory 221604 kb
Host smart-f6859389-a259-4a17-94e4-53d328804eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205621880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.205621880
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4130409618
Short name T499
Test name
Test status
Simulation time 245242091 ps
CPU time 1.04 seconds
Started Jul 31 05:20:25 PM PDT 24
Finished Jul 31 05:20:26 PM PDT 24
Peak memory 217580 kb
Host smart-aca21868-1837-4de0-9a5f-ef2a3595331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130409618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4130409618
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.786836917
Short name T210
Test name
Test status
Simulation time 198606086 ps
CPU time 0.97 seconds
Started Jul 31 05:20:43 PM PDT 24
Finished Jul 31 05:20:49 PM PDT 24
Peak memory 200160 kb
Host smart-17f11f8d-e186-4e9a-9ca2-7ab941f72fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786836917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.786836917
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1753889613
Short name T186
Test name
Test status
Simulation time 676738663 ps
CPU time 3.42 seconds
Started Jul 31 05:20:37 PM PDT 24
Finished Jul 31 05:20:41 PM PDT 24
Peak memory 200548 kb
Host smart-a3027f7d-0f52-4d7a-9045-fabf09103d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753889613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1753889613
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.283689053
Short name T381
Test name
Test status
Simulation time 174996143 ps
CPU time 1.2 seconds
Started Jul 31 05:20:54 PM PDT 24
Finished Jul 31 05:20:55 PM PDT 24
Peak memory 200408 kb
Host smart-a38aa93a-b850-4d23-8f47-f54640527bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283689053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.283689053
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3471802596
Short name T35
Test name
Test status
Simulation time 112404865 ps
CPU time 1.11 seconds
Started Jul 31 05:20:36 PM PDT 24
Finished Jul 31 05:20:37 PM PDT 24
Peak memory 200492 kb
Host smart-6ea5f39a-cc43-432c-af41-205b45e5c225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471802596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3471802596
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.871612347
Short name T225
Test name
Test status
Simulation time 4990443122 ps
CPU time 17.63 seconds
Started Jul 31 05:20:38 PM PDT 24
Finished Jul 31 05:20:55 PM PDT 24
Peak memory 208840 kb
Host smart-6eb6946b-82b8-4d82-a88c-23b6f1806dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871612347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.871612347
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3354509674
Short name T224
Test name
Test status
Simulation time 447784318 ps
CPU time 2.24 seconds
Started Jul 31 05:20:37 PM PDT 24
Finished Jul 31 05:20:40 PM PDT 24
Peak memory 200280 kb
Host smart-55edf912-17b7-4376-a065-05ddf7c8513e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354509674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3354509674
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.148601773
Short name T195
Test name
Test status
Simulation time 163150679 ps
CPU time 1.14 seconds
Started Jul 31 05:20:33 PM PDT 24
Finished Jul 31 05:20:34 PM PDT 24
Peak memory 200308 kb
Host smart-0a669130-0415-4c01-a31f-a9ef6e49ca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148601773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.148601773
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1155088662
Short name T323
Test name
Test status
Simulation time 69329410 ps
CPU time 0.75 seconds
Started Jul 31 05:20:49 PM PDT 24
Finished Jul 31 05:20:50 PM PDT 24
Peak memory 200304 kb
Host smart-33ae0cd3-5bcc-4b98-a96c-81de0d2a007a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155088662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1155088662
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4086259095
Short name T310
Test name
Test status
Simulation time 1228542188 ps
CPU time 5.92 seconds
Started Jul 31 05:20:30 PM PDT 24
Finished Jul 31 05:20:36 PM PDT 24
Peak memory 217760 kb
Host smart-7e4d4c46-6fef-432d-8287-cb54906ec0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086259095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4086259095
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2936754981
Short name T240
Test name
Test status
Simulation time 244833315 ps
CPU time 1.05 seconds
Started Jul 31 05:20:30 PM PDT 24
Finished Jul 31 05:20:32 PM PDT 24
Peak memory 217480 kb
Host smart-9b6744cf-67d7-4687-a733-5beb778ade11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936754981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2936754981
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1257590840
Short name T380
Test name
Test status
Simulation time 165276533 ps
CPU time 0.83 seconds
Started Jul 31 05:20:45 PM PDT 24
Finished Jul 31 05:20:51 PM PDT 24
Peak memory 200116 kb
Host smart-d31ca6f5-00f6-4997-b7e3-de035addde2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257590840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1257590840
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3663816347
Short name T474
Test name
Test status
Simulation time 1750911700 ps
CPU time 6.16 seconds
Started Jul 31 05:20:43 PM PDT 24
Finished Jul 31 05:20:49 PM PDT 24
Peak memory 200560 kb
Host smart-22620060-0155-4c42-af4e-5efecbb34887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663816347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3663816347
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.725790925
Short name T283
Test name
Test status
Simulation time 146323522 ps
CPU time 1.05 seconds
Started Jul 31 05:20:51 PM PDT 24
Finished Jul 31 05:20:52 PM PDT 24
Peak memory 200392 kb
Host smart-2fa459ac-23d1-4a87-add2-9ec23843b0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725790925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.725790925
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3065906894
Short name T533
Test name
Test status
Simulation time 187856106 ps
CPU time 1.32 seconds
Started Jul 31 05:20:29 PM PDT 24
Finished Jul 31 05:20:30 PM PDT 24
Peak memory 200512 kb
Host smart-4b5edc1f-a36e-41fa-aece-2c55ccc8bbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065906894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3065906894
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2564193459
Short name T245
Test name
Test status
Simulation time 7961044656 ps
CPU time 34.66 seconds
Started Jul 31 05:20:31 PM PDT 24
Finished Jul 31 05:21:05 PM PDT 24
Peak memory 200632 kb
Host smart-2505fa68-97bc-45c1-9e52-35580f0f77a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564193459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2564193459
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.924239022
Short name T132
Test name
Test status
Simulation time 458291380 ps
CPU time 2.83 seconds
Started Jul 31 05:20:33 PM PDT 24
Finished Jul 31 05:20:36 PM PDT 24
Peak memory 200320 kb
Host smart-0f759e86-6ef2-47b6-af45-135127e2fd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924239022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.924239022
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2878632483
Short name T491
Test name
Test status
Simulation time 131023001 ps
CPU time 0.93 seconds
Started Jul 31 05:20:44 PM PDT 24
Finished Jul 31 05:20:45 PM PDT 24
Peak memory 200356 kb
Host smart-54a50811-5848-44ae-b749-965dc1494013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878632483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2878632483
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3309727722
Short name T357
Test name
Test status
Simulation time 100699864 ps
CPU time 0.8 seconds
Started Jul 31 05:20:48 PM PDT 24
Finished Jul 31 05:20:48 PM PDT 24
Peak memory 200168 kb
Host smart-99f39a27-0f3a-4b15-86a2-938fd6432551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309727722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3309727722
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.799256224
Short name T496
Test name
Test status
Simulation time 2355846845 ps
CPU time 8.08 seconds
Started Jul 31 05:20:41 PM PDT 24
Finished Jul 31 05:20:49 PM PDT 24
Peak memory 217928 kb
Host smart-d190958a-eeca-4e6a-b221-a42449b874c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799256224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.799256224
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2046093443
Short name T281
Test name
Test status
Simulation time 245860782 ps
CPU time 1.09 seconds
Started Jul 31 05:20:35 PM PDT 24
Finished Jul 31 05:20:36 PM PDT 24
Peak memory 217580 kb
Host smart-02b8a670-8d95-42be-9522-648c7c38e0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046093443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2046093443
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1434977062
Short name T462
Test name
Test status
Simulation time 205403077 ps
CPU time 0.99 seconds
Started Jul 31 05:20:47 PM PDT 24
Finished Jul 31 05:20:48 PM PDT 24
Peak memory 200156 kb
Host smart-da5692b1-0f8c-4fbc-8780-2f9fb8915f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434977062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1434977062
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3910866084
Short name T106
Test name
Test status
Simulation time 1925422262 ps
CPU time 6.78 seconds
Started Jul 31 05:21:04 PM PDT 24
Finished Jul 31 05:21:11 PM PDT 24
Peak memory 200560 kb
Host smart-b7b4d41e-b494-4b85-b95e-505e6ad07c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910866084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3910866084
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1625596479
Short name T184
Test name
Test status
Simulation time 169938875 ps
CPU time 1.16 seconds
Started Jul 31 05:20:39 PM PDT 24
Finished Jul 31 05:20:40 PM PDT 24
Peak memory 200352 kb
Host smart-b6b6d5db-1bc0-4ebc-95a5-e005a6f54d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625596479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1625596479
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.606475621
Short name T140
Test name
Test status
Simulation time 113775186 ps
CPU time 1.15 seconds
Started Jul 31 05:20:50 PM PDT 24
Finished Jul 31 05:20:52 PM PDT 24
Peak memory 200468 kb
Host smart-534d1303-04b0-4d57-bcaf-08c9cf3189be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606475621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.606475621
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2832295218
Short name T361
Test name
Test status
Simulation time 193580609 ps
CPU time 1.55 seconds
Started Jul 31 05:20:31 PM PDT 24
Finished Jul 31 05:20:32 PM PDT 24
Peak memory 200264 kb
Host smart-82941754-f1f0-4254-868f-a4998fbe4ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832295218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2832295218
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.550767981
Short name T411
Test name
Test status
Simulation time 267860950 ps
CPU time 1.86 seconds
Started Jul 31 05:20:36 PM PDT 24
Finished Jul 31 05:20:38 PM PDT 24
Peak memory 200300 kb
Host smart-17cb93b9-c401-4c56-8615-8bdc2eae1d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550767981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.550767981
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1448933041
Short name T193
Test name
Test status
Simulation time 68030060 ps
CPU time 0.76 seconds
Started Jul 31 05:20:48 PM PDT 24
Finished Jul 31 05:20:49 PM PDT 24
Peak memory 200348 kb
Host smart-bec4bbce-ce26-4a30-b996-6d3604a70413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448933041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1448933041
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.453220529
Short name T244
Test name
Test status
Simulation time 72533798 ps
CPU time 0.77 seconds
Started Jul 31 05:20:42 PM PDT 24
Finished Jul 31 05:20:43 PM PDT 24
Peak memory 200088 kb
Host smart-a7842fd6-cbce-4b5b-ba8c-507fb1302d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453220529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.453220529
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.4028237933
Short name T470
Test name
Test status
Simulation time 2349514349 ps
CPU time 8.15 seconds
Started Jul 31 05:20:47 PM PDT 24
Finished Jul 31 05:20:56 PM PDT 24
Peak memory 217956 kb
Host smart-062ad478-e39d-44c0-9c16-35cf83f3e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028237933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.4028237933
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1451926013
Short name T404
Test name
Test status
Simulation time 244239355 ps
CPU time 1.19 seconds
Started Jul 31 05:20:48 PM PDT 24
Finished Jul 31 05:20:49 PM PDT 24
Peak memory 217436 kb
Host smart-839b51bb-df8e-4765-a5a7-8212bbf34c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451926013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1451926013
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3818591218
Short name T413
Test name
Test status
Simulation time 142536123 ps
CPU time 0.89 seconds
Started Jul 31 05:20:47 PM PDT 24
Finished Jul 31 05:20:48 PM PDT 24
Peak memory 200132 kb
Host smart-a9047720-5ef3-42ac-a579-0027641d4380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818591218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3818591218
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3290963256
Short name T330
Test name
Test status
Simulation time 1358120861 ps
CPU time 5.74 seconds
Started Jul 31 05:20:56 PM PDT 24
Finished Jul 31 05:21:01 PM PDT 24
Peak memory 200552 kb
Host smart-a7d46bac-0ccf-45f2-bbf6-4eebaa6c0b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290963256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3290963256
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3069308161
Short name T422
Test name
Test status
Simulation time 185069411 ps
CPU time 1.13 seconds
Started Jul 31 05:20:40 PM PDT 24
Finished Jul 31 05:20:42 PM PDT 24
Peak memory 200340 kb
Host smart-49ad120b-74a4-4059-85b2-22904388f228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069308161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3069308161
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1326082588
Short name T467
Test name
Test status
Simulation time 120030714 ps
CPU time 1.18 seconds
Started Jul 31 05:20:53 PM PDT 24
Finished Jul 31 05:20:55 PM PDT 24
Peak memory 200460 kb
Host smart-124e3123-cbf4-4cd6-b845-8c439a2c178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326082588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1326082588
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2664230656
Short name T273
Test name
Test status
Simulation time 10735831866 ps
CPU time 40.06 seconds
Started Jul 31 05:21:02 PM PDT 24
Finished Jul 31 05:21:42 PM PDT 24
Peak memory 208828 kb
Host smart-4747fea6-3e4c-4ea0-a2f4-e8e133edc8e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664230656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2664230656
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2232291530
Short name T177
Test name
Test status
Simulation time 300908555 ps
CPU time 1.93 seconds
Started Jul 31 05:20:36 PM PDT 24
Finished Jul 31 05:20:38 PM PDT 24
Peak memory 208492 kb
Host smart-110eb00e-1ad8-4167-93f8-490410884d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232291530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2232291530
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.588675797
Short name T394
Test name
Test status
Simulation time 79664762 ps
CPU time 0.82 seconds
Started Jul 31 05:20:34 PM PDT 24
Finished Jul 31 05:20:35 PM PDT 24
Peak memory 200344 kb
Host smart-8b1f1a8a-4932-460e-a377-80b46826773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588675797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.588675797
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2257952652
Short name T445
Test name
Test status
Simulation time 83324569 ps
CPU time 0.81 seconds
Started Jul 31 05:20:55 PM PDT 24
Finished Jul 31 05:20:56 PM PDT 24
Peak memory 200212 kb
Host smart-4d269a51-e6bf-4e37-9db1-6bd30905389c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257952652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2257952652
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3242417185
Short name T262
Test name
Test status
Simulation time 1228088015 ps
CPU time 5.31 seconds
Started Jul 31 05:20:42 PM PDT 24
Finished Jul 31 05:20:47 PM PDT 24
Peak memory 217384 kb
Host smart-9c16690c-26ac-4164-b0a2-088ab5bec75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242417185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3242417185
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1676042667
Short name T304
Test name
Test status
Simulation time 244956611 ps
CPU time 1.03 seconds
Started Jul 31 05:20:44 PM PDT 24
Finished Jul 31 05:20:45 PM PDT 24
Peak memory 217412 kb
Host smart-7a9888d4-857b-4e03-bd5b-8bb45a3bc26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676042667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1676042667
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.442712593
Short name T482
Test name
Test status
Simulation time 177821638 ps
CPU time 0.87 seconds
Started Jul 31 05:20:45 PM PDT 24
Finished Jul 31 05:21:01 PM PDT 24
Peak memory 200148 kb
Host smart-b8bb8aa5-3c62-4bf4-bb68-9dc061a76d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442712593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.442712593
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1524216713
Short name T285
Test name
Test status
Simulation time 1764629890 ps
CPU time 6.86 seconds
Started Jul 31 05:20:51 PM PDT 24
Finished Jul 31 05:20:58 PM PDT 24
Peak memory 200604 kb
Host smart-71fd64a9-a8ac-4ec8-9c15-c4226902af3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524216713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1524216713
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.4142532538
Short name T456
Test name
Test status
Simulation time 149788787 ps
CPU time 1.13 seconds
Started Jul 31 05:20:41 PM PDT 24
Finished Jul 31 05:20:43 PM PDT 24
Peak memory 200272 kb
Host smart-1b87d11f-fd85-4867-b5b5-a90f49958760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142532538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.4142532538
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2968824287
Short name T1
Test name
Test status
Simulation time 116986699 ps
CPU time 1.15 seconds
Started Jul 31 05:20:35 PM PDT 24
Finished Jul 31 05:20:36 PM PDT 24
Peak memory 200444 kb
Host smart-93b5248b-33d7-482b-9f87-390cec32ff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968824287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2968824287
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2781678213
Short name T514
Test name
Test status
Simulation time 3095348329 ps
CPU time 11.03 seconds
Started Jul 31 05:20:41 PM PDT 24
Finished Jul 31 05:20:52 PM PDT 24
Peak memory 200612 kb
Host smart-15f9112f-8a73-4b96-912b-f8feddbd28a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781678213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2781678213
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.177208763
Short name T88
Test name
Test status
Simulation time 129112565 ps
CPU time 1.65 seconds
Started Jul 31 05:20:46 PM PDT 24
Finished Jul 31 05:20:53 PM PDT 24
Peak memory 200296 kb
Host smart-bbb1d1d0-2636-4c4a-9947-cd3e6062c59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177208763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.177208763
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1189220826
Short name T165
Test name
Test status
Simulation time 149539709 ps
CPU time 1.16 seconds
Started Jul 31 05:20:49 PM PDT 24
Finished Jul 31 05:20:51 PM PDT 24
Peak memory 200284 kb
Host smart-a3bbd160-49ea-49da-9539-7844d35cef9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189220826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1189220826
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.501263893
Short name T311
Test name
Test status
Simulation time 77820237 ps
CPU time 0.79 seconds
Started Jul 31 05:19:43 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 200196 kb
Host smart-05ecc738-605f-44df-9d05-9278530ee87e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501263893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.501263893
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.479793292
Short name T51
Test name
Test status
Simulation time 1891581717 ps
CPU time 6.66 seconds
Started Jul 31 05:19:48 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 221672 kb
Host smart-94c2376f-29ae-4d54-a9d9-43d2c5592632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479793292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.479793292
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2565148135
Short name T284
Test name
Test status
Simulation time 244691893 ps
CPU time 1.04 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 217472 kb
Host smart-ee9fe4b6-75af-4b7e-8776-eaef3d54b546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565148135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2565148135
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3128044149
Short name T16
Test name
Test status
Simulation time 89576409 ps
CPU time 0.73 seconds
Started Jul 31 05:19:43 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 200160 kb
Host smart-cbbbca23-c4e7-4573-8f26-d356ed14b339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128044149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3128044149
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.54947056
Short name T131
Test name
Test status
Simulation time 1558338171 ps
CPU time 5.94 seconds
Started Jul 31 05:19:38 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 200596 kb
Host smart-350cdf01-8ef4-4103-9077-65547b0a94e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54947056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.54947056
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1866702990
Short name T473
Test name
Test status
Simulation time 156440395 ps
CPU time 1.07 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 200280 kb
Host smart-0f4de8a3-5055-4f9f-a0a9-2048097ce56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866702990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1866702990
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1042243864
Short name T518
Test name
Test status
Simulation time 248833868 ps
CPU time 1.6 seconds
Started Jul 31 05:19:30 PM PDT 24
Finished Jul 31 05:19:31 PM PDT 24
Peak memory 200516 kb
Host smart-d1f3da32-1a72-4865-88a4-b8202ab25c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042243864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1042243864
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.669808822
Short name T301
Test name
Test status
Simulation time 4932644399 ps
CPU time 17.15 seconds
Started Jul 31 05:19:39 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 200620 kb
Host smart-1006e3a1-9a5a-4088-8487-09de712fbdf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669808822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.669808822
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3548909765
Short name T202
Test name
Test status
Simulation time 403783053 ps
CPU time 2.31 seconds
Started Jul 31 05:19:46 PM PDT 24
Finished Jul 31 05:19:49 PM PDT 24
Peak memory 200224 kb
Host smart-652597e9-b996-47cc-8340-42a3f63f08d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548909765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3548909765
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.241563801
Short name T158
Test name
Test status
Simulation time 84373516 ps
CPU time 0.9 seconds
Started Jul 31 05:19:50 PM PDT 24
Finished Jul 31 05:19:51 PM PDT 24
Peak memory 200292 kb
Host smart-56bf9386-a8ec-4017-b1b7-df2ec933bdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241563801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.241563801
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3702304278
Short name T360
Test name
Test status
Simulation time 69604837 ps
CPU time 0.85 seconds
Started Jul 31 05:19:46 PM PDT 24
Finished Jul 31 05:19:47 PM PDT 24
Peak memory 200156 kb
Host smart-1eacf80b-eba1-4ff6-a0da-dcef44adf087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702304278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3702304278
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3594582692
Short name T375
Test name
Test status
Simulation time 2365253813 ps
CPU time 7.91 seconds
Started Jul 31 05:19:40 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 217876 kb
Host smart-5dd2e17d-86df-499e-a118-0b0e5b6c5857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594582692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3594582692
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1784674800
Short name T229
Test name
Test status
Simulation time 244782567 ps
CPU time 1.1 seconds
Started Jul 31 05:19:41 PM PDT 24
Finished Jul 31 05:19:42 PM PDT 24
Peak memory 217556 kb
Host smart-664cefbe-e9ac-4b3f-bc7e-58181302edae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784674800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1784674800
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.4244405163
Short name T341
Test name
Test status
Simulation time 187483705 ps
CPU time 0.92 seconds
Started Jul 31 05:19:47 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 200160 kb
Host smart-4fb26e36-77d6-420a-88de-06e4bb60b907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244405163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.4244405163
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.847529404
Short name T255
Test name
Test status
Simulation time 702617043 ps
CPU time 3.54 seconds
Started Jul 31 05:19:44 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 200560 kb
Host smart-82560a93-cf77-4084-9b2c-bb1147e4abe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847529404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.847529404
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3467191211
Short name T151
Test name
Test status
Simulation time 98204186 ps
CPU time 0.96 seconds
Started Jul 31 05:19:43 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 200328 kb
Host smart-4dcbdccc-e34f-4dbd-bf87-0d62686aa07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467191211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3467191211
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.4067518155
Short name T449
Test name
Test status
Simulation time 125620844 ps
CPU time 1.18 seconds
Started Jul 31 05:19:45 PM PDT 24
Finished Jul 31 05:19:51 PM PDT 24
Peak memory 200500 kb
Host smart-4e1ab918-f338-4e97-a9b7-3d3fec804217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067518155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4067518155
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3486407095
Short name T130
Test name
Test status
Simulation time 5647827167 ps
CPU time 21.94 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:20:16 PM PDT 24
Peak memory 200628 kb
Host smart-941aa61d-f641-4516-a4db-840e1424bb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486407095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3486407095
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.819949843
Short name T459
Test name
Test status
Simulation time 147863966 ps
CPU time 1.77 seconds
Started Jul 31 05:19:50 PM PDT 24
Finished Jul 31 05:19:56 PM PDT 24
Peak memory 200296 kb
Host smart-f2a80d08-05a2-499f-bd34-8862a1305df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819949843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.819949843
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.788200311
Short name T153
Test name
Test status
Simulation time 104862916 ps
CPU time 0.95 seconds
Started Jul 31 05:19:47 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 200276 kb
Host smart-9d0ef5ef-afe2-494f-a6f7-0c8a367a9595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788200311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.788200311
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1549589625
Short name T250
Test name
Test status
Simulation time 84653711 ps
CPU time 0.79 seconds
Started Jul 31 05:19:43 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 200112 kb
Host smart-a4ff3bc8-5577-4e0c-a446-eda1810009cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549589625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1549589625
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2624354114
Short name T475
Test name
Test status
Simulation time 1224868672 ps
CPU time 5.29 seconds
Started Jul 31 05:19:39 PM PDT 24
Finished Jul 31 05:19:44 PM PDT 24
Peak memory 217732 kb
Host smart-836078a6-8d17-49f2-83cc-a05076282938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624354114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2624354114
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3462804735
Short name T396
Test name
Test status
Simulation time 244124743 ps
CPU time 1 seconds
Started Jul 31 05:19:42 PM PDT 24
Finished Jul 31 05:19:43 PM PDT 24
Peak memory 217516 kb
Host smart-a1e7a5b2-9ba1-456d-a57e-4787f94eac38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462804735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3462804735
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1075572464
Short name T19
Test name
Test status
Simulation time 225946511 ps
CPU time 0.89 seconds
Started Jul 31 05:19:47 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 200048 kb
Host smart-0b96723b-4e9a-4904-8c61-6e47a50cdb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075572464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1075572464
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3703679415
Short name T197
Test name
Test status
Simulation time 1646786259 ps
CPU time 6.86 seconds
Started Jul 31 05:19:47 PM PDT 24
Finished Jul 31 05:19:54 PM PDT 24
Peak memory 200524 kb
Host smart-bb980983-0e5d-4ae7-976f-b5ce3f444104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703679415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3703679415
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1563934309
Short name T34
Test name
Test status
Simulation time 152940814 ps
CPU time 1.12 seconds
Started Jul 31 05:19:48 PM PDT 24
Finished Jul 31 05:19:49 PM PDT 24
Peak memory 200368 kb
Host smart-452f1e15-5fc9-4701-912a-9408107bec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563934309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1563934309
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3736664403
Short name T347
Test name
Test status
Simulation time 222523590 ps
CPU time 1.41 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:53 PM PDT 24
Peak memory 200452 kb
Host smart-a082cc97-99f1-493d-b0bf-0634712c7724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736664403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3736664403
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3959145185
Short name T87
Test name
Test status
Simulation time 21400997395 ps
CPU time 66.23 seconds
Started Jul 31 05:19:43 PM PDT 24
Finished Jul 31 05:20:49 PM PDT 24
Peak memory 200476 kb
Host smart-064d5bee-4b1f-4349-955a-6c7073972796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959145185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3959145185
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2187459707
Short name T178
Test name
Test status
Simulation time 321028668 ps
CPU time 2.05 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:54 PM PDT 24
Peak memory 200276 kb
Host smart-e2448afb-47dd-4dff-99a0-fd008518dbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187459707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2187459707
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1833390525
Short name T264
Test name
Test status
Simulation time 98867466 ps
CPU time 0.99 seconds
Started Jul 31 05:19:39 PM PDT 24
Finished Jul 31 05:19:40 PM PDT 24
Peak memory 200352 kb
Host smart-1a16d9c0-c8ba-4289-85ac-d17a02ef8e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833390525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1833390525
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1811595042
Short name T461
Test name
Test status
Simulation time 128902387 ps
CPU time 0.85 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200096 kb
Host smart-99dcf392-9376-4fb2-999d-995528b06ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811595042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1811595042
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2931914740
Short name T471
Test name
Test status
Simulation time 1248380152 ps
CPU time 5.17 seconds
Started Jul 31 05:19:56 PM PDT 24
Finished Jul 31 05:20:01 PM PDT 24
Peak memory 217716 kb
Host smart-f9f369d6-06f7-48bf-b0a3-6c5e0e365ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931914740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2931914740
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2789818918
Short name T433
Test name
Test status
Simulation time 243451837 ps
CPU time 1.06 seconds
Started Jul 31 05:19:57 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 217484 kb
Host smart-6eec487a-00d7-4ff0-beeb-f64622716be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789818918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2789818918
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2294751397
Short name T493
Test name
Test status
Simulation time 101941694 ps
CPU time 0.78 seconds
Started Jul 31 05:19:59 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 200300 kb
Host smart-50aa2759-7516-4fab-84f7-743e8ca6a662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294751397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2294751397
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2630621964
Short name T412
Test name
Test status
Simulation time 1154415445 ps
CPU time 5.65 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:20:01 PM PDT 24
Peak memory 200468 kb
Host smart-0b3148e2-a14b-410e-b8e5-a0d18226006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630621964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2630621964
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4092083425
Short name T173
Test name
Test status
Simulation time 112410590 ps
CPU time 1.06 seconds
Started Jul 31 05:19:42 PM PDT 24
Finished Jul 31 05:19:43 PM PDT 24
Peak memory 200280 kb
Host smart-edb8f308-39ec-4a65-ac80-0390d996b5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092083425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4092083425
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2137321203
Short name T540
Test name
Test status
Simulation time 202790110 ps
CPU time 1.49 seconds
Started Jul 31 05:19:52 PM PDT 24
Finished Jul 31 05:19:54 PM PDT 24
Peak memory 200452 kb
Host smart-bfdff44e-cf58-4877-8452-83f856ed6a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137321203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2137321203
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2154915937
Short name T543
Test name
Test status
Simulation time 4072358730 ps
CPU time 17.74 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:20:09 PM PDT 24
Peak memory 200580 kb
Host smart-f2a77cc1-9e6d-456a-bee3-b096d9b225c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154915937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2154915937
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2735847610
Short name T288
Test name
Test status
Simulation time 125823672 ps
CPU time 1.59 seconds
Started Jul 31 05:19:54 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 208504 kb
Host smart-3cc42e90-d094-4409-8a02-92b197291f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735847610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2735847610
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.17595393
Short name T260
Test name
Test status
Simulation time 137581516 ps
CPU time 1.17 seconds
Started Jul 31 05:19:46 PM PDT 24
Finished Jul 31 05:19:47 PM PDT 24
Peak memory 200288 kb
Host smart-0104e355-8017-4c19-bf91-0c535bd769b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17595393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.17595393
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.712086379
Short name T390
Test name
Test status
Simulation time 68524957 ps
CPU time 0.74 seconds
Started Jul 31 05:19:49 PM PDT 24
Finished Jul 31 05:19:50 PM PDT 24
Peak memory 200132 kb
Host smart-53f9e575-b291-4f9f-bc84-8643e20fea76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712086379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.712086379
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2540493110
Short name T358
Test name
Test status
Simulation time 1902244514 ps
CPU time 7.95 seconds
Started Jul 31 05:19:46 PM PDT 24
Finished Jul 31 05:19:55 PM PDT 24
Peak memory 217740 kb
Host smart-11e7b764-09ec-4d13-a525-bde0e999202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540493110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2540493110
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1045361175
Short name T271
Test name
Test status
Simulation time 245402301 ps
CPU time 1.18 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 217636 kb
Host smart-e5296e7b-6a2c-4ea0-93dc-cd0355be4273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045361175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1045361175
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2040011346
Short name T431
Test name
Test status
Simulation time 166290755 ps
CPU time 0.82 seconds
Started Jul 31 05:19:58 PM PDT 24
Finished Jul 31 05:19:59 PM PDT 24
Peak memory 200156 kb
Host smart-450e0936-7559-4905-a808-04bbb51e36f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040011346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2040011346
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.4240174267
Short name T228
Test name
Test status
Simulation time 2081541878 ps
CPU time 8.15 seconds
Started Jul 31 05:19:46 PM PDT 24
Finished Jul 31 05:19:54 PM PDT 24
Peak memory 200544 kb
Host smart-0fb0f615-1d6f-473f-bd79-7089522785b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240174267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.4240174267
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.466995373
Short name T8
Test name
Test status
Simulation time 98283400 ps
CPU time 0.99 seconds
Started Jul 31 05:19:48 PM PDT 24
Finished Jul 31 05:19:49 PM PDT 24
Peak memory 200496 kb
Host smart-3eb5bfaf-adb6-49c7-bc2a-37d46cc55a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466995373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.466995373
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2622686951
Short name T160
Test name
Test status
Simulation time 262321780 ps
CPU time 1.55 seconds
Started Jul 31 05:19:50 PM PDT 24
Finished Jul 31 05:19:52 PM PDT 24
Peak memory 200524 kb
Host smart-c235e6dd-09b6-4d56-9ff3-95791fffe6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622686951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2622686951
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.4129401746
Short name T82
Test name
Test status
Simulation time 1315329829 ps
CPU time 6.41 seconds
Started Jul 31 05:19:51 PM PDT 24
Finished Jul 31 05:19:58 PM PDT 24
Peak memory 200536 kb
Host smart-326782dc-e057-490d-970c-149cadaef7c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129401746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.4129401746
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.801018876
Short name T495
Test name
Test status
Simulation time 262609264 ps
CPU time 1.39 seconds
Started Jul 31 05:19:55 PM PDT 24
Finished Jul 31 05:19:57 PM PDT 24
Peak memory 200496 kb
Host smart-157f566a-7d2b-4f7c-b1d9-aadbf86880ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801018876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.801018876
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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