Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8909

1

T4

21

T5

37

T8

19

auto[1]

11921

1

T4

80

T5

25

T8

82

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6362	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6965	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3241	1			T4	17		T5	7		T8	13
reset_info_cp[4]	4261	1			T4	13		T5	18		T8	19
reset_info_cp[8]	125	1			T4	1		T5	1		T8	1
reset_info_cp[16]	122	1			T4	1		T8	1		T11	1
reset_info_cp[32]	124	1			T4	2		T8	1		T9	2
reset_info_cp[64]	132	1			T11	3		T15	1		T25	4
reset_info_cp[128]	118	1			T11	4		T136	1		T86	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3354	1			T4	21		T5	10		T8	19
reset_info_cp[1]	auto[1]	2991	1			T4	5		T5	10		T8	7
reset_info_cp[2]	auto[0]	1014	1			T5	3		T9	7		T11	24
reset_info_cp[2]	auto[1]	2227	1			T4	17		T5	4		T8	13
reset_info_cp[4]	auto[0]	1565	1			T5	14		T9	4		T11	37
reset_info_cp[4]	auto[1]	2696	1			T4	13		T5	4		T8	19
reset_info_cp[8]	auto[0]	53	1			T25	1		T84	1		T86	1
reset_info_cp[8]	auto[1]	72	1			T4	1		T5	1		T8	1
reset_info_cp[16]	auto[0]	47	1			T24	1		T84	1		T133	1
reset_info_cp[16]	auto[1]	75	1			T4	1		T8	1		T11	1
reset_info_cp[32]	auto[0]	53	1			T9	1		T11	1		T133	1
reset_info_cp[32]	auto[1]	71	1			T4	2		T8	1		T9	1
reset_info_cp[64]	auto[0]	53	1			T11	2		T25	3		T41	1
reset_info_cp[64]	auto[1]	79	1			T11	1		T15	1		T25	1
reset_info_cp[128]	auto[0]	49	1			T11	2		T86	2		T144	1
reset_info_cp[128]	auto[1]	69	1			T11	2		T136	1		T101	1