Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.40 99.40 99.31 99.87 99.83 99.46 98.52


Total test records in report: 620
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T540 /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1534233975 Aug 01 06:24:33 PM PDT 24 Aug 01 06:24:34 PM PDT 24 95605670 ps
T541 /workspace/coverage/default/11.rstmgr_por_stretcher.876869744 Aug 01 06:24:14 PM PDT 24 Aug 01 06:24:15 PM PDT 24 124541305 ps
T542 /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3780578436 Aug 01 06:24:57 PM PDT 24 Aug 01 06:24:59 PM PDT 24 228284454 ps
T543 /workspace/coverage/default/3.rstmgr_stress_all.3174761469 Aug 01 06:24:10 PM PDT 24 Aug 01 06:24:27 PM PDT 24 4441906913 ps
T544 /workspace/coverage/default/6.rstmgr_sw_rst.246885410 Aug 01 06:24:07 PM PDT 24 Aug 01 06:24:10 PM PDT 24 384197687 ps
T58 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2675463784 Aug 01 06:21:11 PM PDT 24 Aug 01 06:21:12 PM PDT 24 82197529 ps
T59 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1839714387 Aug 01 06:21:05 PM PDT 24 Aug 01 06:21:06 PM PDT 24 71998243 ps
T60 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1241730085 Aug 01 06:20:53 PM PDT 24 Aug 01 06:20:55 PM PDT 24 166982479 ps
T61 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.779282312 Aug 01 06:21:10 PM PDT 24 Aug 01 06:21:12 PM PDT 24 104780631 ps
T63 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3990494763 Aug 01 06:20:55 PM PDT 24 Aug 01 06:20:57 PM PDT 24 133361357 ps
T109 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1297769851 Aug 01 06:21:04 PM PDT 24 Aug 01 06:21:05 PM PDT 24 72576992 ps
T64 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.798729510 Aug 01 06:20:56 PM PDT 24 Aug 01 06:20:58 PM PDT 24 187247798 ps
T65 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4005215028 Aug 01 06:20:56 PM PDT 24 Aug 01 06:20:58 PM PDT 24 114783817 ps
T66 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1441270060 Aug 01 06:21:06 PM PDT 24 Aug 01 06:21:07 PM PDT 24 449694465 ps
T110 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.398468215 Aug 01 06:20:50 PM PDT 24 Aug 01 06:20:51 PM PDT 24 69863367 ps
T92 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.628386280 Aug 01 06:21:11 PM PDT 24 Aug 01 06:21:13 PM PDT 24 140666562 ps
T67 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1102728289 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:47 PM PDT 24 504114041 ps
T68 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3769501892 Aug 01 06:20:51 PM PDT 24 Aug 01 06:20:53 PM PDT 24 169955662 ps
T93 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.78845476 Aug 01 06:21:05 PM PDT 24 Aug 01 06:21:13 PM PDT 24 921334176 ps
T111 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1973652170 Aug 01 06:20:53 PM PDT 24 Aug 01 06:20:54 PM PDT 24 212360402 ps
T112 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3278166723 Aug 01 06:21:08 PM PDT 24 Aug 01 06:21:10 PM PDT 24 140357308 ps
T94 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.275633026 Aug 01 06:21:00 PM PDT 24 Aug 01 06:21:01 PM PDT 24 147195754 ps
T115 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3457336702 Aug 01 06:20:49 PM PDT 24 Aug 01 06:20:51 PM PDT 24 421912344 ps
T95 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1525199776 Aug 01 06:20:53 PM PDT 24 Aug 01 06:20:55 PM PDT 24 160957223 ps
T96 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2791666264 Aug 01 06:21:09 PM PDT 24 Aug 01 06:21:11 PM PDT 24 435576366 ps
T97 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3668953086 Aug 01 06:21:11 PM PDT 24 Aug 01 06:21:13 PM PDT 24 261788722 ps
T113 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1023196529 Aug 01 06:20:56 PM PDT 24 Aug 01 06:20:57 PM PDT 24 82120919 ps
T114 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.291794004 Aug 01 06:21:00 PM PDT 24 Aug 01 06:21:01 PM PDT 24 61023369 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.15345853 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:49 PM PDT 24 112497126 ps
T98 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3071034053 Aug 01 06:20:54 PM PDT 24 Aug 01 06:20:56 PM PDT 24 204118538 ps
T99 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.568419866 Aug 01 06:20:49 PM PDT 24 Aug 01 06:20:51 PM PDT 24 182290738 ps
T138 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3457619018 Aug 01 06:20:53 PM PDT 24 Aug 01 06:20:55 PM PDT 24 463030893 ps
T546 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2796767297 Aug 01 06:21:07 PM PDT 24 Aug 01 06:21:09 PM PDT 24 428371522 ps
T121 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1165185641 Aug 01 06:21:13 PM PDT 24 Aug 01 06:21:14 PM PDT 24 131068102 ps
T116 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3192637174 Aug 01 06:21:15 PM PDT 24 Aug 01 06:21:18 PM PDT 24 878791666 ps
T140 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3034838412 Aug 01 06:20:55 PM PDT 24 Aug 01 06:20:57 PM PDT 24 431904538 ps
T547 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2858187216 Aug 01 06:21:04 PM PDT 24 Aug 01 06:21:05 PM PDT 24 108538508 ps
T126 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1765508066 Aug 01 06:21:12 PM PDT 24 Aug 01 06:21:15 PM PDT 24 350459223 ps
T125 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.156018966 Aug 01 06:21:09 PM PDT 24 Aug 01 06:21:12 PM PDT 24 415407623 ps
T548 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2830406537 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:52 PM PDT 24 1183073705 ps
T549 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3922782561 Aug 01 06:20:59 PM PDT 24 Aug 01 06:21:00 PM PDT 24 67665765 ps
T550 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3554672406 Aug 01 06:20:58 PM PDT 24 Aug 01 06:20:59 PM PDT 24 59564136 ps
T551 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.777948597 Aug 01 06:20:49 PM PDT 24 Aug 01 06:20:51 PM PDT 24 200358334 ps
T552 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.613221565 Aug 01 06:20:48 PM PDT 24 Aug 01 06:20:50 PM PDT 24 201564648 ps
T553 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4083204079 Aug 01 06:20:52 PM PDT 24 Aug 01 06:20:54 PM PDT 24 110152002 ps
T124 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1633914313 Aug 01 06:20:48 PM PDT 24 Aug 01 06:20:51 PM PDT 24 883572687 ps
T554 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.554034339 Aug 01 06:21:08 PM PDT 24 Aug 01 06:21:11 PM PDT 24 195041524 ps
T555 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3294783277 Aug 01 06:21:12 PM PDT 24 Aug 01 06:21:14 PM PDT 24 482875271 ps
T556 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3481139728 Aug 01 06:20:49 PM PDT 24 Aug 01 06:20:50 PM PDT 24 145288943 ps
T557 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.113911243 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:49 PM PDT 24 134829037 ps
T122 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3825272886 Aug 01 06:21:10 PM PDT 24 Aug 01 06:21:14 PM PDT 24 882238079 ps
T558 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1690150576 Aug 01 06:20:46 PM PDT 24 Aug 01 06:20:51 PM PDT 24 489407342 ps
T559 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1395391837 Aug 01 06:20:46 PM PDT 24 Aug 01 06:20:47 PM PDT 24 104734134 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2018532204 Aug 01 06:20:52 PM PDT 24 Aug 01 06:20:53 PM PDT 24 62861699 ps
T561 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3950185822 Aug 01 06:21:13 PM PDT 24 Aug 01 06:21:16 PM PDT 24 302366838 ps
T562 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.233196802 Aug 01 06:21:10 PM PDT 24 Aug 01 06:21:12 PM PDT 24 239542024 ps
T563 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.208478322 Aug 01 06:20:54 PM PDT 24 Aug 01 06:20:55 PM PDT 24 105197525 ps
T564 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3707289147 Aug 01 06:20:50 PM PDT 24 Aug 01 06:20:52 PM PDT 24 199696762 ps
T565 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3890517923 Aug 01 06:20:54 PM PDT 24 Aug 01 06:20:55 PM PDT 24 72538887 ps
T566 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.439082118 Aug 01 06:21:05 PM PDT 24 Aug 01 06:21:06 PM PDT 24 62201501 ps
T567 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1684461976 Aug 01 06:20:49 PM PDT 24 Aug 01 06:20:50 PM PDT 24 102994502 ps
T568 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.215389261 Aug 01 06:21:17 PM PDT 24 Aug 01 06:21:18 PM PDT 24 124985445 ps
T569 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.990944689 Aug 01 06:21:01 PM PDT 24 Aug 01 06:21:03 PM PDT 24 265039873 ps
T139 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4137602193 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:51 PM PDT 24 864042593 ps
T570 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3402289034 Aug 01 06:21:09 PM PDT 24 Aug 01 06:21:10 PM PDT 24 58859018 ps
T571 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.780834685 Aug 01 06:20:51 PM PDT 24 Aug 01 06:20:53 PM PDT 24 181817224 ps
T572 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.863470335 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:48 PM PDT 24 776822317 ps
T573 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.988914438 Aug 01 06:21:15 PM PDT 24 Aug 01 06:21:16 PM PDT 24 63454017 ps
T574 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2631116384 Aug 01 06:21:13 PM PDT 24 Aug 01 06:21:14 PM PDT 24 173567317 ps
T575 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2009233055 Aug 01 06:21:10 PM PDT 24 Aug 01 06:21:11 PM PDT 24 88787036 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3805567704 Aug 01 06:20:48 PM PDT 24 Aug 01 06:20:49 PM PDT 24 63413149 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.433046512 Aug 01 06:20:42 PM PDT 24 Aug 01 06:20:44 PM PDT 24 120566808 ps
T578 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3826474193 Aug 01 06:20:52 PM PDT 24 Aug 01 06:20:57 PM PDT 24 607207252 ps
T579 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.4154372450 Aug 01 06:20:56 PM PDT 24 Aug 01 06:20:59 PM PDT 24 181952706 ps
T580 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3650651150 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:53 PM PDT 24 483452181 ps
T581 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4073739650 Aug 01 06:21:10 PM PDT 24 Aug 01 06:21:13 PM PDT 24 305947071 ps
T582 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.883576354 Aug 01 06:20:46 PM PDT 24 Aug 01 06:20:48 PM PDT 24 95532737 ps
T583 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3031766680 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:52 PM PDT 24 1536094534 ps
T584 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3952637237 Aug 01 06:21:05 PM PDT 24 Aug 01 06:21:06 PM PDT 24 86021574 ps
T585 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2106126811 Aug 01 06:20:59 PM PDT 24 Aug 01 06:21:00 PM PDT 24 198190793 ps
T586 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1591630208 Aug 01 06:21:13 PM PDT 24 Aug 01 06:21:14 PM PDT 24 132490335 ps
T587 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1240912086 Aug 01 06:21:17 PM PDT 24 Aug 01 06:21:18 PM PDT 24 75328195 ps
T588 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.850337118 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:48 PM PDT 24 88909472 ps
T117 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.233234775 Aug 01 06:20:54 PM PDT 24 Aug 01 06:20:57 PM PDT 24 912326798 ps
T589 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3440179493 Aug 01 06:21:07 PM PDT 24 Aug 01 06:21:09 PM PDT 24 141784922 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3138414132 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:48 PM PDT 24 61909336 ps
T591 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2935139528 Aug 01 06:20:51 PM PDT 24 Aug 01 06:20:53 PM PDT 24 152653161 ps
T592 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2067543717 Aug 01 06:21:07 PM PDT 24 Aug 01 06:21:08 PM PDT 24 61992330 ps
T593 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1945514992 Aug 01 06:21:07 PM PDT 24 Aug 01 06:21:08 PM PDT 24 82200645 ps
T594 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3928270387 Aug 01 06:20:49 PM PDT 24 Aug 01 06:20:51 PM PDT 24 229526207 ps
T595 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1909817760 Aug 01 06:20:52 PM PDT 24 Aug 01 06:20:54 PM PDT 24 167704551 ps
T596 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1301800283 Aug 01 06:21:01 PM PDT 24 Aug 01 06:21:02 PM PDT 24 85030136 ps
T597 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.434576059 Aug 01 06:20:50 PM PDT 24 Aug 01 06:20:54 PM PDT 24 498698778 ps
T118 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3394993911 Aug 01 06:21:10 PM PDT 24 Aug 01 06:21:12 PM PDT 24 521623910 ps
T598 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3593877306 Aug 01 06:21:13 PM PDT 24 Aug 01 06:21:14 PM PDT 24 130398194 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1578606335 Aug 01 06:20:46 PM PDT 24 Aug 01 06:20:48 PM PDT 24 152530891 ps
T600 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3408910827 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:48 PM PDT 24 113994716 ps
T601 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2420267949 Aug 01 06:20:59 PM PDT 24 Aug 01 06:21:02 PM PDT 24 178610451 ps
T602 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1799635046 Aug 01 06:21:14 PM PDT 24 Aug 01 06:21:17 PM PDT 24 355369237 ps
T603 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.932456976 Aug 01 06:21:09 PM PDT 24 Aug 01 06:21:12 PM PDT 24 182787807 ps
T604 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.767111393 Aug 01 06:20:57 PM PDT 24 Aug 01 06:20:58 PM PDT 24 147279451 ps
T605 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1634906492 Aug 01 06:20:59 PM PDT 24 Aug 01 06:21:00 PM PDT 24 68866825 ps
T120 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2150561525 Aug 01 06:21:13 PM PDT 24 Aug 01 06:21:16 PM PDT 24 887625248 ps
T606 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.562764167 Aug 01 06:20:46 PM PDT 24 Aug 01 06:20:48 PM PDT 24 155816586 ps
T607 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2433627857 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:49 PM PDT 24 134405739 ps
T608 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.969581648 Aug 01 06:21:13 PM PDT 24 Aug 01 06:21:15 PM PDT 24 103326208 ps
T609 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3371562384 Aug 01 06:21:07 PM PDT 24 Aug 01 06:21:08 PM PDT 24 206080742 ps
T119 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3968360516 Aug 01 06:21:12 PM PDT 24 Aug 01 06:21:14 PM PDT 24 820910081 ps
T610 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1357138278 Aug 01 06:20:44 PM PDT 24 Aug 01 06:20:45 PM PDT 24 83783287 ps
T611 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3303897590 Aug 01 06:20:50 PM PDT 24 Aug 01 06:20:55 PM PDT 24 678087450 ps
T612 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3933101226 Aug 01 06:21:11 PM PDT 24 Aug 01 06:21:13 PM PDT 24 426693080 ps
T613 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2420126319 Aug 01 06:21:14 PM PDT 24 Aug 01 06:21:15 PM PDT 24 150201784 ps
T614 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1203349452 Aug 01 06:21:12 PM PDT 24 Aug 01 06:21:14 PM PDT 24 251814707 ps
T615 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1665614865 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:48 PM PDT 24 491626071 ps
T616 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.478621137 Aug 01 06:20:48 PM PDT 24 Aug 01 06:20:49 PM PDT 24 54952202 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4231695497 Aug 01 06:20:43 PM PDT 24 Aug 01 06:20:52 PM PDT 24 1555167883 ps
T618 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2335777308 Aug 01 06:21:12 PM PDT 24 Aug 01 06:21:14 PM PDT 24 134650050 ps
T619 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.4240940774 Aug 01 06:20:54 PM PDT 24 Aug 01 06:20:58 PM PDT 24 499903562 ps
T620 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3907618393 Aug 01 06:20:53 PM PDT 24 Aug 01 06:20:54 PM PDT 24 84371555 ps
T123 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2262558964 Aug 01 06:21:03 PM PDT 24 Aug 01 06:21:06 PM PDT 24 806451183 ps

Test location /workspace/coverage/default/4.rstmgr_reset.628003253
Short name T9
Test name
Test status
Simulation time 1722292239 ps
CPU time 5.99 seconds
Started Aug 01 06:24:15 PM PDT 24
Finished Aug 01 06:24:21 PM PDT 24
Peak memory 200544 kb
Host smart-fa7aa1ab-a9f5-44eb-b4ac-637bb3f2d7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628003253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.628003253
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3555066681
Short name T6
Test name
Test status
Simulation time 353242052 ps
CPU time 2.18 seconds
Started Aug 01 06:24:21 PM PDT 24
Finished Aug 01 06:24:23 PM PDT 24
Peak memory 200244 kb
Host smart-9806a8f7-eb1a-4bb0-86e3-11a08fecb40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555066681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3555066681
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.798729510
Short name T64
Test name
Test status
Simulation time 187247798 ps
CPU time 1.8 seconds
Started Aug 01 06:20:56 PM PDT 24
Finished Aug 01 06:20:58 PM PDT 24
Peak memory 208376 kb
Host smart-aa85dd2f-72ea-4cd1-a360-453af1a7dcdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798729510 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.798729510
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1360157031
Short name T72
Test name
Test status
Simulation time 8291440070 ps
CPU time 14.49 seconds
Started Aug 01 06:24:17 PM PDT 24
Finished Aug 01 06:24:31 PM PDT 24
Peak memory 217236 kb
Host smart-955216bf-4c4a-40a8-bb2c-e8a3cc381c5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360157031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1360157031
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1511983639
Short name T136
Test name
Test status
Simulation time 1220323183 ps
CPU time 6.42 seconds
Started Aug 01 06:24:11 PM PDT 24
Finished Aug 01 06:24:18 PM PDT 24
Peak memory 217684 kb
Host smart-66e7dd53-6c3b-4382-93a7-2b4110866ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511983639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1511983639
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2420023687
Short name T11
Test name
Test status
Simulation time 9436353470 ps
CPU time 33.62 seconds
Started Aug 01 06:24:52 PM PDT 24
Finished Aug 01 06:25:25 PM PDT 24
Peak memory 200564 kb
Host smart-0211dfc8-9203-486e-9c05-b1695dc759cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420023687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2420023687
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.78845476
Short name T93
Test name
Test status
Simulation time 921334176 ps
CPU time 3.15 seconds
Started Aug 01 06:21:05 PM PDT 24
Finished Aug 01 06:21:13 PM PDT 24
Peak memory 200220 kb
Host smart-5098ab3b-2cba-467b-b23c-0d3bed89bad1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78845476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.78845476
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.827173027
Short name T54
Test name
Test status
Simulation time 75694365 ps
CPU time 0.85 seconds
Started Aug 01 06:24:45 PM PDT 24
Finished Aug 01 06:24:46 PM PDT 24
Peak memory 200028 kb
Host smart-b2f9f529-eee9-43b2-aadc-dad2699e265a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827173027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.827173027
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.709694894
Short name T29
Test name
Test status
Simulation time 1227800273 ps
CPU time 6.03 seconds
Started Aug 01 06:25:27 PM PDT 24
Finished Aug 01 06:25:33 PM PDT 24
Peak memory 217744 kb
Host smart-1ad8ea4f-577a-490f-9dd9-49fb7cd420db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709694894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.709694894
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.554034339
Short name T554
Test name
Test status
Simulation time 195041524 ps
CPU time 2.79 seconds
Started Aug 01 06:21:08 PM PDT 24
Finished Aug 01 06:21:11 PM PDT 24
Peak memory 216412 kb
Host smart-7caa247a-11ed-46f2-971b-1b57eafbcc1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554034339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.554034339
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3426386719
Short name T141
Test name
Test status
Simulation time 178166614 ps
CPU time 1.23 seconds
Started Aug 01 06:24:18 PM PDT 24
Finished Aug 01 06:24:19 PM PDT 24
Peak memory 200272 kb
Host smart-0737cb73-6321-4c3b-867e-dae6030e4e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426386719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3426386719
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3809283950
Short name T167
Test name
Test status
Simulation time 4827649596 ps
CPU time 17.4 seconds
Started Aug 01 06:24:15 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 210928 kb
Host smart-9196fac4-ff40-4808-93a8-607e49363c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809283950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3809283950
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.233234775
Short name T117
Test name
Test status
Simulation time 912326798 ps
CPU time 2.86 seconds
Started Aug 01 06:20:54 PM PDT 24
Finished Aug 01 06:20:57 PM PDT 24
Peak memory 200120 kb
Host smart-564bf069-7639-4525-ad79-22ea097c8cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233234775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
233234775
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4220607357
Short name T148
Test name
Test status
Simulation time 160901805 ps
CPU time 1.26 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:33 PM PDT 24
Peak memory 200296 kb
Host smart-a1ee10db-6297-407a-a9ff-c56365ece463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220607357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4220607357
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1539997347
Short name T36
Test name
Test status
Simulation time 2359587255 ps
CPU time 7.73 seconds
Started Aug 01 06:24:30 PM PDT 24
Finished Aug 01 06:24:37 PM PDT 24
Peak memory 217688 kb
Host smart-d006f238-9a4b-4726-bfaa-08487e53293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539997347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1539997347
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2631116384
Short name T574
Test name
Test status
Simulation time 173567317 ps
CPU time 1.49 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 208208 kb
Host smart-2f562d9d-4450-4bc2-904b-a8ce129dc6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631116384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2631116384
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1839714387
Short name T59
Test name
Test status
Simulation time 71998243 ps
CPU time 0.79 seconds
Started Aug 01 06:21:05 PM PDT 24
Finished Aug 01 06:21:06 PM PDT 24
Peak memory 200004 kb
Host smart-33238cb9-ec8a-483f-a88b-04daff91fcea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839714387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1839714387
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3754804211
Short name T20
Test name
Test status
Simulation time 165114915 ps
CPU time 0.9 seconds
Started Aug 01 06:23:54 PM PDT 24
Finished Aug 01 06:23:55 PM PDT 24
Peak memory 200100 kb
Host smart-ff1b1f77-709d-456f-9f8e-d73ce9d7213d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754804211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3754804211
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3457336702
Short name T115
Test name
Test status
Simulation time 421912344 ps
CPU time 1.94 seconds
Started Aug 01 06:20:49 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 200172 kb
Host smart-f200f70f-a424-41c5-9373-bcdb406765b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457336702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3457336702
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1803092504
Short name T231
Test name
Test status
Simulation time 149732313 ps
CPU time 1.79 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:09 PM PDT 24
Peak memory 200208 kb
Host smart-29ad49cd-647d-46bd-8239-f0da8326f547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803092504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1803092504
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1578606335
Short name T599
Test name
Test status
Simulation time 152530891 ps
CPU time 1.83 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 200120 kb
Host smart-fd77160b-7153-4c2a-b474-4427d4afb09f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578606335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
578606335
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3031766680
Short name T583
Test name
Test status
Simulation time 1536094534 ps
CPU time 7.52 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:52 PM PDT 24
Peak memory 200156 kb
Host smart-5113335b-347b-487c-8db8-fa60a83ab53c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031766680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
031766680
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.850337118
Short name T588
Test name
Test status
Simulation time 88909472 ps
CPU time 0.81 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 199992 kb
Host smart-022fc610-c301-4162-8e9f-c0b9c64ed7e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850337118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.850337118
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.777948597
Short name T551
Test name
Test status
Simulation time 200358334 ps
CPU time 1.34 seconds
Started Aug 01 06:20:49 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 208276 kb
Host smart-b2e0efd2-9ac1-4923-b413-322fd013533e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777948597 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.777948597
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.478621137
Short name T616
Test name
Test status
Simulation time 54952202 ps
CPU time 0.77 seconds
Started Aug 01 06:20:48 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 200004 kb
Host smart-4093dcf7-ca08-496a-8768-8820c89a4248
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478621137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.478621137
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3928270387
Short name T594
Test name
Test status
Simulation time 229526207 ps
CPU time 1.49 seconds
Started Aug 01 06:20:49 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 200164 kb
Host smart-f115de50-3f83-46ac-97f3-d9c189dcac09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928270387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3928270387
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.434576059
Short name T597
Test name
Test status
Simulation time 498698778 ps
CPU time 3.48 seconds
Started Aug 01 06:20:50 PM PDT 24
Finished Aug 01 06:20:54 PM PDT 24
Peak memory 208236 kb
Host smart-a5b3683e-b027-4037-8cf0-dcc03a581b6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434576059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.434576059
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1102728289
Short name T67
Test name
Test status
Simulation time 504114041 ps
CPU time 1.99 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:47 PM PDT 24
Peak memory 200128 kb
Host smart-1074c86a-3b93-46ff-9dfe-c024ac6ce692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102728289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1102728289
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.15345853
Short name T545
Test name
Test status
Simulation time 112497126 ps
CPU time 1.47 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 200104 kb
Host smart-007bae1c-846a-4cb0-9d5c-10568cd7945c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15345853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.15345853
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1690150576
Short name T558
Test name
Test status
Simulation time 489407342 ps
CPU time 5.37 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 200040 kb
Host smart-247b5834-399c-4040-8ff1-e1f37e2db2ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690150576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
690150576
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1357138278
Short name T610
Test name
Test status
Simulation time 83783287 ps
CPU time 0.79 seconds
Started Aug 01 06:20:44 PM PDT 24
Finished Aug 01 06:20:45 PM PDT 24
Peak memory 199964 kb
Host smart-51491a52-fedc-4bc3-a781-a3de3820c8f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357138278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
357138278
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3769501892
Short name T68
Test name
Test status
Simulation time 169955662 ps
CPU time 1.42 seconds
Started Aug 01 06:20:51 PM PDT 24
Finished Aug 01 06:20:53 PM PDT 24
Peak memory 212896 kb
Host smart-313b006c-0e5f-4577-8df0-e0573f730795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769501892 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3769501892
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3805567704
Short name T576
Test name
Test status
Simulation time 63413149 ps
CPU time 0.81 seconds
Started Aug 01 06:20:48 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 200008 kb
Host smart-8d5a1e45-2b16-468a-9fc5-0234a2e6cb7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805567704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3805567704
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.767111393
Short name T604
Test name
Test status
Simulation time 147279451 ps
CPU time 1.1 seconds
Started Aug 01 06:20:57 PM PDT 24
Finished Aug 01 06:20:58 PM PDT 24
Peak memory 200060 kb
Host smart-35fe2f1a-232d-434b-8760-abbd02210992
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767111393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.767111393
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1665614865
Short name T615
Test name
Test status
Simulation time 491626071 ps
CPU time 3.11 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 212252 kb
Host smart-8fa24e1b-10ae-46c6-8ea7-8d7901b23b44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665614865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1665614865
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1591630208
Short name T586
Test name
Test status
Simulation time 132490335 ps
CPU time 1.06 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 200396 kb
Host smart-0bdea3c3-697b-46f9-9a72-e73a59e3e6d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591630208 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1591630208
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2067543717
Short name T592
Test name
Test status
Simulation time 61992330 ps
CPU time 0.73 seconds
Started Aug 01 06:21:07 PM PDT 24
Finished Aug 01 06:21:08 PM PDT 24
Peak memory 200004 kb
Host smart-067b260a-b2b0-4727-b34a-70d6d1802367
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067543717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2067543717
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2420126319
Short name T613
Test name
Test status
Simulation time 150201784 ps
CPU time 1.11 seconds
Started Aug 01 06:21:14 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 199956 kb
Host smart-b0dfea8e-371e-44e1-bd42-fc85009eb836
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420126319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2420126319
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2796767297
Short name T546
Test name
Test status
Simulation time 428371522 ps
CPU time 1.81 seconds
Started Aug 01 06:21:07 PM PDT 24
Finished Aug 01 06:21:09 PM PDT 24
Peak memory 200216 kb
Host smart-0929c307-4bc8-47b5-af08-abacb04dea4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796767297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2796767297
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3371562384
Short name T609
Test name
Test status
Simulation time 206080742 ps
CPU time 1.28 seconds
Started Aug 01 06:21:07 PM PDT 24
Finished Aug 01 06:21:08 PM PDT 24
Peak memory 208336 kb
Host smart-e2b2a5aa-cb33-465d-a52a-aa68359d2627
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371562384 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3371562384
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1945514992
Short name T593
Test name
Test status
Simulation time 82200645 ps
CPU time 0.92 seconds
Started Aug 01 06:21:07 PM PDT 24
Finished Aug 01 06:21:08 PM PDT 24
Peak memory 200004 kb
Host smart-4dd956fc-d65f-4a05-8916-8a89d1b57a0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945514992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1945514992
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3952637237
Short name T584
Test name
Test status
Simulation time 86021574 ps
CPU time 0.94 seconds
Started Aug 01 06:21:05 PM PDT 24
Finished Aug 01 06:21:06 PM PDT 24
Peak memory 200076 kb
Host smart-278e133d-8d7f-4f9e-bf6a-1902cce16027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952637237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3952637237
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.4240940774
Short name T619
Test name
Test status
Simulation time 499903562 ps
CPU time 3.45 seconds
Started Aug 01 06:20:54 PM PDT 24
Finished Aug 01 06:20:58 PM PDT 24
Peak memory 208300 kb
Host smart-72782dad-a44f-4a40-8a6f-275a2880d66c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240940774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.4240940774
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1441270060
Short name T66
Test name
Test status
Simulation time 449694465 ps
CPU time 1.73 seconds
Started Aug 01 06:21:06 PM PDT 24
Finished Aug 01 06:21:07 PM PDT 24
Peak memory 200220 kb
Host smart-e5b6417c-f067-46c6-b6b2-7ccb5576458b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441270060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1441270060
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3440179493
Short name T589
Test name
Test status
Simulation time 141784922 ps
CPU time 1.48 seconds
Started Aug 01 06:21:07 PM PDT 24
Finished Aug 01 06:21:09 PM PDT 24
Peak memory 208400 kb
Host smart-676089db-6c13-4c06-af72-d1c4e8386819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440179493 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3440179493
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1301800283
Short name T596
Test name
Test status
Simulation time 85030136 ps
CPU time 0.87 seconds
Started Aug 01 06:21:01 PM PDT 24
Finished Aug 01 06:21:02 PM PDT 24
Peak memory 200004 kb
Host smart-664dcfa8-66c8-4bd2-b400-ad3d9268bd39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301800283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1301800283
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1203349452
Short name T614
Test name
Test status
Simulation time 251814707 ps
CPU time 1.56 seconds
Started Aug 01 06:21:12 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 200144 kb
Host smart-4161670d-63e6-405b-a6b5-a850b94a2a0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203349452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1203349452
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.156018966
Short name T125
Test name
Test status
Simulation time 415407623 ps
CPU time 3.18 seconds
Started Aug 01 06:21:09 PM PDT 24
Finished Aug 01 06:21:12 PM PDT 24
Peak memory 208288 kb
Host smart-c8872c46-2b56-4358-af5c-be6fec215493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156018966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.156018966
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3457619018
Short name T138
Test name
Test status
Simulation time 463030893 ps
CPU time 2.02 seconds
Started Aug 01 06:20:53 PM PDT 24
Finished Aug 01 06:20:55 PM PDT 24
Peak memory 200132 kb
Host smart-d6f433bc-053b-467a-a5f8-2ee43c7525f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457619018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3457619018
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2675463784
Short name T58
Test name
Test status
Simulation time 82197529 ps
CPU time 0.98 seconds
Started Aug 01 06:21:11 PM PDT 24
Finished Aug 01 06:21:12 PM PDT 24
Peak memory 200072 kb
Host smart-833faa60-c683-493c-b63b-6a127a48eca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675463784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2675463784
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.4154372450
Short name T579
Test name
Test status
Simulation time 181952706 ps
CPU time 2.52 seconds
Started Aug 01 06:20:56 PM PDT 24
Finished Aug 01 06:20:59 PM PDT 24
Peak memory 208360 kb
Host smart-acf41990-1c72-44e6-960b-2a1836dfc869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154372450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.4154372450
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3825272886
Short name T122
Test name
Test status
Simulation time 882238079 ps
CPU time 3.38 seconds
Started Aug 01 06:21:10 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 200152 kb
Host smart-76b21fd9-a007-44a7-9a7a-f184dba263da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825272886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3825272886
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1525199776
Short name T95
Test name
Test status
Simulation time 160957223 ps
CPU time 1.53 seconds
Started Aug 01 06:20:53 PM PDT 24
Finished Aug 01 06:20:55 PM PDT 24
Peak memory 208380 kb
Host smart-601ed96f-99cb-4c97-ab37-d1cb6cc81dd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525199776 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1525199776
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3890517923
Short name T565
Test name
Test status
Simulation time 72538887 ps
CPU time 0.78 seconds
Started Aug 01 06:20:54 PM PDT 24
Finished Aug 01 06:20:55 PM PDT 24
Peak memory 199940 kb
Host smart-a21b6b37-e47a-41a4-83ff-b09f00356c71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890517923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3890517923
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1023196529
Short name T113
Test name
Test status
Simulation time 82120919 ps
CPU time 0.98 seconds
Started Aug 01 06:20:56 PM PDT 24
Finished Aug 01 06:20:57 PM PDT 24
Peak memory 199964 kb
Host smart-4c617c71-92b1-4d56-890f-09488241d591
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023196529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1023196529
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3950185822
Short name T561
Test name
Test status
Simulation time 302366838 ps
CPU time 2.49 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:16 PM PDT 24
Peak memory 212184 kb
Host smart-9e52bc13-6bcd-40d7-b6d7-0eb1393ac53f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950185822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3950185822
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3294783277
Short name T555
Test name
Test status
Simulation time 482875271 ps
CPU time 2.22 seconds
Started Aug 01 06:21:12 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 200120 kb
Host smart-c49c6deb-8838-4e7b-ac87-438807f0869a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294783277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3294783277
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2335777308
Short name T618
Test name
Test status
Simulation time 134650050 ps
CPU time 1.06 seconds
Started Aug 01 06:21:12 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 200140 kb
Host smart-425913ae-cb12-4cb9-9690-fd716b25a6bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335777308 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2335777308
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.988914438
Short name T573
Test name
Test status
Simulation time 63454017 ps
CPU time 0.77 seconds
Started Aug 01 06:21:15 PM PDT 24
Finished Aug 01 06:21:16 PM PDT 24
Peak memory 200024 kb
Host smart-d2176047-856e-4138-9234-8ecc914bf330
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988914438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.988914438
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2858187216
Short name T547
Test name
Test status
Simulation time 108538508 ps
CPU time 1.01 seconds
Started Aug 01 06:21:04 PM PDT 24
Finished Aug 01 06:21:05 PM PDT 24
Peak memory 200072 kb
Host smart-7af33f71-3f33-493d-a2c1-efe7dde8383c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858187216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2858187216
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.932456976
Short name T603
Test name
Test status
Simulation time 182787807 ps
CPU time 2.69 seconds
Started Aug 01 06:21:09 PM PDT 24
Finished Aug 01 06:21:12 PM PDT 24
Peak memory 208288 kb
Host smart-d32d880c-e936-4f33-a178-67d30c110362
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932456976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.932456976
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2262558964
Short name T123
Test name
Test status
Simulation time 806451183 ps
CPU time 2.86 seconds
Started Aug 01 06:21:03 PM PDT 24
Finished Aug 01 06:21:06 PM PDT 24
Peak memory 200204 kb
Host smart-c8b25178-6e30-4f7b-8783-cb1c124d6eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262558964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2262558964
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.215389261
Short name T568
Test name
Test status
Simulation time 124985445 ps
CPU time 1.32 seconds
Started Aug 01 06:21:17 PM PDT 24
Finished Aug 01 06:21:18 PM PDT 24
Peak memory 208332 kb
Host smart-aa7fa575-3e30-4dec-a57c-c06a566495e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215389261 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.215389261
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3402289034
Short name T570
Test name
Test status
Simulation time 58859018 ps
CPU time 0.77 seconds
Started Aug 01 06:21:09 PM PDT 24
Finished Aug 01 06:21:10 PM PDT 24
Peak memory 200004 kb
Host smart-d5865591-3690-4bbc-bf2f-88b94e7d556f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402289034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3402289034
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1240912086
Short name T587
Test name
Test status
Simulation time 75328195 ps
CPU time 1.01 seconds
Started Aug 01 06:21:17 PM PDT 24
Finished Aug 01 06:21:18 PM PDT 24
Peak memory 200060 kb
Host smart-4a251ac0-2b7e-4f3a-8d9b-645ab56cbc50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240912086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1240912086
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3668953086
Short name T97
Test name
Test status
Simulation time 261788722 ps
CPU time 1.92 seconds
Started Aug 01 06:21:11 PM PDT 24
Finished Aug 01 06:21:13 PM PDT 24
Peak memory 216384 kb
Host smart-34bb8695-3e8c-4699-9350-188fe2d79030
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668953086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3668953086
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3933101226
Short name T612
Test name
Test status
Simulation time 426693080 ps
CPU time 1.78 seconds
Started Aug 01 06:21:11 PM PDT 24
Finished Aug 01 06:21:13 PM PDT 24
Peak memory 200204 kb
Host smart-ee63c057-0a50-42df-90f1-d74238e4b40f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933101226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3933101226
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1165185641
Short name T121
Test name
Test status
Simulation time 131068102 ps
CPU time 1.05 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 208296 kb
Host smart-5b7bf6f6-a8d9-491b-881c-ff8b10b65b3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165185641 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1165185641
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2009233055
Short name T575
Test name
Test status
Simulation time 88787036 ps
CPU time 0.9 seconds
Started Aug 01 06:21:10 PM PDT 24
Finished Aug 01 06:21:11 PM PDT 24
Peak memory 199728 kb
Host smart-5b87843d-ccd0-4d94-8b97-7c1674ef37ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009233055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2009233055
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.233196802
Short name T562
Test name
Test status
Simulation time 239542024 ps
CPU time 1.5 seconds
Started Aug 01 06:21:10 PM PDT 24
Finished Aug 01 06:21:12 PM PDT 24
Peak memory 200140 kb
Host smart-6ea15caf-e6e6-4992-b114-71034cd64335
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233196802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.233196802
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1799635046
Short name T602
Test name
Test status
Simulation time 355369237 ps
CPU time 2.73 seconds
Started Aug 01 06:21:14 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 211880 kb
Host smart-f4908dde-0cd0-4427-acb7-74643617c1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799635046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1799635046
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2791666264
Short name T96
Test name
Test status
Simulation time 435576366 ps
CPU time 1.76 seconds
Started Aug 01 06:21:09 PM PDT 24
Finished Aug 01 06:21:11 PM PDT 24
Peak memory 200212 kb
Host smart-65463266-0719-466f-8aee-45e9e2f7cf79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791666264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2791666264
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.275633026
Short name T94
Test name
Test status
Simulation time 147195754 ps
CPU time 1.11 seconds
Started Aug 01 06:21:00 PM PDT 24
Finished Aug 01 06:21:01 PM PDT 24
Peak memory 208272 kb
Host smart-0a01a616-a99b-4eb4-b93b-eea478611486
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275633026 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.275633026
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.291794004
Short name T114
Test name
Test status
Simulation time 61023369 ps
CPU time 0.78 seconds
Started Aug 01 06:21:00 PM PDT 24
Finished Aug 01 06:21:01 PM PDT 24
Peak memory 199968 kb
Host smart-60786952-9e65-40c0-9680-40dbad38d86e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291794004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.291794004
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3278166723
Short name T112
Test name
Test status
Simulation time 140357308 ps
CPU time 1.09 seconds
Started Aug 01 06:21:08 PM PDT 24
Finished Aug 01 06:21:10 PM PDT 24
Peak memory 200052 kb
Host smart-082fe29d-1b3c-4d3f-bf3c-81ca1af7498d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278166723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3278166723
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.4073739650
Short name T581
Test name
Test status
Simulation time 305947071 ps
CPU time 2.17 seconds
Started Aug 01 06:21:10 PM PDT 24
Finished Aug 01 06:21:13 PM PDT 24
Peak memory 208240 kb
Host smart-e3b6c65e-033b-449b-9ab5-5f768df0e365
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073739650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.4073739650
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.628386280
Short name T92
Test name
Test status
Simulation time 140666562 ps
CPU time 1.14 seconds
Started Aug 01 06:21:11 PM PDT 24
Finished Aug 01 06:21:13 PM PDT 24
Peak memory 208244 kb
Host smart-f5121163-3d12-4e7e-9342-c571af1f112e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628386280 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.628386280
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.439082118
Short name T566
Test name
Test status
Simulation time 62201501 ps
CPU time 0.82 seconds
Started Aug 01 06:21:05 PM PDT 24
Finished Aug 01 06:21:06 PM PDT 24
Peak memory 199980 kb
Host smart-1bf5cd88-2e5a-4659-9892-4c7d1b44e486
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439082118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.439082118
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.969581648
Short name T608
Test name
Test status
Simulation time 103326208 ps
CPU time 1.19 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 200156 kb
Host smart-00d7939b-38f1-4d8d-9e68-1a4c52a56693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969581648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.969581648
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3192637174
Short name T116
Test name
Test status
Simulation time 878791666 ps
CPU time 3.09 seconds
Started Aug 01 06:21:15 PM PDT 24
Finished Aug 01 06:21:18 PM PDT 24
Peak memory 200108 kb
Host smart-dbc3f50a-a5c4-46f6-8785-54e5271e7b51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192637174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3192637174
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4083204079
Short name T553
Test name
Test status
Simulation time 110152002 ps
CPU time 1.28 seconds
Started Aug 01 06:20:52 PM PDT 24
Finished Aug 01 06:20:54 PM PDT 24
Peak memory 200140 kb
Host smart-e03acd93-f6d2-4be5-95f4-5b6fe30d0214
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083204079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.4
083204079
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3650651150
Short name T580
Test name
Test status
Simulation time 483452181 ps
CPU time 5.71 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:53 PM PDT 24
Peak memory 200140 kb
Host smart-72fc95cc-9001-4ac4-b122-d00d7014eedf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650651150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
650651150
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1684461976
Short name T567
Test name
Test status
Simulation time 102994502 ps
CPU time 0.85 seconds
Started Aug 01 06:20:49 PM PDT 24
Finished Aug 01 06:20:50 PM PDT 24
Peak memory 200028 kb
Host smart-65b01f73-9dcd-4080-8b06-0aebaeec9d4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684461976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
684461976
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2935139528
Short name T591
Test name
Test status
Simulation time 152653161 ps
CPU time 1.28 seconds
Started Aug 01 06:20:51 PM PDT 24
Finished Aug 01 06:20:53 PM PDT 24
Peak memory 208332 kb
Host smart-81d4fddb-2588-4be9-a566-8aa363f13d5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935139528 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2935139528
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2018532204
Short name T560
Test name
Test status
Simulation time 62861699 ps
CPU time 0.76 seconds
Started Aug 01 06:20:52 PM PDT 24
Finished Aug 01 06:20:53 PM PDT 24
Peak memory 200012 kb
Host smart-38564992-8f55-4504-b324-730410aabd3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018532204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2018532204
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.113911243
Short name T557
Test name
Test status
Simulation time 134829037 ps
CPU time 1.27 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 200100 kb
Host smart-e4e3ce04-8350-43ef-9788-51f33f68f18b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113911243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.113911243
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.562764167
Short name T606
Test name
Test status
Simulation time 155816586 ps
CPU time 1.94 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 208288 kb
Host smart-d412da4a-79d1-4374-bd7c-f42fbb1e2c81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562764167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.562764167
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4137602193
Short name T139
Test name
Test status
Simulation time 864042593 ps
CPU time 3.3 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 200212 kb
Host smart-a4ba68c6-7e14-4517-84df-54a62bb76436
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137602193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.4137602193
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3408910827
Short name T600
Test name
Test status
Simulation time 113994716 ps
CPU time 1.36 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 200084 kb
Host smart-2b9d5234-b183-4aff-b415-1b76655de49e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408910827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
408910827
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4231695497
Short name T617
Test name
Test status
Simulation time 1555167883 ps
CPU time 8.34 seconds
Started Aug 01 06:20:43 PM PDT 24
Finished Aug 01 06:20:52 PM PDT 24
Peak memory 200048 kb
Host smart-945e72a7-42c9-4c74-8762-39c65d4fe2c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231695497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.4
231695497
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3481139728
Short name T556
Test name
Test status
Simulation time 145288943 ps
CPU time 0.92 seconds
Started Aug 01 06:20:49 PM PDT 24
Finished Aug 01 06:20:50 PM PDT 24
Peak memory 200012 kb
Host smart-3d06a8c9-beb1-4a9f-9065-d9643e8d9cd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481139728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
481139728
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.780834685
Short name T571
Test name
Test status
Simulation time 181817224 ps
CPU time 1.6 seconds
Started Aug 01 06:20:51 PM PDT 24
Finished Aug 01 06:20:53 PM PDT 24
Peak memory 208476 kb
Host smart-727a1536-3260-4ade-8e30-ea3b99c0ea0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780834685 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.780834685
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.398468215
Short name T110
Test name
Test status
Simulation time 69863367 ps
CPU time 0.81 seconds
Started Aug 01 06:20:50 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 199980 kb
Host smart-967d052d-dc2d-4118-9385-dbbbeb3c9147
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398468215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.398468215
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.883576354
Short name T582
Test name
Test status
Simulation time 95532737 ps
CPU time 1.22 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 200212 kb
Host smart-45c09ec7-ba48-4ca9-a979-f161227e05a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883576354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.883576354
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3303897590
Short name T611
Test name
Test status
Simulation time 678087450 ps
CPU time 4.2 seconds
Started Aug 01 06:20:50 PM PDT 24
Finished Aug 01 06:20:55 PM PDT 24
Peak memory 216508 kb
Host smart-f02d64cb-b5b0-48f6-a9d0-cb03eb4acc63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303897590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3303897590
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1633914313
Short name T124
Test name
Test status
Simulation time 883572687 ps
CPU time 2.96 seconds
Started Aug 01 06:20:48 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 200192 kb
Host smart-fe600451-6474-4ee4-a843-fda66f864f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633914313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1633914313
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3707289147
Short name T564
Test name
Test status
Simulation time 199696762 ps
CPU time 1.52 seconds
Started Aug 01 06:20:50 PM PDT 24
Finished Aug 01 06:20:52 PM PDT 24
Peak memory 200128 kb
Host smart-9d6cdefa-9c5d-4040-bfed-dd34767b2806
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707289147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
707289147
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2830406537
Short name T548
Test name
Test status
Simulation time 1183073705 ps
CPU time 5.15 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:52 PM PDT 24
Peak memory 200068 kb
Host smart-7ba47b3e-05ff-4722-a759-f8d686523e8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830406537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
830406537
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1395391837
Short name T559
Test name
Test status
Simulation time 104734134 ps
CPU time 0.84 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:47 PM PDT 24
Peak memory 200020 kb
Host smart-cfb4c9a3-6b60-49f0-8648-fc7ad2a5d250
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395391837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
395391837
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2433627857
Short name T607
Test name
Test status
Simulation time 134405739 ps
CPU time 1.05 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 200384 kb
Host smart-b3fb55f1-3a88-4b29-86a8-837481998839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433627857 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2433627857
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3138414132
Short name T590
Test name
Test status
Simulation time 61909336 ps
CPU time 0.84 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 200000 kb
Host smart-85913b66-5aee-4f1f-bb86-d71acae6f3c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138414132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3138414132
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.613221565
Short name T552
Test name
Test status
Simulation time 201564648 ps
CPU time 1.47 seconds
Started Aug 01 06:20:48 PM PDT 24
Finished Aug 01 06:20:50 PM PDT 24
Peak memory 200136 kb
Host smart-a49d36f0-72ab-4955-80de-e9b8955fd619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613221565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.613221565
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.433046512
Short name T577
Test name
Test status
Simulation time 120566808 ps
CPU time 1.65 seconds
Started Aug 01 06:20:42 PM PDT 24
Finished Aug 01 06:20:44 PM PDT 24
Peak memory 216404 kb
Host smart-38ccb62b-1a94-4895-9a5a-4ad5d458d2b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433046512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.433046512
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.863470335
Short name T572
Test name
Test status
Simulation time 776822317 ps
CPU time 2.81 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 200172 kb
Host smart-6c24f248-2258-4d83-9a76-7fa9ac72e7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863470335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
863470335
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3071034053
Short name T98
Test name
Test status
Simulation time 204118538 ps
CPU time 1.29 seconds
Started Aug 01 06:20:54 PM PDT 24
Finished Aug 01 06:20:56 PM PDT 24
Peak memory 208332 kb
Host smart-99386a4f-77f4-4a35-ad4a-0de996c4d6d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071034053 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3071034053
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1297769851
Short name T109
Test name
Test status
Simulation time 72576992 ps
CPU time 0.94 seconds
Started Aug 01 06:21:04 PM PDT 24
Finished Aug 01 06:21:05 PM PDT 24
Peak memory 200008 kb
Host smart-7833ca40-963d-47bf-9af1-d7c0b0f7f481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297769851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1297769851
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1241730085
Short name T60
Test name
Test status
Simulation time 166982479 ps
CPU time 1.28 seconds
Started Aug 01 06:20:53 PM PDT 24
Finished Aug 01 06:20:55 PM PDT 24
Peak memory 200076 kb
Host smart-460d2ffc-bff2-4326-8c81-c7613fd81f71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241730085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1241730085
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.568419866
Short name T99
Test name
Test status
Simulation time 182290738 ps
CPU time 2.59 seconds
Started Aug 01 06:20:49 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 200080 kb
Host smart-04bdfea5-bca6-4d40-a1f3-b2237c5a8c41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568419866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.568419866
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2150561525
Short name T120
Test name
Test status
Simulation time 887625248 ps
CPU time 3.04 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:16 PM PDT 24
Peak memory 200168 kb
Host smart-ac155e7c-69cf-4e0b-bc0e-0956fb81e941
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150561525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2150561525
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2106126811
Short name T585
Test name
Test status
Simulation time 198190793 ps
CPU time 1.31 seconds
Started Aug 01 06:20:59 PM PDT 24
Finished Aug 01 06:21:00 PM PDT 24
Peak memory 208256 kb
Host smart-87e01c1d-1444-4fc0-8439-8053f5cb3d87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106126811 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2106126811
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3922782561
Short name T549
Test name
Test status
Simulation time 67665765 ps
CPU time 0.78 seconds
Started Aug 01 06:20:59 PM PDT 24
Finished Aug 01 06:21:00 PM PDT 24
Peak memory 199924 kb
Host smart-410b3729-3717-4eae-b14e-619cbdb0dbc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922782561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3922782561
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.990944689
Short name T569
Test name
Test status
Simulation time 265039873 ps
CPU time 1.62 seconds
Started Aug 01 06:21:01 PM PDT 24
Finished Aug 01 06:21:03 PM PDT 24
Peak memory 200144 kb
Host smart-837074f9-3522-40b9-b25f-f083f72c35e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990944689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.990944689
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4005215028
Short name T65
Test name
Test status
Simulation time 114783817 ps
CPU time 1.68 seconds
Started Aug 01 06:20:56 PM PDT 24
Finished Aug 01 06:20:58 PM PDT 24
Peak memory 210372 kb
Host smart-28cd3274-4e05-4cb4-ab7e-31454260a4ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005215028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4005215028
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3034838412
Short name T140
Test name
Test status
Simulation time 431904538 ps
CPU time 1.65 seconds
Started Aug 01 06:20:55 PM PDT 24
Finished Aug 01 06:20:57 PM PDT 24
Peak memory 200132 kb
Host smart-9a9741ed-983c-498b-a2d3-2b820c1e1c45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034838412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3034838412
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1909817760
Short name T595
Test name
Test status
Simulation time 167704551 ps
CPU time 1.38 seconds
Started Aug 01 06:20:52 PM PDT 24
Finished Aug 01 06:20:54 PM PDT 24
Peak memory 208452 kb
Host smart-4b9f749c-413e-4bc7-9e09-847dd54d4717
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909817760 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1909817760
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3554672406
Short name T550
Test name
Test status
Simulation time 59564136 ps
CPU time 0.79 seconds
Started Aug 01 06:20:58 PM PDT 24
Finished Aug 01 06:20:59 PM PDT 24
Peak memory 199960 kb
Host smart-8688365d-46e5-467b-82cc-e57fb416d8c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554672406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3554672406
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3593877306
Short name T598
Test name
Test status
Simulation time 130398194 ps
CPU time 1.29 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 200144 kb
Host smart-7a7e66f5-5803-4562-a928-f8a929540ea6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593877306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3593877306
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1765508066
Short name T126
Test name
Test status
Simulation time 350459223 ps
CPU time 2.53 seconds
Started Aug 01 06:21:12 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 208252 kb
Host smart-16970e9e-7070-4043-b83b-2991f573fe83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765508066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1765508066
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3968360516
Short name T119
Test name
Test status
Simulation time 820910081 ps
CPU time 2.73 seconds
Started Aug 01 06:21:12 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 200160 kb
Host smart-54ec2427-bb7f-4761-9563-004c29677d45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968360516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3968360516
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.208478322
Short name T563
Test name
Test status
Simulation time 105197525 ps
CPU time 1.05 seconds
Started Aug 01 06:20:54 PM PDT 24
Finished Aug 01 06:20:55 PM PDT 24
Peak memory 208320 kb
Host smart-11a24e33-4de3-4e27-a3f6-c06362e53259
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208478322 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.208478322
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3907618393
Short name T620
Test name
Test status
Simulation time 84371555 ps
CPU time 0.86 seconds
Started Aug 01 06:20:53 PM PDT 24
Finished Aug 01 06:20:54 PM PDT 24
Peak memory 200000 kb
Host smart-90eb7a91-3dad-49f7-ba19-fe614bd53ea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907618393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3907618393
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1973652170
Short name T111
Test name
Test status
Simulation time 212360402 ps
CPU time 1.49 seconds
Started Aug 01 06:20:53 PM PDT 24
Finished Aug 01 06:20:54 PM PDT 24
Peak memory 200176 kb
Host smart-74310bac-8d75-4a96-aaed-3cb253802228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973652170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1973652170
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2420267949
Short name T601
Test name
Test status
Simulation time 178610451 ps
CPU time 2.65 seconds
Started Aug 01 06:20:59 PM PDT 24
Finished Aug 01 06:21:02 PM PDT 24
Peak memory 216360 kb
Host smart-05351b3e-7865-4843-bd21-61ee92ba9de8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420267949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2420267949
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3394993911
Short name T118
Test name
Test status
Simulation time 521623910 ps
CPU time 1.99 seconds
Started Aug 01 06:21:10 PM PDT 24
Finished Aug 01 06:21:12 PM PDT 24
Peak memory 200164 kb
Host smart-2f1a4270-5aa1-48bd-bca5-81316f605420
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394993911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3394993911
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3990494763
Short name T63
Test name
Test status
Simulation time 133361357 ps
CPU time 1.38 seconds
Started Aug 01 06:20:55 PM PDT 24
Finished Aug 01 06:20:57 PM PDT 24
Peak memory 216444 kb
Host smart-4d059905-5b73-4407-9ac6-2b6f66157ae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990494763 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3990494763
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1634906492
Short name T605
Test name
Test status
Simulation time 68866825 ps
CPU time 0.79 seconds
Started Aug 01 06:20:59 PM PDT 24
Finished Aug 01 06:21:00 PM PDT 24
Peak memory 199988 kb
Host smart-5d6b9c19-ff57-4dbf-80e5-9262082c3b3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634906492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1634906492
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.779282312
Short name T61
Test name
Test status
Simulation time 104780631 ps
CPU time 1.25 seconds
Started Aug 01 06:21:10 PM PDT 24
Finished Aug 01 06:21:12 PM PDT 24
Peak memory 200264 kb
Host smart-4eb849d7-2a62-4506-8cf2-b02a80222799
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779282312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.779282312
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3826474193
Short name T578
Test name
Test status
Simulation time 607207252 ps
CPU time 4.39 seconds
Started Aug 01 06:20:52 PM PDT 24
Finished Aug 01 06:20:57 PM PDT 24
Peak memory 208332 kb
Host smart-9ba9b623-1846-427d-88fd-ab989b96f9fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826474193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3826474193
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.93388916
Short name T298
Test name
Test status
Simulation time 85411688 ps
CPU time 0.84 seconds
Started Aug 01 06:24:15 PM PDT 24
Finished Aug 01 06:24:16 PM PDT 24
Peak memory 200100 kb
Host smart-1ee2e990-a4b0-4f9a-a906-e05b497aaffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93388916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.93388916
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1836715759
Short name T531
Test name
Test status
Simulation time 1218046453 ps
CPU time 6.31 seconds
Started Aug 01 06:24:23 PM PDT 24
Finished Aug 01 06:24:30 PM PDT 24
Peak memory 217668 kb
Host smart-2b4b7834-9109-4dc5-9016-0c1c34924909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836715759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1836715759
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3566831705
Short name T216
Test name
Test status
Simulation time 244240134 ps
CPU time 1.06 seconds
Started Aug 01 06:24:25 PM PDT 24
Finished Aug 01 06:24:26 PM PDT 24
Peak memory 217440 kb
Host smart-66c49558-361a-444a-9b11-f34dca152d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566831705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3566831705
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3855811177
Short name T426
Test name
Test status
Simulation time 838616204 ps
CPU time 4.48 seconds
Started Aug 01 06:23:52 PM PDT 24
Finished Aug 01 06:23:57 PM PDT 24
Peak memory 200536 kb
Host smart-4cabb91a-86a0-47dd-b3a8-8f16fee4ea6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855811177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3855811177
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2639759600
Short name T320
Test name
Test status
Simulation time 147119212 ps
CPU time 1.11 seconds
Started Aug 01 06:24:06 PM PDT 24
Finished Aug 01 06:24:08 PM PDT 24
Peak memory 200248 kb
Host smart-bdd4acbe-be0b-4adf-8235-8e8e668bc2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639759600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2639759600
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1818463487
Short name T255
Test name
Test status
Simulation time 117121417 ps
CPU time 1.13 seconds
Started Aug 01 06:23:53 PM PDT 24
Finished Aug 01 06:23:54 PM PDT 24
Peak memory 200392 kb
Host smart-e1720949-62f2-4619-b760-0f274f7687e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818463487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1818463487
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2900708703
Short name T384
Test name
Test status
Simulation time 81897367 ps
CPU time 0.86 seconds
Started Aug 01 06:23:51 PM PDT 24
Finished Aug 01 06:23:52 PM PDT 24
Peak memory 200292 kb
Host smart-8c2faabd-94fd-47d4-a8e7-f2f58d3a4b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900708703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2900708703
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.890735861
Short name T151
Test name
Test status
Simulation time 85541388 ps
CPU time 0.85 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:33 PM PDT 24
Peak memory 200080 kb
Host smart-7f0afb90-b289-412a-92bc-87e265db316f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890735861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.890735861
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1941028047
Short name T4
Test name
Test status
Simulation time 1887753159 ps
CPU time 7.6 seconds
Started Aug 01 06:24:24 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 229800 kb
Host smart-a132bb5b-0669-4e00-8a10-3ebaa59523bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941028047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1941028047
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2786643901
Short name T185
Test name
Test status
Simulation time 245538638 ps
CPU time 1.04 seconds
Started Aug 01 06:24:17 PM PDT 24
Finished Aug 01 06:24:18 PM PDT 24
Peak memory 217396 kb
Host smart-21ae67e9-b3b8-43a2-8bbf-eee7e533daee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786643901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2786643901
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.141678271
Short name T339
Test name
Test status
Simulation time 117120808 ps
CPU time 0.82 seconds
Started Aug 01 06:24:23 PM PDT 24
Finished Aug 01 06:24:24 PM PDT 24
Peak memory 200128 kb
Host smart-a95fbe1c-76aa-4993-8e3c-f5ac01725045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141678271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.141678271
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3255769920
Short name T527
Test name
Test status
Simulation time 873033442 ps
CPU time 4.33 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:36 PM PDT 24
Peak memory 200532 kb
Host smart-e7a3ba80-7ad7-47f3-a3c9-8c842fe893b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255769920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3255769920
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1381447139
Short name T73
Test name
Test status
Simulation time 8297351775 ps
CPU time 16.1 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 217180 kb
Host smart-fa904273-76c0-4131-ba32-3c8c7bd914da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381447139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1381447139
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.137828880
Short name T355
Test name
Test status
Simulation time 177108417 ps
CPU time 1.18 seconds
Started Aug 01 06:24:16 PM PDT 24
Finished Aug 01 06:24:18 PM PDT 24
Peak memory 200284 kb
Host smart-38135ca8-37ac-4b38-aac7-aeb95eea7089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137828880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.137828880
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.497828447
Short name T259
Test name
Test status
Simulation time 111319888 ps
CPU time 1.19 seconds
Started Aug 01 06:24:23 PM PDT 24
Finished Aug 01 06:24:24 PM PDT 24
Peak memory 200504 kb
Host smart-46edc0ef-76eb-4f28-bcf4-cdf03542060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497828447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.497828447
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3250059244
Short name T180
Test name
Test status
Simulation time 281901761 ps
CPU time 1.78 seconds
Started Aug 01 06:24:16 PM PDT 24
Finished Aug 01 06:24:18 PM PDT 24
Peak memory 200424 kb
Host smart-1fd6f069-af49-42a9-a720-9c9c125070fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250059244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3250059244
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3314929790
Short name T246
Test name
Test status
Simulation time 149699590 ps
CPU time 1.82 seconds
Started Aug 01 06:24:28 PM PDT 24
Finished Aug 01 06:24:30 PM PDT 24
Peak memory 200232 kb
Host smart-37f57d3e-aa05-47cd-9d0e-edbbb676ec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314929790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3314929790
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.4132386246
Short name T290
Test name
Test status
Simulation time 164325773 ps
CPU time 1.03 seconds
Started Aug 01 06:24:16 PM PDT 24
Finished Aug 01 06:24:17 PM PDT 24
Peak memory 200276 kb
Host smart-0c0c0d16-2b8a-4557-ae2c-833369c54f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132386246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.4132386246
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3603014347
Short name T328
Test name
Test status
Simulation time 65445282 ps
CPU time 0.75 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200108 kb
Host smart-b4a241ab-bcb9-43f4-ac0c-c995f168ef3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603014347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3603014347
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3739093709
Short name T233
Test name
Test status
Simulation time 1224659776 ps
CPU time 5.59 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 217624 kb
Host smart-b8cac9ee-1c90-4484-8ee2-075ebbf87540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739093709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3739093709
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1841456262
Short name T450
Test name
Test status
Simulation time 244027092 ps
CPU time 1.11 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:11 PM PDT 24
Peak memory 217396 kb
Host smart-5c24a420-28df-41da-b02b-b53b064d4ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841456262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1841456262
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1252191441
Short name T254
Test name
Test status
Simulation time 130488054 ps
CPU time 0.84 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:11 PM PDT 24
Peak memory 200092 kb
Host smart-50d26a4c-d2b1-4ed5-a841-7d323dba8441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252191441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1252191441
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.4288227715
Short name T327
Test name
Test status
Simulation time 1588244774 ps
CPU time 6.47 seconds
Started Aug 01 06:24:16 PM PDT 24
Finished Aug 01 06:24:23 PM PDT 24
Peak memory 200496 kb
Host smart-82d7a31e-64d8-4232-953e-258f70fbbf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288227715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.4288227715
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1466942870
Short name T362
Test name
Test status
Simulation time 187034081 ps
CPU time 1.21 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:11 PM PDT 24
Peak memory 200292 kb
Host smart-03f81c74-d322-4c0c-abab-9c4f8c7c02da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466942870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1466942870
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2675265950
Short name T87
Test name
Test status
Simulation time 194701161 ps
CPU time 1.44 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:11 PM PDT 24
Peak memory 200432 kb
Host smart-1099086a-fe5b-475a-94a1-5162322cddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675265950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2675265950
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.407036360
Short name T288
Test name
Test status
Simulation time 2085135599 ps
CPU time 9.02 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:19 PM PDT 24
Peak memory 200728 kb
Host smart-c60d2e07-6cec-4e84-aa87-9d0ef82d32e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407036360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.407036360
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2841023700
Short name T478
Test name
Test status
Simulation time 356705171 ps
CPU time 2.06 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200224 kb
Host smart-11d6809b-8a5c-427b-b659-3508237a1ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841023700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2841023700
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.483967946
Short name T431
Test name
Test status
Simulation time 181695296 ps
CPU time 1.08 seconds
Started Aug 01 06:24:14 PM PDT 24
Finished Aug 01 06:24:15 PM PDT 24
Peak memory 200292 kb
Host smart-d42bcf2b-a538-4142-8913-d71ba748b3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483967946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.483967946
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3962399424
Short name T307
Test name
Test status
Simulation time 72831813 ps
CPU time 0.79 seconds
Started Aug 01 06:24:14 PM PDT 24
Finished Aug 01 06:24:20 PM PDT 24
Peak memory 200040 kb
Host smart-846de841-f9e3-4699-bf47-fd7f65102eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962399424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3962399424
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4059872188
Short name T432
Test name
Test status
Simulation time 1886247396 ps
CPU time 6.92 seconds
Started Aug 01 06:24:19 PM PDT 24
Finished Aug 01 06:24:26 PM PDT 24
Peak memory 217724 kb
Host smart-dd9f0cda-73d2-4d9c-9218-3da4df0b50d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059872188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4059872188
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.402139649
Short name T304
Test name
Test status
Simulation time 244040027 ps
CPU time 1.13 seconds
Started Aug 01 06:24:11 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 217440 kb
Host smart-60591c99-ee30-48bf-92de-907fffa2821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402139649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.402139649
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.876869744
Short name T541
Test name
Test status
Simulation time 124541305 ps
CPU time 0.77 seconds
Started Aug 01 06:24:14 PM PDT 24
Finished Aug 01 06:24:15 PM PDT 24
Peak memory 200100 kb
Host smart-1ff205fa-32ee-4523-9eb1-90205e6014ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876869744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.876869744
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4293907920
Short name T24
Test name
Test status
Simulation time 674705479 ps
CPU time 3.61 seconds
Started Aug 01 06:24:19 PM PDT 24
Finished Aug 01 06:24:22 PM PDT 24
Peak memory 200548 kb
Host smart-11bd5797-7df1-4e92-91b0-eac69ec02563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293907920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4293907920
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2727809643
Short name T51
Test name
Test status
Simulation time 184832441 ps
CPU time 1.28 seconds
Started Aug 01 06:24:12 PM PDT 24
Finished Aug 01 06:24:13 PM PDT 24
Peak memory 200464 kb
Host smart-057c5914-5eeb-4fae-a577-9493d3cebae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727809643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2727809643
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.911637043
Short name T25
Test name
Test status
Simulation time 8675979177 ps
CPU time 31.9 seconds
Started Aug 01 06:24:16 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 200612 kb
Host smart-f9bb03af-f4b6-4836-a872-2aad2b393b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911637043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.911637043
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3038885514
Short name T145
Test name
Test status
Simulation time 175365269 ps
CPU time 1.16 seconds
Started Aug 01 06:24:13 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 200280 kb
Host smart-2959db84-67e1-4616-8778-f3e04d1e87aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038885514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3038885514
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2139140437
Short name T371
Test name
Test status
Simulation time 69163389 ps
CPU time 0.85 seconds
Started Aug 01 06:24:19 PM PDT 24
Finished Aug 01 06:24:20 PM PDT 24
Peak memory 200040 kb
Host smart-0853d35e-36a8-4411-aad7-94b495a08b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139140437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2139140437
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3893942465
Short name T295
Test name
Test status
Simulation time 1230255350 ps
CPU time 5.61 seconds
Started Aug 01 06:24:28 PM PDT 24
Finished Aug 01 06:24:34 PM PDT 24
Peak memory 216968 kb
Host smart-e1d75b75-ed87-4374-9b94-e1b0baa767ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893942465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3893942465
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3352799496
Short name T511
Test name
Test status
Simulation time 244615088 ps
CPU time 1.07 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 217452 kb
Host smart-f8813df1-8540-4dee-963b-ca63fdaeae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352799496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3352799496
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2523378941
Short name T458
Test name
Test status
Simulation time 189731312 ps
CPU time 0.86 seconds
Started Aug 01 06:24:13 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 200072 kb
Host smart-f8c541d6-2508-4ea6-a6ac-4f7307accca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523378941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2523378941
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1281904689
Short name T308
Test name
Test status
Simulation time 1630580167 ps
CPU time 5.56 seconds
Started Aug 01 06:24:13 PM PDT 24
Finished Aug 01 06:24:19 PM PDT 24
Peak memory 200472 kb
Host smart-81faf3a9-f534-485f-be8d-f46d036d20a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281904689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1281904689
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2124650536
Short name T367
Test name
Test status
Simulation time 100272102 ps
CPU time 0.96 seconds
Started Aug 01 06:24:32 PM PDT 24
Finished Aug 01 06:24:33 PM PDT 24
Peak memory 200300 kb
Host smart-d6bbcc47-7bb5-41f0-81b0-ede7749dce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124650536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2124650536
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.157437341
Short name T152
Test name
Test status
Simulation time 111872251 ps
CPU time 1.15 seconds
Started Aug 01 06:24:15 PM PDT 24
Finished Aug 01 06:24:16 PM PDT 24
Peak memory 200376 kb
Host smart-9470051e-35a2-4534-b36a-4c416c554ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157437341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.157437341
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3605804033
Short name T514
Test name
Test status
Simulation time 12518719352 ps
CPU time 45.43 seconds
Started Aug 01 06:24:43 PM PDT 24
Finished Aug 01 06:25:28 PM PDT 24
Peak memory 208760 kb
Host smart-60b649bc-3ba0-4726-a29f-d074ab5fd9f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605804033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3605804033
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.4074948394
Short name T335
Test name
Test status
Simulation time 142575811 ps
CPU time 1.7 seconds
Started Aug 01 06:24:27 PM PDT 24
Finished Aug 01 06:24:29 PM PDT 24
Peak memory 200236 kb
Host smart-67f06e2b-d519-4fd4-a21d-0bb47f8cd8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074948394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.4074948394
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.68482549
Short name T156
Test name
Test status
Simulation time 111067089 ps
CPU time 1 seconds
Started Aug 01 06:24:12 PM PDT 24
Finished Aug 01 06:24:13 PM PDT 24
Peak memory 200260 kb
Host smart-6b2d633a-86d0-4d27-a23f-30e3e6c80005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68482549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.68482549
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1944398926
Short name T253
Test name
Test status
Simulation time 72232608 ps
CPU time 0.89 seconds
Started Aug 01 06:24:30 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200108 kb
Host smart-15d49f00-98d1-4ae7-a55b-c700e35261e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944398926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1944398926
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.259111939
Short name T45
Test name
Test status
Simulation time 1241749303 ps
CPU time 5.31 seconds
Started Aug 01 06:24:37 PM PDT 24
Finished Aug 01 06:24:42 PM PDT 24
Peak memory 216696 kb
Host smart-2b600821-295f-425e-b9c1-3d64b9abaae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259111939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.259111939
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1300859606
Short name T360
Test name
Test status
Simulation time 244532320 ps
CPU time 1.06 seconds
Started Aug 01 06:24:30 PM PDT 24
Finished Aug 01 06:24:31 PM PDT 24
Peak memory 217464 kb
Host smart-9cc461a8-5662-4cc4-b8b1-e193cf8e19cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300859606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1300859606
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.668806805
Short name T1
Test name
Test status
Simulation time 111695974 ps
CPU time 0.83 seconds
Started Aug 01 06:24:28 PM PDT 24
Finished Aug 01 06:24:29 PM PDT 24
Peak memory 200092 kb
Host smart-be3a9be7-250c-4cfe-8953-0c2ccac90539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668806805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.668806805
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1542364046
Short name T101
Test name
Test status
Simulation time 1092537148 ps
CPU time 5.54 seconds
Started Aug 01 06:24:26 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200504 kb
Host smart-a92785ad-766f-4e99-9033-73d64ac3bdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542364046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1542364046
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2059530945
Short name T142
Test name
Test status
Simulation time 145814174 ps
CPU time 1.09 seconds
Started Aug 01 06:24:32 PM PDT 24
Finished Aug 01 06:24:33 PM PDT 24
Peak memory 200288 kb
Host smart-64824ed8-894e-4696-a16b-21a3ec60bbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059530945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2059530945
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1468940166
Short name T75
Test name
Test status
Simulation time 253536036 ps
CPU time 1.48 seconds
Started Aug 01 06:24:30 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200436 kb
Host smart-062c74e8-57f3-4060-bd44-4b4e04dc905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468940166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1468940166
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2274744169
Short name T342
Test name
Test status
Simulation time 16872425156 ps
CPU time 60.59 seconds
Started Aug 01 06:24:26 PM PDT 24
Finished Aug 01 06:25:27 PM PDT 24
Peak memory 208720 kb
Host smart-fe791e96-c08b-4dc9-b7b2-232b854a6144
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274744169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2274744169
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2775887086
Short name T313
Test name
Test status
Simulation time 371703623 ps
CPU time 2.06 seconds
Started Aug 01 06:24:29 PM PDT 24
Finished Aug 01 06:24:31 PM PDT 24
Peak memory 200232 kb
Host smart-f583b11f-ed37-4944-bd20-d1f2dbd21e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775887086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2775887086
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.115473053
Short name T200
Test name
Test status
Simulation time 94123123 ps
CPU time 0.92 seconds
Started Aug 01 06:24:20 PM PDT 24
Finished Aug 01 06:24:21 PM PDT 24
Peak memory 200348 kb
Host smart-55ad293b-e688-4dc4-905a-9eeeb2b242e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115473053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.115473053
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.985488837
Short name T418
Test name
Test status
Simulation time 62692726 ps
CPU time 0.74 seconds
Started Aug 01 06:24:25 PM PDT 24
Finished Aug 01 06:24:26 PM PDT 24
Peak memory 200116 kb
Host smart-f1342827-8966-4ad0-be77-27561b16edef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985488837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.985488837
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3677711727
Short name T284
Test name
Test status
Simulation time 2348381984 ps
CPU time 9.32 seconds
Started Aug 01 06:24:21 PM PDT 24
Finished Aug 01 06:24:30 PM PDT 24
Peak memory 217664 kb
Host smart-42f0b43e-2097-4cb2-9e2f-b8aba2f56925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677711727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3677711727
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.397356182
Short name T452
Test name
Test status
Simulation time 244525119 ps
CPU time 1.03 seconds
Started Aug 01 06:24:29 PM PDT 24
Finished Aug 01 06:24:31 PM PDT 24
Peak memory 217464 kb
Host smart-a0ffa5c9-332d-4f95-89a4-66930bca7b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397356182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.397356182
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.77191136
Short name T78
Test name
Test status
Simulation time 220166262 ps
CPU time 0.91 seconds
Started Aug 01 06:24:30 PM PDT 24
Finished Aug 01 06:24:31 PM PDT 24
Peak memory 200100 kb
Host smart-c1bb6429-537f-4cd9-85e2-6f8e7afd7aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77191136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.77191136
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4172938107
Short name T485
Test name
Test status
Simulation time 692873575 ps
CPU time 3.96 seconds
Started Aug 01 06:24:28 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200548 kb
Host smart-06c3380b-a143-4ad9-8aff-dcf0728dcee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172938107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4172938107
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3147199786
Short name T224
Test name
Test status
Simulation time 188494435 ps
CPU time 1.19 seconds
Started Aug 01 06:24:42 PM PDT 24
Finished Aug 01 06:24:44 PM PDT 24
Peak memory 200296 kb
Host smart-0bc4d5cd-e84a-41d7-a50b-890018bf01c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147199786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3147199786
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.430781695
Short name T437
Test name
Test status
Simulation time 195415970 ps
CPU time 1.35 seconds
Started Aug 01 06:24:18 PM PDT 24
Finished Aug 01 06:24:19 PM PDT 24
Peak memory 200484 kb
Host smart-4181c674-a7cd-4c14-92a1-61a4bac2a3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430781695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.430781695
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1440844926
Short name T473
Test name
Test status
Simulation time 710796048 ps
CPU time 3.51 seconds
Started Aug 01 06:24:17 PM PDT 24
Finished Aug 01 06:24:21 PM PDT 24
Peak memory 200416 kb
Host smart-0840474a-c7ef-4f94-9a96-e79b77b0f07e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440844926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1440844926
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3384754033
Short name T190
Test name
Test status
Simulation time 389193673 ps
CPU time 2.4 seconds
Started Aug 01 06:24:40 PM PDT 24
Finished Aug 01 06:24:42 PM PDT 24
Peak memory 200252 kb
Host smart-f9c28963-f55b-4158-9afc-667afa086654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384754033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3384754033
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3896214364
Short name T349
Test name
Test status
Simulation time 158532800 ps
CPU time 1.3 seconds
Started Aug 01 06:24:27 PM PDT 24
Finished Aug 01 06:24:28 PM PDT 24
Peak memory 200472 kb
Host smart-5d696abe-dd0a-44b9-b7d2-91e9ac703049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896214364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3896214364
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1557911826
Short name T296
Test name
Test status
Simulation time 81330865 ps
CPU time 0.84 seconds
Started Aug 01 06:24:32 PM PDT 24
Finished Aug 01 06:24:33 PM PDT 24
Peak memory 200044 kb
Host smart-52af2779-def3-47e8-8747-a88911cd2248
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557911826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1557911826
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3344613907
Short name T32
Test name
Test status
Simulation time 1886376971 ps
CPU time 7.14 seconds
Started Aug 01 06:24:23 PM PDT 24
Finished Aug 01 06:24:30 PM PDT 24
Peak memory 217708 kb
Host smart-718dd4d8-d836-4f52-95b9-d973826ae412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344613907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3344613907
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3816277921
Short name T311
Test name
Test status
Simulation time 247077764 ps
CPU time 1.02 seconds
Started Aug 01 06:24:43 PM PDT 24
Finished Aug 01 06:24:44 PM PDT 24
Peak memory 217440 kb
Host smart-9368e4da-2cef-4abe-aa1f-60f8ec8f588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816277921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3816277921
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2655699671
Short name T443
Test name
Test status
Simulation time 186944477 ps
CPU time 0.84 seconds
Started Aug 01 06:24:20 PM PDT 24
Finished Aug 01 06:24:21 PM PDT 24
Peak memory 200032 kb
Host smart-3e7bc3ff-f3f6-4397-adeb-27de1e0fb2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655699671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2655699671
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2754394652
Short name T100
Test name
Test status
Simulation time 894206261 ps
CPU time 4.31 seconds
Started Aug 01 06:24:37 PM PDT 24
Finished Aug 01 06:24:41 PM PDT 24
Peak memory 200496 kb
Host smart-83253d38-374e-4994-bc8f-27444f70c204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754394652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2754394652
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.186171418
Short name T474
Test name
Test status
Simulation time 151457589 ps
CPU time 1.09 seconds
Started Aug 01 06:24:24 PM PDT 24
Finished Aug 01 06:24:25 PM PDT 24
Peak memory 200264 kb
Host smart-9f2c5905-c7c8-4afd-8c48-044a66d36041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186171418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.186171418
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4187639324
Short name T489
Test name
Test status
Simulation time 258703383 ps
CPU time 1.54 seconds
Started Aug 01 06:24:27 PM PDT 24
Finished Aug 01 06:24:28 PM PDT 24
Peak memory 200464 kb
Host smart-daf5aa84-868f-4afe-a986-db3cc7b51a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187639324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4187639324
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2823174587
Short name T402
Test name
Test status
Simulation time 5416287490 ps
CPU time 22.82 seconds
Started Aug 01 06:24:40 PM PDT 24
Finished Aug 01 06:25:03 PM PDT 24
Peak memory 200564 kb
Host smart-79553a94-218b-4a26-8d05-1a39b6d16869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823174587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2823174587
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2516853776
Short name T519
Test name
Test status
Simulation time 437025540 ps
CPU time 2.32 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:33 PM PDT 24
Peak memory 200252 kb
Host smart-0d6b3d36-dc40-4eca-9fb8-3ef8e1ec4df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516853776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2516853776
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.764584020
Short name T356
Test name
Test status
Simulation time 299786695 ps
CPU time 1.6 seconds
Started Aug 01 06:24:32 PM PDT 24
Finished Aug 01 06:24:34 PM PDT 24
Peak memory 200440 kb
Host smart-0566b59e-4980-4c28-b8c2-473be2ab1e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764584020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.764584020
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1738544219
Short name T162
Test name
Test status
Simulation time 63236098 ps
CPU time 0.77 seconds
Started Aug 01 06:24:30 PM PDT 24
Finished Aug 01 06:24:31 PM PDT 24
Peak memory 200112 kb
Host smart-e86abe51-1795-40ad-b425-a8efd3107d01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738544219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1738544219
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.874338406
Short name T532
Test name
Test status
Simulation time 243746078 ps
CPU time 1.18 seconds
Started Aug 01 06:24:19 PM PDT 24
Finished Aug 01 06:24:20 PM PDT 24
Peak memory 217288 kb
Host smart-7042367e-6d45-4b52-863a-7c564ec4e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874338406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.874338406
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.952676050
Short name T448
Test name
Test status
Simulation time 206696476 ps
CPU time 0.93 seconds
Started Aug 01 06:24:39 PM PDT 24
Finished Aug 01 06:24:40 PM PDT 24
Peak memory 200100 kb
Host smart-4ae396d5-ae6b-4919-929c-9d36e7ef64f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952676050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.952676050
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3021215416
Short name T435
Test name
Test status
Simulation time 752905359 ps
CPU time 4 seconds
Started Aug 01 06:24:21 PM PDT 24
Finished Aug 01 06:24:25 PM PDT 24
Peak memory 200540 kb
Host smart-303288db-49b0-4472-bf84-0a0da656b66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021215416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3021215416
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.899725005
Short name T159
Test name
Test status
Simulation time 143231263 ps
CPU time 1.13 seconds
Started Aug 01 06:24:23 PM PDT 24
Finished Aug 01 06:24:24 PM PDT 24
Peak memory 200344 kb
Host smart-262e1906-019d-4eb5-9cee-4fae92875149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899725005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.899725005
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2186293640
Short name T332
Test name
Test status
Simulation time 234453138 ps
CPU time 1.71 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:33 PM PDT 24
Peak memory 200428 kb
Host smart-6c6dbe92-1380-4784-abc2-b01401e27eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186293640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2186293640
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1548996645
Short name T176
Test name
Test status
Simulation time 8434480223 ps
CPU time 30.46 seconds
Started Aug 01 06:24:27 PM PDT 24
Finished Aug 01 06:24:57 PM PDT 24
Peak memory 210168 kb
Host smart-18de0065-2689-4874-817b-e4493bafa0b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548996645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1548996645
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.756685297
Short name T192
Test name
Test status
Simulation time 139898800 ps
CPU time 1.76 seconds
Started Aug 01 06:24:44 PM PDT 24
Finished Aug 01 06:24:46 PM PDT 24
Peak memory 200244 kb
Host smart-0b5c8d96-368a-4e49-b0b2-0ef5e424885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756685297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.756685297
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3167384508
Short name T226
Test name
Test status
Simulation time 122328048 ps
CPU time 1.07 seconds
Started Aug 01 06:24:29 PM PDT 24
Finished Aug 01 06:24:30 PM PDT 24
Peak memory 200284 kb
Host smart-cae9f448-ca04-4238-b5d0-7ac1fb723054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167384508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3167384508
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3319233336
Short name T503
Test name
Test status
Simulation time 73284041 ps
CPU time 0.81 seconds
Started Aug 01 06:24:41 PM PDT 24
Finished Aug 01 06:24:42 PM PDT 24
Peak memory 200108 kb
Host smart-5890cced-f0b1-4160-b02e-953ced83a000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319233336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3319233336
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2537562807
Short name T49
Test name
Test status
Simulation time 1893549662 ps
CPU time 8.03 seconds
Started Aug 01 06:24:32 PM PDT 24
Finished Aug 01 06:24:40 PM PDT 24
Peak memory 221628 kb
Host smart-b7f0bcfc-a592-4f70-a7d7-0b3fa8562c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537562807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2537562807
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3457169769
Short name T182
Test name
Test status
Simulation time 244949260 ps
CPU time 1.04 seconds
Started Aug 01 06:24:28 PM PDT 24
Finished Aug 01 06:24:29 PM PDT 24
Peak memory 217476 kb
Host smart-3010f791-944e-4a3a-b7d2-6e9d024ff296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457169769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3457169769
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1379973179
Short name T389
Test name
Test status
Simulation time 200118544 ps
CPU time 0.88 seconds
Started Aug 01 06:24:18 PM PDT 24
Finished Aug 01 06:24:19 PM PDT 24
Peak memory 200032 kb
Host smart-faae1441-fec9-4b1d-913b-97c37ec33eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379973179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1379973179
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2946259753
Short name T375
Test name
Test status
Simulation time 1361665555 ps
CPU time 4.99 seconds
Started Aug 01 06:24:28 PM PDT 24
Finished Aug 01 06:24:34 PM PDT 24
Peak memory 200488 kb
Host smart-cfc519f5-216b-40bd-9fd6-e3d6e972b231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946259753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2946259753
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.4182300145
Short name T451
Test name
Test status
Simulation time 153997826 ps
CPU time 1.1 seconds
Started Aug 01 06:24:19 PM PDT 24
Finished Aug 01 06:24:20 PM PDT 24
Peak memory 200268 kb
Host smart-db977dbb-71da-4f38-b646-f8c4464e3c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182300145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.4182300145
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2200569871
Short name T257
Test name
Test status
Simulation time 112821325 ps
CPU time 1.17 seconds
Started Aug 01 06:24:38 PM PDT 24
Finished Aug 01 06:24:39 PM PDT 24
Peak memory 200432 kb
Host smart-6bbfa684-8c14-4135-a306-632f2fe83708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200569871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2200569871
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2804716176
Short name T368
Test name
Test status
Simulation time 4246489702 ps
CPU time 14.4 seconds
Started Aug 01 06:24:29 PM PDT 24
Finished Aug 01 06:24:43 PM PDT 24
Peak memory 200536 kb
Host smart-6d7dd9e8-596e-4f8b-a4a7-f8701006eddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804716176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2804716176
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1459638407
Short name T43
Test name
Test status
Simulation time 346455976 ps
CPU time 2.14 seconds
Started Aug 01 06:24:19 PM PDT 24
Finished Aug 01 06:24:21 PM PDT 24
Peak memory 208416 kb
Host smart-251dd195-d0b7-4663-891a-e5f0eaf35258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459638407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1459638407
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1724844074
Short name T405
Test name
Test status
Simulation time 74443393 ps
CPU time 0.77 seconds
Started Aug 01 06:24:30 PM PDT 24
Finished Aug 01 06:24:31 PM PDT 24
Peak memory 200104 kb
Host smart-0a74de89-8bcb-47de-b019-7ee0b983a57b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724844074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1724844074
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.89688702
Short name T27
Test name
Test status
Simulation time 1889120124 ps
CPU time 6.92 seconds
Started Aug 01 06:24:46 PM PDT 24
Finished Aug 01 06:24:53 PM PDT 24
Peak memory 221660 kb
Host smart-c95a3238-3c90-4534-8801-b497adc3e0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89688702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.89688702
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1748508036
Short name T412
Test name
Test status
Simulation time 244703968 ps
CPU time 1.1 seconds
Started Aug 01 06:24:42 PM PDT 24
Finished Aug 01 06:24:43 PM PDT 24
Peak memory 217440 kb
Host smart-28449014-70d0-4f73-8e2a-faec1e47ad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748508036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1748508036
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3946889583
Short name T18
Test name
Test status
Simulation time 107453024 ps
CPU time 0.81 seconds
Started Aug 01 06:24:42 PM PDT 24
Finished Aug 01 06:24:43 PM PDT 24
Peak memory 200100 kb
Host smart-083925d4-6e52-436e-aea4-9a9fb05be255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946889583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3946889583
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2981398305
Short name T315
Test name
Test status
Simulation time 2005469788 ps
CPU time 8.29 seconds
Started Aug 01 06:24:42 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 200504 kb
Host smart-70c10b36-773a-47a4-b871-ae2f550afc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981398305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2981398305
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2852545412
Short name T204
Test name
Test status
Simulation time 98822140 ps
CPU time 1.02 seconds
Started Aug 01 06:24:29 PM PDT 24
Finished Aug 01 06:24:30 PM PDT 24
Peak memory 200260 kb
Host smart-1c8768d1-382b-4ba5-84fb-4b64b3943907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852545412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2852545412
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2217279063
Short name T522
Test name
Test status
Simulation time 111323735 ps
CPU time 1.19 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200412 kb
Host smart-0b8b0594-a9ab-427d-afcf-df473e8aee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217279063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2217279063
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2944093746
Short name T416
Test name
Test status
Simulation time 1412452857 ps
CPU time 6.23 seconds
Started Aug 01 06:24:37 PM PDT 24
Finished Aug 01 06:24:44 PM PDT 24
Peak memory 208696 kb
Host smart-db3081b6-f1e4-4fd8-8957-9b021e46d5c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944093746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2944093746
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.4216101717
Short name T166
Test name
Test status
Simulation time 264648046 ps
CPU time 1.79 seconds
Started Aug 01 06:24:30 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200252 kb
Host smart-3c35adf0-fada-4040-9111-28d42d9fe730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216101717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.4216101717
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.7355598
Short name T526
Test name
Test status
Simulation time 146620572 ps
CPU time 1.14 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200284 kb
Host smart-7ee867ff-e5ae-4deb-ba2e-810a77361180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7355598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.7355598
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.201364376
Short name T510
Test name
Test status
Simulation time 63982444 ps
CPU time 0.76 seconds
Started Aug 01 06:24:41 PM PDT 24
Finished Aug 01 06:24:42 PM PDT 24
Peak memory 200080 kb
Host smart-bd6786d8-cb62-436c-9ef0-80f2496a6088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201364376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.201364376
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.687097821
Short name T421
Test name
Test status
Simulation time 1895744820 ps
CPU time 7.58 seconds
Started Aug 01 06:24:30 PM PDT 24
Finished Aug 01 06:24:38 PM PDT 24
Peak memory 217680 kb
Host smart-d6a958cb-efe6-43a7-9eda-f71f87565e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687097821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.687097821
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1335178602
Short name T399
Test name
Test status
Simulation time 244620043 ps
CPU time 1.08 seconds
Started Aug 01 06:24:36 PM PDT 24
Finished Aug 01 06:24:37 PM PDT 24
Peak memory 217500 kb
Host smart-21e91684-a28f-44f9-bb41-50aefb45c00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335178602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1335178602
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.4276693585
Short name T197
Test name
Test status
Simulation time 155653933 ps
CPU time 0.84 seconds
Started Aug 01 06:24:29 PM PDT 24
Finished Aug 01 06:24:30 PM PDT 24
Peak memory 200048 kb
Host smart-2f11d904-95ae-4d6a-9073-b61371327e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276693585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.4276693585
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3706989361
Short name T217
Test name
Test status
Simulation time 746707361 ps
CPU time 3.64 seconds
Started Aug 01 06:24:32 PM PDT 24
Finished Aug 01 06:24:35 PM PDT 24
Peak memory 200436 kb
Host smart-a542c2bd-6914-4ca4-9970-250d235de6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706989361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3706989361
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.957720559
Short name T396
Test name
Test status
Simulation time 107897162 ps
CPU time 1.01 seconds
Started Aug 01 06:24:39 PM PDT 24
Finished Aug 01 06:24:40 PM PDT 24
Peak memory 200300 kb
Host smart-4d04c39f-ad22-4db1-b3da-7a10e9a5678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957720559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.957720559
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2853372739
Short name T467
Test name
Test status
Simulation time 121166139 ps
CPU time 1.21 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200484 kb
Host smart-1dcb7e24-574a-4f8c-91d1-ab963d3650b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853372739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2853372739
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1543351237
Short name T490
Test name
Test status
Simulation time 6986328739 ps
CPU time 23.73 seconds
Started Aug 01 06:24:34 PM PDT 24
Finished Aug 01 06:24:58 PM PDT 24
Peak memory 208724 kb
Host smart-90450c83-9095-4c78-974f-b71bee292585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543351237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1543351237
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.362216340
Short name T88
Test name
Test status
Simulation time 293407562 ps
CPU time 2.06 seconds
Started Aug 01 06:24:32 PM PDT 24
Finished Aug 01 06:24:34 PM PDT 24
Peak memory 208388 kb
Host smart-0b818225-046e-4a09-9a05-bda29bb3efc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362216340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.362216340
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.593002683
Short name T499
Test name
Test status
Simulation time 86146970 ps
CPU time 0.84 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200240 kb
Host smart-b57a3dba-bfdb-4ee2-860a-4e7eccd03c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593002683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.593002683
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1200502527
Short name T194
Test name
Test status
Simulation time 65398379 ps
CPU time 0.82 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:11 PM PDT 24
Peak memory 200324 kb
Host smart-065aa61d-2faa-4f61-ad3a-97ccc56a56ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200502527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1200502527
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1527376360
Short name T337
Test name
Test status
Simulation time 1225534284 ps
CPU time 5.59 seconds
Started Aug 01 06:24:29 PM PDT 24
Finished Aug 01 06:24:34 PM PDT 24
Peak memory 217672 kb
Host smart-d8f3ce4d-0f15-4072-95c1-da4761495f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527376360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1527376360
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3695311859
Short name T81
Test name
Test status
Simulation time 244537736 ps
CPU time 1.2 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 217448 kb
Host smart-2ac54091-749f-4481-93a6-4bd3778b0738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695311859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3695311859
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3725381743
Short name T209
Test name
Test status
Simulation time 154486617 ps
CPU time 0.8 seconds
Started Aug 01 06:24:23 PM PDT 24
Finished Aug 01 06:24:24 PM PDT 24
Peak memory 200084 kb
Host smart-fc2264c3-bfca-4462-a4e5-0cc0ba5e98df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725381743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3725381743
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3954288528
Short name T343
Test name
Test status
Simulation time 825745810 ps
CPU time 4.26 seconds
Started Aug 01 06:24:26 PM PDT 24
Finished Aug 01 06:24:31 PM PDT 24
Peak memory 200480 kb
Host smart-45c3d942-8cfb-4e5e-8013-08e129e23b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954288528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3954288528
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1314339701
Short name T70
Test name
Test status
Simulation time 8524434851 ps
CPU time 12.87 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:23 PM PDT 24
Peak memory 217096 kb
Host smart-38b4ffde-2d07-4658-8e9a-bf82fc530176
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314339701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1314339701
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1342784159
Short name T175
Test name
Test status
Simulation time 182702961 ps
CPU time 1.17 seconds
Started Aug 01 06:24:29 PM PDT 24
Finished Aug 01 06:24:30 PM PDT 24
Peak memory 200272 kb
Host smart-7ce1c0bf-3d6a-4b28-aa09-748f5c612f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342784159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1342784159
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3650901792
Short name T220
Test name
Test status
Simulation time 115106039 ps
CPU time 1.17 seconds
Started Aug 01 06:24:17 PM PDT 24
Finished Aug 01 06:24:19 PM PDT 24
Peak memory 200472 kb
Host smart-6c1e3935-2728-4f08-981f-52c6894c6034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650901792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3650901792
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1948753195
Short name T89
Test name
Test status
Simulation time 189500560 ps
CPU time 1.17 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:09 PM PDT 24
Peak memory 200268 kb
Host smart-66b54aa2-3c2c-47b9-a0fd-9aaeee723495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948753195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1948753195
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2978765566
Short name T161
Test name
Test status
Simulation time 274747471 ps
CPU time 1.92 seconds
Started Aug 01 06:24:28 PM PDT 24
Finished Aug 01 06:24:30 PM PDT 24
Peak memory 200220 kb
Host smart-294d74cf-95eb-44e9-9de9-febe24669861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978765566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2978765566
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.730215706
Short name T147
Test name
Test status
Simulation time 85452968 ps
CPU time 0.87 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 200296 kb
Host smart-0af627cf-c784-4dbb-96c8-40024a456423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730215706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.730215706
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2330743656
Short name T171
Test name
Test status
Simulation time 52730549 ps
CPU time 0.72 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:49 PM PDT 24
Peak memory 200108 kb
Host smart-9d1009ed-686e-4221-9fe4-b6f8c016d1e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330743656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2330743656
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.773128182
Short name T498
Test name
Test status
Simulation time 1912378313 ps
CPU time 7.2 seconds
Started Aug 01 06:24:47 PM PDT 24
Finished Aug 01 06:24:54 PM PDT 24
Peak memory 221652 kb
Host smart-4d298ba5-bb7c-4636-a7a0-f5454da73519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773128182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.773128182
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.564502553
Short name T210
Test name
Test status
Simulation time 245250593 ps
CPU time 1.06 seconds
Started Aug 01 06:24:34 PM PDT 24
Finished Aug 01 06:24:35 PM PDT 24
Peak memory 217464 kb
Host smart-3bd76e89-f7eb-4cd7-a1b7-ea2dae613769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564502553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.564502553
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2073485327
Short name T19
Test name
Test status
Simulation time 216109170 ps
CPU time 0.88 seconds
Started Aug 01 06:24:51 PM PDT 24
Finished Aug 01 06:24:52 PM PDT 24
Peak memory 200128 kb
Host smart-f06719b2-fa17-4349-8675-9c87483ff44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073485327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2073485327
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2479621563
Short name T103
Test name
Test status
Simulation time 955586042 ps
CPU time 5.04 seconds
Started Aug 01 06:24:39 PM PDT 24
Finished Aug 01 06:24:44 PM PDT 24
Peak memory 200540 kb
Host smart-ca191737-078e-4e2f-974c-39bce55ab6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479621563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2479621563
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1345365970
Short name T494
Test name
Test status
Simulation time 185819089 ps
CPU time 1.26 seconds
Started Aug 01 06:24:41 PM PDT 24
Finished Aug 01 06:24:42 PM PDT 24
Peak memory 200300 kb
Host smart-e849ea41-8e5b-4836-b62f-67e0fb50f3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345365970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1345365970
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.987952747
Short name T488
Test name
Test status
Simulation time 190990943 ps
CPU time 1.44 seconds
Started Aug 01 06:24:44 PM PDT 24
Finished Aug 01 06:24:45 PM PDT 24
Peak memory 200380 kb
Host smart-a1b29cbd-92d3-4b02-a6c4-79caeb9e5a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987952747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.987952747
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1142225621
Short name T275
Test name
Test status
Simulation time 3620854367 ps
CPU time 16.17 seconds
Started Aug 01 06:24:49 PM PDT 24
Finished Aug 01 06:25:06 PM PDT 24
Peak memory 200564 kb
Host smart-66bbb4fa-279c-4f56-ab33-15194a9d97dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142225621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1142225621
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2135400627
Short name T365
Test name
Test status
Simulation time 292157585 ps
CPU time 1.91 seconds
Started Aug 01 06:24:33 PM PDT 24
Finished Aug 01 06:24:35 PM PDT 24
Peak memory 208428 kb
Host smart-6a4c7f28-a1b4-4587-af0a-d9337f5a9418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135400627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2135400627
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.535258406
Short name T133
Test name
Test status
Simulation time 304242361 ps
CPU time 1.51 seconds
Started Aug 01 06:24:47 PM PDT 24
Finished Aug 01 06:24:49 PM PDT 24
Peak memory 200384 kb
Host smart-2d5f1b88-d44a-41c9-80d0-34cc4a453315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535258406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.535258406
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2237803054
Short name T277
Test name
Test status
Simulation time 86609383 ps
CPU time 0.8 seconds
Started Aug 01 06:24:33 PM PDT 24
Finished Aug 01 06:24:34 PM PDT 24
Peak memory 200112 kb
Host smart-658593ed-4b08-4a0e-a35a-19ecb1622ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237803054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2237803054
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3467472354
Short name T31
Test name
Test status
Simulation time 1233419043 ps
CPU time 5.56 seconds
Started Aug 01 06:24:46 PM PDT 24
Finished Aug 01 06:24:51 PM PDT 24
Peak memory 217692 kb
Host smart-1d2a88fa-dc01-4c85-9c0e-9c32f4724ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467472354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3467472354
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1354520197
Short name T42
Test name
Test status
Simulation time 244781228 ps
CPU time 1.08 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:49 PM PDT 24
Peak memory 217528 kb
Host smart-43000160-b1d0-48e3-9998-a96892b804b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354520197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1354520197
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3770266730
Short name T508
Test name
Test status
Simulation time 179610670 ps
CPU time 0.9 seconds
Started Aug 01 06:24:39 PM PDT 24
Finished Aug 01 06:24:40 PM PDT 24
Peak memory 200068 kb
Host smart-3b45a419-53e8-4de2-b80e-73ae4beab320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770266730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3770266730
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2576469870
Short name T276
Test name
Test status
Simulation time 849324071 ps
CPU time 4.28 seconds
Started Aug 01 06:24:42 PM PDT 24
Finished Aug 01 06:24:46 PM PDT 24
Peak memory 200488 kb
Host smart-e17ecef0-2ac9-45cc-80db-622b4fda78d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576469870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2576469870
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.607265631
Short name T465
Test name
Test status
Simulation time 179273520 ps
CPU time 1.32 seconds
Started Aug 01 06:24:39 PM PDT 24
Finished Aug 01 06:24:41 PM PDT 24
Peak memory 200216 kb
Host smart-ac0d8238-e237-4a54-894c-8f421753d488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607265631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.607265631
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3730977321
Short name T512
Test name
Test status
Simulation time 255659753 ps
CPU time 1.52 seconds
Started Aug 01 06:24:40 PM PDT 24
Finished Aug 01 06:24:41 PM PDT 24
Peak memory 200400 kb
Host smart-c442e4bb-dbbb-4393-8d7f-5f2ec0123327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730977321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3730977321
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3020869181
Short name T521
Test name
Test status
Simulation time 8745266570 ps
CPU time 30.96 seconds
Started Aug 01 06:24:39 PM PDT 24
Finished Aug 01 06:25:11 PM PDT 24
Peak memory 200564 kb
Host smart-31e283e8-deee-477e-a45c-7e5546598421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020869181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3020869181
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1748502398
Short name T158
Test name
Test status
Simulation time 300691397 ps
CPU time 2.41 seconds
Started Aug 01 06:24:41 PM PDT 24
Finished Aug 01 06:24:43 PM PDT 24
Peak memory 208444 kb
Host smart-e230394a-7e51-4024-a7b8-821e5015fa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748502398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1748502398
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.758241549
Short name T321
Test name
Test status
Simulation time 100909427 ps
CPU time 0.87 seconds
Started Aug 01 06:24:35 PM PDT 24
Finished Aug 01 06:24:36 PM PDT 24
Peak memory 200276 kb
Host smart-c170ca10-f67a-4877-9976-ab5405785178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758241549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.758241549
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1561673727
Short name T47
Test name
Test status
Simulation time 2372214635 ps
CPU time 7.8 seconds
Started Aug 01 06:24:52 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 217852 kb
Host smart-1bffcea4-4ecc-4913-95c3-d73d7841c229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561673727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1561673727
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1622891457
Short name T247
Test name
Test status
Simulation time 244124179 ps
CPU time 1.08 seconds
Started Aug 01 06:24:46 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 217436 kb
Host smart-f0393f79-f422-47b5-ab6f-7818885753b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622891457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1622891457
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3085058920
Short name T385
Test name
Test status
Simulation time 249025779 ps
CPU time 0.95 seconds
Started Aug 01 06:24:36 PM PDT 24
Finished Aug 01 06:24:38 PM PDT 24
Peak memory 200080 kb
Host smart-5642d55f-8e1f-4b4e-a52a-48e631a7c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085058920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3085058920
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3002174038
Short name T357
Test name
Test status
Simulation time 1456502886 ps
CPU time 6.28 seconds
Started Aug 01 06:24:34 PM PDT 24
Finished Aug 01 06:24:41 PM PDT 24
Peak memory 200540 kb
Host smart-0a814503-3c6c-4475-a086-596a77d8af2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002174038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3002174038
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.841200582
Short name T235
Test name
Test status
Simulation time 109813450 ps
CPU time 1 seconds
Started Aug 01 06:24:33 PM PDT 24
Finished Aug 01 06:24:34 PM PDT 24
Peak memory 200288 kb
Host smart-45edc30a-f5ef-4649-acb4-238c040f4f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841200582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.841200582
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2591632816
Short name T359
Test name
Test status
Simulation time 247902296 ps
CPU time 1.47 seconds
Started Aug 01 06:24:41 PM PDT 24
Finished Aug 01 06:24:42 PM PDT 24
Peak memory 200484 kb
Host smart-052cb9c4-fd9c-434f-ad70-ca88c50347c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591632816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2591632816
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1763084341
Short name T538
Test name
Test status
Simulation time 15225520911 ps
CPU time 49.04 seconds
Started Aug 01 06:24:43 PM PDT 24
Finished Aug 01 06:25:32 PM PDT 24
Peak memory 210804 kb
Host smart-84267b42-6c63-4f8e-b618-b98d1413930a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763084341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1763084341
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1957281220
Short name T244
Test name
Test status
Simulation time 145412451 ps
CPU time 1.86 seconds
Started Aug 01 06:24:40 PM PDT 24
Finished Aug 01 06:24:42 PM PDT 24
Peak memory 200164 kb
Host smart-1f267e90-a75c-4921-befc-fb1f638163d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957281220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1957281220
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1883025399
Short name T283
Test name
Test status
Simulation time 150360915 ps
CPU time 1.15 seconds
Started Aug 01 06:24:44 PM PDT 24
Finished Aug 01 06:24:45 PM PDT 24
Peak memory 200284 kb
Host smart-302c95b4-46bd-4f40-a499-f01329679678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883025399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1883025399
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.159850241
Short name T407
Test name
Test status
Simulation time 77691587 ps
CPU time 0.79 seconds
Started Aug 01 06:24:36 PM PDT 24
Finished Aug 01 06:24:37 PM PDT 24
Peak memory 200092 kb
Host smart-7ca168f5-0e94-4fa0-801e-d0856a5d3b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159850241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.159850241
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.4008147969
Short name T33
Test name
Test status
Simulation time 2155091527 ps
CPU time 7.87 seconds
Started Aug 01 06:24:44 PM PDT 24
Finished Aug 01 06:24:52 PM PDT 24
Peak memory 217596 kb
Host smart-962681f0-ff85-4608-83a6-c73b126b4df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008147969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.4008147969
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3195444819
Short name T53
Test name
Test status
Simulation time 244361106 ps
CPU time 1.05 seconds
Started Aug 01 06:24:54 PM PDT 24
Finished Aug 01 06:24:55 PM PDT 24
Peak memory 217460 kb
Host smart-02be97db-dcb9-40c8-9a6e-0b657e8bd611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195444819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3195444819
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1602896619
Short name T23
Test name
Test status
Simulation time 251250930 ps
CPU time 1 seconds
Started Aug 01 06:24:44 PM PDT 24
Finished Aug 01 06:24:45 PM PDT 24
Peak memory 200088 kb
Host smart-dcab00e4-cfc5-45fa-b2ea-6ba4b6bc8258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602896619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1602896619
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1108449701
Short name T303
Test name
Test status
Simulation time 1429366527 ps
CPU time 6.06 seconds
Started Aug 01 06:24:43 PM PDT 24
Finished Aug 01 06:24:49 PM PDT 24
Peak memory 200488 kb
Host smart-109cb75f-1d2e-4287-b53e-d2b0191ce55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108449701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1108449701
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2732737154
Short name T358
Test name
Test status
Simulation time 102190529 ps
CPU time 1.01 seconds
Started Aug 01 06:24:36 PM PDT 24
Finished Aug 01 06:24:37 PM PDT 24
Peak memory 200276 kb
Host smart-61628005-1150-4da9-800e-3b7e106078dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732737154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2732737154
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2462392534
Short name T447
Test name
Test status
Simulation time 124706318 ps
CPU time 1.17 seconds
Started Aug 01 06:24:46 PM PDT 24
Finished Aug 01 06:24:47 PM PDT 24
Peak memory 200428 kb
Host smart-351c0712-311b-4c1f-b883-b160d8736aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462392534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2462392534
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2728110236
Short name T286
Test name
Test status
Simulation time 3877362821 ps
CPU time 16.17 seconds
Started Aug 01 06:24:45 PM PDT 24
Finished Aug 01 06:25:02 PM PDT 24
Peak memory 208696 kb
Host smart-04f3eae0-70a2-426b-a4fa-3cee666e5404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728110236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2728110236
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.951443433
Short name T376
Test name
Test status
Simulation time 457959319 ps
CPU time 2.3 seconds
Started Aug 01 06:24:33 PM PDT 24
Finished Aug 01 06:24:35 PM PDT 24
Peak memory 200228 kb
Host smart-0408e53d-3ddc-4dff-b8f8-1191f375c777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951443433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.951443433
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1178984001
Short name T86
Test name
Test status
Simulation time 175661004 ps
CPU time 1.29 seconds
Started Aug 01 06:24:45 PM PDT 24
Finished Aug 01 06:24:47 PM PDT 24
Peak memory 200436 kb
Host smart-a359f9a3-b42b-4624-ba7d-bf322f736c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178984001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1178984001
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3328023087
Short name T218
Test name
Test status
Simulation time 87361215 ps
CPU time 0.85 seconds
Started Aug 01 06:24:47 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 200068 kb
Host smart-0c39de6a-9e4b-4195-bff3-9dc8f6ee9a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328023087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3328023087
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4222257975
Short name T26
Test name
Test status
Simulation time 1914334630 ps
CPU time 6.82 seconds
Started Aug 01 06:24:36 PM PDT 24
Finished Aug 01 06:24:43 PM PDT 24
Peak memory 217668 kb
Host smart-0d56f920-b088-41dc-9090-a3cddae2afd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222257975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4222257975
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1509437866
Short name T279
Test name
Test status
Simulation time 244736546 ps
CPU time 1.08 seconds
Started Aug 01 06:24:38 PM PDT 24
Finished Aug 01 06:24:39 PM PDT 24
Peak memory 217460 kb
Host smart-1f66d7c8-7609-4e92-9cbc-c994d5ca62ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509437866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1509437866
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1519174704
Short name T195
Test name
Test status
Simulation time 196988065 ps
CPU time 0.93 seconds
Started Aug 01 06:24:44 PM PDT 24
Finished Aug 01 06:24:45 PM PDT 24
Peak memory 200068 kb
Host smart-1d632ec8-ed1c-47f2-8897-0dad1f558050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519174704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1519174704
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3742716513
Short name T131
Test name
Test status
Simulation time 1919132293 ps
CPU time 6.66 seconds
Started Aug 01 06:24:40 PM PDT 24
Finished Aug 01 06:24:47 PM PDT 24
Peak memory 200460 kb
Host smart-d2dd60af-5ce4-4c94-b6b5-513704ade7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742716513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3742716513
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1534233975
Short name T540
Test name
Test status
Simulation time 95605670 ps
CPU time 1.01 seconds
Started Aug 01 06:24:33 PM PDT 24
Finished Aug 01 06:24:34 PM PDT 24
Peak memory 200276 kb
Host smart-fcb91517-80dd-4e4f-ba5d-e5e49f5329ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534233975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1534233975
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.716355270
Short name T400
Test name
Test status
Simulation time 119580672 ps
CPU time 1.18 seconds
Started Aug 01 06:24:32 PM PDT 24
Finished Aug 01 06:24:33 PM PDT 24
Peak memory 200428 kb
Host smart-eabcf3c1-9185-4bad-b6bd-763e6457c2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716355270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.716355270
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3872065448
Short name T477
Test name
Test status
Simulation time 8685525491 ps
CPU time 32.09 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:25:21 PM PDT 24
Peak memory 200520 kb
Host smart-86254160-f554-4658-847f-4e4ff60cd189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872065448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3872065448
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1053917892
Short name T513
Test name
Test status
Simulation time 363207854 ps
CPU time 2.5 seconds
Started Aug 01 06:24:46 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 200148 kb
Host smart-74fd9539-2968-478f-967d-2aa084097c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053917892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1053917892
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2046153387
Short name T50
Test name
Test status
Simulation time 134875170 ps
CPU time 0.94 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 200252 kb
Host smart-8ecd5111-3db9-421b-80ea-5a22c47950c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046153387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2046153387
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1034705919
Short name T434
Test name
Test status
Simulation time 75154580 ps
CPU time 0.82 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:49 PM PDT 24
Peak memory 200108 kb
Host smart-13c289fe-ca21-49ed-bf13-71e0123719b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034705919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1034705919
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.4145318155
Short name T37
Test name
Test status
Simulation time 1229494908 ps
CPU time 5.49 seconds
Started Aug 01 06:24:46 PM PDT 24
Finished Aug 01 06:24:51 PM PDT 24
Peak memory 217384 kb
Host smart-8c9fd475-a3d3-4568-a9db-7ea75a3a94b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145318155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.4145318155
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3342357735
Short name T487
Test name
Test status
Simulation time 243786361 ps
CPU time 1.06 seconds
Started Aug 01 06:24:39 PM PDT 24
Finished Aug 01 06:24:40 PM PDT 24
Peak memory 217436 kb
Host smart-fad3485f-e33b-4ebf-a3c5-7717dd4930d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342357735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3342357735
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3288717356
Short name T22
Test name
Test status
Simulation time 239284487 ps
CPU time 0.97 seconds
Started Aug 01 06:24:42 PM PDT 24
Finished Aug 01 06:24:43 PM PDT 24
Peak memory 200020 kb
Host smart-c9bda295-5618-4c2e-89a1-e11920148293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288717356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3288717356
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.620549088
Short name T230
Test name
Test status
Simulation time 842737811 ps
CPU time 4.58 seconds
Started Aug 01 06:24:43 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 200472 kb
Host smart-3310ca5f-fef8-4fde-ba0b-26b831c591b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620549088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.620549088
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.4258491394
Short name T221
Test name
Test status
Simulation time 150191664 ps
CPU time 1.16 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:49 PM PDT 24
Peak memory 200244 kb
Host smart-c2c8c092-7c1c-429d-9484-982e3499372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258491394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.4258491394
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.232903328
Short name T476
Test name
Test status
Simulation time 125499497 ps
CPU time 1.25 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 200444 kb
Host smart-0ffcaa34-1646-4938-9fd3-b9802f554593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232903328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.232903328
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.4120947158
Short name T336
Test name
Test status
Simulation time 6401201172 ps
CPU time 25.9 seconds
Started Aug 01 06:24:40 PM PDT 24
Finished Aug 01 06:25:06 PM PDT 24
Peak memory 200564 kb
Host smart-25311e2a-e116-4a0e-a23e-f91773ed7fa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120947158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.4120947158
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.766144811
Short name T214
Test name
Test status
Simulation time 111531792 ps
CPU time 1.44 seconds
Started Aug 01 06:24:38 PM PDT 24
Finished Aug 01 06:24:39 PM PDT 24
Peak memory 200224 kb
Host smart-1c443d5d-0bfd-4d94-9ab1-b38b9ecd9fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766144811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.766144811
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2507604902
Short name T15
Test name
Test status
Simulation time 92784635 ps
CPU time 0.88 seconds
Started Aug 01 06:24:43 PM PDT 24
Finished Aug 01 06:24:44 PM PDT 24
Peak memory 200252 kb
Host smart-efcee423-b8c4-484d-87d2-2c021c687b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507604902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2507604902
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.418474983
Short name T433
Test name
Test status
Simulation time 68273052 ps
CPU time 0.73 seconds
Started Aug 01 06:24:49 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 200100 kb
Host smart-9b287e7c-c0a8-477f-b8d1-94aa4693c57d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418474983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.418474983
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3585002018
Short name T30
Test name
Test status
Simulation time 1898337045 ps
CPU time 6.93 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:25:04 PM PDT 24
Peak memory 221684 kb
Host smart-5e89b761-def3-4160-bf33-e4f6e96b03c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585002018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3585002018
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3065135400
Short name T378
Test name
Test status
Simulation time 243941032 ps
CPU time 1.08 seconds
Started Aug 01 06:24:45 PM PDT 24
Finished Aug 01 06:24:47 PM PDT 24
Peak memory 217488 kb
Host smart-4bf6fe66-dc25-4a02-aa5b-08f5e44e53b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065135400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3065135400
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2369816469
Short name T413
Test name
Test status
Simulation time 129696999 ps
CPU time 0.83 seconds
Started Aug 01 06:24:41 PM PDT 24
Finished Aug 01 06:24:42 PM PDT 24
Peak memory 200088 kb
Host smart-167dcdb4-9052-4a11-8e75-73b053ce6737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369816469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2369816469
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1040307733
Short name T441
Test name
Test status
Simulation time 751032941 ps
CPU time 3.93 seconds
Started Aug 01 06:24:41 PM PDT 24
Finished Aug 01 06:24:45 PM PDT 24
Peak memory 200548 kb
Host smart-78c1136e-5e38-4267-9307-159badb740d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040307733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1040307733
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2530080772
Short name T325
Test name
Test status
Simulation time 108692401 ps
CPU time 1.02 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200288 kb
Host smart-6434257c-ca1b-442d-9d5a-27885aaa4f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530080772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2530080772
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1035177035
Short name T534
Test name
Test status
Simulation time 257195201 ps
CPU time 1.43 seconds
Started Aug 01 06:24:47 PM PDT 24
Finished Aug 01 06:24:49 PM PDT 24
Peak memory 200420 kb
Host smart-2d7e9081-d1ed-46ce-afc2-6f22e603bc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035177035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1035177035
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1865128277
Short name T324
Test name
Test status
Simulation time 16309612610 ps
CPU time 54.04 seconds
Started Aug 01 06:24:40 PM PDT 24
Finished Aug 01 06:25:34 PM PDT 24
Peak memory 208732 kb
Host smart-918ca898-4f3c-4401-9743-d8d3264e84c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865128277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1865128277
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.66142150
Short name T331
Test name
Test status
Simulation time 364774799 ps
CPU time 2.48 seconds
Started Aug 01 06:24:45 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 200220 kb
Host smart-5c250a5d-1fb6-4547-a3dc-5ba3301a1771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66142150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.66142150
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3789060194
Short name T157
Test name
Test status
Simulation time 97897850 ps
CPU time 0.91 seconds
Started Aug 01 06:24:41 PM PDT 24
Finished Aug 01 06:24:42 PM PDT 24
Peak memory 200264 kb
Host smart-b5e89ea7-6365-4bbe-af74-4b2eb78c9267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789060194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3789060194
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1338069077
Short name T164
Test name
Test status
Simulation time 73106560 ps
CPU time 0.75 seconds
Started Aug 01 06:24:49 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 200104 kb
Host smart-c12b0522-d754-4b37-bdc2-437d225dd3e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338069077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1338069077
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.81011824
Short name T455
Test name
Test status
Simulation time 2362976009 ps
CPU time 7.87 seconds
Started Aug 01 06:24:52 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 221308 kb
Host smart-9c8f14c4-897a-4172-93db-ab56a99ac6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81011824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.81011824
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3133659703
Short name T492
Test name
Test status
Simulation time 243874920 ps
CPU time 1.03 seconds
Started Aug 01 06:24:49 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 217432 kb
Host smart-bc5f94a5-cb1e-4feb-b598-1a426d798d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133659703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3133659703
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.239342947
Short name T206
Test name
Test status
Simulation time 78538982 ps
CPU time 0.72 seconds
Started Aug 01 06:24:44 PM PDT 24
Finished Aug 01 06:24:45 PM PDT 24
Peak memory 200068 kb
Host smart-ac555454-f99b-4073-af19-3529412dd4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239342947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.239342947
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2379751413
Short name T256
Test name
Test status
Simulation time 1250882477 ps
CPU time 4.86 seconds
Started Aug 01 06:24:43 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 200464 kb
Host smart-e2d4219b-e17f-45dc-b56c-af65f38ef8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379751413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2379751413
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1606427184
Short name T377
Test name
Test status
Simulation time 100455646 ps
CPU time 1.03 seconds
Started Aug 01 06:24:44 PM PDT 24
Finished Aug 01 06:24:46 PM PDT 24
Peak memory 200300 kb
Host smart-103bf155-652e-4a79-9d0a-d0a46a420c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606427184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1606427184
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3763676080
Short name T480
Test name
Test status
Simulation time 125524756 ps
CPU time 1.16 seconds
Started Aug 01 06:24:46 PM PDT 24
Finished Aug 01 06:24:47 PM PDT 24
Peak memory 200404 kb
Host smart-4b98f4f9-9fe5-4951-9086-0115628fc459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763676080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3763676080
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1290584703
Short name T352
Test name
Test status
Simulation time 9895270272 ps
CPU time 35.72 seconds
Started Aug 01 06:24:49 PM PDT 24
Finished Aug 01 06:25:25 PM PDT 24
Peak memory 208760 kb
Host smart-5aca58cd-8012-4a7a-ac19-2e92d3af024a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290584703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1290584703
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3703455699
Short name T459
Test name
Test status
Simulation time 139408498 ps
CPU time 1.84 seconds
Started Aug 01 06:24:51 PM PDT 24
Finished Aug 01 06:24:53 PM PDT 24
Peak memory 200176 kb
Host smart-94d80ed9-759e-4a1c-b943-030c56f1e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703455699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3703455699
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3694654228
Short name T312
Test name
Test status
Simulation time 116118666 ps
CPU time 1.03 seconds
Started Aug 01 06:24:42 PM PDT 24
Finished Aug 01 06:24:43 PM PDT 24
Peak memory 200228 kb
Host smart-b885750f-87d7-4952-a94e-07f693c39f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694654228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3694654228
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.965015345
Short name T228
Test name
Test status
Simulation time 59415641 ps
CPU time 0.75 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 200036 kb
Host smart-095549cc-aeac-4f75-b6f6-d02447b2cfb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965015345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.965015345
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2084162397
Short name T392
Test name
Test status
Simulation time 2363587879 ps
CPU time 7.84 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:56 PM PDT 24
Peak memory 217324 kb
Host smart-0182e4da-6f8f-461e-ab50-a40129cddc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084162397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2084162397
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1300101325
Short name T454
Test name
Test status
Simulation time 246197833 ps
CPU time 1.02 seconds
Started Aug 01 06:24:45 PM PDT 24
Finished Aug 01 06:24:47 PM PDT 24
Peak memory 217408 kb
Host smart-e9d723e9-2ef7-4af9-8e21-dccb92d48233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300101325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1300101325
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3409399873
Short name T16
Test name
Test status
Simulation time 186995835 ps
CPU time 0.95 seconds
Started Aug 01 06:24:43 PM PDT 24
Finished Aug 01 06:24:44 PM PDT 24
Peak memory 200056 kb
Host smart-a955ae2f-58b1-45e1-ab25-0ac798879546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409399873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3409399873
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.4241141554
Short name T108
Test name
Test status
Simulation time 709285678 ps
CPU time 3.88 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 200492 kb
Host smart-3e68badf-7c8c-47d8-82d4-5b3908381c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241141554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.4241141554
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1677176684
Short name T314
Test name
Test status
Simulation time 183233681 ps
CPU time 1.17 seconds
Started Aug 01 06:24:49 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 200256 kb
Host smart-3033a879-2240-43bd-9f64-db76e68e7552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677176684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1677176684
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.466004619
Short name T135
Test name
Test status
Simulation time 254240223 ps
CPU time 1.48 seconds
Started Aug 01 06:24:49 PM PDT 24
Finished Aug 01 06:24:51 PM PDT 24
Peak memory 200432 kb
Host smart-eabd23ee-5d8c-4ca3-a300-85782fbd0409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466004619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.466004619
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3810507484
Short name T370
Test name
Test status
Simulation time 5581909369 ps
CPU time 26.56 seconds
Started Aug 01 06:24:54 PM PDT 24
Finished Aug 01 06:25:20 PM PDT 24
Peak memory 208796 kb
Host smart-f408df47-76f1-4617-a881-2e2db6112547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810507484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3810507484
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3147987503
Short name T293
Test name
Test status
Simulation time 108031318 ps
CPU time 1.42 seconds
Started Aug 01 06:24:42 PM PDT 24
Finished Aug 01 06:24:44 PM PDT 24
Peak memory 200248 kb
Host smart-4fe75f8c-62a6-448b-bdbd-772f0daae37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147987503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3147987503
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3091523959
Short name T394
Test name
Test status
Simulation time 123910871 ps
CPU time 1.02 seconds
Started Aug 01 06:24:47 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 200268 kb
Host smart-0bcc62cb-536d-422c-8514-5903d4f9172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091523959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3091523959
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1846850877
Short name T179
Test name
Test status
Simulation time 69115200 ps
CPU time 0.82 seconds
Started Aug 01 06:24:43 PM PDT 24
Finished Aug 01 06:24:44 PM PDT 24
Peak memory 200112 kb
Host smart-c7c319f1-3e5c-4b01-9256-79acc8db904d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846850877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1846850877
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.955440391
Short name T8
Test name
Test status
Simulation time 2367381179 ps
CPU time 8.04 seconds
Started Aug 01 06:24:54 PM PDT 24
Finished Aug 01 06:25:02 PM PDT 24
Peak memory 221472 kb
Host smart-acc5f548-d842-4ed6-8ee5-00f186c80575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955440391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.955440391
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3751431430
Short name T282
Test name
Test status
Simulation time 244283036 ps
CPU time 1.06 seconds
Started Aug 01 06:24:44 PM PDT 24
Finished Aug 01 06:24:45 PM PDT 24
Peak memory 217408 kb
Host smart-bbfbe26a-70f5-41dd-ba27-6381ccd190da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751431430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3751431430
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3187514719
Short name T14
Test name
Test status
Simulation time 87451603 ps
CPU time 0.77 seconds
Started Aug 01 06:24:46 PM PDT 24
Finished Aug 01 06:24:47 PM PDT 24
Peak memory 200092 kb
Host smart-d1e81b25-c174-41e9-8a37-834b42492c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187514719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3187514719
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.863038006
Short name T80
Test name
Test status
Simulation time 1709922061 ps
CPU time 6.39 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:25:03 PM PDT 24
Peak memory 200500 kb
Host smart-3208350d-5890-48ac-98a3-c0ea3e5bc313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863038006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.863038006
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4066095564
Short name T181
Test name
Test status
Simulation time 155488752 ps
CPU time 1.11 seconds
Started Aug 01 06:24:50 PM PDT 24
Finished Aug 01 06:24:51 PM PDT 24
Peak memory 200352 kb
Host smart-999602f5-73f3-419e-b2be-eb4dca7c2c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066095564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4066095564
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2746820833
Short name T236
Test name
Test status
Simulation time 127577178 ps
CPU time 1.16 seconds
Started Aug 01 06:24:50 PM PDT 24
Finished Aug 01 06:24:51 PM PDT 24
Peak memory 200436 kb
Host smart-6e55c1ac-99c7-4588-91fc-ea83b47a74fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746820833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2746820833
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1179558422
Short name T305
Test name
Test status
Simulation time 236617122 ps
CPU time 1.21 seconds
Started Aug 01 06:24:45 PM PDT 24
Finished Aug 01 06:24:47 PM PDT 24
Peak memory 200268 kb
Host smart-32fb80c7-5604-4ba1-b773-9bce55643bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179558422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1179558422
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2655702357
Short name T501
Test name
Test status
Simulation time 148788944 ps
CPU time 1.8 seconds
Started Aug 01 06:24:47 PM PDT 24
Finished Aug 01 06:24:49 PM PDT 24
Peak memory 200192 kb
Host smart-a1e1c7af-db04-4888-b940-3cd7abafdd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655702357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2655702357
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3841668927
Short name T482
Test name
Test status
Simulation time 240823496 ps
CPU time 1.36 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:24:57 PM PDT 24
Peak memory 200432 kb
Host smart-40bef495-8d27-42bb-8176-99269767417d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841668927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3841668927
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1503792239
Short name T429
Test name
Test status
Simulation time 82195734 ps
CPU time 0.87 seconds
Started Aug 01 06:24:12 PM PDT 24
Finished Aug 01 06:24:13 PM PDT 24
Peak memory 200100 kb
Host smart-ae8abad0-7428-4492-b704-f5b1feeb55aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503792239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1503792239
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.663906622
Short name T397
Test name
Test status
Simulation time 244614059 ps
CPU time 1.02 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:09 PM PDT 24
Peak memory 217496 kb
Host smart-4ea08f95-8350-481d-94a0-048a4a56efb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663906622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.663906622
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1477925744
Short name T442
Test name
Test status
Simulation time 198542373 ps
CPU time 0.94 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200096 kb
Host smart-19b79fbe-17bd-4adf-ba37-d11586dc0125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477925744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1477925744
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2608626290
Short name T268
Test name
Test status
Simulation time 1035036708 ps
CPU time 5.31 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:15 PM PDT 24
Peak memory 200776 kb
Host smart-fb3a5fb3-835c-46f3-a4c7-51eb654aecbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608626290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2608626290
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3983698410
Short name T71
Test name
Test status
Simulation time 16682655742 ps
CPU time 24.37 seconds
Started Aug 01 06:24:13 PM PDT 24
Finished Aug 01 06:24:37 PM PDT 24
Peak memory 217212 kb
Host smart-20242df0-eefc-460b-b696-0019bddc72b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983698410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3983698410
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.102749404
Short name T301
Test name
Test status
Simulation time 166153187 ps
CPU time 1.28 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 200520 kb
Host smart-fe061971-5ff1-4bc1-97a7-582a0c090a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102749404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.102749404
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.717920934
Short name T83
Test name
Test status
Simulation time 112021739 ps
CPU time 1.19 seconds
Started Aug 01 06:24:18 PM PDT 24
Finished Aug 01 06:24:20 PM PDT 24
Peak memory 200432 kb
Host smart-b5c7696b-ef3d-4bf1-b240-e142f9648171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717920934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.717920934
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3174761469
Short name T543
Test name
Test status
Simulation time 4441906913 ps
CPU time 15.87 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:27 PM PDT 24
Peak memory 200580 kb
Host smart-a5940262-9489-4d4a-a537-e2804b6c012e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174761469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3174761469
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.4009240703
Short name T505
Test name
Test status
Simulation time 327738856 ps
CPU time 2.05 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200208 kb
Host smart-9f7e6bc5-9e94-4583-b96b-d84c952a610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009240703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4009240703
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1646658856
Short name T211
Test name
Test status
Simulation time 145576739 ps
CPU time 1.26 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200248 kb
Host smart-5ef6361b-6226-4c72-b07a-34278aa5e965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646658856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1646658856
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1115877763
Short name T160
Test name
Test status
Simulation time 66982702 ps
CPU time 0.71 seconds
Started Aug 01 06:24:45 PM PDT 24
Finished Aug 01 06:24:46 PM PDT 24
Peak memory 200108 kb
Host smart-6905d96e-96a1-48a4-b60d-0393b3a63a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115877763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1115877763
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.4010400844
Short name T48
Test name
Test status
Simulation time 1895002639 ps
CPU time 6.86 seconds
Started Aug 01 06:24:47 PM PDT 24
Finished Aug 01 06:24:54 PM PDT 24
Peak memory 217200 kb
Host smart-b977b8a8-827c-4249-9a6c-0bfb0c665812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010400844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.4010400844
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3137101900
Short name T150
Test name
Test status
Simulation time 244792464 ps
CPU time 1.04 seconds
Started Aug 01 06:24:47 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 217396 kb
Host smart-c0dce3ef-4443-48fd-acb2-e40d8349eda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137101900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3137101900
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.854942070
Short name T191
Test name
Test status
Simulation time 195661370 ps
CPU time 0.86 seconds
Started Aug 01 06:24:50 PM PDT 24
Finished Aug 01 06:24:51 PM PDT 24
Peak memory 200032 kb
Host smart-5d3acdaf-cd3a-4d69-9910-a992175d23dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854942070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.854942070
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3873765515
Short name T466
Test name
Test status
Simulation time 1475173349 ps
CPU time 5.65 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:54 PM PDT 24
Peak memory 200496 kb
Host smart-a24e3d7c-d6d5-4654-bf09-7778f1507780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873765515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3873765515
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2806404400
Short name T261
Test name
Test status
Simulation time 167666889 ps
CPU time 1.13 seconds
Started Aug 01 06:24:46 PM PDT 24
Finished Aug 01 06:24:47 PM PDT 24
Peak memory 200244 kb
Host smart-897b569b-cbe7-4da2-90c6-b971c2254fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806404400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2806404400
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3880398132
Short name T262
Test name
Test status
Simulation time 184041799 ps
CPU time 1.48 seconds
Started Aug 01 06:24:46 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 200424 kb
Host smart-a05bf905-b34c-4f1f-9874-03736e1e90b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880398132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3880398132
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3769204358
Short name T90
Test name
Test status
Simulation time 151947071 ps
CPU time 1.92 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:51 PM PDT 24
Peak memory 200244 kb
Host smart-c693e9f0-fefd-43b3-84dc-d014a47d04b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769204358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3769204358
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.36226473
Short name T453
Test name
Test status
Simulation time 118790054 ps
CPU time 1.03 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:24:57 PM PDT 24
Peak memory 200280 kb
Host smart-225bd8a3-e746-4f66-a504-502326574968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36226473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.36226473
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1724320400
Short name T341
Test name
Test status
Simulation time 78572028 ps
CPU time 0.77 seconds
Started Aug 01 06:24:51 PM PDT 24
Finished Aug 01 06:24:52 PM PDT 24
Peak memory 200060 kb
Host smart-3f26ce9d-28a1-478a-9b82-e3a752f96e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724320400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1724320400
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.4143231851
Short name T57
Test name
Test status
Simulation time 1875546302 ps
CPU time 6.84 seconds
Started Aug 01 06:24:50 PM PDT 24
Finished Aug 01 06:24:57 PM PDT 24
Peak memory 221616 kb
Host smart-399b9e12-156b-42f3-8de3-2850bf7712de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143231851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.4143231851
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2711363153
Short name T223
Test name
Test status
Simulation time 247031771 ps
CPU time 1.01 seconds
Started Aug 01 06:24:51 PM PDT 24
Finished Aug 01 06:24:52 PM PDT 24
Peak memory 217464 kb
Host smart-6bca9fd3-062a-4c4c-80d7-9e99da988041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711363153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2711363153
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3019225558
Short name T388
Test name
Test status
Simulation time 215816203 ps
CPU time 0.95 seconds
Started Aug 01 06:24:49 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 200068 kb
Host smart-eb1c3d6d-6e2f-454c-9502-336c6929fa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019225558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3019225558
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2458205070
Short name T105
Test name
Test status
Simulation time 1298045517 ps
CPU time 5.09 seconds
Started Aug 01 06:24:53 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200728 kb
Host smart-27132b2d-a34f-4f9e-b6b7-2e882fb594b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458205070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2458205070
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2350200788
Short name T423
Test name
Test status
Simulation time 174704493 ps
CPU time 1.17 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200324 kb
Host smart-4f5a5512-fac8-413a-8053-a5bc024376cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350200788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2350200788
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.992699768
Short name T302
Test name
Test status
Simulation time 115077334 ps
CPU time 1.19 seconds
Started Aug 01 06:24:50 PM PDT 24
Finished Aug 01 06:24:51 PM PDT 24
Peak memory 200396 kb
Host smart-d9ea1bc3-c84e-4d4f-ab21-85da9adfa2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992699768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.992699768
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2047320909
Short name T84
Test name
Test status
Simulation time 1875928608 ps
CPU time 7.36 seconds
Started Aug 01 06:24:45 PM PDT 24
Finished Aug 01 06:24:53 PM PDT 24
Peak memory 200484 kb
Host smart-ca295376-dae2-4fd6-b5fe-49962dd3408d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047320909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2047320909
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2880839274
Short name T273
Test name
Test status
Simulation time 318120050 ps
CPU time 2.33 seconds
Started Aug 01 06:24:45 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 200216 kb
Host smart-d80c779d-caab-46f1-9464-51a4e5af12ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880839274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2880839274
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.932519003
Short name T239
Test name
Test status
Simulation time 172250372 ps
CPU time 1.17 seconds
Started Aug 01 06:24:50 PM PDT 24
Finished Aug 01 06:24:52 PM PDT 24
Peak memory 200228 kb
Host smart-38a2624c-e0c7-415d-93b2-725ec97b00d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932519003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.932519003
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1000930454
Short name T186
Test name
Test status
Simulation time 70026703 ps
CPU time 0.74 seconds
Started Aug 01 06:24:55 PM PDT 24
Finished Aug 01 06:24:56 PM PDT 24
Peak memory 200108 kb
Host smart-512fe962-c164-4dbb-b268-1945fa27d8a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000930454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1000930454
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2601514195
Short name T34
Test name
Test status
Simulation time 1886124217 ps
CPU time 6.86 seconds
Started Aug 01 06:24:47 PM PDT 24
Finished Aug 01 06:24:54 PM PDT 24
Peak memory 220776 kb
Host smart-2ffa271a-5ea3-458d-83e4-9bdcd8a3cc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601514195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2601514195
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.747905914
Short name T250
Test name
Test status
Simulation time 244028355 ps
CPU time 1.07 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 217372 kb
Host smart-ea10b6a0-1d5b-4742-bea9-bb2efa1bb430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747905914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.747905914
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.950200079
Short name T530
Test name
Test status
Simulation time 145952872 ps
CPU time 0.83 seconds
Started Aug 01 06:24:53 PM PDT 24
Finished Aug 01 06:24:54 PM PDT 24
Peak memory 200056 kb
Host smart-f01e1599-d6cf-41ad-8711-1d38fca5fbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950200079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.950200079
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2234085944
Short name T353
Test name
Test status
Simulation time 1758878322 ps
CPU time 6.26 seconds
Started Aug 01 06:24:51 PM PDT 24
Finished Aug 01 06:24:58 PM PDT 24
Peak memory 200436 kb
Host smart-2fc95b7f-595c-4306-b089-1f24d5c53bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234085944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2234085944
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1846410776
Short name T449
Test name
Test status
Simulation time 137361151 ps
CPU time 1.14 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 200344 kb
Host smart-9a438cfa-95cf-40d4-a526-3047b8068bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846410776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1846410776
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.39979397
Short name T422
Test name
Test status
Simulation time 119151520 ps
CPU time 1.13 seconds
Started Aug 01 06:24:53 PM PDT 24
Finished Aug 01 06:24:54 PM PDT 24
Peak memory 200404 kb
Host smart-3205b01c-ec0b-47ce-ad82-d2955e388d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39979397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.39979397
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2254993073
Short name T212
Test name
Test status
Simulation time 2958220107 ps
CPU time 13.21 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:25:09 PM PDT 24
Peak memory 200556 kb
Host smart-a557b972-3089-40f4-a8b5-688ccbed696c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254993073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2254993073
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4138239437
Short name T269
Test name
Test status
Simulation time 511238111 ps
CPU time 2.63 seconds
Started Aug 01 06:24:51 PM PDT 24
Finished Aug 01 06:24:53 PM PDT 24
Peak memory 200176 kb
Host smart-fc173d29-f7b8-4ee2-8f81-7cf53f70b38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138239437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4138239437
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3323364270
Short name T165
Test name
Test status
Simulation time 85663156 ps
CPU time 0.96 seconds
Started Aug 01 06:24:48 PM PDT 24
Finished Aug 01 06:24:50 PM PDT 24
Peak memory 200340 kb
Host smart-b974acb4-4d08-4297-ab01-56d6059c0271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323364270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3323364270
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2194550687
Short name T417
Test name
Test status
Simulation time 69858262 ps
CPU time 0.76 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200092 kb
Host smart-afde2218-9e0c-4d91-b26a-40161c7564a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194550687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2194550687
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2360485868
Short name T299
Test name
Test status
Simulation time 1221869516 ps
CPU time 5.51 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:25:03 PM PDT 24
Peak memory 216960 kb
Host smart-b019ba42-d236-4b9b-925a-8f53b9754fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360485868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2360485868
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3757071351
Short name T10
Test name
Test status
Simulation time 244872077 ps
CPU time 1.11 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 217456 kb
Host smart-415c3237-e549-40c4-abef-13f19cd73b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757071351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3757071351
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2670505554
Short name T340
Test name
Test status
Simulation time 139039195 ps
CPU time 0.8 seconds
Started Aug 01 06:25:06 PM PDT 24
Finished Aug 01 06:25:07 PM PDT 24
Peak memory 200060 kb
Host smart-00038275-c6aa-47ca-bedb-0c65c93de21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670505554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2670505554
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.632016966
Short name T463
Test name
Test status
Simulation time 1457715956 ps
CPU time 5.49 seconds
Started Aug 01 06:24:53 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200500 kb
Host smart-770b9ba2-ed6f-407a-b535-b06837e82c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632016966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.632016966
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2735259047
Short name T213
Test name
Test status
Simulation time 101444311 ps
CPU time 0.98 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 200300 kb
Host smart-330e1790-0063-4dfa-a7cb-4d281ffe506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735259047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2735259047
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1094249437
Short name T439
Test name
Test status
Simulation time 226153790 ps
CPU time 1.56 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 200428 kb
Host smart-2627fcfd-6dc8-47aa-80d0-167c68a59d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094249437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1094249437
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.371834013
Short name T41
Test name
Test status
Simulation time 1074161490 ps
CPU time 4.68 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:25:02 PM PDT 24
Peak memory 200552 kb
Host smart-2b4f3edd-e800-4ac8-8111-a9b15a630a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371834013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.371834013
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.382576796
Short name T403
Test name
Test status
Simulation time 328740597 ps
CPU time 2.09 seconds
Started Aug 01 06:25:00 PM PDT 24
Finished Aug 01 06:25:02 PM PDT 24
Peak memory 200236 kb
Host smart-955e7b3d-d229-4d26-8f5a-2b277e07b000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382576796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.382576796
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3187294134
Short name T271
Test name
Test status
Simulation time 140691629 ps
CPU time 1.12 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:24:57 PM PDT 24
Peak memory 200296 kb
Host smart-bd0b2ea2-3849-4340-9fa5-f617ee10f438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187294134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3187294134
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.178593465
Short name T318
Test name
Test status
Simulation time 81150749 ps
CPU time 0.8 seconds
Started Aug 01 06:25:00 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 200152 kb
Host smart-72c07dfd-f8e1-454f-b0a6-d54ae0289708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178593465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.178593465
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2272664347
Short name T249
Test name
Test status
Simulation time 2336336988 ps
CPU time 8.28 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:07 PM PDT 24
Peak memory 217732 kb
Host smart-3a543fb5-60de-4ee6-a144-5488c0a40063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272664347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2272664347
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3173627775
Short name T149
Test name
Test status
Simulation time 244152210 ps
CPU time 1.06 seconds
Started Aug 01 06:25:08 PM PDT 24
Finished Aug 01 06:25:09 PM PDT 24
Peak memory 217476 kb
Host smart-92bd58f9-7075-44eb-aaaf-55171b35a78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173627775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3173627775
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.711957702
Short name T241
Test name
Test status
Simulation time 223656962 ps
CPU time 0.92 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:24:58 PM PDT 24
Peak memory 200092 kb
Host smart-2f57a3fa-fd6c-497b-a17c-a7acfc1f8271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711957702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.711957702
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.192524987
Short name T177
Test name
Test status
Simulation time 1060746561 ps
CPU time 5.18 seconds
Started Aug 01 06:24:55 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 200548 kb
Host smart-384cd5a6-1c5c-475c-bf7b-7fedd929ce45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192524987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.192524987
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2412165765
Short name T419
Test name
Test status
Simulation time 137157124 ps
CPU time 1.12 seconds
Started Aug 01 06:25:19 PM PDT 24
Finished Aug 01 06:25:20 PM PDT 24
Peak memory 200276 kb
Host smart-f417a5dd-ce17-4e10-9c78-bf30f4e70d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412165765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2412165765
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.551867943
Short name T227
Test name
Test status
Simulation time 195731345 ps
CPU time 1.39 seconds
Started Aug 01 06:25:02 PM PDT 24
Finished Aug 01 06:25:03 PM PDT 24
Peak memory 200472 kb
Host smart-0550ed57-69dc-4d1b-bd56-0f27d9c260b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551867943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.551867943
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3207989314
Short name T137
Test name
Test status
Simulation time 11080867539 ps
CPU time 44.24 seconds
Started Aug 01 06:24:53 PM PDT 24
Finished Aug 01 06:25:38 PM PDT 24
Peak memory 200544 kb
Host smart-38fca42c-eaf4-439c-93fa-416ba8b25798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207989314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3207989314
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.989800893
Short name T414
Test name
Test status
Simulation time 115414825 ps
CPU time 1.43 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:24:58 PM PDT 24
Peak memory 200240 kb
Host smart-66727cc1-658f-4928-902f-dfe038cf3e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989800893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.989800893
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3780578436
Short name T542
Test name
Test status
Simulation time 228284454 ps
CPU time 1.46 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200360 kb
Host smart-ba4245f1-ecf7-48f8-96b3-bae9a0334a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780578436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3780578436
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1173987599
Short name T528
Test name
Test status
Simulation time 61330880 ps
CPU time 0.71 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 200040 kb
Host smart-d067a287-71c4-453a-9716-8e31ee4cdd9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173987599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1173987599
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.692671409
Short name T55
Test name
Test status
Simulation time 2352958560 ps
CPU time 9.25 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:08 PM PDT 24
Peak memory 221468 kb
Host smart-50feb124-90da-41c6-a3d9-cc379602f6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692671409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.692671409
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.778334992
Short name T354
Test name
Test status
Simulation time 244202101 ps
CPU time 1.13 seconds
Started Aug 01 06:25:00 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 217496 kb
Host smart-0a08e57a-6202-47d9-8af6-405cbaa02964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778334992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.778334992
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.22115778
Short name T21
Test name
Test status
Simulation time 184160707 ps
CPU time 0.85 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:24:57 PM PDT 24
Peak memory 200080 kb
Host smart-6a50bc6b-66c1-4c7f-bd6d-c1d96ea1a030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22115778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.22115778
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1658186349
Short name T430
Test name
Test status
Simulation time 954625706 ps
CPU time 4.86 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 200496 kb
Host smart-004e0e45-a55a-4217-9df2-5326064cba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658186349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1658186349
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3229258979
Short name T440
Test name
Test status
Simulation time 181414483 ps
CPU time 1.19 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200268 kb
Host smart-1e8766f8-4f88-4ed0-80d9-4b3007ce8ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229258979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3229258979
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1074453618
Short name T207
Test name
Test status
Simulation time 193110116 ps
CPU time 1.34 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200476 kb
Host smart-0d2672e3-9bb7-4139-bb31-6b997cfbaee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074453618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1074453618
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.429243457
Short name T469
Test name
Test status
Simulation time 4610826081 ps
CPU time 18.16 seconds
Started Aug 01 06:24:54 PM PDT 24
Finished Aug 01 06:25:12 PM PDT 24
Peak memory 208724 kb
Host smart-ff1ef19c-c62d-44db-bd1f-63417d39f412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429243457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.429243457
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.151090839
Short name T329
Test name
Test status
Simulation time 144660835 ps
CPU time 1.77 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200240 kb
Host smart-d535bfc1-f8c2-4fff-b301-bb6599291f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151090839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.151090839
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2636123945
Short name T237
Test name
Test status
Simulation time 241580462 ps
CPU time 1.42 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200268 kb
Host smart-fbc5c45c-0c34-47b2-abe8-28460b5e3f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636123945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2636123945
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.225256351
Short name T184
Test name
Test status
Simulation time 73739098 ps
CPU time 0.78 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:24:58 PM PDT 24
Peak memory 200100 kb
Host smart-99deab77-9efc-45d0-9246-f3862353f879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225256351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.225256351
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3270844101
Short name T39
Test name
Test status
Simulation time 1900290512 ps
CPU time 7.29 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:25:05 PM PDT 24
Peak memory 221628 kb
Host smart-462920f5-71d0-4ef1-b1e4-71fe00248fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270844101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3270844101
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1034950200
Short name T3
Test name
Test status
Simulation time 245697167 ps
CPU time 1.07 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:06 PM PDT 24
Peak memory 217452 kb
Host smart-860e1a47-a68f-45b7-b043-b2d9b22162a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034950200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1034950200
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2004382600
Short name T330
Test name
Test status
Simulation time 161829372 ps
CPU time 0.81 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 200100 kb
Host smart-a7bb60a8-b53d-4a01-af80-bc429346b739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004382600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2004382600
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.4127436190
Short name T415
Test name
Test status
Simulation time 1648828832 ps
CPU time 6.18 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:25:03 PM PDT 24
Peak memory 200504 kb
Host smart-e0a4904a-ad20-4f4d-bf55-eb31d390e740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127436190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.4127436190
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2005591586
Short name T245
Test name
Test status
Simulation time 98067420 ps
CPU time 1.01 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200292 kb
Host smart-91c910e7-bca9-4ea1-a591-f2fd738e3793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005591586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2005591586
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.53734922
Short name T12
Test name
Test status
Simulation time 194491485 ps
CPU time 1.35 seconds
Started Aug 01 06:25:15 PM PDT 24
Finished Aug 01 06:25:16 PM PDT 24
Peak memory 200436 kb
Host smart-5c44d1bc-6058-4bc2-92c2-f3d118cf48d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53734922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.53734922
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.251255684
Short name T107
Test name
Test status
Simulation time 9606518115 ps
CPU time 33.49 seconds
Started Aug 01 06:25:04 PM PDT 24
Finished Aug 01 06:25:37 PM PDT 24
Peak memory 208792 kb
Host smart-8f0484db-fc00-4659-97f2-e5c52e8f3a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251255684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.251255684
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1625843879
Short name T504
Test name
Test status
Simulation time 364111971 ps
CPU time 2.02 seconds
Started Aug 01 06:25:00 PM PDT 24
Finished Aug 01 06:25:02 PM PDT 24
Peak memory 200236 kb
Host smart-825be992-dcca-4280-9c69-99de1b047068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625843879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1625843879
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.285811994
Short name T199
Test name
Test status
Simulation time 68986350 ps
CPU time 0.81 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 200288 kb
Host smart-9c8cf74f-e2ab-43e6-a399-af4786d5b6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285811994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.285811994
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.900946936
Short name T287
Test name
Test status
Simulation time 60204336 ps
CPU time 0.73 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 200100 kb
Host smart-0b57c988-84c0-4c25-bfb1-5387e8421b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900946936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.900946936
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3402436481
Short name T46
Test name
Test status
Simulation time 1225170667 ps
CPU time 5.48 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:03 PM PDT 24
Peak memory 221620 kb
Host smart-3d98ec47-04c7-4229-89ea-ae7db675f1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402436481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3402436481
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1280556368
Short name T319
Test name
Test status
Simulation time 245023470 ps
CPU time 1.05 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 217468 kb
Host smart-1f334bb4-72fc-4145-bc13-7b61f01a4535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280556368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1280556368
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.32923827
Short name T497
Test name
Test status
Simulation time 125487205 ps
CPU time 0.82 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200100 kb
Host smart-e54a2c7f-c5ea-465d-b628-5e835bfcf28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32923827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.32923827
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3385177169
Short name T132
Test name
Test status
Simulation time 1849369232 ps
CPU time 6.78 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:06 PM PDT 24
Peak memory 200284 kb
Host smart-f5c07bff-76c1-4e81-8341-cf6a690dc6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385177169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3385177169
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1235986938
Short name T274
Test name
Test status
Simulation time 100442721 ps
CPU time 1.01 seconds
Started Aug 01 06:25:10 PM PDT 24
Finished Aug 01 06:25:11 PM PDT 24
Peak memory 200244 kb
Host smart-0d0e3cf4-ec94-46e0-881c-25c26512ba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235986938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1235986938
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.4154098461
Short name T387
Test name
Test status
Simulation time 197706417 ps
CPU time 1.41 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 200444 kb
Host smart-26d4cf43-b81f-4dd2-a135-544074adafba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154098461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4154098461
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1052621788
Short name T537
Test name
Test status
Simulation time 4580981119 ps
CPU time 21.97 seconds
Started Aug 01 06:25:18 PM PDT 24
Finished Aug 01 06:25:40 PM PDT 24
Peak memory 200520 kb
Host smart-77fd4ccc-bf65-4a57-bc3e-97a20492db25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052621788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1052621788
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2206121245
Short name T334
Test name
Test status
Simulation time 144116014 ps
CPU time 1.73 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:24:58 PM PDT 24
Peak memory 200248 kb
Host smart-ace43d2b-bf9d-412a-bb8d-8e861e195cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206121245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2206121245
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1186365562
Short name T144
Test name
Test status
Simulation time 231204921 ps
CPU time 1.34 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 200476 kb
Host smart-9de15647-466e-4d5e-8381-a74236b07fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186365562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1186365562
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2892877373
Short name T74
Test name
Test status
Simulation time 82746248 ps
CPU time 0.8 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:24:57 PM PDT 24
Peak memory 200100 kb
Host smart-41d7d7f3-9418-4ee2-aecc-e79a2fc59711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892877373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2892877373
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3485617406
Short name T278
Test name
Test status
Simulation time 1226782340 ps
CPU time 5.58 seconds
Started Aug 01 06:25:00 PM PDT 24
Finished Aug 01 06:25:06 PM PDT 24
Peak memory 217596 kb
Host smart-ab2583e8-45e4-41b4-aad4-8b8798660d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485617406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3485617406
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2605807434
Short name T323
Test name
Test status
Simulation time 244323662 ps
CPU time 1.09 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:24:58 PM PDT 24
Peak memory 217464 kb
Host smart-5042e2d6-ffc4-40dd-a357-6dc4be157cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605807434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2605807434
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2102707910
Short name T525
Test name
Test status
Simulation time 109414079 ps
CPU time 0.77 seconds
Started Aug 01 06:25:00 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 200048 kb
Host smart-48b96a76-1801-4283-af0a-514eeeaecbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102707910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2102707910
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1161086838
Short name T102
Test name
Test status
Simulation time 949992844 ps
CPU time 4.48 seconds
Started Aug 01 06:25:09 PM PDT 24
Finished Aug 01 06:25:14 PM PDT 24
Peak memory 200460 kb
Host smart-e16a3415-49ab-4cc4-8363-de000791d541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161086838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1161086838
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.886757963
Short name T420
Test name
Test status
Simulation time 106204093 ps
CPU time 0.99 seconds
Started Aug 01 06:25:00 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 200292 kb
Host smart-e8402df7-974a-45bf-89e6-b0c52b731154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886757963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.886757963
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1658919780
Short name T13
Test name
Test status
Simulation time 255290080 ps
CPU time 1.58 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 200272 kb
Host smart-d8fde4b9-ee27-4994-9174-fc559d8f9fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658919780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1658919780
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2161175310
Short name T172
Test name
Test status
Simulation time 13824273474 ps
CPU time 47.44 seconds
Started Aug 01 06:25:20 PM PDT 24
Finished Aug 01 06:26:08 PM PDT 24
Peak memory 200528 kb
Host smart-229a7a3a-6240-4358-98b3-0707dde3167c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161175310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2161175310
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2736492526
Short name T260
Test name
Test status
Simulation time 380667216 ps
CPU time 2.25 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 208432 kb
Host smart-8429e02b-b829-423f-a1d9-c45abebae32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736492526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2736492526
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.354520370
Short name T409
Test name
Test status
Simulation time 64033754 ps
CPU time 0.83 seconds
Started Aug 01 06:25:01 PM PDT 24
Finished Aug 01 06:25:02 PM PDT 24
Peak memory 200284 kb
Host smart-966e5e9c-2906-4b91-ba1c-97a88cd28f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354520370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.354520370
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.4264804419
Short name T383
Test name
Test status
Simulation time 78064482 ps
CPU time 0.81 seconds
Started Aug 01 06:25:16 PM PDT 24
Finished Aug 01 06:25:17 PM PDT 24
Peak memory 200032 kb
Host smart-e627f50a-1527-4664-a2e9-8826b736f0b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264804419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.4264804419
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1666077508
Short name T38
Test name
Test status
Simulation time 2152877103 ps
CPU time 7.6 seconds
Started Aug 01 06:24:56 PM PDT 24
Finished Aug 01 06:25:03 PM PDT 24
Peak memory 217976 kb
Host smart-97542bd1-58b9-4b37-be10-245a186e5452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666077508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1666077508
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2551853587
Short name T333
Test name
Test status
Simulation time 244360158 ps
CPU time 1.05 seconds
Started Aug 01 06:25:12 PM PDT 24
Finished Aug 01 06:25:14 PM PDT 24
Peak memory 217464 kb
Host smart-ee30772a-429b-4bee-b777-4567973cdc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551853587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2551853587
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.584984152
Short name T316
Test name
Test status
Simulation time 95161472 ps
CPU time 0.81 seconds
Started Aug 01 06:25:19 PM PDT 24
Finished Aug 01 06:25:20 PM PDT 24
Peak memory 200020 kb
Host smart-1468a9ac-fa5f-4bd1-bdd0-c453c346caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584984152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.584984152
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2756682715
Short name T5
Test name
Test status
Simulation time 1663046017 ps
CPU time 6.87 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:07 PM PDT 24
Peak memory 200556 kb
Host smart-99dde3f1-831b-4cf1-a3d9-74456e071665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756682715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2756682715
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.769838349
Short name T424
Test name
Test status
Simulation time 177531137 ps
CPU time 1.26 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 200356 kb
Host smart-bc8cb854-5302-4077-8415-1c6c13ce3750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769838349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.769838349
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.651102017
Short name T62
Test name
Test status
Simulation time 199203559 ps
CPU time 1.36 seconds
Started Aug 01 06:25:18 PM PDT 24
Finished Aug 01 06:25:19 PM PDT 24
Peak memory 200404 kb
Host smart-2084cdee-4087-4a07-ba74-6e36c2326665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651102017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.651102017
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3138276178
Short name T404
Test name
Test status
Simulation time 7994382902 ps
CPU time 28.13 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:25:28 PM PDT 24
Peak memory 208732 kb
Host smart-d64c9e76-c225-4ee1-bb68-114c489eeb7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138276178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3138276178
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4060973336
Short name T76
Test name
Test status
Simulation time 503364719 ps
CPU time 2.68 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 200232 kb
Host smart-61ad2fc6-f07c-4f78-95bf-48611f2ffc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060973336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4060973336
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4288226580
Short name T456
Test name
Test status
Simulation time 101490251 ps
CPU time 0.94 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 200284 kb
Host smart-a05619fd-ffe9-448d-bf22-4ff175d09d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288226580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4288226580
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1610579339
Short name T468
Test name
Test status
Simulation time 68650066 ps
CPU time 0.77 seconds
Started Aug 01 06:24:13 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 200088 kb
Host smart-249eb73f-5d78-4949-b88f-3fab4432fa88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610579339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1610579339
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.460295838
Short name T470
Test name
Test status
Simulation time 1894333750 ps
CPU time 6.71 seconds
Started Aug 01 06:24:20 PM PDT 24
Finished Aug 01 06:24:27 PM PDT 24
Peak memory 221592 kb
Host smart-a91683c5-b027-43d0-8292-99ed364c9a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460295838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.460295838
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1336407804
Short name T272
Test name
Test status
Simulation time 244034320 ps
CPU time 1.05 seconds
Started Aug 01 06:24:13 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 217472 kb
Host smart-00f6619c-397b-4b80-a07a-2e150ba9cbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336407804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1336407804
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1718014611
Short name T229
Test name
Test status
Simulation time 138447928 ps
CPU time 0.82 seconds
Started Aug 01 06:24:12 PM PDT 24
Finished Aug 01 06:24:13 PM PDT 24
Peak memory 200084 kb
Host smart-d56edf82-2ede-46a9-99af-64b832eeac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718014611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1718014611
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3950421899
Short name T69
Test name
Test status
Simulation time 8289425085 ps
CPU time 14.68 seconds
Started Aug 01 06:24:14 PM PDT 24
Finished Aug 01 06:24:29 PM PDT 24
Peak memory 217140 kb
Host smart-88f1d378-13ed-46cf-8571-34ce662f6255
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950421899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3950421899
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.74022754
Short name T425
Test name
Test status
Simulation time 103691370 ps
CPU time 1.01 seconds
Started Aug 01 06:24:14 PM PDT 24
Finished Aug 01 06:24:15 PM PDT 24
Peak memory 200268 kb
Host smart-e27eb783-c40b-42d4-b946-caabbeba7f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74022754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.74022754
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1652109694
Short name T193
Test name
Test status
Simulation time 193148507 ps
CPU time 1.43 seconds
Started Aug 01 06:24:12 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 200432 kb
Host smart-59b4173d-dd6a-4005-8151-2d60ba11674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652109694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1652109694
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3848629248
Short name T130
Test name
Test status
Simulation time 4612949342 ps
CPU time 15.72 seconds
Started Aug 01 06:24:14 PM PDT 24
Finished Aug 01 06:24:30 PM PDT 24
Peak memory 200524 kb
Host smart-ed350d0f-c5ca-4b98-b480-2b2466cf7451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848629248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3848629248
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1672322954
Short name T436
Test name
Test status
Simulation time 141860189 ps
CPU time 1.69 seconds
Started Aug 01 06:24:14 PM PDT 24
Finished Aug 01 06:24:16 PM PDT 24
Peak memory 208428 kb
Host smart-cb6690e6-181a-4f17-8f7d-070d861a6e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672322954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1672322954
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.434446784
Short name T252
Test name
Test status
Simulation time 133493871 ps
CPU time 1.02 seconds
Started Aug 01 06:24:14 PM PDT 24
Finished Aug 01 06:24:15 PM PDT 24
Peak memory 200228 kb
Host smart-3285b879-1deb-4bef-ac14-a04bae8cc978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434446784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.434446784
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3720569361
Short name T40
Test name
Test status
Simulation time 73274658 ps
CPU time 0.79 seconds
Started Aug 01 06:25:13 PM PDT 24
Finished Aug 01 06:25:14 PM PDT 24
Peak memory 200092 kb
Host smart-72f67c81-63c4-4116-bae7-b9b0d0629b4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720569361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3720569361
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.493749594
Short name T56
Test name
Test status
Simulation time 1230906763 ps
CPU time 5.6 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:05 PM PDT 24
Peak memory 217384 kb
Host smart-1c367d25-af14-4747-ade8-bea4a92d7d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493749594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.493749594
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2478775971
Short name T344
Test name
Test status
Simulation time 244414308 ps
CPU time 1.06 seconds
Started Aug 01 06:25:07 PM PDT 24
Finished Aug 01 06:25:08 PM PDT 24
Peak memory 217472 kb
Host smart-74089965-4f8d-47ab-ae56-9a47442a967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478775971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2478775971
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.36929450
Short name T379
Test name
Test status
Simulation time 227708141 ps
CPU time 0.96 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:24:58 PM PDT 24
Peak memory 200056 kb
Host smart-05c5274d-0c89-4941-81ed-66ab5d0b2e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36929450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.36929450
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1560670574
Short name T258
Test name
Test status
Simulation time 927326475 ps
CPU time 4.57 seconds
Started Aug 01 06:25:12 PM PDT 24
Finished Aug 01 06:25:17 PM PDT 24
Peak memory 200504 kb
Host smart-bd015b36-6906-4e83-ad34-28cbde59f4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560670574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1560670574
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2607381044
Short name T169
Test name
Test status
Simulation time 106439740 ps
CPU time 0.96 seconds
Started Aug 01 06:25:16 PM PDT 24
Finished Aug 01 06:25:22 PM PDT 24
Peak memory 200292 kb
Host smart-0f8d97f6-63c1-4952-b8e1-e75f274f2453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607381044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2607381044
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1253330068
Short name T380
Test name
Test status
Simulation time 199401797 ps
CPU time 1.34 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:01 PM PDT 24
Peak memory 200408 kb
Host smart-b8da9b23-0fd6-4506-b1b5-e401f2c8cbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253330068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1253330068
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2646295080
Short name T500
Test name
Test status
Simulation time 7982639320 ps
CPU time 26.06 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:25 PM PDT 24
Peak memory 200548 kb
Host smart-d0742789-6d30-4e7e-a1c8-692ec3c87f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646295080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2646295080
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2604417526
Short name T7
Test name
Test status
Simulation time 138708262 ps
CPU time 1.79 seconds
Started Aug 01 06:25:04 PM PDT 24
Finished Aug 01 06:25:06 PM PDT 24
Peak memory 200240 kb
Host smart-aa490461-824c-452c-bdc0-8dd1b7509abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604417526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2604417526
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.4156486842
Short name T155
Test name
Test status
Simulation time 131239509 ps
CPU time 1.05 seconds
Started Aug 01 06:25:11 PM PDT 24
Finished Aug 01 06:25:13 PM PDT 24
Peak memory 200292 kb
Host smart-aa2b05de-b9b6-4e31-a875-19308d5944f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156486842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4156486842
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1494896900
Short name T363
Test name
Test status
Simulation time 73862637 ps
CPU time 0.77 seconds
Started Aug 01 06:25:16 PM PDT 24
Finished Aug 01 06:25:17 PM PDT 24
Peak memory 200108 kb
Host smart-75f91987-abd3-4ef9-9349-29d840f493d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494896900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1494896900
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3798360359
Short name T264
Test name
Test status
Simulation time 1219837967 ps
CPU time 5.74 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:25:03 PM PDT 24
Peak memory 216788 kb
Host smart-ea885710-7e23-440b-8bcf-853d7931b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798360359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3798360359
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.109408167
Short name T146
Test name
Test status
Simulation time 244410033 ps
CPU time 1.02 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 217440 kb
Host smart-9366a3d6-5431-4a82-af37-1966b20363a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109408167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.109408167
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2681713487
Short name T460
Test name
Test status
Simulation time 184576054 ps
CPU time 0.87 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 199816 kb
Host smart-c2838742-7ecf-4ea2-ba20-15972d4e7ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681713487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2681713487
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1265026900
Short name T189
Test name
Test status
Simulation time 1575672380 ps
CPU time 6.13 seconds
Started Aug 01 06:24:59 PM PDT 24
Finished Aug 01 06:25:05 PM PDT 24
Peak memory 200488 kb
Host smart-e725c019-19d2-41c8-af24-831dc974c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265026900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1265026900
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2181898892
Short name T201
Test name
Test status
Simulation time 113397676 ps
CPU time 1.06 seconds
Started Aug 01 06:25:10 PM PDT 24
Finished Aug 01 06:25:11 PM PDT 24
Peak memory 200276 kb
Host smart-70196b0e-fff4-447f-91be-9f5acc5023af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181898892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2181898892
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3693722207
Short name T507
Test name
Test status
Simulation time 120898152 ps
CPU time 1.23 seconds
Started Aug 01 06:25:13 PM PDT 24
Finished Aug 01 06:25:14 PM PDT 24
Peak memory 200420 kb
Host smart-379644a1-3d29-42ca-8579-0a9bd2a8c0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693722207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3693722207
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1229702532
Short name T350
Test name
Test status
Simulation time 9878186067 ps
CPU time 33.6 seconds
Started Aug 01 06:25:01 PM PDT 24
Finished Aug 01 06:25:35 PM PDT 24
Peak memory 208736 kb
Host smart-9b94faaa-ce12-46c2-8f70-394669c8b6e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229702532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1229702532
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2274677919
Short name T369
Test name
Test status
Simulation time 395496406 ps
CPU time 2.02 seconds
Started Aug 01 06:25:18 PM PDT 24
Finished Aug 01 06:25:21 PM PDT 24
Peak memory 200244 kb
Host smart-a6930dd9-c4e8-40af-9d40-2cf1588827fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274677919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2274677919
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.881216997
Short name T242
Test name
Test status
Simulation time 74124501 ps
CPU time 0.78 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 200276 kb
Host smart-deb2a408-6e10-4fd6-ad1b-63e3a9e8d1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881216997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.881216997
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1834621289
Short name T483
Test name
Test status
Simulation time 72945354 ps
CPU time 0.8 seconds
Started Aug 01 06:25:18 PM PDT 24
Finished Aug 01 06:25:19 PM PDT 24
Peak memory 200112 kb
Host smart-10add0a7-d9b8-4c60-96d7-f65c8f283b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834621289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1834621289
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.801040291
Short name T317
Test name
Test status
Simulation time 1888620257 ps
CPU time 7.65 seconds
Started Aug 01 06:25:02 PM PDT 24
Finished Aug 01 06:25:10 PM PDT 24
Peak memory 217596 kb
Host smart-ca1165c2-713b-4b70-8989-f387baeb2cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801040291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.801040291
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1969770153
Short name T266
Test name
Test status
Simulation time 244829869 ps
CPU time 1.18 seconds
Started Aug 01 06:25:09 PM PDT 24
Finished Aug 01 06:25:11 PM PDT 24
Peak memory 217436 kb
Host smart-a73df8bd-b603-4eac-8628-afe10f017bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969770153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1969770153
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1858626552
Short name T208
Test name
Test status
Simulation time 83855128 ps
CPU time 0.74 seconds
Started Aug 01 06:25:08 PM PDT 24
Finished Aug 01 06:25:09 PM PDT 24
Peak memory 200096 kb
Host smart-a4823606-6fae-4062-b0d7-ed1703941233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858626552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1858626552
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3998964957
Short name T128
Test name
Test status
Simulation time 1886703131 ps
CPU time 7.15 seconds
Started Aug 01 06:24:57 PM PDT 24
Finished Aug 01 06:25:04 PM PDT 24
Peak memory 200432 kb
Host smart-061c89b3-9c77-4348-840a-b536a0f5441d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998964957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3998964957
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1410601976
Short name T174
Test name
Test status
Simulation time 97746920 ps
CPU time 1.01 seconds
Started Aug 01 06:24:58 PM PDT 24
Finished Aug 01 06:25:00 PM PDT 24
Peak memory 200272 kb
Host smart-d7e35b4a-442e-4c59-b149-42303423a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410601976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1410601976
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1140423172
Short name T270
Test name
Test status
Simulation time 114857839 ps
CPU time 1.19 seconds
Started Aug 01 06:25:17 PM PDT 24
Finished Aug 01 06:25:18 PM PDT 24
Peak memory 200436 kb
Host smart-1e180ba4-0e38-4929-8a34-4554c757c3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140423172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1140423172
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2932393844
Short name T178
Test name
Test status
Simulation time 4371488827 ps
CPU time 19.51 seconds
Started Aug 01 06:25:10 PM PDT 24
Finished Aug 01 06:25:30 PM PDT 24
Peak memory 200832 kb
Host smart-35112eb8-9561-414c-b27a-a33a7c5d708f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932393844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2932393844
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1512378689
Short name T232
Test name
Test status
Simulation time 370653823 ps
CPU time 2.46 seconds
Started Aug 01 06:25:01 PM PDT 24
Finished Aug 01 06:25:04 PM PDT 24
Peak memory 200172 kb
Host smart-84c22b97-3fc4-4e1c-8c98-f8720bc5b85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512378689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1512378689
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1648841387
Short name T289
Test name
Test status
Simulation time 121155770 ps
CPU time 1.1 seconds
Started Aug 01 06:25:12 PM PDT 24
Finished Aug 01 06:25:13 PM PDT 24
Peak memory 200224 kb
Host smart-72e4f300-4e3d-455a-bea4-2793f86af253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648841387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1648841387
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2096085558
Short name T292
Test name
Test status
Simulation time 70064614 ps
CPU time 0.76 seconds
Started Aug 01 06:25:22 PM PDT 24
Finished Aug 01 06:25:23 PM PDT 24
Peak memory 200092 kb
Host smart-03a00243-f8c8-48fa-9687-2d892e0f9c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096085558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2096085558
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.468700453
Short name T446
Test name
Test status
Simulation time 1892590152 ps
CPU time 7.24 seconds
Started Aug 01 06:25:17 PM PDT 24
Finished Aug 01 06:25:25 PM PDT 24
Peak memory 217464 kb
Host smart-ccf44c42-a859-4b23-8368-10e1507238c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468700453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.468700453
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1349885316
Short name T386
Test name
Test status
Simulation time 268621596 ps
CPU time 1.09 seconds
Started Aug 01 06:25:22 PM PDT 24
Finished Aug 01 06:25:23 PM PDT 24
Peak memory 217440 kb
Host smart-51cbe29c-b6ae-4bb8-8183-47dd32f859dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349885316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1349885316
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.400143272
Short name T364
Test name
Test status
Simulation time 133733580 ps
CPU time 0.79 seconds
Started Aug 01 06:25:12 PM PDT 24
Finished Aug 01 06:25:13 PM PDT 24
Peak memory 200072 kb
Host smart-a69394ad-9d3c-478e-8ab3-3301d8e560ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400143272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.400143272
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.4186206647
Short name T535
Test name
Test status
Simulation time 1169079496 ps
CPU time 5.39 seconds
Started Aug 01 06:25:20 PM PDT 24
Finished Aug 01 06:25:26 PM PDT 24
Peak memory 200540 kb
Host smart-38baf15d-4a40-4e53-9623-7db889215207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186206647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.4186206647
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1963168846
Short name T533
Test name
Test status
Simulation time 99772656 ps
CPU time 0.98 seconds
Started Aug 01 06:25:19 PM PDT 24
Finished Aug 01 06:25:21 PM PDT 24
Peak memory 200256 kb
Host smart-cb57ebea-1cac-4a0a-9342-3bbc8fa579e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963168846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1963168846
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.898990020
Short name T506
Test name
Test status
Simulation time 250330180 ps
CPU time 1.49 seconds
Started Aug 01 06:25:17 PM PDT 24
Finished Aug 01 06:25:19 PM PDT 24
Peak memory 200484 kb
Host smart-9746893f-c7b6-44f7-a60c-806b619dc73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898990020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.898990020
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.920622112
Short name T188
Test name
Test status
Simulation time 1140079523 ps
CPU time 5.3 seconds
Started Aug 01 06:25:13 PM PDT 24
Finished Aug 01 06:25:18 PM PDT 24
Peak memory 200728 kb
Host smart-0b752e95-1b6d-432b-a5eb-c4b6036831ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920622112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.920622112
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4027105724
Short name T310
Test name
Test status
Simulation time 495329504 ps
CPU time 2.88 seconds
Started Aug 01 06:25:14 PM PDT 24
Finished Aug 01 06:25:17 PM PDT 24
Peak memory 200348 kb
Host smart-820e90a0-9696-411f-9843-d4a8d39b927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027105724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4027105724
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3237351217
Short name T445
Test name
Test status
Simulation time 66121835 ps
CPU time 0.83 seconds
Started Aug 01 06:25:23 PM PDT 24
Finished Aug 01 06:25:24 PM PDT 24
Peak memory 200316 kb
Host smart-924d4f62-61f9-4817-9ad1-8b4f24fd0c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237351217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3237351217
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1626721577
Short name T238
Test name
Test status
Simulation time 79859043 ps
CPU time 0.79 seconds
Started Aug 01 06:25:28 PM PDT 24
Finished Aug 01 06:25:29 PM PDT 24
Peak memory 200116 kb
Host smart-8bf09c78-659d-47c0-beb1-456836841367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626721577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1626721577
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.304494076
Short name T28
Test name
Test status
Simulation time 1901507594 ps
CPU time 6.66 seconds
Started Aug 01 06:25:20 PM PDT 24
Finished Aug 01 06:25:27 PM PDT 24
Peak memory 217328 kb
Host smart-0b96f47b-dd41-4459-aadb-9720c385895e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304494076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.304494076
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1700205522
Short name T393
Test name
Test status
Simulation time 245697772 ps
CPU time 1.05 seconds
Started Aug 01 06:25:14 PM PDT 24
Finished Aug 01 06:25:16 PM PDT 24
Peak memory 217404 kb
Host smart-4dbb0095-7bfb-4290-8afa-fd1fd873c5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700205522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1700205522
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3241258312
Short name T309
Test name
Test status
Simulation time 202000581 ps
CPU time 0.96 seconds
Started Aug 01 06:25:08 PM PDT 24
Finished Aug 01 06:25:09 PM PDT 24
Peak memory 200148 kb
Host smart-d264c45f-6db4-463d-83e9-1836963fb4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241258312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3241258312
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2435810011
Short name T373
Test name
Test status
Simulation time 1690117864 ps
CPU time 6.2 seconds
Started Aug 01 06:25:19 PM PDT 24
Finished Aug 01 06:25:25 PM PDT 24
Peak memory 200488 kb
Host smart-1b0986df-0f61-4182-aa2e-70b05df8c138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435810011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2435810011
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2749930451
Short name T366
Test name
Test status
Simulation time 148541638 ps
CPU time 1.09 seconds
Started Aug 01 06:25:22 PM PDT 24
Finished Aug 01 06:25:24 PM PDT 24
Peak memory 200324 kb
Host smart-db4b1856-94c7-49b0-abb9-8a23686eb36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749930451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2749930451
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1447905488
Short name T297
Test name
Test status
Simulation time 244125755 ps
CPU time 1.52 seconds
Started Aug 01 06:25:04 PM PDT 24
Finished Aug 01 06:25:06 PM PDT 24
Peak memory 200392 kb
Host smart-a8179e80-bbbb-4615-a5b7-19b7026aa869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447905488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1447905488
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2640819597
Short name T170
Test name
Test status
Simulation time 6091880642 ps
CPU time 25.27 seconds
Started Aug 01 06:25:07 PM PDT 24
Finished Aug 01 06:25:33 PM PDT 24
Peak memory 200496 kb
Host smart-9e63c19f-e3f5-4566-ab1c-037bb2fefb1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640819597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2640819597
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1004242658
Short name T347
Test name
Test status
Simulation time 384909404 ps
CPU time 2.17 seconds
Started Aug 01 06:25:20 PM PDT 24
Finished Aug 01 06:25:23 PM PDT 24
Peak memory 200248 kb
Host smart-47f74ded-3b5c-4020-af05-462cba8939a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004242658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1004242658
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.608531491
Short name T263
Test name
Test status
Simulation time 241332070 ps
CPU time 1.53 seconds
Started Aug 01 06:25:09 PM PDT 24
Finished Aug 01 06:25:11 PM PDT 24
Peak memory 200436 kb
Host smart-7c79cb25-6b32-4dd7-b21e-bc29abeac471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608531491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.608531491
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3775449412
Short name T348
Test name
Test status
Simulation time 61032057 ps
CPU time 0.75 seconds
Started Aug 01 06:25:19 PM PDT 24
Finished Aug 01 06:25:20 PM PDT 24
Peak memory 200096 kb
Host smart-1bfadd2d-8eef-4714-b202-d7fd4e0a26e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775449412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3775449412
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2280352255
Short name T390
Test name
Test status
Simulation time 1225121174 ps
CPU time 5.68 seconds
Started Aug 01 06:25:18 PM PDT 24
Finished Aug 01 06:25:24 PM PDT 24
Peak memory 221660 kb
Host smart-5ab3b097-ee27-4a35-b2c1-63c9521fc076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280352255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2280352255
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2166342397
Short name T520
Test name
Test status
Simulation time 245527608 ps
CPU time 1.02 seconds
Started Aug 01 06:25:15 PM PDT 24
Finished Aug 01 06:25:17 PM PDT 24
Peak memory 217664 kb
Host smart-3e73738f-1b0c-4e53-8626-c9225475c142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166342397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2166342397
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3951642140
Short name T17
Test name
Test status
Simulation time 159274070 ps
CPU time 0.9 seconds
Started Aug 01 06:25:18 PM PDT 24
Finished Aug 01 06:25:20 PM PDT 24
Peak memory 200080 kb
Host smart-c2cce76b-acbb-49df-b3b6-7aff40002353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951642140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3951642140
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.4089092841
Short name T205
Test name
Test status
Simulation time 1505335190 ps
CPU time 6.32 seconds
Started Aug 01 06:25:04 PM PDT 24
Finished Aug 01 06:25:11 PM PDT 24
Peak memory 200532 kb
Host smart-f4caa43b-4da1-4de6-bba7-0864c8862e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089092841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.4089092841
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2669930000
Short name T225
Test name
Test status
Simulation time 174529149 ps
CPU time 1.17 seconds
Started Aug 01 06:25:19 PM PDT 24
Finished Aug 01 06:25:21 PM PDT 24
Peak memory 200324 kb
Host smart-0e0cf38c-65d8-4449-8489-11271d65e99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669930000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2669930000
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1327064390
Short name T134
Test name
Test status
Simulation time 254203397 ps
CPU time 1.51 seconds
Started Aug 01 06:25:20 PM PDT 24
Finished Aug 01 06:25:22 PM PDT 24
Peak memory 200420 kb
Host smart-add848e5-dab8-4364-b353-1f30da4bd65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327064390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1327064390
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.237611202
Short name T496
Test name
Test status
Simulation time 8248888212 ps
CPU time 28.1 seconds
Started Aug 01 06:25:20 PM PDT 24
Finished Aug 01 06:25:48 PM PDT 24
Peak memory 200600 kb
Host smart-6b5a5585-4288-4871-b6a6-23b128ddb319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237611202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.237611202
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1245567611
Short name T475
Test name
Test status
Simulation time 126023753 ps
CPU time 1.52 seconds
Started Aug 01 06:25:08 PM PDT 24
Finished Aug 01 06:25:10 PM PDT 24
Peak memory 208448 kb
Host smart-822a1772-301c-4b74-a2a5-80a206971dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245567611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1245567611
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3402610791
Short name T529
Test name
Test status
Simulation time 100070753 ps
CPU time 0.94 seconds
Started Aug 01 06:25:20 PM PDT 24
Finished Aug 01 06:25:21 PM PDT 24
Peak memory 200280 kb
Host smart-623727bc-fcfc-480e-91e4-62762102ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402610791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3402610791
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2077529479
Short name T391
Test name
Test status
Simulation time 70440577 ps
CPU time 0.75 seconds
Started Aug 01 06:25:22 PM PDT 24
Finished Aug 01 06:25:23 PM PDT 24
Peak memory 200124 kb
Host smart-1e875e8c-889e-4ca5-9772-6cafb96d0a02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077529479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2077529479
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1727193828
Short name T35
Test name
Test status
Simulation time 1223715960 ps
CPU time 5.37 seconds
Started Aug 01 06:25:13 PM PDT 24
Finished Aug 01 06:25:19 PM PDT 24
Peak memory 217624 kb
Host smart-fc3a6d6e-9eb3-42cd-bf36-ea1ba1f4f9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727193828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1727193828
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.415016284
Short name T215
Test name
Test status
Simulation time 244774657 ps
CPU time 1.07 seconds
Started Aug 01 06:25:07 PM PDT 24
Finished Aug 01 06:25:08 PM PDT 24
Peak memory 217436 kb
Host smart-4e6dfaee-4231-4ef6-bdc9-9a30f74e47ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415016284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.415016284
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3055741649
Short name T222
Test name
Test status
Simulation time 85234809 ps
CPU time 0.72 seconds
Started Aug 01 06:25:11 PM PDT 24
Finished Aug 01 06:25:12 PM PDT 24
Peak memory 200084 kb
Host smart-222c13da-5997-4583-aeec-871a630807a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055741649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3055741649
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1423987803
Short name T300
Test name
Test status
Simulation time 1718961247 ps
CPU time 6.69 seconds
Started Aug 01 06:25:08 PM PDT 24
Finished Aug 01 06:25:15 PM PDT 24
Peak memory 200540 kb
Host smart-4515289e-d97e-4ab3-9d2e-6c40687e924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423987803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1423987803
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1882846701
Short name T143
Test name
Test status
Simulation time 101907251 ps
CPU time 1.03 seconds
Started Aug 01 06:25:18 PM PDT 24
Finished Aug 01 06:25:20 PM PDT 24
Peak memory 200296 kb
Host smart-b32a4a64-bb78-470d-b5ea-c1478007b4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882846701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1882846701
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2135385521
Short name T406
Test name
Test status
Simulation time 198537168 ps
CPU time 1.38 seconds
Started Aug 01 06:25:22 PM PDT 24
Finished Aug 01 06:25:23 PM PDT 24
Peak memory 200400 kb
Host smart-6d138a58-5736-466b-a5fa-1cb9f11fceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135385521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2135385521
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1595807719
Short name T104
Test name
Test status
Simulation time 5399374351 ps
CPU time 24.83 seconds
Started Aug 01 06:25:07 PM PDT 24
Finished Aug 01 06:25:32 PM PDT 24
Peak memory 208780 kb
Host smart-ad7bd1f0-f475-4b04-9b5c-fb0d9a3d6db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595807719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1595807719
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3928426301
Short name T91
Test name
Test status
Simulation time 132409360 ps
CPU time 1.77 seconds
Started Aug 01 06:25:16 PM PDT 24
Finished Aug 01 06:25:18 PM PDT 24
Peak memory 200272 kb
Host smart-1a5856a4-eccd-4734-a83d-ee8de6f1030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928426301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3928426301
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.686401083
Short name T410
Test name
Test status
Simulation time 161284322 ps
CPU time 1.4 seconds
Started Aug 01 06:25:16 PM PDT 24
Finished Aug 01 06:25:18 PM PDT 24
Peak memory 200660 kb
Host smart-29d098eb-0daf-4fec-835e-a79ed3f3fd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686401083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.686401083
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2388349397
Short name T265
Test name
Test status
Simulation time 67863485 ps
CPU time 0.78 seconds
Started Aug 01 06:25:19 PM PDT 24
Finished Aug 01 06:25:20 PM PDT 24
Peak memory 200112 kb
Host smart-95a14852-54c8-4886-b1a0-563634ed0c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388349397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2388349397
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2331817047
Short name T77
Test name
Test status
Simulation time 247577728 ps
CPU time 1.06 seconds
Started Aug 01 06:25:12 PM PDT 24
Finished Aug 01 06:25:13 PM PDT 24
Peak memory 217464 kb
Host smart-86d12538-1f32-462e-8df4-91a87329cf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331817047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2331817047
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3058914567
Short name T219
Test name
Test status
Simulation time 143283892 ps
CPU time 0.83 seconds
Started Aug 01 06:25:07 PM PDT 24
Finished Aug 01 06:25:08 PM PDT 24
Peak memory 200068 kb
Host smart-3bad0217-c198-46ce-a505-a944ab024405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058914567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3058914567
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.405363788
Short name T408
Test name
Test status
Simulation time 822088872 ps
CPU time 4.07 seconds
Started Aug 01 06:25:05 PM PDT 24
Finished Aug 01 06:25:10 PM PDT 24
Peak memory 200548 kb
Host smart-115e0dbc-5707-4315-86c0-5040034df151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405363788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.405363788
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.804590278
Short name T203
Test name
Test status
Simulation time 106110223 ps
CPU time 0.99 seconds
Started Aug 01 06:25:28 PM PDT 24
Finished Aug 01 06:25:29 PM PDT 24
Peak memory 200308 kb
Host smart-373bffc9-13ae-44b2-a0d7-1f0ceb74b3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804590278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.804590278
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.970048369
Short name T168
Test name
Test status
Simulation time 193743983 ps
CPU time 1.37 seconds
Started Aug 01 06:25:09 PM PDT 24
Finished Aug 01 06:25:11 PM PDT 24
Peak memory 200440 kb
Host smart-373e85a7-df24-46c3-b307-abe2cae08864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970048369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.970048369
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.780251074
Short name T471
Test name
Test status
Simulation time 208124805 ps
CPU time 1.19 seconds
Started Aug 01 06:25:27 PM PDT 24
Finished Aug 01 06:25:28 PM PDT 24
Peak memory 200304 kb
Host smart-ad98d69d-f35e-43ea-8125-4c7f8cf2e9f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780251074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.780251074
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3865066770
Short name T85
Test name
Test status
Simulation time 121069396 ps
CPU time 1.6 seconds
Started Aug 01 06:25:29 PM PDT 24
Finished Aug 01 06:25:30 PM PDT 24
Peak memory 208460 kb
Host smart-92399901-c4bc-4397-91be-b7453f5672ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865066770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3865066770
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3487337515
Short name T267
Test name
Test status
Simulation time 250778820 ps
CPU time 1.42 seconds
Started Aug 01 06:25:21 PM PDT 24
Finished Aug 01 06:25:23 PM PDT 24
Peak memory 200316 kb
Host smart-b95f962d-73ba-443d-94b3-f5b62ddf5478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487337515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3487337515
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.199656088
Short name T198
Test name
Test status
Simulation time 71063130 ps
CPU time 0.78 seconds
Started Aug 01 06:25:24 PM PDT 24
Finished Aug 01 06:25:25 PM PDT 24
Peak memory 200048 kb
Host smart-42b73f11-7170-4a4d-839e-9f24a9748de2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199656088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.199656088
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2626695164
Short name T251
Test name
Test status
Simulation time 1224879255 ps
CPU time 5.33 seconds
Started Aug 01 06:25:18 PM PDT 24
Finished Aug 01 06:25:23 PM PDT 24
Peak memory 217688 kb
Host smart-744e42cb-b5bc-460d-a549-955be5578cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626695164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2626695164
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2831377075
Short name T509
Test name
Test status
Simulation time 244023132 ps
CPU time 1.12 seconds
Started Aug 01 06:25:27 PM PDT 24
Finished Aug 01 06:25:29 PM PDT 24
Peak memory 217372 kb
Host smart-1b67bba0-3026-4e41-8e03-2e4d66643149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831377075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2831377075
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1889875777
Short name T361
Test name
Test status
Simulation time 112697481 ps
CPU time 0.77 seconds
Started Aug 01 06:25:19 PM PDT 24
Finished Aug 01 06:25:20 PM PDT 24
Peak memory 200100 kb
Host smart-66e0ee46-0ee2-46bd-9157-858db99518a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889875777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1889875777
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3664656102
Short name T127
Test name
Test status
Simulation time 1677492573 ps
CPU time 6.44 seconds
Started Aug 01 06:25:20 PM PDT 24
Finished Aug 01 06:25:26 PM PDT 24
Peak memory 200504 kb
Host smart-85d6f825-4e30-4fb8-9de3-e0d5882a9609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664656102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3664656102
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2241410662
Short name T285
Test name
Test status
Simulation time 100775521 ps
CPU time 0.94 seconds
Started Aug 01 06:25:27 PM PDT 24
Finished Aug 01 06:25:28 PM PDT 24
Peak memory 200308 kb
Host smart-981c1c02-de47-45f9-ac83-8d242d64a01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241410662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2241410662
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2784277093
Short name T153
Test name
Test status
Simulation time 202375486 ps
CPU time 1.36 seconds
Started Aug 01 06:25:22 PM PDT 24
Finished Aug 01 06:25:24 PM PDT 24
Peak memory 200456 kb
Host smart-cc255491-e10a-4893-b764-4aae42f5840a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784277093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2784277093
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.143195742
Short name T536
Test name
Test status
Simulation time 7671175644 ps
CPU time 28.74 seconds
Started Aug 01 06:25:22 PM PDT 24
Finished Aug 01 06:25:51 PM PDT 24
Peak memory 200608 kb
Host smart-ddd61860-9048-48a0-b4c0-0e50c462966f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143195742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.143195742
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3561602082
Short name T294
Test name
Test status
Simulation time 124318450 ps
CPU time 1.39 seconds
Started Aug 01 06:25:20 PM PDT 24
Finished Aug 01 06:25:22 PM PDT 24
Peak memory 200240 kb
Host smart-ec9bca72-4175-4434-bfbe-f781301a55dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561602082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3561602082
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1979907502
Short name T82
Test name
Test status
Simulation time 210485384 ps
CPU time 1.24 seconds
Started Aug 01 06:25:28 PM PDT 24
Finished Aug 01 06:25:29 PM PDT 24
Peak memory 200304 kb
Host smart-26a53806-3fc0-4855-bd77-f224b0cea77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979907502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1979907502
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3113563073
Short name T401
Test name
Test status
Simulation time 55623572 ps
CPU time 0.72 seconds
Started Aug 01 06:25:22 PM PDT 24
Finished Aug 01 06:25:23 PM PDT 24
Peak memory 200104 kb
Host smart-4587a594-1f79-4c64-8af9-b10c59964577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113563073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3113563073
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3574981720
Short name T472
Test name
Test status
Simulation time 1237215905 ps
CPU time 5.61 seconds
Started Aug 01 06:25:24 PM PDT 24
Finished Aug 01 06:25:29 PM PDT 24
Peak memory 217688 kb
Host smart-cd7c46c3-0fc4-4f97-b8c0-3fb0c71ebf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574981720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3574981720
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.703684784
Short name T464
Test name
Test status
Simulation time 244235055 ps
CPU time 1.08 seconds
Started Aug 01 06:26:00 PM PDT 24
Finished Aug 01 06:26:01 PM PDT 24
Peak memory 217440 kb
Host smart-27818b98-a2a9-4d9b-a8bc-b1197f118d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703684784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.703684784
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2746755560
Short name T539
Test name
Test status
Simulation time 130110843 ps
CPU time 0.84 seconds
Started Aug 01 06:25:25 PM PDT 24
Finished Aug 01 06:25:26 PM PDT 24
Peak memory 200032 kb
Host smart-ea4ece3e-f28a-4e1b-b70b-6f139049887a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746755560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2746755560
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1833457322
Short name T484
Test name
Test status
Simulation time 775544344 ps
CPU time 4.13 seconds
Started Aug 01 06:25:26 PM PDT 24
Finished Aug 01 06:25:31 PM PDT 24
Peak memory 200432 kb
Host smart-901615df-77aa-4188-868e-76bd0ae72b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833457322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1833457322
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3591699624
Short name T281
Test name
Test status
Simulation time 144359003 ps
CPU time 1.06 seconds
Started Aug 01 06:25:21 PM PDT 24
Finished Aug 01 06:25:23 PM PDT 24
Peak memory 200296 kb
Host smart-bc1b6264-94f5-4981-89ca-fad2ea94f053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591699624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3591699624
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1348783602
Short name T79
Test name
Test status
Simulation time 118863120 ps
CPU time 1.18 seconds
Started Aug 01 06:25:31 PM PDT 24
Finished Aug 01 06:25:32 PM PDT 24
Peak memory 200368 kb
Host smart-21e44ade-57b9-40a4-b5d6-29de57b31d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348783602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1348783602
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1197544434
Short name T106
Test name
Test status
Simulation time 4807278690 ps
CPU time 22 seconds
Started Aug 01 06:25:19 PM PDT 24
Finished Aug 01 06:25:42 PM PDT 24
Peak memory 200596 kb
Host smart-ce9123e9-7103-4fdc-a0b7-f5f9129fd567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197544434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1197544434
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3469712561
Short name T518
Test name
Test status
Simulation time 528236349 ps
CPU time 2.62 seconds
Started Aug 01 06:25:23 PM PDT 24
Finished Aug 01 06:25:26 PM PDT 24
Peak memory 200184 kb
Host smart-f440a2f2-bf80-4b1d-a05a-30bc98f121f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469712561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3469712561
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1556825719
Short name T457
Test name
Test status
Simulation time 268034104 ps
CPU time 1.37 seconds
Started Aug 01 06:25:12 PM PDT 24
Finished Aug 01 06:25:13 PM PDT 24
Peak memory 200296 kb
Host smart-93e90b50-58e6-4ea0-8d84-86766a9dba5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556825719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1556825719
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3236065013
Short name T517
Test name
Test status
Simulation time 74783684 ps
CPU time 0.79 seconds
Started Aug 01 06:24:21 PM PDT 24
Finished Aug 01 06:24:22 PM PDT 24
Peak memory 200112 kb
Host smart-4c1d52d5-4536-49f5-b64e-59abe1064c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236065013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3236065013
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1063461414
Short name T462
Test name
Test status
Simulation time 1228464866 ps
CPU time 6.08 seconds
Started Aug 01 06:24:21 PM PDT 24
Finished Aug 01 06:24:27 PM PDT 24
Peak memory 217340 kb
Host smart-a4ee4085-334d-49ea-b613-5ca2781ab6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063461414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1063461414
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.4189859582
Short name T326
Test name
Test status
Simulation time 244232453 ps
CPU time 1.08 seconds
Started Aug 01 06:24:29 PM PDT 24
Finished Aug 01 06:24:31 PM PDT 24
Peak memory 217536 kb
Host smart-08d9f675-a134-46c1-b99e-ce76de7726a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189859582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.4189859582
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.186570450
Short name T481
Test name
Test status
Simulation time 108237518 ps
CPU time 0.76 seconds
Started Aug 01 06:24:19 PM PDT 24
Finished Aug 01 06:24:20 PM PDT 24
Peak memory 200032 kb
Host smart-d8551bab-384c-4594-beca-e7b6c1eab1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186570450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.186570450
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2704111370
Short name T129
Test name
Test status
Simulation time 1484839479 ps
CPU time 5.91 seconds
Started Aug 01 06:24:23 PM PDT 24
Finished Aug 01 06:24:29 PM PDT 24
Peak memory 200536 kb
Host smart-68b8588b-741c-4c12-8124-912f0c963339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704111370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2704111370
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2926250545
Short name T381
Test name
Test status
Simulation time 108037688 ps
CPU time 1.02 seconds
Started Aug 01 06:24:16 PM PDT 24
Finished Aug 01 06:24:18 PM PDT 24
Peak memory 200296 kb
Host smart-115afee4-6c60-4638-81da-8c30adba109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926250545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2926250545
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.4269459666
Short name T187
Test name
Test status
Simulation time 112246521 ps
CPU time 1.15 seconds
Started Aug 01 06:24:27 PM PDT 24
Finished Aug 01 06:24:28 PM PDT 24
Peak memory 200400 kb
Host smart-3998d4f9-2025-4351-9980-6df2ad2d6203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269459666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.4269459666
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3173161126
Short name T444
Test name
Test status
Simulation time 6768204715 ps
CPU time 32.51 seconds
Started Aug 01 06:24:16 PM PDT 24
Finished Aug 01 06:24:48 PM PDT 24
Peak memory 200568 kb
Host smart-4446c61b-999d-45ad-880b-72c0f151fa4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173161126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3173161126
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1205453654
Short name T524
Test name
Test status
Simulation time 444501844 ps
CPU time 2.71 seconds
Started Aug 01 06:24:16 PM PDT 24
Finished Aug 01 06:24:19 PM PDT 24
Peak memory 200248 kb
Host smart-a359fda2-fb30-43a2-9068-79662c9be288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205453654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1205453654
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2288868675
Short name T338
Test name
Test status
Simulation time 172537133 ps
CPU time 1.1 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:32 PM PDT 24
Peak memory 200328 kb
Host smart-c2dce2cf-c46c-4b20-9c1d-e09965568946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288868675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2288868675
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3928868077
Short name T2
Test name
Test status
Simulation time 53568078 ps
CPU time 0.7 seconds
Started Aug 01 06:24:06 PM PDT 24
Finished Aug 01 06:24:07 PM PDT 24
Peak memory 200108 kb
Host smart-247291e9-f463-4c16-8360-d3aeac2775bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928868077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3928868077
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.301426124
Short name T395
Test name
Test status
Simulation time 1897166966 ps
CPU time 7.27 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 217708 kb
Host smart-6b225f9c-2fc8-4409-9e49-62d171181a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301426124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.301426124
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1745016770
Short name T491
Test name
Test status
Simulation time 244489027 ps
CPU time 1.04 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:09 PM PDT 24
Peak memory 217448 kb
Host smart-9dbd4de2-79b2-468a-9f04-17481919b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745016770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1745016770
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.537783399
Short name T493
Test name
Test status
Simulation time 158914000 ps
CPU time 0.86 seconds
Started Aug 01 06:24:24 PM PDT 24
Finished Aug 01 06:24:25 PM PDT 24
Peak memory 200084 kb
Host smart-ff5abeff-52b6-4625-956a-270fee149429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537783399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.537783399
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1293041719
Short name T479
Test name
Test status
Simulation time 1602416942 ps
CPU time 6.39 seconds
Started Aug 01 06:24:31 PM PDT 24
Finished Aug 01 06:24:38 PM PDT 24
Peak memory 200492 kb
Host smart-06919207-7b0d-4861-a3ef-1c3e0ad5aaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293041719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1293041719
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1304854070
Short name T438
Test name
Test status
Simulation time 153775544 ps
CPU time 1.13 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:08 PM PDT 24
Peak memory 200264 kb
Host smart-b3b18a41-48cf-4843-a004-3b82ac7ed2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304854070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1304854070
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.630746414
Short name T502
Test name
Test status
Simulation time 236865888 ps
CPU time 1.37 seconds
Started Aug 01 06:24:22 PM PDT 24
Finished Aug 01 06:24:24 PM PDT 24
Peak memory 200428 kb
Host smart-37aceada-9423-4b21-bbf1-f221c424f317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630746414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.630746414
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3701689725
Short name T515
Test name
Test status
Simulation time 3235899006 ps
CPU time 11.48 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:16 PM PDT 24
Peak memory 200616 kb
Host smart-920a3c34-a432-4d42-bc29-2700bb8215c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701689725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3701689725
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.246885410
Short name T544
Test name
Test status
Simulation time 384197687 ps
CPU time 2.63 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200168 kb
Host smart-86c62cb9-da22-4462-9679-31a29abd9137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246885410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.246885410
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3370943751
Short name T173
Test name
Test status
Simulation time 114953876 ps
CPU time 0.95 seconds
Started Aug 01 06:24:05 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 200284 kb
Host smart-21e6faf7-380c-4199-b34e-984217995a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370943751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3370943751
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.882073525
Short name T234
Test name
Test status
Simulation time 69071750 ps
CPU time 0.8 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:11 PM PDT 24
Peak memory 200088 kb
Host smart-142658a8-0206-4239-83ca-32c0ddb94fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882073525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.882073525
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3845463847
Short name T44
Test name
Test status
Simulation time 1889337994 ps
CPU time 7.15 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:15 PM PDT 24
Peak memory 221592 kb
Host smart-806621bf-3b78-47c3-97e7-af3c2d54a248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845463847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3845463847
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3306538143
Short name T306
Test name
Test status
Simulation time 245199275 ps
CPU time 1.1 seconds
Started Aug 01 06:24:13 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 217448 kb
Host smart-73415631-f0e4-4395-8c57-da7c6c18d51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306538143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3306538143
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.250015402
Short name T495
Test name
Test status
Simulation time 85480293 ps
CPU time 0.75 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:09 PM PDT 24
Peak memory 200100 kb
Host smart-3ecf1218-130f-4d95-8b8e-09b4d6419d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250015402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.250015402
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.910844792
Short name T322
Test name
Test status
Simulation time 1757670106 ps
CPU time 6.28 seconds
Started Aug 01 06:24:12 PM PDT 24
Finished Aug 01 06:24:18 PM PDT 24
Peak memory 200428 kb
Host smart-334fdae0-12fe-44fd-ac51-0c0fa71fe5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910844792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.910844792
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2298109536
Short name T411
Test name
Test status
Simulation time 150525599 ps
CPU time 1.15 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200300 kb
Host smart-baf141c0-c994-476b-8ee6-302687354b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298109536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2298109536
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3299032612
Short name T163
Test name
Test status
Simulation time 106150489 ps
CPU time 1.2 seconds
Started Aug 01 06:24:14 PM PDT 24
Finished Aug 01 06:24:15 PM PDT 24
Peak memory 200428 kb
Host smart-e1aa5b53-a8b6-41fc-b864-17a8e96e4c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299032612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3299032612
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2653720913
Short name T243
Test name
Test status
Simulation time 2796966926 ps
CPU time 12.45 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:19 PM PDT 24
Peak memory 208768 kb
Host smart-b40d8d8b-3365-4431-a7b2-c96082273d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653720913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2653720913
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1073753174
Short name T398
Test name
Test status
Simulation time 136457685 ps
CPU time 1.74 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 208520 kb
Host smart-baf61d06-614f-449a-9bef-acc00ca7007d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073753174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1073753174
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2598027747
Short name T202
Test name
Test status
Simulation time 257281393 ps
CPU time 1.52 seconds
Started Aug 01 06:24:11 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 200484 kb
Host smart-991dfbbe-6520-493c-a349-3f64824ad034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598027747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2598027747
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2058402332
Short name T523
Test name
Test status
Simulation time 72736466 ps
CPU time 0.8 seconds
Started Aug 01 06:24:06 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 200104 kb
Host smart-16e0b47a-716e-462c-8525-854cee9e9f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058402332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2058402332
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2986226916
Short name T280
Test name
Test status
Simulation time 1232590954 ps
CPU time 5.45 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 217680 kb
Host smart-d18aaede-ab1b-479b-a5ff-88f648b922d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986226916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2986226916
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1095975577
Short name T345
Test name
Test status
Simulation time 243875224 ps
CPU time 1.02 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 217444 kb
Host smart-41754ac3-cc2d-458e-a26b-04131fcc19e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095975577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1095975577
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2515130018
Short name T382
Test name
Test status
Simulation time 129196473 ps
CPU time 0.83 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:08 PM PDT 24
Peak memory 200100 kb
Host smart-7363e9a8-fe83-445e-bc6b-1eadc1427c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515130018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2515130018
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2958227003
Short name T427
Test name
Test status
Simulation time 919791821 ps
CPU time 4.88 seconds
Started Aug 01 06:24:06 PM PDT 24
Finished Aug 01 06:24:11 PM PDT 24
Peak memory 200428 kb
Host smart-20a8f967-d1b5-45fb-92d4-3068518f4e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958227003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2958227003
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1380270477
Short name T461
Test name
Test status
Simulation time 140247100 ps
CPU time 1.14 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200288 kb
Host smart-287c6431-d567-46fe-b796-7dc79060f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380270477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1380270477
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2003997230
Short name T154
Test name
Test status
Simulation time 199705902 ps
CPU time 1.49 seconds
Started Aug 01 06:24:06 PM PDT 24
Finished Aug 01 06:24:08 PM PDT 24
Peak memory 200360 kb
Host smart-ccfd9b2d-403b-4f36-8947-96a1ce662852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003997230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2003997230
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1013265623
Short name T351
Test name
Test status
Simulation time 6516535863 ps
CPU time 29.21 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:38 PM PDT 24
Peak memory 200532 kb
Host smart-860d9a6f-ad72-4ef0-a2a0-c2a24ecb15a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013265623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1013265623
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2739507404
Short name T374
Test name
Test status
Simulation time 355205408 ps
CPU time 2.45 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 200232 kb
Host smart-8a0a478e-e163-46f8-bc80-0fe3283f7943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739507404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2739507404
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1641097092
Short name T291
Test name
Test status
Simulation time 155950109 ps
CPU time 1.22 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200284 kb
Host smart-89af6c5d-4e2d-409f-a258-7d425f0644b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641097092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1641097092
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.4056572402
Short name T346
Test name
Test status
Simulation time 80158094 ps
CPU time 0.78 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:09 PM PDT 24
Peak memory 200068 kb
Host smart-5f5e05ea-465f-4f81-939e-dc4cfa5cffbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056572402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.4056572402
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1805453721
Short name T486
Test name
Test status
Simulation time 1897455395 ps
CPU time 6.94 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:15 PM PDT 24
Peak memory 216784 kb
Host smart-db61feeb-2371-4b01-a178-fc3a81bb3567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805453721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1805453721
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2323692943
Short name T240
Test name
Test status
Simulation time 244501050 ps
CPU time 1.07 seconds
Started Aug 01 06:24:12 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 217436 kb
Host smart-86190790-85db-4345-99b8-f2edbde05ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323692943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2323692943
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3145705025
Short name T428
Test name
Test status
Simulation time 111147281 ps
CPU time 0.76 seconds
Started Aug 01 06:24:11 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 200080 kb
Host smart-d4e3bc85-ee08-4e3e-963e-d04451e3930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145705025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3145705025
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1422102363
Short name T196
Test name
Test status
Simulation time 1771829844 ps
CPU time 6.8 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 200424 kb
Host smart-2e5114ad-09e6-4a91-b469-d36f6cfff5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422102363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1422102363
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2872986658
Short name T183
Test name
Test status
Simulation time 158374322 ps
CPU time 1.14 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200280 kb
Host smart-8f7b95b7-3c77-48b0-8555-e7f1c86b917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872986658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2872986658
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2247046380
Short name T248
Test name
Test status
Simulation time 119705976 ps
CPU time 1.14 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200400 kb
Host smart-8d3df660-b264-43f6-958d-2583e2f03383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247046380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2247046380
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.358938255
Short name T516
Test name
Test status
Simulation time 6759454414 ps
CPU time 24.65 seconds
Started Aug 01 06:24:13 PM PDT 24
Finished Aug 01 06:24:38 PM PDT 24
Peak memory 208808 kb
Host smart-dcfd5052-694c-446a-a6b8-e78e43aa2268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358938255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.358938255
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.475024718
Short name T52
Test name
Test status
Simulation time 463572367 ps
CPU time 2.32 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 200228 kb
Host smart-981f770f-0505-4b42-9e35-f3072dd9f41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475024718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.475024718
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.331178985
Short name T372
Test name
Test status
Simulation time 102772402 ps
CPU time 0.94 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 200240 kb
Host smart-80ca3ac7-f4a1-4c8c-96a7-efc8ece9a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331178985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.331178985
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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