Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8081

1

T1

26

T2

9

T8

20

auto[1]

11152

1

T1

33

T2

1

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5833	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6505	1			T1	15		T2	1		T3	1
reset_info_cp[2]	3058	1			T1	10		T5	1		T8	17
reset_info_cp[4]	3882	1			T1	19		T5	1		T8	14
reset_info_cp[8]	103	1			T10	2		T104	1		T105	1
reset_info_cp[16]	121	1			T2	1		T10	2		T31	2
reset_info_cp[32]	119	1			T10	1		T15	1		T31	2
reset_info_cp[64]	115	1			T10	2		T14	2		T92	1
reset_info_cp[128]	117	1			T13	2		T31	2		T38	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3094	1			T1	5		T8	20		T10	23
reset_info_cp[1]	auto[1]	2791	1			T1	9		T5	1		T8	6
reset_info_cp[2]	auto[0]	977	1			T1	5		T10	10		T14	5
reset_info_cp[2]	auto[1]	2081	1			T1	5		T5	1		T8	17
reset_info_cp[4]	auto[0]	1366	1			T1	5		T10	19		T14	5
reset_info_cp[4]	auto[1]	2516	1			T1	14		T5	1		T8	14
reset_info_cp[8]	auto[0]	46	1			T10	1		T140	2		T106	2
reset_info_cp[8]	auto[1]	57	1			T10	1		T104	1		T105	1
reset_info_cp[16]	auto[0]	47	1			T2	1		T10	2		T50	2
reset_info_cp[16]	auto[1]	74	1			T31	2		T141	1		T40	1
reset_info_cp[32]	auto[0]	54	1			T10	1		T15	1		T31	1
reset_info_cp[32]	auto[1]	65	1			T31	1		T50	1		T67	1
reset_info_cp[64]	auto[0]	43	1			T14	1		T83	1		T106	2
reset_info_cp[64]	auto[1]	72	1			T10	2		T14	1		T92	1
reset_info_cp[128]	auto[0]	45	1			T50	1		T83	1		T106	2
reset_info_cp[128]	auto[1]	72	1			T13	2		T31	2		T38	1