Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
count_cp	4	0	4	100.00	100	1	1	0
length_cp	8	0	8	100.00	100	1	1	0

Summary for Variable count_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for count_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8998	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cb[0]	1278	1			T1	3		T2	1		T3	1
cb[1]	1133	1			T1	4		T7	4		T8	4
cb[2]	1052	1			T1	4		T7	4		T8	4
cb[3]	984	1			T1	4		T7	4		T8	4

---

Summary for Variable length_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for length_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10994	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lb[0]	363	1			T7	1		T8	1		T10	1
lb[1]	317	1			T7	1		T10	2		T92	1
lb[2]	340	1			T1	1		T8	2		T10	1
lb[3]	328	1			T8	1		T10	2		T92	1
lb[4]	300	1			T13	1		T31	3		T22	2
lb[5]	288	1			T1	1		T13	2		T92	1
lb[6]	307	1			T8	1		T92	1		T21	2
lb[7]	208	1			T1	1		T13	1		T21	1