Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/14.rstmgr_por_stretcher.3432523595 Aug 02 05:17:33 PM PDT 24 Aug 02 05:17:34 PM PDT 24 155083204 ps
T537 /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.521093971 Aug 02 05:17:22 PM PDT 24 Aug 02 05:17:23 PM PDT 24 244652721 ps
T538 /workspace/coverage/default/32.rstmgr_alert_test.104378825 Aug 02 05:17:58 PM PDT 24 Aug 02 05:17:59 PM PDT 24 65787937 ps
T539 /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2045918028 Aug 02 05:17:45 PM PDT 24 Aug 02 05:17:46 PM PDT 24 243664221 ps
T540 /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.788271256 Aug 02 05:18:20 PM PDT 24 Aug 02 05:18:21 PM PDT 24 243991678 ps
T69 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.672365205 Aug 02 05:15:01 PM PDT 24 Aug 02 05:15:02 PM PDT 24 73122555 ps
T70 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3002572408 Aug 02 05:14:35 PM PDT 24 Aug 02 05:14:37 PM PDT 24 415661784 ps
T71 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.948418919 Aug 02 05:15:00 PM PDT 24 Aug 02 05:15:01 PM PDT 24 88278783 ps
T72 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1482875448 Aug 02 05:14:23 PM PDT 24 Aug 02 05:14:25 PM PDT 24 83779532 ps
T73 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1893873826 Aug 02 05:14:46 PM PDT 24 Aug 02 05:14:49 PM PDT 24 924073049 ps
T114 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1048374183 Aug 02 05:14:59 PM PDT 24 Aug 02 05:15:00 PM PDT 24 73117904 ps
T115 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4252147273 Aug 02 05:15:07 PM PDT 24 Aug 02 05:15:08 PM PDT 24 209355900 ps
T74 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1560759087 Aug 02 05:14:47 PM PDT 24 Aug 02 05:14:49 PM PDT 24 244112528 ps
T138 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3351950485 Aug 02 05:14:30 PM PDT 24 Aug 02 05:14:40 PM PDT 24 2280213629 ps
T77 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.413613802 Aug 02 05:14:58 PM PDT 24 Aug 02 05:15:01 PM PDT 24 898868010 ps
T96 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1354843566 Aug 02 05:14:59 PM PDT 24 Aug 02 05:15:01 PM PDT 24 417585140 ps
T122 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3295979252 Aug 02 05:14:44 PM PDT 24 Aug 02 05:14:46 PM PDT 24 478376930 ps
T75 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.990723220 Aug 02 05:14:23 PM PDT 24 Aug 02 05:14:26 PM PDT 24 431956418 ps
T76 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2324296646 Aug 02 05:14:47 PM PDT 24 Aug 02 05:14:48 PM PDT 24 175619921 ps
T97 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2612679529 Aug 02 05:14:31 PM PDT 24 Aug 02 05:14:32 PM PDT 24 185397974 ps
T98 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2818626825 Aug 02 05:14:54 PM PDT 24 Aug 02 05:14:57 PM PDT 24 799203603 ps
T541 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3163526434 Aug 02 05:14:27 PM PDT 24 Aug 02 05:14:28 PM PDT 24 93328204 ps
T116 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1182239104 Aug 02 05:14:52 PM PDT 24 Aug 02 05:14:53 PM PDT 24 285823865 ps
T103 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2697244895 Aug 02 05:14:59 PM PDT 24 Aug 02 05:15:03 PM PDT 24 878207198 ps
T117 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1614207982 Aug 02 05:14:48 PM PDT 24 Aug 02 05:14:49 PM PDT 24 86748797 ps
T118 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2835659010 Aug 02 05:14:54 PM PDT 24 Aug 02 05:14:56 PM PDT 24 147694036 ps
T99 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3330209391 Aug 02 05:14:58 PM PDT 24 Aug 02 05:15:01 PM PDT 24 373123056 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2942092503 Aug 02 05:14:29 PM PDT 24 Aug 02 05:14:30 PM PDT 24 91821831 ps
T100 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1299957707 Aug 02 05:14:22 PM PDT 24 Aug 02 05:14:24 PM PDT 24 153246458 ps
T543 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2403371896 Aug 02 05:14:35 PM PDT 24 Aug 02 05:14:36 PM PDT 24 87953737 ps
T101 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2673309862 Aug 02 05:14:48 PM PDT 24 Aug 02 05:14:49 PM PDT 24 117784622 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3174208500 Aug 02 05:14:48 PM PDT 24 Aug 02 05:14:49 PM PDT 24 128455379 ps
T102 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.757798934 Aug 02 05:14:48 PM PDT 24 Aug 02 05:14:52 PM PDT 24 623917146 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4102288271 Aug 02 05:14:48 PM PDT 24 Aug 02 05:14:51 PM PDT 24 765420403 ps
T119 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2070536739 Aug 02 05:14:58 PM PDT 24 Aug 02 05:14:59 PM PDT 24 74828129 ps
T546 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.604133350 Aug 02 05:14:51 PM PDT 24 Aug 02 05:14:54 PM PDT 24 813787552 ps
T120 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3102044962 Aug 02 05:14:23 PM PDT 24 Aug 02 05:14:24 PM PDT 24 63901824 ps
T547 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3849328591 Aug 02 05:15:00 PM PDT 24 Aug 02 05:15:02 PM PDT 24 65945231 ps
T127 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.716593078 Aug 02 05:14:31 PM PDT 24 Aug 02 05:14:33 PM PDT 24 167286001 ps
T128 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.405858910 Aug 02 05:14:44 PM PDT 24 Aug 02 05:14:45 PM PDT 24 123859074 ps
T126 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3603883624 Aug 02 05:14:55 PM PDT 24 Aug 02 05:14:58 PM PDT 24 439834345 ps
T548 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2373959594 Aug 02 05:14:37 PM PDT 24 Aug 02 05:14:39 PM PDT 24 207077824 ps
T549 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1694662505 Aug 02 05:14:23 PM PDT 24 Aug 02 05:14:24 PM PDT 24 87237011 ps
T123 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2428788279 Aug 02 05:14:37 PM PDT 24 Aug 02 05:14:39 PM PDT 24 480419428 ps
T550 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3499181473 Aug 02 05:14:54 PM PDT 24 Aug 02 05:14:55 PM PDT 24 81364542 ps
T551 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2469923303 Aug 02 05:14:43 PM PDT 24 Aug 02 05:14:44 PM PDT 24 210990740 ps
T552 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.98549114 Aug 02 05:14:40 PM PDT 24 Aug 02 05:14:41 PM PDT 24 102234067 ps
T121 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.59599603 Aug 02 05:14:54 PM PDT 24 Aug 02 05:14:55 PM PDT 24 122078784 ps
T553 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3003099647 Aug 02 05:14:52 PM PDT 24 Aug 02 05:14:54 PM PDT 24 471236987 ps
T554 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.586009510 Aug 02 05:14:59 PM PDT 24 Aug 02 05:15:02 PM PDT 24 186453550 ps
T555 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3266860994 Aug 02 05:14:37 PM PDT 24 Aug 02 05:14:38 PM PDT 24 119857517 ps
T556 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2176291121 Aug 02 05:14:38 PM PDT 24 Aug 02 05:14:41 PM PDT 24 435209896 ps
T557 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.407648278 Aug 02 05:14:31 PM PDT 24 Aug 02 05:14:33 PM PDT 24 477662009 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.677354602 Aug 02 05:14:45 PM PDT 24 Aug 02 05:14:53 PM PDT 24 1547798361 ps
T559 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3636856757 Aug 02 05:14:52 PM PDT 24 Aug 02 05:14:54 PM PDT 24 146406265 ps
T560 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.264687599 Aug 02 05:14:54 PM PDT 24 Aug 02 05:14:55 PM PDT 24 72276676 ps
T561 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2885948699 Aug 02 05:14:55 PM PDT 24 Aug 02 05:14:58 PM PDT 24 540871920 ps
T562 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3926764809 Aug 02 05:14:17 PM PDT 24 Aug 02 05:14:19 PM PDT 24 209397760 ps
T563 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3085830423 Aug 02 05:14:32 PM PDT 24 Aug 02 05:14:37 PM PDT 24 1022324430 ps
T564 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3172219309 Aug 02 05:14:49 PM PDT 24 Aug 02 05:14:52 PM PDT 24 418333262 ps
T565 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3140335927 Aug 02 05:15:04 PM PDT 24 Aug 02 05:15:05 PM PDT 24 121164391 ps
T566 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.583488173 Aug 02 05:14:35 PM PDT 24 Aug 02 05:14:43 PM PDT 24 1542085291 ps
T567 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.953162988 Aug 02 05:14:40 PM PDT 24 Aug 02 05:14:41 PM PDT 24 81533399 ps
T568 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2136258504 Aug 02 05:14:53 PM PDT 24 Aug 02 05:14:54 PM PDT 24 99697725 ps
T569 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3387548931 Aug 02 05:14:58 PM PDT 24 Aug 02 05:14:59 PM PDT 24 107661678 ps
T570 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2931160013 Aug 02 05:14:36 PM PDT 24 Aug 02 05:14:38 PM PDT 24 80400613 ps
T571 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.19628751 Aug 02 05:14:54 PM PDT 24 Aug 02 05:14:56 PM PDT 24 129986320 ps
T572 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1605943466 Aug 02 05:14:45 PM PDT 24 Aug 02 05:14:47 PM PDT 24 436457232 ps
T573 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2165272050 Aug 02 05:14:29 PM PDT 24 Aug 02 05:14:30 PM PDT 24 58364665 ps
T574 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.925750080 Aug 02 05:14:42 PM PDT 24 Aug 02 05:14:44 PM PDT 24 101699798 ps
T575 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3887243354 Aug 02 05:14:35 PM PDT 24 Aug 02 05:14:38 PM PDT 24 187617282 ps
T576 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4161687033 Aug 02 05:14:53 PM PDT 24 Aug 02 05:14:54 PM PDT 24 127622588 ps
T577 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.970139652 Aug 02 05:14:49 PM PDT 24 Aug 02 05:14:51 PM PDT 24 478126944 ps
T124 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.311771185 Aug 02 05:14:26 PM PDT 24 Aug 02 05:14:29 PM PDT 24 899488877 ps
T578 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.551164147 Aug 02 05:14:49 PM PDT 24 Aug 02 05:14:51 PM PDT 24 194571927 ps
T579 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3002966519 Aug 02 05:15:00 PM PDT 24 Aug 02 05:15:01 PM PDT 24 191690055 ps
T580 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1415178225 Aug 02 05:14:47 PM PDT 24 Aug 02 05:14:48 PM PDT 24 88494989 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1816353812 Aug 02 05:14:49 PM PDT 24 Aug 02 05:14:51 PM PDT 24 285529373 ps
T582 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.184931942 Aug 02 05:14:24 PM PDT 24 Aug 02 05:14:27 PM PDT 24 435785766 ps
T583 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3668969831 Aug 02 05:14:55 PM PDT 24 Aug 02 05:14:56 PM PDT 24 67124344 ps
T136 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3136287093 Aug 02 05:14:42 PM PDT 24 Aug 02 05:14:44 PM PDT 24 524153971 ps
T584 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1307625137 Aug 02 05:14:26 PM PDT 24 Aug 02 05:14:27 PM PDT 24 74325708 ps
T585 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.283502577 Aug 02 05:14:44 PM PDT 24 Aug 02 05:14:46 PM PDT 24 426901170 ps
T586 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4132319066 Aug 02 05:14:46 PM PDT 24 Aug 02 05:14:47 PM PDT 24 132082240 ps
T587 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.683327854 Aug 02 05:14:35 PM PDT 24 Aug 02 05:14:36 PM PDT 24 193280017 ps
T588 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3090114917 Aug 02 05:14:47 PM PDT 24 Aug 02 05:14:53 PM PDT 24 188954409 ps
T589 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.153489353 Aug 02 05:14:36 PM PDT 24 Aug 02 05:14:37 PM PDT 24 68080299 ps
T590 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.409948219 Aug 02 05:14:45 PM PDT 24 Aug 02 05:14:46 PM PDT 24 193323567 ps
T591 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4235301250 Aug 02 05:15:00 PM PDT 24 Aug 02 05:15:01 PM PDT 24 73238178 ps
T592 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.914983779 Aug 02 05:14:45 PM PDT 24 Aug 02 05:14:49 PM PDT 24 877873638 ps
T593 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.639667773 Aug 02 05:14:39 PM PDT 24 Aug 02 05:14:40 PM PDT 24 72485497 ps
T594 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1711648859 Aug 02 05:14:37 PM PDT 24 Aug 02 05:14:41 PM PDT 24 572079839 ps
T125 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.239063558 Aug 02 05:14:54 PM PDT 24 Aug 02 05:14:57 PM PDT 24 904955693 ps
T595 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.245582439 Aug 02 05:15:03 PM PDT 24 Aug 02 05:15:04 PM PDT 24 85204105 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4115315260 Aug 02 05:14:49 PM PDT 24 Aug 02 05:14:51 PM PDT 24 158451367 ps
T597 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2057392868 Aug 02 05:14:46 PM PDT 24 Aug 02 05:14:47 PM PDT 24 102992062 ps
T598 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3393187329 Aug 02 05:14:51 PM PDT 24 Aug 02 05:14:52 PM PDT 24 54278184 ps
T599 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2869385864 Aug 02 05:15:00 PM PDT 24 Aug 02 05:15:02 PM PDT 24 92022033 ps
T600 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2722860461 Aug 02 05:14:40 PM PDT 24 Aug 02 05:14:41 PM PDT 24 85457270 ps
T601 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.718465688 Aug 02 05:14:46 PM PDT 24 Aug 02 05:14:47 PM PDT 24 121028601 ps
T602 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1485488850 Aug 02 05:14:50 PM PDT 24 Aug 02 05:14:54 PM PDT 24 479043985 ps
T603 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4115405987 Aug 02 05:14:50 PM PDT 24 Aug 02 05:14:52 PM PDT 24 192408327 ps
T604 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2934788992 Aug 02 05:14:59 PM PDT 24 Aug 02 05:15:00 PM PDT 24 76486702 ps
T605 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.228627094 Aug 02 05:14:26 PM PDT 24 Aug 02 05:14:28 PM PDT 24 150898845 ps
T606 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3909620890 Aug 02 05:14:53 PM PDT 24 Aug 02 05:14:54 PM PDT 24 203037913 ps
T607 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2242960656 Aug 02 05:14:24 PM PDT 24 Aug 02 05:14:26 PM PDT 24 145649723 ps
T608 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1676410564 Aug 02 05:14:46 PM PDT 24 Aug 02 05:14:47 PM PDT 24 162491914 ps
T609 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.507623680 Aug 02 05:14:25 PM PDT 24 Aug 02 05:14:28 PM PDT 24 272192602 ps
T610 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3701132469 Aug 02 05:14:50 PM PDT 24 Aug 02 05:14:57 PM PDT 24 197195730 ps
T611 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1339100520 Aug 02 05:14:48 PM PDT 24 Aug 02 05:14:49 PM PDT 24 61614508 ps
T612 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2841174332 Aug 02 05:15:08 PM PDT 24 Aug 02 05:15:10 PM PDT 24 262121818 ps
T613 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.346651205 Aug 02 05:14:52 PM PDT 24 Aug 02 05:14:55 PM PDT 24 195867803 ps
T614 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.698024739 Aug 02 05:14:49 PM PDT 24 Aug 02 05:14:52 PM PDT 24 408405253 ps
T615 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.314989837 Aug 02 05:14:22 PM PDT 24 Aug 02 05:14:23 PM PDT 24 102164290 ps
T616 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2065516817 Aug 02 05:14:47 PM PDT 24 Aug 02 05:14:48 PM PDT 24 65413383 ps
T137 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2721232855 Aug 02 05:14:27 PM PDT 24 Aug 02 05:14:31 PM PDT 24 920920510 ps
T617 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.101479276 Aug 02 05:14:59 PM PDT 24 Aug 02 05:15:05 PM PDT 24 109445846 ps
T618 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.145997979 Aug 02 05:14:42 PM PDT 24 Aug 02 05:14:44 PM PDT 24 99537579 ps
T619 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1371884489 Aug 02 05:14:49 PM PDT 24 Aug 02 05:14:52 PM PDT 24 208781613 ps
T620 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.64272669 Aug 02 05:15:01 PM PDT 24 Aug 02 05:15:02 PM PDT 24 113987224 ps

Test location /workspace/coverage/default/18.rstmgr_stress_all.2313472309
Short name T10
Test name
Test status
Simulation time 2565969912 ps
CPU time 11.44 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:32 PM PDT 24
Peak memory 208812 kb
Host smart-863fd671-c8d2-4094-8739-276e45b60ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313472309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2313472309
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3985228862
Short name T91
Test name
Test status
Simulation time 188993781 ps
CPU time 1.36 seconds
Started Aug 02 05:17:22 PM PDT 24
Finished Aug 02 05:17:23 PM PDT 24
Peak memory 200508 kb
Host smart-7c278727-41f5-4b4b-8c09-c7c050f11a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985228862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3985228862
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1893873826
Short name T73
Test name
Test status
Simulation time 924073049 ps
CPU time 3.25 seconds
Started Aug 02 05:14:46 PM PDT 24
Finished Aug 02 05:14:49 PM PDT 24
Peak memory 200140 kb
Host smart-b631b618-4ff7-4cb4-8283-2d2be1c03710
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893873826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1893873826
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.693354209
Short name T33
Test name
Test status
Simulation time 453535353 ps
CPU time 2.29 seconds
Started Aug 02 05:17:29 PM PDT 24
Finished Aug 02 05:17:32 PM PDT 24
Peak memory 208508 kb
Host smart-4a0db1ea-50e1-4eda-8fb8-44aa668b836b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693354209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.693354209
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1154973206
Short name T57
Test name
Test status
Simulation time 8581810423 ps
CPU time 12.97 seconds
Started Aug 02 05:16:52 PM PDT 24
Finished Aug 02 05:17:05 PM PDT 24
Peak memory 217256 kb
Host smart-a156ba06-3a0b-47da-8412-f755555eba6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154973206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1154973206
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3408609845
Short name T8
Test name
Test status
Simulation time 1893544212 ps
CPU time 7.67 seconds
Started Aug 02 05:17:03 PM PDT 24
Finished Aug 02 05:17:11 PM PDT 24
Peak memory 221772 kb
Host smart-b17d0b3f-68c0-491a-b27f-d8f0a9b68aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408609845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3408609845
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3330209391
Short name T99
Test name
Test status
Simulation time 373123056 ps
CPU time 3.16 seconds
Started Aug 02 05:14:58 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 208464 kb
Host smart-bc86a05e-1bd1-45a6-bf8c-d60feb2a20d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330209391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3330209391
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.4127594154
Short name T50
Test name
Test status
Simulation time 4717445115 ps
CPU time 21.11 seconds
Started Aug 02 05:17:27 PM PDT 24
Finished Aug 02 05:17:48 PM PDT 24
Peak memory 200612 kb
Host smart-425425ff-2350-47fc-8aab-a6f75e3f610b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127594154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.4127594154
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.472954666
Short name T51
Test name
Test status
Simulation time 99530744 ps
CPU time 0.96 seconds
Started Aug 02 05:17:32 PM PDT 24
Finished Aug 02 05:17:33 PM PDT 24
Peak memory 200412 kb
Host smart-f9b66afc-e005-441d-af61-897c5c518254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472954666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.472954666
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1203948247
Short name T40
Test name
Test status
Simulation time 1902547902 ps
CPU time 7.28 seconds
Started Aug 02 05:17:18 PM PDT 24
Finished Aug 02 05:17:25 PM PDT 24
Peak memory 217420 kb
Host smart-c0701c18-9d24-4095-b984-66ab8f246216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203948247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1203948247
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.463222056
Short name T153
Test name
Test status
Simulation time 67578307 ps
CPU time 0.74 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:11 PM PDT 24
Peak memory 200160 kb
Host smart-2500f3fd-121c-4fd7-ac68-3a3bf5eef056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463222056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.463222056
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1208902502
Short name T113
Test name
Test status
Simulation time 12877471290 ps
CPU time 45.4 seconds
Started Aug 02 05:17:58 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 208820 kb
Host smart-4817c8c0-5e73-4a3a-beff-056978ad4a69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208902502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1208902502
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2428788279
Short name T123
Test name
Test status
Simulation time 480419428 ps
CPU time 1.9 seconds
Started Aug 02 05:14:37 PM PDT 24
Finished Aug 02 05:14:39 PM PDT 24
Peak memory 200256 kb
Host smart-9cc3fe30-9b0f-4f0c-8006-2754337c8778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428788279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2428788279
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3009129075
Short name T15
Test name
Test status
Simulation time 148492901 ps
CPU time 1.05 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 200368 kb
Host smart-b86993d4-fc33-47c8-8a5b-aefb34e127ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009129075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3009129075
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2872433366
Short name T42
Test name
Test status
Simulation time 1887578436 ps
CPU time 6.95 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 221620 kb
Host smart-ad0bc01f-b33e-4df0-86e1-b426822357ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872433366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2872433366
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3102044962
Short name T120
Test name
Test status
Simulation time 63901824 ps
CPU time 0.74 seconds
Started Aug 02 05:14:23 PM PDT 24
Finished Aug 02 05:14:24 PM PDT 24
Peak memory 200004 kb
Host smart-f6fd8671-1610-42d1-9e0a-18f85d6abe1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102044962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3102044962
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1778430473
Short name T26
Test name
Test status
Simulation time 170706638 ps
CPU time 0.91 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 200072 kb
Host smart-e27df9fa-b51f-4437-ab4e-ae61996d0e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778430473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1778430473
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2697244895
Short name T103
Test name
Test status
Simulation time 878207198 ps
CPU time 3.22 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:03 PM PDT 24
Peak memory 200220 kb
Host smart-f7d01a59-74c1-448e-8b5f-089dfc8a2838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697244895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2697244895
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.239063558
Short name T125
Test name
Test status
Simulation time 904955693 ps
CPU time 3.1 seconds
Started Aug 02 05:14:54 PM PDT 24
Finished Aug 02 05:14:57 PM PDT 24
Peak memory 200200 kb
Host smart-d727b872-281e-461e-9b04-170267e4a004
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239063558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.239063558
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2176291121
Short name T556
Test name
Test status
Simulation time 435209896 ps
CPU time 2.57 seconds
Started Aug 02 05:14:38 PM PDT 24
Finished Aug 02 05:14:41 PM PDT 24
Peak memory 200120 kb
Host smart-ef39f245-7d3c-4ba7-8c17-b6493691a9b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176291121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
176291121
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.507623680
Short name T609
Test name
Test status
Simulation time 272192602 ps
CPU time 3.26 seconds
Started Aug 02 05:14:25 PM PDT 24
Finished Aug 02 05:14:28 PM PDT 24
Peak memory 200148 kb
Host smart-30a078de-45d7-4065-a742-5894283104ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507623680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.507623680
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3174208500
Short name T544
Test name
Test status
Simulation time 128455379 ps
CPU time 0.96 seconds
Started Aug 02 05:14:48 PM PDT 24
Finished Aug 02 05:14:49 PM PDT 24
Peak memory 200032 kb
Host smart-ab93dd1c-d299-42c7-b87d-c3342de73dd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174208500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
174208500
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1299957707
Short name T100
Test name
Test status
Simulation time 153246458 ps
CPU time 1.33 seconds
Started Aug 02 05:14:22 PM PDT 24
Finished Aug 02 05:14:24 PM PDT 24
Peak memory 208412 kb
Host smart-c711b663-1938-44f8-9309-30d03df264e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299957707 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1299957707
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1307625137
Short name T584
Test name
Test status
Simulation time 74325708 ps
CPU time 0.82 seconds
Started Aug 02 05:14:26 PM PDT 24
Finished Aug 02 05:14:27 PM PDT 24
Peak memory 200072 kb
Host smart-ba59d47c-092c-4b97-a76d-0dbb84005a6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307625137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1307625137
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.925750080
Short name T574
Test name
Test status
Simulation time 101699798 ps
CPU time 1.27 seconds
Started Aug 02 05:14:42 PM PDT 24
Finished Aug 02 05:14:44 PM PDT 24
Peak memory 200220 kb
Host smart-2c53ddce-c3a3-41bd-8881-2cc35f541717
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925750080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.925750080
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3926764809
Short name T562
Test name
Test status
Simulation time 209397760 ps
CPU time 1.75 seconds
Started Aug 02 05:14:17 PM PDT 24
Finished Aug 02 05:14:19 PM PDT 24
Peak memory 200152 kb
Host smart-7db3741c-fee9-45d8-88e5-ef3e9494fe6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926764809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3926764809
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2721232855
Short name T137
Test name
Test status
Simulation time 920920510 ps
CPU time 3.25 seconds
Started Aug 02 05:14:27 PM PDT 24
Finished Aug 02 05:14:31 PM PDT 24
Peak memory 200260 kb
Host smart-0152eb91-7351-488f-af68-0b6b36215cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721232855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2721232855
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.184931942
Short name T582
Test name
Test status
Simulation time 435785766 ps
CPU time 2.72 seconds
Started Aug 02 05:14:24 PM PDT 24
Finished Aug 02 05:14:27 PM PDT 24
Peak memory 200168 kb
Host smart-3b1f0bc5-ccd8-4ac6-ad24-593307ef0941
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184931942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.184931942
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3351950485
Short name T138
Test name
Test status
Simulation time 2280213629 ps
CPU time 10.51 seconds
Started Aug 02 05:14:30 PM PDT 24
Finished Aug 02 05:14:40 PM PDT 24
Peak memory 200204 kb
Host smart-3b9c7bc6-c695-4121-8f2d-d287e7aee5d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351950485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
351950485
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3163526434
Short name T541
Test name
Test status
Simulation time 93328204 ps
CPU time 0.88 seconds
Started Aug 02 05:14:27 PM PDT 24
Finished Aug 02 05:14:28 PM PDT 24
Peak memory 200060 kb
Host smart-04281719-4703-4175-906b-bb79f8b57580
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163526434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
163526434
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.716593078
Short name T127
Test name
Test status
Simulation time 167286001 ps
CPU time 1.4 seconds
Started Aug 02 05:14:31 PM PDT 24
Finished Aug 02 05:14:33 PM PDT 24
Peak memory 208472 kb
Host smart-66b78520-1eff-40ac-aa26-6726722af04c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716593078 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.716593078
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.639667773
Short name T593
Test name
Test status
Simulation time 72485497 ps
CPU time 0.93 seconds
Started Aug 02 05:14:39 PM PDT 24
Finished Aug 02 05:14:40 PM PDT 24
Peak memory 200180 kb
Host smart-73fa53e0-5699-4089-8685-8ab6d1861acb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639667773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.639667773
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.990723220
Short name T75
Test name
Test status
Simulation time 431956418 ps
CPU time 2.89 seconds
Started Aug 02 05:14:23 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 208328 kb
Host smart-603f560a-4d56-463b-9ebc-f1df75e25406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990723220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.990723220
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.407648278
Short name T557
Test name
Test status
Simulation time 477662009 ps
CPU time 1.89 seconds
Started Aug 02 05:14:31 PM PDT 24
Finished Aug 02 05:14:33 PM PDT 24
Peak memory 200244 kb
Host smart-bf51e23b-3718-4e8b-aa57-c56b7ab4bab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407648278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
407648278
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3701132469
Short name T610
Test name
Test status
Simulation time 197195730 ps
CPU time 1.98 seconds
Started Aug 02 05:14:50 PM PDT 24
Finished Aug 02 05:14:57 PM PDT 24
Peak memory 208492 kb
Host smart-b2daebf6-f59d-470c-950d-9d845f6b3678
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701132469 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3701132469
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4235301250
Short name T591
Test name
Test status
Simulation time 73238178 ps
CPU time 0.76 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 199964 kb
Host smart-6ac78d92-009e-4039-960f-e330b9015abc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235301250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4235301250
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.551164147
Short name T578
Test name
Test status
Simulation time 194571927 ps
CPU time 1.47 seconds
Started Aug 02 05:14:49 PM PDT 24
Finished Aug 02 05:14:51 PM PDT 24
Peak memory 200152 kb
Host smart-1d7cc8bf-3ba6-41ea-bcfe-23dd886c5ff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551164147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.551164147
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.914983779
Short name T592
Test name
Test status
Simulation time 877873638 ps
CPU time 3.21 seconds
Started Aug 02 05:14:45 PM PDT 24
Finished Aug 02 05:14:49 PM PDT 24
Peak memory 200300 kb
Host smart-df3cd548-a465-42a1-a499-2be251a8a349
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914983779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.914983779
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4132319066
Short name T586
Test name
Test status
Simulation time 132082240 ps
CPU time 1.02 seconds
Started Aug 02 05:14:46 PM PDT 24
Finished Aug 02 05:14:47 PM PDT 24
Peak memory 200116 kb
Host smart-b5be6a21-5bbd-43b6-b036-12dba5b8ab9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132319066 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.4132319066
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2065516817
Short name T616
Test name
Test status
Simulation time 65413383 ps
CPU time 0.76 seconds
Started Aug 02 05:14:47 PM PDT 24
Finished Aug 02 05:14:48 PM PDT 24
Peak memory 200004 kb
Host smart-dd7d75ea-b78f-4326-bd30-d66e5cffeec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065516817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2065516817
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2057392868
Short name T597
Test name
Test status
Simulation time 102992062 ps
CPU time 1.28 seconds
Started Aug 02 05:14:46 PM PDT 24
Finished Aug 02 05:14:47 PM PDT 24
Peak memory 200236 kb
Host smart-0ca6eb2b-fe0f-47ba-a613-2495a2e4885c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057392868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2057392868
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1371884489
Short name T619
Test name
Test status
Simulation time 208781613 ps
CPU time 2.91 seconds
Started Aug 02 05:14:49 PM PDT 24
Finished Aug 02 05:14:52 PM PDT 24
Peak memory 208392 kb
Host smart-6acd9636-2d76-48c5-aa53-00949ff663fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371884489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1371884489
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.970139652
Short name T577
Test name
Test status
Simulation time 478126944 ps
CPU time 2 seconds
Started Aug 02 05:14:49 PM PDT 24
Finished Aug 02 05:14:51 PM PDT 24
Peak memory 200240 kb
Host smart-9f2c0a65-091f-47e2-8a84-58e30651c58d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970139652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.970139652
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.409948219
Short name T590
Test name
Test status
Simulation time 193323567 ps
CPU time 1.19 seconds
Started Aug 02 05:14:45 PM PDT 24
Finished Aug 02 05:14:46 PM PDT 24
Peak memory 200180 kb
Host smart-37cf1e3a-2fcb-4701-a63d-99f417dd3d82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409948219 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.409948219
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2934788992
Short name T604
Test name
Test status
Simulation time 76486702 ps
CPU time 0.82 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:00 PM PDT 24
Peak memory 200060 kb
Host smart-5891ac95-21e7-40a2-bc64-857bb6a97ac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934788992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2934788992
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.101479276
Short name T617
Test name
Test status
Simulation time 109445846 ps
CPU time 1 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:05 PM PDT 24
Peak memory 200140 kb
Host smart-536f4daa-e15b-443d-85f0-5336fc90ecc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101479276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.101479276
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.145997979
Short name T618
Test name
Test status
Simulation time 99537579 ps
CPU time 1.4 seconds
Started Aug 02 05:14:42 PM PDT 24
Finished Aug 02 05:14:44 PM PDT 24
Peak memory 200124 kb
Host smart-3252ea04-076d-4c2b-8e19-321d1afb5e87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145997979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.145997979
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4161687033
Short name T576
Test name
Test status
Simulation time 127622588 ps
CPU time 1.47 seconds
Started Aug 02 05:14:53 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 208488 kb
Host smart-d994d3df-e9bc-4951-865d-57e55a9e1741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161687033 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4161687033
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2070536739
Short name T119
Test name
Test status
Simulation time 74828129 ps
CPU time 0.85 seconds
Started Aug 02 05:14:58 PM PDT 24
Finished Aug 02 05:14:59 PM PDT 24
Peak memory 200084 kb
Host smart-c1b3770d-cd76-4bbe-8238-50982b7e1d24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070536739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2070536739
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1182239104
Short name T116
Test name
Test status
Simulation time 285823865 ps
CPU time 1.65 seconds
Started Aug 02 05:14:52 PM PDT 24
Finished Aug 02 05:14:53 PM PDT 24
Peak memory 200152 kb
Host smart-3bc3dce2-559b-48d0-a1db-5868fc6865df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182239104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1182239104
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2841174332
Short name T612
Test name
Test status
Simulation time 262121818 ps
CPU time 1.91 seconds
Started Aug 02 05:15:08 PM PDT 24
Finished Aug 02 05:15:10 PM PDT 24
Peak memory 208472 kb
Host smart-6c3a0906-f3ca-4cf1-84be-b2d9eae705aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841174332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2841174332
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2136258504
Short name T568
Test name
Test status
Simulation time 99697725 ps
CPU time 0.9 seconds
Started Aug 02 05:14:53 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 200200 kb
Host smart-a11ad47c-12d8-4f6c-bdee-dd647e2a43d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136258504 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2136258504
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3393187329
Short name T598
Test name
Test status
Simulation time 54278184 ps
CPU time 0.77 seconds
Started Aug 02 05:14:51 PM PDT 24
Finished Aug 02 05:14:52 PM PDT 24
Peak memory 200096 kb
Host smart-e9517fa6-4456-4d50-aa0d-70e82e0989ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393187329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3393187329
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3636856757
Short name T559
Test name
Test status
Simulation time 146406265 ps
CPU time 1.37 seconds
Started Aug 02 05:14:52 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 208460 kb
Host smart-f42657d7-a722-44fb-b6c7-c469c55dd9b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636856757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3636856757
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2885948699
Short name T561
Test name
Test status
Simulation time 540871920 ps
CPU time 3.38 seconds
Started Aug 02 05:14:55 PM PDT 24
Finished Aug 02 05:14:58 PM PDT 24
Peak memory 200156 kb
Host smart-f9853026-f115-4663-bf62-5e4fea0341f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885948699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2885948699
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3003099647
Short name T553
Test name
Test status
Simulation time 471236987 ps
CPU time 2.03 seconds
Started Aug 02 05:14:52 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 200284 kb
Host smart-75f0891f-5c01-4ac4-9d12-e25830a381f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003099647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3003099647
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3090114917
Short name T588
Test name
Test status
Simulation time 188954409 ps
CPU time 1.23 seconds
Started Aug 02 05:14:47 PM PDT 24
Finished Aug 02 05:14:53 PM PDT 24
Peak memory 208404 kb
Host smart-6f781582-1b92-4e5d-bbae-1615de24a45b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090114917 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3090114917
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1339100520
Short name T611
Test name
Test status
Simulation time 61614508 ps
CPU time 0.77 seconds
Started Aug 02 05:14:48 PM PDT 24
Finished Aug 02 05:14:49 PM PDT 24
Peak memory 200028 kb
Host smart-6eab0284-6f23-433f-a06b-e084b6c2e88d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339100520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1339100520
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.718465688
Short name T601
Test name
Test status
Simulation time 121028601 ps
CPU time 1.02 seconds
Started Aug 02 05:14:46 PM PDT 24
Finished Aug 02 05:14:47 PM PDT 24
Peak memory 200172 kb
Host smart-63e04c30-0a95-4e7c-8bf4-fb65dacfcbb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718465688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.718465688
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3603883624
Short name T126
Test name
Test status
Simulation time 439834345 ps
CPU time 3.23 seconds
Started Aug 02 05:14:55 PM PDT 24
Finished Aug 02 05:14:58 PM PDT 24
Peak memory 208448 kb
Host smart-a2fa8963-1e30-4b4b-965c-6acb9390e106
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603883624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3603883624
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3295979252
Short name T122
Test name
Test status
Simulation time 478376930 ps
CPU time 1.97 seconds
Started Aug 02 05:14:44 PM PDT 24
Finished Aug 02 05:14:46 PM PDT 24
Peak memory 200228 kb
Host smart-29dceba0-2fdd-4bc6-b1a5-6fa65d1b857e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295979252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3295979252
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2673309862
Short name T101
Test name
Test status
Simulation time 117784622 ps
CPU time 1.21 seconds
Started Aug 02 05:14:48 PM PDT 24
Finished Aug 02 05:14:49 PM PDT 24
Peak memory 208288 kb
Host smart-40f628fc-5043-4225-9d6e-52bf4c9a9384
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673309862 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2673309862
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3668969831
Short name T583
Test name
Test status
Simulation time 67124344 ps
CPU time 0.8 seconds
Started Aug 02 05:14:55 PM PDT 24
Finished Aug 02 05:14:56 PM PDT 24
Peak memory 200096 kb
Host smart-7d0c9fd9-536e-4034-96ff-8b0f7c708797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668969831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3668969831
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.245582439
Short name T595
Test name
Test status
Simulation time 85204105 ps
CPU time 0.97 seconds
Started Aug 02 05:15:03 PM PDT 24
Finished Aug 02 05:15:04 PM PDT 24
Peak memory 200140 kb
Host smart-ae0a4dd0-8a1e-4f50-b795-ce1ee7b40cb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245582439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.245582439
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.346651205
Short name T613
Test name
Test status
Simulation time 195867803 ps
CPU time 2.77 seconds
Started Aug 02 05:14:52 PM PDT 24
Finished Aug 02 05:14:55 PM PDT 24
Peak memory 211584 kb
Host smart-0807a83c-4ed3-4c44-8a85-7eeb8d88006e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346651205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.346651205
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3909620890
Short name T606
Test name
Test status
Simulation time 203037913 ps
CPU time 1.32 seconds
Started Aug 02 05:14:53 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 208324 kb
Host smart-b244aead-0fe0-40da-90f8-a22cdcd3bf4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909620890 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3909620890
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.672365205
Short name T69
Test name
Test status
Simulation time 73122555 ps
CPU time 0.79 seconds
Started Aug 02 05:15:01 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 200148 kb
Host smart-29bb9785-2232-4fed-be14-16947da15b7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672365205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.672365205
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3002966519
Short name T579
Test name
Test status
Simulation time 191690055 ps
CPU time 1.47 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 200216 kb
Host smart-397c5477-e118-437d-9b81-7add55a7f9d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002966519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3002966519
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1485488850
Short name T602
Test name
Test status
Simulation time 479043985 ps
CPU time 3.05 seconds
Started Aug 02 05:14:50 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 208232 kb
Host smart-edc78b77-90f3-4eee-a85a-6977bcb1369f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485488850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1485488850
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2818626825
Short name T98
Test name
Test status
Simulation time 799203603 ps
CPU time 3.16 seconds
Started Aug 02 05:14:54 PM PDT 24
Finished Aug 02 05:14:57 PM PDT 24
Peak memory 200076 kb
Host smart-c7ebf2d0-c1e4-4b56-a473-59de0691df13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818626825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2818626825
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2324296646
Short name T76
Test name
Test status
Simulation time 175619921 ps
CPU time 1.22 seconds
Started Aug 02 05:14:47 PM PDT 24
Finished Aug 02 05:14:48 PM PDT 24
Peak memory 200176 kb
Host smart-96320b45-4e14-41ca-a559-f1a05baab943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324296646 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2324296646
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3499181473
Short name T550
Test name
Test status
Simulation time 81364542 ps
CPU time 0.83 seconds
Started Aug 02 05:14:54 PM PDT 24
Finished Aug 02 05:14:55 PM PDT 24
Peak memory 200112 kb
Host smart-20e4b662-24a9-473f-9c24-def3e0e297f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499181473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3499181473
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3140335927
Short name T565
Test name
Test status
Simulation time 121164391 ps
CPU time 1.12 seconds
Started Aug 02 05:15:04 PM PDT 24
Finished Aug 02 05:15:05 PM PDT 24
Peak memory 200160 kb
Host smart-e768afc8-6571-4d13-a0ae-c1aca68f1862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140335927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3140335927
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.586009510
Short name T554
Test name
Test status
Simulation time 186453550 ps
CPU time 2.6 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 208360 kb
Host smart-8908f68c-d5d5-4e88-9f36-5872769d1605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586009510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.586009510
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1354843566
Short name T96
Test name
Test status
Simulation time 417585140 ps
CPU time 1.78 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 200340 kb
Host smart-22657d14-1ee4-4803-a8f4-c091d9b4ae98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354843566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1354843566
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4115405987
Short name T603
Test name
Test status
Simulation time 192408327 ps
CPU time 1.32 seconds
Started Aug 02 05:14:50 PM PDT 24
Finished Aug 02 05:14:52 PM PDT 24
Peak memory 200196 kb
Host smart-000e5889-ccf5-4d25-84a5-475001aac406
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115405987 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4115405987
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1048374183
Short name T114
Test name
Test status
Simulation time 73117904 ps
CPU time 0.75 seconds
Started Aug 02 05:14:59 PM PDT 24
Finished Aug 02 05:15:00 PM PDT 24
Peak memory 200120 kb
Host smart-c446854c-4a80-40c0-b4a7-1e6c2e1616e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048374183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1048374183
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.19628751
Short name T571
Test name
Test status
Simulation time 129986320 ps
CPU time 1.3 seconds
Started Aug 02 05:14:54 PM PDT 24
Finished Aug 02 05:14:56 PM PDT 24
Peak memory 200136 kb
Host smart-53c356a8-50f6-4053-94fd-87cb1d651cb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19628751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sam
e_csr_outstanding.19628751
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3172219309
Short name T564
Test name
Test status
Simulation time 418333262 ps
CPU time 2.94 seconds
Started Aug 02 05:14:49 PM PDT 24
Finished Aug 02 05:14:52 PM PDT 24
Peak memory 208428 kb
Host smart-f326f4d2-577e-4450-91ac-2189ad31a0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172219309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3172219309
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1605943466
Short name T572
Test name
Test status
Simulation time 436457232 ps
CPU time 1.88 seconds
Started Aug 02 05:14:45 PM PDT 24
Finished Aug 02 05:14:47 PM PDT 24
Peak memory 200248 kb
Host smart-845c29b4-4954-4ee7-bb64-dcb3b48ab8d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605943466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1605943466
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.228627094
Short name T605
Test name
Test status
Simulation time 150898845 ps
CPU time 1.98 seconds
Started Aug 02 05:14:26 PM PDT 24
Finished Aug 02 05:14:28 PM PDT 24
Peak memory 200064 kb
Host smart-721f40c2-32e7-4675-8c3c-f1b689e2c2ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228627094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.228627094
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.677354602
Short name T558
Test name
Test status
Simulation time 1547798361 ps
CPU time 8.21 seconds
Started Aug 02 05:14:45 PM PDT 24
Finished Aug 02 05:14:53 PM PDT 24
Peak memory 200120 kb
Host smart-7f183b4b-685d-4416-9e81-46d53b3e6c4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677354602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.677354602
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2942092503
Short name T542
Test name
Test status
Simulation time 91821831 ps
CPU time 0.83 seconds
Started Aug 02 05:14:29 PM PDT 24
Finished Aug 02 05:14:30 PM PDT 24
Peak memory 200072 kb
Host smart-79442765-d617-4e91-8692-fe0d4f99b2c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942092503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
942092503
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.405858910
Short name T128
Test name
Test status
Simulation time 123859074 ps
CPU time 1.4 seconds
Started Aug 02 05:14:44 PM PDT 24
Finished Aug 02 05:14:45 PM PDT 24
Peak memory 208356 kb
Host smart-64c0a76f-49d1-45b4-9f0b-48bdec799d8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405858910 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.405858910
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.153489353
Short name T589
Test name
Test status
Simulation time 68080299 ps
CPU time 0.76 seconds
Started Aug 02 05:14:36 PM PDT 24
Finished Aug 02 05:14:37 PM PDT 24
Peak memory 200076 kb
Host smart-f7b7d261-4c07-482b-a4ef-84387819ed71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153489353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.153489353
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2835659010
Short name T118
Test name
Test status
Simulation time 147694036 ps
CPU time 1.27 seconds
Started Aug 02 05:14:54 PM PDT 24
Finished Aug 02 05:14:56 PM PDT 24
Peak memory 200100 kb
Host smart-f97acd09-997a-4d28-a7c0-47c7b45e5dab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835659010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2835659010
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.314989837
Short name T615
Test name
Test status
Simulation time 102164290 ps
CPU time 1.32 seconds
Started Aug 02 05:14:22 PM PDT 24
Finished Aug 02 05:14:23 PM PDT 24
Peak memory 208364 kb
Host smart-003f3b84-b5c8-4ee8-addd-0abd560cf5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314989837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.314989837
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.311771185
Short name T124
Test name
Test status
Simulation time 899488877 ps
CPU time 2.8 seconds
Started Aug 02 05:14:26 PM PDT 24
Finished Aug 02 05:14:29 PM PDT 24
Peak memory 200224 kb
Host smart-94d5f0a2-89f3-419e-b86e-5bff4d39058d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311771185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
311771185
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.64272669
Short name T620
Test name
Test status
Simulation time 113987224 ps
CPU time 1.32 seconds
Started Aug 02 05:15:01 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 200204 kb
Host smart-6da19550-54fb-431d-a836-cc0192bbec55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64272669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.64272669
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.583488173
Short name T566
Test name
Test status
Simulation time 1542085291 ps
CPU time 7.86 seconds
Started Aug 02 05:14:35 PM PDT 24
Finished Aug 02 05:14:43 PM PDT 24
Peak memory 200220 kb
Host smart-899934cc-4a68-4939-a20c-ee460ece068f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583488173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.583488173
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3266860994
Short name T555
Test name
Test status
Simulation time 119857517 ps
CPU time 0.87 seconds
Started Aug 02 05:14:37 PM PDT 24
Finished Aug 02 05:14:38 PM PDT 24
Peak memory 200116 kb
Host smart-ec93ee67-3547-40a6-8ac7-0ceb2d1619b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266860994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
266860994
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4115315260
Short name T596
Test name
Test status
Simulation time 158451367 ps
CPU time 1.32 seconds
Started Aug 02 05:14:49 PM PDT 24
Finished Aug 02 05:14:51 PM PDT 24
Peak memory 208336 kb
Host smart-1f43c887-34ee-4de9-9527-45e76214071b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115315260 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.4115315260
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2403371896
Short name T543
Test name
Test status
Simulation time 87953737 ps
CPU time 0.85 seconds
Started Aug 02 05:14:35 PM PDT 24
Finished Aug 02 05:14:36 PM PDT 24
Peak memory 200020 kb
Host smart-68761e81-b119-4b2d-a2bd-5ec2fcc8e8d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403371896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2403371896
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.948418919
Short name T71
Test name
Test status
Simulation time 88278783 ps
CPU time 1.01 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 200092 kb
Host smart-a589c9bd-744c-43d6-9cd2-7153e6819373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948418919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.948418919
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1711648859
Short name T594
Test name
Test status
Simulation time 572079839 ps
CPU time 3.79 seconds
Started Aug 02 05:14:37 PM PDT 24
Finished Aug 02 05:14:41 PM PDT 24
Peak memory 200164 kb
Host smart-4d12110a-7e3e-45d2-a50f-e9b8d1fac7b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711648859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1711648859
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2242960656
Short name T607
Test name
Test status
Simulation time 145649723 ps
CPU time 1.9 seconds
Started Aug 02 05:14:24 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 200080 kb
Host smart-f1ea383d-8c15-460f-a326-02ad2d4fe56d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242960656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
242960656
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3085830423
Short name T563
Test name
Test status
Simulation time 1022324430 ps
CPU time 5.12 seconds
Started Aug 02 05:14:32 PM PDT 24
Finished Aug 02 05:14:37 PM PDT 24
Peak memory 200108 kb
Host smart-c1ea37db-2ffc-40e2-8a25-cf51416708b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085830423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
085830423
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1694662505
Short name T549
Test name
Test status
Simulation time 87237011 ps
CPU time 0.79 seconds
Started Aug 02 05:14:23 PM PDT 24
Finished Aug 02 05:14:24 PM PDT 24
Peak memory 200008 kb
Host smart-766e2fa4-b5ac-4179-ae52-402233904661
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694662505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
694662505
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.683327854
Short name T587
Test name
Test status
Simulation time 193280017 ps
CPU time 1.3 seconds
Started Aug 02 05:14:35 PM PDT 24
Finished Aug 02 05:14:36 PM PDT 24
Peak memory 208376 kb
Host smart-32285233-c15e-481f-acfe-f68c87e6fb5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683327854 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.683327854
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2722860461
Short name T600
Test name
Test status
Simulation time 85457270 ps
CPU time 0.94 seconds
Started Aug 02 05:14:40 PM PDT 24
Finished Aug 02 05:14:41 PM PDT 24
Peak memory 200016 kb
Host smart-13bd55fa-0552-4859-8f5c-92576d51b860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722860461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2722860461
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1676410564
Short name T608
Test name
Test status
Simulation time 162491914 ps
CPU time 1.16 seconds
Started Aug 02 05:14:46 PM PDT 24
Finished Aug 02 05:14:47 PM PDT 24
Peak memory 200192 kb
Host smart-7c73f774-f184-449f-8a1d-5e2be5fb2b09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676410564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1676410564
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.98549114
Short name T552
Test name
Test status
Simulation time 102234067 ps
CPU time 1.36 seconds
Started Aug 02 05:14:40 PM PDT 24
Finished Aug 02 05:14:41 PM PDT 24
Peak memory 208404 kb
Host smart-339b9763-be8b-4ba0-bc33-4f3d7e45c695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98549114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.98549114
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4102288271
Short name T545
Test name
Test status
Simulation time 765420403 ps
CPU time 2.74 seconds
Started Aug 02 05:14:48 PM PDT 24
Finished Aug 02 05:14:51 PM PDT 24
Peak memory 200240 kb
Host smart-62078759-1c9f-49ed-aae4-43c11cd109c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102288271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.4102288271
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2469923303
Short name T551
Test name
Test status
Simulation time 210990740 ps
CPU time 1.41 seconds
Started Aug 02 05:14:43 PM PDT 24
Finished Aug 02 05:14:44 PM PDT 24
Peak memory 208488 kb
Host smart-43ad07b7-9ee2-425c-b45c-0d7a7c1fed7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469923303 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2469923303
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2165272050
Short name T573
Test name
Test status
Simulation time 58364665 ps
CPU time 0.71 seconds
Started Aug 02 05:14:29 PM PDT 24
Finished Aug 02 05:14:30 PM PDT 24
Peak memory 200012 kb
Host smart-aa76af63-2c3a-4592-a882-418fa11b020f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165272050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2165272050
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2931160013
Short name T570
Test name
Test status
Simulation time 80400613 ps
CPU time 0.99 seconds
Started Aug 02 05:14:36 PM PDT 24
Finished Aug 02 05:14:38 PM PDT 24
Peak memory 200056 kb
Host smart-ed012d9f-397f-4992-a36c-02844dbff764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931160013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2931160013
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1560759087
Short name T74
Test name
Test status
Simulation time 244112528 ps
CPU time 1.99 seconds
Started Aug 02 05:14:47 PM PDT 24
Finished Aug 02 05:14:49 PM PDT 24
Peak memory 210772 kb
Host smart-b46e4576-f6c7-40bd-859d-019d377d1f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560759087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1560759087
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.283502577
Short name T585
Test name
Test status
Simulation time 426901170 ps
CPU time 1.83 seconds
Started Aug 02 05:14:44 PM PDT 24
Finished Aug 02 05:14:46 PM PDT 24
Peak memory 200292 kb
Host smart-164cc98c-bb86-4797-a05e-6978f33b4d17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283502577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
283502577
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2373959594
Short name T548
Test name
Test status
Simulation time 207077824 ps
CPU time 1.37 seconds
Started Aug 02 05:14:37 PM PDT 24
Finished Aug 02 05:14:39 PM PDT 24
Peak memory 208264 kb
Host smart-670a63e0-b4ea-40de-9a10-d90c1c5e40f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373959594 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2373959594
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.953162988
Short name T567
Test name
Test status
Simulation time 81533399 ps
CPU time 0.87 seconds
Started Aug 02 05:14:40 PM PDT 24
Finished Aug 02 05:14:41 PM PDT 24
Peak memory 200048 kb
Host smart-b3b98aa0-7a87-467d-a4fa-b0710045f600
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953162988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.953162988
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1482875448
Short name T72
Test name
Test status
Simulation time 83779532 ps
CPU time 1.02 seconds
Started Aug 02 05:14:23 PM PDT 24
Finished Aug 02 05:14:25 PM PDT 24
Peak memory 200148 kb
Host smart-3403b786-5de2-4122-9361-95be3617773f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482875448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1482875448
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.698024739
Short name T614
Test name
Test status
Simulation time 408405253 ps
CPU time 3 seconds
Started Aug 02 05:14:49 PM PDT 24
Finished Aug 02 05:14:52 PM PDT 24
Peak memory 200108 kb
Host smart-cf1a212f-a67d-4785-a656-872f2375fdb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698024739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.698024739
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3136287093
Short name T136
Test name
Test status
Simulation time 524153971 ps
CPU time 1.92 seconds
Started Aug 02 05:14:42 PM PDT 24
Finished Aug 02 05:14:44 PM PDT 24
Peak memory 200272 kb
Host smart-f27d3f95-364b-4225-bd0d-1ac6f475e5ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136287093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3136287093
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2612679529
Short name T97
Test name
Test status
Simulation time 185397974 ps
CPU time 1.19 seconds
Started Aug 02 05:14:31 PM PDT 24
Finished Aug 02 05:14:32 PM PDT 24
Peak memory 208320 kb
Host smart-e5748a47-58bd-425e-9a7a-9423da563c01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612679529 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2612679529
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1614207982
Short name T117
Test name
Test status
Simulation time 86748797 ps
CPU time 0.92 seconds
Started Aug 02 05:14:48 PM PDT 24
Finished Aug 02 05:14:49 PM PDT 24
Peak memory 200148 kb
Host smart-6c01590f-fa55-4763-a6bb-f9b1369df836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614207982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1614207982
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1415178225
Short name T580
Test name
Test status
Simulation time 88494989 ps
CPU time 1.03 seconds
Started Aug 02 05:14:47 PM PDT 24
Finished Aug 02 05:14:48 PM PDT 24
Peak memory 200128 kb
Host smart-05cc2319-b2cc-4129-ad4e-9c6287ce0535
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415178225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1415178225
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3887243354
Short name T575
Test name
Test status
Simulation time 187617282 ps
CPU time 2.77 seconds
Started Aug 02 05:14:35 PM PDT 24
Finished Aug 02 05:14:38 PM PDT 24
Peak memory 216428 kb
Host smart-7648f56b-37ca-4ce5-9998-d1bcc3d03fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887243354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3887243354
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3002572408
Short name T70
Test name
Test status
Simulation time 415661784 ps
CPU time 1.74 seconds
Started Aug 02 05:14:35 PM PDT 24
Finished Aug 02 05:14:37 PM PDT 24
Peak memory 200304 kb
Host smart-c1f56636-9e7c-4b9e-86c3-c315d072b443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002572408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3002572408
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3387548931
Short name T569
Test name
Test status
Simulation time 107661678 ps
CPU time 1.13 seconds
Started Aug 02 05:14:58 PM PDT 24
Finished Aug 02 05:14:59 PM PDT 24
Peak memory 208372 kb
Host smart-3a070b5a-aa57-4d4a-bbda-5c824a285da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387548931 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3387548931
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.264687599
Short name T560
Test name
Test status
Simulation time 72276676 ps
CPU time 0.87 seconds
Started Aug 02 05:14:54 PM PDT 24
Finished Aug 02 05:14:55 PM PDT 24
Peak memory 200088 kb
Host smart-47e0ac73-4ccc-4105-a1d5-b89a054dfd9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264687599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.264687599
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.59599603
Short name T121
Test name
Test status
Simulation time 122078784 ps
CPU time 1.06 seconds
Started Aug 02 05:14:54 PM PDT 24
Finished Aug 02 05:14:55 PM PDT 24
Peak memory 200072 kb
Host smart-e77ea084-dd0f-4677-8832-094761a36792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59599603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same
_csr_outstanding.59599603
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.757798934
Short name T102
Test name
Test status
Simulation time 623917146 ps
CPU time 3.92 seconds
Started Aug 02 05:14:48 PM PDT 24
Finished Aug 02 05:14:52 PM PDT 24
Peak memory 208448 kb
Host smart-e507f05f-91c9-4335-83d7-786b249a69a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757798934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.757798934
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.604133350
Short name T546
Test name
Test status
Simulation time 813787552 ps
CPU time 2.91 seconds
Started Aug 02 05:14:51 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 200200 kb
Host smart-5c8240e3-2987-4969-a589-c7236a142240
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604133350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
604133350
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2869385864
Short name T599
Test name
Test status
Simulation time 92022033 ps
CPU time 0.94 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 200060 kb
Host smart-98cce081-7fc8-4007-a6ed-893023f6bebe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869385864 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2869385864
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3849328591
Short name T547
Test name
Test status
Simulation time 65945231 ps
CPU time 0.76 seconds
Started Aug 02 05:15:00 PM PDT 24
Finished Aug 02 05:15:02 PM PDT 24
Peak memory 200116 kb
Host smart-230f5c41-c9c2-43fe-81a2-629a819c524a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849328591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3849328591
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4252147273
Short name T115
Test name
Test status
Simulation time 209355900 ps
CPU time 1.4 seconds
Started Aug 02 05:15:07 PM PDT 24
Finished Aug 02 05:15:08 PM PDT 24
Peak memory 200196 kb
Host smart-f72b7dc6-6c65-406f-8c82-b91b4448ee0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252147273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.4252147273
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1816353812
Short name T581
Test name
Test status
Simulation time 285529373 ps
CPU time 2.07 seconds
Started Aug 02 05:14:49 PM PDT 24
Finished Aug 02 05:14:51 PM PDT 24
Peak memory 211040 kb
Host smart-91c20ca2-b000-417a-8156-f77e5145952f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816353812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1816353812
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.413613802
Short name T77
Test name
Test status
Simulation time 898868010 ps
CPU time 3.01 seconds
Started Aug 02 05:14:58 PM PDT 24
Finished Aug 02 05:15:01 PM PDT 24
Peak memory 200248 kb
Host smart-999cbe7d-1498-44bf-84fd-b83b337b4198
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413613802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
413613802
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.4270777901
Short name T218
Test name
Test status
Simulation time 75189647 ps
CPU time 0.78 seconds
Started Aug 02 05:16:56 PM PDT 24
Finished Aug 02 05:16:57 PM PDT 24
Peak memory 200208 kb
Host smart-8c6a3992-128d-49e9-8e9c-6e5bc8371b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270777901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4270777901
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.194849317
Short name T486
Test name
Test status
Simulation time 2357256931 ps
CPU time 8.74 seconds
Started Aug 02 05:16:48 PM PDT 24
Finished Aug 02 05:16:58 PM PDT 24
Peak memory 217924 kb
Host smart-af5916d7-ed91-487b-ab6f-7c97ff1f090d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194849317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.194849317
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1366080635
Short name T19
Test name
Test status
Simulation time 245325496 ps
CPU time 0.99 seconds
Started Aug 02 05:16:49 PM PDT 24
Finished Aug 02 05:16:56 PM PDT 24
Peak memory 217608 kb
Host smart-2d1520aa-f99c-4e43-a3ae-d71ce8aa9083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366080635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1366080635
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1702072211
Short name T506
Test name
Test status
Simulation time 183995323 ps
CPU time 0.95 seconds
Started Aug 02 05:16:49 PM PDT 24
Finished Aug 02 05:16:50 PM PDT 24
Peak memory 200172 kb
Host smart-a8439e55-88d0-461d-b30e-222e1d155e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702072211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1702072211
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1563615507
Short name T485
Test name
Test status
Simulation time 1299415097 ps
CPU time 5.44 seconds
Started Aug 02 05:17:13 PM PDT 24
Finished Aug 02 05:17:19 PM PDT 24
Peak memory 200500 kb
Host smart-e0d7d51e-0d47-4711-919b-a888b0b06cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563615507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1563615507
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3003215317
Short name T412
Test name
Test status
Simulation time 163076355 ps
CPU time 1.13 seconds
Started Aug 02 05:16:59 PM PDT 24
Finished Aug 02 05:17:00 PM PDT 24
Peak memory 200372 kb
Host smart-18be1924-ac91-4c40-a0e2-22acfc2feb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003215317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3003215317
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.841784406
Short name T141
Test name
Test status
Simulation time 114855695 ps
CPU time 1.13 seconds
Started Aug 02 05:17:00 PM PDT 24
Finished Aug 02 05:17:01 PM PDT 24
Peak memory 200548 kb
Host smart-3ea17f7a-8a62-4ad6-ac31-8f2c1ab1b3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841784406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.841784406
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3471618079
Short name T519
Test name
Test status
Simulation time 1457752952 ps
CPU time 6.93 seconds
Started Aug 02 05:16:59 PM PDT 24
Finished Aug 02 05:17:06 PM PDT 24
Peak memory 200612 kb
Host smart-1cb55b60-09b9-4a2b-9bdb-676dc73d5d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471618079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3471618079
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3388602521
Short name T206
Test name
Test status
Simulation time 441162079 ps
CPU time 2.2 seconds
Started Aug 02 05:16:52 PM PDT 24
Finished Aug 02 05:16:54 PM PDT 24
Peak memory 208536 kb
Host smart-dd9294e7-582f-4262-b9d8-22e97995e91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388602521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3388602521
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2718547822
Short name T140
Test name
Test status
Simulation time 231456481 ps
CPU time 1.36 seconds
Started Aug 02 05:17:00 PM PDT 24
Finished Aug 02 05:17:02 PM PDT 24
Peak memory 200344 kb
Host smart-66271e70-11ac-4408-b442-3903ae88eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718547822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2718547822
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4097616780
Short name T177
Test name
Test status
Simulation time 65193781 ps
CPU time 0.74 seconds
Started Aug 02 05:17:24 PM PDT 24
Finished Aug 02 05:17:25 PM PDT 24
Peak memory 200212 kb
Host smart-62f36a20-64d7-4967-8f81-4d4aeb8440d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097616780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4097616780
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1254392231
Short name T334
Test name
Test status
Simulation time 244065789 ps
CPU time 1.07 seconds
Started Aug 02 05:16:47 PM PDT 24
Finished Aug 02 05:16:48 PM PDT 24
Peak memory 217448 kb
Host smart-96fd64f2-0df5-4b09-b7bf-a04e0c8a0c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254392231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1254392231
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2751229663
Short name T408
Test name
Test status
Simulation time 148249185 ps
CPU time 0.85 seconds
Started Aug 02 05:16:59 PM PDT 24
Finished Aug 02 05:17:05 PM PDT 24
Peak memory 200148 kb
Host smart-61b4cd27-b77a-42af-8958-08d513d56d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751229663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2751229663
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1889699259
Short name T181
Test name
Test status
Simulation time 998083090 ps
CPU time 4.7 seconds
Started Aug 02 05:17:09 PM PDT 24
Finished Aug 02 05:17:19 PM PDT 24
Peak memory 200584 kb
Host smart-6ce446de-0c54-45f0-9135-0112738f8189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889699259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1889699259
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3567790325
Short name T79
Test name
Test status
Simulation time 8420313442 ps
CPU time 12.4 seconds
Started Aug 02 05:17:12 PM PDT 24
Finished Aug 02 05:17:25 PM PDT 24
Peak memory 217356 kb
Host smart-874f9e61-4e10-40ef-a8ca-a89f8c4df644
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567790325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3567790325
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.720696864
Short name T330
Test name
Test status
Simulation time 170776080 ps
CPU time 1.1 seconds
Started Aug 02 05:17:06 PM PDT 24
Finished Aug 02 05:17:07 PM PDT 24
Peak memory 200372 kb
Host smart-127f92a4-13f5-4067-b5a4-40673cefd7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720696864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.720696864
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1270364024
Short name T215
Test name
Test status
Simulation time 199941246 ps
CPU time 1.44 seconds
Started Aug 02 05:17:23 PM PDT 24
Finished Aug 02 05:17:25 PM PDT 24
Peak memory 200512 kb
Host smart-24e9e62c-a3d7-4865-b553-65a58c11fe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270364024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1270364024
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2416812830
Short name T344
Test name
Test status
Simulation time 6869076613 ps
CPU time 24.11 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:44 PM PDT 24
Peak memory 200644 kb
Host smart-29a85884-9ed5-49e9-9fdd-dad13b0b5fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416812830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2416812830
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2820052530
Short name T212
Test name
Test status
Simulation time 145117406 ps
CPU time 1.76 seconds
Started Aug 02 05:17:23 PM PDT 24
Finished Aug 02 05:17:25 PM PDT 24
Peak memory 200316 kb
Host smart-b207a1df-81ab-40f3-b059-84e9a249a08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820052530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2820052530
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3714902297
Short name T195
Test name
Test status
Simulation time 278496721 ps
CPU time 1.42 seconds
Started Aug 02 05:17:00 PM PDT 24
Finished Aug 02 05:17:02 PM PDT 24
Peak memory 200436 kb
Host smart-58133f9f-315e-4821-a7ef-4cb3091a190a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714902297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3714902297
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3817630979
Short name T49
Test name
Test status
Simulation time 2350877706 ps
CPU time 8.8 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:39 PM PDT 24
Peak memory 221720 kb
Host smart-4416303a-27a7-4d83-9843-2dc25295fdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817630979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3817630979
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.925597667
Short name T419
Test name
Test status
Simulation time 248375134 ps
CPU time 1.03 seconds
Started Aug 02 05:16:52 PM PDT 24
Finished Aug 02 05:16:54 PM PDT 24
Peak memory 217496 kb
Host smart-2ddc67b4-0d63-4f19-baeb-47447411068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925597667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.925597667
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2321903871
Short name T366
Test name
Test status
Simulation time 228023181 ps
CPU time 0.98 seconds
Started Aug 02 05:17:09 PM PDT 24
Finished Aug 02 05:17:10 PM PDT 24
Peak memory 200212 kb
Host smart-e4ecb545-2257-4ffc-9d4e-59b69947b24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321903871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2321903871
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3768713998
Short name T511
Test name
Test status
Simulation time 1540371222 ps
CPU time 5.96 seconds
Started Aug 02 05:17:27 PM PDT 24
Finished Aug 02 05:17:33 PM PDT 24
Peak memory 200440 kb
Host smart-e030df33-6165-4041-a8f6-c63eb37dfc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768713998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3768713998
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1079974429
Short name T416
Test name
Test status
Simulation time 149784484 ps
CPU time 1.03 seconds
Started Aug 02 05:17:03 PM PDT 24
Finished Aug 02 05:17:04 PM PDT 24
Peak memory 200408 kb
Host smart-525652b2-c445-4ed8-996b-a6f4225a0cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079974429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1079974429
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.881544614
Short name T56
Test name
Test status
Simulation time 118231902 ps
CPU time 1.15 seconds
Started Aug 02 05:16:59 PM PDT 24
Finished Aug 02 05:17:00 PM PDT 24
Peak memory 200396 kb
Host smart-2e70fc9f-bc9f-4a01-ae86-b978329fabb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881544614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.881544614
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2922626043
Short name T438
Test name
Test status
Simulation time 6357460436 ps
CPU time 28.41 seconds
Started Aug 02 05:17:02 PM PDT 24
Finished Aug 02 05:17:30 PM PDT 24
Peak memory 200704 kb
Host smart-41fb2040-6788-488d-a10a-e908fe46e13e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922626043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2922626043
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2723601008
Short name T281
Test name
Test status
Simulation time 268072141 ps
CPU time 1.54 seconds
Started Aug 02 05:17:16 PM PDT 24
Finished Aug 02 05:17:17 PM PDT 24
Peak memory 200388 kb
Host smart-35ddd323-1973-4141-9894-c24d9beb5dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723601008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2723601008
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.147113623
Short name T162
Test name
Test status
Simulation time 83536687 ps
CPU time 0.89 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:11 PM PDT 24
Peak memory 200220 kb
Host smart-6bd78647-84a1-4dec-83ce-7328ccdf3b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147113623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.147113623
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1054613947
Short name T340
Test name
Test status
Simulation time 1901887659 ps
CPU time 7.83 seconds
Started Aug 02 05:17:29 PM PDT 24
Finished Aug 02 05:17:36 PM PDT 24
Peak memory 217776 kb
Host smart-27297123-fa26-49a6-80ce-cbcd92e4cc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054613947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1054613947
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2493983650
Short name T226
Test name
Test status
Simulation time 244564710 ps
CPU time 1.08 seconds
Started Aug 02 05:17:32 PM PDT 24
Finished Aug 02 05:17:34 PM PDT 24
Peak memory 217568 kb
Host smart-91f185a9-0e10-4f54-839e-e8270ad6a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493983650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2493983650
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.4031923495
Short name T373
Test name
Test status
Simulation time 104245858 ps
CPU time 0.85 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 200112 kb
Host smart-e4dc8e35-d23a-41e6-bda5-1aaa39cca8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031923495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.4031923495
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2697002400
Short name T202
Test name
Test status
Simulation time 1007029688 ps
CPU time 4.7 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 200528 kb
Host smart-491e7c65-940a-48cf-b85a-7bbfe74f9a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697002400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2697002400
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1724774879
Short name T184
Test name
Test status
Simulation time 153898083 ps
CPU time 1.11 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:16 PM PDT 24
Peak memory 200424 kb
Host smart-98ffe8b7-7ea7-4bca-abb1-7ffce4694596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724774879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1724774879
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3413084825
Short name T264
Test name
Test status
Simulation time 128244235 ps
CPU time 1.2 seconds
Started Aug 02 05:17:17 PM PDT 24
Finished Aug 02 05:17:19 PM PDT 24
Peak memory 200480 kb
Host smart-05bdb0b5-7cb3-4f9f-a929-56f2a735846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413084825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3413084825
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.4124694567
Short name T534
Test name
Test status
Simulation time 8723349518 ps
CPU time 31.11 seconds
Started Aug 02 05:17:02 PM PDT 24
Finished Aug 02 05:17:33 PM PDT 24
Peak memory 200680 kb
Host smart-74058739-f1b5-4416-954d-f2d1c944b29d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124694567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.4124694567
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3019168783
Short name T182
Test name
Test status
Simulation time 143867472 ps
CPU time 1.68 seconds
Started Aug 02 05:17:28 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 200240 kb
Host smart-5cddc107-a4d3-4945-877c-1dd0624f8912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019168783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3019168783
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1351777576
Short name T443
Test name
Test status
Simulation time 64119397 ps
CPU time 0.78 seconds
Started Aug 02 05:16:56 PM PDT 24
Finished Aug 02 05:16:57 PM PDT 24
Peak memory 200356 kb
Host smart-c17e1da3-f559-4d85-8a66-433b0787b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351777576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1351777576
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3747961892
Short name T329
Test name
Test status
Simulation time 72283760 ps
CPU time 0.82 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:16 PM PDT 24
Peak memory 200184 kb
Host smart-06b0b323-1ec5-40f5-8e2d-ec757aaa89fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747961892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3747961892
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1132557189
Short name T473
Test name
Test status
Simulation time 2363090470 ps
CPU time 8.11 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:17:23 PM PDT 24
Peak memory 217884 kb
Host smart-866ee36e-5c7f-4dd8-b906-370043e561d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132557189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1132557189
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.565152725
Short name T496
Test name
Test status
Simulation time 244856852 ps
CPU time 1.02 seconds
Started Aug 02 05:16:55 PM PDT 24
Finished Aug 02 05:16:57 PM PDT 24
Peak memory 217420 kb
Host smart-676da41e-7535-48aa-9091-45641de24c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565152725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.565152725
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1127096247
Short name T284
Test name
Test status
Simulation time 87200780 ps
CPU time 0.77 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 199940 kb
Host smart-3a672bf8-a8d6-4798-a751-12fe70ce73e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127096247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1127096247
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.4076730494
Short name T194
Test name
Test status
Simulation time 854075110 ps
CPU time 4.59 seconds
Started Aug 02 05:17:24 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 200540 kb
Host smart-43681d7d-3ed3-4c0a-9772-0a389c0049e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076730494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.4076730494
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.75778770
Short name T203
Test name
Test status
Simulation time 96864314 ps
CPU time 0.98 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:16 PM PDT 24
Peak memory 200352 kb
Host smart-f762745e-eb6c-4ab7-843c-8149e6921042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75778770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.75778770
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1291200683
Short name T179
Test name
Test status
Simulation time 214148439 ps
CPU time 1.42 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:11 PM PDT 24
Peak memory 200572 kb
Host smart-9ffafb7e-5809-493f-89ab-7bb055a5369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291200683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1291200683
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2753403575
Short name T311
Test name
Test status
Simulation time 8558353034 ps
CPU time 40.31 seconds
Started Aug 02 05:17:19 PM PDT 24
Finished Aug 02 05:18:00 PM PDT 24
Peak memory 200580 kb
Host smart-1373049c-fa7d-4263-b64c-6e93144753bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753403575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2753403575
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.667983485
Short name T387
Test name
Test status
Simulation time 133203471 ps
CPU time 1.6 seconds
Started Aug 02 05:17:17 PM PDT 24
Finished Aug 02 05:17:19 PM PDT 24
Peak memory 208536 kb
Host smart-0e1f5f41-3599-4e1a-a953-ecb52171cfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667983485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.667983485
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2923867800
Short name T16
Test name
Test status
Simulation time 112238048 ps
CPU time 0.95 seconds
Started Aug 02 05:17:33 PM PDT 24
Finished Aug 02 05:17:34 PM PDT 24
Peak memory 200360 kb
Host smart-50078dfe-e55b-472c-a692-5ad97152b507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923867800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2923867800
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.4030863094
Short name T66
Test name
Test status
Simulation time 80079478 ps
CPU time 0.82 seconds
Started Aug 02 05:17:25 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 200032 kb
Host smart-072f8788-871a-408e-ad64-ed03cc5cf0fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030863094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.4030863094
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1501533279
Short name T41
Test name
Test status
Simulation time 1903222180 ps
CPU time 8.24 seconds
Started Aug 02 05:17:04 PM PDT 24
Finished Aug 02 05:17:12 PM PDT 24
Peak memory 217464 kb
Host smart-56647505-d667-4f1c-8d96-c05d642504f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501533279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1501533279
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.203482253
Short name T157
Test name
Test status
Simulation time 244074259 ps
CPU time 1.07 seconds
Started Aug 02 05:17:21 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 217552 kb
Host smart-021cb716-309b-4588-8284-b656988c02f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203482253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.203482253
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.4221528125
Short name T401
Test name
Test status
Simulation time 171034728 ps
CPU time 0.9 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:16 PM PDT 24
Peak memory 200196 kb
Host smart-b6ad5730-5cb7-4dcd-9adb-18978543e8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221528125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.4221528125
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3906444312
Short name T132
Test name
Test status
Simulation time 2267802069 ps
CPU time 7.63 seconds
Started Aug 02 05:17:23 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 200648 kb
Host smart-e391fc6d-94a4-40d8-a5a4-b1326c2856a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906444312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3906444312
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2068026217
Short name T358
Test name
Test status
Simulation time 106778613 ps
CPU time 0.98 seconds
Started Aug 02 05:17:07 PM PDT 24
Finished Aug 02 05:17:08 PM PDT 24
Peak memory 200388 kb
Host smart-2e1f8a81-52c7-49d0-b8e3-7af6a2d81154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068026217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2068026217
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.547776643
Short name T257
Test name
Test status
Simulation time 120408914 ps
CPU time 1.21 seconds
Started Aug 02 05:17:24 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 200464 kb
Host smart-18bf9fcf-97ca-4727-b2f1-cb1b037ec697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547776643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.547776643
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3835720942
Short name T262
Test name
Test status
Simulation time 1245254347 ps
CPU time 5.91 seconds
Started Aug 02 05:16:54 PM PDT 24
Finished Aug 02 05:17:00 PM PDT 24
Peak memory 200616 kb
Host smart-71b72c14-af97-43c2-891e-85c6e46cab65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835720942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3835720942
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2779661451
Short name T161
Test name
Test status
Simulation time 261069036 ps
CPU time 1.8 seconds
Started Aug 02 05:17:23 PM PDT 24
Finished Aug 02 05:17:25 PM PDT 24
Peak memory 200340 kb
Host smart-c42196be-6298-45d0-afdf-6ff37762da0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779661451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2779661451
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.880288835
Short name T160
Test name
Test status
Simulation time 74899453 ps
CPU time 0.87 seconds
Started Aug 02 05:17:11 PM PDT 24
Finished Aug 02 05:17:12 PM PDT 24
Peak memory 200404 kb
Host smart-2c8eed53-3c91-416a-9a63-4a4a0162fbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880288835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.880288835
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2989785776
Short name T298
Test name
Test status
Simulation time 80499571 ps
CPU time 0.81 seconds
Started Aug 02 05:17:08 PM PDT 24
Finished Aug 02 05:17:09 PM PDT 24
Peak memory 200212 kb
Host smart-074b4ee8-38ee-4f72-9cff-1b4dac1742ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989785776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2989785776
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.14446743
Short name T64
Test name
Test status
Simulation time 1223292767 ps
CPU time 5.26 seconds
Started Aug 02 05:17:04 PM PDT 24
Finished Aug 02 05:17:09 PM PDT 24
Peak memory 217160 kb
Host smart-4b7f765e-2056-48a9-acc2-0c1134372beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14446743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.14446743
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.4144962629
Short name T165
Test name
Test status
Simulation time 243443048 ps
CPU time 1.06 seconds
Started Aug 02 05:17:28 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 217416 kb
Host smart-02c2fc28-f52e-4c8b-8141-5d8897a6643d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144962629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.4144962629
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3432523595
Short name T536
Test name
Test status
Simulation time 155083204 ps
CPU time 0.88 seconds
Started Aug 02 05:17:33 PM PDT 24
Finished Aug 02 05:17:34 PM PDT 24
Peak memory 200204 kb
Host smart-49053b47-3761-4d7a-8dd1-6d9a649a4bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432523595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3432523595
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3298748202
Short name T342
Test name
Test status
Simulation time 1574623819 ps
CPU time 5.95 seconds
Started Aug 02 05:17:18 PM PDT 24
Finished Aug 02 05:17:24 PM PDT 24
Peak memory 200612 kb
Host smart-bed2d1de-9c33-42af-a133-85791b44b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298748202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3298748202
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.897598157
Short name T359
Test name
Test status
Simulation time 171279452 ps
CPU time 1.2 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:16 PM PDT 24
Peak memory 200368 kb
Host smart-ba6e3212-551c-489a-9027-2a99f87fd1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897598157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.897598157
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3112586773
Short name T310
Test name
Test status
Simulation time 120157820 ps
CPU time 1.15 seconds
Started Aug 02 05:17:17 PM PDT 24
Finished Aug 02 05:17:18 PM PDT 24
Peak memory 200508 kb
Host smart-e736b5f2-ccb3-4eca-9ef1-d89f630cfab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112586773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3112586773
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.858407158
Short name T147
Test name
Test status
Simulation time 188606445 ps
CPU time 1.19 seconds
Started Aug 02 05:17:02 PM PDT 24
Finished Aug 02 05:17:04 PM PDT 24
Peak memory 200336 kb
Host smart-aa8110a6-0c1e-4905-b7e1-36f7b1aaeefa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858407158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.858407158
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2862077408
Short name T192
Test name
Test status
Simulation time 312781453 ps
CPU time 2.03 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:17 PM PDT 24
Peak memory 200340 kb
Host smart-d54f07e1-1b67-4499-9e26-d592296f7a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862077408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2862077408
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.248014311
Short name T246
Test name
Test status
Simulation time 75442133 ps
CPU time 0.85 seconds
Started Aug 02 05:16:54 PM PDT 24
Finished Aug 02 05:16:55 PM PDT 24
Peak memory 200376 kb
Host smart-191001f8-18cb-40e9-ae1e-53b207ab8ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248014311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.248014311
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1966395012
Short name T111
Test name
Test status
Simulation time 79954168 ps
CPU time 0.79 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:17:20 PM PDT 24
Peak memory 200240 kb
Host smart-841e95b5-d745-4f90-97cf-71ee016826a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966395012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1966395012
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1251314740
Short name T54
Test name
Test status
Simulation time 244498003 ps
CPU time 1.1 seconds
Started Aug 02 05:17:28 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 217400 kb
Host smart-2c277bce-c6bb-4f4c-9165-75ffb171ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251314740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1251314740
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.900242400
Short name T277
Test name
Test status
Simulation time 138772454 ps
CPU time 0.82 seconds
Started Aug 02 05:16:57 PM PDT 24
Finished Aug 02 05:16:58 PM PDT 24
Peak memory 200172 kb
Host smart-2d754c2d-17ed-4a6a-a0dc-483ad18c5cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900242400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.900242400
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2464415964
Short name T531
Test name
Test status
Simulation time 1753001422 ps
CPU time 6.81 seconds
Started Aug 02 05:17:09 PM PDT 24
Finished Aug 02 05:17:16 PM PDT 24
Peak memory 200536 kb
Host smart-d1af7a6f-27cf-4179-8cd1-e62e7b04ed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464415964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2464415964
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2982678479
Short name T500
Test name
Test status
Simulation time 106111629 ps
CPU time 0.95 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 200416 kb
Host smart-370d0faa-d76b-4068-a40f-9850488ba553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982678479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2982678479
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3989606539
Short name T524
Test name
Test status
Simulation time 115373227 ps
CPU time 1.2 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:17:16 PM PDT 24
Peak memory 200476 kb
Host smart-633ec01e-c73f-4137-852f-8ffccbe15695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989606539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3989606539
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.871592698
Short name T447
Test name
Test status
Simulation time 197943450 ps
CPU time 1.26 seconds
Started Aug 02 05:17:24 PM PDT 24
Finished Aug 02 05:17:25 PM PDT 24
Peak memory 200532 kb
Host smart-647f7547-3539-463f-a7e0-bd55f3ec920f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871592698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.871592698
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.917261202
Short name T152
Test name
Test status
Simulation time 367165190 ps
CPU time 2.36 seconds
Started Aug 02 05:17:29 PM PDT 24
Finished Aug 02 05:17:32 PM PDT 24
Peak memory 200320 kb
Host smart-3ad28cb1-0286-4c20-9eff-06e83c20007a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917261202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.917261202
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2984430228
Short name T170
Test name
Test status
Simulation time 269916299 ps
CPU time 1.57 seconds
Started Aug 02 05:17:23 PM PDT 24
Finished Aug 02 05:17:24 PM PDT 24
Peak memory 200304 kb
Host smart-3469dbee-feb8-49b6-8154-b27aded2f49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984430228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2984430228
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4032521652
Short name T287
Test name
Test status
Simulation time 67620165 ps
CPU time 0.75 seconds
Started Aug 02 05:17:26 PM PDT 24
Finished Aug 02 05:17:27 PM PDT 24
Peak memory 200164 kb
Host smart-7933e7b7-a44b-469b-adf9-8cb01fdd715e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032521652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4032521652
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3188619416
Short name T321
Test name
Test status
Simulation time 1894132705 ps
CPU time 7.42 seconds
Started Aug 02 05:17:24 PM PDT 24
Finished Aug 02 05:17:32 PM PDT 24
Peak memory 217648 kb
Host smart-e6e6e328-3b1d-480d-87aa-884b66bfe189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188619416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3188619416
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3775672007
Short name T20
Test name
Test status
Simulation time 244153101 ps
CPU time 1.15 seconds
Started Aug 02 05:17:18 PM PDT 24
Finished Aug 02 05:17:19 PM PDT 24
Peak memory 217416 kb
Host smart-efede1df-e243-49a5-8f03-246ea80d0025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775672007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3775672007
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.672329058
Short name T198
Test name
Test status
Simulation time 118914848 ps
CPU time 0.83 seconds
Started Aug 02 05:17:31 PM PDT 24
Finished Aug 02 05:17:32 PM PDT 24
Peak memory 200144 kb
Host smart-f496eac9-f419-4d74-9de8-bd27dfe728f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672329058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.672329058
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3349160485
Short name T88
Test name
Test status
Simulation time 1593955023 ps
CPU time 5.85 seconds
Started Aug 02 05:17:21 PM PDT 24
Finished Aug 02 05:17:27 PM PDT 24
Peak memory 200540 kb
Host smart-4b90f828-7d31-4802-8f45-3e7d0c359b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349160485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3349160485
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3745346844
Short name T188
Test name
Test status
Simulation time 153828206 ps
CPU time 1.17 seconds
Started Aug 02 05:17:21 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 200380 kb
Host smart-c5d1505a-013b-41c9-bd4e-529afe147ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745346844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3745346844
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1521597304
Short name T319
Test name
Test status
Simulation time 238659845 ps
CPU time 1.38 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 200548 kb
Host smart-25cd6268-686b-474e-8801-ab4b3e3d1b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521597304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1521597304
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1358142186
Short name T454
Test name
Test status
Simulation time 136864946 ps
CPU time 1.72 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 200088 kb
Host smart-2c757664-9a89-4cd7-af9b-78692f2a144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358142186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1358142186
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1106287701
Short name T274
Test name
Test status
Simulation time 140414324 ps
CPU time 1.06 seconds
Started Aug 02 05:17:25 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 200340 kb
Host smart-a8eeffb5-e8f2-4fb6-b201-23b06c788848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106287701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1106287701
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2257324407
Short name T432
Test name
Test status
Simulation time 52358809 ps
CPU time 0.78 seconds
Started Aug 02 05:17:26 PM PDT 24
Finished Aug 02 05:17:27 PM PDT 24
Peak memory 200068 kb
Host smart-6673794a-1e30-4132-ac61-f84fbe55ef99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257324407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2257324407
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2338383472
Short name T394
Test name
Test status
Simulation time 1229074711 ps
CPU time 5.1 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:41 PM PDT 24
Peak memory 217736 kb
Host smart-c2dde44c-e7b1-4ebb-b0aa-5ab76965afa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338383472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2338383472
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.521093971
Short name T537
Test name
Test status
Simulation time 244652721 ps
CPU time 1.07 seconds
Started Aug 02 05:17:22 PM PDT 24
Finished Aug 02 05:17:23 PM PDT 24
Peak memory 217532 kb
Host smart-740cb558-5935-452b-b6c9-ae68147f6512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521093971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.521093971
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2506326374
Short name T444
Test name
Test status
Simulation time 180906484 ps
CPU time 0.88 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 200180 kb
Host smart-c4c15fe5-1df0-433e-bb2e-ee75f84c07f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506326374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2506326374
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.88738983
Short name T105
Test name
Test status
Simulation time 1493051171 ps
CPU time 5.82 seconds
Started Aug 02 05:17:24 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 200540 kb
Host smart-521e3ea6-cb1c-4f33-a8cb-389b734789fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88738983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.88738983
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.575293640
Short name T150
Test name
Test status
Simulation time 140654360 ps
CPU time 1.16 seconds
Started Aug 02 05:17:22 PM PDT 24
Finished Aug 02 05:17:23 PM PDT 24
Peak memory 200376 kb
Host smart-b15b3669-3c39-4ac8-9e84-9385826631e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575293640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.575293640
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.4077960805
Short name T90
Test name
Test status
Simulation time 117862472 ps
CPU time 1.18 seconds
Started Aug 02 05:17:22 PM PDT 24
Finished Aug 02 05:17:23 PM PDT 24
Peak memory 200568 kb
Host smart-c8003dba-bc68-4668-b131-1d1c945cf541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077960805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.4077960805
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.439482975
Short name T108
Test name
Test status
Simulation time 955913430 ps
CPU time 4.34 seconds
Started Aug 02 05:17:31 PM PDT 24
Finished Aug 02 05:17:36 PM PDT 24
Peak memory 200588 kb
Host smart-53b0a8f0-0e28-4e95-9d7f-6b6462497ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439482975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.439482975
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3895129149
Short name T490
Test name
Test status
Simulation time 126234810 ps
CPU time 1.61 seconds
Started Aug 02 05:17:13 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 200376 kb
Host smart-c16aef6a-85db-4004-9e6d-c019b90e2a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895129149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3895129149
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3621079849
Short name T312
Test name
Test status
Simulation time 165318212 ps
CPU time 1.25 seconds
Started Aug 02 05:17:35 PM PDT 24
Finished Aug 02 05:17:36 PM PDT 24
Peak memory 200356 kb
Host smart-1a454006-978a-461f-b9ae-30c6b6c7d675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621079849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3621079849
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1151544966
Short name T435
Test name
Test status
Simulation time 76858087 ps
CPU time 0.78 seconds
Started Aug 02 05:17:21 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 200188 kb
Host smart-f6577e88-ee04-4207-ae9c-b0960157ae05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151544966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1151544966
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1831300680
Short name T390
Test name
Test status
Simulation time 243822933 ps
CPU time 1.06 seconds
Started Aug 02 05:17:25 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 217496 kb
Host smart-507cd427-7025-47f4-b420-98397290e8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831300680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1831300680
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.622762612
Short name T397
Test name
Test status
Simulation time 108523128 ps
CPU time 0.77 seconds
Started Aug 02 05:17:21 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 200100 kb
Host smart-cc873283-327f-4ef5-a071-04d90a328088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622762612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.622762612
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2685277187
Short name T38
Test name
Test status
Simulation time 843082704 ps
CPU time 4.41 seconds
Started Aug 02 05:17:12 PM PDT 24
Finished Aug 02 05:17:17 PM PDT 24
Peak memory 200584 kb
Host smart-b2d0a620-0372-47d8-9359-7646d63037cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685277187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2685277187
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1819147355
Short name T93
Test name
Test status
Simulation time 146623028 ps
CPU time 1.09 seconds
Started Aug 02 05:17:11 PM PDT 24
Finished Aug 02 05:17:12 PM PDT 24
Peak memory 200416 kb
Host smart-86694fbc-3387-4efc-947e-541f257bf40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819147355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1819147355
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.523660977
Short name T159
Test name
Test status
Simulation time 108455249 ps
CPU time 1.2 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 200488 kb
Host smart-c3d76c87-7419-4958-aab7-d577965cfd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523660977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.523660977
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2866622281
Short name T345
Test name
Test status
Simulation time 140995783 ps
CPU time 1.71 seconds
Started Aug 02 05:17:24 PM PDT 24
Finished Aug 02 05:17:30 PM PDT 24
Peak memory 208572 kb
Host smart-19e12358-d5d4-4102-881f-54bb41d0bf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866622281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2866622281
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2057791098
Short name T464
Test name
Test status
Simulation time 201065974 ps
CPU time 1.36 seconds
Started Aug 02 05:17:13 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 200384 kb
Host smart-b59caadf-1152-4056-9234-1f5ed6da3dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057791098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2057791098
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.415231114
Short name T527
Test name
Test status
Simulation time 62866147 ps
CPU time 0.79 seconds
Started Aug 02 05:17:22 PM PDT 24
Finished Aug 02 05:17:23 PM PDT 24
Peak memory 200188 kb
Host smart-0bd96ca1-172b-4335-9762-8399f94dcd07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415231114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.415231114
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3643242942
Short name T328
Test name
Test status
Simulation time 1227757015 ps
CPU time 5.17 seconds
Started Aug 02 05:17:23 PM PDT 24
Finished Aug 02 05:17:28 PM PDT 24
Peak memory 217824 kb
Host smart-5c21f92d-e536-49e4-aefd-63b2a3233b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643242942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3643242942
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.549385324
Short name T414
Test name
Test status
Simulation time 254987761 ps
CPU time 1.03 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 217508 kb
Host smart-16023d63-5cf7-4ae0-861d-1992c8b25d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549385324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.549385324
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1283206940
Short name T395
Test name
Test status
Simulation time 171905361 ps
CPU time 0.85 seconds
Started Aug 02 05:17:26 PM PDT 24
Finished Aug 02 05:17:27 PM PDT 24
Peak memory 200088 kb
Host smart-f7a6628b-2441-4179-a78e-7a01f3d39e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283206940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1283206940
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1999635260
Short name T455
Test name
Test status
Simulation time 1699962096 ps
CPU time 6.62 seconds
Started Aug 02 05:17:27 PM PDT 24
Finished Aug 02 05:17:34 PM PDT 24
Peak memory 200564 kb
Host smart-855a2e50-a306-4598-9d68-257d54aa57c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999635260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1999635260
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2702927018
Short name T429
Test name
Test status
Simulation time 147899962 ps
CPU time 1.1 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 200388 kb
Host smart-01e6a09d-97fe-4fa7-99d3-e62077624a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702927018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2702927018
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1771782045
Short name T521
Test name
Test status
Simulation time 4506783841 ps
CPU time 15.74 seconds
Started Aug 02 05:17:26 PM PDT 24
Finished Aug 02 05:17:42 PM PDT 24
Peak memory 200556 kb
Host smart-8ff5bd2b-f124-4665-a7d8-f4886fcc5ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771782045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1771782045
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1127231437
Short name T305
Test name
Test status
Simulation time 264999412 ps
CPU time 1.85 seconds
Started Aug 02 05:17:24 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 200252 kb
Host smart-ee49f90b-47d7-4d00-8d16-56dd39b895e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127231437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1127231437
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1880246978
Short name T237
Test name
Test status
Simulation time 207414714 ps
CPU time 1.28 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:32 PM PDT 24
Peak memory 200352 kb
Host smart-e930925a-e6c8-44f7-b637-ea2a5f735785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880246978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1880246978
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3809672154
Short name T450
Test name
Test status
Simulation time 66149030 ps
CPU time 0.76 seconds
Started Aug 02 05:16:52 PM PDT 24
Finished Aug 02 05:16:53 PM PDT 24
Peak memory 200184 kb
Host smart-f30fdc91-f240-4c65-be38-a2a7f45f9181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809672154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3809672154
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3811492915
Short name T481
Test name
Test status
Simulation time 1883084539 ps
CPU time 7.81 seconds
Started Aug 02 05:17:17 PM PDT 24
Finished Aug 02 05:17:25 PM PDT 24
Peak memory 217768 kb
Host smart-29933ade-d012-430f-bb63-6640833af297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811492915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3811492915
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.362079794
Short name T520
Test name
Test status
Simulation time 245901231 ps
CPU time 1.11 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 217624 kb
Host smart-c4e565e6-d4ec-45e5-802d-786363235f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362079794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.362079794
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.380715370
Short name T265
Test name
Test status
Simulation time 123373762 ps
CPU time 0.85 seconds
Started Aug 02 05:17:27 PM PDT 24
Finished Aug 02 05:17:28 PM PDT 24
Peak memory 200184 kb
Host smart-04da18f1-8b46-4e65-8b92-2e061f91ccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380715370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.380715370
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.4116451067
Short name T417
Test name
Test status
Simulation time 1919870157 ps
CPU time 6.55 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 200600 kb
Host smart-60d8ad44-05a2-41a2-9834-3688a0803e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116451067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.4116451067
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3279052496
Short name T80
Test name
Test status
Simulation time 9217441292 ps
CPU time 13.56 seconds
Started Aug 02 05:17:03 PM PDT 24
Finished Aug 02 05:17:17 PM PDT 24
Peak memory 217264 kb
Host smart-0c20d1b4-7cb5-47b5-89f3-23ac2a9cafcf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279052496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3279052496
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3854476874
Short name T225
Test name
Test status
Simulation time 98496214 ps
CPU time 0.99 seconds
Started Aug 02 05:17:18 PM PDT 24
Finished Aug 02 05:17:19 PM PDT 24
Peak memory 200372 kb
Host smart-6c212767-bfb0-4f47-a259-57f205e406c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854476874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3854476874
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3017583394
Short name T52
Test name
Test status
Simulation time 108523715 ps
CPU time 1.16 seconds
Started Aug 02 05:17:17 PM PDT 24
Finished Aug 02 05:17:18 PM PDT 24
Peak memory 200544 kb
Host smart-336acbf6-eef6-430a-b286-f63ec2eea74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017583394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3017583394
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.104273934
Short name T336
Test name
Test status
Simulation time 10464779784 ps
CPU time 34.78 seconds
Started Aug 02 05:16:48 PM PDT 24
Finished Aug 02 05:17:23 PM PDT 24
Peak memory 200648 kb
Host smart-765d3791-fb37-48d7-b086-5dd5ae56a010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104273934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.104273934
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2347254689
Short name T174
Test name
Test status
Simulation time 291375059 ps
CPU time 1.95 seconds
Started Aug 02 05:16:55 PM PDT 24
Finished Aug 02 05:16:57 PM PDT 24
Peak memory 208512 kb
Host smart-8e21922f-9fc7-4b9d-97c2-d8f1944f5dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347254689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2347254689
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3620675993
Short name T167
Test name
Test status
Simulation time 75040909 ps
CPU time 0.85 seconds
Started Aug 02 05:17:11 PM PDT 24
Finished Aug 02 05:17:12 PM PDT 24
Peak memory 200280 kb
Host smart-8dc868d0-cb88-46ab-8f80-954d36534d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620675993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3620675993
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2675533822
Short name T183
Test name
Test status
Simulation time 75485908 ps
CPU time 0.81 seconds
Started Aug 02 05:17:24 PM PDT 24
Finished Aug 02 05:17:25 PM PDT 24
Peak memory 200184 kb
Host smart-aee6844c-3d04-4374-8885-b1228bf91bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675533822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2675533822
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2239936437
Short name T499
Test name
Test status
Simulation time 1911339791 ps
CPU time 7.91 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 220936 kb
Host smart-0f435f52-00fe-4842-93fa-2637d53acb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239936437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2239936437
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2806682450
Short name T146
Test name
Test status
Simulation time 245246190 ps
CPU time 1.02 seconds
Started Aug 02 05:17:27 PM PDT 24
Finished Aug 02 05:17:28 PM PDT 24
Peak memory 217532 kb
Host smart-f6d3a084-8eee-4d7d-b991-369c03765d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806682450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2806682450
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1932353607
Short name T316
Test name
Test status
Simulation time 242940080 ps
CPU time 0.91 seconds
Started Aug 02 05:17:28 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 200168 kb
Host smart-fb560e31-91b7-4917-9838-825c66f6e907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932353607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1932353607
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3528423446
Short name T383
Test name
Test status
Simulation time 1266114819 ps
CPU time 5.48 seconds
Started Aug 02 05:17:26 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 200508 kb
Host smart-7ec3f731-05ce-40e4-8e5a-e1107f153923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528423446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3528423446
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3511643189
Short name T139
Test name
Test status
Simulation time 114022202 ps
CPU time 1.07 seconds
Started Aug 02 05:17:28 PM PDT 24
Finished Aug 02 05:17:30 PM PDT 24
Peak memory 200364 kb
Host smart-4cad5864-fabd-41c9-a97f-6b37a465d28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511643189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3511643189
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3406429338
Short name T199
Test name
Test status
Simulation time 124534560 ps
CPU time 1.18 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:16 PM PDT 24
Peak memory 200492 kb
Host smart-c5a28c1a-c4fe-479c-873d-f68a9d8ed503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406429338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3406429338
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.130324710
Short name T436
Test name
Test status
Simulation time 5653032261 ps
CPU time 19.76 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:40 PM PDT 24
Peak memory 200592 kb
Host smart-d3215335-4b86-450d-a81b-d5ba785904e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130324710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.130324710
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.4200656841
Short name T197
Test name
Test status
Simulation time 367494489 ps
CPU time 2.45 seconds
Started Aug 02 05:17:27 PM PDT 24
Finished Aug 02 05:17:30 PM PDT 24
Peak memory 200296 kb
Host smart-0e1c2f67-b832-4033-b3a5-6487660849f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200656841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.4200656841
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2712535163
Short name T89
Test name
Test status
Simulation time 73329609 ps
CPU time 0.77 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 200152 kb
Host smart-c69bb90e-aa2a-4970-9ebf-a50a26a541fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712535163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2712535163
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1150644838
Short name T267
Test name
Test status
Simulation time 1887045541 ps
CPU time 7.31 seconds
Started Aug 02 05:17:19 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 217512 kb
Host smart-792bc8ca-68fe-4d33-82a3-de04c56d5a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150644838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1150644838
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3970794830
Short name T238
Test name
Test status
Simulation time 244372026 ps
CPU time 1.01 seconds
Started Aug 02 05:17:39 PM PDT 24
Finished Aug 02 05:17:40 PM PDT 24
Peak memory 217460 kb
Host smart-9bf551f0-5364-4940-b639-0eafd1bf2d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970794830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3970794830
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2908714292
Short name T368
Test name
Test status
Simulation time 179318925 ps
CPU time 0.95 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:37 PM PDT 24
Peak memory 200144 kb
Host smart-3d2e5e1e-2790-4162-b3cc-42545b00e3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908714292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2908714292
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3669687543
Short name T398
Test name
Test status
Simulation time 588210640 ps
CPU time 3.48 seconds
Started Aug 02 05:17:40 PM PDT 24
Finished Aug 02 05:17:44 PM PDT 24
Peak memory 200572 kb
Host smart-9442a2ce-2a8b-473d-b4b1-312cb7e342a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669687543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3669687543
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2908489957
Short name T352
Test name
Test status
Simulation time 99480314 ps
CPU time 1.02 seconds
Started Aug 02 05:17:39 PM PDT 24
Finished Aug 02 05:17:40 PM PDT 24
Peak memory 200348 kb
Host smart-977b8c73-5aa2-4d74-8280-daf4acb96ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908489957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2908489957
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2247292542
Short name T231
Test name
Test status
Simulation time 191732814 ps
CPU time 1.36 seconds
Started Aug 02 05:17:33 PM PDT 24
Finished Aug 02 05:17:34 PM PDT 24
Peak memory 200460 kb
Host smart-36bdccd0-872f-4bb4-822c-792718b1a2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247292542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2247292542
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2211091224
Short name T374
Test name
Test status
Simulation time 1073878867 ps
CPU time 4.74 seconds
Started Aug 02 05:17:21 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 200508 kb
Host smart-321aed42-f335-48f4-95c0-74d864293293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211091224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2211091224
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2629245065
Short name T221
Test name
Test status
Simulation time 124239495 ps
CPU time 1.63 seconds
Started Aug 02 05:17:34 PM PDT 24
Finished Aug 02 05:17:36 PM PDT 24
Peak memory 208524 kb
Host smart-0f104ce1-04b1-4753-93ab-f26e0f571ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629245065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2629245065
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3642309838
Short name T404
Test name
Test status
Simulation time 78940407 ps
CPU time 0.84 seconds
Started Aug 02 05:17:31 PM PDT 24
Finished Aug 02 05:17:32 PM PDT 24
Peak memory 200340 kb
Host smart-a418666a-8937-4f84-9d9d-46383924e5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642309838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3642309838
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1441069405
Short name T278
Test name
Test status
Simulation time 72652438 ps
CPU time 0.77 seconds
Started Aug 02 05:17:28 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 200248 kb
Host smart-4c0f4246-55a3-4316-a329-898bed8118c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441069405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1441069405
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.769633563
Short name T44
Test name
Test status
Simulation time 1886554901 ps
CPU time 7.11 seconds
Started Aug 02 05:17:43 PM PDT 24
Finished Aug 02 05:17:50 PM PDT 24
Peak memory 221708 kb
Host smart-5b921358-057c-49d8-8df2-37049c702d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769633563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.769633563
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2613896199
Short name T240
Test name
Test status
Simulation time 244276441 ps
CPU time 1.1 seconds
Started Aug 02 05:17:24 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 217476 kb
Host smart-9e5aeb5f-4488-4112-a13c-b68c2940f68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613896199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2613896199
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2537340063
Short name T196
Test name
Test status
Simulation time 1506666778 ps
CPU time 6.4 seconds
Started Aug 02 05:17:25 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 200508 kb
Host smart-3233c36c-a52f-4fb2-ae38-d51db3feff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537340063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2537340063
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.262775500
Short name T346
Test name
Test status
Simulation time 146113368 ps
CPU time 1.13 seconds
Started Aug 02 05:17:35 PM PDT 24
Finished Aug 02 05:17:36 PM PDT 24
Peak memory 200348 kb
Host smart-776d29e9-7867-4168-afe6-5dd4ea1de700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262775500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.262775500
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3729473730
Short name T222
Test name
Test status
Simulation time 199481497 ps
CPU time 1.38 seconds
Started Aug 02 05:17:25 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 200528 kb
Host smart-52d0e9d6-1724-41e7-964a-75275a496974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729473730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3729473730
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3177401139
Short name T495
Test name
Test status
Simulation time 438319604 ps
CPU time 2.06 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:38 PM PDT 24
Peak memory 200560 kb
Host smart-c1f05c59-7f7d-41f6-8604-9b190bbb4776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177401139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3177401139
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2191551629
Short name T517
Test name
Test status
Simulation time 116123197 ps
CPU time 1.47 seconds
Started Aug 02 05:17:25 PM PDT 24
Finished Aug 02 05:17:27 PM PDT 24
Peak memory 200344 kb
Host smart-4b1429af-7455-4a7c-b8a8-6acaa158685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191551629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2191551629
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3239460383
Short name T189
Test name
Test status
Simulation time 93617098 ps
CPU time 0.94 seconds
Started Aug 02 05:17:32 PM PDT 24
Finished Aug 02 05:17:33 PM PDT 24
Peak memory 200420 kb
Host smart-03738a77-60ed-4444-a26c-4ce123ff6f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239460383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3239460383
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1897497207
Short name T263
Test name
Test status
Simulation time 60902857 ps
CPU time 0.76 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 200212 kb
Host smart-0930857c-2ee2-4f2d-a1e6-98f555b9deac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897497207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1897497207
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3839667262
Short name T48
Test name
Test status
Simulation time 1232624525 ps
CPU time 5.42 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:35 PM PDT 24
Peak memory 217396 kb
Host smart-7613cfd7-c3e9-492f-a100-12ab71c71279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839667262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3839667262
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2949283258
Short name T279
Test name
Test status
Simulation time 243988059 ps
CPU time 1.03 seconds
Started Aug 02 05:17:26 PM PDT 24
Finished Aug 02 05:17:27 PM PDT 24
Peak memory 217576 kb
Host smart-20fac800-eb56-444e-8be4-f2c98d3738df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949283258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2949283258
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1527394859
Short name T338
Test name
Test status
Simulation time 163660975 ps
CPU time 0.84 seconds
Started Aug 02 05:17:26 PM PDT 24
Finished Aug 02 05:17:27 PM PDT 24
Peak memory 200136 kb
Host smart-9ca2a4e6-7fcc-4d19-9453-aab53399f209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527394859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1527394859
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2027559019
Short name T269
Test name
Test status
Simulation time 1865344247 ps
CPU time 6.28 seconds
Started Aug 02 05:17:42 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 200588 kb
Host smart-d6823d86-fa2a-4ab9-9003-db65d2471434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027559019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2027559019
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.858288662
Short name T434
Test name
Test status
Simulation time 146583437 ps
CPU time 1.13 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 200384 kb
Host smart-c0df8707-6337-4a7f-b381-30bedb27d781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858288662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.858288662
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3864098679
Short name T405
Test name
Test status
Simulation time 197992432 ps
CPU time 1.38 seconds
Started Aug 02 05:17:27 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 200544 kb
Host smart-43128caa-c5eb-4fbd-b5ed-f11ca5a3db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864098679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3864098679
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.687029526
Short name T301
Test name
Test status
Simulation time 2527265235 ps
CPU time 11.63 seconds
Started Aug 02 05:17:25 PM PDT 24
Finished Aug 02 05:17:36 PM PDT 24
Peak memory 200564 kb
Host smart-6d55942e-409e-4f01-84f9-f64554d525f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687029526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.687029526
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.595889836
Short name T214
Test name
Test status
Simulation time 449279895 ps
CPU time 2.45 seconds
Started Aug 02 05:17:27 PM PDT 24
Finished Aug 02 05:17:30 PM PDT 24
Peak memory 200324 kb
Host smart-990cd4dc-fbe1-4f3c-b974-a13d69e07a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595889836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.595889836
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3965184100
Short name T245
Test name
Test status
Simulation time 87574404 ps
CPU time 0.84 seconds
Started Aug 02 05:17:31 PM PDT 24
Finished Aug 02 05:17:32 PM PDT 24
Peak memory 200344 kb
Host smart-ee795519-732f-45fb-a6ee-3b047fd07176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965184100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3965184100
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2520231569
Short name T200
Test name
Test status
Simulation time 66027386 ps
CPU time 0.74 seconds
Started Aug 02 05:17:28 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 200128 kb
Host smart-5f7d14be-0982-4b0b-b168-f2b302e240f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520231569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2520231569
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2217171465
Short name T295
Test name
Test status
Simulation time 1229120574 ps
CPU time 5.49 seconds
Started Aug 02 05:17:43 PM PDT 24
Finished Aug 02 05:17:48 PM PDT 24
Peak memory 217744 kb
Host smart-1a3d75e5-56c3-489a-b337-3b2dce81b4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217171465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2217171465
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.986073216
Short name T300
Test name
Test status
Simulation time 244788107 ps
CPU time 1.05 seconds
Started Aug 02 05:17:28 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 217412 kb
Host smart-9a65cf3f-72a1-4f10-83e5-c95823b81805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986073216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.986073216
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3930763457
Short name T385
Test name
Test status
Simulation time 225824635 ps
CPU time 0.97 seconds
Started Aug 02 05:17:33 PM PDT 24
Finished Aug 02 05:17:34 PM PDT 24
Peak memory 200200 kb
Host smart-238a3266-a82c-41bf-b7f0-891628c14c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930763457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3930763457
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3079659080
Short name T171
Test name
Test status
Simulation time 1024340205 ps
CPU time 4.83 seconds
Started Aug 02 05:17:28 PM PDT 24
Finished Aug 02 05:17:33 PM PDT 24
Peak memory 200604 kb
Host smart-7b054f33-fa08-479b-9a02-9cb4083d4782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079659080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3079659080
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2602640455
Short name T457
Test name
Test status
Simulation time 115621842 ps
CPU time 1.22 seconds
Started Aug 02 05:17:33 PM PDT 24
Finished Aug 02 05:17:34 PM PDT 24
Peak memory 200564 kb
Host smart-121d3e17-29f2-4ebc-ab96-3dee42be13a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602640455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2602640455
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1573517085
Short name T110
Test name
Test status
Simulation time 3764688653 ps
CPU time 17.58 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:54 PM PDT 24
Peak memory 208812 kb
Host smart-e67a7735-ddad-4abf-9eac-8e5979baf40d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573517085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1573517085
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2571758370
Short name T11
Test name
Test status
Simulation time 369367244 ps
CPU time 2.31 seconds
Started Aug 02 05:17:31 PM PDT 24
Finished Aug 02 05:17:33 PM PDT 24
Peak memory 200320 kb
Host smart-57aefbda-fbc8-4bb3-8c9b-f89c4ea0f080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571758370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2571758370
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2235600720
Short name T356
Test name
Test status
Simulation time 187991522 ps
CPU time 1.18 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 200356 kb
Host smart-e91cf842-6cea-409c-91e3-99929642a54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235600720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2235600720
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3382724414
Short name T406
Test name
Test status
Simulation time 88234210 ps
CPU time 0.86 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 200104 kb
Host smart-e10ca4ee-3052-4743-bcdd-205f1b1737b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382724414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3382724414
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1236791062
Short name T470
Test name
Test status
Simulation time 1227174850 ps
CPU time 5.77 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:18:01 PM PDT 24
Peak memory 217728 kb
Host smart-52964a51-8ebc-48cf-9c9e-3a52c3c4ebb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236791062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1236791062
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1709501168
Short name T384
Test name
Test status
Simulation time 244328249 ps
CPU time 1.04 seconds
Started Aug 02 05:17:35 PM PDT 24
Finished Aug 02 05:17:36 PM PDT 24
Peak memory 217532 kb
Host smart-db51e111-95db-4990-bd85-6aafd562cbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709501168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1709501168
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3372884897
Short name T502
Test name
Test status
Simulation time 216405612 ps
CPU time 0.89 seconds
Started Aug 02 05:17:38 PM PDT 24
Finished Aug 02 05:17:39 PM PDT 24
Peak memory 200092 kb
Host smart-22c85d5c-fbaa-4d9d-b01e-4d362c24f209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372884897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3372884897
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1099768958
Short name T480
Test name
Test status
Simulation time 857203893 ps
CPU time 4.29 seconds
Started Aug 02 05:17:31 PM PDT 24
Finished Aug 02 05:17:35 PM PDT 24
Peak memory 200576 kb
Host smart-8066820a-029b-453e-8583-67d5b6d9a7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099768958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1099768958
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.840726762
Short name T361
Test name
Test status
Simulation time 145830161 ps
CPU time 1.07 seconds
Started Aug 02 05:17:41 PM PDT 24
Finished Aug 02 05:17:42 PM PDT 24
Peak memory 200412 kb
Host smart-0054e191-38ca-43e9-addd-c57acfca1074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840726762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.840726762
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.213215185
Short name T439
Test name
Test status
Simulation time 205248262 ps
CPU time 1.47 seconds
Started Aug 02 05:17:43 PM PDT 24
Finished Aug 02 05:17:44 PM PDT 24
Peak memory 200488 kb
Host smart-6a8805ba-a518-4caf-9509-b488a2bca5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213215185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.213215185
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1027768343
Short name T341
Test name
Test status
Simulation time 12773721428 ps
CPU time 45.12 seconds
Started Aug 02 05:17:41 PM PDT 24
Finished Aug 02 05:18:26 PM PDT 24
Peak memory 208876 kb
Host smart-27648615-3b9f-47a2-9282-c511b49eaa82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027768343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1027768343
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.546037817
Short name T365
Test name
Test status
Simulation time 129583350 ps
CPU time 1.6 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:48 PM PDT 24
Peak memory 200312 kb
Host smart-00f39612-a794-4682-b43b-d545af10d1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546037817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.546037817
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.570005360
Short name T463
Test name
Test status
Simulation time 266084553 ps
CPU time 1.4 seconds
Started Aug 02 05:17:51 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 200320 kb
Host smart-075e8039-42a7-4854-828e-3dfa67364ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570005360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.570005360
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2902290832
Short name T87
Test name
Test status
Simulation time 71121791 ps
CPU time 0.8 seconds
Started Aug 02 05:17:35 PM PDT 24
Finished Aug 02 05:17:36 PM PDT 24
Peak memory 200156 kb
Host smart-15bea7b0-1973-475f-aa5e-3f2ef974b3bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902290832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2902290832
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3596083097
Short name T63
Test name
Test status
Simulation time 1234364597 ps
CPU time 5.32 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:17:54 PM PDT 24
Peak memory 217792 kb
Host smart-07ab5c16-373b-4b6c-9451-4fca4547a171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596083097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3596083097
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.841806631
Short name T172
Test name
Test status
Simulation time 243779203 ps
CPU time 1.15 seconds
Started Aug 02 05:17:42 PM PDT 24
Finished Aug 02 05:17:44 PM PDT 24
Peak memory 217504 kb
Host smart-f05540f4-c515-4622-b9ee-46df7871745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841806631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.841806631
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1735882718
Short name T431
Test name
Test status
Simulation time 142613599 ps
CPU time 0.81 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:17:56 PM PDT 24
Peak memory 200164 kb
Host smart-bad0e59c-6c71-46d3-977c-d62468d08cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735882718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1735882718
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1550422372
Short name T339
Test name
Test status
Simulation time 881948544 ps
CPU time 3.94 seconds
Started Aug 02 05:17:51 PM PDT 24
Finished Aug 02 05:17:55 PM PDT 24
Peak memory 200552 kb
Host smart-8fd85e78-3d46-47d5-a75e-ceb1a3b3fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550422372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1550422372
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3218815629
Short name T353
Test name
Test status
Simulation time 103189469 ps
CPU time 0.96 seconds
Started Aug 02 05:17:39 PM PDT 24
Finished Aug 02 05:17:40 PM PDT 24
Peak memory 200408 kb
Host smart-bc035c66-620f-4cdd-a75b-88583c659b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218815629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3218815629
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1372854285
Short name T258
Test name
Test status
Simulation time 118327679 ps
CPU time 1.21 seconds
Started Aug 02 05:18:02 PM PDT 24
Finished Aug 02 05:18:04 PM PDT 24
Peak memory 200560 kb
Host smart-3282b3e4-4895-4249-8dc7-6a3d83d0c9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372854285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1372854285
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.180438487
Short name T386
Test name
Test status
Simulation time 9199560837 ps
CPU time 32.51 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:18:17 PM PDT 24
Peak memory 208868 kb
Host smart-307943f5-9de6-48e0-a346-dfbf0a3f2d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180438487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.180438487
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2860294160
Short name T355
Test name
Test status
Simulation time 127526804 ps
CPU time 1.55 seconds
Started Aug 02 05:17:37 PM PDT 24
Finished Aug 02 05:17:39 PM PDT 24
Peak memory 208584 kb
Host smart-d5b7d789-16e3-465a-8c70-ed9d44816a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860294160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2860294160
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3291160989
Short name T213
Test name
Test status
Simulation time 235581825 ps
CPU time 1.41 seconds
Started Aug 02 05:18:10 PM PDT 24
Finished Aug 02 05:18:12 PM PDT 24
Peak memory 200380 kb
Host smart-689e8aef-a2b9-49b8-b676-df810aad76a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291160989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3291160989
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.142483698
Short name T324
Test name
Test status
Simulation time 77534085 ps
CPU time 0.78 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:17:45 PM PDT 24
Peak memory 200160 kb
Host smart-ea283409-27df-46e2-b5a9-57322c2dcef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142483698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.142483698
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1024300599
Short name T377
Test name
Test status
Simulation time 2353878425 ps
CPU time 8.31 seconds
Started Aug 02 05:17:38 PM PDT 24
Finished Aug 02 05:17:46 PM PDT 24
Peak memory 217912 kb
Host smart-71608486-e134-4aa1-a14d-f371b25849b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024300599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1024300599
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3271344299
Short name T413
Test name
Test status
Simulation time 245082509 ps
CPU time 1.08 seconds
Started Aug 02 05:17:37 PM PDT 24
Finished Aug 02 05:17:38 PM PDT 24
Peak memory 217552 kb
Host smart-6926763f-9944-4d5e-997c-554af6b03ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271344299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3271344299
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2623176276
Short name T313
Test name
Test status
Simulation time 108369006 ps
CPU time 0.85 seconds
Started Aug 02 05:17:38 PM PDT 24
Finished Aug 02 05:17:39 PM PDT 24
Peak memory 200196 kb
Host smart-17e1d127-b0b7-4ba1-ae8b-d09b380f054b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623176276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2623176276
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.4151120830
Short name T14
Test name
Test status
Simulation time 679043410 ps
CPU time 3.57 seconds
Started Aug 02 05:17:35 PM PDT 24
Finished Aug 02 05:17:39 PM PDT 24
Peak memory 200536 kb
Host smart-3d4b4df2-f0e6-499b-b199-e9f5ecdae65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151120830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4151120830
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1336377409
Short name T367
Test name
Test status
Simulation time 144189759 ps
CPU time 1.04 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:47 PM PDT 24
Peak memory 200364 kb
Host smart-3d6554e9-7417-4fee-a72c-30884238600c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336377409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1336377409
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2953550192
Short name T249
Test name
Test status
Simulation time 253578669 ps
CPU time 1.62 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:37 PM PDT 24
Peak memory 200576 kb
Host smart-0c7daec2-4885-49cb-88ca-63dce8afde62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953550192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2953550192
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3274332926
Short name T389
Test name
Test status
Simulation time 7830644683 ps
CPU time 26.43 seconds
Started Aug 02 05:17:38 PM PDT 24
Finished Aug 02 05:18:04 PM PDT 24
Peak memory 208848 kb
Host smart-fbd07aa4-597d-4a45-bd2b-314fceb2e987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274332926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3274332926
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.4269055769
Short name T314
Test name
Test status
Simulation time 160444371 ps
CPU time 1.83 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:17:45 PM PDT 24
Peak memory 200344 kb
Host smart-501480f9-4730-4292-a303-59a22e13898f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269055769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4269055769
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2129616822
Short name T2
Test name
Test status
Simulation time 153610004 ps
CPU time 1.05 seconds
Started Aug 02 05:17:42 PM PDT 24
Finished Aug 02 05:17:44 PM PDT 24
Peak memory 200364 kb
Host smart-32edbc38-8fa1-412f-a146-488fb1466ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129616822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2129616822
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2242313842
Short name T494
Test name
Test status
Simulation time 83496101 ps
CPU time 0.85 seconds
Started Aug 02 05:17:37 PM PDT 24
Finished Aug 02 05:17:38 PM PDT 24
Peak memory 200156 kb
Host smart-1a4c408e-fa28-432e-9009-54887037fe6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242313842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2242313842
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4179749036
Short name T357
Test name
Test status
Simulation time 2385139212 ps
CPU time 8.55 seconds
Started Aug 02 05:17:34 PM PDT 24
Finished Aug 02 05:17:43 PM PDT 24
Peak memory 221828 kb
Host smart-5aed636a-3d60-4725-9f6b-a01fb16e3279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179749036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.4179749036
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.762598034
Short name T224
Test name
Test status
Simulation time 249952812 ps
CPU time 1.03 seconds
Started Aug 02 05:17:34 PM PDT 24
Finished Aug 02 05:17:35 PM PDT 24
Peak memory 217492 kb
Host smart-955831aa-a9d9-4a70-b915-b927f2c1020e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762598034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.762598034
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1372965174
Short name T275
Test name
Test status
Simulation time 231958468 ps
CPU time 0.97 seconds
Started Aug 02 05:18:09 PM PDT 24
Finished Aug 02 05:18:11 PM PDT 24
Peak memory 200132 kb
Host smart-44b97b1e-2645-46bb-98bb-512d4dbcbcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372965174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1372965174
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1836607106
Short name T92
Test name
Test status
Simulation time 839700539 ps
CPU time 4.09 seconds
Started Aug 02 05:17:43 PM PDT 24
Finished Aug 02 05:17:48 PM PDT 24
Peak memory 200580 kb
Host smart-302f012b-922b-4426-a506-6e3762c47167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836607106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1836607106
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2303717673
Short name T35
Test name
Test status
Simulation time 156997825 ps
CPU time 1.19 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:37 PM PDT 24
Peak memory 200344 kb
Host smart-66ba3c7c-d121-4ab4-8bad-68c9bbf847fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303717673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2303717673
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.334015683
Short name T82
Test name
Test status
Simulation time 120990513 ps
CPU time 1.2 seconds
Started Aug 02 05:17:43 PM PDT 24
Finished Aug 02 05:17:45 PM PDT 24
Peak memory 200536 kb
Host smart-cdc9376b-b1f3-43ef-9229-5a5dc119db5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334015683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.334015683
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3042080972
Short name T323
Test name
Test status
Simulation time 2868682438 ps
CPU time 13.4 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:17:57 PM PDT 24
Peak memory 208828 kb
Host smart-f4e37eea-6125-4052-8a0b-ae84b86c3634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042080972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3042080972
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.694975173
Short name T3
Test name
Test status
Simulation time 140913578 ps
CPU time 1.71 seconds
Started Aug 02 05:17:34 PM PDT 24
Finished Aug 02 05:17:35 PM PDT 24
Peak memory 200324 kb
Host smart-5f4ed09c-b415-4342-9c06-8a1a6dddf522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694975173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.694975173
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.446282802
Short name T175
Test name
Test status
Simulation time 113611017 ps
CPU time 1.01 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:37 PM PDT 24
Peak memory 200344 kb
Host smart-e1deaf12-9d58-4913-95cf-44efa6ddaaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446282802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.446282802
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1614090500
Short name T9
Test name
Test status
Simulation time 76314615 ps
CPU time 0.88 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:17:51 PM PDT 24
Peak memory 200208 kb
Host smart-a9c1446f-4e10-4bf7-b221-cdc47790d380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614090500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1614090500
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3550292371
Short name T62
Test name
Test status
Simulation time 2390467651 ps
CPU time 7.88 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:18:01 PM PDT 24
Peak memory 217916 kb
Host smart-d49a841f-d2fb-4cd1-a5a2-97c1dc1e4651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550292371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3550292371
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1889623978
Short name T445
Test name
Test status
Simulation time 245071077 ps
CPU time 1.06 seconds
Started Aug 02 05:17:37 PM PDT 24
Finished Aug 02 05:17:38 PM PDT 24
Peak memory 217580 kb
Host smart-a451044c-5129-4f3d-a935-5e64232aa073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889623978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1889623978
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3692615371
Short name T282
Test name
Test status
Simulation time 92774849 ps
CPU time 0.79 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:37 PM PDT 24
Peak memory 200196 kb
Host smart-f0d3ca7d-73ed-447a-8802-d64772331438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692615371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3692615371
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.340295976
Short name T504
Test name
Test status
Simulation time 762124056 ps
CPU time 4.1 seconds
Started Aug 02 05:17:34 PM PDT 24
Finished Aug 02 05:17:39 PM PDT 24
Peak memory 200492 kb
Host smart-f530fdfd-01b7-4391-8d9f-8f188f75fed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340295976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.340295976
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3188157675
Short name T166
Test name
Test status
Simulation time 146622591 ps
CPU time 1.08 seconds
Started Aug 02 05:17:29 PM PDT 24
Finished Aug 02 05:17:30 PM PDT 24
Peak memory 200380 kb
Host smart-8f6887fd-ab63-440c-9eed-d8f4cec18dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188157675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3188157675
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.223951426
Short name T466
Test name
Test status
Simulation time 199531138 ps
CPU time 1.38 seconds
Started Aug 02 05:17:37 PM PDT 24
Finished Aug 02 05:17:38 PM PDT 24
Peak memory 200556 kb
Host smart-f0176024-4912-4f8a-8aa0-84cb6a4219fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223951426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.223951426
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3877923644
Short name T178
Test name
Test status
Simulation time 214036271 ps
CPU time 1.21 seconds
Started Aug 02 05:17:32 PM PDT 24
Finished Aug 02 05:17:34 PM PDT 24
Peak memory 200368 kb
Host smart-26e6ab98-29bc-45fa-add2-ba174912679a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877923644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3877923644
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2613028634
Short name T428
Test name
Test status
Simulation time 393332003 ps
CPU time 2.6 seconds
Started Aug 02 05:17:58 PM PDT 24
Finished Aug 02 05:18:01 PM PDT 24
Peak memory 200320 kb
Host smart-49ef94b1-b8d2-4713-958c-c6428ead1f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613028634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2613028634
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1438564016
Short name T86
Test name
Test status
Simulation time 277078099 ps
CPU time 1.48 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:17:56 PM PDT 24
Peak memory 200388 kb
Host smart-04bf201d-bf00-45fb-a2ec-48ade6418396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438564016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1438564016
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2016919722
Short name T392
Test name
Test status
Simulation time 59741005 ps
CPU time 0.72 seconds
Started Aug 02 05:17:23 PM PDT 24
Finished Aug 02 05:17:24 PM PDT 24
Peak memory 200064 kb
Host smart-303e69d3-759a-4341-8482-b3087bf2cc6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016919722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2016919722
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2632487408
Short name T61
Test name
Test status
Simulation time 1225954208 ps
CPU time 5.51 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:26 PM PDT 24
Peak memory 217764 kb
Host smart-9d602e77-c5b8-4c9e-a495-3feb0c36ed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632487408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2632487408
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2067920169
Short name T205
Test name
Test status
Simulation time 244107784 ps
CPU time 1.08 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:17 PM PDT 24
Peak memory 217488 kb
Host smart-6f09a0f8-4a59-49d9-905d-fef39cf98472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067920169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2067920169
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1350741813
Short name T22
Test name
Test status
Simulation time 188199707 ps
CPU time 0.9 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:11 PM PDT 24
Peak memory 200076 kb
Host smart-e1c7448e-64e8-4dde-9ed1-8fbbfe5f722b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350741813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1350741813
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.576897413
Short name T396
Test name
Test status
Simulation time 1758082711 ps
CPU time 6.23 seconds
Started Aug 02 05:16:54 PM PDT 24
Finished Aug 02 05:17:00 PM PDT 24
Peak memory 200628 kb
Host smart-312e7308-721c-4f5e-ba5f-133793c3a1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576897413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.576897413
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3888847805
Short name T81
Test name
Test status
Simulation time 16694877120 ps
CPU time 24 seconds
Started Aug 02 05:16:53 PM PDT 24
Finished Aug 02 05:17:17 PM PDT 24
Peak memory 217280 kb
Host smart-f6ecd65f-3f7e-4d67-89f3-3bfff3b71ab8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888847805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3888847805
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2994268501
Short name T423
Test name
Test status
Simulation time 111913677 ps
CPU time 1.01 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 200340 kb
Host smart-e775ee3e-5f2f-4392-95b4-9f4f492b652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994268501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2994268501
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.855350954
Short name T491
Test name
Test status
Simulation time 125032102 ps
CPU time 1.19 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:17:25 PM PDT 24
Peak memory 200492 kb
Host smart-e0c14076-a132-49a4-8cfc-0b652ca68f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855350954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.855350954
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1811175776
Short name T468
Test name
Test status
Simulation time 2340301506 ps
CPU time 8.53 seconds
Started Aug 02 05:17:06 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 200620 kb
Host smart-98c808db-7ae9-4cab-914d-fd6088abeb24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811175776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1811175776
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2755764514
Short name T255
Test name
Test status
Simulation time 125821145 ps
CPU time 1.6 seconds
Started Aug 02 05:17:26 PM PDT 24
Finished Aug 02 05:17:27 PM PDT 24
Peak memory 208504 kb
Host smart-729b5afa-09fe-4acd-bade-e8fe8e121fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755764514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2755764514
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2354390035
Short name T503
Test name
Test status
Simulation time 225866544 ps
CPU time 1.4 seconds
Started Aug 02 05:16:52 PM PDT 24
Finished Aug 02 05:16:53 PM PDT 24
Peak memory 200552 kb
Host smart-03af98e4-f086-494c-a1fe-1da47c911324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354390035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2354390035
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.4253196257
Short name T251
Test name
Test status
Simulation time 68034818 ps
CPU time 0.79 seconds
Started Aug 02 05:17:33 PM PDT 24
Finished Aug 02 05:17:34 PM PDT 24
Peak memory 200128 kb
Host smart-cf381025-45e4-4fda-a353-39b26264e022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253196257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.4253196257
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.4049923171
Short name T424
Test name
Test status
Simulation time 1232079333 ps
CPU time 5.71 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:17:50 PM PDT 24
Peak memory 217636 kb
Host smart-5c023a2c-6b33-4122-b875-6be3e3cd5c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049923171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.4049923171
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3493821736
Short name T169
Test name
Test status
Simulation time 247364719 ps
CPU time 1 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:17:51 PM PDT 24
Peak memory 217436 kb
Host smart-33cd56e1-ed77-477f-b8cd-4352720b4e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493821736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3493821736
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2913723253
Short name T29
Test name
Test status
Simulation time 175244727 ps
CPU time 0.8 seconds
Started Aug 02 05:17:51 PM PDT 24
Finished Aug 02 05:17:52 PM PDT 24
Peak memory 200220 kb
Host smart-07e704a3-e712-4f41-9e0e-970dfc7702e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913723253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2913723253
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3571430451
Short name T131
Test name
Test status
Simulation time 1844459658 ps
CPU time 6.99 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:17:52 PM PDT 24
Peak memory 200612 kb
Host smart-5be76b1f-80db-444b-81b2-28b418fc1bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571430451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3571430451
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2555387266
Short name T304
Test name
Test status
Simulation time 108484836 ps
CPU time 0.99 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:37 PM PDT 24
Peak memory 200312 kb
Host smart-0cf47073-a73c-4ecf-83cd-39c70b9ac343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555387266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2555387266
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4214813591
Short name T95
Test name
Test status
Simulation time 109697743 ps
CPU time 1.14 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 200504 kb
Host smart-be5c84a4-2231-4fca-8b20-987e680a57b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214813591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4214813591
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2353711015
Short name T104
Test name
Test status
Simulation time 1949799737 ps
CPU time 7.29 seconds
Started Aug 02 05:18:07 PM PDT 24
Finished Aug 02 05:18:14 PM PDT 24
Peak memory 200564 kb
Host smart-1c9c01d4-e644-4756-95a2-343fcecdad29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353711015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2353711015
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.775374880
Short name T378
Test name
Test status
Simulation time 292821285 ps
CPU time 2.02 seconds
Started Aug 02 05:18:09 PM PDT 24
Finished Aug 02 05:18:11 PM PDT 24
Peak memory 200304 kb
Host smart-a8e2aebf-0348-4bec-b173-138ebee50639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775374880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.775374880
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3470662913
Short name T307
Test name
Test status
Simulation time 115539481 ps
CPU time 1.03 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:17:51 PM PDT 24
Peak memory 200368 kb
Host smart-2109a85c-6f3d-4c91-8486-c41827d6a446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470662913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3470662913
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2392799348
Short name T158
Test name
Test status
Simulation time 64247622 ps
CPU time 0.79 seconds
Started Aug 02 05:17:37 PM PDT 24
Finished Aug 02 05:17:38 PM PDT 24
Peak memory 200152 kb
Host smart-fd167f6f-1fde-4e54-abfa-4fdb84572b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392799348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2392799348
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.576305825
Short name T59
Test name
Test status
Simulation time 1222580827 ps
CPU time 5.53 seconds
Started Aug 02 05:17:49 PM PDT 24
Finished Aug 02 05:17:55 PM PDT 24
Peak memory 221656 kb
Host smart-2c820e31-1dcc-4144-9a3f-2ed3f9d02469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576305825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.576305825
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2591997459
Short name T280
Test name
Test status
Simulation time 244658173 ps
CPU time 1.05 seconds
Started Aug 02 05:18:00 PM PDT 24
Finished Aug 02 05:18:02 PM PDT 24
Peak memory 217456 kb
Host smart-40f0c053-a1a6-4d65-ba64-63c88bbf1c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591997459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2591997459
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2397559139
Short name T28
Test name
Test status
Simulation time 215991505 ps
CPU time 0.93 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 200088 kb
Host smart-2174c3c9-6958-46a4-a2cd-bb17d240f923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397559139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2397559139
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1107156707
Short name T254
Test name
Test status
Simulation time 849239017 ps
CPU time 4.71 seconds
Started Aug 02 05:17:51 PM PDT 24
Finished Aug 02 05:17:56 PM PDT 24
Peak memory 200612 kb
Host smart-6fc841a0-7a8c-4a1f-b0cd-07c86739508a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107156707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1107156707
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3688564206
Short name T220
Test name
Test status
Simulation time 186208544 ps
CPU time 1.21 seconds
Started Aug 02 05:17:42 PM PDT 24
Finished Aug 02 05:17:43 PM PDT 24
Peak memory 200328 kb
Host smart-a5cec768-1893-45d9-94e2-cc9666e7582a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688564206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3688564206
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3076450329
Short name T148
Test name
Test status
Simulation time 124201241 ps
CPU time 1.18 seconds
Started Aug 02 05:17:41 PM PDT 24
Finished Aug 02 05:17:42 PM PDT 24
Peak memory 200528 kb
Host smart-360fce96-5733-45a2-8e98-382729d0fe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076450329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3076450329
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3643001140
Short name T130
Test name
Test status
Simulation time 9507431596 ps
CPU time 31.49 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:18:23 PM PDT 24
Peak memory 209576 kb
Host smart-e091df67-881f-4162-8903-7dce364e847c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643001140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3643001140
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3113471785
Short name T523
Test name
Test status
Simulation time 349612399 ps
CPU time 1.96 seconds
Started Aug 02 05:17:43 PM PDT 24
Finished Aug 02 05:17:45 PM PDT 24
Peak memory 200204 kb
Host smart-5baaca5b-9048-465a-b9d5-c2de8ce236b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113471785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3113471785
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3045519325
Short name T411
Test name
Test status
Simulation time 146322509 ps
CPU time 1.06 seconds
Started Aug 02 05:17:49 PM PDT 24
Finished Aug 02 05:17:51 PM PDT 24
Peak memory 200372 kb
Host smart-16be8238-87b2-419a-adb6-6c9a141cd862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045519325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3045519325
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.104378825
Short name T538
Test name
Test status
Simulation time 65787937 ps
CPU time 0.84 seconds
Started Aug 02 05:17:58 PM PDT 24
Finished Aug 02 05:17:59 PM PDT 24
Peak memory 200200 kb
Host smart-8a414228-03c9-4ac3-818f-5d7d6fdccc94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104378825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.104378825
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2339617986
Short name T46
Test name
Test status
Simulation time 2341337288 ps
CPU time 8.07 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:17:58 PM PDT 24
Peak memory 217944 kb
Host smart-a0d4a9fb-69fb-45e2-96f9-cb9f943ce1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339617986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2339617986
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3489832826
Short name T242
Test name
Test status
Simulation time 243276376 ps
CPU time 1.09 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:17:56 PM PDT 24
Peak memory 217532 kb
Host smart-8483e782-d668-4d65-8d82-a54d5020b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489832826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3489832826
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2881032560
Short name T233
Test name
Test status
Simulation time 169981868 ps
CPU time 0.84 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 200172 kb
Host smart-09a24e81-8acb-4d94-9375-e5b80820f214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881032560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2881032560
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2743692619
Short name T351
Test name
Test status
Simulation time 1049590471 ps
CPU time 4.89 seconds
Started Aug 02 05:17:41 PM PDT 24
Finished Aug 02 05:17:51 PM PDT 24
Peak memory 200564 kb
Host smart-2627fdb9-136c-4125-8036-e0f15abc9b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743692619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2743692619
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3980070514
Short name T363
Test name
Test status
Simulation time 107870492 ps
CPU time 1 seconds
Started Aug 02 05:18:10 PM PDT 24
Finished Aug 02 05:18:11 PM PDT 24
Peak memory 200408 kb
Host smart-b80244c1-74e3-48cb-be71-8d938c7c30cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980070514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3980070514
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.937469523
Short name T236
Test name
Test status
Simulation time 110953399 ps
CPU time 1.22 seconds
Started Aug 02 05:17:42 PM PDT 24
Finished Aug 02 05:17:43 PM PDT 24
Peak memory 200528 kb
Host smart-06bdffb5-f315-4c48-b549-00f9ce12517c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937469523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.937469523
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3024555822
Short name T472
Test name
Test status
Simulation time 5412440190 ps
CPU time 21.17 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:18:05 PM PDT 24
Peak memory 200592 kb
Host smart-69ecb46b-f4f4-44bd-afaf-8071f9ffe980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024555822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3024555822
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1220727934
Short name T154
Test name
Test status
Simulation time 117079015 ps
CPU time 1.49 seconds
Started Aug 02 05:17:35 PM PDT 24
Finished Aug 02 05:17:37 PM PDT 24
Peak memory 200328 kb
Host smart-46f08bea-b96d-412d-b4da-02f89ab5d9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220727934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1220727934
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1507951935
Short name T228
Test name
Test status
Simulation time 156234565 ps
CPU time 1.16 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:17:50 PM PDT 24
Peak memory 200548 kb
Host smart-696703d8-3307-4cb6-916d-684cfe755d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507951935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1507951935
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1068583601
Short name T409
Test name
Test status
Simulation time 66735395 ps
CPU time 0.77 seconds
Started Aug 02 05:17:51 PM PDT 24
Finished Aug 02 05:17:52 PM PDT 24
Peak memory 200144 kb
Host smart-f1792d61-bf0a-412e-ab98-4cc1d4076774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068583601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1068583601
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.12785854
Short name T474
Test name
Test status
Simulation time 1890337612 ps
CPU time 6.93 seconds
Started Aug 02 05:17:39 PM PDT 24
Finished Aug 02 05:17:46 PM PDT 24
Peak memory 217680 kb
Host smart-20495d33-88b9-423a-950b-5595ad0bdcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12785854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.12785854
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3650454951
Short name T297
Test name
Test status
Simulation time 244993194 ps
CPU time 1.06 seconds
Started Aug 02 05:17:42 PM PDT 24
Finished Aug 02 05:17:43 PM PDT 24
Peak memory 217532 kb
Host smart-937a96f0-8053-4e14-bbbb-af228c39546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650454951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3650454951
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.124649581
Short name T229
Test name
Test status
Simulation time 91733702 ps
CPU time 0.76 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 200196 kb
Host smart-860ec42b-893b-4750-8e6c-8fe23c0b7970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124649581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.124649581
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1322206599
Short name T292
Test name
Test status
Simulation time 1466665743 ps
CPU time 6.77 seconds
Started Aug 02 05:17:37 PM PDT 24
Finished Aug 02 05:17:44 PM PDT 24
Peak memory 200556 kb
Host smart-2453867b-9766-4162-b4c1-d5df19a92d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322206599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1322206599
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3335363459
Short name T407
Test name
Test status
Simulation time 178530967 ps
CPU time 1.2 seconds
Started Aug 02 05:17:47 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 200380 kb
Host smart-2c07921d-1bdd-4e44-ae7d-4f5551f69cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335363459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3335363459
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3701123106
Short name T393
Test name
Test status
Simulation time 241902937 ps
CPU time 1.46 seconds
Started Aug 02 05:17:31 PM PDT 24
Finished Aug 02 05:17:33 PM PDT 24
Peak memory 200520 kb
Host smart-251e7a7f-1f22-4420-8633-1471c9d55c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701123106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3701123106
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.188134833
Short name T420
Test name
Test status
Simulation time 3721985262 ps
CPU time 16.19 seconds
Started Aug 02 05:17:53 PM PDT 24
Finished Aug 02 05:18:09 PM PDT 24
Peak memory 200688 kb
Host smart-7f04978f-2ab8-4e5c-9f12-6f4addd473f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188134833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.188134833
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.24646440
Short name T4
Test name
Test status
Simulation time 419079785 ps
CPU time 2.65 seconds
Started Aug 02 05:18:00 PM PDT 24
Finished Aug 02 05:18:03 PM PDT 24
Peak memory 200332 kb
Host smart-99162cc4-34ca-470e-88cf-59354c98b0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24646440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.24646440
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2674680663
Short name T335
Test name
Test status
Simulation time 66486624 ps
CPU time 0.78 seconds
Started Aug 02 05:17:39 PM PDT 24
Finished Aug 02 05:17:40 PM PDT 24
Peak memory 200340 kb
Host smart-5fa881a1-16df-4f31-add2-4786dd611fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674680663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2674680663
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2563107956
Short name T39
Test name
Test status
Simulation time 81163279 ps
CPU time 0.82 seconds
Started Aug 02 05:17:38 PM PDT 24
Finished Aug 02 05:17:39 PM PDT 24
Peak memory 200200 kb
Host smart-1d3d9108-2a72-4d90-9113-cf2243d095cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563107956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2563107956
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.602027398
Short name T425
Test name
Test status
Simulation time 1885340534 ps
CPU time 7.03 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:18:02 PM PDT 24
Peak memory 217680 kb
Host smart-456adea2-03ff-410d-b1fd-b3e5bfbc011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602027398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.602027398
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2365050979
Short name T326
Test name
Test status
Simulation time 245148045 ps
CPU time 1.05 seconds
Started Aug 02 05:17:38 PM PDT 24
Finished Aug 02 05:17:39 PM PDT 24
Peak memory 217628 kb
Host smart-d35b2ecb-d86c-4652-9164-d67d98fb22aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365050979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2365050979
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1259678492
Short name T461
Test name
Test status
Simulation time 177907718 ps
CPU time 0.84 seconds
Started Aug 02 05:17:56 PM PDT 24
Finished Aug 02 05:17:57 PM PDT 24
Peak memory 200188 kb
Host smart-1c0f3753-e945-4eea-84b1-ffe34eb693c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259678492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1259678492
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2432348006
Short name T107
Test name
Test status
Simulation time 1267875219 ps
CPU time 5.16 seconds
Started Aug 02 05:17:34 PM PDT 24
Finished Aug 02 05:17:39 PM PDT 24
Peak memory 200564 kb
Host smart-6092d539-4766-404e-9570-3bf195bd381c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432348006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2432348006
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3024323995
Short name T293
Test name
Test status
Simulation time 149737226 ps
CPU time 1.09 seconds
Started Aug 02 05:17:49 PM PDT 24
Finished Aug 02 05:17:50 PM PDT 24
Peak memory 200416 kb
Host smart-cbda2af6-3b5d-4fde-adba-487bdf0f8f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024323995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3024323995
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1765698848
Short name T381
Test name
Test status
Simulation time 125613863 ps
CPU time 1.15 seconds
Started Aug 02 05:17:56 PM PDT 24
Finished Aug 02 05:17:58 PM PDT 24
Peak memory 200520 kb
Host smart-c3aa322c-1917-4c6a-b12f-db0eecb4e223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765698848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1765698848
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3376383608
Short name T296
Test name
Test status
Simulation time 12519207385 ps
CPU time 41.81 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:18:32 PM PDT 24
Peak memory 208812 kb
Host smart-1dd5d8b0-bf89-4397-ab3d-c788393f7562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376383608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3376383608
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4079878999
Short name T37
Test name
Test status
Simulation time 323913015 ps
CPU time 2.26 seconds
Started Aug 02 05:17:51 PM PDT 24
Finished Aug 02 05:17:54 PM PDT 24
Peak memory 200276 kb
Host smart-a6a61c84-0909-4ee8-a154-d735584b1a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079878999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4079878999
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.47395012
Short name T418
Test name
Test status
Simulation time 277023681 ps
CPU time 1.46 seconds
Started Aug 02 05:17:39 PM PDT 24
Finished Aug 02 05:17:41 PM PDT 24
Peak memory 200600 kb
Host smart-2ca4c1c4-658e-45df-bc95-9b7330ed2d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47395012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.47395012
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1301042791
Short name T185
Test name
Test status
Simulation time 60148514 ps
CPU time 0.69 seconds
Started Aug 02 05:17:47 PM PDT 24
Finished Aug 02 05:17:48 PM PDT 24
Peak memory 200144 kb
Host smart-4917900a-451b-4b14-9324-9f0e75b2d92d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301042791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1301042791
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2112458992
Short name T479
Test name
Test status
Simulation time 1212840797 ps
CPU time 5.61 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:18:00 PM PDT 24
Peak memory 217796 kb
Host smart-cc8ed496-e9c1-4a26-b358-d985c3ebe200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112458992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2112458992
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3564309925
Short name T163
Test name
Test status
Simulation time 244238401 ps
CPU time 1.14 seconds
Started Aug 02 05:17:51 PM PDT 24
Finished Aug 02 05:17:52 PM PDT 24
Peak memory 217504 kb
Host smart-04d0134b-7387-40cb-ac93-e66cae66a9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564309925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3564309925
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1285907468
Short name T510
Test name
Test status
Simulation time 133699273 ps
CPU time 0.78 seconds
Started Aug 02 05:17:40 PM PDT 24
Finished Aug 02 05:17:41 PM PDT 24
Peak memory 200144 kb
Host smart-4e06ed30-b22e-4fd8-a384-74ab2463cfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285907468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1285907468
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2975373456
Short name T532
Test name
Test status
Simulation time 1448409610 ps
CPU time 5.32 seconds
Started Aug 02 05:17:49 PM PDT 24
Finished Aug 02 05:17:55 PM PDT 24
Peak memory 200544 kb
Host smart-a3ffcc8f-2b82-44d5-a752-b45500ebd169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975373456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2975373456
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.462115998
Short name T219
Test name
Test status
Simulation time 108533904 ps
CPU time 1.01 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 200344 kb
Host smart-dd4834dc-b6d5-4af3-a4df-006de4636c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462115998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.462115998
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.72133405
Short name T186
Test name
Test status
Simulation time 118285362 ps
CPU time 1.18 seconds
Started Aug 02 05:17:49 PM PDT 24
Finished Aug 02 05:17:51 PM PDT 24
Peak memory 200484 kb
Host smart-a38874e3-d8c0-49a9-9d4c-eb32bcf07bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72133405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.72133405
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2800583259
Short name T234
Test name
Test status
Simulation time 237246988 ps
CPU time 1.39 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:38 PM PDT 24
Peak memory 200524 kb
Host smart-6c76a01f-cc29-4d50-9815-25f6bb4d75d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800583259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2800583259
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.197750995
Short name T239
Test name
Test status
Simulation time 531208451 ps
CPU time 2.66 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:17:57 PM PDT 24
Peak memory 200324 kb
Host smart-3efb1d55-f5ae-4f0a-8de7-952cb630192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197750995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.197750995
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1988393996
Short name T533
Test name
Test status
Simulation time 141571162 ps
CPU time 1.04 seconds
Started Aug 02 05:17:41 PM PDT 24
Finished Aug 02 05:17:42 PM PDT 24
Peak memory 200340 kb
Host smart-cad21b53-2b28-4654-adab-c6a7a8ccaa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988393996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1988393996
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.475565642
Short name T271
Test name
Test status
Simulation time 90026090 ps
CPU time 0.87 seconds
Started Aug 02 05:17:47 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 200144 kb
Host smart-c2775c05-9104-44bf-8f57-4ba839cba70b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475565642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.475565642
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4001245607
Short name T449
Test name
Test status
Simulation time 1216799201 ps
CPU time 5.71 seconds
Started Aug 02 05:17:49 PM PDT 24
Finished Aug 02 05:17:55 PM PDT 24
Peak memory 217368 kb
Host smart-31954759-6a54-4ed4-9ae8-d3b93ed2cafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001245607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4001245607
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1944946748
Short name T7
Test name
Test status
Simulation time 245664567 ps
CPU time 1.04 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 217512 kb
Host smart-d13549a1-015f-436d-9b88-a8540d2e9f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944946748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1944946748
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.101429693
Short name T268
Test name
Test status
Simulation time 121528869 ps
CPU time 0.79 seconds
Started Aug 02 05:17:53 PM PDT 24
Finished Aug 02 05:17:54 PM PDT 24
Peak memory 200172 kb
Host smart-a73be1e2-60da-41ae-9813-a103f6a3b4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101429693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.101429693
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1515212328
Short name T498
Test name
Test status
Simulation time 1637000763 ps
CPU time 6.17 seconds
Started Aug 02 05:17:59 PM PDT 24
Finished Aug 02 05:18:06 PM PDT 24
Peak memory 200484 kb
Host smart-3ff90b19-4ed2-4160-ae7b-19006e37ed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515212328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1515212328
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2613069923
Short name T53
Test name
Test status
Simulation time 179656842 ps
CPU time 1.14 seconds
Started Aug 02 05:17:53 PM PDT 24
Finished Aug 02 05:17:54 PM PDT 24
Peak memory 200344 kb
Host smart-33d05bc1-86bf-4d65-a84f-86998d0a1b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613069923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2613069923
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.58018974
Short name T253
Test name
Test status
Simulation time 117316259 ps
CPU time 1.15 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:17:51 PM PDT 24
Peak memory 200552 kb
Host smart-9b2bef55-9037-4d77-8291-f6c3dc45db71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58018974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.58018974
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.4195488018
Short name T507
Test name
Test status
Simulation time 3664564401 ps
CPU time 18.21 seconds
Started Aug 02 05:17:58 PM PDT 24
Finished Aug 02 05:18:17 PM PDT 24
Peak memory 208792 kb
Host smart-94806d5c-5011-4033-8861-287aad3670c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195488018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.4195488018
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.924970960
Short name T84
Test name
Test status
Simulation time 359538723 ps
CPU time 2.09 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:17:50 PM PDT 24
Peak memory 200296 kb
Host smart-2f836473-2882-4845-bb9b-37423d9f9c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924970960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.924970960
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.449698585
Short name T191
Test name
Test status
Simulation time 84327065 ps
CPU time 0.83 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:17:46 PM PDT 24
Peak memory 200364 kb
Host smart-54fcabc9-949c-49fe-a7bf-c1c3440ad6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449698585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.449698585
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3263437962
Short name T216
Test name
Test status
Simulation time 75033429 ps
CPU time 0.77 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 200128 kb
Host smart-d4348576-c771-42b4-8316-b33df4615f01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263437962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3263437962
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2245424285
Short name T453
Test name
Test status
Simulation time 1912377368 ps
CPU time 6.66 seconds
Started Aug 02 05:17:35 PM PDT 24
Finished Aug 02 05:17:42 PM PDT 24
Peak memory 217596 kb
Host smart-3d4b0db4-7df8-4af3-9904-44027334cbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245424285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2245424285
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1044986594
Short name T332
Test name
Test status
Simulation time 245078898 ps
CPU time 1.08 seconds
Started Aug 02 05:17:43 PM PDT 24
Finished Aug 02 05:17:44 PM PDT 24
Peak memory 217552 kb
Host smart-f3992b17-747f-4a66-af15-69916a023533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044986594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1044986594
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2714869131
Short name T272
Test name
Test status
Simulation time 111162863 ps
CPU time 0.81 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:18:12 PM PDT 24
Peak memory 200240 kb
Host smart-819a69cb-f258-486c-8178-1210de240a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714869131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2714869131
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2197857988
Short name T291
Test name
Test status
Simulation time 1945801228 ps
CPU time 7.73 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:17:56 PM PDT 24
Peak memory 200644 kb
Host smart-f247e5b0-b74f-4b8c-b2b6-5efe8638e606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197857988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2197857988
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2182492867
Short name T467
Test name
Test status
Simulation time 107987252 ps
CPU time 0.96 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:17:54 PM PDT 24
Peak memory 200416 kb
Host smart-a0b62c5f-370d-4f02-8908-0ec2ff2ead48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182492867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2182492867
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.4052534948
Short name T285
Test name
Test status
Simulation time 197075156 ps
CPU time 1.35 seconds
Started Aug 02 05:17:37 PM PDT 24
Finished Aug 02 05:17:38 PM PDT 24
Peak memory 200584 kb
Host smart-ae99e106-a430-4344-a2cd-7cdd96e9f72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052534948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4052534948
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3433547964
Short name T317
Test name
Test status
Simulation time 194618088 ps
CPU time 1.21 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:17:52 PM PDT 24
Peak memory 200320 kb
Host smart-ec32808b-fa15-4ee0-bd10-ca43489b5f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433547964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3433547964
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.4237933412
Short name T294
Test name
Test status
Simulation time 110780376 ps
CPU time 1.41 seconds
Started Aug 02 05:17:40 PM PDT 24
Finished Aug 02 05:17:42 PM PDT 24
Peak memory 200268 kb
Host smart-1e0c295c-69fa-4b05-8073-144c0c346a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237933412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.4237933412
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2506598595
Short name T530
Test name
Test status
Simulation time 193450320 ps
CPU time 1.31 seconds
Started Aug 02 05:17:40 PM PDT 24
Finished Aug 02 05:17:42 PM PDT 24
Peak memory 200316 kb
Host smart-b8e77c67-861c-4e7f-85cb-9f3b97c3731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506598595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2506598595
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3086358875
Short name T315
Test name
Test status
Simulation time 79317929 ps
CPU time 0.8 seconds
Started Aug 02 05:18:08 PM PDT 24
Finished Aug 02 05:18:09 PM PDT 24
Peak memory 200140 kb
Host smart-8e4a5087-ba3e-4c7b-a125-e397c09d2fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086358875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3086358875
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.126201606
Short name T47
Test name
Test status
Simulation time 1228286299 ps
CPU time 5.43 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:52 PM PDT 24
Peak memory 216724 kb
Host smart-cbaba68d-40e7-48b4-89a1-f9b09e09690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126201606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.126201606
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2045918028
Short name T539
Test name
Test status
Simulation time 243664221 ps
CPU time 1.06 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:17:46 PM PDT 24
Peak memory 217488 kb
Host smart-1c242f71-e49d-4073-8df3-d61a54d542a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045918028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2045918028
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1185666622
Short name T399
Test name
Test status
Simulation time 100313977 ps
CPU time 0.8 seconds
Started Aug 02 05:17:38 PM PDT 24
Finished Aug 02 05:17:39 PM PDT 24
Peak memory 200144 kb
Host smart-aadb2d25-b5dc-4b1c-8916-cfd310ebdf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185666622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1185666622
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3073489420
Short name T370
Test name
Test status
Simulation time 845912706 ps
CPU time 4.42 seconds
Started Aug 02 05:18:00 PM PDT 24
Finished Aug 02 05:18:05 PM PDT 24
Peak memory 200564 kb
Host smart-3ebc77cd-e816-495e-8248-2e0020746536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073489420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3073489420
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1172793223
Short name T477
Test name
Test status
Simulation time 111154546 ps
CPU time 0.99 seconds
Started Aug 02 05:17:49 PM PDT 24
Finished Aug 02 05:17:50 PM PDT 24
Peak memory 200372 kb
Host smart-89fd35ca-a2c3-4740-9f24-2bcfc65b4ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172793223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1172793223
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.947776306
Short name T156
Test name
Test status
Simulation time 124272551 ps
CPU time 1.17 seconds
Started Aug 02 05:17:56 PM PDT 24
Finished Aug 02 05:17:58 PM PDT 24
Peak memory 200484 kb
Host smart-2ed22b5f-491b-450f-a291-afd9eb4efcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947776306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.947776306
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2407204501
Short name T458
Test name
Test status
Simulation time 11631586394 ps
CPU time 37.34 seconds
Started Aug 02 05:17:59 PM PDT 24
Finished Aug 02 05:18:36 PM PDT 24
Peak memory 200640 kb
Host smart-9fb0c670-e115-459d-8df9-19686ec06fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407204501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2407204501
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2774383247
Short name T32
Test name
Test status
Simulation time 121619211 ps
CPU time 1.6 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:17:52 PM PDT 24
Peak memory 200316 kb
Host smart-b34fda02-e2c8-4233-b373-ee10dfe9f72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774383247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2774383247
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2636434699
Short name T201
Test name
Test status
Simulation time 103287146 ps
CPU time 0.94 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:47 PM PDT 24
Peak memory 200364 kb
Host smart-2079a7df-f4aa-470b-bae6-00495950194e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636434699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2636434699
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.71726573
Short name T252
Test name
Test status
Simulation time 68735935 ps
CPU time 0.74 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:17:45 PM PDT 24
Peak memory 200204 kb
Host smart-0d2c799b-874e-404b-b3f5-3b6f342384a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71726573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.71726573
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4203337644
Short name T402
Test name
Test status
Simulation time 1238173239 ps
CPU time 5.57 seconds
Started Aug 02 05:18:02 PM PDT 24
Finished Aug 02 05:18:08 PM PDT 24
Peak memory 217772 kb
Host smart-b88cd7d8-a53d-46b7-97a9-3ab316bdc30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203337644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4203337644
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2467605863
Short name T325
Test name
Test status
Simulation time 244401518 ps
CPU time 1.1 seconds
Started Aug 02 05:18:19 PM PDT 24
Finished Aug 02 05:18:20 PM PDT 24
Peak memory 217380 kb
Host smart-830570d9-02e4-4c83-bfc0-67d38d82418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467605863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2467605863
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2284102709
Short name T462
Test name
Test status
Simulation time 245774639 ps
CPU time 0.95 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 200152 kb
Host smart-ba0b2fd6-6d3e-4a50-bee7-619d34319763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284102709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2284102709
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1469870399
Short name T1
Test name
Test status
Simulation time 902488933 ps
CPU time 4.22 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:51 PM PDT 24
Peak memory 200604 kb
Host smart-554d701c-1a7c-444b-bd06-da406ac6e474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469870399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1469870399
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1684659901
Short name T235
Test name
Test status
Simulation time 113732817 ps
CPU time 1.06 seconds
Started Aug 02 05:17:57 PM PDT 24
Finished Aug 02 05:17:58 PM PDT 24
Peak memory 200232 kb
Host smart-bea55af4-a580-4b8e-bded-9c3a311272e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684659901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1684659901
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.4242141722
Short name T134
Test name
Test status
Simulation time 261334229 ps
CPU time 1.5 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:17:52 PM PDT 24
Peak memory 200552 kb
Host smart-e5c5b701-3bf7-4bab-8a4c-1bdb1a327c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242141722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.4242141722
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3134025078
Short name T31
Test name
Test status
Simulation time 10962443331 ps
CPU time 35.76 seconds
Started Aug 02 05:18:05 PM PDT 24
Finished Aug 02 05:18:41 PM PDT 24
Peak memory 200488 kb
Host smart-761a1455-34f5-4de5-af69-c03d168d952c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134025078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3134025078
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.865741028
Short name T250
Test name
Test status
Simulation time 312488168 ps
CPU time 2.07 seconds
Started Aug 02 05:17:38 PM PDT 24
Finished Aug 02 05:17:40 PM PDT 24
Peak memory 200300 kb
Host smart-ea92ff0f-5256-43a4-8faf-42d4c87b042b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865741028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.865741028
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3810601203
Short name T478
Test name
Test status
Simulation time 149827833 ps
CPU time 1.06 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:17:45 PM PDT 24
Peak memory 200352 kb
Host smart-c1a84590-57c2-43ff-87a3-10ab65f4febd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810601203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3810601203
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.44352738
Short name T382
Test name
Test status
Simulation time 63786421 ps
CPU time 0.78 seconds
Started Aug 02 05:17:04 PM PDT 24
Finished Aug 02 05:17:10 PM PDT 24
Peak memory 199664 kb
Host smart-509f45e9-1b3f-4b5f-81a8-188f3046f1f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44352738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.44352738
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4231103652
Short name T34
Test name
Test status
Simulation time 1229291396 ps
CPU time 5.56 seconds
Started Aug 02 05:17:22 PM PDT 24
Finished Aug 02 05:17:28 PM PDT 24
Peak memory 217560 kb
Host smart-fb4aae79-a89a-43bf-aa3a-f3136e6dd195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231103652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4231103652
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3873203744
Short name T476
Test name
Test status
Simulation time 244362597 ps
CPU time 1.05 seconds
Started Aug 02 05:17:13 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 217568 kb
Host smart-f1208776-9afd-4fc6-8d6f-a8ec8a4b864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873203744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3873203744
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3484140072
Short name T492
Test name
Test status
Simulation time 111896824 ps
CPU time 0.79 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:11 PM PDT 24
Peak memory 200088 kb
Host smart-a229f98b-8b52-43cf-a030-b4a51f2c9f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484140072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3484140072
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1519390068
Short name T350
Test name
Test status
Simulation time 1731125558 ps
CPU time 6.84 seconds
Started Aug 02 05:17:17 PM PDT 24
Finished Aug 02 05:17:24 PM PDT 24
Peak memory 200564 kb
Host smart-ffc47ce7-783d-4e10-896b-7d36d1ebb164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519390068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1519390068
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3661824547
Short name T78
Test name
Test status
Simulation time 16702505137 ps
CPU time 25.99 seconds
Started Aug 02 05:17:05 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 217720 kb
Host smart-0ace9056-6d83-44e0-855a-6af1cfb7b40f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661824547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3661824547
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3450728058
Short name T145
Test name
Test status
Simulation time 171901169 ps
CPU time 1.25 seconds
Started Aug 02 05:17:17 PM PDT 24
Finished Aug 02 05:17:19 PM PDT 24
Peak memory 200352 kb
Host smart-3de906e7-b731-4986-acc0-8e12e9b83d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450728058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3450728058
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2069070054
Short name T448
Test name
Test status
Simulation time 231116438 ps
CPU time 1.41 seconds
Started Aug 02 05:17:04 PM PDT 24
Finished Aug 02 05:17:05 PM PDT 24
Peak memory 199820 kb
Host smart-d9c9afc9-e667-412f-b1d8-49ad198c2eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069070054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2069070054
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.514800056
Short name T306
Test name
Test status
Simulation time 4776729495 ps
CPU time 18.55 seconds
Started Aug 02 05:17:03 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 208848 kb
Host smart-2f76fd1f-a99f-4200-a111-b203daa18ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514800056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.514800056
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3912224396
Short name T487
Test name
Test status
Simulation time 105943330 ps
CPU time 1.41 seconds
Started Aug 02 05:17:13 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 200316 kb
Host smart-24faa97c-d705-46a0-a83f-0ba1b5c7270f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912224396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3912224396
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1801622755
Short name T514
Test name
Test status
Simulation time 85150118 ps
CPU time 0.84 seconds
Started Aug 02 05:16:55 PM PDT 24
Finished Aug 02 05:16:56 PM PDT 24
Peak memory 200396 kb
Host smart-18440c8c-860c-4cc8-8955-61672e3af19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801622755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1801622755
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2028876242
Short name T360
Test name
Test status
Simulation time 87705625 ps
CPU time 0.88 seconds
Started Aug 02 05:18:01 PM PDT 24
Finished Aug 02 05:18:02 PM PDT 24
Peak memory 200168 kb
Host smart-2232abb9-aa89-495c-8286-a7fb2d427b74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028876242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2028876242
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1669039279
Short name T354
Test name
Test status
Simulation time 1230256767 ps
CPU time 5.26 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 217744 kb
Host smart-933b5be5-9030-4986-8b1b-e607e41d7996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669039279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1669039279
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3479319431
Short name T283
Test name
Test status
Simulation time 244945883 ps
CPU time 1.04 seconds
Started Aug 02 05:18:12 PM PDT 24
Finished Aug 02 05:18:14 PM PDT 24
Peak memory 217508 kb
Host smart-0b446398-6a41-4ff3-a782-6f918ab50c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479319431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3479319431
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.528250921
Short name T23
Test name
Test status
Simulation time 129940285 ps
CPU time 0.8 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:17:46 PM PDT 24
Peak memory 200172 kb
Host smart-996ac859-acc2-416b-8c28-ccc321dd31e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528250921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.528250921
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.351373769
Short name T286
Test name
Test status
Simulation time 1508999904 ps
CPU time 5.54 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:17:55 PM PDT 24
Peak memory 200596 kb
Host smart-936cc2d5-5928-4f8d-8f9a-5120d901f7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351373769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.351373769
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3113812549
Short name T210
Test name
Test status
Simulation time 168113081 ps
CPU time 1.14 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 200368 kb
Host smart-0a45dae0-fb9e-4f15-865a-8e4c50262880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113812549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3113812549
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3908743451
Short name T259
Test name
Test status
Simulation time 194406350 ps
CPU time 1.32 seconds
Started Aug 02 05:17:43 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 200364 kb
Host smart-c9ef390b-aba0-4b21-b265-1eea9c9b6eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908743451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3908743451
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.4256196061
Short name T451
Test name
Test status
Simulation time 2203675823 ps
CPU time 9.58 seconds
Started Aug 02 05:18:00 PM PDT 24
Finished Aug 02 05:18:10 PM PDT 24
Peak memory 200488 kb
Host smart-47cd7cea-35b1-4dbc-9708-958173320611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256196061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.4256196061
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2646263131
Short name T415
Test name
Test status
Simulation time 367570778 ps
CPU time 2.49 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:17:57 PM PDT 24
Peak memory 200284 kb
Host smart-e6cd9274-8b94-42bc-9258-3e13da7f04df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646263131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2646263131
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1930941553
Short name T437
Test name
Test status
Simulation time 186732730 ps
CPU time 1.22 seconds
Started Aug 02 05:17:59 PM PDT 24
Finished Aug 02 05:18:01 PM PDT 24
Peak memory 200328 kb
Host smart-12308c37-2165-41bd-92a6-59995551f147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930941553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1930941553
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3914493480
Short name T501
Test name
Test status
Simulation time 91454957 ps
CPU time 0.8 seconds
Started Aug 02 05:18:02 PM PDT 24
Finished Aug 02 05:18:03 PM PDT 24
Peak memory 200216 kb
Host smart-b57350ba-790a-4e73-bb12-4c0bc21b5cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914493480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3914493480
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3406142406
Short name T529
Test name
Test status
Simulation time 2365254709 ps
CPU time 8.39 seconds
Started Aug 02 05:17:39 PM PDT 24
Finished Aug 02 05:17:48 PM PDT 24
Peak memory 221832 kb
Host smart-12bd2b8b-dc77-41d3-8510-1326b13e92ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406142406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3406142406
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.397575867
Short name T441
Test name
Test status
Simulation time 244741632 ps
CPU time 1.06 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:17:46 PM PDT 24
Peak memory 217512 kb
Host smart-d9dec5eb-cb07-4c90-8397-3820862d5adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397575867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.397575867
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.790850028
Short name T24
Test name
Test status
Simulation time 123982700 ps
CPU time 0.82 seconds
Started Aug 02 05:17:41 PM PDT 24
Finished Aug 02 05:17:42 PM PDT 24
Peak memory 200168 kb
Host smart-f3e1ace6-b4fe-4789-aa55-46b765f4645a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790850028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.790850028
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2128176689
Short name T112
Test name
Test status
Simulation time 955529255 ps
CPU time 4.39 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:17:49 PM PDT 24
Peak memory 200544 kb
Host smart-5dbaaa72-25e8-45e7-ba8a-0b044758d6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128176689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2128176689
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4147378001
Short name T349
Test name
Test status
Simulation time 103789758 ps
CPU time 0.97 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:17:56 PM PDT 24
Peak memory 200368 kb
Host smart-289d3e6f-53e7-47f1-bc42-0ac3f2014893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147378001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4147378001
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.4061267241
Short name T331
Test name
Test status
Simulation time 208606137 ps
CPU time 1.44 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:47 PM PDT 24
Peak memory 200616 kb
Host smart-b378dc38-a424-430e-92b4-0c1e63fb8fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061267241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4061267241
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1459358027
Short name T204
Test name
Test status
Simulation time 141790066 ps
CPU time 1.22 seconds
Started Aug 02 05:18:01 PM PDT 24
Finished Aug 02 05:18:02 PM PDT 24
Peak memory 200148 kb
Host smart-d914444b-c6a9-46c4-9b32-a017bc6aed89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459358027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1459358027
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.116236755
Short name T94
Test name
Test status
Simulation time 280907116 ps
CPU time 1.89 seconds
Started Aug 02 05:17:40 PM PDT 24
Finished Aug 02 05:17:42 PM PDT 24
Peak memory 200308 kb
Host smart-e1022da3-433a-433b-9d56-ead8bf3ca93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116236755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.116236755
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.172245638
Short name T452
Test name
Test status
Simulation time 122190361 ps
CPU time 1.09 seconds
Started Aug 02 05:17:53 PM PDT 24
Finished Aug 02 05:17:54 PM PDT 24
Peak memory 200220 kb
Host smart-8e242ec1-dacd-4387-b965-509a684b8d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172245638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.172245638
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3550532197
Short name T273
Test name
Test status
Simulation time 90203007 ps
CPU time 0.77 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:17:55 PM PDT 24
Peak memory 200220 kb
Host smart-412f0824-853a-43fb-83cf-b343c10ffb85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550532197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3550532197
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2138280637
Short name T372
Test name
Test status
Simulation time 1228497501 ps
CPU time 5.93 seconds
Started Aug 02 05:17:53 PM PDT 24
Finished Aug 02 05:17:59 PM PDT 24
Peak memory 217760 kb
Host smart-35e47402-b7ea-49e0-a067-cc7d09b03d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138280637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2138280637
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.79992401
Short name T290
Test name
Test status
Simulation time 244192830 ps
CPU time 1.13 seconds
Started Aug 02 05:17:36 PM PDT 24
Finished Aug 02 05:17:38 PM PDT 24
Peak memory 217524 kb
Host smart-cd0e9b94-ec47-4b21-94d8-31e782a2f9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79992401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.79992401
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1596594350
Short name T27
Test name
Test status
Simulation time 202700168 ps
CPU time 0.89 seconds
Started Aug 02 05:18:13 PM PDT 24
Finished Aug 02 05:18:14 PM PDT 24
Peak memory 200184 kb
Host smart-932bf452-d4cb-424e-929a-646e44a9be78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596594350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1596594350
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2857489961
Short name T422
Test name
Test status
Simulation time 1537299742 ps
CPU time 5.77 seconds
Started Aug 02 05:17:42 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 200556 kb
Host smart-025cb521-0ffa-4859-9f2c-3d8f44595d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857489961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2857489961
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.4000069255
Short name T505
Test name
Test status
Simulation time 144413526 ps
CPU time 1.1 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:17:45 PM PDT 24
Peak memory 200344 kb
Host smart-93d6086e-4632-433f-a01a-56f95c90cbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000069255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.4000069255
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.4149336064
Short name T388
Test name
Test status
Simulation time 192401300 ps
CPU time 1.29 seconds
Started Aug 02 05:17:41 PM PDT 24
Finished Aug 02 05:17:43 PM PDT 24
Peak memory 200504 kb
Host smart-f3264bb9-fbd8-40bf-bec2-9cc43784bfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149336064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.4149336064
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2883734380
Short name T193
Test name
Test status
Simulation time 4397525291 ps
CPU time 21.05 seconds
Started Aug 02 05:17:48 PM PDT 24
Finished Aug 02 05:18:09 PM PDT 24
Peak memory 208880 kb
Host smart-33662290-317d-449c-a812-3e15fc7cf3e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883734380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2883734380
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3702944606
Short name T241
Test name
Test status
Simulation time 145107231 ps
CPU time 2.01 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:48 PM PDT 24
Peak memory 200348 kb
Host smart-2e87766a-f13e-4228-a85f-8a10fe1d3417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702944606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3702944606
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1421329673
Short name T288
Test name
Test status
Simulation time 103915500 ps
CPU time 0.9 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:18:08 PM PDT 24
Peak memory 200384 kb
Host smart-18691fe6-8d4d-4aec-9231-7e9bbaaa18e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421329673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1421329673
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2580637640
Short name T266
Test name
Test status
Simulation time 71443867 ps
CPU time 0.83 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:18:07 PM PDT 24
Peak memory 200152 kb
Host smart-0d9ccef2-fcc0-4054-a201-e586a5e57b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580637640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2580637640
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3710401664
Short name T375
Test name
Test status
Simulation time 1225257952 ps
CPU time 6 seconds
Started Aug 02 05:18:02 PM PDT 24
Finished Aug 02 05:18:08 PM PDT 24
Peak memory 221696 kb
Host smart-6ace9393-2b0b-4d8c-99e2-ce9d5c6002f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710401664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3710401664
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3357835708
Short name T400
Test name
Test status
Simulation time 243908852 ps
CPU time 1.12 seconds
Started Aug 02 05:18:08 PM PDT 24
Finished Aug 02 05:18:09 PM PDT 24
Peak memory 217492 kb
Host smart-9f46e864-422b-4d69-8a87-212d7840f3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357835708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3357835708
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3678869209
Short name T30
Test name
Test status
Simulation time 136150501 ps
CPU time 0.83 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:47 PM PDT 24
Peak memory 200156 kb
Host smart-c9032ffa-f6f1-4dd4-91d8-2418bf565833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678869209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3678869209
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2513128714
Short name T380
Test name
Test status
Simulation time 972458230 ps
CPU time 4.84 seconds
Started Aug 02 05:18:09 PM PDT 24
Finished Aug 02 05:18:14 PM PDT 24
Peak memory 200572 kb
Host smart-7c74c88a-9718-4753-84d5-142bc0a01e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513128714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2513128714
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1844566136
Short name T493
Test name
Test status
Simulation time 97119277 ps
CPU time 0.99 seconds
Started Aug 02 05:17:42 PM PDT 24
Finished Aug 02 05:17:43 PM PDT 24
Peak memory 200356 kb
Host smart-bb1c9d67-0088-412b-bab2-b2d842cec9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844566136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1844566136
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1738152813
Short name T5
Test name
Test status
Simulation time 122989187 ps
CPU time 1.33 seconds
Started Aug 02 05:18:07 PM PDT 24
Finished Aug 02 05:18:09 PM PDT 24
Peak memory 200544 kb
Host smart-d91e4732-dc5c-4e61-9da2-8d4e8af1120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738152813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1738152813
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.86128232
Short name T244
Test name
Test status
Simulation time 13893854215 ps
CPU time 46.43 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:18:32 PM PDT 24
Peak memory 200628 kb
Host smart-281776a1-f781-4b90-9959-d339295b94d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86128232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.86128232
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1190477821
Short name T469
Test name
Test status
Simulation time 510659879 ps
CPU time 2.62 seconds
Started Aug 02 05:17:53 PM PDT 24
Finished Aug 02 05:17:56 PM PDT 24
Peak memory 200320 kb
Host smart-e3e1ed9f-5019-418f-a0ab-4068dc22fc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190477821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1190477821
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.63459669
Short name T142
Test name
Test status
Simulation time 99036680 ps
CPU time 0.86 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 200412 kb
Host smart-fbafa12f-c069-4e88-8dc5-704458bd16c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63459669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.63459669
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3838135788
Short name T320
Test name
Test status
Simulation time 75156739 ps
CPU time 0.78 seconds
Started Aug 02 05:18:04 PM PDT 24
Finished Aug 02 05:18:05 PM PDT 24
Peak memory 200156 kb
Host smart-8e94c39a-9186-43ad-852f-e9e516611ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838135788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3838135788
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.223059715
Short name T45
Test name
Test status
Simulation time 2353641261 ps
CPU time 7.96 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:18:14 PM PDT 24
Peak memory 217836 kb
Host smart-86dfc3a1-4e28-405b-bd7f-90a71b85e634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223059715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.223059715
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3618911090
Short name T471
Test name
Test status
Simulation time 244190184 ps
CPU time 1.06 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:17:56 PM PDT 24
Peak memory 217484 kb
Host smart-ec757f4a-7ca0-4be4-ae18-4081ad48488d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618911090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3618911090
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1694077761
Short name T497
Test name
Test status
Simulation time 152189570 ps
CPU time 0.86 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:17:46 PM PDT 24
Peak memory 200148 kb
Host smart-44d59a2b-3ee5-47f0-a97e-82d362d559e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694077761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1694077761
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.671147980
Short name T347
Test name
Test status
Simulation time 775449884 ps
CPU time 4.31 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:50 PM PDT 24
Peak memory 200608 kb
Host smart-38ef990d-3432-43dc-a3c8-6822332b214d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671147980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.671147980
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.4132854157
Short name T337
Test name
Test status
Simulation time 162230845 ps
CPU time 1.22 seconds
Started Aug 02 05:17:51 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 200392 kb
Host smart-59ecbcf4-02bb-45e6-91ac-07cf52c9b724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132854157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.4132854157
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.4006895639
Short name T135
Test name
Test status
Simulation time 231527796 ps
CPU time 1.51 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:17:54 PM PDT 24
Peak memory 200560 kb
Host smart-42dfdfc9-3540-420d-bbc6-4c9a84e50993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006895639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.4006895639
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.11611462
Short name T217
Test name
Test status
Simulation time 5478318392 ps
CPU time 23.21 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:18:13 PM PDT 24
Peak memory 208852 kb
Host smart-97b92f46-0763-491d-a433-9256d9f28e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11611462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.11611462
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1265581739
Short name T508
Test name
Test status
Simulation time 137866216 ps
CPU time 1.61 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:18:08 PM PDT 24
Peak memory 200176 kb
Host smart-92cd9525-cd4c-41de-b7b5-f17c82a174d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265581739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1265581739
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1512057080
Short name T426
Test name
Test status
Simulation time 228250177 ps
CPU time 1.28 seconds
Started Aug 02 05:18:01 PM PDT 24
Finished Aug 02 05:18:02 PM PDT 24
Peak memory 200348 kb
Host smart-821d0dd3-75e2-41ed-8abf-1aa6050a26d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512057080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1512057080
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4200125992
Short name T371
Test name
Test status
Simulation time 66619298 ps
CPU time 0.72 seconds
Started Aug 02 05:17:54 PM PDT 24
Finished Aug 02 05:17:55 PM PDT 24
Peak memory 200128 kb
Host smart-5269f7a7-93d5-46f4-8028-addfda023bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200125992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4200125992
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1659330648
Short name T65
Test name
Test status
Simulation time 1227036966 ps
CPU time 5.56 seconds
Started Aug 02 05:18:00 PM PDT 24
Finished Aug 02 05:18:06 PM PDT 24
Peak memory 221692 kb
Host smart-d63bd7ea-e2f4-4152-a59e-c402bd20d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659330648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1659330648
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1517938662
Short name T211
Test name
Test status
Simulation time 244523410 ps
CPU time 1.09 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:18:12 PM PDT 24
Peak memory 217492 kb
Host smart-d0620598-b49b-404c-a0f4-55c98a6cbbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517938662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1517938662
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.64744641
Short name T21
Test name
Test status
Simulation time 93743625 ps
CPU time 0.76 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:18:07 PM PDT 24
Peak memory 200184 kb
Host smart-562039b3-ce62-42e1-ab9f-908d4f74e2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64744641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.64744641
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1069774063
Short name T223
Test name
Test status
Simulation time 1267164371 ps
CPU time 5.35 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:17:50 PM PDT 24
Peak memory 200492 kb
Host smart-e144b1e0-63ef-4c53-9917-663a0d6b422c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069774063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1069774063
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2685167615
Short name T164
Test name
Test status
Simulation time 99162254 ps
CPU time 1.02 seconds
Started Aug 02 05:17:54 PM PDT 24
Finished Aug 02 05:17:55 PM PDT 24
Peak memory 200368 kb
Host smart-0578a5e8-2303-4bc6-8667-4013b08c72b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685167615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2685167615
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1802326658
Short name T318
Test name
Test status
Simulation time 242401568 ps
CPU time 1.59 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:17:46 PM PDT 24
Peak memory 200516 kb
Host smart-407852e7-44d9-4a99-84c8-d5675c5d2606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802326658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1802326658
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1054316689
Short name T465
Test name
Test status
Simulation time 131814344 ps
CPU time 1.74 seconds
Started Aug 02 05:18:08 PM PDT 24
Finished Aug 02 05:18:10 PM PDT 24
Peak memory 208516 kb
Host smart-253d4c04-3d45-4d99-8c83-0d8fb6355c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054316689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1054316689
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3072592927
Short name T525
Test name
Test status
Simulation time 86191527 ps
CPU time 0.88 seconds
Started Aug 02 05:17:50 PM PDT 24
Finished Aug 02 05:17:52 PM PDT 24
Peak memory 200392 kb
Host smart-fcab8ced-82cc-4a0f-bcc1-2289a90dbd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072592927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3072592927
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.81887347
Short name T230
Test name
Test status
Simulation time 69906248 ps
CPU time 0.82 seconds
Started Aug 02 05:18:03 PM PDT 24
Finished Aug 02 05:18:04 PM PDT 24
Peak memory 200180 kb
Host smart-8da540b0-8e9e-4ec2-a704-7517977c2706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81887347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.81887347
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1482404846
Short name T176
Test name
Test status
Simulation time 1887579906 ps
CPU time 7.51 seconds
Started Aug 02 05:17:58 PM PDT 24
Finished Aug 02 05:18:06 PM PDT 24
Peak memory 217052 kb
Host smart-34bd3fea-e9d5-4817-b7a4-2c0eb14677c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482404846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1482404846
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3597731891
Short name T18
Test name
Test status
Simulation time 244191030 ps
CPU time 1.05 seconds
Started Aug 02 05:18:15 PM PDT 24
Finished Aug 02 05:18:16 PM PDT 24
Peak memory 217500 kb
Host smart-6ab45d74-e6c5-47cd-b2a3-c7d4131d66c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597731891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3597731891
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.161973722
Short name T482
Test name
Test status
Simulation time 198027193 ps
CPU time 0.86 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:46 PM PDT 24
Peak memory 200168 kb
Host smart-e5210ff3-2a94-4040-a519-cf2ae06f0f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161973722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.161973722
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.4005862563
Short name T440
Test name
Test status
Simulation time 1359796208 ps
CPU time 5.27 seconds
Started Aug 02 05:18:00 PM PDT 24
Finished Aug 02 05:18:05 PM PDT 24
Peak memory 200596 kb
Host smart-09b3cc2b-54b2-4097-b641-f08ea21678db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005862563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.4005862563
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1034936545
Short name T303
Test name
Test status
Simulation time 106241412 ps
CPU time 1.08 seconds
Started Aug 02 05:18:12 PM PDT 24
Finished Aug 02 05:18:13 PM PDT 24
Peak memory 200324 kb
Host smart-3ce3084b-b728-4c4f-b549-0df74b3093e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034936545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1034936545
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1222866509
Short name T155
Test name
Test status
Simulation time 201576603 ps
CPU time 1.35 seconds
Started Aug 02 05:18:02 PM PDT 24
Finished Aug 02 05:18:04 PM PDT 24
Peak memory 200560 kb
Host smart-e8e4289f-7bfc-4d1a-ab4e-4238889a5495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222866509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1222866509
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.202520053
Short name T243
Test name
Test status
Simulation time 7035096163 ps
CPU time 30.19 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:18:17 PM PDT 24
Peak memory 208888 kb
Host smart-a2d01b9f-3b68-4046-a1fb-bbd0b544ba09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202520053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.202520053
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2000420034
Short name T208
Test name
Test status
Simulation time 255574275 ps
CPU time 1.8 seconds
Started Aug 02 05:18:13 PM PDT 24
Finished Aug 02 05:18:15 PM PDT 24
Peak memory 200296 kb
Host smart-20eb0135-43a9-4577-a930-d9cb9e68ef04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000420034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2000420034
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3576553375
Short name T83
Test name
Test status
Simulation time 166527947 ps
CPU time 1.29 seconds
Started Aug 02 05:18:03 PM PDT 24
Finished Aug 02 05:18:04 PM PDT 24
Peak memory 200488 kb
Host smart-f682e67c-f835-4a6c-8271-8d4f73aa757e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576553375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3576553375
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.128895642
Short name T456
Test name
Test status
Simulation time 71280325 ps
CPU time 0.73 seconds
Started Aug 02 05:17:41 PM PDT 24
Finished Aug 02 05:17:42 PM PDT 24
Peak memory 200140 kb
Host smart-2a6dfb89-5c86-46ba-b7df-2f653dc530d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128895642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.128895642
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2757113817
Short name T488
Test name
Test status
Simulation time 2196458388 ps
CPU time 7.56 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:18:13 PM PDT 24
Peak memory 217632 kb
Host smart-c92e8764-d21a-41df-a321-ec21d8f7966c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757113817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2757113817
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2297599641
Short name T513
Test name
Test status
Simulation time 244657070 ps
CPU time 1.04 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:17:45 PM PDT 24
Peak memory 217308 kb
Host smart-1984e5af-665e-409a-9dd3-241db3596334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297599641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2297599641
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.4012009054
Short name T187
Test name
Test status
Simulation time 119238163 ps
CPU time 0.79 seconds
Started Aug 02 05:17:53 PM PDT 24
Finished Aug 02 05:17:54 PM PDT 24
Peak memory 200132 kb
Host smart-4f66d262-c795-41f5-a0c2-a6094a4fa46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012009054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4012009054
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2742431811
Short name T446
Test name
Test status
Simulation time 1624118369 ps
CPU time 5.57 seconds
Started Aug 02 05:18:05 PM PDT 24
Finished Aug 02 05:18:10 PM PDT 24
Peak memory 200592 kb
Host smart-db29a648-0449-4d40-8747-907b357262ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742431811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2742431811
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.190455386
Short name T362
Test name
Test status
Simulation time 111189255 ps
CPU time 1.04 seconds
Started Aug 02 05:18:04 PM PDT 24
Finished Aug 02 05:18:05 PM PDT 24
Peak memory 200428 kb
Host smart-c7634957-39ef-4561-baab-41063d66aa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190455386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.190455386
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.474373950
Short name T12
Test name
Test status
Simulation time 208069138 ps
CPU time 1.33 seconds
Started Aug 02 05:18:03 PM PDT 24
Finished Aug 02 05:18:04 PM PDT 24
Peak memory 200516 kb
Host smart-b7426ddb-a7ba-4995-8d27-b638141aa789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474373950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.474373950
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.767214985
Short name T109
Test name
Test status
Simulation time 2653466206 ps
CPU time 13.22 seconds
Started Aug 02 05:18:14 PM PDT 24
Finished Aug 02 05:18:27 PM PDT 24
Peak memory 208852 kb
Host smart-f384560b-53c5-4923-9d2a-0a1bec277063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767214985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.767214985
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1287421737
Short name T528
Test name
Test status
Simulation time 351656016 ps
CPU time 1.93 seconds
Started Aug 02 05:17:46 PM PDT 24
Finished Aug 02 05:17:48 PM PDT 24
Peak memory 200300 kb
Host smart-dfb5e3cc-941d-46be-8ea2-223adec80f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287421737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1287421737
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2813146908
Short name T308
Test name
Test status
Simulation time 113450671 ps
CPU time 1.01 seconds
Started Aug 02 05:18:04 PM PDT 24
Finished Aug 02 05:18:05 PM PDT 24
Peak memory 200352 kb
Host smart-a84c3304-1998-4c65-a748-15e8d6d469d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813146908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2813146908
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1417298937
Short name T515
Test name
Test status
Simulation time 70286435 ps
CPU time 0.75 seconds
Started Aug 02 05:17:49 PM PDT 24
Finished Aug 02 05:17:50 PM PDT 24
Peak memory 200176 kb
Host smart-06a51fad-c049-49b4-8858-08c6fe7b562d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417298937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1417298937
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.4284604614
Short name T68
Test name
Test status
Simulation time 2362924479 ps
CPU time 8.5 seconds
Started Aug 02 05:18:23 PM PDT 24
Finished Aug 02 05:18:32 PM PDT 24
Peak memory 217752 kb
Host smart-cb3757bb-e408-4685-830f-343cb1b5dd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284604614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.4284604614
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.110312499
Short name T302
Test name
Test status
Simulation time 244203962 ps
CPU time 1.03 seconds
Started Aug 02 05:17:44 PM PDT 24
Finished Aug 02 05:17:46 PM PDT 24
Peak memory 217528 kb
Host smart-8ed897b6-b8e8-4f4f-9394-a87f0257877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110312499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.110312499
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.559252940
Short name T327
Test name
Test status
Simulation time 84440625 ps
CPU time 0.75 seconds
Started Aug 02 05:18:08 PM PDT 24
Finished Aug 02 05:18:09 PM PDT 24
Peak memory 200144 kb
Host smart-ab75dc83-f225-412a-8fed-30cef13e606b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559252940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.559252940
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3762284838
Short name T232
Test name
Test status
Simulation time 835418656 ps
CPU time 4.42 seconds
Started Aug 02 05:17:59 PM PDT 24
Finished Aug 02 05:18:04 PM PDT 24
Peak memory 200604 kb
Host smart-80824180-ba7a-4cd7-b960-fb7cfb82f116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762284838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3762284838
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3069326233
Short name T509
Test name
Test status
Simulation time 181525584 ps
CPU time 1.2 seconds
Started Aug 02 05:17:58 PM PDT 24
Finished Aug 02 05:18:00 PM PDT 24
Peak memory 200324 kb
Host smart-3340b6f5-fad0-4700-add4-033f468fb010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069326233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3069326233
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2361222961
Short name T535
Test name
Test status
Simulation time 261791038 ps
CPU time 1.63 seconds
Started Aug 02 05:17:54 PM PDT 24
Finished Aug 02 05:17:56 PM PDT 24
Peak memory 200560 kb
Host smart-c82e9328-6450-4779-94ec-e264d0f6da52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361222961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2361222961
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3976904982
Short name T516
Test name
Test status
Simulation time 3726261341 ps
CPU time 16.01 seconds
Started Aug 02 05:17:45 PM PDT 24
Finished Aug 02 05:18:01 PM PDT 24
Peak memory 200628 kb
Host smart-552a0afe-51be-412c-843f-e26f996aa8ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976904982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3976904982
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2855388309
Short name T85
Test name
Test status
Simulation time 126285214 ps
CPU time 1.59 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:18:07 PM PDT 24
Peak memory 200376 kb
Host smart-399dc053-329d-492a-90b7-204f49ff5c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855388309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2855388309
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1105386365
Short name T270
Test name
Test status
Simulation time 248083663 ps
CPU time 1.51 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:17:54 PM PDT 24
Peak memory 200368 kb
Host smart-f1446100-1dba-4fb9-a7f4-9b8c56446f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105386365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1105386365
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2454480407
Short name T151
Test name
Test status
Simulation time 73747891 ps
CPU time 0.8 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:18:07 PM PDT 24
Peak memory 200216 kb
Host smart-70c577d6-50a0-4f95-9d7d-9fc5704ef5db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454480407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2454480407
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3443100286
Short name T256
Test name
Test status
Simulation time 1220286294 ps
CPU time 5.55 seconds
Started Aug 02 05:18:02 PM PDT 24
Finished Aug 02 05:18:08 PM PDT 24
Peak memory 217592 kb
Host smart-880a9182-1f35-40fa-a214-7b1f6fb78ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443100286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3443100286
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.146856445
Short name T143
Test name
Test status
Simulation time 244611464 ps
CPU time 1.08 seconds
Started Aug 02 05:18:14 PM PDT 24
Finished Aug 02 05:18:15 PM PDT 24
Peak memory 217544 kb
Host smart-d9cd6dbd-27d6-46f0-aae4-35eda6994413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146856445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.146856445
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.4249408999
Short name T460
Test name
Test status
Simulation time 94699944 ps
CPU time 0.75 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 200160 kb
Host smart-d18d3a02-db7d-4b3b-a1dd-987f359b32df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249408999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.4249408999
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3526162277
Short name T55
Test name
Test status
Simulation time 1413669897 ps
CPU time 5.73 seconds
Started Aug 02 05:17:51 PM PDT 24
Finished Aug 02 05:17:57 PM PDT 24
Peak memory 200632 kb
Host smart-aa10dc97-7ca3-40a7-9b58-9593af42bbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526162277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3526162277
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1215873103
Short name T376
Test name
Test status
Simulation time 156398509 ps
CPU time 1.19 seconds
Started Aug 02 05:17:54 PM PDT 24
Finished Aug 02 05:17:55 PM PDT 24
Peak memory 200380 kb
Host smart-aed48863-586b-40c0-a236-4f261084d6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215873103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1215873103
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1032379787
Short name T144
Test name
Test status
Simulation time 118454175 ps
CPU time 1.25 seconds
Started Aug 02 05:17:58 PM PDT 24
Finished Aug 02 05:18:00 PM PDT 24
Peak memory 200520 kb
Host smart-fd0eb36d-33cc-4834-97b2-27394ce5870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032379787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1032379787
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.220133464
Short name T58
Test name
Test status
Simulation time 1551134538 ps
CPU time 7.44 seconds
Started Aug 02 05:17:49 PM PDT 24
Finished Aug 02 05:17:57 PM PDT 24
Peak memory 200600 kb
Host smart-a3ec3d29-0fdc-42a3-8214-d1a35ae03459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220133464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.220133464
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2167410827
Short name T343
Test name
Test status
Simulation time 285540545 ps
CPU time 2 seconds
Started Aug 02 05:18:08 PM PDT 24
Finished Aug 02 05:18:10 PM PDT 24
Peak memory 200348 kb
Host smart-0cbbb557-a03f-4122-b12c-581d83e5e62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167410827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2167410827
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.942202001
Short name T173
Test name
Test status
Simulation time 192899275 ps
CPU time 1.18 seconds
Started Aug 02 05:17:56 PM PDT 24
Finished Aug 02 05:17:57 PM PDT 24
Peak memory 200396 kb
Host smart-109ea1b9-6ecf-431e-b16d-c60a75d9efb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942202001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.942202001
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.41710052
Short name T526
Test name
Test status
Simulation time 79906389 ps
CPU time 0.8 seconds
Started Aug 02 05:16:59 PM PDT 24
Finished Aug 02 05:17:00 PM PDT 24
Peak memory 200128 kb
Host smart-abcfaaa0-9f7c-4986-9553-76364dcf2b42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41710052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.41710052
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1573006623
Short name T421
Test name
Test status
Simulation time 2365419680 ps
CPU time 8.73 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 217944 kb
Host smart-cfac35e2-2c27-4b8d-afff-239d143979f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573006623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1573006623
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2469074795
Short name T17
Test name
Test status
Simulation time 244363616 ps
CPU time 1.09 seconds
Started Aug 02 05:17:13 PM PDT 24
Finished Aug 02 05:17:15 PM PDT 24
Peak memory 217568 kb
Host smart-dc2716f4-e821-4013-a430-7d2e8478123d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469074795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2469074795
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2011691488
Short name T260
Test name
Test status
Simulation time 187567370 ps
CPU time 0.83 seconds
Started Aug 02 05:16:52 PM PDT 24
Finished Aug 02 05:16:58 PM PDT 24
Peak memory 200208 kb
Host smart-7e6f0152-1b00-4d85-9ebc-1583d98851f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011691488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2011691488
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.516423684
Short name T430
Test name
Test status
Simulation time 848210242 ps
CPU time 4.61 seconds
Started Aug 02 05:17:17 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 200580 kb
Host smart-87fb56f4-ccde-4e2e-b9ee-cde350fa72dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516423684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.516423684
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2202273089
Short name T369
Test name
Test status
Simulation time 146832209 ps
CPU time 1.09 seconds
Started Aug 02 05:16:59 PM PDT 24
Finished Aug 02 05:17:00 PM PDT 24
Peak memory 200408 kb
Host smart-7f5d7531-f0cc-4f54-a1a1-15b732ef5eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202273089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2202273089
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.167538248
Short name T299
Test name
Test status
Simulation time 198240702 ps
CPU time 1.34 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:12 PM PDT 24
Peak memory 200580 kb
Host smart-c78d14b0-fe1f-4bf7-ace0-343d1ce81fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167538248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.167538248
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2857661461
Short name T379
Test name
Test status
Simulation time 1288239550 ps
CPU time 5.94 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 200456 kb
Host smart-96732be0-52bb-4446-93bf-f1d2431670c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857661461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2857661461
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.4091335638
Short name T427
Test name
Test status
Simulation time 288315817 ps
CPU time 1.86 seconds
Started Aug 02 05:16:54 PM PDT 24
Finished Aug 02 05:16:57 PM PDT 24
Peak memory 200212 kb
Host smart-a359e833-40d5-4fca-8716-6d3a9374421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091335638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.4091335638
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.67579407
Short name T459
Test name
Test status
Simulation time 105404711 ps
CPU time 0.93 seconds
Started Aug 02 05:17:19 PM PDT 24
Finished Aug 02 05:17:20 PM PDT 24
Peak memory 200420 kb
Host smart-8dad48ff-29be-4bc5-b32c-831938ed1a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67579407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.67579407
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.4258419621
Short name T522
Test name
Test status
Simulation time 70816559 ps
CPU time 0.76 seconds
Started Aug 02 05:18:08 PM PDT 24
Finished Aug 02 05:18:09 PM PDT 24
Peak memory 200044 kb
Host smart-cd87c759-58ac-42c8-8575-8370e1e82a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258419621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4258419621
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1862714518
Short name T43
Test name
Test status
Simulation time 1228037873 ps
CPU time 5.47 seconds
Started Aug 02 05:17:04 PM PDT 24
Finished Aug 02 05:17:10 PM PDT 24
Peak memory 216952 kb
Host smart-54eaddcc-5a61-439b-85e6-976c221a96db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862714518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1862714518
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.788271256
Short name T540
Test name
Test status
Simulation time 243991678 ps
CPU time 1.15 seconds
Started Aug 02 05:18:20 PM PDT 24
Finished Aug 02 05:18:21 PM PDT 24
Peak memory 217408 kb
Host smart-11b84e9d-0c3c-40da-899f-4ff0f5a26720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788271256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.788271256
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1853019471
Short name T489
Test name
Test status
Simulation time 86277777 ps
CPU time 0.76 seconds
Started Aug 02 05:16:51 PM PDT 24
Finished Aug 02 05:16:52 PM PDT 24
Peak memory 200204 kb
Host smart-1ad2c766-477e-4b38-a23d-b2a47bb99b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853019471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1853019471
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3409313838
Short name T484
Test name
Test status
Simulation time 829990605 ps
CPU time 3.92 seconds
Started Aug 02 05:17:08 PM PDT 24
Finished Aug 02 05:17:12 PM PDT 24
Peak memory 200676 kb
Host smart-8e96d43b-55a8-4c6a-bac3-1f656c031792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409313838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3409313838
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1466832062
Short name T168
Test name
Test status
Simulation time 177492882 ps
CPU time 1.24 seconds
Started Aug 02 05:17:01 PM PDT 24
Finished Aug 02 05:17:02 PM PDT 24
Peak memory 200312 kb
Host smart-6cab14f1-5595-4b21-b19c-c1f36650711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466832062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1466832062
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1337712453
Short name T475
Test name
Test status
Simulation time 195957567 ps
CPU time 1.4 seconds
Started Aug 02 05:16:56 PM PDT 24
Finished Aug 02 05:16:58 PM PDT 24
Peak memory 200556 kb
Host smart-f0436490-496a-4dc6-911c-99159bc19d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337712453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1337712453
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.53934921
Short name T133
Test name
Test status
Simulation time 11843426430 ps
CPU time 37.82 seconds
Started Aug 02 05:17:09 PM PDT 24
Finished Aug 02 05:17:47 PM PDT 24
Peak memory 216952 kb
Host smart-12c2dfe7-1873-4287-a691-0b32ae319f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53934921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.53934921
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.213361412
Short name T6
Test name
Test status
Simulation time 406369228 ps
CPU time 2.26 seconds
Started Aug 02 05:17:22 PM PDT 24
Finished Aug 02 05:17:24 PM PDT 24
Peak memory 208460 kb
Host smart-4acaae32-9951-4dfd-858a-3d3a2100831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213361412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.213361412
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3133724106
Short name T333
Test name
Test status
Simulation time 173952572 ps
CPU time 1.2 seconds
Started Aug 02 05:17:11 PM PDT 24
Finished Aug 02 05:17:12 PM PDT 24
Peak memory 200420 kb
Host smart-cbff83cd-0402-4020-8352-bf3782320b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133724106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3133724106
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1658080639
Short name T149
Test name
Test status
Simulation time 72862918 ps
CPU time 0.78 seconds
Started Aug 02 05:16:48 PM PDT 24
Finished Aug 02 05:16:49 PM PDT 24
Peak memory 200160 kb
Host smart-7b069f45-54af-4dd3-b3c7-b009b0e9c56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658080639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1658080639
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.542806407
Short name T13
Test name
Test status
Simulation time 1217960560 ps
CPU time 5.46 seconds
Started Aug 02 05:16:56 PM PDT 24
Finished Aug 02 05:17:01 PM PDT 24
Peak memory 217068 kb
Host smart-4607059f-e9fb-461a-8d64-95fc2fbd7c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542806407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.542806407
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2109898679
Short name T348
Test name
Test status
Simulation time 245243797 ps
CPU time 1.04 seconds
Started Aug 02 05:16:53 PM PDT 24
Finished Aug 02 05:16:54 PM PDT 24
Peak memory 217500 kb
Host smart-43b0f019-32b4-4ace-9621-7aaff5f03621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109898679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2109898679
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.379970025
Short name T391
Test name
Test status
Simulation time 188372755 ps
CPU time 0.87 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:11 PM PDT 24
Peak memory 200152 kb
Host smart-f037dcb0-2b1b-4bf7-88ed-1214e7979b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379970025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.379970025
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2416077156
Short name T433
Test name
Test status
Simulation time 925880288 ps
CPU time 4.58 seconds
Started Aug 02 05:17:07 PM PDT 24
Finished Aug 02 05:17:12 PM PDT 24
Peak memory 200460 kb
Host smart-8a975973-419e-42a2-8991-88b5d9c8dd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416077156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2416077156
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4171458389
Short name T276
Test name
Test status
Simulation time 166912583 ps
CPU time 1.17 seconds
Started Aug 02 05:17:06 PM PDT 24
Finished Aug 02 05:17:07 PM PDT 24
Peak memory 200360 kb
Host smart-1d39b573-c3fd-4b2e-9cd1-cb50a879dd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171458389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4171458389
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.456617970
Short name T410
Test name
Test status
Simulation time 195371117 ps
CPU time 1.43 seconds
Started Aug 02 05:17:02 PM PDT 24
Finished Aug 02 05:17:04 PM PDT 24
Peak memory 200004 kb
Host smart-f14f7133-de2b-45ce-8e95-bf3f12f01237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456617970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.456617970
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2892686134
Short name T106
Test name
Test status
Simulation time 16162207181 ps
CPU time 52.5 seconds
Started Aug 02 05:17:14 PM PDT 24
Finished Aug 02 05:18:06 PM PDT 24
Peak memory 208860 kb
Host smart-78364cb7-8f52-4c99-a152-55eace963e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892686134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2892686134
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1018196486
Short name T518
Test name
Test status
Simulation time 142201047 ps
CPU time 1.64 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:18:12 PM PDT 24
Peak memory 200168 kb
Host smart-66ef0b2f-30ba-4b24-915f-6de0c4fc4872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018196486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1018196486
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.4200745504
Short name T207
Test name
Test status
Simulation time 262160754 ps
CPU time 1.48 seconds
Started Aug 02 05:17:27 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 200252 kb
Host smart-78a7bbff-6539-4928-9087-32962b18daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200745504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.4200745504
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.858711120
Short name T209
Test name
Test status
Simulation time 83454388 ps
CPU time 0.8 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 200076 kb
Host smart-1cbbca4d-34dc-4607-bb25-81250b7da406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858711120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.858711120
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.4009521273
Short name T67
Test name
Test status
Simulation time 1216670547 ps
CPU time 5.21 seconds
Started Aug 02 05:17:47 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 216424 kb
Host smart-f5663225-54b7-4eb0-bcf2-3ec3ca767ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009521273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4009521273
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3988820711
Short name T227
Test name
Test status
Simulation time 244194271 ps
CPU time 1.07 seconds
Started Aug 02 05:18:12 PM PDT 24
Finished Aug 02 05:18:13 PM PDT 24
Peak memory 217348 kb
Host smart-a14e38fe-7e0c-4630-94a4-acdf4e5b28c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988820711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3988820711
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.4219531173
Short name T512
Test name
Test status
Simulation time 129615988 ps
CPU time 0.82 seconds
Started Aug 02 05:17:21 PM PDT 24
Finished Aug 02 05:17:22 PM PDT 24
Peak memory 200160 kb
Host smart-6a8f1567-cab3-489a-8fc0-f427336a2a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219531173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.4219531173
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.622219377
Short name T403
Test name
Test status
Simulation time 1038696488 ps
CPU time 5.04 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:20 PM PDT 24
Peak memory 200588 kb
Host smart-2c923230-0187-442a-b5b3-0ed825d40901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622219377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.622219377
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.242156080
Short name T322
Test name
Test status
Simulation time 111571805 ps
CPU time 1.06 seconds
Started Aug 02 05:17:15 PM PDT 24
Finished Aug 02 05:17:16 PM PDT 24
Peak memory 200376 kb
Host smart-4cf42853-196d-4481-a028-43728c7aa3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242156080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.242156080
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.923479936
Short name T180
Test name
Test status
Simulation time 113035256 ps
CPU time 1.17 seconds
Started Aug 02 05:17:20 PM PDT 24
Finished Aug 02 05:17:21 PM PDT 24
Peak memory 200476 kb
Host smart-bdc58dfc-6b47-4fa2-ab9e-2d3eaf74ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923479936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.923479936
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.651187691
Short name T129
Test name
Test status
Simulation time 11708628712 ps
CPU time 36.65 seconds
Started Aug 02 05:18:21 PM PDT 24
Finished Aug 02 05:18:58 PM PDT 24
Peak memory 200536 kb
Host smart-7ae976a8-fb41-485a-9ff1-91077dfcbc71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651187691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.651187691
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3520619598
Short name T36
Test name
Test status
Simulation time 248914957 ps
CPU time 1.63 seconds
Started Aug 02 05:16:50 PM PDT 24
Finished Aug 02 05:16:52 PM PDT 24
Peak memory 200328 kb
Host smart-667294ac-29e2-4b62-a89a-fb5ad9c08ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520619598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3520619598
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.4109097992
Short name T248
Test name
Test status
Simulation time 145374612 ps
CPU time 1.01 seconds
Started Aug 02 05:17:07 PM PDT 24
Finished Aug 02 05:17:08 PM PDT 24
Peak memory 200364 kb
Host smart-9436cf8f-17d2-464e-a933-9514076610c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109097992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.4109097992
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1318589806
Short name T190
Test name
Test status
Simulation time 60981294 ps
CPU time 0.73 seconds
Started Aug 02 05:17:23 PM PDT 24
Finished Aug 02 05:17:24 PM PDT 24
Peak memory 200172 kb
Host smart-24ddcb95-cd34-4b4f-be1f-e482727b669e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318589806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1318589806
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3561309506
Short name T60
Test name
Test status
Simulation time 1224323825 ps
CPU time 5.9 seconds
Started Aug 02 05:17:03 PM PDT 24
Finished Aug 02 05:17:09 PM PDT 24
Peak memory 217644 kb
Host smart-1c475789-f3e9-4f23-9f5a-31d89767e091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561309506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3561309506
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2425683601
Short name T247
Test name
Test status
Simulation time 243111854 ps
CPU time 1.15 seconds
Started Aug 02 05:17:30 PM PDT 24
Finished Aug 02 05:17:31 PM PDT 24
Peak memory 217624 kb
Host smart-52e450a8-ae74-443c-8c87-e690d8c598d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425683601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2425683601
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3733197236
Short name T25
Test name
Test status
Simulation time 169496621 ps
CPU time 0.96 seconds
Started Aug 02 05:17:03 PM PDT 24
Finished Aug 02 05:17:04 PM PDT 24
Peak memory 200196 kb
Host smart-f3e58c7f-c2f0-4337-befe-3ca982289671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733197236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3733197236
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.4095187741
Short name T364
Test name
Test status
Simulation time 676373554 ps
CPU time 3.77 seconds
Started Aug 02 05:17:13 PM PDT 24
Finished Aug 02 05:17:17 PM PDT 24
Peak memory 200652 kb
Host smart-836ae1a5-e91d-407f-acb8-e503bf720071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095187741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.4095187741
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2435803720
Short name T483
Test name
Test status
Simulation time 153605514 ps
CPU time 1.2 seconds
Started Aug 02 05:17:02 PM PDT 24
Finished Aug 02 05:17:03 PM PDT 24
Peak memory 200392 kb
Host smart-e80363e5-433e-4394-b92e-b48bae146e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435803720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2435803720
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2825751705
Short name T261
Test name
Test status
Simulation time 125082319 ps
CPU time 1.16 seconds
Started Aug 02 05:16:52 PM PDT 24
Finished Aug 02 05:16:54 PM PDT 24
Peak memory 200516 kb
Host smart-414f6495-5bb2-4e5d-96fa-408ad5a94fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825751705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2825751705
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.114878837
Short name T309
Test name
Test status
Simulation time 8186679444 ps
CPU time 26.68 seconds
Started Aug 02 05:17:10 PM PDT 24
Finished Aug 02 05:17:37 PM PDT 24
Peak memory 200628 kb
Host smart-ffd7cb99-bea0-46de-a74e-9c1705eadb50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114878837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.114878837
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3471162201
Short name T289
Test name
Test status
Simulation time 142650413 ps
CPU time 1.65 seconds
Started Aug 02 05:17:08 PM PDT 24
Finished Aug 02 05:17:09 PM PDT 24
Peak memory 200296 kb
Host smart-dbc7ae3b-643c-43f6-bb81-c8d6874eed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471162201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3471162201
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.107103140
Short name T442
Test name
Test status
Simulation time 65813980 ps
CPU time 0.82 seconds
Started Aug 02 05:17:26 PM PDT 24
Finished Aug 02 05:17:27 PM PDT 24
Peak memory 200432 kb
Host smart-398b0000-527d-4d99-a0e2-cf4da9d94098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107103140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.107103140
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%