Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7920

1

T3

19

T4

16

T7

208

auto[1]

10870

1

T3

82

T4

85

T6

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5880	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6261	1			T1	1		T2	1		T3	27
reset_info_cp[2]	2890	1			T3	15		T4	17		T6	1
reset_info_cp[4]	3848	1			T3	17		T4	18		T6	1
reset_info_cp[8]	103	1			T7	2		T11	1		T49	2
reset_info_cp[16]	106	1			T7	3		T33	1		T36	1
reset_info_cp[32]	105	1			T3	1		T7	4		T10	1
reset_info_cp[64]	91	1			T3	1		T7	2		T73	1
reset_info_cp[128]	126	1			T7	3		T12	1		T13	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3014	1			T3	19		T4	16		T7	69
reset_info_cp[1]	auto[1]	2627	1			T3	7		T4	10		T6	1
reset_info_cp[2]	auto[0]	920	1			T7	25		T12	3		T74	22
reset_info_cp[2]	auto[1]	1970	1			T3	15		T4	17		T6	1
reset_info_cp[4]	auto[0]	1318	1			T7	34		T12	11		T74	32
reset_info_cp[4]	auto[1]	2530	1			T3	17		T4	18		T6	1
reset_info_cp[8]	auto[0]	47	1			T7	2		T74	1		T75	1
reset_info_cp[8]	auto[1]	56	1			T11	1		T49	2		T34	1
reset_info_cp[16]	auto[0]	36	1			T7	1		T74	1		T78	2
reset_info_cp[16]	auto[1]	70	1			T7	2		T33	1		T36	1
reset_info_cp[32]	auto[0]	45	1			T7	2		T80	2		T94	1
reset_info_cp[32]	auto[1]	60	1			T3	1		T7	2		T10	1
reset_info_cp[64]	auto[0]	38	1			T7	2		T76	1		T27	1
reset_info_cp[64]	auto[1]	53	1			T3	1		T73	1		T34	1
reset_info_cp[128]	auto[0]	51	1			T7	1		T13	1		T74	1
reset_info_cp[128]	auto[1]	75	1			T7	2		T12	1		T33	1