Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
count_cp	4	0	4	100.00	100	1	1	0
length_cp	8	0	8	100.00	100	1	1	0

Summary for Variable count_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for count_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9619	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cb[0]	1298	1			T1	3		T2	3		T3	3
cb[1]	1143	1			T1	4		T2	4		T3	4
cb[2]	1078	1			T1	4		T2	4		T3	4
cb[3]	1001	1			T1	4		T2	4		T3	4

---

Summary for Variable length_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for length_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11581	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lb[0]	361	1			T1	1		T2	2		T3	2
lb[1]	342	1			T1	1		T3	1		T4	3
lb[2]	327	1			T3	1		T7	3		T45	17
lb[3]	321	1			T3	1		T7	3		T10	2
lb[4]	335	1			T3	1		T4	2		T7	2
lb[5]	296	1			T4	1		T7	1		T10	2
lb[6]	321	1			T3	1		T4	1		T7	2
lb[7]	255	1			T3	1		T4	1		T7	1