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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T534 /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3193374947 Aug 03 04:39:30 PM PDT 24 Aug 03 04:39:36 PM PDT 24 1222334599 ps
T535 /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.909196648 Aug 03 04:39:53 PM PDT 24 Aug 03 04:39:59 PM PDT 24 1214411645 ps
T536 /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2117206170 Aug 03 04:39:38 PM PDT 24 Aug 03 04:39:40 PM PDT 24 243621369 ps
T537 /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.959141871 Aug 03 04:39:00 PM PDT 24 Aug 03 04:39:02 PM PDT 24 112648098 ps
T538 /workspace/coverage/default/4.rstmgr_reset.1835125191 Aug 03 04:38:41 PM PDT 24 Aug 03 04:38:47 PM PDT 24 1498300205 ps
T58 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.4192143392 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:47 PM PDT 24 142537259 ps
T53 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4087002403 Aug 03 04:36:44 PM PDT 24 Aug 03 04:36:46 PM PDT 24 104611860 ps
T59 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.932353737 Aug 03 04:36:57 PM PDT 24 Aug 03 04:37:00 PM PDT 24 457787655 ps
T54 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2380498563 Aug 03 04:36:34 PM PDT 24 Aug 03 04:36:36 PM PDT 24 249695852 ps
T55 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1024895121 Aug 03 04:36:40 PM PDT 24 Aug 03 04:36:41 PM PDT 24 78366558 ps
T539 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1149227853 Aug 03 04:36:31 PM PDT 24 Aug 03 04:36:32 PM PDT 24 140907956 ps
T56 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.207730027 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:47 PM PDT 24 224290435 ps
T102 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3885135666 Aug 03 04:36:41 PM PDT 24 Aug 03 04:36:42 PM PDT 24 71113148 ps
T60 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4042988562 Aug 03 04:36:32 PM PDT 24 Aug 03 04:36:34 PM PDT 24 133455034 ps
T103 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2676998727 Aug 03 04:36:30 PM PDT 24 Aug 03 04:36:31 PM PDT 24 83399755 ps
T104 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.964375214 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:47 PM PDT 24 60232885 ps
T61 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1454329163 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:47 PM PDT 24 405779776 ps
T105 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2564250610 Aug 03 04:36:44 PM PDT 24 Aug 03 04:36:45 PM PDT 24 167040502 ps
T106 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1108980498 Aug 03 04:36:41 PM PDT 24 Aug 03 04:36:42 PM PDT 24 207193521 ps
T67 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1353810703 Aug 03 04:36:34 PM PDT 24 Aug 03 04:36:35 PM PDT 24 121526103 ps
T83 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1185364246 Aug 03 04:36:28 PM PDT 24 Aug 03 04:36:30 PM PDT 24 167958731 ps
T107 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.607884724 Aug 03 04:36:44 PM PDT 24 Aug 03 04:36:46 PM PDT 24 123689809 ps
T540 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2934245831 Aug 03 04:36:28 PM PDT 24 Aug 03 04:36:29 PM PDT 24 97489966 ps
T108 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3949409970 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:47 PM PDT 24 85984925 ps
T84 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3374923481 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:47 PM PDT 24 293610153 ps
T85 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2078363053 Aug 03 04:36:47 PM PDT 24 Aug 03 04:36:50 PM PDT 24 348953676 ps
T68 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3469231349 Aug 03 04:36:32 PM PDT 24 Aug 03 04:36:36 PM PDT 24 938154662 ps
T95 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.504305486 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:56 PM PDT 24 83735912 ps
T86 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.318368723 Aug 03 04:36:17 PM PDT 24 Aug 03 04:36:19 PM PDT 24 458497343 ps
T541 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1182596643 Aug 03 04:36:34 PM PDT 24 Aug 03 04:36:35 PM PDT 24 112412639 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3284881062 Aug 03 04:36:38 PM PDT 24 Aug 03 04:36:40 PM PDT 24 112403217 ps
T543 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2611809589 Aug 03 04:36:52 PM PDT 24 Aug 03 04:36:53 PM PDT 24 93814829 ps
T88 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1318936411 Aug 03 04:36:42 PM PDT 24 Aug 03 04:36:46 PM PDT 24 994084432 ps
T87 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3529312993 Aug 03 04:36:43 PM PDT 24 Aug 03 04:36:46 PM PDT 24 393956923 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1222937339 Aug 03 04:36:14 PM PDT 24 Aug 03 04:36:15 PM PDT 24 66369713 ps
T545 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2886834705 Aug 03 04:36:40 PM PDT 24 Aug 03 04:36:42 PM PDT 24 254208703 ps
T89 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.756154906 Aug 03 04:36:35 PM PDT 24 Aug 03 04:36:36 PM PDT 24 134452152 ps
T546 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2884917934 Aug 03 04:36:51 PM PDT 24 Aug 03 04:36:52 PM PDT 24 114489018 ps
T115 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3443518679 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:46 PM PDT 24 136203407 ps
T547 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3635430292 Aug 03 04:36:33 PM PDT 24 Aug 03 04:36:34 PM PDT 24 118151722 ps
T109 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1183748056 Aug 03 04:36:38 PM PDT 24 Aug 03 04:36:40 PM PDT 24 141400729 ps
T110 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2926943039 Aug 03 04:36:47 PM PDT 24 Aug 03 04:36:50 PM PDT 24 787240094 ps
T548 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2864059913 Aug 03 04:36:36 PM PDT 24 Aug 03 04:36:39 PM PDT 24 920461900 ps
T549 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3033856336 Aug 03 04:36:43 PM PDT 24 Aug 03 04:36:44 PM PDT 24 124872762 ps
T550 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3013212389 Aug 03 04:36:44 PM PDT 24 Aug 03 04:36:46 PM PDT 24 377204294 ps
T551 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2478988636 Aug 03 04:36:44 PM PDT 24 Aug 03 04:36:45 PM PDT 24 85994701 ps
T552 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2726616539 Aug 03 04:36:15 PM PDT 24 Aug 03 04:36:16 PM PDT 24 64403335 ps
T553 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1653342264 Aug 03 04:36:44 PM PDT 24 Aug 03 04:36:47 PM PDT 24 449360424 ps
T112 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.488930555 Aug 03 04:36:40 PM PDT 24 Aug 03 04:36:42 PM PDT 24 436739245 ps
T554 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.717559103 Aug 03 04:36:29 PM PDT 24 Aug 03 04:36:32 PM PDT 24 450248787 ps
T555 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1727658283 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:49 PM PDT 24 882785696 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1595564117 Aug 03 04:36:33 PM PDT 24 Aug 03 04:36:35 PM PDT 24 155273020 ps
T557 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2008185395 Aug 03 04:36:59 PM PDT 24 Aug 03 04:37:01 PM PDT 24 218583434 ps
T558 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2298571497 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:47 PM PDT 24 187198841 ps
T559 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1729352716 Aug 03 04:36:48 PM PDT 24 Aug 03 04:36:49 PM PDT 24 64439212 ps
T113 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2817089504 Aug 03 04:36:26 PM PDT 24 Aug 03 04:36:28 PM PDT 24 513292149 ps
T560 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1148068525 Aug 03 04:36:42 PM PDT 24 Aug 03 04:36:44 PM PDT 24 158114034 ps
T561 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3187156560 Aug 03 04:36:30 PM PDT 24 Aug 03 04:36:32 PM PDT 24 427335045 ps
T562 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4250596698 Aug 03 04:36:34 PM PDT 24 Aug 03 04:36:35 PM PDT 24 64323524 ps
T563 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3071172214 Aug 03 04:36:15 PM PDT 24 Aug 03 04:36:17 PM PDT 24 428066503 ps
T564 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3933936856 Aug 03 04:36:41 PM PDT 24 Aug 03 04:36:43 PM PDT 24 453289309 ps
T565 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1487211629 Aug 03 04:36:40 PM PDT 24 Aug 03 04:36:42 PM PDT 24 201704939 ps
T566 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3427185024 Aug 03 04:36:44 PM PDT 24 Aug 03 04:36:46 PM PDT 24 405625091 ps
T567 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3118165851 Aug 03 04:36:36 PM PDT 24 Aug 03 04:36:38 PM PDT 24 441664896 ps
T568 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2512954597 Aug 03 04:36:34 PM PDT 24 Aug 03 04:36:36 PM PDT 24 160439639 ps
T569 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4081161883 Aug 03 04:36:37 PM PDT 24 Aug 03 04:36:39 PM PDT 24 237959298 ps
T570 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.608646834 Aug 03 04:36:28 PM PDT 24 Aug 03 04:36:31 PM PDT 24 276455872 ps
T571 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3404745436 Aug 03 04:36:37 PM PDT 24 Aug 03 04:36:38 PM PDT 24 143065580 ps
T572 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1786887879 Aug 03 04:36:40 PM PDT 24 Aug 03 04:36:41 PM PDT 24 73999140 ps
T573 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.781513148 Aug 03 04:36:50 PM PDT 24 Aug 03 04:36:52 PM PDT 24 470419085 ps
T574 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.39706586 Aug 03 04:36:32 PM PDT 24 Aug 03 04:36:34 PM PDT 24 131360116 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1518581055 Aug 03 04:36:28 PM PDT 24 Aug 03 04:36:30 PM PDT 24 141860184 ps
T576 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3519506322 Aug 03 04:36:15 PM PDT 24 Aug 03 04:36:16 PM PDT 24 90775760 ps
T577 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.372050171 Aug 03 04:36:19 PM PDT 24 Aug 03 04:36:28 PM PDT 24 1544047658 ps
T578 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2878072880 Aug 03 04:36:17 PM PDT 24 Aug 03 04:36:18 PM PDT 24 146374539 ps
T579 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3777196836 Aug 03 04:36:39 PM PDT 24 Aug 03 04:36:40 PM PDT 24 127619691 ps
T580 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.264365739 Aug 03 04:36:38 PM PDT 24 Aug 03 04:36:39 PM PDT 24 65113405 ps
T581 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1044742721 Aug 03 04:36:48 PM PDT 24 Aug 03 04:36:49 PM PDT 24 80780877 ps
T582 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.167679548 Aug 03 04:36:14 PM PDT 24 Aug 03 04:36:16 PM PDT 24 219191334 ps
T125 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.522253963 Aug 03 04:36:49 PM PDT 24 Aug 03 04:36:52 PM PDT 24 916242287 ps
T583 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3709677405 Aug 03 04:36:41 PM PDT 24 Aug 03 04:36:43 PM PDT 24 121402292 ps
T584 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1794739672 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:47 PM PDT 24 185481416 ps
T585 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.340712314 Aug 03 04:36:34 PM PDT 24 Aug 03 04:36:35 PM PDT 24 201113488 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2336710337 Aug 03 04:36:28 PM PDT 24 Aug 03 04:36:31 PM PDT 24 502322373 ps
T587 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2453763584 Aug 03 04:36:40 PM PDT 24 Aug 03 04:36:44 PM PDT 24 603538471 ps
T588 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1155962996 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:48 PM PDT 24 166107225 ps
T589 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1080413827 Aug 03 04:36:33 PM PDT 24 Aug 03 04:36:34 PM PDT 24 81778881 ps
T590 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.701360891 Aug 03 04:36:40 PM PDT 24 Aug 03 04:36:41 PM PDT 24 159077703 ps
T591 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1741321098 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:47 PM PDT 24 68908032 ps
T592 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.519285716 Aug 03 04:36:44 PM PDT 24 Aug 03 04:36:45 PM PDT 24 145529652 ps
T114 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3547371156 Aug 03 04:36:50 PM PDT 24 Aug 03 04:36:53 PM PDT 24 907958909 ps
T593 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1218961822 Aug 03 04:36:34 PM PDT 24 Aug 03 04:36:36 PM PDT 24 130707326 ps
T594 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1656584812 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:46 PM PDT 24 125275541 ps
T595 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2675094575 Aug 03 04:36:42 PM PDT 24 Aug 03 04:36:43 PM PDT 24 131362481 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2682299144 Aug 03 04:36:36 PM PDT 24 Aug 03 04:36:45 PM PDT 24 1567164031 ps
T597 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.674933525 Aug 03 04:36:33 PM PDT 24 Aug 03 04:36:34 PM PDT 24 131619203 ps
T598 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1026038336 Aug 03 04:36:53 PM PDT 24 Aug 03 04:36:54 PM PDT 24 121571880 ps
T599 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1348995992 Aug 03 04:36:42 PM PDT 24 Aug 03 04:36:46 PM PDT 24 548624075 ps
T600 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1953979996 Aug 03 04:36:44 PM PDT 24 Aug 03 04:36:45 PM PDT 24 84197807 ps
T601 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3559261257 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:47 PM PDT 24 124995210 ps
T602 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2280359076 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:48 PM PDT 24 889739672 ps
T603 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3746307750 Aug 03 04:36:25 PM PDT 24 Aug 03 04:36:26 PM PDT 24 78442617 ps
T604 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3464514688 Aug 03 04:36:23 PM PDT 24 Aug 03 04:36:25 PM PDT 24 157282682 ps
T605 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4009511236 Aug 03 04:36:39 PM PDT 24 Aug 03 04:36:40 PM PDT 24 158316568 ps
T606 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4191998815 Aug 03 04:36:32 PM PDT 24 Aug 03 04:36:37 PM PDT 24 488043627 ps
T607 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.357388011 Aug 03 04:36:37 PM PDT 24 Aug 03 04:36:38 PM PDT 24 81574722 ps
T608 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.236387505 Aug 03 04:36:32 PM PDT 24 Aug 03 04:36:40 PM PDT 24 1544966735 ps
T609 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3306337733 Aug 03 04:36:34 PM PDT 24 Aug 03 04:36:35 PM PDT 24 75733009 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.811140623 Aug 03 04:36:35 PM PDT 24 Aug 03 04:36:36 PM PDT 24 92281895 ps
T611 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.959189470 Aug 03 04:36:43 PM PDT 24 Aug 03 04:36:45 PM PDT 24 152190321 ps
T612 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3877843319 Aug 03 04:36:39 PM PDT 24 Aug 03 04:36:40 PM PDT 24 103748263 ps
T613 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.242140216 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:46 PM PDT 24 74327403 ps
T614 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1313993194 Aug 03 04:36:50 PM PDT 24 Aug 03 04:36:52 PM PDT 24 481492110 ps
T615 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3024750855 Aug 03 04:36:51 PM PDT 24 Aug 03 04:36:52 PM PDT 24 119521794 ps
T616 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1189389104 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:48 PM PDT 24 199905997 ps
T617 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2728758387 Aug 03 04:36:38 PM PDT 24 Aug 03 04:36:39 PM PDT 24 151912186 ps
T111 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1582090570 Aug 03 04:36:47 PM PDT 24 Aug 03 04:36:49 PM PDT 24 472915701 ps
T618 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2293465632 Aug 03 04:36:42 PM PDT 24 Aug 03 04:36:43 PM PDT 24 123188981 ps
T619 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.268844510 Aug 03 04:36:25 PM PDT 24 Aug 03 04:36:26 PM PDT 24 124541082 ps
T620 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1901032507 Aug 03 04:36:20 PM PDT 24 Aug 03 04:36:22 PM PDT 24 158028671 ps

Test location /workspace/coverage/default/44.rstmgr_stress_all.3564685350
Short name T7
Test name
Test status
Simulation time 12455801888 ps
CPU time 44.05 seconds
Started Aug 03 04:39:51 PM PDT 24
Finished Aug 03 04:40:35 PM PDT 24
Peak memory 200504 kb
Host smart-5dfc3690-ee35-49cd-af84-69aca39f1804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564685350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3564685350
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3889349348
Short name T77
Test name
Test status
Simulation time 202319660 ps
CPU time 1.41 seconds
Started Aug 03 04:39:31 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 200404 kb
Host smart-44fe232d-c258-40fc-9bd8-71f4cb49f003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889349348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3889349348
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.932353737
Short name T59
Test name
Test status
Simulation time 457787655 ps
CPU time 3.28 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 208280 kb
Host smart-82139343-9b7f-440e-8e85-8186ee6641b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932353737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.932353737
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.681109636
Short name T45
Test name
Test status
Simulation time 17050089703 ps
CPU time 24.52 seconds
Started Aug 03 04:38:41 PM PDT 24
Finished Aug 03 04:39:06 PM PDT 24
Peak memory 217260 kb
Host smart-cffa43ec-cf9e-43fa-8bf6-ddcb4a0fc3ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681109636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.681109636
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.285452819
Short name T3
Test name
Test status
Simulation time 2357059447 ps
CPU time 8.68 seconds
Started Aug 03 04:38:50 PM PDT 24
Finished Aug 03 04:38:59 PM PDT 24
Peak memory 217812 kb
Host smart-ac5650b3-9da3-4020-8994-73171a0349f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285452819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.285452819
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1454329163
Short name T61
Test name
Test status
Simulation time 405779776 ps
CPU time 1.83 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 200132 kb
Host smart-5bfdcf41-d40d-498b-b4fd-02a6586674f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454329163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1454329163
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1695368379
Short name T52
Test name
Test status
Simulation time 348251327 ps
CPU time 2.24 seconds
Started Aug 03 04:39:17 PM PDT 24
Finished Aug 03 04:39:20 PM PDT 24
Peak memory 200216 kb
Host smart-17ffe4b8-e93a-444f-b710-28172358caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695368379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1695368379
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1344423400
Short name T132
Test name
Test status
Simulation time 114619649 ps
CPU time 1.04 seconds
Started Aug 03 04:39:19 PM PDT 24
Finished Aug 03 04:39:21 PM PDT 24
Peak memory 200148 kb
Host smart-dceb60e7-425e-417d-b33f-7ded3baf34f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344423400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1344423400
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2926943039
Short name T110
Test name
Test status
Simulation time 787240094 ps
CPU time 2.71 seconds
Started Aug 03 04:36:47 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 200200 kb
Host smart-b7df388f-d65f-452b-a3ca-c7ff81abaf23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926943039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2926943039
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2040624790
Short name T28
Test name
Test status
Simulation time 91998683 ps
CPU time 0.82 seconds
Started Aug 03 04:39:10 PM PDT 24
Finished Aug 03 04:39:11 PM PDT 24
Peak memory 199980 kb
Host smart-439df655-717a-46fb-9c05-08253c658b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040624790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2040624790
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1586733206
Short name T37
Test name
Test status
Simulation time 2362715215 ps
CPU time 8.09 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:50 PM PDT 24
Peak memory 217144 kb
Host smart-394e59ad-1b9a-45dc-ab32-f1f8782fb2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586733206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1586733206
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2201522138
Short name T162
Test name
Test status
Simulation time 162946478 ps
CPU time 1.22 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:45 PM PDT 24
Peak memory 200288 kb
Host smart-2639738a-c45d-4f40-8b10-b9f2bfe1c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201522138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2201522138
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1183748056
Short name T109
Test name
Test status
Simulation time 141400729 ps
CPU time 2 seconds
Started Aug 03 04:36:38 PM PDT 24
Finished Aug 03 04:36:40 PM PDT 24
Peak memory 216288 kb
Host smart-9da39ff4-4504-4399-a26f-9e983655e264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183748056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1183748056
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2564250610
Short name T105
Test name
Test status
Simulation time 167040502 ps
CPU time 1.21 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:45 PM PDT 24
Peak memory 199960 kb
Host smart-a73c6813-cab3-4632-9a98-184c74689843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564250610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2564250610
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2778279303
Short name T22
Test name
Test status
Simulation time 111405037 ps
CPU time 0.87 seconds
Started Aug 03 04:39:10 PM PDT 24
Finished Aug 03 04:39:11 PM PDT 24
Peak memory 199968 kb
Host smart-090cb643-17fe-4165-bce5-57973dc9a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778279303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2778279303
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1582090570
Short name T111
Test name
Test status
Simulation time 472915701 ps
CPU time 1.94 seconds
Started Aug 03 04:36:47 PM PDT 24
Finished Aug 03 04:36:49 PM PDT 24
Peak memory 200152 kb
Host smart-63a28642-e417-4c38-a10d-fe23232eebc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582090570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1582090570
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3547371156
Short name T114
Test name
Test status
Simulation time 907958909 ps
CPU time 2.99 seconds
Started Aug 03 04:36:50 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 200164 kb
Host smart-94b34a09-dc37-45bf-9a84-e65149ee112b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547371156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3547371156
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.70894374
Short name T277
Test name
Test status
Simulation time 123040770 ps
CPU time 1.45 seconds
Started Aug 03 04:38:37 PM PDT 24
Finished Aug 03 04:38:39 PM PDT 24
Peak memory 200216 kb
Host smart-c342e1f6-d041-43d0-a0e5-b5ed9ba6b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70894374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.70894374
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1901032507
Short name T620
Test name
Test status
Simulation time 158028671 ps
CPU time 2.02 seconds
Started Aug 03 04:36:20 PM PDT 24
Finished Aug 03 04:36:22 PM PDT 24
Peak memory 200152 kb
Host smart-4c6de706-b44d-4af2-98dd-95428212764f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901032507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
901032507
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.608646834
Short name T570
Test name
Test status
Simulation time 276455872 ps
CPU time 3.22 seconds
Started Aug 03 04:36:28 PM PDT 24
Finished Aug 03 04:36:31 PM PDT 24
Peak memory 199972 kb
Host smart-043a2598-d55b-4c69-bab3-bcf584479f99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608646834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.608646834
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3519506322
Short name T576
Test name
Test status
Simulation time 90775760 ps
CPU time 0.78 seconds
Started Aug 03 04:36:15 PM PDT 24
Finished Aug 03 04:36:16 PM PDT 24
Peak memory 200036 kb
Host smart-aeec4638-2deb-4507-80da-7cbc00617486
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519506322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
519506322
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.268844510
Short name T619
Test name
Test status
Simulation time 124541082 ps
CPU time 1.25 seconds
Started Aug 03 04:36:25 PM PDT 24
Finished Aug 03 04:36:26 PM PDT 24
Peak memory 208152 kb
Host smart-cb25f7fb-16f0-4c33-bc7c-593a49a01b77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268844510 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.268844510
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1222937339
Short name T544
Test name
Test status
Simulation time 66369713 ps
CPU time 0.78 seconds
Started Aug 03 04:36:14 PM PDT 24
Finished Aug 03 04:36:15 PM PDT 24
Peak memory 199924 kb
Host smart-0d5030af-f716-4ed4-bc34-05ef4c77f427
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222937339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1222937339
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3746307750
Short name T603
Test name
Test status
Simulation time 78442617 ps
CPU time 0.99 seconds
Started Aug 03 04:36:25 PM PDT 24
Finished Aug 03 04:36:26 PM PDT 24
Peak memory 200068 kb
Host smart-6753cb43-5062-4495-b940-aae864b63797
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746307750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3746307750
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.167679548
Short name T582
Test name
Test status
Simulation time 219191334 ps
CPU time 1.69 seconds
Started Aug 03 04:36:14 PM PDT 24
Finished Aug 03 04:36:16 PM PDT 24
Peak memory 208284 kb
Host smart-68521ffb-db66-416e-81f1-e9aec4b5cff8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167679548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.167679548
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3187156560
Short name T561
Test name
Test status
Simulation time 427335045 ps
CPU time 1.78 seconds
Started Aug 03 04:36:30 PM PDT 24
Finished Aug 03 04:36:32 PM PDT 24
Peak memory 200156 kb
Host smart-8a99bcc3-c0bc-4141-8fcf-c22cb1462f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187156560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3187156560
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2934245831
Short name T540
Test name
Test status
Simulation time 97489966 ps
CPU time 1.33 seconds
Started Aug 03 04:36:28 PM PDT 24
Finished Aug 03 04:36:29 PM PDT 24
Peak memory 200024 kb
Host smart-45198eb2-7a2c-4141-bf79-6a17d29356da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934245831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
934245831
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.372050171
Short name T577
Test name
Test status
Simulation time 1544047658 ps
CPU time 8.54 seconds
Started Aug 03 04:36:19 PM PDT 24
Finished Aug 03 04:36:28 PM PDT 24
Peak memory 200132 kb
Host smart-77c1864e-4317-4ae3-a58b-5855c06a5ad4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372050171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.372050171
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2878072880
Short name T578
Test name
Test status
Simulation time 146374539 ps
CPU time 0.96 seconds
Started Aug 03 04:36:17 PM PDT 24
Finished Aug 03 04:36:18 PM PDT 24
Peak memory 199892 kb
Host smart-212d8d30-a7bf-44c8-9add-8deb5c6b03d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878072880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
878072880
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1595564117
Short name T556
Test name
Test status
Simulation time 155273020 ps
CPU time 1.38 seconds
Started Aug 03 04:36:33 PM PDT 24
Finished Aug 03 04:36:35 PM PDT 24
Peak memory 208224 kb
Host smart-25da4f6b-d800-4816-aa62-a36364a61b98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595564117 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1595564117
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2726616539
Short name T552
Test name
Test status
Simulation time 64403335 ps
CPU time 0.8 seconds
Started Aug 03 04:36:15 PM PDT 24
Finished Aug 03 04:36:16 PM PDT 24
Peak memory 199920 kb
Host smart-c7baea69-3cc6-4db2-92d1-b4bc6237720e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726616539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2726616539
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1518581055
Short name T575
Test name
Test status
Simulation time 141860184 ps
CPU time 1.18 seconds
Started Aug 03 04:36:28 PM PDT 24
Finished Aug 03 04:36:30 PM PDT 24
Peak memory 199856 kb
Host smart-8906f4c6-981f-4f85-99c1-4484f1579403
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518581055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1518581055
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3464514688
Short name T604
Test name
Test status
Simulation time 157282682 ps
CPU time 2.22 seconds
Started Aug 03 04:36:23 PM PDT 24
Finished Aug 03 04:36:25 PM PDT 24
Peak memory 216384 kb
Host smart-a25f47b5-5cb6-4319-92a4-35c5dff89cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464514688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3464514688
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.318368723
Short name T86
Test name
Test status
Simulation time 458497343 ps
CPU time 1.84 seconds
Started Aug 03 04:36:17 PM PDT 24
Finished Aug 03 04:36:19 PM PDT 24
Peak memory 200352 kb
Host smart-5fd24b06-0bce-4bf0-869c-9713d3efb0f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318368723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
318368723
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.519285716
Short name T592
Test name
Test status
Simulation time 145529652 ps
CPU time 1.15 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:45 PM PDT 24
Peak memory 208288 kb
Host smart-e33ac918-e3d4-435f-bf6f-e29b9524c173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519285716 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.519285716
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.357388011
Short name T607
Test name
Test status
Simulation time 81574722 ps
CPU time 0.89 seconds
Started Aug 03 04:36:37 PM PDT 24
Finished Aug 03 04:36:38 PM PDT 24
Peak memory 200008 kb
Host smart-8d77b98a-0c95-4c96-9c91-db965ed57a3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357388011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.357388011
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.959189470
Short name T611
Test name
Test status
Simulation time 152190321 ps
CPU time 1.14 seconds
Started Aug 03 04:36:43 PM PDT 24
Finished Aug 03 04:36:45 PM PDT 24
Peak memory 200032 kb
Host smart-c9e6ebfc-d78a-4815-931d-0c8b3d4599fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959189470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.959189470
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3374923481
Short name T84
Test name
Test status
Simulation time 293610153 ps
CPU time 1.93 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 208244 kb
Host smart-e9f4f253-ab9d-4620-8cc6-a4b38d452325
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374923481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3374923481
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3118165851
Short name T567
Test name
Test status
Simulation time 441664896 ps
CPU time 1.73 seconds
Started Aug 03 04:36:36 PM PDT 24
Finished Aug 03 04:36:38 PM PDT 24
Peak memory 200208 kb
Host smart-7c59b8cf-8ce4-4040-9edf-711f5a80dd27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118165851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3118165851
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3033856336
Short name T549
Test name
Test status
Simulation time 124872762 ps
CPU time 1 seconds
Started Aug 03 04:36:43 PM PDT 24
Finished Aug 03 04:36:44 PM PDT 24
Peak memory 200148 kb
Host smart-f69ad74e-e477-46e8-9184-46083bc96bb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033856336 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3033856336
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.504305486
Short name T95
Test name
Test status
Simulation time 83735912 ps
CPU time 0.82 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:56 PM PDT 24
Peak memory 199920 kb
Host smart-11c0466d-2c49-425f-b131-0ae85c38da2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504305486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.504305486
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2453763584
Short name T587
Test name
Test status
Simulation time 603538471 ps
CPU time 3.48 seconds
Started Aug 03 04:36:40 PM PDT 24
Finished Aug 03 04:36:44 PM PDT 24
Peak memory 216448 kb
Host smart-e2b9ab04-fdee-488a-aa5c-8b63edf83e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453763584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2453763584
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2675094575
Short name T595
Test name
Test status
Simulation time 131362481 ps
CPU time 1.24 seconds
Started Aug 03 04:36:42 PM PDT 24
Finished Aug 03 04:36:43 PM PDT 24
Peak memory 208300 kb
Host smart-c00a3c27-5d68-45bc-a337-454d7a3d1aea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675094575 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2675094575
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2611809589
Short name T543
Test name
Test status
Simulation time 93814829 ps
CPU time 0.94 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 199984 kb
Host smart-ce5aac2b-147c-4a98-a496-10c3d758caca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611809589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2611809589
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1108980498
Short name T106
Test name
Test status
Simulation time 207193521 ps
CPU time 1.57 seconds
Started Aug 03 04:36:41 PM PDT 24
Finished Aug 03 04:36:42 PM PDT 24
Peak memory 200156 kb
Host smart-f0565573-4e95-4757-912e-9e44b3630eb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108980498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1108980498
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1313993194
Short name T614
Test name
Test status
Simulation time 481492110 ps
CPU time 1.85 seconds
Started Aug 03 04:36:50 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 200032 kb
Host smart-381bb876-070f-4334-af89-837aba463151
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313993194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1313993194
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3024750855
Short name T615
Test name
Test status
Simulation time 119521794 ps
CPU time 1.34 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 208196 kb
Host smart-752b2fff-2144-459b-801f-f44d1dbd1b22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024750855 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3024750855
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1729352716
Short name T559
Test name
Test status
Simulation time 64439212 ps
CPU time 0.85 seconds
Started Aug 03 04:36:48 PM PDT 24
Finished Aug 03 04:36:49 PM PDT 24
Peak memory 199940 kb
Host smart-e7cc2c69-5757-40ef-a959-9e189aabea4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729352716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1729352716
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1656584812
Short name T594
Test name
Test status
Simulation time 125275541 ps
CPU time 1.28 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 200108 kb
Host smart-c336f0ba-3ccf-432a-b387-9a1174269a74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656584812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1656584812
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.4192143392
Short name T58
Test name
Test status
Simulation time 142537259 ps
CPU time 1.9 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 208252 kb
Host smart-acfdc590-d442-462e-b374-ffa7318be480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192143392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.4192143392
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3443518679
Short name T115
Test name
Test status
Simulation time 136203407 ps
CPU time 1.38 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 208320 kb
Host smart-04ad5c0d-c9ba-41f7-a46e-88b2480164c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443518679 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3443518679
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2478988636
Short name T551
Test name
Test status
Simulation time 85994701 ps
CPU time 0.88 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:45 PM PDT 24
Peak memory 199928 kb
Host smart-ef43bf44-6dcb-44e9-829d-640c179ab51a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478988636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2478988636
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2008185395
Short name T557
Test name
Test status
Simulation time 218583434 ps
CPU time 1.43 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:01 PM PDT 24
Peak memory 200112 kb
Host smart-7371b187-43b4-48d0-a9a4-1aa2d401acbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008185395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2008185395
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3013212389
Short name T550
Test name
Test status
Simulation time 377204294 ps
CPU time 2.7 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 208256 kb
Host smart-1aab1177-0d9d-4d0c-a255-ac8372f7fc90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013212389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3013212389
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2280359076
Short name T602
Test name
Test status
Simulation time 889739672 ps
CPU time 3.09 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:48 PM PDT 24
Peak memory 200180 kb
Host smart-be323335-1526-4e5a-a575-ed592efdf28f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280359076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2280359076
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3559261257
Short name T601
Test name
Test status
Simulation time 124995210 ps
CPU time 0.96 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 200080 kb
Host smart-132706ec-a516-434a-a550-4ada153698f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559261257 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3559261257
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.242140216
Short name T613
Test name
Test status
Simulation time 74327403 ps
CPU time 0.82 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 199992 kb
Host smart-c2274309-f377-4831-a694-624402d8422f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242140216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.242140216
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2293465632
Short name T618
Test name
Test status
Simulation time 123188981 ps
CPU time 1.09 seconds
Started Aug 03 04:36:42 PM PDT 24
Finished Aug 03 04:36:43 PM PDT 24
Peak memory 199964 kb
Host smart-ef9c9e92-06b0-44de-9a97-d72324c9f757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293465632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2293465632
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2078363053
Short name T85
Test name
Test status
Simulation time 348953676 ps
CPU time 2.36 seconds
Started Aug 03 04:36:47 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 208324 kb
Host smart-62626ca2-004e-434e-b834-755a6864b3cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078363053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2078363053
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1189389104
Short name T616
Test name
Test status
Simulation time 199905997 ps
CPU time 2.01 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:48 PM PDT 24
Peak memory 208428 kb
Host smart-9ea15f4e-f073-4621-b3ad-126384b3f137
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189389104 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1189389104
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3885135666
Short name T102
Test name
Test status
Simulation time 71113148 ps
CPU time 0.83 seconds
Started Aug 03 04:36:41 PM PDT 24
Finished Aug 03 04:36:42 PM PDT 24
Peak memory 199936 kb
Host smart-14a983ea-0e32-4493-b838-8e893c40b28d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885135666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3885135666
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1044742721
Short name T581
Test name
Test status
Simulation time 80780877 ps
CPU time 0.99 seconds
Started Aug 03 04:36:48 PM PDT 24
Finished Aug 03 04:36:49 PM PDT 24
Peak memory 200000 kb
Host smart-66b746f5-4885-4f48-80e5-0ffd840322cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044742721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1044742721
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2298571497
Short name T558
Test name
Test status
Simulation time 187198841 ps
CPU time 1.44 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 200000 kb
Host smart-5c7a5951-56af-45cf-a2d2-4d3de6277f12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298571497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2298571497
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1727658283
Short name T555
Test name
Test status
Simulation time 882785696 ps
CPU time 2.95 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:49 PM PDT 24
Peak memory 200172 kb
Host smart-1faa538c-f46c-4191-a299-1b43ba81d0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727658283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1727658283
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2884917934
Short name T546
Test name
Test status
Simulation time 114489018 ps
CPU time 0.92 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 200104 kb
Host smart-52483971-5d9a-410b-b73f-a86dc42f3dfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884917934 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2884917934
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.964375214
Short name T104
Test name
Test status
Simulation time 60232885 ps
CPU time 0.91 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 199912 kb
Host smart-2c3b1d99-08b9-4a6c-92d6-46465f2d1f81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964375214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.964375214
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.607884724
Short name T107
Test name
Test status
Simulation time 123689809 ps
CPU time 1.04 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 200072 kb
Host smart-2d2f9073-82ee-47c5-b120-2c8f0d81e59c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607884724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.607884724
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.522253963
Short name T125
Test name
Test status
Simulation time 916242287 ps
CPU time 3.58 seconds
Started Aug 03 04:36:49 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 200000 kb
Host smart-8bc6e6d7-40a7-4c06-9269-2e9247e73c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522253963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.522253963
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1487211629
Short name T565
Test name
Test status
Simulation time 201704939 ps
CPU time 1.95 seconds
Started Aug 03 04:36:40 PM PDT 24
Finished Aug 03 04:36:42 PM PDT 24
Peak memory 208268 kb
Host smart-5c353395-fa23-4034-b269-52c13a0f869c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487211629 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1487211629
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3949409970
Short name T108
Test name
Test status
Simulation time 85984925 ps
CPU time 0.83 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 200012 kb
Host smart-ef4e815c-95d8-45e1-a258-a2ad61698cbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949409970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3949409970
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.701360891
Short name T590
Test name
Test status
Simulation time 159077703 ps
CPU time 1.16 seconds
Started Aug 03 04:36:40 PM PDT 24
Finished Aug 03 04:36:41 PM PDT 24
Peak memory 200076 kb
Host smart-ee15b35d-edb7-46e5-b987-03a9ba59fba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701360891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.701360891
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1348995992
Short name T599
Test name
Test status
Simulation time 548624075 ps
CPU time 3.61 seconds
Started Aug 03 04:36:42 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 208268 kb
Host smart-0af57d24-7dd6-4222-a9a9-b4411aea4d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348995992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1348995992
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1318936411
Short name T88
Test name
Test status
Simulation time 994084432 ps
CPU time 3.09 seconds
Started Aug 03 04:36:42 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 200136 kb
Host smart-630db067-96c0-48a8-a381-49f0e0bdbbb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318936411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1318936411
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1218961822
Short name T593
Test name
Test status
Simulation time 130707326 ps
CPU time 1.54 seconds
Started Aug 03 04:36:34 PM PDT 24
Finished Aug 03 04:36:36 PM PDT 24
Peak memory 208344 kb
Host smart-d6feaeba-aef3-4e17-a05b-275ae14e2b6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218961822 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1218961822
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1953979996
Short name T600
Test name
Test status
Simulation time 84197807 ps
CPU time 0.87 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:45 PM PDT 24
Peak memory 200012 kb
Host smart-04ce2e36-084d-4d27-af4b-418114c17f7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953979996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1953979996
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.207730027
Short name T56
Test name
Test status
Simulation time 224290435 ps
CPU time 1.52 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 200076 kb
Host smart-b53688aa-cd11-47c5-8280-25393681c4ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207730027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.207730027
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4009511236
Short name T605
Test name
Test status
Simulation time 158316568 ps
CPU time 1.34 seconds
Started Aug 03 04:36:39 PM PDT 24
Finished Aug 03 04:36:40 PM PDT 24
Peak memory 208220 kb
Host smart-0515bca5-4407-46bb-ae7b-f0f6045cc474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009511236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4009511236
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3284881062
Short name T542
Test name
Test status
Simulation time 112403217 ps
CPU time 1.35 seconds
Started Aug 03 04:36:38 PM PDT 24
Finished Aug 03 04:36:40 PM PDT 24
Peak memory 200140 kb
Host smart-f9fea2f5-697c-4f5e-9c25-ec9728f3a527
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284881062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
284881062
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.236387505
Short name T608
Test name
Test status
Simulation time 1544966735 ps
CPU time 8.38 seconds
Started Aug 03 04:36:32 PM PDT 24
Finished Aug 03 04:36:40 PM PDT 24
Peak memory 200148 kb
Host smart-8ada6646-7b64-4f83-8225-455331fe49f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236387505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.236387505
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2728758387
Short name T617
Test name
Test status
Simulation time 151912186 ps
CPU time 1.05 seconds
Started Aug 03 04:36:38 PM PDT 24
Finished Aug 03 04:36:39 PM PDT 24
Peak memory 199920 kb
Host smart-3ea8c6df-859b-4ecd-8805-97b9d2b05e10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728758387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
728758387
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.674933525
Short name T597
Test name
Test status
Simulation time 131619203 ps
CPU time 1.34 seconds
Started Aug 03 04:36:33 PM PDT 24
Finished Aug 03 04:36:34 PM PDT 24
Peak memory 208200 kb
Host smart-f49878d4-9699-4cf7-ae97-6aed04d0c3a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674933525 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.674933525
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2676998727
Short name T103
Test name
Test status
Simulation time 83399755 ps
CPU time 0.87 seconds
Started Aug 03 04:36:30 PM PDT 24
Finished Aug 03 04:36:31 PM PDT 24
Peak memory 199924 kb
Host smart-f64d855e-f91e-4306-b978-065462002b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676998727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2676998727
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.39706586
Short name T574
Test name
Test status
Simulation time 131360116 ps
CPU time 1.33 seconds
Started Aug 03 04:36:32 PM PDT 24
Finished Aug 03 04:36:34 PM PDT 24
Peak memory 200156 kb
Host smart-cf0641c4-7cf4-473d-ada3-967072160401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39706586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same
_csr_outstanding.39706586
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1185364246
Short name T83
Test name
Test status
Simulation time 167958731 ps
CPU time 1.45 seconds
Started Aug 03 04:36:28 PM PDT 24
Finished Aug 03 04:36:30 PM PDT 24
Peak memory 208096 kb
Host smart-98bb6bbe-8828-465c-b2f6-c816f804b376
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185364246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1185364246
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3071172214
Short name T563
Test name
Test status
Simulation time 428066503 ps
CPU time 1.99 seconds
Started Aug 03 04:36:15 PM PDT 24
Finished Aug 03 04:36:17 PM PDT 24
Peak memory 208332 kb
Host smart-1dd3e0de-06a1-49dd-aada-6be6dd13c86c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071172214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3071172214
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.717559103
Short name T554
Test name
Test status
Simulation time 450248787 ps
CPU time 2.85 seconds
Started Aug 03 04:36:29 PM PDT 24
Finished Aug 03 04:36:32 PM PDT 24
Peak memory 200012 kb
Host smart-9c33b4a9-e02d-428d-bcae-88a1f40c5d93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717559103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.717559103
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2682299144
Short name T596
Test name
Test status
Simulation time 1567164031 ps
CPU time 8.1 seconds
Started Aug 03 04:36:36 PM PDT 24
Finished Aug 03 04:36:45 PM PDT 24
Peak memory 200104 kb
Host smart-d76af92e-6a64-414d-a89e-3f4b5020d390
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682299144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
682299144
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.811140623
Short name T610
Test name
Test status
Simulation time 92281895 ps
CPU time 0.84 seconds
Started Aug 03 04:36:35 PM PDT 24
Finished Aug 03 04:36:36 PM PDT 24
Peak memory 199800 kb
Host smart-a5a9ede7-dc06-4830-9576-054786d75720
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811140623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.811140623
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3404745436
Short name T571
Test name
Test status
Simulation time 143065580 ps
CPU time 1.09 seconds
Started Aug 03 04:36:37 PM PDT 24
Finished Aug 03 04:36:38 PM PDT 24
Peak memory 200140 kb
Host smart-cc400bdf-5aa1-449c-95aa-42adad5649f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404745436 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3404745436
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1024895121
Short name T55
Test name
Test status
Simulation time 78366558 ps
CPU time 0.84 seconds
Started Aug 03 04:36:40 PM PDT 24
Finished Aug 03 04:36:41 PM PDT 24
Peak memory 199956 kb
Host smart-adc0a5b9-1cf8-48e4-9fe2-4b008d03d644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024895121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1024895121
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2512954597
Short name T568
Test name
Test status
Simulation time 160439639 ps
CPU time 1.28 seconds
Started Aug 03 04:36:34 PM PDT 24
Finished Aug 03 04:36:36 PM PDT 24
Peak memory 199952 kb
Host smart-c5f92141-de5b-4f68-a457-ad95d8645cea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512954597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2512954597
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2336710337
Short name T586
Test name
Test status
Simulation time 502322373 ps
CPU time 3.38 seconds
Started Aug 03 04:36:28 PM PDT 24
Finished Aug 03 04:36:31 PM PDT 24
Peak memory 208124 kb
Host smart-f1d55fbc-76a7-42cd-a358-95b66ac6180b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336710337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2336710337
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2817089504
Short name T113
Test name
Test status
Simulation time 513292149 ps
CPU time 2.16 seconds
Started Aug 03 04:36:26 PM PDT 24
Finished Aug 03 04:36:28 PM PDT 24
Peak memory 200160 kb
Host smart-cf959540-6163-469d-8d1c-8e539d39b36e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817089504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2817089504
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1148068525
Short name T560
Test name
Test status
Simulation time 158114034 ps
CPU time 1.77 seconds
Started Aug 03 04:36:42 PM PDT 24
Finished Aug 03 04:36:44 PM PDT 24
Peak memory 200012 kb
Host smart-00708473-3fc2-4631-82df-07eafc2e87b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148068525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
148068525
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4191998815
Short name T606
Test name
Test status
Simulation time 488043627 ps
CPU time 5.68 seconds
Started Aug 03 04:36:32 PM PDT 24
Finished Aug 03 04:36:37 PM PDT 24
Peak memory 199928 kb
Host smart-386468ae-7661-4733-b5e6-0618e98e3cb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191998815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
191998815
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1149227853
Short name T539
Test name
Test status
Simulation time 140907956 ps
CPU time 0.91 seconds
Started Aug 03 04:36:31 PM PDT 24
Finished Aug 03 04:36:32 PM PDT 24
Peak memory 199948 kb
Host smart-e803610e-62c5-425f-8d52-ac1e41650254
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149227853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
149227853
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.756154906
Short name T89
Test name
Test status
Simulation time 134452152 ps
CPU time 1.02 seconds
Started Aug 03 04:36:35 PM PDT 24
Finished Aug 03 04:36:36 PM PDT 24
Peak memory 200440 kb
Host smart-b883b745-4929-4499-b47f-793b14380fcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756154906 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.756154906
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3306337733
Short name T609
Test name
Test status
Simulation time 75733009 ps
CPU time 0.84 seconds
Started Aug 03 04:36:34 PM PDT 24
Finished Aug 03 04:36:35 PM PDT 24
Peak memory 199996 kb
Host smart-38448a77-5118-4d4a-a6a2-22331840e6f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306337733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3306337733
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2380498563
Short name T54
Test name
Test status
Simulation time 249695852 ps
CPU time 1.67 seconds
Started Aug 03 04:36:34 PM PDT 24
Finished Aug 03 04:36:36 PM PDT 24
Peak memory 200196 kb
Host smart-c74b84d3-0e24-4078-a7e5-61992b4339e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380498563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2380498563
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4081161883
Short name T569
Test name
Test status
Simulation time 237959298 ps
CPU time 1.93 seconds
Started Aug 03 04:36:37 PM PDT 24
Finished Aug 03 04:36:39 PM PDT 24
Peak memory 208252 kb
Host smart-064f0be4-4766-49dd-90cc-69d311a84b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081161883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.4081161883
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3427185024
Short name T566
Test name
Test status
Simulation time 405625091 ps
CPU time 1.64 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 200096 kb
Host smart-1bb907de-26f6-4f3f-b66f-6b7a6102dcb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427185024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3427185024
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3777196836
Short name T579
Test name
Test status
Simulation time 127619691 ps
CPU time 1.24 seconds
Started Aug 03 04:36:39 PM PDT 24
Finished Aug 03 04:36:40 PM PDT 24
Peak memory 208244 kb
Host smart-7c73de1f-2dec-4524-bccf-1ffcf8ea56f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777196836 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3777196836
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4250596698
Short name T562
Test name
Test status
Simulation time 64323524 ps
CPU time 0.83 seconds
Started Aug 03 04:36:34 PM PDT 24
Finished Aug 03 04:36:35 PM PDT 24
Peak memory 199860 kb
Host smart-5c47536a-8744-4286-a6b5-db40d0f49eed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250596698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.4250596698
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3635430292
Short name T547
Test name
Test status
Simulation time 118151722 ps
CPU time 1.18 seconds
Started Aug 03 04:36:33 PM PDT 24
Finished Aug 03 04:36:34 PM PDT 24
Peak memory 199996 kb
Host smart-9356c181-d515-471b-a887-7fdde5362c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635430292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3635430292
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3709677405
Short name T583
Test name
Test status
Simulation time 121402292 ps
CPU time 1.54 seconds
Started Aug 03 04:36:41 PM PDT 24
Finished Aug 03 04:36:43 PM PDT 24
Peak memory 216396 kb
Host smart-2f79ce2f-4c5a-4c07-941b-ccf3d242b8ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709677405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3709677405
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2864059913
Short name T548
Test name
Test status
Simulation time 920461900 ps
CPU time 3.64 seconds
Started Aug 03 04:36:36 PM PDT 24
Finished Aug 03 04:36:39 PM PDT 24
Peak memory 200156 kb
Host smart-43b32f57-bc18-4b76-9de0-c32a2bf59e5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864059913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2864059913
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1026038336
Short name T598
Test name
Test status
Simulation time 121571880 ps
CPU time 0.96 seconds
Started Aug 03 04:36:53 PM PDT 24
Finished Aug 03 04:36:54 PM PDT 24
Peak memory 200064 kb
Host smart-07b10a5d-eab3-45da-97e1-9c1abbc5a777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026038336 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1026038336
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.264365739
Short name T580
Test name
Test status
Simulation time 65113405 ps
CPU time 0.79 seconds
Started Aug 03 04:36:38 PM PDT 24
Finished Aug 03 04:36:39 PM PDT 24
Peak memory 200016 kb
Host smart-f2def433-3878-4fac-b321-845514573df5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264365739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.264365739
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2886834705
Short name T545
Test name
Test status
Simulation time 254208703 ps
CPU time 1.71 seconds
Started Aug 03 04:36:40 PM PDT 24
Finished Aug 03 04:36:42 PM PDT 24
Peak memory 200076 kb
Host smart-f8865d86-6009-4758-9c15-42f6c0275505
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886834705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2886834705
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4042988562
Short name T60
Test name
Test status
Simulation time 133455034 ps
CPU time 1.8 seconds
Started Aug 03 04:36:32 PM PDT 24
Finished Aug 03 04:36:34 PM PDT 24
Peak memory 208276 kb
Host smart-820230e6-ed79-4bd9-8939-d1d8e7ad390c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042988562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4042988562
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.488930555
Short name T112
Test name
Test status
Simulation time 436739245 ps
CPU time 1.7 seconds
Started Aug 03 04:36:40 PM PDT 24
Finished Aug 03 04:36:42 PM PDT 24
Peak memory 200092 kb
Host smart-f6357912-8c3a-42a1-bcb8-446fbf4f3976
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488930555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
488930555
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1353810703
Short name T67
Test name
Test status
Simulation time 121526103 ps
CPU time 1.22 seconds
Started Aug 03 04:36:34 PM PDT 24
Finished Aug 03 04:36:35 PM PDT 24
Peak memory 208188 kb
Host smart-8f921849-bc0d-4db7-8a07-70a5ec1ed8f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353810703 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1353810703
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1080413827
Short name T589
Test name
Test status
Simulation time 81778881 ps
CPU time 0.85 seconds
Started Aug 03 04:36:33 PM PDT 24
Finished Aug 03 04:36:34 PM PDT 24
Peak memory 199992 kb
Host smart-2dccf323-0ca1-4162-86e0-76d166eb0b59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080413827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1080413827
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1794739672
Short name T584
Test name
Test status
Simulation time 185481416 ps
CPU time 1.4 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 200112 kb
Host smart-a4184fcf-f11a-48c6-99a5-8e4423656cb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794739672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1794739672
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3877843319
Short name T612
Test name
Test status
Simulation time 103748263 ps
CPU time 1.51 seconds
Started Aug 03 04:36:39 PM PDT 24
Finished Aug 03 04:36:40 PM PDT 24
Peak memory 208212 kb
Host smart-30591c45-4b31-49f9-bf36-f26a71ed900a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877843319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3877843319
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.781513148
Short name T573
Test name
Test status
Simulation time 470419085 ps
CPU time 2.2 seconds
Started Aug 03 04:36:50 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 200112 kb
Host smart-33556552-bc7b-4865-b7bd-fdfce538a185
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781513148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
781513148
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1155962996
Short name T588
Test name
Test status
Simulation time 166107225 ps
CPU time 1.45 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:48 PM PDT 24
Peak memory 208296 kb
Host smart-173993b2-2af8-4626-87a7-501f6a6b27f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155962996 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1155962996
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1741321098
Short name T591
Test name
Test status
Simulation time 68908032 ps
CPU time 0.79 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 199868 kb
Host smart-656a0fce-e626-403f-bdc4-757c7467692f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741321098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1741321098
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4087002403
Short name T53
Test name
Test status
Simulation time 104611860 ps
CPU time 1.19 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 200220 kb
Host smart-3d24caf7-61bd-4f91-b557-2ec401bf95dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087002403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.4087002403
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3529312993
Short name T87
Test name
Test status
Simulation time 393956923 ps
CPU time 2.88 seconds
Started Aug 03 04:36:43 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 212592 kb
Host smart-92ecfa36-1b65-4866-8daf-48813e6cfcaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529312993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3529312993
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3933936856
Short name T564
Test name
Test status
Simulation time 453289309 ps
CPU time 1.9 seconds
Started Aug 03 04:36:41 PM PDT 24
Finished Aug 03 04:36:43 PM PDT 24
Peak memory 200236 kb
Host smart-ef2c3f77-5107-4ef1-903d-cc8f83c1005a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933936856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3933936856
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.340712314
Short name T585
Test name
Test status
Simulation time 201113488 ps
CPU time 1.24 seconds
Started Aug 03 04:36:34 PM PDT 24
Finished Aug 03 04:36:35 PM PDT 24
Peak memory 200100 kb
Host smart-1b31cf91-6438-42fa-ad28-8952b6f48a1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340712314 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.340712314
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1786887879
Short name T572
Test name
Test status
Simulation time 73999140 ps
CPU time 0.84 seconds
Started Aug 03 04:36:40 PM PDT 24
Finished Aug 03 04:36:41 PM PDT 24
Peak memory 200000 kb
Host smart-60519a47-0b7a-4a10-9632-b99248d41992
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786887879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1786887879
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1182596643
Short name T541
Test name
Test status
Simulation time 112412639 ps
CPU time 1.34 seconds
Started Aug 03 04:36:34 PM PDT 24
Finished Aug 03 04:36:35 PM PDT 24
Peak memory 199944 kb
Host smart-b0d45138-ce16-4f15-83ce-2e489c75d14d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182596643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1182596643
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1653342264
Short name T553
Test name
Test status
Simulation time 449360424 ps
CPU time 2.89 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 208152 kb
Host smart-bdf01199-d242-4d9a-bdb2-5cdf31134381
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653342264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1653342264
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3469231349
Short name T68
Test name
Test status
Simulation time 938154662 ps
CPU time 3.07 seconds
Started Aug 03 04:36:32 PM PDT 24
Finished Aug 03 04:36:36 PM PDT 24
Peak memory 200180 kb
Host smart-f944dc04-738f-4b33-9437-0306df26131f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469231349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3469231349
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.4252510771
Short name T389
Test name
Test status
Simulation time 60916051 ps
CPU time 0.74 seconds
Started Aug 03 04:38:48 PM PDT 24
Finished Aug 03 04:38:49 PM PDT 24
Peak memory 200068 kb
Host smart-a847b852-11e0-420a-983d-91b09b899dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252510771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4252510771
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3334955022
Short name T310
Test name
Test status
Simulation time 2181539030 ps
CPU time 7.57 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:51 PM PDT 24
Peak memory 217688 kb
Host smart-ba26b007-2a99-410a-bed5-50a14cf2aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334955022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3334955022
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3805672058
Short name T283
Test name
Test status
Simulation time 244498126 ps
CPU time 1.09 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:43 PM PDT 24
Peak memory 217436 kb
Host smart-984ca0d0-a9f8-4377-8d2c-855a42898b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805672058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3805672058
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1373184492
Short name T520
Test name
Test status
Simulation time 220291021 ps
CPU time 0.96 seconds
Started Aug 03 04:38:39 PM PDT 24
Finished Aug 03 04:38:40 PM PDT 24
Peak memory 200100 kb
Host smart-1fd0f4b2-fec6-41cf-9d36-6e384d5ab5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373184492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1373184492
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1655892080
Short name T236
Test name
Test status
Simulation time 1034702170 ps
CPU time 5.35 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:48 PM PDT 24
Peak memory 200352 kb
Host smart-b98bc56d-d871-44ad-a110-495b83c282c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655892080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1655892080
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1318930387
Short name T62
Test name
Test status
Simulation time 16502919457 ps
CPU time 27.52 seconds
Started Aug 03 04:38:44 PM PDT 24
Finished Aug 03 04:39:12 PM PDT 24
Peak memory 218192 kb
Host smart-08cb7815-d492-4576-94ed-75851c6b9f72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318930387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1318930387
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2028005517
Short name T532
Test name
Test status
Simulation time 99661933 ps
CPU time 0.95 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:44 PM PDT 24
Peak memory 200188 kb
Host smart-12486031-d788-4ba5-8f11-c36227197552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028005517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2028005517
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1905240398
Short name T121
Test name
Test status
Simulation time 260576963 ps
CPU time 1.49 seconds
Started Aug 03 04:38:39 PM PDT 24
Finished Aug 03 04:38:41 PM PDT 24
Peak memory 200440 kb
Host smart-d5444d8f-0fdc-4c03-b5b6-6a0c385b02ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905240398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1905240398
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1495865186
Short name T356
Test name
Test status
Simulation time 1034988745 ps
CPU time 5.03 seconds
Started Aug 03 04:38:40 PM PDT 24
Finished Aug 03 04:38:45 PM PDT 24
Peak memory 200368 kb
Host smart-66d41f94-2218-4479-8411-6b8f9f351829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495865186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1495865186
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3845095435
Short name T353
Test name
Test status
Simulation time 87527423 ps
CPU time 0.87 seconds
Started Aug 03 04:38:40 PM PDT 24
Finished Aug 03 04:38:41 PM PDT 24
Peak memory 200284 kb
Host smart-a2119f12-38ba-45b1-a52d-e6ad20c3d09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845095435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3845095435
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.567584467
Short name T225
Test name
Test status
Simulation time 74771580 ps
CPU time 0.76 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:48 PM PDT 24
Peak memory 200104 kb
Host smart-961fec31-7aa2-4614-958e-717e96f985d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567584467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.567584467
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.782138961
Short name T34
Test name
Test status
Simulation time 1891135160 ps
CPU time 8.07 seconds
Started Aug 03 04:38:41 PM PDT 24
Finished Aug 03 04:38:49 PM PDT 24
Peak memory 216848 kb
Host smart-a82eebba-7db3-414a-ba0f-790e5335737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782138961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.782138961
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1190995098
Short name T490
Test name
Test status
Simulation time 243701774 ps
CPU time 1.1 seconds
Started Aug 03 04:38:40 PM PDT 24
Finished Aug 03 04:38:41 PM PDT 24
Peak memory 217292 kb
Host smart-acd01b8f-05bc-4aa4-84cb-c7095bd20d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190995098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1190995098
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3563171962
Short name T388
Test name
Test status
Simulation time 202782630 ps
CPU time 0.87 seconds
Started Aug 03 04:38:41 PM PDT 24
Finished Aug 03 04:38:42 PM PDT 24
Peak memory 200100 kb
Host smart-0ac83b2b-1cc6-4d1d-a088-13d1660ae9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563171962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3563171962
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3650814461
Short name T529
Test name
Test status
Simulation time 1411296496 ps
CPU time 5.63 seconds
Started Aug 03 04:38:41 PM PDT 24
Finished Aug 03 04:38:47 PM PDT 24
Peak memory 200388 kb
Host smart-052bd27b-15ba-4534-b414-7c5c76f4ec46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650814461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3650814461
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3875181086
Short name T63
Test name
Test status
Simulation time 16521710457 ps
CPU time 26.96 seconds
Started Aug 03 04:38:44 PM PDT 24
Finished Aug 03 04:39:12 PM PDT 24
Peak memory 217204 kb
Host smart-77b0b118-1bb9-43c0-ad1a-c8363ea7651f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875181086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3875181086
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.332120142
Short name T143
Test name
Test status
Simulation time 109273266 ps
CPU time 0.96 seconds
Started Aug 03 04:38:40 PM PDT 24
Finished Aug 03 04:38:41 PM PDT 24
Peak memory 200284 kb
Host smart-a5f9fb95-30a9-4dfc-b864-0b486e1b663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332120142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.332120142
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.854243393
Short name T487
Test name
Test status
Simulation time 123523712 ps
CPU time 1.16 seconds
Started Aug 03 04:38:38 PM PDT 24
Finished Aug 03 04:38:39 PM PDT 24
Peak memory 200404 kb
Host smart-9acb9bc6-72b3-4a5c-9868-775a16321319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854243393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.854243393
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1021077135
Short name T80
Test name
Test status
Simulation time 11215784959 ps
CPU time 39.28 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:39:21 PM PDT 24
Peak memory 200552 kb
Host smart-9c188b5d-6859-44c4-b389-9bc3f8cb8c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021077135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1021077135
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1165796903
Short name T304
Test name
Test status
Simulation time 364955539 ps
CPU time 2.13 seconds
Started Aug 03 04:38:36 PM PDT 24
Finished Aug 03 04:38:38 PM PDT 24
Peak memory 200080 kb
Host smart-cc591395-1d06-41dc-a9b6-42a875ee94ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165796903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1165796903
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.29737681
Short name T331
Test name
Test status
Simulation time 78120138 ps
CPU time 0.85 seconds
Started Aug 03 04:39:09 PM PDT 24
Finished Aug 03 04:39:10 PM PDT 24
Peak memory 200088 kb
Host smart-6faf3981-45b6-41f3-bdb5-2defa6d41c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29737681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.29737681
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3978189919
Short name T41
Test name
Test status
Simulation time 2349975624 ps
CPU time 8.02 seconds
Started Aug 03 04:39:06 PM PDT 24
Finished Aug 03 04:39:14 PM PDT 24
Peak memory 217860 kb
Host smart-1dda852f-3df5-4f2e-950e-ed44eed7e13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978189919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3978189919
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.345972015
Short name T410
Test name
Test status
Simulation time 244527931 ps
CPU time 1.11 seconds
Started Aug 03 04:38:56 PM PDT 24
Finished Aug 03 04:38:58 PM PDT 24
Peak memory 217420 kb
Host smart-a5207ac3-c896-4fd9-883f-2029c2ceb47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345972015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.345972015
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3539203966
Short name T91
Test name
Test status
Simulation time 1652871867 ps
CPU time 6.38 seconds
Started Aug 03 04:38:58 PM PDT 24
Finished Aug 03 04:39:04 PM PDT 24
Peak memory 200544 kb
Host smart-c2f64c26-cadb-43da-88bb-34d45934b6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539203966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3539203966
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.83579056
Short name T11
Test name
Test status
Simulation time 114485341 ps
CPU time 1 seconds
Started Aug 03 04:38:54 PM PDT 24
Finished Aug 03 04:38:55 PM PDT 24
Peak memory 200296 kb
Host smart-9325481e-a9c9-4388-a5d4-7de15a6d039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83579056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.83579056
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3423068137
Short name T124
Test name
Test status
Simulation time 255858180 ps
CPU time 1.56 seconds
Started Aug 03 04:39:19 PM PDT 24
Finished Aug 03 04:39:20 PM PDT 24
Peak memory 200400 kb
Host smart-ddd59f55-ded1-4da2-8e66-33ee4e5ab8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423068137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3423068137
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.180780859
Short name T27
Test name
Test status
Simulation time 5344982821 ps
CPU time 25.18 seconds
Started Aug 03 04:39:27 PM PDT 24
Finished Aug 03 04:39:53 PM PDT 24
Peak memory 200572 kb
Host smart-35deccd8-8b32-4f66-8f5d-649ba92e3bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180780859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.180780859
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1169622132
Short name T459
Test name
Test status
Simulation time 530542413 ps
CPU time 2.91 seconds
Started Aug 03 04:39:00 PM PDT 24
Finished Aug 03 04:39:03 PM PDT 24
Peak memory 200220 kb
Host smart-ea532306-ca3f-4cca-828a-b05c9500cefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169622132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1169622132
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.297945938
Short name T395
Test name
Test status
Simulation time 170405217 ps
CPU time 1.16 seconds
Started Aug 03 04:38:54 PM PDT 24
Finished Aug 03 04:38:55 PM PDT 24
Peak memory 200248 kb
Host smart-2e43ef36-ebad-46a1-a17c-e4d52158cfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297945938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.297945938
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2514293787
Short name T344
Test name
Test status
Simulation time 86313702 ps
CPU time 0.79 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:16 PM PDT 24
Peak memory 199976 kb
Host smart-9ec0f7e1-d5fa-427b-9500-aa9ab872bc9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514293787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2514293787
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1557687356
Short name T457
Test name
Test status
Simulation time 1221171781 ps
CPU time 5.34 seconds
Started Aug 03 04:39:13 PM PDT 24
Finished Aug 03 04:39:19 PM PDT 24
Peak memory 221636 kb
Host smart-f4e9a864-414f-4efd-b26e-f595a045cca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557687356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1557687356
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1515226916
Short name T474
Test name
Test status
Simulation time 244697713 ps
CPU time 1.05 seconds
Started Aug 03 04:39:12 PM PDT 24
Finished Aug 03 04:39:14 PM PDT 24
Peak memory 217340 kb
Host smart-7a5d5c26-60f6-499f-a032-91fb267ed3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515226916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1515226916
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2153493660
Short name T243
Test name
Test status
Simulation time 129152361 ps
CPU time 0.84 seconds
Started Aug 03 04:39:04 PM PDT 24
Finished Aug 03 04:39:05 PM PDT 24
Peak memory 200060 kb
Host smart-5753a967-df28-436d-ac92-fde8db1547a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153493660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2153493660
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1192030844
Short name T100
Test name
Test status
Simulation time 1167622516 ps
CPU time 5.23 seconds
Started Aug 03 04:38:55 PM PDT 24
Finished Aug 03 04:39:01 PM PDT 24
Peak memory 200336 kb
Host smart-bb62162f-6945-4a17-af0a-06853abdd306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192030844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1192030844
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2856950933
Short name T148
Test name
Test status
Simulation time 110039480 ps
CPU time 1.04 seconds
Started Aug 03 04:38:56 PM PDT 24
Finished Aug 03 04:38:57 PM PDT 24
Peak memory 200288 kb
Host smart-09393653-f669-4d47-befc-6f6389d909a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856950933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2856950933
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1658045787
Short name T517
Test name
Test status
Simulation time 116915315 ps
CPU time 1.22 seconds
Started Aug 03 04:39:10 PM PDT 24
Finished Aug 03 04:39:11 PM PDT 24
Peak memory 200272 kb
Host smart-6b5f816f-293b-4dc9-9d02-696113105e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658045787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1658045787
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1440817040
Short name T494
Test name
Test status
Simulation time 5049148949 ps
CPU time 20.33 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 210776 kb
Host smart-c2339e1f-309c-4b58-936f-3799f5cf63c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440817040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1440817040
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3609375189
Short name T201
Test name
Test status
Simulation time 471742495 ps
CPU time 2.59 seconds
Started Aug 03 04:38:55 PM PDT 24
Finished Aug 03 04:38:58 PM PDT 24
Peak memory 200220 kb
Host smart-b45f1234-9bec-41e6-bff4-ef1de63dbbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609375189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3609375189
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1892302455
Short name T276
Test name
Test status
Simulation time 186564171 ps
CPU time 1.22 seconds
Started Aug 03 04:38:58 PM PDT 24
Finished Aug 03 04:38:59 PM PDT 24
Peak memory 200168 kb
Host smart-e85c7694-39b4-46dd-a20c-fc17efb062b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892302455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1892302455
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.990356986
Short name T438
Test name
Test status
Simulation time 71864356 ps
CPU time 0.77 seconds
Started Aug 03 04:39:13 PM PDT 24
Finished Aug 03 04:39:14 PM PDT 24
Peak memory 199996 kb
Host smart-ed17d01a-554a-4eab-a7b1-0991d5ab838b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990356986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.990356986
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3986811683
Short name T10
Test name
Test status
Simulation time 1894078806 ps
CPU time 7.66 seconds
Started Aug 03 04:39:14 PM PDT 24
Finished Aug 03 04:39:22 PM PDT 24
Peak memory 217456 kb
Host smart-fa221d4f-0a76-46b2-8879-c2faa57d9062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986811683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3986811683
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.660222603
Short name T129
Test name
Test status
Simulation time 244691965 ps
CPU time 1.09 seconds
Started Aug 03 04:39:03 PM PDT 24
Finished Aug 03 04:39:04 PM PDT 24
Peak memory 217508 kb
Host smart-05616e8f-2f68-4806-a002-dba311573135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660222603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.660222603
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1760985092
Short name T16
Test name
Test status
Simulation time 195499434 ps
CPU time 0.96 seconds
Started Aug 03 04:39:00 PM PDT 24
Finished Aug 03 04:39:01 PM PDT 24
Peak memory 200060 kb
Host smart-ceb0bcf6-cded-48ee-9ef8-3a238a508c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760985092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1760985092
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3230278605
Short name T96
Test name
Test status
Simulation time 1046659776 ps
CPU time 4.8 seconds
Started Aug 03 04:39:25 PM PDT 24
Finished Aug 03 04:39:30 PM PDT 24
Peak memory 200488 kb
Host smart-b6ab76a5-54ee-40d9-a109-85e1cad3638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230278605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3230278605
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3830503274
Short name T342
Test name
Test status
Simulation time 105790402 ps
CPU time 1.06 seconds
Started Aug 03 04:39:22 PM PDT 24
Finished Aug 03 04:39:23 PM PDT 24
Peak memory 200240 kb
Host smart-53e42c3d-9b62-41bf-87d4-4fec8ac5faca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830503274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3830503274
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2376130400
Short name T502
Test name
Test status
Simulation time 204070984 ps
CPU time 1.36 seconds
Started Aug 03 04:39:13 PM PDT 24
Finished Aug 03 04:39:15 PM PDT 24
Peak memory 200336 kb
Host smart-49cd4d4d-e1a8-4872-8e09-28da4fb6f322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376130400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2376130400
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3981449218
Short name T476
Test name
Test status
Simulation time 7868558585 ps
CPU time 29.88 seconds
Started Aug 03 04:39:24 PM PDT 24
Finished Aug 03 04:39:54 PM PDT 24
Peak memory 200452 kb
Host smart-92e2c75c-e14e-442c-88e3-8d83538a7c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981449218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3981449218
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1435041084
Short name T495
Test name
Test status
Simulation time 271994547 ps
CPU time 1.94 seconds
Started Aug 03 04:39:00 PM PDT 24
Finished Aug 03 04:39:03 PM PDT 24
Peak memory 200232 kb
Host smart-8e633095-51e9-442e-b784-3febc1d4702a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435041084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1435041084
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3997765736
Short name T396
Test name
Test status
Simulation time 92449234 ps
CPU time 0.85 seconds
Started Aug 03 04:39:13 PM PDT 24
Finished Aug 03 04:39:14 PM PDT 24
Peak memory 199988 kb
Host smart-0ca485a2-7385-40a7-8fd3-dd5a09882186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997765736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3997765736
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3505992111
Short name T269
Test name
Test status
Simulation time 65953661 ps
CPU time 0.83 seconds
Started Aug 03 04:39:06 PM PDT 24
Finished Aug 03 04:39:07 PM PDT 24
Peak memory 200088 kb
Host smart-d665e495-4399-4ff9-981c-f6327c3411a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505992111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3505992111
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.4161290084
Short name T42
Test name
Test status
Simulation time 2351681035 ps
CPU time 8.51 seconds
Started Aug 03 04:39:13 PM PDT 24
Finished Aug 03 04:39:22 PM PDT 24
Peak memory 217812 kb
Host smart-a56a5c41-0af0-4d34-9555-4d0a5c504fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161290084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.4161290084
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.516684234
Short name T197
Test name
Test status
Simulation time 244818361 ps
CPU time 1.09 seconds
Started Aug 03 04:39:03 PM PDT 24
Finished Aug 03 04:39:04 PM PDT 24
Peak memory 217524 kb
Host smart-14738f06-7d2a-4e29-9dae-9c4960ffc8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516684234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.516684234
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.558651325
Short name T306
Test name
Test status
Simulation time 78079753 ps
CPU time 0.78 seconds
Started Aug 03 04:39:03 PM PDT 24
Finished Aug 03 04:39:04 PM PDT 24
Peak memory 200016 kb
Host smart-b47b0d88-329f-4bb4-bc57-b77aea768b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558651325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.558651325
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.20616713
Short name T326
Test name
Test status
Simulation time 1471452944 ps
CPU time 5.58 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:21 PM PDT 24
Peak memory 200536 kb
Host smart-7b8c1c1e-b8fb-4518-b032-7c20e4e74e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20616713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.20616713
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.863315245
Short name T287
Test name
Test status
Simulation time 151333569 ps
CPU time 1.2 seconds
Started Aug 03 04:39:25 PM PDT 24
Finished Aug 03 04:39:26 PM PDT 24
Peak memory 200484 kb
Host smart-8c7994d9-85af-4713-8745-b1adf4004c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863315245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.863315245
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2583273787
Short name T247
Test name
Test status
Simulation time 113529528 ps
CPU time 1.12 seconds
Started Aug 03 04:39:01 PM PDT 24
Finished Aug 03 04:39:02 PM PDT 24
Peak memory 200332 kb
Host smart-04efb733-51c8-4bef-bca2-1bc6d8e8f687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583273787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2583273787
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1233587603
Short name T305
Test name
Test status
Simulation time 5020901470 ps
CPU time 17.26 seconds
Started Aug 03 04:39:14 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 208736 kb
Host smart-fb2cde80-237e-4ffb-b500-5c7b7352ee73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233587603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1233587603
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1413579097
Short name T501
Test name
Test status
Simulation time 339994053 ps
CPU time 2.07 seconds
Started Aug 03 04:39:06 PM PDT 24
Finished Aug 03 04:39:08 PM PDT 24
Peak memory 208356 kb
Host smart-caa1ab50-4704-4d68-bbe5-a885365dc498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413579097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1413579097
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2583959126
Short name T242
Test name
Test status
Simulation time 128993504 ps
CPU time 1.13 seconds
Started Aug 03 04:39:02 PM PDT 24
Finished Aug 03 04:39:03 PM PDT 24
Peak memory 200284 kb
Host smart-0e74b6e1-5fd3-42fa-bc67-c30bb5c61075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583959126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2583959126
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3366836604
Short name T217
Test name
Test status
Simulation time 63493003 ps
CPU time 0.77 seconds
Started Aug 03 04:39:10 PM PDT 24
Finished Aug 03 04:39:10 PM PDT 24
Peak memory 199948 kb
Host smart-6509badb-8a45-4d49-a789-d80a4f489f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366836604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3366836604
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3735827458
Short name T390
Test name
Test status
Simulation time 2364846816 ps
CPU time 8.6 seconds
Started Aug 03 04:39:06 PM PDT 24
Finished Aug 03 04:39:15 PM PDT 24
Peak memory 217804 kb
Host smart-e2ddff42-a42a-4109-8ccf-a0a8fcdd40d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735827458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3735827458
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3063540970
Short name T203
Test name
Test status
Simulation time 243366416 ps
CPU time 1.06 seconds
Started Aug 03 04:39:14 PM PDT 24
Finished Aug 03 04:39:15 PM PDT 24
Peak memory 217460 kb
Host smart-2ae2f7ff-faed-4f9a-a7cb-e2cdff0b3d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063540970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3063540970
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4080210595
Short name T237
Test name
Test status
Simulation time 156911603 ps
CPU time 0.88 seconds
Started Aug 03 04:39:12 PM PDT 24
Finished Aug 03 04:39:13 PM PDT 24
Peak memory 199960 kb
Host smart-201f05c1-80c4-493c-95e9-1f0314966e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080210595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4080210595
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.126608482
Short name T350
Test name
Test status
Simulation time 969995864 ps
CPU time 4.91 seconds
Started Aug 03 04:39:17 PM PDT 24
Finished Aug 03 04:39:22 PM PDT 24
Peak memory 200476 kb
Host smart-5a7d7bb3-c8d8-442d-b88d-73337b31ce0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126608482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.126608482
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2364896702
Short name T230
Test name
Test status
Simulation time 111036311 ps
CPU time 1.05 seconds
Started Aug 03 04:39:09 PM PDT 24
Finished Aug 03 04:39:10 PM PDT 24
Peak memory 200248 kb
Host smart-96fec60d-5cda-4f41-b4c1-81158861bd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364896702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2364896702
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3799712090
Short name T182
Test name
Test status
Simulation time 242493126 ps
CPU time 1.47 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:17 PM PDT 24
Peak memory 200352 kb
Host smart-295755eb-00f9-4d85-ba5b-b4ab61b53cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799712090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3799712090
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.66825573
Short name T358
Test name
Test status
Simulation time 4625617082 ps
CPU time 17.28 seconds
Started Aug 03 04:39:04 PM PDT 24
Finished Aug 03 04:39:21 PM PDT 24
Peak memory 208604 kb
Host smart-0e409e26-b393-464b-a4b3-62e505f1e836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66825573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.66825573
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.463785380
Short name T185
Test name
Test status
Simulation time 468919105 ps
CPU time 2.62 seconds
Started Aug 03 04:39:13 PM PDT 24
Finished Aug 03 04:39:16 PM PDT 24
Peak memory 199984 kb
Host smart-e23dd2d1-464c-4bf5-9490-83f9914d8b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463785380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.463785380
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.4205128671
Short name T417
Test name
Test status
Simulation time 200321491 ps
CPU time 1.3 seconds
Started Aug 03 04:39:18 PM PDT 24
Finished Aug 03 04:39:19 PM PDT 24
Peak memory 200276 kb
Host smart-cb874bca-bab0-4d2e-b4fd-bc5f760cc693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205128671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.4205128671
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.107862657
Short name T381
Test name
Test status
Simulation time 78277042 ps
CPU time 0.86 seconds
Started Aug 03 04:39:10 PM PDT 24
Finished Aug 03 04:39:11 PM PDT 24
Peak memory 200100 kb
Host smart-80067605-2923-4f8d-970f-4a6bd7903932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107862657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.107862657
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.229106554
Short name T450
Test name
Test status
Simulation time 1223075581 ps
CPU time 6.19 seconds
Started Aug 03 04:39:11 PM PDT 24
Finished Aug 03 04:39:17 PM PDT 24
Peak memory 217688 kb
Host smart-0232c07a-0c28-4f3b-a06b-d2c068572e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229106554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.229106554
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2164137638
Short name T472
Test name
Test status
Simulation time 263121704 ps
CPU time 1.08 seconds
Started Aug 03 04:39:09 PM PDT 24
Finished Aug 03 04:39:10 PM PDT 24
Peak memory 217532 kb
Host smart-2892c196-4cdc-4580-b31c-6f9bcc614eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164137638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2164137638
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3319717914
Short name T195
Test name
Test status
Simulation time 88659255 ps
CPU time 0.71 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:30 PM PDT 24
Peak memory 199992 kb
Host smart-f5c95822-e719-4a98-80ea-77055a43fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319717914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3319717914
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.201508158
Short name T318
Test name
Test status
Simulation time 935949874 ps
CPU time 4.91 seconds
Started Aug 03 04:39:13 PM PDT 24
Finished Aug 03 04:39:18 PM PDT 24
Peak memory 200492 kb
Host smart-ab6792a0-dc96-47d9-8066-5008bba3a231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201508158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.201508158
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.642988078
Short name T522
Test name
Test status
Simulation time 168664307 ps
CPU time 1.13 seconds
Started Aug 03 04:39:11 PM PDT 24
Finished Aug 03 04:39:12 PM PDT 24
Peak memory 200264 kb
Host smart-9b565192-9126-4989-9f9b-247b2e98b693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642988078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.642988078
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.657893979
Short name T335
Test name
Test status
Simulation time 1948252883 ps
CPU time 7.58 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200512 kb
Host smart-a3fbfb53-b7d6-4b71-806a-e6a07abadc57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657893979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.657893979
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3617425129
Short name T398
Test name
Test status
Simulation time 146076666 ps
CPU time 1.9 seconds
Started Aug 03 04:39:11 PM PDT 24
Finished Aug 03 04:39:13 PM PDT 24
Peak memory 200236 kb
Host smart-660b5bf4-4456-446f-90a3-46e32a54c26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617425129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3617425129
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2606221407
Short name T145
Test name
Test status
Simulation time 194030237 ps
CPU time 1.21 seconds
Started Aug 03 04:39:10 PM PDT 24
Finished Aug 03 04:39:11 PM PDT 24
Peak memory 200216 kb
Host smart-22b6e762-701f-4cba-b1cb-a056815f84fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606221407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2606221407
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3460037293
Short name T491
Test name
Test status
Simulation time 1895629836 ps
CPU time 8.13 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 217548 kb
Host smart-cb9ce1b6-c47c-42ad-8cd1-851813fafad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460037293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3460037293
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.441433725
Short name T270
Test name
Test status
Simulation time 244328641 ps
CPU time 1.07 seconds
Started Aug 03 04:39:08 PM PDT 24
Finished Aug 03 04:39:09 PM PDT 24
Peak memory 217428 kb
Host smart-6795351f-adab-47af-9bd7-ba7921ec94e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441433725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.441433725
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2710634659
Short name T23
Test name
Test status
Simulation time 77164339 ps
CPU time 0.74 seconds
Started Aug 03 04:39:27 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 199968 kb
Host smart-680dcb9e-791e-4e12-9c73-0476fb2f1409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710634659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2710634659
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2487808309
Short name T403
Test name
Test status
Simulation time 1505920141 ps
CPU time 5.51 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:35 PM PDT 24
Peak memory 200500 kb
Host smart-4a9f4c11-ca5c-4b08-a6a8-58faed4402ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487808309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2487808309
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2373166292
Short name T416
Test name
Test status
Simulation time 113190953 ps
CPU time 0.99 seconds
Started Aug 03 04:39:11 PM PDT 24
Finished Aug 03 04:39:12 PM PDT 24
Peak memory 200264 kb
Host smart-8efaf343-5261-45f2-b647-5e0413c5ea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373166292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2373166292
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2772538390
Short name T79
Test name
Test status
Simulation time 113855078 ps
CPU time 1.18 seconds
Started Aug 03 04:39:09 PM PDT 24
Finished Aug 03 04:39:11 PM PDT 24
Peak memory 200432 kb
Host smart-1e92a3b2-94e2-4f8c-841d-6937a9f99c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772538390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2772538390
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1045504114
Short name T303
Test name
Test status
Simulation time 3245673101 ps
CPU time 12.34 seconds
Started Aug 03 04:39:25 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 208684 kb
Host smart-ce07c28d-c7bf-4d0f-b9e4-a7cc9e2ec133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045504114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1045504114
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2634830511
Short name T298
Test name
Test status
Simulation time 414534794 ps
CPU time 2.58 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:35 PM PDT 24
Peak memory 208400 kb
Host smart-457b5448-dd7e-4658-881c-c76c38db91be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634830511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2634830511
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2211565871
Short name T373
Test name
Test status
Simulation time 227416782 ps
CPU time 1.34 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 200260 kb
Host smart-207cd796-9cdd-4994-a406-3694536b757e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211565871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2211565871
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3720448156
Short name T64
Test name
Test status
Simulation time 65275391 ps
CPU time 0.78 seconds
Started Aug 03 04:39:18 PM PDT 24
Finished Aug 03 04:39:19 PM PDT 24
Peak memory 199980 kb
Host smart-9153206f-0390-4eef-b694-1b79ab94fd26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720448156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3720448156
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3692951515
Short name T245
Test name
Test status
Simulation time 1873968259 ps
CPU time 7.86 seconds
Started Aug 03 04:39:11 PM PDT 24
Finished Aug 03 04:39:19 PM PDT 24
Peak memory 217668 kb
Host smart-a8b25c7e-49ad-4580-b872-d306148868ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692951515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3692951515
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.4136272276
Short name T519
Test name
Test status
Simulation time 243784698 ps
CPU time 1.19 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 217332 kb
Host smart-4797ab6e-f08d-4a65-b2d3-01048d66506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136272276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.4136272276
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.921797508
Short name T507
Test name
Test status
Simulation time 96825231 ps
CPU time 0.75 seconds
Started Aug 03 04:39:10 PM PDT 24
Finished Aug 03 04:39:11 PM PDT 24
Peak memory 200068 kb
Host smart-40e7f75e-265e-46f6-932d-bc5e6d46c41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921797508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.921797508
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2851536151
Short name T92
Test name
Test status
Simulation time 1132865608 ps
CPU time 5.82 seconds
Started Aug 03 04:39:09 PM PDT 24
Finished Aug 03 04:39:15 PM PDT 24
Peak memory 200336 kb
Host smart-f42334c8-9b4a-47d0-8989-1317a0ca5a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851536151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2851536151
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1837920102
Short name T405
Test name
Test status
Simulation time 111400377 ps
CPU time 0.98 seconds
Started Aug 03 04:39:23 PM PDT 24
Finished Aug 03 04:39:24 PM PDT 24
Peak memory 200164 kb
Host smart-b3b86079-fada-4ed7-8b60-72319b4527dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837920102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1837920102
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2840103206
Short name T156
Test name
Test status
Simulation time 122066103 ps
CPU time 1.24 seconds
Started Aug 03 04:39:10 PM PDT 24
Finished Aug 03 04:39:11 PM PDT 24
Peak memory 200292 kb
Host smart-c1ef94b4-97a4-443f-ace1-3875a7bf0078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840103206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2840103206
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.442475745
Short name T191
Test name
Test status
Simulation time 629586479 ps
CPU time 3.07 seconds
Started Aug 03 04:39:13 PM PDT 24
Finished Aug 03 04:39:16 PM PDT 24
Peak memory 200420 kb
Host smart-a0badd4b-b90e-46af-a8f8-5671dfc2f064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442475745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.442475745
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2275921789
Short name T178
Test name
Test status
Simulation time 271192391 ps
CPU time 1.85 seconds
Started Aug 03 04:39:18 PM PDT 24
Finished Aug 03 04:39:20 PM PDT 24
Peak memory 200144 kb
Host smart-7a927307-64f4-4e77-9b37-c1eca22c832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275921789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2275921789
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.328299372
Short name T307
Test name
Test status
Simulation time 163365700 ps
CPU time 1.35 seconds
Started Aug 03 04:39:11 PM PDT 24
Finished Aug 03 04:39:13 PM PDT 24
Peak memory 200428 kb
Host smart-8a2886bb-9006-4ad7-be64-c03c395bc530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328299372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.328299372
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1663000054
Short name T128
Test name
Test status
Simulation time 81907881 ps
CPU time 0.83 seconds
Started Aug 03 04:39:17 PM PDT 24
Finished Aug 03 04:39:17 PM PDT 24
Peak memory 200080 kb
Host smart-efb80296-b8c9-4944-9011-6cf698b28ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663000054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1663000054
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2732410841
Short name T464
Test name
Test status
Simulation time 1230491432 ps
CPU time 5.76 seconds
Started Aug 03 04:39:25 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 217588 kb
Host smart-7666e30b-0271-4c2e-8741-6bd5c53cd195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732410841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2732410841
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.235020313
Short name T443
Test name
Test status
Simulation time 244580710 ps
CPU time 1.09 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 217356 kb
Host smart-ebf396ef-3095-4abd-90e4-bd5fd0611efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235020313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.235020313
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2640203307
Short name T285
Test name
Test status
Simulation time 108323505 ps
CPU time 0.78 seconds
Started Aug 03 04:39:21 PM PDT 24
Finished Aug 03 04:39:22 PM PDT 24
Peak memory 200084 kb
Host smart-50792b82-b934-460d-89ee-c84051442552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640203307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2640203307
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3909240241
Short name T471
Test name
Test status
Simulation time 1704418375 ps
CPU time 6.7 seconds
Started Aug 03 04:39:17 PM PDT 24
Finished Aug 03 04:39:24 PM PDT 24
Peak memory 200500 kb
Host smart-0e7ba3fd-660d-48ff-b5df-830a38759254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909240241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3909240241
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2130113406
Short name T147
Test name
Test status
Simulation time 154414249 ps
CPU time 1.13 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 200272 kb
Host smart-063e140c-9f46-494a-9edd-3aeeb165da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130113406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2130113406
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.557633072
Short name T235
Test name
Test status
Simulation time 253114660 ps
CPU time 1.51 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 200488 kb
Host smart-3ce4e333-b085-4780-8b8e-bd2717e9f1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557633072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.557633072
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1928128416
Short name T308
Test name
Test status
Simulation time 4613277061 ps
CPU time 21.88 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200556 kb
Host smart-dbd64ada-a55f-4d5a-883b-1c5482b51daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928128416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1928128416
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1126700576
Short name T470
Test name
Test status
Simulation time 379291203 ps
CPU time 2.49 seconds
Started Aug 03 04:39:31 PM PDT 24
Finished Aug 03 04:39:34 PM PDT 24
Peak memory 200120 kb
Host smart-0759e77b-2519-4366-9cd0-dc4664a865d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126700576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1126700576
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.330518562
Short name T216
Test name
Test status
Simulation time 182368781 ps
CPU time 1.24 seconds
Started Aug 03 04:39:28 PM PDT 24
Finished Aug 03 04:39:30 PM PDT 24
Peak memory 200240 kb
Host smart-2ad32d9f-d944-4d38-bf84-0214df03b187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330518562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.330518562
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.4005387267
Short name T149
Test name
Test status
Simulation time 60704067 ps
CPU time 0.74 seconds
Started Aug 03 04:39:28 PM PDT 24
Finished Aug 03 04:39:29 PM PDT 24
Peak memory 200024 kb
Host smart-9725ce81-bf30-4485-ad8b-6cda64e8f81f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005387267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4005387267
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3815551710
Short name T36
Test name
Test status
Simulation time 1232048886 ps
CPU time 5.38 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 217076 kb
Host smart-9263aa9c-c20e-48c9-9d73-ad2f0dff370e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815551710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3815551710
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2155927680
Short name T262
Test name
Test status
Simulation time 245110984 ps
CPU time 1.02 seconds
Started Aug 03 04:39:21 PM PDT 24
Finished Aug 03 04:39:22 PM PDT 24
Peak memory 217496 kb
Host smart-f5ec57e1-bc46-4fe3-bf9e-7bbcac446ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155927680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2155927680
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1591764277
Short name T15
Test name
Test status
Simulation time 146073379 ps
CPU time 0.91 seconds
Started Aug 03 04:39:18 PM PDT 24
Finished Aug 03 04:39:19 PM PDT 24
Peak memory 199928 kb
Host smart-eae67afa-3da3-467c-ba04-4851331925b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591764277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1591764277
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1505680002
Short name T117
Test name
Test status
Simulation time 1617252076 ps
CPU time 6.02 seconds
Started Aug 03 04:39:17 PM PDT 24
Finished Aug 03 04:39:23 PM PDT 24
Peak memory 200500 kb
Host smart-6dbda932-c175-4575-bde9-0c847bc96627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505680002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1505680002
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.82605048
Short name T315
Test name
Test status
Simulation time 98408680 ps
CPU time 1.01 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:17 PM PDT 24
Peak memory 200104 kb
Host smart-457d32d6-101d-496a-af61-7d7ba69fd6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82605048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.82605048
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3282791846
Short name T14
Test name
Test status
Simulation time 196908087 ps
CPU time 1.34 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200476 kb
Host smart-1d5c78d5-e8d2-4e43-afb9-2c29b7defa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282791846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3282791846
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3085009409
Short name T75
Test name
Test status
Simulation time 2425793125 ps
CPU time 9.16 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:43 PM PDT 24
Peak memory 208756 kb
Host smart-77bfc01f-69fe-4d2a-9f7e-670942a4612c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085009409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3085009409
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2701933469
Short name T200
Test name
Test status
Simulation time 66574081 ps
CPU time 0.84 seconds
Started Aug 03 04:39:18 PM PDT 24
Finished Aug 03 04:39:19 PM PDT 24
Peak memory 200272 kb
Host smart-33198b3b-7783-46b0-b1cf-eca5cd139f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701933469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2701933469
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2996710912
Short name T525
Test name
Test status
Simulation time 77785872 ps
CPU time 0.86 seconds
Started Aug 03 04:38:41 PM PDT 24
Finished Aug 03 04:38:42 PM PDT 24
Peak memory 200116 kb
Host smart-089e45cc-7664-40a1-a004-f2491b679a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996710912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2996710912
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2393027579
Short name T286
Test name
Test status
Simulation time 246565527 ps
CPU time 1.01 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:44 PM PDT 24
Peak memory 217448 kb
Host smart-5791ae6c-f1fe-41bf-a9a0-586b97837cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393027579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2393027579
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4015778100
Short name T361
Test name
Test status
Simulation time 122323911 ps
CPU time 0.75 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:43 PM PDT 24
Peak memory 200084 kb
Host smart-9bc122e5-cbab-436e-b9ec-0cbc96d11378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015778100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4015778100
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.4146001149
Short name T206
Test name
Test status
Simulation time 1422510419 ps
CPU time 6.05 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:54 PM PDT 24
Peak memory 200380 kb
Host smart-4d87406b-c5b5-4906-92f4-195adaeab440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146001149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.4146001149
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.114803663
Short name T137
Test name
Test status
Simulation time 178944676 ps
CPU time 1.22 seconds
Started Aug 03 04:38:47 PM PDT 24
Finished Aug 03 04:38:49 PM PDT 24
Peak memory 200252 kb
Host smart-41837c95-bec8-4f59-951f-44478bcb6991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114803663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.114803663
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.4175830320
Short name T120
Test name
Test status
Simulation time 249365964 ps
CPU time 1.51 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:44 PM PDT 24
Peak memory 200384 kb
Host smart-884de3c7-6d28-45cd-bf2f-d7068acb03e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175830320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4175830320
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2841114733
Short name T186
Test name
Test status
Simulation time 4564154255 ps
CPU time 15.93 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:39:04 PM PDT 24
Peak memory 200520 kb
Host smart-a3d35427-9805-4faf-a03f-3888fe108aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841114733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2841114733
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2064898946
Short name T51
Test name
Test status
Simulation time 438043490 ps
CPU time 2.16 seconds
Started Aug 03 04:38:40 PM PDT 24
Finished Aug 03 04:38:42 PM PDT 24
Peak memory 208436 kb
Host smart-559e0cda-16e2-46db-a590-e55453581c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064898946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2064898946
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3274662683
Short name T484
Test name
Test status
Simulation time 170910249 ps
CPU time 1.09 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:45 PM PDT 24
Peak memory 200188 kb
Host smart-ceb5e1cf-a897-4c25-98d4-82268c2ee756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274662683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3274662683
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3672779032
Short name T264
Test name
Test status
Simulation time 59487809 ps
CPU time 0.74 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:35 PM PDT 24
Peak memory 200056 kb
Host smart-77333e75-d33f-4183-a518-c6b7c0582e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672779032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3672779032
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.865911589
Short name T43
Test name
Test status
Simulation time 2195667926 ps
CPU time 8.08 seconds
Started Aug 03 04:39:30 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 217648 kb
Host smart-4103c9c7-6ee0-4691-b341-a475f84b26fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865911589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.865911589
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2994995077
Short name T221
Test name
Test status
Simulation time 244708968 ps
CPU time 1.05 seconds
Started Aug 03 04:39:14 PM PDT 24
Finished Aug 03 04:39:15 PM PDT 24
Peak memory 217464 kb
Host smart-c6c0a46f-6d10-4fa6-ad90-a04fe4ae9c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994995077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2994995077
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.67531864
Short name T346
Test name
Test status
Simulation time 204619571 ps
CPU time 0.96 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:30 PM PDT 24
Peak memory 199968 kb
Host smart-0821e4bb-2204-4b48-97e8-5c636691eef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67531864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.67531864
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3810254722
Short name T165
Test name
Test status
Simulation time 930881313 ps
CPU time 4.72 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200504 kb
Host smart-94cc055f-fe1e-4f91-a73d-1be855131a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810254722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3810254722
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1424211530
Short name T146
Test name
Test status
Simulation time 178125552 ps
CPU time 1.21 seconds
Started Aug 03 04:39:18 PM PDT 24
Finished Aug 03 04:39:20 PM PDT 24
Peak memory 200128 kb
Host smart-cb55e284-b5ed-4a40-b216-8d77a0b55f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424211530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1424211530
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1888061616
Short name T374
Test name
Test status
Simulation time 196696303 ps
CPU time 1.35 seconds
Started Aug 03 04:39:19 PM PDT 24
Finished Aug 03 04:39:20 PM PDT 24
Peak memory 200396 kb
Host smart-0b9823bc-3827-40db-87e0-8b6925a2b4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888061616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1888061616
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2021831453
Short name T533
Test name
Test status
Simulation time 9628060621 ps
CPU time 31.74 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:40:09 PM PDT 24
Peak memory 200524 kb
Host smart-e0a7f058-c2f8-4afe-9d4d-ca167456ee33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021831453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2021831453
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3863420211
Short name T246
Test name
Test status
Simulation time 514455712 ps
CPU time 2.8 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:18 PM PDT 24
Peak memory 200204 kb
Host smart-658e81db-8573-4f93-a07c-7dfb95c177da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863420211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3863420211
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1241333883
Short name T167
Test name
Test status
Simulation time 127946788 ps
CPU time 1.15 seconds
Started Aug 03 04:39:19 PM PDT 24
Finished Aug 03 04:39:20 PM PDT 24
Peak memory 200148 kb
Host smart-9c75494e-b932-4b46-89a2-08c2806950f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241333883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1241333883
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1100598760
Short name T280
Test name
Test status
Simulation time 63989025 ps
CPU time 0.72 seconds
Started Aug 03 04:39:26 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 200024 kb
Host smart-cde104e5-6a63-4b00-8372-2f1a091df9e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100598760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1100598760
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1112681643
Short name T363
Test name
Test status
Simulation time 2330094111 ps
CPU time 7.99 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:47 PM PDT 24
Peak memory 221708 kb
Host smart-4f7e451d-0e53-45fe-8942-161a11c706a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112681643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1112681643
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3023203453
Short name T351
Test name
Test status
Simulation time 243996595 ps
CPU time 1.13 seconds
Started Aug 03 04:39:18 PM PDT 24
Finished Aug 03 04:39:19 PM PDT 24
Peak memory 217508 kb
Host smart-69f81e16-5bcf-4921-97b3-3908f5b985bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023203453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3023203453
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2362175585
Short name T20
Test name
Test status
Simulation time 168824096 ps
CPU time 0.87 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:16 PM PDT 24
Peak memory 199976 kb
Host smart-38d66acd-8efe-4738-bfac-a83375bb153e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362175585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2362175585
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.4080381015
Short name T431
Test name
Test status
Simulation time 1114617762 ps
CPU time 5.36 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 200732 kb
Host smart-20467d83-72d1-4770-974d-2ef609e0ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080381015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.4080381015
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3314788211
Short name T475
Test name
Test status
Simulation time 170612390 ps
CPU time 1.23 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200264 kb
Host smart-962aee49-86b3-403b-8e5e-5741fa390835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314788211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3314788211
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1619236843
Short name T399
Test name
Test status
Simulation time 235038197 ps
CPU time 1.44 seconds
Started Aug 03 04:39:21 PM PDT 24
Finished Aug 03 04:39:22 PM PDT 24
Peak memory 200404 kb
Host smart-a167b138-d400-47a9-a175-346c55473dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619236843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1619236843
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3304855202
Short name T466
Test name
Test status
Simulation time 3474134828 ps
CPU time 14.76 seconds
Started Aug 03 04:39:14 PM PDT 24
Finished Aug 03 04:39:29 PM PDT 24
Peak memory 200512 kb
Host smart-c71f6248-241c-44f5-bba3-b8d2a2998bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304855202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3304855202
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.500316630
Short name T296
Test name
Test status
Simulation time 127698899 ps
CPU time 1.53 seconds
Started Aug 03 04:39:17 PM PDT 24
Finished Aug 03 04:39:19 PM PDT 24
Peak memory 200216 kb
Host smart-48a60aed-c145-4367-8022-4330e07da430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500316630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.500316630
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2400253307
Short name T122
Test name
Test status
Simulation time 75822334 ps
CPU time 0.82 seconds
Started Aug 03 04:39:22 PM PDT 24
Finished Aug 03 04:39:23 PM PDT 24
Peak memory 200144 kb
Host smart-b721c52e-6381-4083-9f6b-6f3c29558b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400253307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2400253307
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2902726299
Short name T429
Test name
Test status
Simulation time 62407616 ps
CPU time 0.73 seconds
Started Aug 03 04:39:17 PM PDT 24
Finished Aug 03 04:39:17 PM PDT 24
Peak memory 200104 kb
Host smart-f6712dc7-4ab5-4ec6-b322-01810b697c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902726299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2902726299
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3193374947
Short name T534
Test name
Test status
Simulation time 1222334599 ps
CPU time 5.76 seconds
Started Aug 03 04:39:30 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 217604 kb
Host smart-650e15c4-21a2-4606-bb57-c469db02670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193374947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3193374947
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.4145013843
Short name T482
Test name
Test status
Simulation time 243959392 ps
CPU time 1.05 seconds
Started Aug 03 04:39:27 PM PDT 24
Finished Aug 03 04:39:28 PM PDT 24
Peak memory 217388 kb
Host smart-864809f0-d3f0-4634-b15a-0a6d224e686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145013843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.4145013843
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3492701940
Short name T169
Test name
Test status
Simulation time 101203209 ps
CPU time 0.78 seconds
Started Aug 03 04:39:27 PM PDT 24
Finished Aug 03 04:39:28 PM PDT 24
Peak memory 200052 kb
Host smart-8e3bdca4-896b-40f6-ae78-c1be33bfaa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492701940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3492701940
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2065472521
Short name T383
Test name
Test status
Simulation time 1549292589 ps
CPU time 6.91 seconds
Started Aug 03 04:39:20 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 200464 kb
Host smart-cfa5d0b7-d32c-4613-931b-4720b6b56c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065472521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2065472521
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.101484539
Short name T496
Test name
Test status
Simulation time 129994256 ps
CPU time 1.2 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:35 PM PDT 24
Peak memory 200392 kb
Host smart-a8caaf51-224b-4563-9527-d293933cc39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101484539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.101484539
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.686642463
Short name T511
Test name
Test status
Simulation time 1458713466 ps
CPU time 5.6 seconds
Started Aug 03 04:39:21 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 200400 kb
Host smart-7cb34569-d7cf-4e56-9e47-303923e2f4db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686642463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.686642463
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2669101120
Short name T406
Test name
Test status
Simulation time 366833116 ps
CPU time 2.34 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 200144 kb
Host smart-934b6acb-1ddc-4192-b5bd-faf1c9c2bf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669101120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2669101120
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1643940214
Short name T259
Test name
Test status
Simulation time 245694194 ps
CPU time 1.43 seconds
Started Aug 03 04:39:25 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 200468 kb
Host smart-6e082db3-b563-4ef8-b6fc-cddceabc1f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643940214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1643940214
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3212297153
Short name T359
Test name
Test status
Simulation time 64541273 ps
CPU time 0.76 seconds
Started Aug 03 04:39:26 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 199976 kb
Host smart-4ecdae4e-e399-4151-867c-87bd4c9692eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212297153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3212297153
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.863651549
Short name T404
Test name
Test status
Simulation time 1226089780 ps
CPU time 6.01 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:21 PM PDT 24
Peak memory 217264 kb
Host smart-4947d122-c23b-4ba8-85a6-a183d8150f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863651549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.863651549
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2793251390
Short name T456
Test name
Test status
Simulation time 244490628 ps
CPU time 1.16 seconds
Started Aug 03 04:39:26 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 217448 kb
Host smart-1b632ff6-d021-47f6-91e8-67b475fb381b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793251390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2793251390
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.972668502
Short name T325
Test name
Test status
Simulation time 156490921 ps
CPU time 0.84 seconds
Started Aug 03 04:39:17 PM PDT 24
Finished Aug 03 04:39:18 PM PDT 24
Peak memory 199976 kb
Host smart-b95d779e-f840-4645-b669-9de067f10a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972668502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.972668502
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3831068531
Short name T98
Test name
Test status
Simulation time 2047213828 ps
CPU time 7.34 seconds
Started Aug 03 04:39:18 PM PDT 24
Finished Aug 03 04:39:25 PM PDT 24
Peak memory 200500 kb
Host smart-c9b36315-d938-4ffd-b931-f5b25b570477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831068531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3831068531
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2251791663
Short name T72
Test name
Test status
Simulation time 102786375 ps
CPU time 1.04 seconds
Started Aug 03 04:39:26 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 200296 kb
Host smart-2e779cdd-872b-4780-8e1c-b8b2233d685a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251791663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2251791663
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.4260131856
Short name T57
Test name
Test status
Simulation time 128037458 ps
CPU time 1.28 seconds
Started Aug 03 04:39:18 PM PDT 24
Finished Aug 03 04:39:19 PM PDT 24
Peak memory 200268 kb
Host smart-4d8e3a34-81be-4400-941f-2f3d4982808d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260131856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.4260131856
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2398816090
Short name T248
Test name
Test status
Simulation time 5621783311 ps
CPU time 24.72 seconds
Started Aug 03 04:39:23 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 208720 kb
Host smart-a82de2a8-655d-42c7-8640-4a90d2b5ee46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398816090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2398816090
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.584509386
Short name T295
Test name
Test status
Simulation time 516544267 ps
CPU time 2.67 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:17 PM PDT 24
Peak memory 200072 kb
Host smart-2faa0160-2789-4908-a650-041a34ebc040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584509386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.584509386
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2299885698
Short name T339
Test name
Test status
Simulation time 122024444 ps
CPU time 0.96 seconds
Started Aug 03 04:39:16 PM PDT 24
Finished Aug 03 04:39:17 PM PDT 24
Peak memory 200284 kb
Host smart-59bbd023-f22d-4770-98b4-7f051aee0190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299885698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2299885698
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3847873327
Short name T238
Test name
Test status
Simulation time 60162721 ps
CPU time 0.74 seconds
Started Aug 03 04:39:26 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 199964 kb
Host smart-85cac35d-8ae1-41b9-89ba-d196c13c3748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847873327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3847873327
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.776844929
Short name T469
Test name
Test status
Simulation time 2344757959 ps
CPU time 8.32 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 217752 kb
Host smart-7cd80a91-6751-407e-8acf-0a38fa2ca769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776844929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.776844929
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3729577365
Short name T413
Test name
Test status
Simulation time 244490544 ps
CPU time 1.04 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 217416 kb
Host smart-3e589cad-be1a-44cc-ad83-dc3dde0ff510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729577365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3729577365
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1572696765
Short name T213
Test name
Test status
Simulation time 146408288 ps
CPU time 0.89 seconds
Started Aug 03 04:39:24 PM PDT 24
Finished Aug 03 04:39:25 PM PDT 24
Peak memory 199980 kb
Host smart-a151f63b-afd2-4e50-b908-d2adb02870d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572696765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1572696765
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1852453306
Short name T12
Test name
Test status
Simulation time 1307047276 ps
CPU time 5.13 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 200416 kb
Host smart-0554029f-2e88-49f5-a458-efd624926089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852453306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1852453306
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.562267256
Short name T174
Test name
Test status
Simulation time 140987728 ps
CPU time 1.12 seconds
Started Aug 03 04:39:22 PM PDT 24
Finished Aug 03 04:39:23 PM PDT 24
Peak memory 200264 kb
Host smart-238d7355-8e32-4b33-a806-41c6ea8ff092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562267256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.562267256
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2939178866
Short name T144
Test name
Test status
Simulation time 110121704 ps
CPU time 1.27 seconds
Started Aug 03 04:39:24 PM PDT 24
Finished Aug 03 04:39:26 PM PDT 24
Peak memory 200428 kb
Host smart-137c275e-61cb-4fc0-b346-746ddb905ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939178866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2939178866
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1077742042
Short name T345
Test name
Test status
Simulation time 6144036411 ps
CPU time 25.77 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:40:04 PM PDT 24
Peak memory 200524 kb
Host smart-5ad51720-1265-4f8d-95d8-69261490898b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077742042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1077742042
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3943165409
Short name T320
Test name
Test status
Simulation time 440784070 ps
CPU time 2.5 seconds
Started Aug 03 04:39:23 PM PDT 24
Finished Aug 03 04:39:26 PM PDT 24
Peak memory 200160 kb
Host smart-04c3d1c7-e00d-4f9d-ad37-e1c0f9ef942b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943165409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3943165409
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1747128468
Short name T180
Test name
Test status
Simulation time 176032743 ps
CPU time 1.17 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200248 kb
Host smart-470a6747-993d-4bdc-ba15-a498be76b50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747128468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1747128468
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3312707207
Short name T293
Test name
Test status
Simulation time 53496881 ps
CPU time 0.71 seconds
Started Aug 03 04:39:35 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 200044 kb
Host smart-1d40fdc7-4bd8-4cff-9ca2-2362249f7ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312707207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3312707207
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1142064743
Short name T229
Test name
Test status
Simulation time 1899078250 ps
CPU time 6.85 seconds
Started Aug 03 04:39:26 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 217652 kb
Host smart-0ad34af2-d350-4187-9aa3-62a439a09319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142064743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1142064743
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.473138690
Short name T311
Test name
Test status
Simulation time 243733920 ps
CPU time 1.13 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 217336 kb
Host smart-7784c10d-bd0b-476f-b969-84db91619753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473138690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.473138690
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1511780017
Short name T393
Test name
Test status
Simulation time 180030510 ps
CPU time 0.87 seconds
Started Aug 03 04:39:30 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 200072 kb
Host smart-73525a38-919e-4e2a-bcde-346927cd8b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511780017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1511780017
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2519635274
Short name T402
Test name
Test status
Simulation time 660949701 ps
CPU time 3.6 seconds
Started Aug 03 04:39:25 PM PDT 24
Finished Aug 03 04:39:29 PM PDT 24
Peak memory 200404 kb
Host smart-9c4633b6-0261-480b-a31f-3f1db9d581a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519635274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2519635274
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3791464797
Short name T453
Test name
Test status
Simulation time 97203509 ps
CPU time 0.95 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:34 PM PDT 24
Peak memory 200188 kb
Host smart-dbe7535a-26d2-46d1-bc7f-2dc198d5e759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791464797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3791464797
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3184170970
Short name T499
Test name
Test status
Simulation time 202910742 ps
CPU time 1.44 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 200416 kb
Host smart-03fec495-498a-4e0a-bc66-2e4bcb21815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184170970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3184170970
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1303046347
Short name T209
Test name
Test status
Simulation time 10577370673 ps
CPU time 34.77 seconds
Started Aug 03 04:39:41 PM PDT 24
Finished Aug 03 04:40:16 PM PDT 24
Peak memory 200544 kb
Host smart-0a5637b6-213b-4e39-a304-61cda69057a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303046347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1303046347
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1938968177
Short name T479
Test name
Test status
Simulation time 450779073 ps
CPU time 2.73 seconds
Started Aug 03 04:39:24 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 200128 kb
Host smart-e01a1f40-2753-4820-a196-067efda664ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938968177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1938968177
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.4144931557
Short name T78
Test name
Test status
Simulation time 130069824 ps
CPU time 1.11 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 200276 kb
Host smart-5d3335ee-65b8-40ed-bef2-eaad723ab905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144931557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.4144931557
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2131590867
Short name T251
Test name
Test status
Simulation time 64456825 ps
CPU time 0.77 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200076 kb
Host smart-abc009c3-8249-4401-aab5-708a7f057d6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131590867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2131590867
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.370631444
Short name T512
Test name
Test status
Simulation time 1226133756 ps
CPU time 5.96 seconds
Started Aug 03 04:39:27 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 216712 kb
Host smart-521fd1b3-df55-40f2-8de0-96aaf87dec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370631444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.370631444
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2117206170
Short name T536
Test name
Test status
Simulation time 243621369 ps
CPU time 1.06 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 217356 kb
Host smart-68d31731-c7dc-4a9c-8658-93187429e3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117206170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2117206170
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3882768800
Short name T509
Test name
Test status
Simulation time 160410744 ps
CPU time 0.82 seconds
Started Aug 03 04:39:35 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 200084 kb
Host smart-c129d28a-05ed-4f4d-b051-ae49d12b529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882768800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3882768800
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1722914353
Short name T486
Test name
Test status
Simulation time 1104950989 ps
CPU time 5.06 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:34 PM PDT 24
Peak memory 200396 kb
Host smart-d9a3a105-495a-4432-92bf-748a58a6bb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722914353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1722914353
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3874323202
Short name T26
Test name
Test status
Simulation time 178196545 ps
CPU time 1.27 seconds
Started Aug 03 04:39:23 PM PDT 24
Finished Aug 03 04:39:24 PM PDT 24
Peak memory 200292 kb
Host smart-b951d02f-3e58-4e0e-bc32-0c793b4c7177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874323202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3874323202
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1005324540
Short name T275
Test name
Test status
Simulation time 121904397 ps
CPU time 1.29 seconds
Started Aug 03 04:39:22 PM PDT 24
Finished Aug 03 04:39:24 PM PDT 24
Peak memory 200432 kb
Host smart-b8240553-273b-48e8-82c2-493e8e3b5424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005324540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1005324540
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1635498937
Short name T477
Test name
Test status
Simulation time 5294156665 ps
CPU time 22.87 seconds
Started Aug 03 04:39:22 PM PDT 24
Finished Aug 03 04:39:45 PM PDT 24
Peak memory 200576 kb
Host smart-e8b8d07a-23f3-4d4b-8683-7a7db49475b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635498937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1635498937
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3296120070
Short name T249
Test name
Test status
Simulation time 117577873 ps
CPU time 1.43 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 200248 kb
Host smart-40d9d58c-f51f-41ba-9d67-04bfdba499b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296120070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3296120070
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.304774716
Short name T510
Test name
Test status
Simulation time 82402535 ps
CPU time 0.83 seconds
Started Aug 03 04:39:25 PM PDT 24
Finished Aug 03 04:39:26 PM PDT 24
Peak memory 200212 kb
Host smart-0288da39-1108-44f8-b5c8-bb6cdb84fd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304774716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.304774716
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3242314356
Short name T211
Test name
Test status
Simulation time 62188905 ps
CPU time 0.74 seconds
Started Aug 03 04:39:26 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 200096 kb
Host smart-5ce72528-96ce-4ab9-9cdb-189b72629980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242314356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3242314356
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2033396171
Short name T35
Test name
Test status
Simulation time 2197256632 ps
CPU time 7.79 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:42 PM PDT 24
Peak memory 217432 kb
Host smart-9408952f-f81b-4504-9a2f-c59b4edbc507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033396171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2033396171
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2926583497
Short name T71
Test name
Test status
Simulation time 244281228 ps
CPU time 1.02 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 217348 kb
Host smart-98dd0c93-996e-4e79-9a0b-7222e6c8394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926583497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2926583497
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.347911046
Short name T435
Test name
Test status
Simulation time 149118512 ps
CPU time 0.85 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:34 PM PDT 24
Peak memory 200084 kb
Host smart-818d8a9f-d089-4c2f-8882-ec5cb4c86374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347911046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.347911046
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3883183879
Short name T379
Test name
Test status
Simulation time 1752719781 ps
CPU time 5.78 seconds
Started Aug 03 04:39:35 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 200480 kb
Host smart-61e02cf1-1ebd-40d7-942f-cc2f7506257e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883183879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3883183879
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2161069626
Short name T375
Test name
Test status
Simulation time 97111563 ps
CPU time 0.98 seconds
Started Aug 03 04:39:23 PM PDT 24
Finished Aug 03 04:39:24 PM PDT 24
Peak memory 200288 kb
Host smart-915fa7eb-e9fb-48ae-95ec-e3b7ac15b865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161069626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2161069626
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1883848006
Short name T400
Test name
Test status
Simulation time 247289076 ps
CPU time 1.46 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:35 PM PDT 24
Peak memory 200328 kb
Host smart-76d6458a-6ffa-4a35-81d2-531600bc80ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883848006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1883848006
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2707862263
Short name T313
Test name
Test status
Simulation time 5036694302 ps
CPU time 23.51 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:40:01 PM PDT 24
Peak memory 208652 kb
Host smart-ec3765ef-f608-4bde-8e1b-1a4186ad0a33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707862263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2707862263
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2756027000
Short name T157
Test name
Test status
Simulation time 469239975 ps
CPU time 2.43 seconds
Started Aug 03 04:39:26 PM PDT 24
Finished Aug 03 04:39:29 PM PDT 24
Peak memory 208424 kb
Host smart-4a046d8d-48b2-4ae0-93e3-4b77577e09df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756027000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2756027000
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3366442541
Short name T427
Test name
Test status
Simulation time 91409292 ps
CPU time 0.93 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200296 kb
Host smart-ecf3bd7a-fa77-4d0d-8410-1d60bcbfc5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366442541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3366442541
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2519281720
Short name T352
Test name
Test status
Simulation time 60159578 ps
CPU time 0.74 seconds
Started Aug 03 04:39:25 PM PDT 24
Finished Aug 03 04:39:26 PM PDT 24
Peak memory 200100 kb
Host smart-14c8a101-4abc-4667-9108-f346739e2d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519281720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2519281720
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3243841240
Short name T4
Test name
Test status
Simulation time 1892637648 ps
CPU time 7 seconds
Started Aug 03 04:39:35 PM PDT 24
Finished Aug 03 04:39:42 PM PDT 24
Peak memory 217388 kb
Host smart-4a6120c4-5d76-431a-90e7-2d712838551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243841240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3243841240
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1926627675
Short name T1
Test name
Test status
Simulation time 244200214 ps
CPU time 1.06 seconds
Started Aug 03 04:39:23 PM PDT 24
Finished Aug 03 04:39:24 PM PDT 24
Peak memory 217300 kb
Host smart-53bd55a1-1941-4e95-8676-d48e65e84cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926627675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1926627675
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.468560546
Short name T17
Test name
Test status
Simulation time 106535306 ps
CPU time 0.8 seconds
Started Aug 03 04:39:45 PM PDT 24
Finished Aug 03 04:39:46 PM PDT 24
Peak memory 200016 kb
Host smart-7b6d42e0-5d1b-46fc-abcb-e17b784ef69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468560546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.468560546
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.4243932062
Short name T215
Test name
Test status
Simulation time 882044221 ps
CPU time 4.19 seconds
Started Aug 03 04:39:20 PM PDT 24
Finished Aug 03 04:39:24 PM PDT 24
Peak memory 200336 kb
Host smart-ad4b34b2-9def-48cc-8cea-433cac8dda9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243932062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.4243932062
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.358807477
Short name T210
Test name
Test status
Simulation time 110903609 ps
CPU time 1.03 seconds
Started Aug 03 04:39:23 PM PDT 24
Finished Aug 03 04:39:24 PM PDT 24
Peak memory 200180 kb
Host smart-a29cdae6-d34e-4a31-83b6-ef3edab20e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358807477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.358807477
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.802452669
Short name T329
Test name
Test status
Simulation time 197583453 ps
CPU time 1.37 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200440 kb
Host smart-bb604955-48cf-4367-b913-8af9878b3cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802452669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.802452669
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2630744598
Short name T468
Test name
Test status
Simulation time 5015150524 ps
CPU time 25.12 seconds
Started Aug 03 04:39:23 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200604 kb
Host smart-ed9925fb-60ce-45e3-8670-3c74a6cc8a2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630744598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2630744598
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1417526456
Short name T333
Test name
Test status
Simulation time 125905092 ps
CPU time 1.6 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 200120 kb
Host smart-e06f78e5-c1f7-4229-857b-99776909b272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417526456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1417526456
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3562267325
Short name T294
Test name
Test status
Simulation time 107568247 ps
CPU time 0.98 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200264 kb
Host smart-03f03885-3d7f-4be4-904b-afb442ea46d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562267325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3562267325
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1375490687
Short name T323
Test name
Test status
Simulation time 73444991 ps
CPU time 0.85 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:30 PM PDT 24
Peak memory 200088 kb
Host smart-814f5fca-3c95-4417-a2f2-8fcc5a2461e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375490687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1375490687
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.4176953050
Short name T461
Test name
Test status
Simulation time 1895547939 ps
CPU time 7.64 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 217396 kb
Host smart-b2786e4b-d1e3-48db-b5c6-67c167fa49b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176953050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.4176953050
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3296543977
Short name T257
Test name
Test status
Simulation time 244957903 ps
CPU time 1.06 seconds
Started Aug 03 04:39:30 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 217376 kb
Host smart-02b699a1-f520-459c-a7ec-d40c6cce305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296543977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3296543977
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2997637366
Short name T408
Test name
Test status
Simulation time 134160127 ps
CPU time 0.82 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200100 kb
Host smart-ae296b19-64a1-4a19-a2c5-b1d7d9a2dbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997637366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2997637366
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.953321072
Short name T377
Test name
Test status
Simulation time 930127302 ps
CPU time 4.59 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 200496 kb
Host smart-d46a95d9-a4ac-4a38-8034-a606d77db0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953321072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.953321072
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1971681389
Short name T366
Test name
Test status
Simulation time 107414682 ps
CPU time 1 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:35 PM PDT 24
Peak memory 200232 kb
Host smart-2f70d221-5d56-47e1-8357-b28b3922e6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971681389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1971681389
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.4140100027
Short name T155
Test name
Test status
Simulation time 255082051 ps
CPU time 1.61 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200388 kb
Host smart-ca273c3e-09f2-4522-8155-592dc3315969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140100027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.4140100027
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1046695363
Short name T347
Test name
Test status
Simulation time 1853427991 ps
CPU time 6.86 seconds
Started Aug 03 04:39:31 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 200416 kb
Host smart-84ef8860-7f48-4c1c-b5e2-2b2dc99a952e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046695363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1046695363
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3343007313
Short name T179
Test name
Test status
Simulation time 117564117 ps
CPU time 1.51 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 200120 kb
Host smart-d6381f26-84bd-4f45-90cf-dc94f61a531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343007313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3343007313
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.27114802
Short name T152
Test name
Test status
Simulation time 88081207 ps
CPU time 0.89 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 200284 kb
Host smart-29ea44c9-0b18-4b5a-8ad2-3bb65c4bafbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27114802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.27114802
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3117773490
Short name T219
Test name
Test status
Simulation time 292194066 ps
CPU time 1.26 seconds
Started Aug 03 04:38:50 PM PDT 24
Finished Aug 03 04:38:51 PM PDT 24
Peak memory 200088 kb
Host smart-2f63003b-0750-4272-bc45-ae802c34b02f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117773490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3117773490
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.495160550
Short name T368
Test name
Test status
Simulation time 1894842211 ps
CPU time 6.55 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:49 PM PDT 24
Peak memory 217660 kb
Host smart-093cf991-61e8-4a4a-8ac3-83e67eab0516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495160550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.495160550
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1423933467
Short name T364
Test name
Test status
Simulation time 244942401 ps
CPU time 1.04 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:43 PM PDT 24
Peak memory 217508 kb
Host smart-80a242f6-1c79-4ebd-9146-c0263f8315a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423933467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1423933467
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1939274412
Short name T506
Test name
Test status
Simulation time 184491119 ps
CPU time 0.85 seconds
Started Aug 03 04:38:41 PM PDT 24
Finished Aug 03 04:38:42 PM PDT 24
Peak memory 200068 kb
Host smart-6e08d5b0-0e1d-4a4a-b97d-f75eb6ff39ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939274412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1939274412
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3513099175
Short name T391
Test name
Test status
Simulation time 758197512 ps
CPU time 4.1 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:47 PM PDT 24
Peak memory 200496 kb
Host smart-77a7d845-1138-4b6f-9ab6-c8f57e20e022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513099175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3513099175
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3610516921
Short name T69
Test name
Test status
Simulation time 8276352828 ps
CPU time 15.4 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:59 PM PDT 24
Peak memory 217372 kb
Host smart-de7fc77e-9574-46e0-bcf6-2b72cfeb1fea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610516921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3610516921
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2301587326
Short name T446
Test name
Test status
Simulation time 156489141 ps
CPU time 1.08 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:44 PM PDT 24
Peak memory 200272 kb
Host smart-927c1f05-2816-44e2-bf5f-6c3b509290f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301587326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2301587326
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2947255330
Short name T239
Test name
Test status
Simulation time 241785506 ps
CPU time 1.42 seconds
Started Aug 03 04:38:44 PM PDT 24
Finished Aug 03 04:38:46 PM PDT 24
Peak memory 200392 kb
Host smart-cb0be1cf-98ca-444c-bdf3-dddef8cef14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947255330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2947255330
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1494798376
Short name T327
Test name
Test status
Simulation time 6519590018 ps
CPU time 28.02 seconds
Started Aug 03 04:38:44 PM PDT 24
Finished Aug 03 04:39:12 PM PDT 24
Peak memory 208716 kb
Host smart-46fb1dad-d0ba-4ee3-97d6-4cd1010609ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494798376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1494798376
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3979161049
Short name T370
Test name
Test status
Simulation time 344740445 ps
CPU time 1.94 seconds
Started Aug 03 04:38:44 PM PDT 24
Finished Aug 03 04:38:46 PM PDT 24
Peak memory 200196 kb
Host smart-b453376c-7d4b-4fba-a4d1-b8d5db128959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979161049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3979161049
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3175389245
Short name T260
Test name
Test status
Simulation time 99771655 ps
CPU time 0.86 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:44 PM PDT 24
Peak memory 200188 kb
Host smart-052aaa8b-5923-4c5e-a985-864b138a6f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175389245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3175389245
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1720960442
Short name T224
Test name
Test status
Simulation time 71988803 ps
CPU time 0.82 seconds
Started Aug 03 04:39:31 PM PDT 24
Finished Aug 03 04:39:32 PM PDT 24
Peak memory 200096 kb
Host smart-eecb15a1-b8e4-43c2-9d2f-9f069e6776ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720960442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1720960442
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.411322829
Short name T40
Test name
Test status
Simulation time 1886214806 ps
CPU time 7.51 seconds
Started Aug 03 04:39:35 PM PDT 24
Finished Aug 03 04:39:43 PM PDT 24
Peak memory 217444 kb
Host smart-b3489626-7b11-4088-a793-6c338d59161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411322829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.411322829
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3205365775
Short name T528
Test name
Test status
Simulation time 245035354 ps
CPU time 1.11 seconds
Started Aug 03 04:39:31 PM PDT 24
Finished Aug 03 04:39:32 PM PDT 24
Peak memory 217352 kb
Host smart-cc4ce2e8-774b-4eb9-b8b4-e9a5438d672e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205365775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3205365775
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3732660555
Short name T18
Test name
Test status
Simulation time 83398089 ps
CPU time 0.76 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:30 PM PDT 24
Peak memory 200088 kb
Host smart-53d458d6-e924-4fc1-b385-64c9c927d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732660555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3732660555
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1305048640
Short name T274
Test name
Test status
Simulation time 795783839 ps
CPU time 4.4 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200480 kb
Host smart-3e52a83f-e323-4c48-bca6-41c8f85e307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305048640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1305048640
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3655836540
Short name T498
Test name
Test status
Simulation time 103245250 ps
CPU time 1.01 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:34 PM PDT 24
Peak memory 200288 kb
Host smart-de5d7f6a-193d-46e9-a593-65f554592031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655836540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3655836540
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4188922454
Short name T426
Test name
Test status
Simulation time 120497281 ps
CPU time 1.23 seconds
Started Aug 03 04:39:40 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 200420 kb
Host smart-5df1ab9b-8fca-4f2f-8950-8d58006dfd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188922454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4188922454
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2223933555
Short name T74
Test name
Test status
Simulation time 4417061943 ps
CPU time 18.63 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:53 PM PDT 24
Peak memory 200532 kb
Host smart-f175a2d3-d914-45b5-9222-c5b384c3d63e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223933555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2223933555
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4090884171
Short name T437
Test name
Test status
Simulation time 411402837 ps
CPU time 2.42 seconds
Started Aug 03 04:39:35 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 208632 kb
Host smart-4960082b-6b66-4bc3-aaef-55d66f9fe466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090884171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4090884171
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.116407902
Short name T256
Test name
Test status
Simulation time 225782107 ps
CPU time 1.39 seconds
Started Aug 03 04:39:28 PM PDT 24
Finished Aug 03 04:39:29 PM PDT 24
Peak memory 200288 kb
Host smart-42800110-df0b-4e62-8ee5-ee91d335eb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116407902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.116407902
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2331690910
Short name T348
Test name
Test status
Simulation time 58522224 ps
CPU time 0.7 seconds
Started Aug 03 04:39:30 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 199944 kb
Host smart-824a5482-80c1-4c13-9e57-836611743c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331690910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2331690910
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1349346684
Short name T392
Test name
Test status
Simulation time 2349463918 ps
CPU time 7.79 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:46 PM PDT 24
Peak memory 217696 kb
Host smart-f9e5822f-7ca8-4608-9e03-8f2ce5fd9272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349346684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1349346684
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.812974268
Short name T322
Test name
Test status
Simulation time 243656769 ps
CPU time 1.07 seconds
Started Aug 03 04:39:40 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 217424 kb
Host smart-1f41fa1a-d4e6-4501-a6b1-2ef59dad9d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812974268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.812974268
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.727324725
Short name T19
Test name
Test status
Simulation time 102111888 ps
CPU time 0.79 seconds
Started Aug 03 04:39:35 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 200084 kb
Host smart-fe33c608-f9ee-44c5-bb10-fc315e7c3194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727324725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.727324725
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3278505380
Short name T220
Test name
Test status
Simulation time 1437667229 ps
CPU time 6.03 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:43 PM PDT 24
Peak memory 200364 kb
Host smart-e81d86a7-849e-4861-924b-065caa1659de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278505380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3278505380
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1791033998
Short name T317
Test name
Test status
Simulation time 153913553 ps
CPU time 1.19 seconds
Started Aug 03 04:39:39 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200248 kb
Host smart-04f1f8bd-0943-4ff8-bfab-590dbdc71c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791033998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1791033998
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3672375680
Short name T233
Test name
Test status
Simulation time 244116896 ps
CPU time 1.52 seconds
Started Aug 03 04:39:35 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200476 kb
Host smart-791e63c1-c29b-497a-bf37-f04bd4b308c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672375680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3672375680
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3324191078
Short name T341
Test name
Test status
Simulation time 3968610845 ps
CPU time 18.11 seconds
Started Aug 03 04:39:39 PM PDT 24
Finished Aug 03 04:39:57 PM PDT 24
Peak memory 200608 kb
Host smart-dad945bf-33b8-4cd3-b09e-06eccb1027c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324191078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3324191078
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1657591473
Short name T5
Test name
Test status
Simulation time 148246383 ps
CPU time 1.81 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 200200 kb
Host smart-718954e5-65d9-49b2-8279-698dc2f11a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657591473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1657591473
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2356558517
Short name T462
Test name
Test status
Simulation time 166736033 ps
CPU time 1.1 seconds
Started Aug 03 04:39:39 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200276 kb
Host smart-e9f15c0f-5990-45d1-a4e0-edcb04a5a5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356558517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2356558517
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1373029712
Short name T299
Test name
Test status
Simulation time 76235454 ps
CPU time 0.86 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 199976 kb
Host smart-48491da7-376a-4088-b18f-70eca332bdaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373029712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1373029712
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1605970633
Short name T441
Test name
Test status
Simulation time 1224501564 ps
CPU time 5.66 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 217036 kb
Host smart-461d5f74-2c8f-4456-a89c-2e631738ab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605970633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1605970633
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.414996536
Short name T175
Test name
Test status
Simulation time 244610379 ps
CPU time 1.18 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 217472 kb
Host smart-78b1d671-0963-47f9-9257-e4ec0d8266b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414996536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.414996536
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2492958934
Short name T444
Test name
Test status
Simulation time 221247206 ps
CPU time 0.96 seconds
Started Aug 03 04:39:30 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 200056 kb
Host smart-42b5b17c-2104-41ad-ba59-dea13915a0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492958934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2492958934
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.692634490
Short name T101
Test name
Test status
Simulation time 873363756 ps
CPU time 4.28 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 200508 kb
Host smart-0ddcfa14-86a3-4fa6-b4ac-18e7259a87ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692634490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.692634490
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1366077284
Short name T281
Test name
Test status
Simulation time 99749292 ps
CPU time 1.03 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:34 PM PDT 24
Peak memory 200092 kb
Host smart-f2cd3d4c-b50e-4539-9751-2a6dd35fedca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366077284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1366077284
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.361154600
Short name T282
Test name
Test status
Simulation time 197189422 ps
CPU time 1.36 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 200464 kb
Host smart-35164392-95ad-4d6d-85ff-c459ff41561b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361154600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.361154600
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.4050536866
Short name T531
Test name
Test status
Simulation time 2368217423 ps
CPU time 8.2 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 200528 kb
Host smart-dc1f1900-df02-4069-8b31-6350f49011af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050536866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.4050536866
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3061484166
Short name T81
Test name
Test status
Simulation time 148622896 ps
CPU time 1.88 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200168 kb
Host smart-c73cd3c1-dc82-4efe-b69c-773a53907a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061484166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3061484166
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2412070654
Short name T340
Test name
Test status
Simulation time 86284136 ps
CPU time 0.88 seconds
Started Aug 03 04:39:30 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 200288 kb
Host smart-426f6fbd-eb99-4a86-b5d9-312f9c742371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412070654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2412070654
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.764753804
Short name T488
Test name
Test status
Simulation time 80237266 ps
CPU time 0.79 seconds
Started Aug 03 04:39:40 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 200292 kb
Host smart-87acc483-0af3-4b5b-b9cc-77de324ade9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764753804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.764753804
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.543057506
Short name T314
Test name
Test status
Simulation time 1216208848 ps
CPU time 5.62 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:44 PM PDT 24
Peak memory 217608 kb
Host smart-f21f60ab-ab69-425a-923b-2b1f620183a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543057506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.543057506
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.976965678
Short name T153
Test name
Test status
Simulation time 244661747 ps
CPU time 1.21 seconds
Started Aug 03 04:39:30 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 217516 kb
Host smart-b45b02e8-441d-4892-9ecc-00ae5f98ec60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976965678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.976965678
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3074869050
Short name T430
Test name
Test status
Simulation time 198982635 ps
CPU time 0.96 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 200016 kb
Host smart-fa4c18a9-2830-4bd9-899f-366e56585369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074869050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3074869050
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2993129768
Short name T362
Test name
Test status
Simulation time 2074626321 ps
CPU time 7.39 seconds
Started Aug 03 04:39:39 PM PDT 24
Finished Aug 03 04:39:47 PM PDT 24
Peak memory 200452 kb
Host smart-31210123-ac2e-4ee8-9f02-4065af45ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993129768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2993129768
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1532269958
Short name T135
Test name
Test status
Simulation time 145243683 ps
CPU time 1.09 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 200212 kb
Host smart-df5a3b49-10c2-4c0a-877d-8c205b68e6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532269958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1532269958
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3228666347
Short name T367
Test name
Test status
Simulation time 115613346 ps
CPU time 1.24 seconds
Started Aug 03 04:39:31 PM PDT 24
Finished Aug 03 04:39:32 PM PDT 24
Peak memory 200356 kb
Host smart-b7fc5820-d372-4bfd-b4f2-4fccae9563d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228666347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3228666347
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1437883774
Short name T449
Test name
Test status
Simulation time 2072549373 ps
CPU time 7.75 seconds
Started Aug 03 04:39:40 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200480 kb
Host smart-adad9f15-8ea7-4a66-9844-801d07788335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437883774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1437883774
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2752876103
Short name T485
Test name
Test status
Simulation time 453115660 ps
CPU time 2.43 seconds
Started Aug 03 04:39:30 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 200236 kb
Host smart-2e0fca72-9c4e-4c96-a535-45701b65aab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752876103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2752876103
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3519586998
Short name T324
Test name
Test status
Simulation time 57820852 ps
CPU time 0.74 seconds
Started Aug 03 04:39:33 PM PDT 24
Finished Aug 03 04:39:34 PM PDT 24
Peak memory 200260 kb
Host smart-865aa9cf-1633-4b9b-bdae-ae72db935146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519586998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3519586998
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1185630140
Short name T212
Test name
Test status
Simulation time 66946335 ps
CPU time 0.75 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:30 PM PDT 24
Peak memory 200080 kb
Host smart-0f8a0539-96cd-49a7-8dd8-da4a770502a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185630140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1185630140
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3186611858
Short name T530
Test name
Test status
Simulation time 1226417635 ps
CPU time 5.51 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 221612 kb
Host smart-1afa6cc2-b7e7-4e45-ba78-322af7257c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186611858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3186611858
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.260536364
Short name T515
Test name
Test status
Simulation time 243988555 ps
CPU time 1.18 seconds
Started Aug 03 04:39:31 PM PDT 24
Finished Aug 03 04:39:32 PM PDT 24
Peak memory 217464 kb
Host smart-fca9bc7e-cb28-47e7-9bd2-1f7e802c302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260536364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.260536364
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.4092661551
Short name T447
Test name
Test status
Simulation time 133458068 ps
CPU time 0.82 seconds
Started Aug 03 04:39:39 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200052 kb
Host smart-2787aaeb-7f5d-443b-9146-23535a8223bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092661551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.4092661551
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2403915131
Short name T523
Test name
Test status
Simulation time 818530258 ps
CPU time 4.15 seconds
Started Aug 03 04:39:44 PM PDT 24
Finished Aug 03 04:39:49 PM PDT 24
Peak memory 200372 kb
Host smart-08b2bf7a-7ed8-4a1c-9c68-b9db6e3e9015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403915131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2403915131
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2618448014
Short name T497
Test name
Test status
Simulation time 156579457 ps
CPU time 1.17 seconds
Started Aug 03 04:39:32 PM PDT 24
Finished Aug 03 04:39:34 PM PDT 24
Peak memory 200260 kb
Host smart-3d9b204b-1451-464f-823f-43ed20e687ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618448014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2618448014
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.679098726
Short name T123
Test name
Test status
Simulation time 247525411 ps
CPU time 1.57 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200292 kb
Host smart-a71160d1-d8ec-48b0-bd1e-8f242779a2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679098726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.679098726
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.234090074
Short name T336
Test name
Test status
Simulation time 6611426310 ps
CPU time 23.31 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:57 PM PDT 24
Peak memory 208744 kb
Host smart-6f4448e9-2bfe-448b-b7a8-4cdcae8e337d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234090074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.234090074
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4232776684
Short name T266
Test name
Test status
Simulation time 138620929 ps
CPU time 1.67 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 208416 kb
Host smart-a6c72383-fd81-44af-9c6b-935c612a2682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232776684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4232776684
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3252611043
Short name T483
Test name
Test status
Simulation time 120648317 ps
CPU time 1.01 seconds
Started Aug 03 04:39:39 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200228 kb
Host smart-aaae0ef4-b619-4c68-8597-56e1e7bbaf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252611043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3252611043
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1701846200
Short name T425
Test name
Test status
Simulation time 80365714 ps
CPU time 0.81 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200056 kb
Host smart-008329ef-bc36-486a-ae5c-551198533860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701846200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1701846200
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1098102146
Short name T33
Test name
Test status
Simulation time 1230171274 ps
CPU time 5.62 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:44 PM PDT 24
Peak memory 221664 kb
Host smart-6a9dfd01-8628-4706-a656-3d414edf26ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098102146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1098102146
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2639986132
Short name T126
Test name
Test status
Simulation time 244785521 ps
CPU time 1.13 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 217392 kb
Host smart-ac6a3e2c-1a9f-4b8a-9d08-6ad0d5e06637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639986132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2639986132
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3325300571
Short name T223
Test name
Test status
Simulation time 92701085 ps
CPU time 0.82 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200096 kb
Host smart-1a6b866c-d7bd-4fbb-93f9-68614e658530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325300571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3325300571
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3565521500
Short name T94
Test name
Test status
Simulation time 2080389458 ps
CPU time 7.77 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:46 PM PDT 24
Peak memory 200544 kb
Host smart-c4575c10-a1c5-4a45-912c-9101f6ed4b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565521500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3565521500
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4131587042
Short name T460
Test name
Test status
Simulation time 146993160 ps
CPU time 1.2 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 200296 kb
Host smart-8c99ce24-d910-4f7e-bd69-f0fd0729fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131587042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4131587042
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2743567088
Short name T365
Test name
Test status
Simulation time 112777170 ps
CPU time 1.24 seconds
Started Aug 03 04:39:29 PM PDT 24
Finished Aug 03 04:39:31 PM PDT 24
Peak memory 200416 kb
Host smart-3e218d69-db30-4670-a5a2-d68d475ae7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743567088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2743567088
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1722648839
Short name T371
Test name
Test status
Simulation time 1856511849 ps
CPU time 7.44 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:44 PM PDT 24
Peak memory 200520 kb
Host smart-92eb9080-378c-4407-86bf-b736357347dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722648839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1722648839
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2913559132
Short name T184
Test name
Test status
Simulation time 371741778 ps
CPU time 2.38 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200252 kb
Host smart-e8bd8c2c-1a4a-4379-9f49-c3d590a4373e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913559132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2913559132
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.110739181
Short name T140
Test name
Test status
Simulation time 85527701 ps
CPU time 0.88 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200268 kb
Host smart-e4299dbe-5e40-4fae-81f2-a841849319e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110739181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.110739181
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2532326439
Short name T292
Test name
Test status
Simulation time 73613892 ps
CPU time 0.78 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 200072 kb
Host smart-561be502-dc50-486e-a0eb-347c844d7266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532326439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2532326439
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1827551764
Short name T44
Test name
Test status
Simulation time 1874553694 ps
CPU time 7.36 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:45 PM PDT 24
Peak memory 221588 kb
Host smart-9c7899e3-b84f-4c3c-9a56-5a65dd967ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827551764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1827551764
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3432833732
Short name T8
Test name
Test status
Simulation time 244494996 ps
CPU time 1.04 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 217452 kb
Host smart-f7abcd1d-c6d8-40ef-bb70-880bde447932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432833732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3432833732
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1852831880
Short name T492
Test name
Test status
Simulation time 135663227 ps
CPU time 0.86 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200072 kb
Host smart-c80669f9-a478-4d04-b531-239a42957be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852831880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1852831880
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.395797320
Short name T116
Test name
Test status
Simulation time 1391759445 ps
CPU time 5.48 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:44 PM PDT 24
Peak memory 200420 kb
Host smart-a5f97f63-2249-40a2-a0b0-adbf04f43105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395797320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.395797320
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4066116615
Short name T369
Test name
Test status
Simulation time 176581875 ps
CPU time 1.14 seconds
Started Aug 03 04:39:41 PM PDT 24
Finished Aug 03 04:39:43 PM PDT 24
Peak memory 200268 kb
Host smart-579a99b3-9893-470e-8089-0d1336fca855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066116615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4066116615
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1919185042
Short name T198
Test name
Test status
Simulation time 111329736 ps
CPU time 1.15 seconds
Started Aug 03 04:39:34 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 200408 kb
Host smart-a2c189f8-07f3-42f4-9e02-ccb8fffafeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919185042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1919185042
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.4063481749
Short name T445
Test name
Test status
Simulation time 3630515106 ps
CPU time 16.02 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:55 PM PDT 24
Peak memory 209556 kb
Host smart-3e701dc5-17a1-4c50-9318-6b8232a39f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063481749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.4063481749
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3072773278
Short name T173
Test name
Test status
Simulation time 328366777 ps
CPU time 1.83 seconds
Started Aug 03 04:39:41 PM PDT 24
Finished Aug 03 04:39:43 PM PDT 24
Peak memory 200140 kb
Host smart-2a2e18f7-857c-4f6e-a349-021661f4eb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072773278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3072773278
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1915807846
Short name T189
Test name
Test status
Simulation time 109789398 ps
CPU time 1.05 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200252 kb
Host smart-d34df180-cb39-4fc9-af63-268a7d073377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915807846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1915807846
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3955157987
Short name T136
Test name
Test status
Simulation time 77411083 ps
CPU time 0.76 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200068 kb
Host smart-2f5db090-017e-45fc-a4cc-47447415c21c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955157987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3955157987
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1618240692
Short name T38
Test name
Test status
Simulation time 1213948330 ps
CPU time 5.67 seconds
Started Aug 03 04:39:39 PM PDT 24
Finished Aug 03 04:39:45 PM PDT 24
Peak memory 217564 kb
Host smart-cb159a5f-038b-482e-97c1-4ca98fd62c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618240692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1618240692
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3954381311
Short name T372
Test name
Test status
Simulation time 244040603 ps
CPU time 1.1 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 217436 kb
Host smart-5b23d6bc-57dd-4446-bb1a-b8c88e40df10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954381311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3954381311
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1024687719
Short name T455
Test name
Test status
Simulation time 224290228 ps
CPU time 1.01 seconds
Started Aug 03 04:39:35 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200084 kb
Host smart-a0c8bc44-f21c-418c-af02-77bfffe8f6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024687719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1024687719
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3718752544
Short name T423
Test name
Test status
Simulation time 1669046099 ps
CPU time 6.2 seconds
Started Aug 03 04:39:40 PM PDT 24
Finished Aug 03 04:39:46 PM PDT 24
Peak memory 200484 kb
Host smart-6678197b-eaf0-4d10-9228-e9994778e2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718752544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3718752544
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3700862124
Short name T130
Test name
Test status
Simulation time 145904039 ps
CPU time 1.08 seconds
Started Aug 03 04:39:40 PM PDT 24
Finished Aug 03 04:39:42 PM PDT 24
Peak memory 200292 kb
Host smart-7f6d4c1e-6a20-484a-a15e-24a75af61547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700862124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3700862124
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.41147885
Short name T241
Test name
Test status
Simulation time 240324460 ps
CPU time 1.52 seconds
Started Aug 03 04:39:53 PM PDT 24
Finished Aug 03 04:39:54 PM PDT 24
Peak memory 200440 kb
Host smart-4daea19a-e286-42d0-8aed-25b0dc199272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41147885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.41147885
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2806523336
Short name T382
Test name
Test status
Simulation time 6196748182 ps
CPU time 22.93 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:40:02 PM PDT 24
Peak memory 208748 kb
Host smart-1ec55c03-43e3-43a1-aa0f-9ad5ab8fab36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806523336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2806523336
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2996239882
Short name T513
Test name
Test status
Simulation time 454747871 ps
CPU time 2.78 seconds
Started Aug 03 04:39:45 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200220 kb
Host smart-ac641804-b063-47c2-97e1-0873cfd8fb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996239882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2996239882
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.66857704
Short name T442
Test name
Test status
Simulation time 211154439 ps
CPU time 1.29 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200292 kb
Host smart-dfca5527-a3cb-4627-974e-c5646e2fbb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66857704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.66857704
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3622434525
Short name T183
Test name
Test status
Simulation time 70910839 ps
CPU time 0.79 seconds
Started Aug 03 04:39:39 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200100 kb
Host smart-289674a1-a9b1-420b-bc3d-ec4ae12c01e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622434525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3622434525
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1892824296
Short name T39
Test name
Test status
Simulation time 1897966063 ps
CPU time 6.98 seconds
Started Aug 03 04:39:44 PM PDT 24
Finished Aug 03 04:39:51 PM PDT 24
Peak memory 221580 kb
Host smart-75ca4d2e-21ab-4330-9723-1e5b299799f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892824296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1892824296
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1208987831
Short name T202
Test name
Test status
Simulation time 244485986 ps
CPU time 1.11 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 217436 kb
Host smart-bfc8f16e-1418-4a89-ae5d-7f14dc0a9c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208987831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1208987831
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3270258590
Short name T177
Test name
Test status
Simulation time 131410323 ps
CPU time 0.8 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 200088 kb
Host smart-6cced800-aaf9-4f8f-8b78-053886d03e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270258590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3270258590
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1212663601
Short name T254
Test name
Test status
Simulation time 1542758640 ps
CPU time 6.26 seconds
Started Aug 03 04:39:41 PM PDT 24
Finished Aug 03 04:39:47 PM PDT 24
Peak memory 200488 kb
Host smart-b6d98334-8e28-4edd-b8c2-3a86e456a283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212663601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1212663601
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3736613880
Short name T454
Test name
Test status
Simulation time 97999467 ps
CPU time 1.02 seconds
Started Aug 03 04:39:44 PM PDT 24
Finished Aug 03 04:39:45 PM PDT 24
Peak memory 200260 kb
Host smart-50b02cbc-8542-4aa4-a7f5-dac72780bfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736613880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3736613880
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1674498073
Short name T181
Test name
Test status
Simulation time 234357161 ps
CPU time 1.53 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:38 PM PDT 24
Peak memory 200384 kb
Host smart-9cdacc0c-e7f6-44ba-9330-fcc9283a16c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674498073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1674498073
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1672458288
Short name T524
Test name
Test status
Simulation time 3517056935 ps
CPU time 17.03 seconds
Started Aug 03 04:39:44 PM PDT 24
Finished Aug 03 04:40:01 PM PDT 24
Peak memory 216900 kb
Host smart-99a3d16d-6b13-49e1-aea9-6fde7043a141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672458288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1672458288
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1888266783
Short name T330
Test name
Test status
Simulation time 140830025 ps
CPU time 1.84 seconds
Started Aug 03 04:39:49 PM PDT 24
Finished Aug 03 04:39:51 PM PDT 24
Peak memory 200072 kb
Host smart-7920ec75-f7fd-48d0-83cc-83663be1a8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888266783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1888266783
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2953074772
Short name T422
Test name
Test status
Simulation time 246533059 ps
CPU time 1.45 seconds
Started Aug 03 04:39:41 PM PDT 24
Finished Aug 03 04:39:43 PM PDT 24
Peak memory 200436 kb
Host smart-e48e4560-7d1c-4b63-aa42-fcd44f5df9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953074772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2953074772
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.803320168
Short name T66
Test name
Test status
Simulation time 81232465 ps
CPU time 0.79 seconds
Started Aug 03 04:39:41 PM PDT 24
Finished Aug 03 04:39:42 PM PDT 24
Peak memory 200088 kb
Host smart-65367516-bb9c-4027-bc18-20d19db75dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803320168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.803320168
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3907833486
Short name T49
Test name
Test status
Simulation time 1902429634 ps
CPU time 7.19 seconds
Started Aug 03 04:39:41 PM PDT 24
Finished Aug 03 04:39:49 PM PDT 24
Peak memory 217680 kb
Host smart-c11c1f56-5955-4ea1-b9cb-32c0c76c783b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907833486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3907833486
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.261127778
Short name T397
Test name
Test status
Simulation time 243863603 ps
CPU time 1.15 seconds
Started Aug 03 04:39:40 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 217440 kb
Host smart-692f2023-244d-4c66-8dc3-821e1f0408f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261127778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.261127778
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1161268881
Short name T273
Test name
Test status
Simulation time 117572340 ps
CPU time 0.77 seconds
Started Aug 03 04:39:36 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 200064 kb
Host smart-28452b82-d84b-4d8e-8dd5-c4045c22ea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161268881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1161268881
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.922903241
Short name T164
Test name
Test status
Simulation time 800070362 ps
CPU time 3.78 seconds
Started Aug 03 04:39:49 PM PDT 24
Finished Aug 03 04:39:52 PM PDT 24
Peak memory 200328 kb
Host smart-0d990c81-542c-4fcc-83d6-0dad76a07c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922903241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.922903241
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.535384670
Short name T526
Test name
Test status
Simulation time 154282494 ps
CPU time 1.14 seconds
Started Aug 03 04:39:49 PM PDT 24
Finished Aug 03 04:39:50 PM PDT 24
Peak memory 200120 kb
Host smart-1ede7fcc-c519-41d0-863d-8687b8e9869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535384670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.535384670
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2504910486
Short name T196
Test name
Test status
Simulation time 239915330 ps
CPU time 1.39 seconds
Started Aug 03 04:39:37 PM PDT 24
Finished Aug 03 04:39:39 PM PDT 24
Peak memory 200400 kb
Host smart-df2f2801-8c17-4624-addf-5d4465a78148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504910486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2504910486
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.147160761
Short name T261
Test name
Test status
Simulation time 2732963391 ps
CPU time 14.13 seconds
Started Aug 03 04:39:46 PM PDT 24
Finished Aug 03 04:40:00 PM PDT 24
Peak memory 200568 kb
Host smart-c179cddf-2059-470b-9c0a-3ac72f847734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147160761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.147160761
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2890544388
Short name T434
Test name
Test status
Simulation time 298662753 ps
CPU time 2.01 seconds
Started Aug 03 04:39:50 PM PDT 24
Finished Aug 03 04:39:52 PM PDT 24
Peak memory 208380 kb
Host smart-33639fb8-5632-4eef-b5aa-d164ccc0498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890544388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2890544388
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1084015677
Short name T13
Test name
Test status
Simulation time 166790834 ps
CPU time 1.12 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200208 kb
Host smart-422ac3b7-d360-4c46-a0dc-82a8cb1c314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084015677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1084015677
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3065105117
Short name T151
Test name
Test status
Simulation time 86901120 ps
CPU time 0.88 seconds
Started Aug 03 04:38:48 PM PDT 24
Finished Aug 03 04:38:49 PM PDT 24
Peak memory 199976 kb
Host smart-6c13e514-29b2-44cd-a1fe-c9851f3f9db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065105117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3065105117
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.731892302
Short name T194
Test name
Test status
Simulation time 2349387423 ps
CPU time 7.47 seconds
Started Aug 03 04:38:47 PM PDT 24
Finished Aug 03 04:38:55 PM PDT 24
Peak memory 221116 kb
Host smart-b1ec7631-9216-4640-b8a4-3bd5f053b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731892302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.731892302
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.372756941
Short name T433
Test name
Test status
Simulation time 244831657 ps
CPU time 1.2 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:44 PM PDT 24
Peak memory 217464 kb
Host smart-b4bc5e98-23eb-4e8e-b6e7-d732bdbdff86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372756941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.372756941
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1962980711
Short name T218
Test name
Test status
Simulation time 215540592 ps
CPU time 0.99 seconds
Started Aug 03 04:38:47 PM PDT 24
Finished Aug 03 04:38:48 PM PDT 24
Peak memory 200048 kb
Host smart-c2d78b55-513a-4300-9829-89cbe8c86c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962980711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1962980711
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1835125191
Short name T538
Test name
Test status
Simulation time 1498300205 ps
CPU time 6.51 seconds
Started Aug 03 04:38:41 PM PDT 24
Finished Aug 03 04:38:47 PM PDT 24
Peak memory 200488 kb
Host smart-2cdd9cef-54af-4b08-b502-b3c73bad4af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835125191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1835125191
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4047666906
Short name T70
Test name
Test status
Simulation time 16515917639 ps
CPU time 32.78 seconds
Started Aug 03 04:38:45 PM PDT 24
Finished Aug 03 04:39:18 PM PDT 24
Peak memory 217112 kb
Host smart-bf31bddb-9b6d-4979-818c-f3cc135043b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047666906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4047666906
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2719282790
Short name T473
Test name
Test status
Simulation time 108123563 ps
CPU time 1.01 seconds
Started Aug 03 04:38:47 PM PDT 24
Finished Aug 03 04:38:48 PM PDT 24
Peak memory 200248 kb
Host smart-3e2b49ad-aa24-40f8-89e1-ddf81d0a64dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719282790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2719282790
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1680884280
Short name T301
Test name
Test status
Simulation time 129029002 ps
CPU time 1.17 seconds
Started Aug 03 04:38:42 PM PDT 24
Finished Aug 03 04:38:43 PM PDT 24
Peak memory 200336 kb
Host smart-ab151e25-8dfc-4722-b0dc-5ae559b95984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680884280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1680884280
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2992271991
Short name T332
Test name
Test status
Simulation time 1530543271 ps
CPU time 8.09 seconds
Started Aug 03 04:38:48 PM PDT 24
Finished Aug 03 04:38:56 PM PDT 24
Peak memory 208612 kb
Host smart-00229d3e-eaeb-4f8f-8145-509755d14bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992271991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2992271991
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.409464367
Short name T272
Test name
Test status
Simulation time 364373955 ps
CPU time 2.33 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:45 PM PDT 24
Peak memory 200208 kb
Host smart-afeb5f64-5923-4f47-b773-2f60e2c2881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409464367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.409464367
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2048542099
Short name T252
Test name
Test status
Simulation time 143746437 ps
CPU time 1.23 seconds
Started Aug 03 04:38:50 PM PDT 24
Finished Aug 03 04:38:52 PM PDT 24
Peak memory 200276 kb
Host smart-d3eddc05-f42e-471d-9d0a-fea644203c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048542099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2048542099
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2857856101
Short name T467
Test name
Test status
Simulation time 69274238 ps
CPU time 0.76 seconds
Started Aug 03 04:39:39 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200092 kb
Host smart-9de8d162-8304-4da5-82b4-334f7cb8aada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857856101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2857856101
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.866020133
Short name T267
Test name
Test status
Simulation time 1218465633 ps
CPU time 5.34 seconds
Started Aug 03 04:39:49 PM PDT 24
Finished Aug 03 04:39:54 PM PDT 24
Peak memory 221492 kb
Host smart-d14b5add-86d4-4eb2-915e-56899b69b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866020133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.866020133
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.88126500
Short name T419
Test name
Test status
Simulation time 243998836 ps
CPU time 1.17 seconds
Started Aug 03 04:39:41 PM PDT 24
Finished Aug 03 04:39:43 PM PDT 24
Peak memory 217436 kb
Host smart-6fa51717-18a9-4dcc-bd0c-208ce2d10fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88126500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.88126500
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.316082201
Short name T24
Test name
Test status
Simulation time 173281261 ps
CPU time 0.88 seconds
Started Aug 03 04:39:41 PM PDT 24
Finished Aug 03 04:39:42 PM PDT 24
Peak memory 200092 kb
Host smart-790abe98-0076-46d5-bade-21b0784567d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316082201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.316082201
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3367476173
Short name T161
Test name
Test status
Simulation time 1623706721 ps
CPU time 7.16 seconds
Started Aug 03 04:39:41 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200500 kb
Host smart-cb08a11e-c847-4631-b396-90c0662c7afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367476173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3367476173
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.684660055
Short name T240
Test name
Test status
Simulation time 107499840 ps
CPU time 1.07 seconds
Started Aug 03 04:39:49 PM PDT 24
Finished Aug 03 04:39:50 PM PDT 24
Peak memory 200120 kb
Host smart-ea51c806-9913-4d76-8e4a-83dc1b589b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684660055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.684660055
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2770815805
Short name T505
Test name
Test status
Simulation time 258861936 ps
CPU time 1.53 seconds
Started Aug 03 04:39:40 PM PDT 24
Finished Aug 03 04:39:42 PM PDT 24
Peak memory 200384 kb
Host smart-12eb38f5-9792-4a51-974b-24e7f353ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770815805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2770815805
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.759727189
Short name T463
Test name
Test status
Simulation time 10538578781 ps
CPU time 34.88 seconds
Started Aug 03 04:39:39 PM PDT 24
Finished Aug 03 04:40:14 PM PDT 24
Peak memory 208668 kb
Host smart-b202a000-9a6f-4941-bd83-823fd1175478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759727189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.759727189
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1573304436
Short name T439
Test name
Test status
Simulation time 106291518 ps
CPU time 1.4 seconds
Started Aug 03 04:39:38 PM PDT 24
Finished Aug 03 04:39:40 PM PDT 24
Peak memory 200116 kb
Host smart-d484ab92-673c-459d-9e2c-23eef08112f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573304436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1573304436
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.566015474
Short name T163
Test name
Test status
Simulation time 108941891 ps
CPU time 0.93 seconds
Started Aug 03 04:39:40 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 200264 kb
Host smart-eccd2c7b-2511-480c-ae5e-78f7a897c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566015474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.566015474
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.29544
Short name T508
Test name
Test status
Simulation time 70699832 ps
CPU time 0.78 seconds
Started Aug 03 04:39:56 PM PDT 24
Finished Aug 03 04:39:56 PM PDT 24
Peak memory 200044 kb
Host smart-1d8ffa7a-1be3-48b1-ba15-38c8577d2400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.29544
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3226570572
Short name T387
Test name
Test status
Simulation time 1881633841 ps
CPU time 7.3 seconds
Started Aug 03 04:39:55 PM PDT 24
Finished Aug 03 04:40:03 PM PDT 24
Peak memory 217652 kb
Host smart-be66c505-b544-4adf-8adc-bfc87b809899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226570572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3226570572
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.960287411
Short name T291
Test name
Test status
Simulation time 243701834 ps
CPU time 1.17 seconds
Started Aug 03 04:39:48 PM PDT 24
Finished Aug 03 04:39:49 PM PDT 24
Peak memory 217528 kb
Host smart-a1fde008-a9e9-48f5-937b-9b1d3b9e57e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960287411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.960287411
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1032286887
Short name T192
Test name
Test status
Simulation time 173449877 ps
CPU time 0.85 seconds
Started Aug 03 04:39:48 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200080 kb
Host smart-cc57970e-fa2e-4f16-8d40-298b08b84c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032286887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1032286887
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.61961871
Short name T188
Test name
Test status
Simulation time 924744005 ps
CPU time 4.49 seconds
Started Aug 03 04:39:52 PM PDT 24
Finished Aug 03 04:39:57 PM PDT 24
Peak memory 200420 kb
Host smart-0fd75194-753d-4f51-95cb-465f3bd22195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61961871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.61961871
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2528808459
Short name T138
Test name
Test status
Simulation time 170360226 ps
CPU time 1.14 seconds
Started Aug 03 04:39:47 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200248 kb
Host smart-4db145e7-d0bf-4afa-86a3-46800439e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528808459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2528808459
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1628239043
Short name T166
Test name
Test status
Simulation time 117033374 ps
CPU time 1.21 seconds
Started Aug 03 04:39:42 PM PDT 24
Finished Aug 03 04:39:43 PM PDT 24
Peak memory 200624 kb
Host smart-f48cc4b5-fd87-4f15-827a-83a79cfb9907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628239043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1628239043
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.4159304879
Short name T244
Test name
Test status
Simulation time 168524534 ps
CPU time 1.1 seconds
Started Aug 03 04:39:52 PM PDT 24
Finished Aug 03 04:39:53 PM PDT 24
Peak memory 200072 kb
Host smart-512317fb-2ac6-41b8-8a8e-888c1f2dd51e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159304879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4159304879
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.203263903
Short name T521
Test name
Test status
Simulation time 401460404 ps
CPU time 2.55 seconds
Started Aug 03 04:39:46 PM PDT 24
Finished Aug 03 04:39:49 PM PDT 24
Peak memory 200224 kb
Host smart-e14c7650-cb68-44c8-b74c-5185ea78db5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203263903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.203263903
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.82819397
Short name T73
Test name
Test status
Simulation time 92860509 ps
CPU time 0.87 seconds
Started Aug 03 04:39:46 PM PDT 24
Finished Aug 03 04:39:47 PM PDT 24
Peak memory 200288 kb
Host smart-67c09669-4cc7-4801-a473-d5521504b723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82819397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.82819397
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3674020226
Short name T172
Test name
Test status
Simulation time 64410189 ps
CPU time 0.74 seconds
Started Aug 03 04:39:51 PM PDT 24
Finished Aug 03 04:39:52 PM PDT 24
Peak memory 200080 kb
Host smart-91f43aeb-6e4e-4a76-adbe-3cddab924a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674020226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3674020226
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.909196648
Short name T535
Test name
Test status
Simulation time 1214411645 ps
CPU time 5.75 seconds
Started Aug 03 04:39:53 PM PDT 24
Finished Aug 03 04:39:59 PM PDT 24
Peak memory 221636 kb
Host smart-61a27672-7a8d-4095-8fcb-4fb204ce5b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909196648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.909196648
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2362292336
Short name T227
Test name
Test status
Simulation time 243487902 ps
CPU time 1.11 seconds
Started Aug 03 04:39:57 PM PDT 24
Finished Aug 03 04:39:58 PM PDT 24
Peak memory 217468 kb
Host smart-55c09d4a-d0c5-4876-a948-cc885075324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362292336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2362292336
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.148785441
Short name T154
Test name
Test status
Simulation time 139654430 ps
CPU time 0.85 seconds
Started Aug 03 04:39:53 PM PDT 24
Finished Aug 03 04:39:54 PM PDT 24
Peak memory 199928 kb
Host smart-91149cc6-f0a4-48a8-9459-6697c8c4536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148785441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.148785441
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1376956772
Short name T334
Test name
Test status
Simulation time 693861555 ps
CPU time 3.54 seconds
Started Aug 03 04:39:53 PM PDT 24
Finished Aug 03 04:39:57 PM PDT 24
Peak memory 200420 kb
Host smart-68feffdd-62dc-4e22-aa78-44579d771960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376956772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1376956772
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.4068361078
Short name T500
Test name
Test status
Simulation time 102689781 ps
CPU time 1.07 seconds
Started Aug 03 04:39:56 PM PDT 24
Finished Aug 03 04:39:57 PM PDT 24
Peak memory 200284 kb
Host smart-27079eff-d609-44e0-a7c7-915a5b322f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068361078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.4068361078
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3661645791
Short name T160
Test name
Test status
Simulation time 189111170 ps
CPU time 1.35 seconds
Started Aug 03 04:39:50 PM PDT 24
Finished Aug 03 04:39:51 PM PDT 24
Peak memory 200372 kb
Host smart-7bf297df-68ba-4d0e-8dbd-65c336159bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661645791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3661645791
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4002188227
Short name T432
Test name
Test status
Simulation time 870154332 ps
CPU time 4.81 seconds
Started Aug 03 04:39:54 PM PDT 24
Finished Aug 03 04:39:59 PM PDT 24
Peak memory 200504 kb
Host smart-b4dc0ca8-8c7e-4566-bc64-88b930e1b76a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002188227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4002188227
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.214996146
Short name T255
Test name
Test status
Simulation time 369585281 ps
CPU time 2.56 seconds
Started Aug 03 04:40:02 PM PDT 24
Finished Aug 03 04:40:04 PM PDT 24
Peak memory 200164 kb
Host smart-02c3f4da-a792-401c-82c8-2730405a0160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214996146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.214996146
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1190460014
Short name T258
Test name
Test status
Simulation time 248000075 ps
CPU time 1.34 seconds
Started Aug 03 04:39:58 PM PDT 24
Finished Aug 03 04:40:00 PM PDT 24
Peak memory 200232 kb
Host smart-0101ad44-9734-4228-92a5-d88f35cb005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190460014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1190460014
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3206978818
Short name T204
Test name
Test status
Simulation time 70116936 ps
CPU time 0.84 seconds
Started Aug 03 04:39:56 PM PDT 24
Finished Aug 03 04:39:57 PM PDT 24
Peak memory 200104 kb
Host smart-136b297d-963a-406e-9fa4-1326fc457376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206978818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3206978818
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3395413269
Short name T527
Test name
Test status
Simulation time 1224323842 ps
CPU time 5.48 seconds
Started Aug 03 04:39:46 PM PDT 24
Finished Aug 03 04:39:52 PM PDT 24
Peak memory 221620 kb
Host smart-443b6bcf-5d81-48af-96e5-7ddf07663ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395413269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3395413269
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.813532564
Short name T297
Test name
Test status
Simulation time 246446619 ps
CPU time 1.07 seconds
Started Aug 03 04:39:51 PM PDT 24
Finished Aug 03 04:39:52 PM PDT 24
Peak memory 217432 kb
Host smart-4156b912-3012-4fba-85cf-ba46bdf9d04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813532564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.813532564
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1221439711
Short name T21
Test name
Test status
Simulation time 174023733 ps
CPU time 0.88 seconds
Started Aug 03 04:39:47 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200104 kb
Host smart-a7c92f05-ba65-4991-9632-29ef3070efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221439711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1221439711
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1429957105
Short name T279
Test name
Test status
Simulation time 915536713 ps
CPU time 4.65 seconds
Started Aug 03 04:39:46 PM PDT 24
Finished Aug 03 04:39:50 PM PDT 24
Peak memory 200540 kb
Host smart-df1541c6-2cd3-411c-91c3-f2e2a884264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429957105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1429957105
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2476534901
Short name T504
Test name
Test status
Simulation time 108115558 ps
CPU time 1.04 seconds
Started Aug 03 04:39:56 PM PDT 24
Finished Aug 03 04:39:57 PM PDT 24
Peak memory 200288 kb
Host smart-fa456bdd-ed27-4c4b-9e26-24ec27f48425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476534901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2476534901
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1747676911
Short name T309
Test name
Test status
Simulation time 236248679 ps
CPU time 1.42 seconds
Started Aug 03 04:39:47 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200452 kb
Host smart-eac76a7b-7e07-4548-ba71-0c1f7b0b2c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747676911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1747676911
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1574057569
Short name T480
Test name
Test status
Simulation time 385125767 ps
CPU time 1.71 seconds
Started Aug 03 04:39:45 PM PDT 24
Finished Aug 03 04:39:47 PM PDT 24
Peak memory 200376 kb
Host smart-07cb09cc-0792-4f0f-a175-2861192506a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574057569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1574057569
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1053374709
Short name T349
Test name
Test status
Simulation time 344126219 ps
CPU time 2.15 seconds
Started Aug 03 04:39:53 PM PDT 24
Finished Aug 03 04:39:56 PM PDT 24
Peak memory 200216 kb
Host smart-cb7acbc3-83dc-4430-aeae-82e36f165d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053374709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1053374709
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1135534722
Short name T207
Test name
Test status
Simulation time 207908266 ps
CPU time 1.26 seconds
Started Aug 03 04:39:46 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200260 kb
Host smart-ddd74197-bab5-426f-8e67-ae56a28b1beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135534722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1135534722
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1086720140
Short name T478
Test name
Test status
Simulation time 65568471 ps
CPU time 0.78 seconds
Started Aug 03 04:39:46 PM PDT 24
Finished Aug 03 04:39:47 PM PDT 24
Peak memory 200096 kb
Host smart-27f0a8cf-cd65-4838-987e-c53c51f502fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086720140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1086720140
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.902800354
Short name T50
Test name
Test status
Simulation time 1221549392 ps
CPU time 5.84 seconds
Started Aug 03 04:39:55 PM PDT 24
Finished Aug 03 04:40:01 PM PDT 24
Peak memory 217688 kb
Host smart-269ad733-a81b-43ad-8bb5-926596fabbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902800354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.902800354
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3819203678
Short name T2
Test name
Test status
Simulation time 243526055 ps
CPU time 1.07 seconds
Started Aug 03 04:39:52 PM PDT 24
Finished Aug 03 04:39:53 PM PDT 24
Peak memory 217404 kb
Host smart-50ca727c-b278-4ba4-a8f5-c950f3d39db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819203678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3819203678
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1053921623
Short name T176
Test name
Test status
Simulation time 95191934 ps
CPU time 0.78 seconds
Started Aug 03 04:39:52 PM PDT 24
Finished Aug 03 04:39:53 PM PDT 24
Peak memory 200064 kb
Host smart-0db1ce0d-7262-4131-ad32-caca1f6066dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053921623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1053921623
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1999106461
Short name T93
Test name
Test status
Simulation time 667245054 ps
CPU time 3.8 seconds
Started Aug 03 04:39:48 PM PDT 24
Finished Aug 03 04:39:52 PM PDT 24
Peak memory 200536 kb
Host smart-cd861d5c-5d78-40b1-8375-a3ed6dda6919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999106461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1999106461
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2146431706
Short name T30
Test name
Test status
Simulation time 106205183 ps
CPU time 1.03 seconds
Started Aug 03 04:39:53 PM PDT 24
Finished Aug 03 04:39:54 PM PDT 24
Peak memory 200124 kb
Host smart-2296cce0-3216-4bc2-92fb-7d9f21df47f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146431706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2146431706
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2920677528
Short name T29
Test name
Test status
Simulation time 253942017 ps
CPU time 1.68 seconds
Started Aug 03 04:39:55 PM PDT 24
Finished Aug 03 04:39:57 PM PDT 24
Peak memory 200384 kb
Host smart-8a90c002-81f2-455a-86d6-c877e189c782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920677528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2920677528
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.883387102
Short name T337
Test name
Test status
Simulation time 547459874 ps
CPU time 2.83 seconds
Started Aug 03 04:39:51 PM PDT 24
Finished Aug 03 04:39:54 PM PDT 24
Peak memory 200248 kb
Host smart-1a12a02f-69ba-4734-aed4-61b48005043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883387102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.883387102
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2589236715
Short name T25
Test name
Test status
Simulation time 242124433 ps
CPU time 1.35 seconds
Started Aug 03 04:39:47 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200292 kb
Host smart-72eee884-9ed7-4786-8301-e87a3f3c5d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589236715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2589236715
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3200331220
Short name T409
Test name
Test status
Simulation time 64623039 ps
CPU time 0.73 seconds
Started Aug 03 04:40:02 PM PDT 24
Finished Aug 03 04:40:02 PM PDT 24
Peak memory 199964 kb
Host smart-5fc828e5-8554-4c9f-a596-4e90d56ab603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200331220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3200331220
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1760510807
Short name T321
Test name
Test status
Simulation time 2354598778 ps
CPU time 8.15 seconds
Started Aug 03 04:40:00 PM PDT 24
Finished Aug 03 04:40:09 PM PDT 24
Peak memory 221684 kb
Host smart-61970562-89ac-45c0-9f89-0cc467e8c8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760510807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1760510807
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.147123056
Short name T338
Test name
Test status
Simulation time 245734158 ps
CPU time 1.06 seconds
Started Aug 03 04:40:00 PM PDT 24
Finished Aug 03 04:40:01 PM PDT 24
Peak memory 217448 kb
Host smart-f6c36d12-8335-41a8-8689-d0a00d51cb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147123056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.147123056
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2697627005
Short name T415
Test name
Test status
Simulation time 208897802 ps
CPU time 0.97 seconds
Started Aug 03 04:39:46 PM PDT 24
Finished Aug 03 04:39:48 PM PDT 24
Peak memory 200100 kb
Host smart-696d42c8-8587-4cbf-a089-c8d826e1ebe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697627005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2697627005
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.117557265
Short name T448
Test name
Test status
Simulation time 1486618890 ps
CPU time 6.02 seconds
Started Aug 03 04:39:58 PM PDT 24
Finished Aug 03 04:40:05 PM PDT 24
Peak memory 200508 kb
Host smart-2882db57-ce42-438b-8aa7-79612d66a98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117557265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.117557265
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.324211763
Short name T518
Test name
Test status
Simulation time 168412630 ps
CPU time 1.12 seconds
Started Aug 03 04:39:58 PM PDT 24
Finished Aug 03 04:40:00 PM PDT 24
Peak memory 200300 kb
Host smart-2331e145-19fb-4cae-bc2e-93e7c265ec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324211763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.324211763
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3312353340
Short name T357
Test name
Test status
Simulation time 106624657 ps
CPU time 1.16 seconds
Started Aug 03 04:39:55 PM PDT 24
Finished Aug 03 04:39:56 PM PDT 24
Peak memory 200304 kb
Host smart-6b274daa-8d7c-4d35-8a0e-9aa2b57b7bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312353340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3312353340
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.604434804
Short name T134
Test name
Test status
Simulation time 210539843 ps
CPU time 1.18 seconds
Started Aug 03 04:39:52 PM PDT 24
Finished Aug 03 04:39:54 PM PDT 24
Peak memory 200244 kb
Host smart-84c54ad5-2890-4d20-9d8b-584119bc6699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604434804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.604434804
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2926580386
Short name T133
Test name
Test status
Simulation time 380710367 ps
CPU time 2.57 seconds
Started Aug 03 04:40:02 PM PDT 24
Finished Aug 03 04:40:05 PM PDT 24
Peak memory 200120 kb
Host smart-582c86d7-9439-4057-8efb-080ae78d6eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926580386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2926580386
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3591025038
Short name T193
Test name
Test status
Simulation time 121944612 ps
CPU time 1.16 seconds
Started Aug 03 04:39:57 PM PDT 24
Finished Aug 03 04:39:58 PM PDT 24
Peak memory 200252 kb
Host smart-faf14659-2d0c-4e36-8cc0-ec6c71e18ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591025038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3591025038
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1336445178
Short name T343
Test name
Test status
Simulation time 78908724 ps
CPU time 0.8 seconds
Started Aug 03 04:39:55 PM PDT 24
Finished Aug 03 04:39:56 PM PDT 24
Peak memory 200088 kb
Host smart-2c51a7a0-f949-4d00-a8b4-a4ace4661841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336445178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1336445178
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3176350293
Short name T418
Test name
Test status
Simulation time 2346684149 ps
CPU time 8.46 seconds
Started Aug 03 04:40:09 PM PDT 24
Finished Aug 03 04:40:18 PM PDT 24
Peak memory 217708 kb
Host smart-41a89c4c-4d7c-4230-9243-32ed3cf3cc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176350293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3176350293
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.876427884
Short name T421
Test name
Test status
Simulation time 243815077 ps
CPU time 1.1 seconds
Started Aug 03 04:40:01 PM PDT 24
Finished Aug 03 04:40:02 PM PDT 24
Peak memory 217404 kb
Host smart-8254fb58-bea6-4499-b285-3ee7a3b17992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876427884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.876427884
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3987134822
Short name T401
Test name
Test status
Simulation time 173703738 ps
CPU time 0.9 seconds
Started Aug 03 04:40:10 PM PDT 24
Finished Aug 03 04:40:11 PM PDT 24
Peak memory 199956 kb
Host smart-9e3fc9e4-ba81-49c1-adbe-b47bf86933d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987134822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3987134822
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2013685672
Short name T170
Test name
Test status
Simulation time 783448580 ps
CPU time 4.06 seconds
Started Aug 03 04:40:01 PM PDT 24
Finished Aug 03 04:40:06 PM PDT 24
Peak memory 200468 kb
Host smart-dab38cfd-0910-47a0-a67a-fc8e4f5f1032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013685672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2013685672
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.4111902916
Short name T516
Test name
Test status
Simulation time 175481016 ps
CPU time 1.14 seconds
Started Aug 03 04:40:03 PM PDT 24
Finished Aug 03 04:40:04 PM PDT 24
Peak memory 200252 kb
Host smart-b1a3fe35-1976-4847-a92d-dda6afb664da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111902916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.4111902916
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1518722934
Short name T302
Test name
Test status
Simulation time 200707715 ps
CPU time 1.53 seconds
Started Aug 03 04:40:22 PM PDT 24
Finished Aug 03 04:40:23 PM PDT 24
Peak memory 200432 kb
Host smart-e924a48b-2a70-471e-b3c1-62ebbb21f410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518722934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1518722934
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2988623949
Short name T253
Test name
Test status
Simulation time 6659662657 ps
CPU time 20.73 seconds
Started Aug 03 04:40:03 PM PDT 24
Finished Aug 03 04:40:24 PM PDT 24
Peak memory 200608 kb
Host smart-56bf40d4-1489-4d39-b36f-f3d86e916a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988623949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2988623949
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3262592209
Short name T428
Test name
Test status
Simulation time 521819996 ps
CPU time 2.78 seconds
Started Aug 03 04:40:01 PM PDT 24
Finished Aug 03 04:40:04 PM PDT 24
Peak memory 200208 kb
Host smart-dd1077fc-285b-4e6b-994d-d9e4e5cd1372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262592209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3262592209
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.448146995
Short name T250
Test name
Test status
Simulation time 156064608 ps
CPU time 1.3 seconds
Started Aug 03 04:39:53 PM PDT 24
Finished Aug 03 04:39:55 PM PDT 24
Peak memory 200436 kb
Host smart-4eff8489-c1dd-412a-b27b-d2922b9975a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448146995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.448146995
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2525539375
Short name T231
Test name
Test status
Simulation time 72193037 ps
CPU time 0.86 seconds
Started Aug 03 04:40:06 PM PDT 24
Finished Aug 03 04:40:06 PM PDT 24
Peak memory 200080 kb
Host smart-af29c111-7238-42ee-9855-00543fb46057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525539375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2525539375
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1679124795
Short name T228
Test name
Test status
Simulation time 1893383939 ps
CPU time 6.72 seconds
Started Aug 03 04:40:20 PM PDT 24
Finished Aug 03 04:40:27 PM PDT 24
Peak memory 217400 kb
Host smart-2e4cf40c-558f-49c0-bf3d-0f27be1cc029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679124795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1679124795
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4053163862
Short name T32
Test name
Test status
Simulation time 245191895 ps
CPU time 1.08 seconds
Started Aug 03 04:39:51 PM PDT 24
Finished Aug 03 04:39:52 PM PDT 24
Peak memory 217504 kb
Host smart-04d50ae0-0ded-47ac-9fbd-8c08d73b4871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053163862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4053163862
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.852043284
Short name T284
Test name
Test status
Simulation time 152278342 ps
CPU time 0.89 seconds
Started Aug 03 04:40:03 PM PDT 24
Finished Aug 03 04:40:05 PM PDT 24
Peak memory 200064 kb
Host smart-29f2847f-0b10-457d-aeea-5b89ae72fb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852043284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.852043284
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.239415906
Short name T90
Test name
Test status
Simulation time 1031240331 ps
CPU time 5.02 seconds
Started Aug 03 04:40:08 PM PDT 24
Finished Aug 03 04:40:13 PM PDT 24
Peak memory 200464 kb
Host smart-6681d94f-2076-48f4-a254-dba490a5e816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239415906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.239415906
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3593191429
Short name T150
Test name
Test status
Simulation time 148071153 ps
CPU time 1.15 seconds
Started Aug 03 04:40:05 PM PDT 24
Finished Aug 03 04:40:06 PM PDT 24
Peak memory 200264 kb
Host smart-3780d8bd-8ae6-4551-9171-ba59bd647e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593191429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3593191429
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1040023002
Short name T376
Test name
Test status
Simulation time 113328984 ps
CPU time 1.21 seconds
Started Aug 03 04:40:09 PM PDT 24
Finished Aug 03 04:40:10 PM PDT 24
Peak memory 200428 kb
Host smart-ab51934d-a022-46d0-bcbb-99b15633a1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040023002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1040023002
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3631525182
Short name T234
Test name
Test status
Simulation time 6626667011 ps
CPU time 25.23 seconds
Started Aug 03 04:40:02 PM PDT 24
Finished Aug 03 04:40:28 PM PDT 24
Peak memory 200528 kb
Host smart-bbdb8a95-c5de-44e5-a0bc-f1d03b9edf5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631525182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3631525182
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3004564135
Short name T411
Test name
Test status
Simulation time 130772401 ps
CPU time 1.7 seconds
Started Aug 03 04:39:48 PM PDT 24
Finished Aug 03 04:39:50 PM PDT 24
Peak memory 200168 kb
Host smart-875c6922-72b6-487f-9afb-07dcaf8813c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004564135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3004564135
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.408496351
Short name T481
Test name
Test status
Simulation time 186740578 ps
CPU time 1.21 seconds
Started Aug 03 04:39:53 PM PDT 24
Finished Aug 03 04:39:55 PM PDT 24
Peak memory 200292 kb
Host smart-1345da8d-1673-4f81-be26-ceb0a3a7b17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408496351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.408496351
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3441624602
Short name T65
Test name
Test status
Simulation time 82159082 ps
CPU time 0.84 seconds
Started Aug 03 04:40:02 PM PDT 24
Finished Aug 03 04:40:03 PM PDT 24
Peak memory 200100 kb
Host smart-1799135d-dde9-4b51-993d-e0dad86eca0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441624602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3441624602
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1004305649
Short name T360
Test name
Test status
Simulation time 1898047174 ps
CPU time 7.45 seconds
Started Aug 03 04:40:06 PM PDT 24
Finished Aug 03 04:40:13 PM PDT 24
Peak memory 217376 kb
Host smart-959aa094-0e0c-4ef2-9b14-8db9033196e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004305649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1004305649
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3398346839
Short name T503
Test name
Test status
Simulation time 244606799 ps
CPU time 1.12 seconds
Started Aug 03 04:39:56 PM PDT 24
Finished Aug 03 04:39:57 PM PDT 24
Peak memory 217468 kb
Host smart-55db6156-702d-415a-9dd6-a58b766ca233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398346839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3398346839
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2515555135
Short name T354
Test name
Test status
Simulation time 155738049 ps
CPU time 0.87 seconds
Started Aug 03 04:40:07 PM PDT 24
Finished Aug 03 04:40:08 PM PDT 24
Peak memory 200088 kb
Host smart-eaeea59a-a49b-4f60-96dc-18ef5fc7a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515555135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2515555135
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1125718290
Short name T319
Test name
Test status
Simulation time 2099374607 ps
CPU time 7.8 seconds
Started Aug 03 04:39:51 PM PDT 24
Finished Aug 03 04:39:59 PM PDT 24
Peak memory 200336 kb
Host smart-55b58156-6fa7-444e-a172-47065cdb89e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125718290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1125718290
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3875692315
Short name T407
Test name
Test status
Simulation time 153788160 ps
CPU time 1.11 seconds
Started Aug 03 04:40:09 PM PDT 24
Finished Aug 03 04:40:11 PM PDT 24
Peak memory 200288 kb
Host smart-579b7be0-bd3a-4f7c-87e7-cc172c5c4961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875692315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3875692315
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1418527294
Short name T159
Test name
Test status
Simulation time 106652852 ps
CPU time 1.19 seconds
Started Aug 03 04:39:55 PM PDT 24
Finished Aug 03 04:39:57 PM PDT 24
Peak memory 200432 kb
Host smart-7badb548-26d3-42e5-82d2-a692a64ca06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418527294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1418527294
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3331920579
Short name T187
Test name
Test status
Simulation time 9651519815 ps
CPU time 37.8 seconds
Started Aug 03 04:40:07 PM PDT 24
Finished Aug 03 04:40:45 PM PDT 24
Peak memory 208680 kb
Host smart-a69c63b1-382b-4028-8e32-14b1414ee66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331920579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3331920579
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.422827683
Short name T380
Test name
Test status
Simulation time 414501104 ps
CPU time 2.5 seconds
Started Aug 03 04:40:04 PM PDT 24
Finished Aug 03 04:40:07 PM PDT 24
Peak memory 208440 kb
Host smart-1397067e-3a59-4e79-b95b-1ad2892fd209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422827683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.422827683
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2955815200
Short name T414
Test name
Test status
Simulation time 153916105 ps
CPU time 1.18 seconds
Started Aug 03 04:40:07 PM PDT 24
Finished Aug 03 04:40:08 PM PDT 24
Peak memory 200292 kb
Host smart-f8c69700-ff99-401c-a1e3-0de6b25f7552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955815200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2955815200
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3781421251
Short name T465
Test name
Test status
Simulation time 70610034 ps
CPU time 0.81 seconds
Started Aug 03 04:40:07 PM PDT 24
Finished Aug 03 04:40:08 PM PDT 24
Peak memory 200028 kb
Host smart-64e6a4f2-74e1-4ba3-8fc8-740d83562e0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781421251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3781421251
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3342664355
Short name T214
Test name
Test status
Simulation time 1221341282 ps
CPU time 5.72 seconds
Started Aug 03 04:39:57 PM PDT 24
Finished Aug 03 04:40:03 PM PDT 24
Peak memory 221344 kb
Host smart-ec2039c5-52c1-43d1-b7bf-8f190a9931c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342664355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3342664355
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1411040516
Short name T158
Test name
Test status
Simulation time 244496911 ps
CPU time 1.03 seconds
Started Aug 03 04:40:11 PM PDT 24
Finished Aug 03 04:40:12 PM PDT 24
Peak memory 217356 kb
Host smart-61c99a09-7e8a-478d-b0ca-2af2d83315bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411040516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1411040516
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2996110125
Short name T384
Test name
Test status
Simulation time 84790949 ps
CPU time 0.8 seconds
Started Aug 03 04:40:13 PM PDT 24
Finished Aug 03 04:40:14 PM PDT 24
Peak memory 200052 kb
Host smart-c470eeca-fec2-4e4e-886a-a2e70541c611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996110125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2996110125
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3284493580
Short name T436
Test name
Test status
Simulation time 1419419879 ps
CPU time 5.95 seconds
Started Aug 03 04:40:17 PM PDT 24
Finished Aug 03 04:40:23 PM PDT 24
Peak memory 200456 kb
Host smart-b9a71d49-9563-4d36-91ab-cb3b0fc994ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284493580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3284493580
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3419660374
Short name T440
Test name
Test status
Simulation time 168623890 ps
CPU time 1.18 seconds
Started Aug 03 04:40:05 PM PDT 24
Finished Aug 03 04:40:06 PM PDT 24
Peak memory 200124 kb
Host smart-28e51f20-9434-49c4-84b6-eb7f72234c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419660374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3419660374
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2986838531
Short name T31
Test name
Test status
Simulation time 202489950 ps
CPU time 1.5 seconds
Started Aug 03 04:39:54 PM PDT 24
Finished Aug 03 04:39:56 PM PDT 24
Peak memory 200408 kb
Host smart-f09e6c39-749b-4b01-8728-c3d90a845012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986838531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2986838531
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3937937637
Short name T119
Test name
Test status
Simulation time 3975978218 ps
CPU time 14.32 seconds
Started Aug 03 04:40:07 PM PDT 24
Finished Aug 03 04:40:21 PM PDT 24
Peak memory 208748 kb
Host smart-73962068-c8a9-400a-b534-e5c023be97d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937937637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3937937637
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3849638656
Short name T199
Test name
Test status
Simulation time 263155593 ps
CPU time 1.82 seconds
Started Aug 03 04:40:02 PM PDT 24
Finished Aug 03 04:40:04 PM PDT 24
Peak memory 200204 kb
Host smart-35f03642-2d1d-4ed3-8b76-7558728f27de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849638656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3849638656
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3316771704
Short name T226
Test name
Test status
Simulation time 209613729 ps
CPU time 1.43 seconds
Started Aug 03 04:40:18 PM PDT 24
Finished Aug 03 04:40:20 PM PDT 24
Peak memory 200260 kb
Host smart-20ccfb07-ad92-4c0a-8f7a-a9873390b054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316771704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3316771704
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.71420845
Short name T452
Test name
Test status
Simulation time 66272532 ps
CPU time 0.76 seconds
Started Aug 03 04:38:46 PM PDT 24
Finished Aug 03 04:38:47 PM PDT 24
Peak memory 199984 kb
Host smart-aa6d61ac-10b7-4b90-861f-dfd668c39d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71420845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.71420845
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.4136628264
Short name T232
Test name
Test status
Simulation time 243910049 ps
CPU time 1.12 seconds
Started Aug 03 04:38:50 PM PDT 24
Finished Aug 03 04:38:51 PM PDT 24
Peak memory 217504 kb
Host smart-1b8be011-109a-4262-a78f-b892ca2b9bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136628264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.4136628264
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3752046879
Short name T205
Test name
Test status
Simulation time 163690909 ps
CPU time 0.85 seconds
Started Aug 03 04:38:43 PM PDT 24
Finished Aug 03 04:38:44 PM PDT 24
Peak memory 200096 kb
Host smart-68eee961-db45-40f2-b41e-05dcad666b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752046879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3752046879
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.4075572886
Short name T97
Test name
Test status
Simulation time 2158379931 ps
CPU time 8.09 seconds
Started Aug 03 04:38:47 PM PDT 24
Finished Aug 03 04:38:55 PM PDT 24
Peak memory 200564 kb
Host smart-17f4de08-47c5-4422-9bcc-a0b620ec2824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075572886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4075572886
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4230985533
Short name T6
Test name
Test status
Simulation time 148622279 ps
CPU time 1.13 seconds
Started Aug 03 04:38:45 PM PDT 24
Finished Aug 03 04:38:46 PM PDT 24
Peak memory 200160 kb
Host smart-7861b66e-3384-4396-87d7-3dd52db8789d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230985533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4230985533
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1925948473
Short name T451
Test name
Test status
Simulation time 186414774 ps
CPU time 1.34 seconds
Started Aug 03 04:38:50 PM PDT 24
Finished Aug 03 04:38:51 PM PDT 24
Peak memory 200460 kb
Host smart-5f2850c1-f82c-464a-921f-c85f2dc514a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925948473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1925948473
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.4167635000
Short name T316
Test name
Test status
Simulation time 2802297311 ps
CPU time 12.7 seconds
Started Aug 03 04:38:58 PM PDT 24
Finished Aug 03 04:39:11 PM PDT 24
Peak memory 200616 kb
Host smart-0c63ec3a-2d86-43dd-b515-df337699a0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167635000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.4167635000
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.747058122
Short name T222
Test name
Test status
Simulation time 255065854 ps
CPU time 1.74 seconds
Started Aug 03 04:38:47 PM PDT 24
Finished Aug 03 04:38:48 PM PDT 24
Peak memory 200128 kb
Host smart-804811c5-f32e-4a8e-b061-d4d791cf5f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747058122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.747058122
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3957644074
Short name T420
Test name
Test status
Simulation time 84738048 ps
CPU time 0.85 seconds
Started Aug 03 04:39:07 PM PDT 24
Finished Aug 03 04:39:08 PM PDT 24
Peak memory 200168 kb
Host smart-ac8d945c-b2ed-49a5-9149-2b22f0d3a583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957644074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3957644074
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2848450874
Short name T290
Test name
Test status
Simulation time 65155913 ps
CPU time 0.79 seconds
Started Aug 03 04:39:10 PM PDT 24
Finished Aug 03 04:39:10 PM PDT 24
Peak memory 199992 kb
Host smart-26500690-35d3-4126-a194-2165ae382fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848450874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2848450874
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.881507066
Short name T47
Test name
Test status
Simulation time 2358626982 ps
CPU time 9.51 seconds
Started Aug 03 04:38:50 PM PDT 24
Finished Aug 03 04:39:00 PM PDT 24
Peak memory 221728 kb
Host smart-b4bf1adf-6676-4aec-9a86-0996ac48990e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881507066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.881507066
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.4204722087
Short name T458
Test name
Test status
Simulation time 244448459 ps
CPU time 1.1 seconds
Started Aug 03 04:38:59 PM PDT 24
Finished Aug 03 04:39:01 PM PDT 24
Peak memory 217468 kb
Host smart-af8203d3-c95f-4f61-83b6-30796fe0fe40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204722087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.4204722087
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2563339582
Short name T489
Test name
Test status
Simulation time 193108067 ps
CPU time 0.87 seconds
Started Aug 03 04:38:52 PM PDT 24
Finished Aug 03 04:38:53 PM PDT 24
Peak memory 200100 kb
Host smart-b05e0e98-4ce8-4524-b392-b8a0fec80a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563339582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2563339582
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2829782462
Short name T118
Test name
Test status
Simulation time 1763502500 ps
CPU time 6.41 seconds
Started Aug 03 04:38:58 PM PDT 24
Finished Aug 03 04:39:05 PM PDT 24
Peak memory 200512 kb
Host smart-cc4780ee-497b-458a-a1dc-817b6237cdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829782462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2829782462
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.959141871
Short name T537
Test name
Test status
Simulation time 112648098 ps
CPU time 0.99 seconds
Started Aug 03 04:39:00 PM PDT 24
Finished Aug 03 04:39:02 PM PDT 24
Peak memory 200300 kb
Host smart-eab1ffea-fd74-44cc-9987-c2664b65581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959141871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.959141871
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1651228661
Short name T9
Test name
Test status
Simulation time 255154296 ps
CPU time 1.46 seconds
Started Aug 03 04:38:57 PM PDT 24
Finished Aug 03 04:38:59 PM PDT 24
Peak memory 200404 kb
Host smart-b79b4f37-79a5-4ec1-adcb-0f290b03312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651228661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1651228661
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2657682343
Short name T82
Test name
Test status
Simulation time 3981654550 ps
CPU time 18.33 seconds
Started Aug 03 04:38:58 PM PDT 24
Finished Aug 03 04:39:16 PM PDT 24
Peak memory 200532 kb
Host smart-0e09347c-04fe-4048-8f98-9d3ef99c8f9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657682343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2657682343
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2406903754
Short name T271
Test name
Test status
Simulation time 125986916 ps
CPU time 1.53 seconds
Started Aug 03 04:38:58 PM PDT 24
Finished Aug 03 04:39:00 PM PDT 24
Peak memory 208452 kb
Host smart-7996640a-b744-46f9-8fc0-4964c2d13863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406903754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2406903754
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4197226725
Short name T168
Test name
Test status
Simulation time 122730824 ps
CPU time 1.07 seconds
Started Aug 03 04:38:48 PM PDT 24
Finished Aug 03 04:38:49 PM PDT 24
Peak memory 200108 kb
Host smart-ad428a7d-a6d8-4c83-919f-1fd84393a30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197226725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4197226725
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1101949739
Short name T265
Test name
Test status
Simulation time 89328503 ps
CPU time 0.84 seconds
Started Aug 03 04:38:47 PM PDT 24
Finished Aug 03 04:38:48 PM PDT 24
Peak memory 199944 kb
Host smart-bda2a6fd-d06f-4d0e-be3a-c51269b0cecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101949739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1101949739
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3002843800
Short name T278
Test name
Test status
Simulation time 2172004386 ps
CPU time 8.37 seconds
Started Aug 03 04:38:48 PM PDT 24
Finished Aug 03 04:38:57 PM PDT 24
Peak memory 217064 kb
Host smart-b8323db0-ccd4-4b8d-adfd-891911fb9ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002843800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3002843800
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1434316313
Short name T142
Test name
Test status
Simulation time 244617047 ps
CPU time 1.04 seconds
Started Aug 03 04:38:57 PM PDT 24
Finished Aug 03 04:38:59 PM PDT 24
Peak memory 217528 kb
Host smart-410e7408-155d-4217-bb3a-0d5fc0056b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434316313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1434316313
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3281522701
Short name T385
Test name
Test status
Simulation time 116326847 ps
CPU time 0.79 seconds
Started Aug 03 04:39:07 PM PDT 24
Finished Aug 03 04:39:08 PM PDT 24
Peak memory 199972 kb
Host smart-c4e2c1e4-b43f-4c7a-8ea8-e2a9c40e8b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281522701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3281522701
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2919701965
Short name T328
Test name
Test status
Simulation time 979372144 ps
CPU time 4.89 seconds
Started Aug 03 04:38:51 PM PDT 24
Finished Aug 03 04:38:56 PM PDT 24
Peak memory 200480 kb
Host smart-6da227d4-d32b-4ec7-8fe4-695f6aad5dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919701965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2919701965
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2890825568
Short name T300
Test name
Test status
Simulation time 135454566 ps
CPU time 1.14 seconds
Started Aug 03 04:39:06 PM PDT 24
Finished Aug 03 04:39:07 PM PDT 24
Peak memory 200216 kb
Host smart-a5b4baef-fad0-48d1-88bf-5f4a64485fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890825568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2890825568
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.871275373
Short name T263
Test name
Test status
Simulation time 249736761 ps
CPU time 1.6 seconds
Started Aug 03 04:38:59 PM PDT 24
Finished Aug 03 04:39:01 PM PDT 24
Peak memory 200428 kb
Host smart-399c22b3-baef-4840-ae0f-5a2466643700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871275373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.871275373
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1364498103
Short name T268
Test name
Test status
Simulation time 4976312352 ps
CPU time 17.96 seconds
Started Aug 03 04:38:47 PM PDT 24
Finished Aug 03 04:39:05 PM PDT 24
Peak memory 200512 kb
Host smart-130ed8b1-986f-4dbc-941e-2ba8ac9a9247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364498103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1364498103
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3677607898
Short name T355
Test name
Test status
Simulation time 122660805 ps
CPU time 1.43 seconds
Started Aug 03 04:38:48 PM PDT 24
Finished Aug 03 04:38:49 PM PDT 24
Peak memory 200216 kb
Host smart-32261f59-31ef-4926-8d75-cd33303211c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677607898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3677607898
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3452933171
Short name T139
Test name
Test status
Simulation time 126277101 ps
CPU time 0.93 seconds
Started Aug 03 04:38:58 PM PDT 24
Finished Aug 03 04:38:59 PM PDT 24
Peak memory 200292 kb
Host smart-0363f247-e6ab-431d-97fd-d73712448a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452933171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3452933171
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.84164533
Short name T208
Test name
Test status
Simulation time 71165726 ps
CPU time 0.76 seconds
Started Aug 03 04:38:57 PM PDT 24
Finished Aug 03 04:38:58 PM PDT 24
Peak memory 200088 kb
Host smart-59c77894-ebdc-43a5-8fbb-a07bfb42855c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84164533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.84164533
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.693167296
Short name T48
Test name
Test status
Simulation time 1886419455 ps
CPU time 6.92 seconds
Started Aug 03 04:38:48 PM PDT 24
Finished Aug 03 04:38:55 PM PDT 24
Peak memory 221684 kb
Host smart-ce09e7f2-a5bb-4b9b-98f7-052dae5e0cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693167296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.693167296
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.765715082
Short name T127
Test name
Test status
Simulation time 244277880 ps
CPU time 1.15 seconds
Started Aug 03 04:38:49 PM PDT 24
Finished Aug 03 04:38:50 PM PDT 24
Peak memory 217308 kb
Host smart-cb49a6bf-1e60-417b-b121-28d44084f5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765715082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.765715082
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3867698175
Short name T493
Test name
Test status
Simulation time 181690960 ps
CPU time 0.9 seconds
Started Aug 03 04:38:51 PM PDT 24
Finished Aug 03 04:38:52 PM PDT 24
Peak memory 199944 kb
Host smart-d7290445-3bdd-48b5-bc72-a5f0ea6f66a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867698175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3867698175
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3816568669
Short name T190
Test name
Test status
Simulation time 1333464589 ps
CPU time 6 seconds
Started Aug 03 04:38:58 PM PDT 24
Finished Aug 03 04:39:04 PM PDT 24
Peak memory 200468 kb
Host smart-bd40694e-4181-4b95-ab89-e2b41aad79e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816568669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3816568669
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1346443389
Short name T141
Test name
Test status
Simulation time 114916068 ps
CPU time 1.01 seconds
Started Aug 03 04:39:02 PM PDT 24
Finished Aug 03 04:39:03 PM PDT 24
Peak memory 200104 kb
Host smart-c6ad8da2-3fa7-4799-abda-37bcb2de2b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346443389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1346443389
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1465459409
Short name T131
Test name
Test status
Simulation time 200114278 ps
CPU time 1.4 seconds
Started Aug 03 04:38:59 PM PDT 24
Finished Aug 03 04:39:01 PM PDT 24
Peak memory 200476 kb
Host smart-6e159508-09db-4273-8ab5-dd5a898654ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465459409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1465459409
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3367433141
Short name T514
Test name
Test status
Simulation time 8688719439 ps
CPU time 36.41 seconds
Started Aug 03 04:39:18 PM PDT 24
Finished Aug 03 04:39:54 PM PDT 24
Peak memory 208756 kb
Host smart-66795b10-92ea-4450-bffb-7c83dfd5d105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367433141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3367433141
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2845044312
Short name T378
Test name
Test status
Simulation time 354157465 ps
CPU time 2.25 seconds
Started Aug 03 04:38:59 PM PDT 24
Finished Aug 03 04:39:02 PM PDT 24
Peak memory 200240 kb
Host smart-4e1a1604-056f-4a27-a04c-f04ba01b28fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845044312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2845044312
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2880512558
Short name T76
Test name
Test status
Simulation time 118399834 ps
CPU time 0.99 seconds
Started Aug 03 04:38:58 PM PDT 24
Finished Aug 03 04:38:59 PM PDT 24
Peak memory 200264 kb
Host smart-40a79698-214a-4585-b66a-4f6fb9364e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880512558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2880512558
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1167183349
Short name T171
Test name
Test status
Simulation time 71614072 ps
CPU time 0.76 seconds
Started Aug 03 04:39:16 PM PDT 24
Finished Aug 03 04:39:17 PM PDT 24
Peak memory 200116 kb
Host smart-42e065eb-64f3-4261-b7dd-1b3219eb0b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167183349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1167183349
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2404619581
Short name T46
Test name
Test status
Simulation time 1225497688 ps
CPU time 6.07 seconds
Started Aug 03 04:38:55 PM PDT 24
Finished Aug 03 04:39:01 PM PDT 24
Peak memory 217680 kb
Host smart-edff7877-0087-43c2-acbf-75f7d8589340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404619581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2404619581
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2936853518
Short name T394
Test name
Test status
Simulation time 243567716 ps
CPU time 1.16 seconds
Started Aug 03 04:38:57 PM PDT 24
Finished Aug 03 04:38:59 PM PDT 24
Peak memory 217460 kb
Host smart-a6285fbf-2344-427d-91a8-7b09955be6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936853518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2936853518
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1682783435
Short name T424
Test name
Test status
Simulation time 242189890 ps
CPU time 0.9 seconds
Started Aug 03 04:38:58 PM PDT 24
Finished Aug 03 04:38:59 PM PDT 24
Peak memory 200064 kb
Host smart-2418d562-36ca-4ab9-9041-94f375cd77a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682783435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1682783435
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.936975630
Short name T288
Test name
Test status
Simulation time 1371035013 ps
CPU time 5.56 seconds
Started Aug 03 04:38:56 PM PDT 24
Finished Aug 03 04:39:02 PM PDT 24
Peak memory 200448 kb
Host smart-077d86a7-b6b6-4630-bfb9-7b5ce69aec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936975630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.936975630
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.295128878
Short name T312
Test name
Test status
Simulation time 99280786 ps
CPU time 1.04 seconds
Started Aug 03 04:39:08 PM PDT 24
Finished Aug 03 04:39:09 PM PDT 24
Peak memory 200168 kb
Host smart-94172015-a4b2-4d67-9496-abf978830cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295128878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.295128878
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.113486861
Short name T289
Test name
Test status
Simulation time 105450829 ps
CPU time 1.2 seconds
Started Aug 03 04:39:13 PM PDT 24
Finished Aug 03 04:39:15 PM PDT 24
Peak memory 200444 kb
Host smart-9525ba13-4968-495e-a9ef-8fcd03baade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113486861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.113486861
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.14355122
Short name T99
Test name
Test status
Simulation time 4808370444 ps
CPU time 21.56 seconds
Started Aug 03 04:39:15 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 208636 kb
Host smart-231f3ad3-4260-456d-8c17-e8d50252694b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14355122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.14355122
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.965900205
Short name T386
Test name
Test status
Simulation time 407780777 ps
CPU time 2.24 seconds
Started Aug 03 04:39:00 PM PDT 24
Finished Aug 03 04:39:02 PM PDT 24
Peak memory 208440 kb
Host smart-766b8028-2604-4922-87d4-3dc10857a333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965900205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.965900205
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1607003559
Short name T412
Test name
Test status
Simulation time 131740462 ps
CPU time 1.25 seconds
Started Aug 03 04:38:54 PM PDT 24
Finished Aug 03 04:38:55 PM PDT 24
Peak memory 200204 kb
Host smart-ab562da0-5ea9-4cd2-b3b4-e6ebdcffcce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607003559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1607003559
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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