Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8011

1

T1

19

T2

7

T8

36

auto[1]

10924

1

T1

82

T2

1

T7

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5825	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6388	1			T1	27		T2	1		T3	1
reset_info_cp[2]	2994	1			T1	14		T7	1		T8	13
reset_info_cp[4]	3828	1			T1	18		T7	1		T8	17
reset_info_cp[8]	95	1			T8	1		T10	1		T53	2
reset_info_cp[16]	106	1			T1	1		T10	2		T23	1
reset_info_cp[32]	108	1			T1	1		T8	1		T10	2
reset_info_cp[64]	105	1			T1	1		T10	4		T11	1
reset_info_cp[128]	106	1			T1	1		T10	1		T11	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3116	1			T1	19		T8	7		T10	35
reset_info_cp[1]	auto[1]	2652	1			T1	7		T7	1		T8	8
reset_info_cp[2]	auto[0]	930	1			T8	8		T10	18		T23	13
reset_info_cp[2]	auto[1]	2064	1			T1	14		T7	1		T8	5
reset_info_cp[4]	auto[0]	1363	1			T8	9		T10	26		T23	13
reset_info_cp[4]	auto[1]	2465	1			T1	18		T7	1		T8	8
reset_info_cp[8]	auto[0]	37	1			T8	1		T53	1		T87	3
reset_info_cp[8]	auto[1]	58	1			T10	1		T53	1		T54	1
reset_info_cp[16]	auto[0]	37	1			T10	1		T23	1		T52	3
reset_info_cp[16]	auto[1]	69	1			T1	1		T10	1		T50	1
reset_info_cp[32]	auto[0]	43	1			T8	1		T53	1		T54	2
reset_info_cp[32]	auto[1]	65	1			T1	1		T10	2		T24	2
reset_info_cp[64]	auto[0]	41	1			T11	1		T23	1		T52	1
reset_info_cp[64]	auto[1]	64	1			T1	1		T10	4		T24	1
reset_info_cp[128]	auto[0]	40	1			T23	1		T52	1		T53	1
reset_info_cp[128]	auto[1]	66	1			T1	1		T10	1		T11	1